STM32F048C6U6

STM32F048C6 STM32F048G6 STM32F048T6 ARM®-based 32-bit MCU, 32 KB Flash, crystal-less USB FS 2.0, 9 timers, ADC and comm. interfaces, 1.8 V Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz UFQFPN48 7x7 mm UFQFPN28 4x4 mm • Memories – 32 Kbytes of Flash memory – 6 Kbytes of SRAM with HW parity • CRC calculation unit • Power management – Digital and I/Os supply: VDD = 1.8 V ± 8% – Analog supply: VDDA = from VDD to 3.6 V – Selected I/Os: VDDIO2 = 1.65 V to 3.6 V – Low power modes: Sleep, Stop – VBAT supply for RTC and backup registers • Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x6 PLL option – Internal 40 kHz RC oscillator – Internal 48 MHz oscillator with automatic trimming based on ext. synchronization • Up to 37 fast I/Os – All mappable on external interrupt vectors – Up to 24 I/Os with 5 V tolerant capability and 8 with independent supply VDDIO2 • 5-channel DMA controller WLCSP36 2.6x2.7 mm • Nine timers – One 16-bit advanced-control timer for six channel PWM output – One 32-bit and four 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding – Independent and system watchdog timers – SysTick timer • Communication interfaces – One I2C interface supporting Fast Mode Plus (1 Mbit/s) with extra current sink, SMBus/PMBus and wakeup – Two USARTs supporting master synchronous SPI and modem control, one with ISO7816 interface, LIN, IrDA, auto baud rate detection and wakeup feature – Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames, one with I2S interface multiplexed – USB 2.0 full-speed interface, able to run from internal 48 MHz oscillator and with BCD and LPM support • One 12-bit, 1.0 µs ADC (10 channels) – Conversion range: 0 to 3.6 V – Separate analog supply: 2.4 V to 3.6 V • HDMI CEC, wakeup on header reception • Up to 13 capacitive sensing channels for touchkey, linear and rotary touch sensors • All packages ECOPACK®2 • Serial wire debug (SWD) • 96-bit unique ID • Calendar RTC with alarm and periodic wakeup from Stop January 2017 This is information on a product in full production. DocID026007 Rev 6 1/98 www.st.com Contents STM32F048C6 STM32F048G6 STM32F048T6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 2/98 3.5.1 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12.2 General-purpose timers (TIM2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 20 3.12.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 23 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Contents 3.16 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 24 3.17 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.19 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 42 6.3.3 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.14 NRST and NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID026007 Rev 6 3/98 4 Contents 7 STM32F048C6 STM32F048G6 STM32F048T6 6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.17 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 93 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. STM32F048x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitive sensing GPIOs available on STM32F048x6 devices . . . . . . . . . . . . . . . . . . . . 18 No. of capacitive sensing channels available on STM32F048x6 devices. . . . . . . . . . . . . . 19 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F048x6 I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F048x6 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F048x6 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32F048x6 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 32 Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 33 Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 33 STM32F048x6 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical and maximum current consumption from VDD supply at VDD = 1.8 V . . . . . . . . . . 45 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 46 Typical and maximum consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 47 Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 DocID026007 Rev 6 5/98 6 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. 6/98 STM32F048C6 STM32F048G6 STM32F048T6 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 WLCSP36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WLCSP36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32F048x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 58 HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 WLCSP36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Recommended pad footprint for WLCSP36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 WLCSP36 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DocID026007 Rev 6 7/98 7 Introduction 1 STM32F048C6 STM32F048G6 STM32F048T6 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F048x6 microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website. 8/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 2 Description Description The STM32F048x6 microcontrollers incorporate the high-performance ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (32 Kbytes of Flash memory and 6 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (one I2C, two SPIs/one I2S, one HDMI CEC and two USARTs), one USB Full-speed device (crystal-less), one 12-bit ADC, four 16-bit timers, one 32-bit timer and an advanced-control PWM timer. The STM32F048x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, at a 1.8 V ± 8% power supply. A comprehensive set of power-saving modes allows the design of low-power applications. The STM32F048x6 microcontrollers include devices in three different packages ranging from 36 pins to 48 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F048x6 microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs. DocID026007 Rev 6 9/98 25 Description STM32F048C6 STM32F048G6 STM32F048T6 Table 1. STM32F048x device features and peripheral counts Peripheral STM32F048G6 STM32F048T6 Flash memory (Kbyte) 32 SRAM (Kbyte) 6 Timers Advanced control 1 (16-bit) General purpose 4 (16-bit) 1 (32-bit) SPI [I2S](1) Comm. interfaces 1 [1] 2 [1] 2 I C 1 USART 2 USB 1 CEC 1 12-bit ADC (number of channels) 1 (10 ext. + 3 int.) GPIOs 23 29 37 Capacitive sensing channels 10 13 13 Max. CPU frequency 48 MHz Operating voltage VDD = 1.8 V ± 8%, VDDA = from VDD to 3.6 V Operating temperature Ambient operating temperature: -40°C to 85 °C / -40°C to 105°C Junction temperature: -40°C to 105°C / -40°C to 125°C Packages UFQFPN28 WLCSP36 1. The SPI1 interface can be used either in SPI mode or in I2S audio mode. 10/98 STM32F048C6 DocID026007 Rev 6 UFQFPN48 STM32F048C6 STM32F048G6 STM32F048T6 Description Figure 1. Block diagram 6HULDO:LUH 'HEXJ 2EO )ODVK PHPRU\ LQWHUIDFH 6:&/. 6:',2 DV$) 19,& 65$0 FRQWUROOHU %XVPDWUL[ &257(;0&38 I0$; 0+] )ODVK*3/ .% ELW #9'' 65$0 .% #9''$ +6, +6, 3//&/. /6, *3'0$ FKDQQHOV 9'' 9“ 966 32:(5 9'' +6, 325 5HVHW ,QW 6833/ VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the device. See note (2) below Table 54: ADC accuracy. 6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 19. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID026007 Rev 6 Value Unit –65 to +150 °C 150 °C 41/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 6.3 Operating conditions 6.3.1 General operating conditions Table 20. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 48 fPCLK Internal APB clock frequency - 0 48 VDD Standard operating voltage - 1.65 1.95 V Must not be supplied if VDD is not present 1.65 3.6 V VDD 3.6 2.4 3.6 1.65 3.6 TC and RST I/O –0.3 VDDIOx+0.3 TTa and POR I/O –0.3 VDDA+0.3(1) –0.3 5.2(1) UFQFPN48 - 606 WLCSP36 - 313 UFQFPN28 - 170 –40 85 –40 105 VDDIO2 VDDA VBAT VIN I/O supply voltage Analog operating voltage (ADC not used) Must have a potential equal to or higher than VDD Analog operating voltage (ADC used) Backup operating voltage - I/O input voltage FT and FTf I/O PD Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(2) Maximum power dissipation Ambient temperature for the suffix 7 version Maximum power dissipation –40 105 Low power dissipation(3) –40 125 Suffix 6 version –40 105 Suffix 7 version –40 125 TA TJ V Ambient temperature for the suffix 6 version Junction temperature range Low power dissipation (3) MHz V V mW °C °C °C 1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.4: Thermal characteristics. 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.4: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 21 are derived from tests performed under the ambient temperature condition summarized in Table 20. 42/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 21. Operating conditions at power-up / power-down Symbol tVDD tVDDA 6.3.3 Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate Min Max 0 ∞ 20 ∞ 0 ∞ 20 ∞ Unit µs/V Embedded reference voltage The parameters given in Table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 22. Embedded internal reference voltage Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +105 °C Min Typ Max Unit 1.2 1.23 1.25 V tSTART ADC_IN17 buffer startup time - - - 10(1) µs tS_vrefint ADC sampling time when reading the internal reference voltage - 4(1) - - µs ∆VREFINT Internal reference voltage spread over the temperature range VDDA = 3 V - - 10(1) mV - - 100(1) - 100(1) ppm/°C - 1.5 2.5 TCoeff Temperature coefficient TVREFINT_RDY Internal reference voltage (2) temporization 4.5 ms 1. Guaranteed by design, not tested in production. 2. Guaranteed by design, not tested in production. This parameter is the latency between the time when pin NPOR is set to 1 by the application and the time when the VREFINTRDYF status bit is set to 1 by the hardware. 6.3.4 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. DocID026007 Rev 6 43/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • • The Flash memory access time is adjusted to the fHCLK frequency: – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 23 to Table 27 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. 44/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Parameter Symbol Table 23. Typical and maximum current consumption from VDD supply at VDD = 1.8 V All peripherals enabled(1) Conditions Supply current in Run mode, code executing from Flash memory External clock (HSE bypass) Internal clock (HSI) Supply current in Run mode, code executing from RAM HSI48 IDD External clock (HSE bypass) Internal clock (HSI) HSI48 Supply current in Sleep mode Max @ TA(2) fHCLK Max @ TA(2) External clock (HSE bypass) Internal clock (HSI) Unit Typ Typ HSI48 All peripherals disabled 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 48 MHz 19.0 20.4 20.9 21.3 11.7 12.2 12.8 12.9 48 MHz 18.5 20.0 20.5 20.9 11.5 12.1 12.6 12.8 32 MHz 12.5 13.2 13.6 14.0 7.8 8.4 8.7 8.9 24 MHz 10.1 10.4 10.7 11.0 6.2 6.6 6.9 7.1 8 MHz 3.5 4.0 4.1 4.2 2.3 2.5 2.6 2.6 1 MHz 0.7 0.8 0.9 1.0 0.5 0.7 0.7 0.8 48 MHz 18.7 20.2 20.6 21.0 11.6 12.1 12.7 12.8 32 MHz 12.7 13.4 13.8 14.2 8.0 8.6 8.8 9.1 24 MHz 10.2 10.6 11.0 11.1 6.3 6.8 7.0 7.1 8 MHz 3.7 4.2 4.3 4.5 2.3 2.5 2.6 2.7 48 MHz 18.2 19.6 20.0 20.4 10.9 11.4 12.0 12.2 48 MHz 17.8 19.2 19.7 20.0 10.7 11.4 11.9 12.1 32 MHz 12.1 12.6 13.0 13.4 7.2 7.6 8.0 8.3 24 MHz 9.6 9.9 10.1 10.4 5.6 5.9 6.3 6.5 8 MHz 3.0 3.4 3.6 3.7 1.6 2.0 2.0 2.0 1 MHz 0.4 0.5 0.6 0.7 0.2 0.3 0.3 0.4 48 MHz 18.0 19.4 19.9 20.2 10.8 11.4 12.0 12.1 32 MHz 12.3 12.9 13.2 13.6 7.4 7.8 8.2 8.4 24 MHz 9.8 10.1 10.4 10.6 5.7 5.9 6.3 6.5 8 MHz 3.2 3.6 3.7 3.9 1.7 2.1 2.1 2.2 48 MHz 10.9 12.2 13.0 13.3 2.7 2.8 2.9 3.1 48 MHz 10.7 12.1 12.8 13.1 2.6 2.7 2.8 3.0 32 MHz 7.8 8.3 8.6 9.0 1.7 1.9 2.0 2.3 24 MHz 6.2 6.8 7.2 7.4 1.4 1.4 1.6 1.6 8 MHz 2.0 2.5 2.6 2.7 0.5 0.5 0.6 0.6 1 MHz 0.3 0.3 0.4 0.5 0.1 0.2 0.2 0.2 48 MHz 10.8 12.1 12.9 13.2 2.6 2.7 2.8 3.0 32 MHz 7.9 8.4 8.7 9.2 1.9 2.0 2.1 2.3 24 MHz 6.3 6.9 7.3 7.5 1.4 1.4 1.6 1.7 8 MHz 2.0 2.6 2.7 2.8 0.5 0.6 0.6 0.8 mA mA 1. USB is kept disabled as this IP functions only with a 48 MHz clock. 2. Data based on characterization results, not tested in production unless otherwise specified. DocID026007 Rev 6 45/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 24. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter Conditions (1) Max @ TA(2) fHCLK Max @ TA(2) HSE bypass, PLL on Supply current in Run or Sleep mode, code executing from Flash memory or RAM HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off Unit Typ Typ HSI48 IDDA VDDA = 3.6 V 25 °C 85 °C 105 °C 25 °C 85 °C 105 °C 48 MHz 308 325 330 340 316 332 338 347 48 MHz 147 166 176 180 160 179 191 195 32 MHz 101 118 123 125 109 126 132 135 24 MHz 79 94 98 100 86 100 104 106 8 MHz 1 3 3 3 2 3 3 4 1 MHz 1 2 2 2 2 2 3 3 48 MHz 219 239 250 254 240 260 272 276 32 MHz 172 191 198 201 190 207 215 218 24 MHz 150 167 172 174 165 181 187 189 8 MHz 71 79 81 82 81 89 91 92 µA 1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from the frequency. 2. Data based on characterization results, not tested in production unless otherwise specified. Table 25. Typical and maximum consumption in Stop mode 46/98 1.0 1.0 1.0 1.0 DocID026007 Rev 6 1.1 1.1 1.2 TA = 105 °C VDDA = 3.6 V VDDA = 3.3 V VDDA = 3.0 V VDDA = 2.7 V VDDA = 2.4 V 0.4 All oscillators OFF TA = 85 °C IDDA Supply current in Stop mode Max TA = 25 °C IDD Conditions VDDA = 2.0 V Symbol Parameter VDDA = 1.8 V Typ. @ VDD = 1.8 V 2.3 14.9 35.6 1.5 2.6 3.4 Unit µA STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 26. Typical and maximum current consumption from the VBAT supply Max(1) Typ @ VBAT 2.4 V 2.7 V 3.3 V 3.6 V RTC domain IDD_VBAT supply current Conditions 1.8 V Parameter 1.65 V Symbol TA = 25 °C LSE & RTC ON; “Xtal mode”: lower driving capability; LSEDRV[1:0] = '00' 0.5 0.5 0.6 0.7 0.9 1.1 1.2 LSE & RTC ON; “Xtal mode” higher driving capability; LSEDRV[1:0] = '11' 0.8 TA = TA = 85 °C 105 °C 1.5 Unit 2.0 µA 0.9 1.1 1.2 1.4 1.5 1.6 2.0 2.6 1. Data based on characterization results, not tested in production. Typical current consumption The MCU is placed under the following conditions: • VDD = VDDA = 1.8 V • All I/O pins are in analog input configuration • The Flash memory access time is adjusted to fHCLK frequency: – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz • When the peripherals are enabled, fPCLK = fHCLK • PLL is used for frequencies greater than 8 MHz • AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and 500 kHz respectively DocID026007 Rev 6 47/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 27. Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal Typical consumption in Run mode Symbol Parameter Typical consumption in Sleep mode fHCLK Unit Peripherals Peripherals Peripherals Peripherals enabled disabled enabled disabled IDD IDDA Current consumption from VDD supply Current consumption from VDDA supply 48 MHz 19.8 12.0 11.5 3.1 36 MHz 15.0 9.3 8.7 2.6 32 MHz 13.5 8.4 7.8 2.4 24 MHz 10.2 6.5 6.0 1.8 16 MHz 7.1 4.6 4.2 1.4 8 MHz 3.9 2.6 2.3 0.8 4 MHz 2.3 1.5 1.3 0.5 2 MHz 1.4 1.0 0.9 0.5 1 MHz 1.0 0.8 0.6 0.4 500 kHz 0.8 0.6 0.5 0.4 48 MHz 146 36 MHz 115 32 MHz 105 24 MHz 83 16 MHz 61 8 MHz 1 4 MHz 1 2 MHz 1 1 MHz 1 500 kHz 1 mA μA I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 47: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt 48/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 29: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID026007 Rev 6 49/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 28. Switching output I/O current consumption Symbol Parameter Conditions(1) VDDIOx = 1.8 V CEXT = 0 pF C = CINT + CEXT + CS VDDIOx = 1.8 V CEXT = 10 pF C = CINT + CEXT + CS ISW I/O current consumption VDDIOx = 1.8 V CEXT = 22 pF C = CINT + CEXT + CS VDDIOx = 1.8 V CEXT = 33 pF C = CINT + CEXT + CS VDDIOx = 1.8 V CEXT = 47 pF C = CINT + CEXT + CS 1. CS = 5 pF (estimated value). 50/98 DocID026007 Rev 6 I/O toggling frequency (fSW) Typ 2 MHz 0.09 4 MHz 0.17 8 MHz 0.34 18 MHz 0.79 36 MHz 1.50 48 MHz 2.06 2 MHz 0.13 4 MHz 0.26 8 MHz 0.50 18 MHz 1.18 36 MHz 2.27 48 MHz 3.03 2 MHz 0.18 4 MHz 0.36 8 MHz 0.69 18 MHz 1.60 36 MHz 3.27 2 MHz 0.23 4 MHz 0.45 8 MHz 0.87 18 MHz 2.0 36 MHz 3.7 2 MHz 0.29 4 MHz 0.55 8 MHz 1.09 18 MHz 2.43 Unit mA STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 29. The MCU is placed under the following conditions: • All I/O pins are in analog mode • All peripherals are disabled unless otherwise mentioned • The given value is calculated by measuring the current consumption • – with all peripherals clocked off – with only one peripheral clocked on Ambient operating temperature and supply voltage conditions summarized in Table 17: Voltage characteristics Table 29. Peripheral current consumption Peripheral AHB Typical consumption at 25 °C BusMatrix(1) 2.2 CRC 1.9 DMA 5.1 Flash memory interface 15.0 GPIOA 8.2 GPIOB 7.7 GPIOC 2.1 GPIOF 1.8 SRAM 1.1 TSC 4.9 All AHB peripherals 49.8 DocID026007 Rev 6 Unit µA/MHz 51/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 29. Peripheral current consumption (continued) Peripheral APB-Bridge APB Typical consumption at 25 °C (2) Unit 2.9 ADC(3) 3.9 CEC 1.5 CRS 1.0 DBG (MCU Debug Support) 0.2 I2C1 3.6 PWR 1.4 SPI1 8.5 SPI2 6.1 SYSCFG 1.8 TIM1 15.1 TIM2 16.8 TIM3 11.7 TIM14 5.5 TIM16 7.0 TIM17 6.9 USART1 17.8 USART2 5.6 USB 4.9 WWDG 1.4 All APB peripherals µA/MHz 123.8 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus. 3. The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the tables of characteristics in the subsequent sections. 52/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 6.3.5 Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 30 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture. The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. During wakeup from Stop mode, SYSCLK takes the default setting: HSI 8 MHz. The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode. All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 30. Low-power mode wakeup timings Typ @ VDDA Symbol Parameter tWUSTOP Wakeup from Stop mode tWUSLEEP Wakeup from Sleep mode 6.3.6 = 1.8 V = 3.3 V 3.5 2.8 Max Unit 5.3 µs - µs 4 SYSCLK cycles External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 11: High-speed external clock source AC timing diagram. Table 31. High-speed external user clock characteristics Symbol Parameter(1) Min Typ Max Unit - 8 32 MHz fHSE_ext User external clock source frequency VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx tw(HSEH) tw(HSEL) OSC_IN high or low time 15 - - tr(HSE) tf(HSE) OSC_IN rise or fall time - - 20 V ns 1. Guaranteed by design, not tested in production. DocID026007 Rev 6 53/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Figure 11. High-speed external clock source AC timing diagram WZ+6(+ 9+6(+  9+6(/  WU+6( WI+6( W WZ+6(/ 7+6( 069 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 12. Table 32. Low-speed external user clock characteristics Parameter(1) Symbol fLSE_ext User external clock source frequency Min Typ Max Unit - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDDIOx 450 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) tr(LSE) tf(LSE) V ns OSC32_IN rise or fall time - - 50 1. Guaranteed by design, not tested in production. Figure 12. Low-speed external clock source AC timing diagram WZ/6(+ 9/6(+  9/6(/  WU/6( WI/6( WZ/6(/ W 7/6( 069 54/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 33. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 33. HSE oscillator characteristics Symbol fOSC_IN RF Conditions(1) Min(2) Typ Max(2) Unit Oscillator frequency - 4 8 32 MHz Feedback resistor - - 200 - kΩ - - 8.5 VDD = 1.8 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.4 - VDD = 1.8 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.5 - VDD = 1.8 V, Rm = 30 Ω, CL = 5 pF@32 MHz - 0.8 - VDD = 1.8 V, Rm = 30 Ω, CL = 10 pF@32 MHz - 1 - VDD = 1.8 V, Rm = 30 Ω, CL = 20 pF@32 MHz - 1.5 - Startup 10 - - mA/V VDD is stabilized - 2 - ms Parameter (3) During startup IDD gm tSU(HSE)(4) HSE current consumption Oscillator transconductance Startup time mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design, not tested in production. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. DocID026007 Rev 6 55/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Figure 13. Typical application with an 8 MHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7  I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 069 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 34. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol LSE current consumption IDD Oscillator transconductance gm tSU(LSE) Parameter (3) Startup time Conditions(1) Min(2) Typ Max(2) Unit low drive capability - 0.5 0.9 medium-low drive capability - - 1 medium-high drive capability - - 1.3 high drive capability - - 1.6 low drive capability 5 - - medium-low drive capability 8 - - medium-high drive capability 15 - - high drive capability 25 - - VDDIOx is stabilized - 2 - µA µA/V 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. Guaranteed by design, not tested in production. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 56/98 DocID026007 Rev 6 s STM32F048C6 STM32F048G6 STM32F048T6 Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 14. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 I/6( 'ULYH SURJUDPPDEOH DPSOLILHU N+] UHVRQDWRU 26&B287 &/ 069 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.7 Internal clock source characteristics The parameters given in Table 35 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. The provided curves are characterization results, not tested in production. DocID026007 Rev 6 57/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 High-speed internal (HSI) RC oscillator Table 35. HSI oscillator characteristics(1) Symbol Parameter fHSI Conditions Min Typ - - Frequency TRIM HSI user trimming step DuCy(HSI) Duty cycle Accuracy of the HSI oscillator ACCHSI - - - (2) 45 IDDA(HSI) Unit 8 - MHz - (2) - % 1 (2) 55 % TA = -40 to 105°C (3) -2.8 - 3.8 TA = -10 to 85°C -1.9(3) - 2.3(3) TA = 0 to 85°C -1.9(3) - 2(3) TA = 0 to 70°C -1.3(3) - 2(3) TA = 0 to 55°C -1(3) - 2(3) -1 - 1 - 2(2) µs 80 100(2) µA TA = 25°C(4) tsu(HSI) Max HSI oscillator startup time - 1(2) HSI oscillator power consumption - - (3) % 1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. 4. Factory calibrated, parts not soldered. Figure 15. HSI oscillator accuracy characterization results for soldered parts  ."9 .*/             5

 "

    069 58/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 36. HSI14 oscillator characteristics(1) Symbol fHSI14 TRIM Parameter Conditions Min Typ - - 14 Frequency HSI14 user-trimming step DuCy(HSI14) Duty cycle - - - (2) 45 Accuracy of the HSI14 oscillator (factory calibrated) TA = –10 to 85 °C TA = 25 °C tsu(HSI14) IDDA(HSI14) - MHz (2) - % 1 55 (2) % (3) % (3) - 5.1 –3.2(3) - 3.1(3) % –2.5 - 2.3 (3) % –1 (3) TA = 0 to 70 °C Unit - TA = –40 to 105 °C –4.2 ACCHSI14 Max HSI14 oscillator startup time - 1(2) HSI14 oscillator power consumption - - - 1 % - 2(2) µs 100 150(2) µA 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 16. HSI14 oscillator accuracy characterization results  0$; 0,1     7>ƒ&@ $                   069 DocID026007 Rev 6 59/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 High-speed internal 48 MHz (HSI48) RC oscillator Table 37. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM Parameter Conditions Min Typ Max Unit - - 48 - MHz Frequency HSI48 user-trimming step (2) - DuCy(HSI48) Duty cycle 0.09 - 45 TA = –40 to 105 °C ACCHSI48 TA = –10 to 85 °C Accuracy of the HSI48 oscillator (factory calibrated) T = 0 to 70 °C A IDDA(HSI48) 0.14 - % (2) % (3) 0.2 55 (3) - 4.7 % -4.1(3) - 3.7(3) % - (3) % -4.9 (3) -3.8 TA = 25 °C tsu(HSI48) (2) (2) -2.8 3.4 - 2.9 % µs µA HSI48 oscillator startup time - - - 6(2) HSI48 oscillator power consumption - - 312 350(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 17. HSI48 oscillator accuracy characterization results  0$; 0,1               7>ƒ&@ $         069 60/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Low-speed internal (LSI) RC oscillator Table 38. LSI oscillator characteristics(1) Symbol Parameter fLSI tsu(LSI) Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.8 PLL characteristics The parameters given in Table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 39. PLL characteristics Value Symbol fPLL_IN fPLL_OUT tLOCK JitterPLL Parameter Unit Min Typ Max 1(2) 8.0 24(2) MHz PLL input clock duty cycle (2) 40 - 60(2) % PLL multiplier output clock 16(2) - 48 MHz PLL lock time - - 200(2) µs Cycle-to-cycle jitter - - 300(2) ps PLL input clock(1) 1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design, not tested in production. 6.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 40. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs Page (1 KB) erase time TA = - 40 to +105 °C 20 - 40 ms tME Mass erase time TA = - 40 to +105 °C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design, not tested in production. DocID026007 Rev 6 61/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 41. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Min(1) Unit 10 kcycle at TA = 85 °C 30 at TA = 105 °C 10 10 kcycle(2) at TA = 55 °C 20 1 kcycle (2) Year 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 1.8 V, LQFP48, TA = +25 °C, Voltage limits to be applied on any I/O pin fHCLK = 48 MHz, to induce a functional disturbance conforming to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 1.8 V, LQFP48, TA = +25°C, fHCLK = 48 MHz, conforming to IEC 61000-4-4 4B Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. 62/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 43. EMI characteristics Symbol Parameter SEMI 6.3.11 Conditions Monitored frequency band 0.1 to 30 MHz VDD = 1.8 V, TA = 25 °C, 30 to 130 MHz LQFP48 package Peak level compliant with 130 MHz to 1 GHz IEC 61967-2 EMI Level Max vs. [fHSE/fHCLK] Unit 8/48 MHz -9 12 dBµV 17 3 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. DocID026007 Rev 6 63/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 All 2 2000 V VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming (charge device model) to ANSI/ESD STM5.3.1 All C4 500 V 1. Data based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 45. Electrical sensitivities Symbol LU 6.3.12 Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 46. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. 64/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 46. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection IINJ 6.3.13 Injected current on PA12 pin -0 +5 Injected current on PA9, PB3, PB13, PF11 pins with induced leakage current on adjacent pins less than 50 µA -5 NA Injected current on PB0, PB1 and all other FT and FTf pins, and on NPOR pin -5 NA Injected current on all other TC, TTa and RST pins -5 +5 mA I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 20: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 47. I/O static characteristics Symbol VIL Parameter Low level input voltage Conditions Min Typ Max TC and TTa I/O - - 0.3 VDDIOx+0.07(1) FT and FTf I/O - - 0.475 VDDIOx–0.2(1) All I/Os - - 0.3 VDDIOx - - - - TC and TTa I/O VIH High level input voltage FT and FTf I/O 0.5 VDDIOx All I/Os Vhys Ilkg RPU Schmitt trigger hysteresis Input leakage current(2) Weak pull-up equivalent resistor (3) 0.445 VDDIOx+0.398(1) +0.2(1) 0.7 VDDIOx - - 200 - FT and FTf I/O - 100(1) - TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx - - ± 0.1 TTa in digital mode VDDIOx ≤ VIN ≤ VDDA - - 1 TTa in analog mode VSS ≤ VIN ≤ VDDA - - ± 0.2 FT and FTf I/O VDDIOx ≤ VIN ≤ 5 V - - 10 25 40 55 DocID026007 Rev 6 V V (1) TC and TTa I/O VIN = VSS Unit mV µA kΩ 65/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 47. I/O static characteristics (continued) Symbol Parameter RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions VIN = - VDDIOx - Min Typ Max Unit 25 40 55 kΩ - 5 - pF 1. Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 46: I/O current injection susceptibility. 3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 for standard I/Os, and in Figure 19 for 5 V-tolerant I/Os. The following curves are design simulation results, not tested in production. 66/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Figure 18. TC and TTa I/O input characteristics   7(67('5$1*(  77/VWDQGDUGUHTXLUHPHQW HQW LUHP HTX DUGU QG 6VWD 9,19 9    &02   [ '',2 9 ,+PLQ  81'(),1(',13875$1*( ',2[ 9' 9,+PLQ    9'',2[ 9,/PD[  XLUHPHQW WDQGDUGUHT V 6 2 0 &   9'',2[ 9,/PD[  77/VWDQGDUGUHTXLUHPHQW 7(67('5$1*(             9'',2[9 06Y9 Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics   7(67('5$1*(  77/VWDQGDUGUHTXLUHPHQW HQW LUHP  9   9 ,+PLQ '',2 9 9,+PLQ    [ 81'(),1(',13875$1*(   '',2[ 9 9,/PD[  QG 6VWD &02 9,19 HTX DUGU   '',2[ 77/VWDQGDUGUHTXLUHPHQW XLUHPHQW QGDUGUHT WD &026V [ 9'',2 9,/PD[  7(67('5$1*(             9'',2[9 06Y9 DocID026007 Rev 6 67/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 17: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 17: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified). Table 48. Output voltage characteristics(1) Symbol Parameter VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(4) Output low level voltage for an I/O pin VOH(4) Output high level voltage for an I/O pin VOLFm+(3) Output low level voltage for an FTf I/O pin in Fm+ mode Conditions Min Max CMOS port(2) |IIO| = 8 mA VDDIOx ≥ 2.7 V - 0.4 VDDIOx–0.4 - - 0.4 2.4 - - 1.3 VDDIOx–1.3 - - 0.4 VDDIOx–0.4 - - 0.4 V VDDIOx–0.4 - V |IIO| = 20 mA VDDIOx ≥ 2.7 V - 0.4 V |IIO| = 10 mA - 0.4 V TTL port(2) |IIO| = 8 mA VDDIOx ≥ 2.7 V |IIO| = 20 mA VDDIOx ≥ 2.7 V |IIO| = 6 mA VDDIOx ≥ 2 V |IIO| = 4 mA Unit V V V V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Data based on characterization results. Not tested in production. 4. Data based on characterization results. Not tested in production. 68/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 20 and Table 49, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 49. I/O AC characteristics(1)(2) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions Min Max Unit - 2 MHz - 125 - 125 - 1 - 125 - 125 - 10 - 25 - 25 - 4 - 62.5 - 62.5 CL = 30 pF, VDDIOx ≥ 2.7 V - 50 CL = 50 pF, VDDIOx ≥ 2.7 V - 30 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 20 CL = 50 pF, VDDIOx < 2 V - 10 CL = 30 pF, VDDIOx ≥ 2.7 V - 5 CL = 50 pF, VDDIOx ≥ 2.7 V - 8 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12 CL = 50 pF, VDDIOx < 2 V - 25 CL = 30 pF, VDDIOx ≥ 2.7 V - 5 CL = 50 pF, VDDIOx ≥ 2.7 V - 8 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12 CL = 50 pF, VDDIOx < 2 V - 25 fmax(IO)out Maximum frequency(3) x0 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx < 2 V fmax(IO)out Maximum frequency(3) 01 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx < 2 V fmax(IO)out Maximum frequency(3) 11 tf(IO)out tr(IO)out Output fall time Output rise time DocID026007 Rev 6 ns MHz ns MHz ns MHz ns MHz ns 69/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 49. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) Fm+ configuration (4) - tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time CL = 50 pF, VDDIOx < 2 V tr(IO)out Output rise time tEXTIpw Pulse width of external signals detected by the EXTI controller - Min Max Unit - 2 MHz - 12 - 34 - 0.5 - 16 - 44 10 - ns MHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design, not tested in production. 3. The maximum frequency is defined in Figure 20. 4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration. Figure 20. I/O AC characteristics definition       W I,2RXW W U,2RXW 7  7DQGLIWKHGXW\F\FOHLV 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWW” U I  ZKHQORDGHGE\&VHHWKHWDEOH,2$&FKDUDFWHULVWLFVGHILQLWLRQ 069 6.3.14 NRST and NPOR pin characteristics NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. 70/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 50. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1) VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV V RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ VF(NRST) NRST input filtered pulse - - - 100(1) ns - 700(1) - - ns VNF(NRST) NRST input not filtered pulse 1. Data based on design simulation only. Not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). Figure 21. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9'' 1567 538 ,QWHUQDOUHVHW )LOWHU —) 069 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. NPOR pin characteristics The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor to the VDDA, RPU. Unless otherwise specified, the parameters given in Table 51 below are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. DocID026007 Rev 6 71/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 51. NPOR pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NPOR) NPOR Input low level voltage - - - 0.475 VDDA - 0.2(1) VIH(NPOR) NPOR Input high level voltage - 0.5 VDDA + 0.2(1) - - Vhys(NPOR) NPOR Schmitt trigger voltage hysteresis - - 100(1) - mV VIN = VSS 25 40 55 kΩ RPU Weak pull-up equivalent resistor(2) Unit V 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 6.3.15 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the conditions summarized in Table 20: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 52. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON - 2.4 - 3.6 V VDDA = 3.3 V - 0.9 - mA - 0.6 - 14 MHz IDDA (ADC) Current consumption of the ADC(1) fADC ADC clock frequency fS(2) Sampling rate 12-bit resolution 0.043 - 1 MHz External trigger frequency fADC = 14 MHz, 12-bit resolution - - 823 kHz 12-bit resolution - - 17 1/fADC fTRIG(2) VAIN Conversion voltage range - 0 - VDDA V RAIN(2) External input impedance See Equation 1 and Table 53 for details - - 50 kΩ RADC(2) Sampling switch resistance - - - 1 kΩ CADC(2) Internal sample and hold capacitor - - - 8 pF tCAL(2)(3) Calibration time 72/98 fADC = 14 MHz 5.9 µs - 83 1/fADC DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 52. ADC characteristics (continued) Symbol Parameter WLATENCY(2)(4) tlatr (2) ADC_DR register ready latency Conditions Min Typ Max Unit ADC clock = HSI14 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle fADC = fPCLK/2 = 14 MHz 0.196 µs fADC = fPCLK/2 5.5 1/fPCLK 0.219 µs 10.5 1/fPCLK Trigger conversion latency fADC = fPCLK/4 = 12 MHz fADC = fPCLK/4 JitterADC tS(2) fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs fADC = fHSI14 - 1 - 1/fHSI14 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC ADC jitter on trigger conversion Sampling time tSTAB(2) Stabilization time tCONV(2) Total conversion time (including sampling time) fADC = 14 MHz, 12-bit resolution 12-bit resolution 14 1 1/fADC - 18 14 to 252 (tS for sampling +12.5 for successive approximation) µs 1/fADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA on IDD should be taken into account. 2. Guaranteed by design, not tested in production. 3. Specified value includes only ADC timing. It does not include the latency of the register access. 4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time. Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 53. RAIN max for fADC = 14 MHz Ts (cycles) tS (µs) RAIN max (kΩ)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 DocID026007 Rev 6 73/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 53. RAIN max for fADC = 14 MHz (continued) Ts (cycles) tS (µs) RAIN max (kΩ)(1) 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 54. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ±0.8 ±1.5 ET Total unadjusted error ±3.3 ±4 EO Offset error ±1.9 ±2.8 EG Gain error ±2.8 ±3 ED Differential linearity error ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 ET Total unadjusted error ±3.3 ±4 ±1.9 ±2.8 ±2.8 ±3 ±0.7 ±1.3 ±1.2 ±1.7 EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 3 V to 3.6 V TA = 25 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.7 V to 3.6 V TA = - 40 to 105 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.4 V to 3.6 V TA = 25 °C Unit LSB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. 74/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Figure 22. ADC accuracy characteristics 966$ (*   ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH 7KHLGHDOWUDQVIHUFXUYH (QGSRLQWFRUUHODWLRQOLQH   (7      (2 (/   ('  /6%,'($/              (7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW LGHDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH 9''$ 069 Figure 23. Typical connection diagram using the ADC 9''$ 6DPSOHDQGKROG$'& FRQYHUWHU 97 5$,1  9$,1 5$'& $,1[ 97 &SDUDVLWLF  ,/ “ —$ ELW FRQYHUWHU &$'& 069 1. Refer to Table 52: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 9: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DocID026007 Rev 6 75/98 83 Electrical characteristics 6.3.16 STM32F048C6 STM32F048G6 STM32F048T6 Temperature sensor characteristics Table 55. TS characteristics Symbol Parameter TL(1) Avg_Slope Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) V30 Average slope (2) Voltage at 30 °C (± 5 °C) tSTART(1) ADC_IN16 buffer startup time - - 10 µs tS_temp(1) ADC sampling time when reading the temperature 4 - - µs 1. Guaranteed by design, not tested in production. 2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 2: Temperature sensor calibration values. 6.3.17 VBAT monitoring characteristics Table 56. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 2 x 50 - kΩ Q Ratio on VBAT measurement - 2 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 4 - - µs Er(1) tS_vbat(1) 1. Guaranteed by design, not tested in production. 6.3.18 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 57. TIMx characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT Timer external clock frequency on CH1 to CH4 16-bit timer maximum period tMAX_COUNT 32-bit counter maximum period 76/98 Conditions Min Typ Max Unit - - 1 - tTIMxCLK fTIMxCLK = 48 MHz - 20.8 - ns - - fTIMxCLK/2 - MHz fTIMxCLK = 48 MHz - 24 - MHz - - 216 - tTIMxCLK fTIMxCLK = 48 MHz - 1365 - µs - - 232 - tTIMxCLK fTIMxCLK = 48 MHz - 89.48 - s DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 58. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 59. WWDG min/max timeout value at 48 MHz (PCLK) 6.3.19 Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0853 5.4613 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 Unit ms Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.13: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: DocID026007 Rev 6 77/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Table 60. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 20: General operating conditions. Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 61. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Max Master mode - 18 Slave mode - 18 - 6 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 15 pF tsu(NSS) NSS setup time Slave mode 4Tpclk - th(NSS) NSS hold time Slave mode 2Tpclk + 10 - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 Tpclk/2 -2 Tpclk/2 + 1 Master mode 4 - Slave mode 5 - Master mode 4 - Slave mode 5 - Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk Data output disable time Slave mode 0 18 tv(SO) Data output valid time Slave mode (after enable edge) - 22.5 tv(MO) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 11.5 - Master mode (after enable edge) 2 - Slave mode 25 75 tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO)(2) tdis(SO) (3) th(SO) th(MO) DuCy(SCK) Data input setup time Data input hold time Data output hold time SPI slave input clock duty cycle Unit MHz ns ns % 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 78/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Figure 24. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. 6&.LQSXW WVX166 WK166 WZ6&.+ WU6&. &3+$  &32/  &3+$  &32/  WD62 WZ6&./ 0,62RXWSXW WY62 WK62 )LUVWELW287 WI6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, WVX6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 Figure 25. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 &3+$  &32/  &3+$  &32/  0,62RXWSXW WY62 )LUVWELW287 WVX6, 026,LQSXW WK62 1H[WELWV287 WU6&. WGLV62 /DVWELW287 WK6, )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DocID026007 Rev 6 79/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Figure 26. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WZ6&.+ WZ6&./ WVX0, 0,62 ,13 87 WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 % , 7287 06%287 WY02 /6%287 WK02 DLF 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 62. I2S characteristics(1) Symbol fCK 1/tc(CK) Parameter I2S clock frequency Conditions Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode tr(CK) I2S clock rise time tf(CK) I2S clock fall time Capacitive load CL = 15 pF Min Max 1.597 1.601 0 6.5 - 10 - 12 306 - 312 - tw(CKH) I2S tw(CKL) 2 I S clock low time Master fPCLK= 16 MHz, audio frequency = 48 kHz tv(WS) WS valid time Master mode 2 - th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 7 - th(WS) WS hold time Slave mode 0 - Slave mode 25 75 DuCy(SCK) 80/98 I2S clock high time slave input clock duty cycle DocID026007 Rev 6 Unit MHz ns % STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics Table 62. I2S characteristics(1) (continued) Symbol tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Parameter Conditions Data input setup time (2) (2) tv(SD_MT)(2) tv(SD_ST)(2) th(SD_MT) th(SD_ST) Data input hold time Data output valid time Data output hold time Min Max Master receiver 6 - Slave receiver 2 - Master receiver 4 - Slave receiver 0.5 - Master transmitter - 4 Slave transmitter - 31 Master transmitter 0 - Slave transmitter 13 - Unit ns 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns. Figure 27. I2S slave timing diagram (Philips protocol) &.,QSXW WF&. &32/  &32/  WZ&.+ WK:6 WZ&./ :6LQSXW WY6'B67 WVX:6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW WVX6'B65 6'UHFHLYH /6%UHFHLYH WK6'B67 %LWQWUDQVPLW WK6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID026007 Rev 6 81/98 83 Electrical characteristics STM32F048C6 STM32F048G6 STM32F048T6 Figure 28. I2S master timing diagram (Philips protocol)   WI&. WU&. &.RXWSXW WF&. &32/  WZ&.+ &32/  WY:6 WK:6 WZ&./ :6RXWSXW WY6'B07 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW /6%UHFHLYH /6%WUDQVPLW WK6'B05 WVX6'B05 6'UHFHLYH %LWQWUDQVPLW WK6'B07 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Data based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 82/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Electrical characteristics USB characteristics The STM32F048x6 USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 63. USB electrical characteristics Symbol Conditions Min. Typ Max. Unit USB transceiver operating voltage - 3.0(1) - 3.6 V tSTARTUP(2) USB transceiver startup time - - - 1.0 µs RPUI Embedded USB_DP pull-up value during idle - 1.1 1.26 1.5 RPUR Embedded USB_DP pull-up value during reception - ZDRV(2) Output driver impedance(3) VDDIO2 Parameter kΩ Driving high and low 2.0 2.26 2.6 28 40 44 Ω 1. The STM32F048x6 USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range. 2. Guaranteed by design, not tested in production. 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. DocID026007 Rev 6 83/98 83 Package information 7 STM32F048C6 STM32F048G6 STM32F048T6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 29. UFQFPN48 package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < '  /  &[ƒ SLQFRUQHU ( 5W\S 'HWDLO=  =  $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 84/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Package information Table 64. UFQFPN48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 30. Recommended footprint for UFQFPN48 package                      $%B)3B9 1. Dimensions are expressed in millimeters. DocID026007 Rev 6 85/98 94 Package information STM32F048C6 STM32F048G6 STM32F048T6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 31. UFQFPN48 package marking example WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ (6) &8 ĂƚĞĐŽĚĞ < ^ƚĂŶĚĂƌĚ^důŽŐŽ :: ZĞǀŝƐŝŽŶĐŽĚĞ WŝŶϭŝĚĞŶƚŝĨŝĞƌ 5 D^ϯϳϳϯϱsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 86/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 7.2 Package information WLCSP36 package information WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 32. WLCSP36 package outline H EEE = $EDOOORFDWLRQ ) H * $ 'HWDLO$ H H )  $ $ $  %XPSVLGH 6LGHYLHZ ;  < $ %XPS $ RULHQWDWLRQ UHIHUHQFH HHH =  DDD = $ ‘EEDOOV FFF = ; < GGG = :DIHUEDFNVLGH E = 6HDWLQJSODQH 'HWDLO$ URWDWHGƒ Ϭ>ͺDͺsϮ 1. Drawing is not to scale. Table 65. WLCSP36 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.570 2.605 2.640 0.1012 0.1026 0.1039 E 2.668 2.703 2.738 0.1050 0.1064 0.1078 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - b DocID026007 Rev 6 87/98 94 Package information STM32F048C6 STM32F048G6 STM32F048T6 Table 65. WLCSP36 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.3025 - - 0.0119 - G - 0.3515 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 33. Recommended pad footprint for WLCSP36 package 'SDG 'VP 069 Table 66. WLCSP36 recommended PCB design rules Dimension 88/98 Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 34. WLCSP36 package marking example Žƚ WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ )7 ZĞǀŝƐŝŽŶĐŽĚĞ 5 ĂƚĞĐŽĚĞ < :: D^ϯϳϳϯϰsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID026007 Rev 6 89/98 94 Package information 7.3 STM32F048C6 STM32F048G6 STM32F048T6 UFQFPN28 package information UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 35. UFQFPN28 package outline 'HWDLO< ' ( ' ' ( 'HWDLO= $%B0(B9 1. Drawing is not to scale. Table 67. UFQFPN28 package mechanical data(1) millimeters inches Symbol 90/98 Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - 0.000 0.050 - 0.0000 0.0020 D 3.900 4.000 4.100 0.1535 0.1575 0.1614 D1 2.900 3.000 3.100 0.1142 0.1181 0.1220 E 3.900 4.000 4.100 0.1535 0.1575 0.1614 E1 2.900 3.000 3.100 0.1142 0.1181 0.1220 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 L1 0.250 0.350 0.450 0.0098 0.0138 0.0177 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Package information 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 36. Recommended footprint for UFQFPN28 package               $%B)3B9 1. Dimensions are expressed in millimeters. DocID026007 Rev 6 91/98 94 Package information STM32F048C6 STM32F048G6 STM32F048T6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 37. UFQFPN28 package marking example WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ )* ZĞǀŝƐŝŽŶĐŽĚĞ ĂƚĞĐŽĚĞ Žƚ < :: 5 D^ϯϳϳϯϯsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 92/98 DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 7.4 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 20: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 68. Package thermal characteristics Symbol ΘJA 7.4.1 Parameter Value Thermal resistance junction-ambient UFQFPN48 - 7 mm x 7 mm 33 Thermal resistance junction-ambient WLCSP36 - 2.6 × 2.7 mm 64 Thermal resistance junction-ambient UFQFPN28 - 4 mm x 4 mm 118 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F048x6 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. DocID026007 Rev 6 93/98 94 Ordering information 8 STM32F048C6 STM32F048G6 STM32F048T6 Ordering information For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 69. Ordering information scheme STM32 F Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 048 = STM32F048xx Pin count G = 28 pins T = 36 pins C = 48 pins User code memory size 6 = 32 Kbyte Package U = UFQFPN Y = WLCSP Temperature range 6 = –40 to 85 °C 7 = –40 to 105 °C Options xxx = code ID of programmed parts (includes packing type) TR = tape and reel packing blank = tray packing 94/98 DocID026007 Rev 6 048 C 6 T 6 xxx STM32F048C6 STM32F048G6 STM32F048T6 9 Revision history Revision history Table 70. Document revision history Date Revision 27-May-2014 1 Initial release. 28-May-2014 2 Updated the document status to Preliminary data. No other change in the content. 3 Removed LQFP48 package. Updated: – Table: Typical and maximum current consumption from VDD supply at VDD = 1.8 V, – Table: Typical and maximum current consumption from the VDDA supply, – Table: Typical and maximum consumption in Stop mode, – Table: HSI oscillator characteristics, – Figure: HSI oscillator accuracy characterization results for soldered parts, – Table: ESD absolute maximum ratings, – the document status to Datasheet - production data. Added: – Figure: UFQFPN48 marking example (package top view), – Figure: WLCSP36 marking example (package top view), – Figure: UFQFPN28 marking example (package top view). 4 Cover page – 9 timers instead of 8 in the title – number of I/Os and capacitive sensing channels corrected – Fast Mode Plus current sink corrected from 20 mA to “extra” Updates in Section 2: Description: – updated Figure 1: Block diagram and Figure 2: Clock tree – Table 1: STM32F048x device features and peripheral counts - I/O and capacitive channel numbers corrected Updates in Section 3: Functional overview: – addition of PB2 to Table 4: Capacitive sensing GPIOs available on STM32F048x6 devices – addition of the number of complementary outputs for the advanced control timer and for TIM16, TIM17 general purpose in Table 6: Timer feature comparison – removal of USART2 from Figure 3.5.3: Low-power modes – Table 8: STM32F048x6 I2C implementation - adding “extra” Updates in Section 4: Pinouts and pin descriptions – Figure 4: WLCSP36 package updated – Table 12: STM32F048x6 pin definitions - removal of CIMP1_OUT and USART4_CTS; swap of F2 and D2 for WLCSP36 – Table 14: Alternate functions selected through GPIOB_AFR registers for port B - change of I2C2_SDA and I2C2_SCL to I2C1_SDA and I2C1_SCL 09-Apr-2015 06-Nov-2015 Changes DocID026007 Rev 6 95/98 97 Revision history STM32F048C6 STM32F048G6 STM32F048T6 Table 70. Document revision history (continued) Date 06-Nov-2015 05-Dec-2015 96/98 Revision Changes Updates in Section 5: Memory mapping – Table 16: STM32F048x6 peripheral register boundary addresses change of “SYSCFG + COMP” to “SYSCFG” Updates in Section 6: Electrical characteristics: – VDDIOx replacibg VDD in Figure 18: TC and TTa I/O input characteristics and Figure 19: Five volt tolerant (FT and FTf) I/O input characteristics – footnote for VIN max value in Table 17: Voltage characteristics, – footnote for max VIN in Table 20: General operating conditions, – addition of tSTART parameter in Table 22: Embedded internal reference voltage, removal of -40°C to 85°C condition and the associated footnote – Table 26: Typical and maximum current consumption from the VBAT supply: removing “code executing from Flash or RAM” – removal of the min value for tSTART parameter in Table 55: TS characteristics – the typical value for R parameter in Table 56: VBAT monitoring characteristics 4 – removal of ResTM parameter line from Table 57: TIMx characteristics (continued) and putting all values in new Typ column, substitution of tCOUNTER with tMAX_COUNT, values defined as powers of two – VESD(CDM) class in Table 44: ESD absolute maximum ratings – reorganization of Table 62: I2S characteristics and filling max value of tv(SD_ST) – adding definition of levels in Figure 28: I2S master timing diagram (Philips protocol) Updates in Section 7: Package information: – heading and display of columns in Table 65: WLCSP36 package mechanical data., – Figure 31: UFQFPN48 package marking example (top view) – Figure 34: WLCSP36 package marking example (top view) – Figure 36: Recommended footprint for UFQFPN28 package distance between corner pads added – Figure 37: UFQFPN28 package marking example (top view) – removing “die 445” from Table 68: Package thermal characteristics Updates in Section 8: Part numbering: – adding tray packing to options 5 Section 4: Pinouts and pin descriptions: – Package pinout figures updated (look and feel) – Figure 4: WLCSP36 package- now presented in top view – Table 12: STM32F048x6 pin definitions - note 3 added; Section 6: Electrical characteristics: – Table 47: I/O static characteristics - removed note – Section 6.3.15: 12-bit ADC characteristics - changed introductory sentence DocID026007 Rev 6 STM32F048C6 STM32F048G6 STM32F048T6 Revision history Table 70. Document revision history (continued) Date 10-Jan-2017 Revision 6 Changes Section 6: Electrical characteristics: – Table 34: LSE oscillator characteristics (fLSE = 32.768 kHz) information on configuring different drive capabilities removed. See the corresponding reference manual. – Table 22: Embedded internal reference voltage - VREFINT values – Figure 24: SPI timing diagram - slave mode and CPHA = 0 and Figure 25: SPI timing diagram - slave mode and CPHA = 1 enhanced and corrected Section 8: Ordering information: – The name of the section changed from the previous “Part numbering” DocID026007 Rev 6 97/98 97 STM32F048C6 STM32F048G6 STM32F048T6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 98/98 DocID026007 Rev 6