STM32F058R8H6TR

厂商：
STMICROELECTRONICS(意法半导体)
封装：
UFBGA64
描述：

数据手册：

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数据手册
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STM32F058R8H6TR 数据手册

STM32F058C8 STM32F058R8 STM32F058T8 Advanced ARM®-based 32-bit MCU, 64 KB Flash, 11 timers, ADC, DAC and comm. interfaces, 1.8 V Datasheet - production data Features )%*$ • Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz • Memories – 64 Kbytes of Flash memory – 8 Kbytes of SRAM with HW parity checking • CRC calculation unit • Power management – Digital and I/O supply: VDD = 1.8 V ± 8% – Analog supply: VDDA = from VDD to 3.6 V – Low power modes: Sleep, Stop – VBAT supply for RTC and backup registers • Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x6 PLL option – Internal 40 kHz RC oscillator • Up to 54 fast I/Os – All mappable on external interrupt vectors – Up to 35 I/Os with 5 V tolerant capability • 5-channel DMA controller • One 12-bit, 1.0 µs ADC (up to 16 channels) – Conversion range: 0 to 3.6 V – Separate analog supply from 2.4 up to 3.6 • One 12-bit DAC channel • Two fast low-power analog comparators with programmable input and output • Up to 17 capacitive sensing channels supporting touchkey, linear and rotary touch sensors LQFP64 10x10 mm UFQFPN48 7x7 mm UFBGA64 5x5 mm WLCSP36 2.6x2.7 mm – Two 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control – One 16-bit timer with 1 IC/OC – Independent and system watchdog timers – SysTick timer: 24-bit downcounter – One 16-bit basic timer to drive the DAC • Calendar RTC with alarm and periodic wakeup from Stop • Communication interfaces – Up to two I2C interfaces, one supporting Fast Mode Plus (1 Mbit/s) with extra current sink, SMBus/PMBus and wakeup from Stop mode – Up to two USARTs supporting master synchronous SPI and modem control, one with ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature – Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frame, one with I2S interface multiplexed • HDMI CEC interface, wakeup on header reception • Serial wire debug (SWD) • 96-bit unique ID • All packages ECOPACK®2 • Up to 11 timers – One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop – One 32-bit and one 16-bit timer, with up to 4 IC/OC, usable for IR control decoding – One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop January 2017 This is information on a product in full production. DocID023402 Rev 4 1/104 www.st.com Contents STM32F058C8 STM32F058R8 STM32F058T8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 2/104 3.5.1 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 21 3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Contents 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 24 3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 25 3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43 6.3.3 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.14 NRST and NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DocID023402 Rev 4 3/104 4 Contents 7 STM32F058C8 STM32F058R8 STM32F058T8 6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.16 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.17 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.19 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.21 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 97 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. STM32F058C8/R8/T8 family device features and peripheral counts . . . . . . . . . . . . . . . . . 10 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitive sensing GPIOs available on STM32F058C8/R8/T8 devices . . . . . . . . . . . . . . 19 No. of capacitive sensing channels available on STM32F058C8/R8/T8 devices . . . . . . . . 19 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F058C8/R8/T8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F058C8/R8/T8 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F058C8/R8/T8 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 33 Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 34 STM32F058C8/R8/T8 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical and maximum current consumption from VDD at 1.8 V . . . . . . . . . . . . . . . . . . . . . 45 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 46 Typical and maximum consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 47 Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DocID023402 Rev 4 5/104 6 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. 6/104 STM32F058C8 STM32F058R8 STM32F058T8 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 WLCSP36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WLCSP36 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F058x8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 58 HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 WLCSP36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Recommended pad footprint for WLCSP36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 WLCSP36 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 PD max versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DocID023402 Rev 4 7/104 7 Introduction 1 STM32F058C8 STM32F058R8 STM32F058T8 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F058C8/R8/T8 microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website. 8/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 2 Description Description The STM32F058C8/R8/T8 microcontrollers incorporate the high-performance ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (64 Kbytes of Flash memory and 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs, up to two SPIs, one I2S, one HDMI CEC and up to two USARTs), one 12-bit ADC, one 12-bit DAC, six 16-bit timers, one 32-bit timer and an advanced-control PWM timer. The STM32F058C8/R8/T8 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges at a 1.8 V ± 8% power supply. A comprehensive set of power-saving modes allows the design of low-power applications. The STM32F058C8/R8/T8 microcontrollers include devices in four different packages ranging from 36 pins to 64 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F058C8/R8/T8 microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs. DocID023402 Rev 4 9/104 25 Description STM32F058C8 STM32F058R8 STM32F058T8 Table 1. STM32F058C8/R8/T8 family device features and peripheral counts Peripheral STM32F058T8 STM32F058C8 Flash memory (Kbyte) 64 SRAM (Kbyte) 8 Timers Advanced control 1 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 1 (16-bit) SPI [I2S](1) Comm. interfaces I 1 [1] 2 [1] 2C 2 USART 2 CEC 1 12-bit ADC (number of channels) 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.) 12-bit DAC (number of channels) 1 (1) Analog comparator 2 GPIOs 28 38 54 Capacitive sensing channels 13 16 17 Max. CPU frequency 48 MHz Operating voltage VDD = 1.8 V ± 8%, VDDA = from VDD to 3.6 V Operating temperature Ambient operating temperature: -40°C to 85°C / -40°C to 105°C Junction temperature: -40°C to 105°C / -40°C to 125°C Packages WLCSP36 UFQFPN48 1. The SPI1 interface can be used either in SPI mode or in I2S audio mode. 10/104 STM32F058R8 DocID023402 Rev 4 LQFP64 UFBGA64 STM32F058C8 STM32F058R8 STM32F058T8 Description Figure 1. Block diagram 6HULDO:LUH 'HEXJ 65$0 FRQWUROOHU 19,& %XVPDWUL[ &257(;0&38 I0$; 0+] )ODVK*3/ .% ELW #9'' 65$0 .% #9''$ +6, +6, 3//&/. /6, *3'0$ FKDQQHOV 9'' 9 966 32:(5 9'' 2EO )ODVK PHPRU\ LQWHUIDFH 6:&/. 6:',2 DV$) 325 5HVHW ,QW 6833/@ 026,6' 0,620&. 6&.&. 166:6DV$) 026,0,62 6&.166 DV$) 57& 7RXFK 6HQVLQJ &RQWUROOHU $+% FKDQQHOV FRPSOFKDQQHOV %5.(75LQSXWDV$) 7,0(5ELW FK(75DV$) 7,0(5 FK(75DV$) 7,0(5 FKDQQHODV$) 7,0(5 FKDQQHOV FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) $3% (;7,7:.83 63,,6 :LQGRZ:'* ,5B287DV$) 63, '%*0&8 *3FRPSDUDWRU *3FRPSDUDWRU 86$57 5;7;&76576 &.DV$) 86$57 5;7;&76576 &.DV$) ,& 6&/6'$60%$ H[WUDP$)0DV$) ,& 6&/6'$ DV$) +'0,&(& &(&DV$) #9''$ 7HPS VHQVRU [ $'LQSXW 7$03(557& $/$50287 3:07,0(5 6&@ $ 069 DocID023402 Rev 4 59/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Low-speed internal (LSI) RC oscillator Table 36. LSI oscillator characteristics(1) Symbol Parameter fLSI tsu(LSI) Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.8 PLL characteristics The parameters given in Table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 19: General operating conditions. Table 37. PLL characteristics Value Symbol fPLL_IN fPLL_OUT tLOCK JitterPLL Parameter Unit Min Typ Max 1(2) 8.0 24(2) MHz PLL input clock duty cycle (2) 40 - 60(2) % PLL multiplier output clock 16(2) - 48 MHz PLL lock time - - 200(2) µs Cycle-to-cycle jitter - - 300(2) ps PLL input clock(1) 1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design, not tested in production. 6.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 38. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs Page (1 KB) erase time TA = - 40 to +105 °C 20 - 40 ms tME Mass erase time TA = - 40 to +105 °C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design, not tested in production. 60/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 39. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Min(1) Unit 10 kcycle at TA = 85 °C 30 at TA = 105 °C 10 10 kcycle(2) at TA = 55 °C 20 1 kcycle (2) Year 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 40. They are based on the EMS levels and classes defined in application note AN1709. Table 40. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 1.8 V, LQFP64, TA = +25 °C, Voltage limits to be applied on any I/O pin fHCLK = 48 MHz, to induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 1.8 V, LQFP64, TA = +25°C, fHCLK = 48 MHz, conforming to IEC 61000-4-4 4B Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. DocID023402 Rev 4 61/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 41. EMI characteristics Symbol Parameter SEMI 6.3.11 Conditions Monitored frequency band 0.1 to 30 MHz VDD = 1.8 V, TA = 25 °C, 30 to 130 MHz LQFP64 package Peak level compliant with 130 MHz to 1 GHz IEC 61967-2 EMI Level Max vs. [fHSE/fHCLK] Unit 8/48 MHz 0 22 dBµV 16 3.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. 62/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 42. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 All 2 2000 V VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming (charge device model) to ANSI/ESD STM5.3.1 All C3 250 V 1. Data based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 43. Electrical sensitivities Symbol LU 6.3.12 Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 44. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. DocID023402 Rev 4 63/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Table 44. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection IINJ 6.3.13 Injected current on BOOT0 –0 NA Injected current on all FT, FTf and POR pins –5 NA Injected current on all TTa, TC and RESET pins –5 +5 mA I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the conditions summarized in Table 19: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 45. I/O static characteristics Symbol VIL VIH Vhys Ilkg 64/104 Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Input leakage current(2) Conditions Min Typ Max TC and TTa I/O - - 0.3 VDDIOx+0.07(1) FT and FTf I/O - - 0.475 VDDIOx–0.2(1) BOOT0 - - 0.3 VDDIOx–0.3(1) All I/Os except BOOT0 pin - - 0.3 VDDIOx TC and TTa I/O 0.445 VDDIOx+0.398(1) FT and FTf I/O - - +0.2(1) - - +0.95(1) - - 0.5 VDDIOx BOOT0 0.2 VDDIOx All I/Os except BOOT0 pin 0.7 VDDIOx - TC and TTa I/O - 200(1) - - (1) - (1) - FT and FTf I/O 100 BOOT0 - 300 TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx - - ± 0.1 TTa in digital mode VDDIOx ≤ VIN ≤ VDDA - - 1 TTa in analog mode VSS ≤ VIN ≤ VDDA - - ± 0.2 FT and FTf I/O VDDIOx ≤ VIN ≤ 5 V - - 10 DocID023402 Rev 4 Unit V V mV µA STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 45. I/O static characteristics (continued) Symbol RPU Parameter Weak pull-up equivalent resistor (3) RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions Min Typ Max Unit VIN = VSS 25 40 55 kΩ VIN = - VDDIOx 25 40 55 kΩ - 5 - pF - 1. Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 44: I/O current injection susceptibility. 3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 for standard I/Os, and in Figure 19 for 5 V-tolerant I/Os. The following curves are design simulation results, not tested in production. DocID023402 Rev 4 65/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Figure 18. TC and TTa I/O input characteristics 7(67('5$1*( 77/VWDQGDUGUHTXLUHPHQW HQW LUHP HTX DUGU QG 6VWD 9,19 9 &02 [ '',2 9 ,+PLQ 81'(),1(',13875$1*( ',2[ 9' 9,+PLQ 9'',2[ 9,/PD[ XLUHPHQW WDQGDUGUHT V 6 2 0 & 9'',2[ 9,/PD[ 77/VWDQGDUGUHTXLUHPHQW 7(67('5$1*( 9'',2[9 06Y9 Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics 7(67('5$1*( 77/VWDQGDUGUHTXLUHPHQW HQW LUHP 9 9 ,+PLQ '',2 9 9,+PLQ [ 81'(),1(',13875$1*( '',2[ 9 9,/PD[ QG 6VWD &02 9,19 HTX DUGU '',2[ 77/VWDQGDUGUHTXLUHPHQW XLUHPHQW QGDUGUHT WD &026V [ 9'',2 9,/PD[ 7(67('5$1*( 9'',2[9 06Y9 66/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 16: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 16: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 19: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified). Table 46. Output voltage characteristics(1) Symbol Parameter Conditions VOL(2) Output low level voltage for an I/O pin VOH(2) Output high level voltage for an I/O pin VOLFm+(3) Output low level voltage for an FTf I/O pin in Fm+ mode |IIO| = 4 mA |IIO| = 10 mA Min Max Unit - 0.4 V VDDIOx–0.4 - V - 0.4 V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 16: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. Data based on characterization results. Not tested in production. 3. Data based on design simulation only. Not tested in production. DocID023402 Rev 4 67/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 20 and Table 47, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 19: General operating conditions. Table 47. I/O AC characteristics(1)(2) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions Min Max Unit - 1 MHz - 125 - 125 - 4 - 62.5 - 62.5 - 10 - 25 - 25 - 0.5 - 16 - 44 10 - fmax(IO)out Maximum frequency(3) x0 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF fmax(IO)out Maximum frequency(3) 01 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF fmax(IO)out Maximum frequency(3) 11 Fm+ configuration (4) - tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time CL = 50 pF tr(IO)out Output rise time tEXTIpw Pulse width of external signals detected by the EXTI controller - ns MHz ns MHz ns MHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design, not tested in production. 3. The maximum frequency is defined in Figure 20. 4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration. Figure 20. I/O AC characteristics definition W I,2RXW W U,2RXW 7 7DQGLIWKHGXW\F\FOHLV 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWW U I ZKHQORDGHGE\&VHHWKHWDEOH,2$&FKDUDFWHULVWLFVGHILQLWLRQ 069 68/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 6.3.14 Electrical characteristics NRST and NPOR pin characteristics NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 19: General operating conditions. Table 48. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1) VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV V RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ VF(NRST) NRST input filtered pulse - - - 100(1) ns - 700(1) - - ns VNF(NRST) NRST input not filtered pulse 1. Data based on design simulation only. Not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). Figure 21. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9'' 1567 538 ,QWHUQDOUHVHW )LOWHU ) 069 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 48: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. NPOR pin characteristics The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor to the VDDA, RPU. Unless otherwise specified, the parameters given in Table 49 below are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 19: General operating conditions. DocID023402 Rev 4 69/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Table 49. NPOR pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NPOR) NPOR Input low level voltage - - - 0.475 VDDA - 0.2(1) VIH(NPOR) NPOR Input high level voltage - 0.5 VDDA + 0.2(1) - - Vhys(NPOR) NPOR Schmitt trigger voltage hysteresis - - 100(1) - mV VIN = VSS 25 40 55 kΩ RPU Weak pull-up equivalent resistor(2) Unit V 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 6.3.15 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 19: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 50. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON - 2.4 - 3.6 V VDDA = 3.3 V - 0.9 - mA - 0.6 - 14 MHz IDDA (ADC) Current consumption of the ADC(1) fADC ADC clock frequency fS(2) Sampling rate 12-bit resolution 0.043 - 1 MHz External trigger frequency fADC = 14 MHz, 12-bit resolution - - 823 kHz 12-bit resolution - - 17 1/fADC fTRIG(2) VAIN Conversion voltage range - 0 - VDDA V RAIN(2) External input impedance See Equation 1 and Table 51 for details - - 50 kΩ RADC(2) Sampling switch resistance - - - 1 kΩ CADC(2) Internal sample and hold capacitor - - - 8 pF tCAL(2)(3) Calibration time 70/104 fADC = 14 MHz 5.9 µs - 83 1/fADC DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 50. ADC characteristics (continued) Symbol Parameter WLATENCY(2)(4) tlatr (2) ADC_DR register ready latency Conditions Min Typ Max Unit ADC clock = HSI14 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle fADC = fPCLK/2 = 14 MHz 0.196 µs fADC = fPCLK/2 5.5 1/fPCLK 0.219 µs 10.5 1/fPCLK Trigger conversion latency fADC = fPCLK/4 = 12 MHz fADC = fPCLK/4 JitterADC tS(2) fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs fADC = fHSI14 - 1 - 1/fHSI14 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC ADC jitter on trigger conversion Sampling time tSTAB(2) Stabilization time tCONV(2) Total conversion time (including sampling time) fADC = 14 MHz, 12-bit resolution 12-bit resolution 14 1 1/fADC - 18 14 to 252 (tS for sampling +12.5 for successive approximation) µs 1/fADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA on IDD should be taken into account. 2. Guaranteed by design, not tested in production. 3. Specified value includes only ADC timing. It does not include the latency of the register access. 4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time. Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 51. RAIN max for fADC = 14 MHz Ts (cycles) tS (µs) RAIN max (kΩ)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 DocID023402 Rev 4 71/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Table 51. RAIN max for fADC = 14 MHz (continued) Ts (cycles) tS (µs) RAIN max (kΩ)(1) 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 52. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ±0.8 ±1.5 ET Total unadjusted error ±3.3 ±4 EO Offset error ±1.9 ±2.8 EG Gain error ±2.8 ±3 ED Differential linearity error ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 ET Total unadjusted error ±3.3 ±4 ±1.9 ±2.8 ±2.8 ±3 ±0.7 ±1.3 ±1.2 ±1.7 EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 3 V to 3.6 V TA = 25 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.7 V to 3.6 V TA = - 40 to 105 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.4 V to 3.6 V TA = 25 °C Unit LSB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. 72/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Figure 22. ADC accuracy characteristics 966$ (* ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH 7KHLGHDOWUDQVIHUFXUYH (QGSRLQWFRUUHODWLRQOLQH (7 (2 (/ (' /6%,'($/ (7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW LGHDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH 9''$ 069 Figure 23. Typical connection diagram using the ADC 9''$ 6DPSOHDQGKROG$'& FRQYHUWHU 97 5$,1 9$,1 5$'& $,1[ 97 &SDUDVLWLF ,/ $ ELW FRQYHUWHU &$'& 069 1. Refer to Table 50: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 10: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DocID023402 Rev 4 73/104 84 Electrical characteristics 6.3.16 STM32F058C8 STM32F058R8 STM32F058T8 DAC electrical specifications Table 53. DAC characteristics Symbol Parameter VDDA Analog supply voltage for DAC ON RLOAD(1) Resistive load with buffer ON RO(1) CLOAD(1) Min Typ Max Unit Comments 2.4 - 3.6 V - 5 - - kΩ Load connected to VSSA 25 - - kΩ Load connected to VDDA Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer ON 0.2 - - V DAC_OUT max(1) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC_OUT max(1) Higher DAC_OUT voltage with buffer OFF - - VDDA – 1LSB V - - 600 µA IDDA(1) DAC DC current consumption in quiescent mode(2) With no load, middle code (0x800) on the input - - 700 µA With no load, worst code (0xF1C) on the input Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration - - ±2 LSB Given for the DAC in 12-bit configuration - - ±1 LSB Given for the DAC in 10-bit configuration - - ±4 LSB Given for the DAC in 12-bit configuration - - ±10 mV - - ±3 LSB Given for the DAC in 10-bit at VDDA = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VDDA = 3.6 V DNL(3) INL(3) Offset(3) 74/104 Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VDDA/2) DocID023402 Rev 4 It gives the maximum output excursion of the DAC. - STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 53. DAC characteristics (continued) Symbol Min Typ Max Unit Gain error(3) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration Settling time (full scale: for a 10-bit input code transition (3) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value ±1LSB - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF Update rate(3) Parameter Comments MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1. Guaranteed by design, not tested in production. 2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Figure 24. 12-bit buffered / non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ ELWGLJLWDO WRDQDORJ FRQYHUWHU '$&B287[ &/ 069 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID023402 Rev 4 75/104 84 Electrical characteristics 6.3.17 STM32F058C8 STM32F058R8 STM32F058T8 Comparator characteristics Table 54. Comparator characteristics Symbol VDDA Parameter Analog supply voltage Conditions VREFINT scaler not in use Min(1) Typ Max(1) 1.65 VREFINT scaler in use 2 Unit - 3.6 V VIN Comparator input voltage range - 0 - VDDA - VSC VREFINT scaler offset voltage - - ±5 ±10 mV tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - Next activations - - 0.2 Startup time to reach propagation delay specification - - 60 Ultra-low power mode - 2 4.5 Low power mode - 0.7 1.5 Medium power mode - 0.3 0.6 VDDA ≥ 2.7 V - 50 100 VDDA < 2.7 V - 100 240 Ultra-low power mode - 2 7 Low power mode - 0.7 2.1 Medium power mode - 0.3 1.2 VDDA ≥ 2.7 V - 90 180 VDDA < 2.7 V - 110 300 tSTART Comparator startup time Propagation delay for 200 mV step with 100 mV overdrive High speed mode tD Propagation delay for full range step with 100 mV overdrive High speed mode 1000 (2) ms µs µs ns µs ns Voffset Comparator offset error - - ±4 ±10 mV dVoffset/dT Offset error temperature coefficient - - 18 - µV/°C Ultra-low power mode - 1.2 1.5 Low power mode - 3 5 Medium power mode - 10 15 High speed mode - 75 100 IDD(COMP) 76/104 COMP current consumption DocID023402 Rev 4 µA STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 54. Comparator characteristics (continued) Symbol Parameter No hysteresis (COMPxHYST[1:0]=00) Vhys Min(1) Typ Max(1) Conditions Comparator hysteresis - - High speed mode Low hysteresis (COMPxHYST[1:0]=01) All other power modes 3 High speed mode Medium hysteresis (COMPxHYST[1:0]=10) All other power modes 7 High speed mode High hysteresis (COMPxHYST[1:0]=11) All other power modes 18 5 9 19 0 Unit 13 8 10 26 15 mV 19 49 31 40 1. Data based on characterization results, not tested in production. 2. For more details and conditions see Figure 25: Maximum VREFINT scaler startup time from power down. Figure 25. Maximum VREFINT scaler startup time from power down Ϯ͘Ϭsчs фϮ͘ϰs Ϯ͘ϰsчs фϯ͘Ϭs ϯ͘Ϭsчs фϯ͘ϲs ϭϬϬϬ ƚ^ͺ^;ŵĂǆͿ ;ŵƐͿ ϭϬϬ ϭϬ ϭ ͲϰϬ ͲϮϬ Ϭ ϮϬ ϰϬ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ DocID023402 Rev 4 ϲϬ ϴϬ 77/104 84 Electrical characteristics 6.3.18 STM32F058C8 STM32F058R8 STM32F058T8 Temperature sensor characteristics Table 55. TS characteristics Symbol Parameter TL(1) Avg_Slope Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) V30 Average slope (2) Voltage at 30 °C (± 5 °C) tSTART(1) ADC_IN16 buffer startup time - - 10 µs tS_temp(1) ADC sampling time when reading the temperature 4 - - µs 1. Guaranteed by design, not tested in production. 2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 2: Temperature sensor calibration values. 6.3.19 VBAT monitoring characteristics Table 56. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 2 x 50 - kΩ Q Ratio on VBAT measurement - 2 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 4 - - µs Er(1) tS_vbat(1) 1. Guaranteed by design, not tested in production. 6.3.20 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 57. TIMx characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT Timer external clock frequency on CH1 to CH4 16-bit timer maximum period tMAX_COUNT 32-bit counter maximum period 78/104 Conditions Min Typ Max Unit - - 1 - tTIMxCLK fTIMxCLK = 48 MHz - 20.8 - ns - - fTIMxCLK/2 - MHz fTIMxCLK = 48 MHz - 24 - MHz - - 216 - tTIMxCLK fTIMxCLK = 48 MHz - 1365 - µs - - 232 - tTIMxCLK fTIMxCLK = 48 MHz - 89.48 - s DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 58. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 59. WWDG min/max timeout value at 48 MHz (PCLK) 6.3.21 Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0853 5.4613 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 Unit ms Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.13: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: DocID023402 Rev 4 79/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Table 60. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 19: General operating conditions. Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 61. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Max Master mode - 18 Slave mode - 18 - 6 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 15 pF tsu(NSS) NSS setup time Slave mode 4Tpclk - th(NSS) NSS hold time Slave mode 2Tpclk + 10 - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 Tpclk/2 -2 Tpclk/2 + 1 Master mode 4 - Slave mode 5 - Master mode 4 - Slave mode 5 - Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk Data output disable time Slave mode 0 18 tv(SO) Data output valid time Slave mode (after enable edge) - 22.5 tv(MO) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 11.5 - Master mode (after enable edge) 2 - Slave mode 25 75 tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO)(2) tdis(SO) (3) th(SO) th(MO) DuCy(SCK) Data input setup time Data input hold time Data output hold time SPI slave input clock duty cycle Unit MHz ns ns % 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 80/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Figure 26. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. 6&.LQSXW WVX166 WK166 WZ6&.+ WU6&. &3+$ &32/ &3+$ &32/ WD62 WZ6&./ 0,62RXWSXW WY62 WK62 )LUVWELW287 WI6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, WVX6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 Figure 27. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 &3+$ &32/ &3+$ &32/ 0,62RXWSXW WY62 )LUVWELW287 WVX6, 026,LQSXW WK62 1H[WELWV287 WU6&. WGLV62 /DVWELW287 WK6, )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DocID023402 Rev 4 81/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Figure 28. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WZ6&.+ WZ6&./ WVX0, 0,62 ,13 87 WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 % , 7287 06%287 WY02 /6%287 WK02 DLF 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 62. I2S characteristics(1) Symbol fCK 1/tc(CK) Parameter I2S clock frequency Conditions Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode tr(CK) I2S clock rise time tf(CK) I2S clock fall time Capacitive load CL = 15 pF Min Max 1.597 1.601 0 6.5 - 10 - 12 306 - 312 - tw(CKH) I2S tw(CKL) 2 I S clock low time Master fPCLK= 16 MHz, audio frequency = 48 kHz tv(WS) WS valid time Master mode 2 - th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 7 - th(WS) WS hold time Slave mode 0 - Slave mode 25 75 DuCy(SCK) 82/104 I2S clock high time slave input clock duty cycle DocID023402 Rev 4 Unit MHz ns % STM32F058C8 STM32F058R8 STM32F058T8 Electrical characteristics Table 62. I2S characteristics(1) (continued) Symbol tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Parameter Conditions Data input setup time (2) (2) tv(SD_MT)(2) tv(SD_ST)(2) th(SD_MT) th(SD_ST) Data input hold time Data output valid time Data output hold time Min Max Master receiver 6 - Slave receiver 2 - Master receiver 4 - Slave receiver 0.5 - Master transmitter - 4 Slave transmitter - 31 Master transmitter 0 - Slave transmitter 13 - Unit ns 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns. Figure 29. I2S slave timing diagram (Philips protocol) &.,QSXW WF&. &32/ &32/ WZ&.+ WK:6 WZ&./ :6LQSXW WY6'B67 WVX:6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW WVX6'B65 6'UHFHLYH /6%UHFHLYH WK6'B67 %LWQWUDQVPLW WK6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID023402 Rev 4 83/104 84 Electrical characteristics STM32F058C8 STM32F058R8 STM32F058T8 Figure 30. I2S master timing diagram (Philips protocol) WI&. WU&. &.RXWSXW WF&. &32/ WZ&.+ &32/ WY:6 WK:6 WZ&./ :6RXWSXW WY6'B07 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW /6%UHFHLYH /6%WUDQVPLW WK6'B05 WVX6'B05 6'UHFHLYH %LWQWUDQVPLW WK6'B07 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Data based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 84/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array package. Figure 31. UFBGA64 package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < + %277209,(: EEDOOV HHH 0 = < ; III 0 = 7239,(: $B0(B9 1. Drawing is not to scale. Table 63. UFBGA64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 DocID023402 Rev 4 85/104 100 Package information STM32F058C8 STM32F058R8 STM32F058T8 Table 63. UFBGA64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 32. Recommended footprint for UFBGA64 package 'SDG 'VP $B)3B9 Table 64. UFBGA64 recommended PCB design rules Dimension 86/104 Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 33. UFBGA64 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ )5+ ĂƚĞĐŽĚĞ ^ƚĂŶĚĂƌĚ^důŽŐŽ < :: ZĞǀŝƐŝŽŶĐŽĚĞ ĂůůϭŝĚĞŶƚŝĨŝĞƌ 5 D^ϯϵϬϮϬsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID023402 Rev 4 87/104 100 Package information 7.2 STM32F058C8 STM32F058R8 STM32F058T8 LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 34. LQFP64 package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not to scale. Table 65. LQFP64 package mechanical data inches(1) millimeters Symbol 88/104 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Package information Table 65. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 35. Recommended footprint for LQFP64 package DLF 1. Dimensions are expressed in millimeters. DocID023402 Rev 4 89/104 100 Package information STM32F058C8 STM32F058R8 STM32F058T8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 36. LQFP64 package marking example 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ 670) 57 'DWHFRGH z tt 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 90/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 7.3 Package information UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 37. UFQFPN48 package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU ( 5W\S 'HWDLO= = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. DocID023402 Rev 4 91/104 100 Package information STM32F058C8 STM32F058R8 STM32F058T8 Table 66. UFQFPN48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38. Recommended footprint for UFQFPN48 package 1. Dimensions are expressed in millimeters. 92/104 DocID023402 Rev 4 $%B)3B9 STM32F058C8 STM32F058R8 STM32F058T8 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 39. UFQFPN48 package marking example 3URGXFWLGHQWLILFDWLRQ 670) &8 'DWHFRGH 3LQLGHQWLILHU < :: 5HYLVLRQFRGH 5 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID023402 Rev 4 93/104 100 Package information 7.4 STM32F058C8 STM32F058R8 STM32F058T8 WLCSP36 package information WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 40. WLCSP36 package outline H EEE = $EDOOORFDWLRQ ) H * $ 'HWDLO$ H H ) $ $ $ %XPSVLGH 6LGHYLHZ ; < $ %XPS $ RULHQWDWLRQ UHIHUHQFH HHH = DDD = $ EEDOOV FFF = ; < GGG = :DIHUEDFNVLGH E = 6HDWLQJSODQH 'HWDLO$ URWDWHG Ϭ>ͺDͺsϮ 1. Drawing is not to scale. Table 67. WLCSP36 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.570 2.605 2.640 0.1012 0.1026 0.1039 E 2.668 2.703 2.738 0.1050 0.1064 0.1078 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - b 94/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Package information Table 67. WLCSP36 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.3025 - - 0.0119 - G - 0.3515 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 41. Recommended pad footprint for WLCSP36 package 'SDG 'VP 069 Table 68. WLCSP36 recommended PCB design rules Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed DocID023402 Rev 4 95/104 100 Package information STM32F058C8 STM32F058R8 STM32F058T8 Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. WLCSP36 package marking example Žƚ WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ ) ZĞǀŝƐŝŽŶĐŽĚĞ 5 ĂƚĞĐŽĚĞ < :: D^ϯϵϬϰϮsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 96/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 7.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 19: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 69. Package thermal characteristics Symbol ΘJA 7.5.1 Parameter Value Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient UFBGA64 - 5 × 5 mm 65 Thermal resistance junction-ambient UFQFPN48 - 7 × 7 mm 32 Thermal resistance junction-ambient WLCSP36 - 2.6 × 2.7 mm 60 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.5.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F058C8/R8/T8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. DocID023402 Rev 4 97/104 100 Package information STM32F058C8 STM32F058R8 STM32F058T8 Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Using the values obtained in Table 69 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 19: General operating conditions. In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Ordering information). Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Using the values obtained in Table 69 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts. 98/104 DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Package information Refer to Figure 43 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. Figure 43. LQFP64 PD max versus TA 3'P: 6XIIL[ 6XIIL[ 7$& DocID023402 Rev 4 06Y9 99/104 100 Ordering information 8 STM32F058C8 STM32F058R8 STM32F058T8 Ordering information For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 70. Ordering information scheme STM32 Example: F Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 058 = STM32F058xx Pin count T = 36 pins C = 48 pins R = 64 pins User code memory size 8 = 64 Kbyte Package H = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = –40 °C to +85 °C 7 = –40 °C to +105 °C Options xxx = code ID of programmed parts (includes packing type) TR = tape and reel packing blank = tray packing 100/104 DocID023402 Rev 4 058 R 8 T 6 x STM32F058C8 STM32F058R8 STM32F058T8 9 Revision history Revision history Table 71. Document revision history Date Revision 06-June-2014 1 Initial release 2 Updated the following: – DAC and power management feature descriptions in Features – Table 1: STM32F058C8/R8/T8 family device features and peripheral counts – the position of PC3 in UFBGA64 package in Table 12: Pin definitions,. – Section 3.5.1: Power supply schemes – Figure 13: Power supply scheme – Table 17: Voltage characteristics – Table 20: General operating conditions: updated the footnote for VIN parameter – Table 28: Typical and maximum current consumption from the VBAT supply – Table 52: ADC characteristics – Table 33: High-speed external user clock characteristics: replaced VDD with VDDIOX – Replaced TBD occurrences with values in Table 22: Typical and maximum current consumption from VDD at 1.8 V, – Replaced TBD occurrences with values in Table 23: Typical and maximum current consumption from the VDDA supply, – Table 34: Low-speed external user clock characteristics: replaced VDD with VDDIOX – Table 37: HSI oscillator characteristics and Figure 19: HSI oscillator accuracy characterization results for soldered parts – Table 38: HSI14 oscillator characteristics: changed the min value for ACCHSI14 – Table 41: Flash memory characteristics: changed the values for tME and IDD in write mode – Table 43: EMS characteristics: changed the value of VEFTB – Table 45: ESD absolute maximum ratings – Figure 10: STM32F058x8 memory map – Figure 21: TC and TTa I/O input characteristics – Figure 22: Five volt tolerant (FT and FTf) I/O input characteristics – Figure 23: I/O AC characteristics definition – tSTART definition in Table 24: Embedded internal reference voltage – tSTAB characteristics in Table 52: ADC characteristics – Table 56: Comparator characteristics: changed the description and values for VSC, VDDA and VREFINT parameters. Added Figure 28: Maximum VREFINT scaler startup time from power down 29-Sep-2015 Changes DocID023402 Rev 4 101/104 103 Revision history STM32F058C8 STM32F058R8 STM32F058T8 Table 71. Document revision history (continued) Date Revision Changes – Table 57: TS characteristics: changed the min value for TStemp 29-Sep-2015 16-Dec-2015 102/104 2 (continued) 3 – Table 58: VBAT monitoring characteristics: changed the min value for TS-vbat and the typical value for R parameters – Section 6.3.22: Communication interfaces: updated the description and features in the subsection I2C interface characteristics – Table 64: I2S characteristics: updated the min values for data input hold time (master and slave receiver) – Table 31: Peripheral current consumption Addition of WLCSP36 package. Updates in: – Section 2: Description – Table 1: STM32F058C8/R8/T8 family device features and peripheral counts,Table 5: No. of capacitive sensing channels available on STM32F058C8/R8/T8 devices, – Section 4: Pinouts and pin descriptions with the addition of Figure 6: WLCSP36 package pinout – Table 12: Pin definitions, – Table 20: General operating conditions – Section 7: Package information with the addition of Section 7.5: WLCSP36 package information – Table 74: Package thermal characteristics – Section 8: Part numbering Update of the device marking examples in Section 7: Package information. Section 2: Description: – Table 1: STM32F058C8/R8/T8 family device features and peripheral counts - number of SPIs corrected for 36-pin package – Figure 1: Block diagram modified Section 3: Functional overview: – Figure 2: Clock tree modified; divider for CEC corrected – Table 7: Comparison of I2C analog and digital filters - adding “extra” information for FastPlus mode output Section 4: Pinouts and pin descriptions: – Package pinout figures updated (look and feel) – Figure 6: WLCSP36 package pinout - now presented in top view – Table 12: Pin definitions - note 3 and 5 added; previous note for PB8 removed; Section 6: Electrical characteristics: – Table 21: Embedded internal reference voltage - removed 40°C-85°C temperature range line and the associated note – Table 45: I/O static characteristics - removed note – Section 6.3.15: 12-bit ADC characteristics - changed introductory sentence – Table 50: ADC characteristics updated and table footnotes 3 and 4 added DocID023402 Rev 4 STM32F058C8 STM32F058R8 STM32F058T8 Revision history Table 71. Document revision history (continued) Date Revision 16-Dec-2015 3 (continued) 6-Jan-2017 4 Changes – Table 54: Comparator characteristics - VDDA min modified – Table 57: TIMx characteristics modified – Table 62: I2S characteristics reorganized Section 6: Electrical characteristics: – Table 33: LSE oscillator characteristics (fLSE = 32.768 kHz) information on configuring different drive capabilities removed. See the corresponding reference manual. – Table 21: Embedded internal reference voltage - VREFINT values – Table 53: DAC characteristics - min. RLOAD to VDDA defined – Figure 26: SPI timing diagram - slave mode and CPHA = 0 and Figure 27: SPI timing diagram - slave mode and CPHA = 1 enhanced and corrected Section 8: Ordering information: – The name of the section changed from the previous “Part numbering” DocID023402 Rev 4 103/104 103 STM32F058C8 STM32F058R8 STM32F058T8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 104/104 DocID023402 Rev 4

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