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STM32F072RBT6

STM32F072RBT6

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    LQFP-64_10X10MM

  • 描述:

    基于Arm®的32位MCU,最大128 KB闪存,无晶体USB FS 2.0、CAN、12定时器、ADC、DAC和通信接口,2.0-3.6 V

  • 数据手册
  • 价格&库存
STM32F072RBT6 数据手册
STM32F072x8 STM32F072xB ARM®-based 32-bit MCU, up to 128 KB Flash, crystal-less USB FS 2.0, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6 V Datasheet - production data Features )%*$ ® ® • Core: ARM 32-bit Cortex -M0 CPU, frequency up to 48 MHz LQFP100 14x14 mm UFQFPN48 LQFP64 10x10 mm 7x7 mm LQFP48 7x7 mm • Memories – 64 to 128 Kbytes of Flash memory – 16 Kbytes of SRAM with HW parity UFBGA100 7x7 mm UFBGA64 5x5 mm WLCSP49 3.3x3.1 mm • Calendar RTC with alarm and periodic wakeup from Stop/Standby • CRC calculation unit • Reset and power management – Digital and I/O supply: VDD = 2.0 V to 3.6 V – Analog supply: VDDA = VDD to 3.6 V – Selected I/Os: VDDIO2 = 1.65 V to 3.6 V – Power-on/Power down reset (POR/PDR) – Programmable voltage detector (PVD) – Low power modes: Sleep, Stop, Standby – VBAT supply for RTC and backup registers • Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x6 PLL option – Internal 40 kHz RC oscillator – Internal 48 MHz oscillator with automatic trimming based on ext. synchronization • Up to 87 fast I/Os – All mappable on external interrupt vectors – Up to 68 I/Os with 5V tolerant capability and 19 with independent supply VDDIO2 • Seven-channel DMA controller • 12 timers – One 16-bit advanced-control timer for six-channel PWM output – One 32-bit and seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding or DAC control – Independent and system watchdog timers – SysTick timer • Communication interfaces – Two I2C interfaces supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink, one supporting SMBus/PMBus and wakeup – Four USARTs supporting master synchronous SPI and modem control, two with ISO7816 interface, LIN, IrDA, auto baud rate detection and wakeup feature – Two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames, and with I2S interface multiplexed – CAN interface – USB 2.0 full-speed interface, able to run from internal 48 MHz oscillator and with BCD and LPM support • One 12-bit, 1.0 µs ADC (up to 16 channels) – Conversion range: 0 to 3.6 V – Separate analog supply: 2.4 V to 3.6 V • HDMI CEC wakeup on header reception • One 12-bit D/A converter (with 2 channels) • 96-bit unique ID • Two fast low-power analog comparators with programmable input and output • All packages ECOPACK®2 • Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors • Serial wire debug (SWD) Table 1. Device summary Reference STM32F072x8 STM32F072xB January 2017 This is information on a product in full production. DocID025004 Rev 5 Part number STM32F072C8, STM32F072R8, STM32F072V8, STM32F072CB, STM32F072RB, STM32F072VB 1/128 www.st.com Contents STM32F072x8 STM32F072xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 2/128 3.5.1 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22 3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID025004 Rev 5 STM32F072x8 STM32F072xB 3.14.6 Contents SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25 3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26 3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.22 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.23 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 54 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DocID025004 Rev 5 3/128 4 Contents 7 STM32F072x8 STM32F072xB 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.20 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.4 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F072x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitive sensing GPIOs available on STM32F072x8/xB devices. . . . . . . . . . . . . . . . . . 20 Number of capacitive sensing channels available on STM32F072x8/xB devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F072x8/xB I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F072x8/xB USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F072x8/xB SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32F072x8/xB pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 41 Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 42 Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 43 Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 43 Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 44 Alternate functions available on port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F072x8/xB peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 46 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54 Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 56 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 58 Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 59 Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 60 Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DocID025004 Rev 5 5/128 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. 6/128 STM32F072x8 STM32F072xB Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 WLCSP49 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DocID025004 Rev 5 STM32F072x8 STM32F072xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WLCSP49 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32F072xB memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71 HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 WLCSP49 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 WLCSP49 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 DocID025004 Rev 5 7/128 8 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. 8/128 STM32F072x8 STM32F072xB LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP64 PD max versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 DocID025004 Rev 5 STM32F072x8 STM32F072xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F072x8/xB microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website. DocID025004 Rev 5 9/128 27 Description 2 STM32F072x8 STM32F072xB Description The STM32F072x8/xB microcontrollers incorporate the high-performance ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I2Cs, two SPI/I2S, one HDMI CEC and four USARTs), one USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer. The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs. 10/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Description Table 2. STM32F072x8/xB family device features and peripheral counts Peripheral STM32F072Cx Flash memory (Kbyte) 64 128 STM32F072Rx 64 128 SRAM (Kbyte) Timers Comm. interfaces 1 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 2 (16-bit) SPI [I2S](1) 2 [2] 2C 2 USART 4 CAN 1 USB 1 CEC 1 12-bit ADC (number of channels) 64 128 16 Advanced control I STM32F072Vx 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.) 12-bit DAC (number of channels) 1 (2) Analog comparator 2 GPIOs 37 51 87 Capacitive sensing channels 17 18 24 Max. CPU frequency 48 MHz Operating voltage 2.0 to 3.6 V Operating temperature Ambient operating temperature: -40°C to 85°C / -40°C to 105°C Junction temperature: -40°C to 105°C / -40°C to 125°C Packages LQFP48 UFQFPN48 WLCSP49 LQFP64 UFBGA64 LQFP100 UFBGA100 1. The SPI interface can be used either in SPI mode or in I2S audio mode. DocID025004 Rev 5 11/128 27 Description STM32F072x8 STM32F072xB Figure 1. Block diagram 32:(5 6HULDO:LUH 'HEXJ 2EO )ODVK PHPRU\ LQWHUIDFH 6:&/. 6:',2 DV$) 19,& 65$0 FRQWUROOHU %XVPDWUL[ &257(;0&38 I0$; 0+] 92/75(* 9WR9 9'' )ODVK*3/ XSWR.% ELW #9'' 65$0 .% #9''$ +6, +6, 3//&/. /6, *3'0$ FKDQQHOV +6, 9'' WR9 966 9'',22.,1 325 5HVHW ,QW 6833/@ *3,2SRUW' 3(>@ *3,2SRUW( 3)>@3) 3)>@ *3,2SRUW) JURXSVRI FKDQQHOV '' 026,6' 0,620&. 6&.&. 166:6DV$) ,1387 ,1387 287387 DV$) $+% 3:07,0(5 FKDQQHOV FRPSOFKDQQHOV %5.(75LQSXWDV$) 7,0(5ELW FK(75DV$) 7,0(5 FK(75DV$) 7,0(5 FKDQQHODV$) 7,0(5 FKDQQHOV FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) $3% (;7,7:.83 86% 3+< 86% 65$0% :LQGRZ:'* ,5B287DV$) %[&$1 '%*0&8 63,,6 86$57 5;7;&76576 &.DV$) 86$57 5;7;&76576 &.DV$) 86$57 5;7;&76576 &.DV$) 86$57 5;7;&76576 &.DV$) ,& 6&/6'$60%$ P$)0 DV$) ,& 6&/6'$ P$)0 DV$) 63,,6 6ƒ&@ $                   069 72/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics High-speed internal 48 MHz (HSI48) RC oscillator Table 43. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM Parameter Conditions Min Typ Max Unit - - 48 - MHz Frequency HSI48 user-trimming step (2) - DuCy(HSI48) Duty cycle 0.09 - 45 TA = –40 to 105 °C ACCHSI48 TA = –10 to 85 °C Accuracy of the HSI48 oscillator (factory calibrated) T = 0 to 70 °C A IDDA(HSI48) 0.14 - % (2) % (3) 0.2 55 (3) - 4.7 % -4.1(3) - 3.7(3) % - (3) % -4.9 (3) -3.8 TA = 25 °C tsu(HSI48) (2) (2) -2.8 3.4 - 2.9 % µs µA HSI48 oscillator startup time - - - 6(2) HSI48 oscillator power consumption - - 312 350(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 21. HSI48 oscillator accuracy characterization results  0$; 0,1               7>ƒ&@ $         069 DocID025004 Rev 5 73/128 99 Electrical characteristics STM32F072x8 STM32F072xB Low-speed internal (LSI) RC oscillator Table 44. LSI oscillator characteristics(1) Symbol Parameter fLSI tsu(LSI) Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.9 PLL characteristics The parameters given in Table 45 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 45. PLL characteristics Value Symbol fPLL_IN fPLL_OUT tLOCK JitterPLL Parameter Unit Min Typ Max 1(2) 8.0 24(2) MHz PLL input clock duty cycle (2) 40 - 60(2) % PLL multiplier output clock 16(2) - 48 MHz PLL lock time - - 200(2) µs Cycle-to-cycle jitter - - 300(2) ps PLL input clock(1) 1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design, not tested in production. 6.3.10 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 46. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs Page (2 KB) erase time TA = - 40 to +105 °C 20 - 40 ms tME Mass erase time TA = - 40 to +105 °C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design, not tested in production. 74/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Table 47. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Min(1) Unit 10 kcycle at TA = 85 °C 30 at TA = 105 °C 10 10 kcycle(2) at TA = 55 °C 20 1 kcycle (2) Year 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 48. They are based on the EMS levels and classes defined in application note AN1709. Table 48. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP100, TA = +25 °C, Voltage limits to be applied on any I/O pin fHCLK = 48 MHz, to induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25°C, fHCLK = 48 MHz, conforming to IEC 61000-4-4 4B Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. DocID025004 Rev 5 75/128 99 Electrical characteristics STM32F072x8 STM32F072xB Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 49. EMI characteristics Symbol Parameter SEMI 6.3.12 Conditions Monitored frequency band 0.1 to 30 MHz VDD = 3.6 V, TA = 25 °C, 30 to 130 MHz LQFP100 package Peak level compliant with 130 MHz to 1 GHz IEC 61967-2 EMI Level Max vs. [fHSE/fHCLK] Unit 8/48 MHz -2 27 dBµV 17 4 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. 76/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Table 50. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit All 2 2000 V C3 250 C4 500 VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming WLCSP49 (charge device model) to ANSI/ESD STM5.3.1 All others V 1. Data based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 51. Electrical sensitivities Symbol LU 6.3.13 Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 52. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. DocID025004 Rev 5 77/128 99 Electrical characteristics STM32F072x8 STM32F072xB Table 52. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection IINJ 6.3.14 Injected current on BOOT0 and PF1 pins –0 NA Injected current on PC0 pin –0 +5 Injected current on PA11 and PA12 pins with induced leakage current on adjacent pins less than -1 mA –5 NA Injected current on all other FT and FTf pins –5 NA Injected current on all other TTa, TC and RST pins –5 +5 mA I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 53. I/O static characteristics Symbol VIL VIH Vhys Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Conditions Typ Max - - 0.3 VDDIOx FT and FTf I/O - - 0.475 VDDIOx–0.2(1) BOOT0 - - 0.3 VDDIOx–0.3(1) All I/Os except BOOT0 pin - - 0.3 VDDIOx TC and TTa I/O 0.445 VDDIOx+0.398(1) - - FT and FTf I/O 0.5 VDDIOx +0.2(1) - - BOOT0 0.2 VDDIOx+0.95(1) - - All I/Os except BOOT0 pin 0.7 VDDIOx - - TC and TTa I/O - 200(1) - - (1) - (1) - FT and FTf I/O - DocID025004 Rev 5 100 300 Unit +0.07(1) TC and TTa I/O BOOT0 78/128 Min V V mV STM32F072x8 STM32F072xB Electrical characteristics Table 53. I/O static characteristics (continued) Symbol Ilkg RPU Parameter Input leakage current(2) Weak pull-up equivalent resistor (3) RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions Min Typ Max TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx - - ± 0.1 TTa in digital mode VDDIOx ≤ VIN ≤ VDDA - - 1 TTa in analog mode VSS ≤ VIN ≤ VDDA - - ± 0.2 FT and FTf I/O VDDIOx ≤ VIN ≤ 5 V - - 10 VIN = VSS 25 40 55 kΩ VIN = - VDDIOx 25 40 55 kΩ - 5 - pF - Unit µA 1. Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52: I/O current injection susceptibility. 3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for 5 V-tolerant I/Os. The following curves are design simulation results, not tested in production. DocID025004 Rev 5 79/128 99 Electrical characteristics STM32F072x8 STM32F072xB Figure 22. TC and TTa I/O input characteristics   7(67('5$1*(  77/VWDQGDUGUHTXLUHPHQW HQW LUHP HTX DUGU QG 6VWD 9,1 9 9    &02   [ '',2 9 ,+PLQ  81'(),1(',13875$1*( ',2[ 9' 9,+PLQ    9'',2[ 9,/PD[  XLUHPHQW WDQGDUGUHT V 6 2 0 &   9'',2[ 9,/PD[  77/VWDQGDUGUHTXLUHPHQW 7(67('5$1*(             9'',2[ 9 06Y9 Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics   7(67('5$1*(  77/VWDQGDUGUHTXLUHPHQW HQW LUHP  9   9 ,+PLQ '',2 9 9,+PLQ   [ 81'(),1(',13875$1*(   '',2[ 9 9,/PD[  QG 6VWD &02 9,1 9 HTX DUGU   '',2[ 77/VWDQGDUGUHTXLUHPHQW XLUHPHQW QGDUGUHT WD  &026V [ 9'',2 9,/PD[  7(67('5$1*(             9'',2[ 9 06Y9 80/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 21: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 21: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified). Table 54. Output voltage characteristics(1) Symbol Parameter VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(4) Output low level voltage for an I/O pin VOH(4) Output high level voltage for an I/O pin VOLFm+(3) Output low level voltage for an FTf I/O pin in Fm+ mode Conditions Min Max CMOS port(2) |IIO| = 8 mA VDDIOx ≥ 2.7 V - 0.4 VDDIOx–0.4 - - 0.4 2.4 - - 1.3 VDDIOx–1.3 - - 0.4 VDDIOx–0.4 - - 0.4 V VDDIOx–0.4 - V |IIO| = 20 mA VDDIOx ≥ 2.7 V - 0.4 V |IIO| = 10 mA - 0.4 V TTL port(2) |IIO| = 8 mA VDDIOx ≥ 2.7 V |IIO| = 20 mA VDDIOx ≥ 2.7 V |IIO| = 6 mA VDDIOx ≥ 2 V |IIO| = 4 mA Unit V V V V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Data based on characterization results. Not tested in production. 4. Data based on characterization results. Not tested in production. DocID025004 Rev 5 81/128 99 Electrical characteristics STM32F072x8 STM32F072xB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 24 and Table 55, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 55. I/O AC characteristics(1)(2) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions Min Max Unit - 2 MHz - 125 - 125 - 1 - 125 - 125 - 10 - 25 - 25 - 4 - 62.5 - 62.5 CL = 30 pF, VDDIOx ≥ 2.7 V - 50 CL = 50 pF, VDDIOx ≥ 2.7 V - 30 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 20 CL = 50 pF, VDDIOx < 2 V - 10 CL = 30 pF, VDDIOx ≥ 2.7 V - 5 CL = 50 pF, VDDIOx ≥ 2.7 V - 8 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12 CL = 50 pF, VDDIOx < 2 V - 25 CL = 30 pF, VDDIOx ≥ 2.7 V - 5 CL = 50 pF, VDDIOx ≥ 2.7 V - 8 CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12 CL = 50 pF, VDDIOx < 2 V - 25 fmax(IO)out Maximum frequency(3) x0 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx < 2 V fmax(IO)out Maximum frequency(3) 01 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx < 2 V fmax(IO)out Maximum frequency(3) 11 tf(IO)out tr(IO)out 82/128 Output fall time Output rise time DocID025004 Rev 5 ns MHz ns MHz ns MHz ns MHz ns STM32F072x8 STM32F072xB Electrical characteristics Table 55. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) Fm+ configuration (4) - tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2 V fmax(IO)out Maximum frequency(3) tf(IO)out Output fall time CL = 50 pF, VDDIOx < 2 V tr(IO)out Output rise time tEXTIpw Pulse width of external signals detected by the EXTI controller - Min Max Unit - 2 MHz - 12 - 34 - 0.5 - 16 - 44 10 - ns MHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design, not tested in production. 3. The maximum frequency is defined in Figure 24. 4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration. Figure 24. I/O AC characteristics definition       W I ,2 RXW W U ,2 RXW 7  7DQGLIWKHGXW\F\FOHLV  0D[LPXPIUHTXHQF\LVDFKLHYHGLI WW ” U I  ZKHQORDGHGE\& VHHWKHWDEOH,2$&FKDUDFWHULVWLFVGHILQLWLRQ 069 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 56. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1) VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - - DocID025004 Rev 5 Unit V 83/128 99 Electrical characteristics STM32F072x8 STM32F072xB Table 56. NRST pin characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ VF(NRST) NRST input filtered pulse - - - 100(1) ns 2.7 < VDD < 3.6 300(3) - - 2.0 < VDD < 3.6 (3) - - VNF(NRST) NRST input not filtered pulse 500 ns 1. Data based on design simulation only. Not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 3. Data based on design simulation only. Not tested in production. Figure 25. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW  9'' 538 1567  ,QWHUQDOUHVHW )LOWHU —) 069 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 56: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 6.3.16 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 57. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON - 2.4 - 3.6 V VDDA = 3.3 V - 0.9 - mA - 0.6 - 14 MHz 12-bit resolution 0.043 - 1 MHz IDDA (ADC) Current consumption of the ADC(1) fADC ADC clock frequency fS(2) Sampling rate 84/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Table 57. ADC characteristics (continued) Symbol fTRIG(2) Parameter Conditions Min Typ Max Unit External trigger frequency fADC = 14 MHz, 12-bit resolution - - 823 kHz 12-bit resolution - - 17 1/fADC VAIN Conversion voltage range - 0 - VDDA V RAIN(2) External input impedance See Equation 1 and Table 58 for details - - 50 kΩ RADC(2) Sampling switch resistance - - - 1 kΩ CADC(2) Internal sample and hold capacitor - - - 8 pF tCAL(2)(3) Calibration time WLATENCY(2)(4) tlatr(2) ADC_DR register ready latency fADC = 14 MHz 5.9 µs - 83 1/fADC ADC clock = HSI14 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle fADC = fPCLK/2 = 14 MHz 0.196 µs fADC = fPCLK/2 5.5 1/fPCLK 0.219 µs 10.5 1/fPCLK Trigger conversion latency fADC = fPCLK/4 = 12 MHz fADC = fPCLK/4 JitterADC tS(2) fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs fADC = fHSI14 - 1 - 1/fHSI14 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC ADC jitter on trigger conversion Sampling time tSTAB(2) Stabilization time tCONV(2) Total conversion time (including sampling time) fADC = 14 MHz, 12-bit resolution 12-bit resolution 14 1 - 1/fADC 18 14 to 252 (tS for sampling +12.5 for successive approximation) µs 1/fADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA on IDD should be taken into account. 2. Guaranteed by design, not tested in production. 3. Specified value includes only ADC timing. It does not include the latency of the register access. 4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time. DocID025004 Rev 5 85/128 99 Electrical characteristics STM32F072x8 STM32F072xB Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 58. RAIN max for fADC = 14 MHz Ts (cycles) tS (µs) RAIN max (kΩ)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 59. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ±0.8 ±1.5 ET Total unadjusted error ±3.3 ±4 EO Offset error ±1.9 ±2.8 EG Gain error ±2.8 ±3 ED Differential linearity error ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 ET Total unadjusted error ±3.3 ±4 EO Offset error ±1.9 ±2.8 EG Gain error ±2.8 ±3 ED Differential linearity error ±0.7 ±1.3 EL Integral linearity error ±1.2 ±1.7 fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 3 V to 3.6 V TA = 25 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.7 V to 3.6 V TA = - 40 to 105 °C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.4 V to 3.6 V TA = 25 °C 1. ADC DC accuracy values are measured after internal calibration. 86/128 DocID025004 Rev 5 Unit LSB LSB LSB STM32F072x8 STM32F072xB Electrical characteristics 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. Figure 26. ADC accuracy characteristics 966$ (*    ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH  7KHLGHDOWUDQVIHUFXUYH  (QGSRLQWFRUUHODWLRQOLQH   (7      (2 (/   ('  /6%,'($/              (7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW LGHDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH 9''$ 069 Figure 27. Typical connection diagram using the ADC 9''$ 6DPSOHDQGKROG$'& FRQYHUWHU 97 5$,1  9$,1 5$'& $,1[ 97 &SDUDVLWLF  ,/ “ —$ ELW FRQYHUWHU &$'& 069 1. Refer to Table 57: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DocID025004 Rev 5 87/128 99 Electrical characteristics 6.3.17 STM32F072x8 STM32F072xB DAC electrical specifications Table 60. DAC characteristics Symbol Parameter VDDA Analog supply voltage for DAC ON RLOAD(1) Resistive load with buffer ON RO(1) CLOAD(1) Min Typ Max Unit Comments 2.4 - 3.6 V - 5 - - kΩ Load connected to VSSA 25 - - kΩ Load connected to VDDA Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer ON 0.2 - - V DAC_OUT max(1) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC_OUT max(1) Higher DAC_OUT voltage with buffer OFF - - VDDA – 1LSB V - - 600 µA IDDA(1) DAC DC current consumption in quiescent mode(2) With no load, middle code (0x800) on the input - - 700 µA With no load, worst code (0xF1C) on the input Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration - - ±2 LSB Given for the DAC in 12-bit configuration - - ±1 LSB Given for the DAC in 10-bit configuration - - ±4 LSB Given for the DAC in 12-bit configuration - - ±10 mV - - ±3 LSB Given for the DAC in 10-bit at VDDA = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VDDA = 3.6 V DNL(3) INL(3) Offset(3) 88/128 Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VDDA/2) DocID025004 Rev 5 It gives the maximum output excursion of the DAC. - STM32F072x8 STM32F072xB Electrical characteristics Table 60. DAC characteristics (continued) Symbol Min Typ Max Unit Gain error(3) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration Settling time (full scale: for a 10-bit input code transition (3) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value ±1LSB - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF Update rate(3) Parameter Comments MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1. Guaranteed by design, not tested in production. 2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Figure 28. 12-bit buffered / non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU  5/ ELWGLJLWDO WRDQDORJ FRQYHUWHU '$&B287[ &/ 069 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DocID025004 Rev 5 89/128 99 Electrical characteristics 6.3.18 STM32F072x8 STM32F072xB Comparator characteristics Table 61. Comparator characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit Analog supply voltage - VDD - 3.6 V VIN Comparator input voltage range - 0 - VDDA - VSC VREFINT scaler offset voltage - - ±5 ±10 mV tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - Next activations - - 0.2 Startup time to reach propagation delay specification - - 60 Ultra-low power mode - 2 4.5 Low power mode - 0.7 1.5 Medium power mode - 0.3 0.6 VDDA ≥ 2.7 V - 50 100 VDDA < 2.7 V - 100 240 Ultra-low power mode - 2 7 Low power mode - 0.7 2.1 Medium power mode - 0.3 1.2 VDDA ≥ 2.7 V - 90 180 VDDA < 2.7 V - 110 300 VDDA tSTART Comparator startup time Propagation delay for 200 mV step with 100 mV overdrive High speed mode tD Propagation delay for full range step with 100 mV overdrive High speed mode 1000 (2) ms µs µs ns µs ns Voffset Comparator offset error - - ±4 ±10 mV dVoffset/dT Offset error temperature coefficient - - 18 - µV/°C Ultra-low power mode - 1.2 1.5 Low power mode - 3 5 Medium power mode - 10 15 High speed mode - 75 100 IDD(COMP) 90/128 COMP current consumption DocID025004 Rev 5 µA STM32F072x8 STM32F072xB Electrical characteristics Table 61. Comparator characteristics (continued) Symbol Parameter No hysteresis (COMPxHYST[1:0]=00) Vhys Min(1) Typ Max(1) Conditions Comparator hysteresis - - High speed mode Low hysteresis (COMPxHYST[1:0]=01) All other power modes 3 High speed mode Medium hysteresis (COMPxHYST[1:0]=10) All other power modes 7 High speed mode High hysteresis (COMPxHYST[1:0]=11) All other power modes 18 5 9 19 0 Unit 13 8 10 26 15 mV 19 49 31 40 1. Data based on characterization results, not tested in production. 2. For more details and conditions see Figure 29: Maximum VREFINT scaler startup time from power down. Figure 29. Maximum VREFINT scaler startup time from power down Ϯ͘Ϭsчs  фϮ͘ϰs Ϯ͘ϰsчs  фϯ͘Ϭs ϯ͘Ϭsчs  фϯ͘ϲs ϭϬϬϬ ƚ^ͺ^;ŵĂdžͿ ;ŵƐͿ ϭϬϬ ϭϬ ϭ ͲϰϬ ͲϮϬ Ϭ ϮϬ ϰϬ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ DocID025004 Rev 5 ϲϬ ϴϬ  91/128 99 Electrical characteristics 6.3.19 STM32F072x8 STM32F072xB Temperature sensor characteristics Table 62. TS characteristics Symbol Parameter TL(1) Avg_Slope Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) V30 Average slope (2) Voltage at 30 °C (± 5 °C) tSTART(1) ADC_IN16 buffer startup time - - 10 µs tS_temp(1) ADC sampling time when reading the temperature 4 - - µs 1. Guaranteed by design, not tested in production. 2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3: Temperature sensor calibration values. 6.3.20 VBAT monitoring characteristics Table 63. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 2 x 50 - kΩ Q Ratio on VBAT measurement - 2 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 4 - - µs Er(1) tS_vbat(1) 1. Guaranteed by design, not tested in production. 6.3.21 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 64. TIMx characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT Timer external clock frequency on CH1 to CH4 16-bit timer maximum period tMAX_COUNT 32-bit counter maximum period 92/128 Conditions Min Typ Max Unit - - 1 - tTIMxCLK fTIMxCLK = 48 MHz - 20.8 - ns - - fTIMxCLK/2 - MHz fTIMxCLK = 48 MHz - 24 - MHz - - 216 - tTIMxCLK fTIMxCLK = 48 MHz - 1365 - µs - - 232 - tTIMxCLK fTIMxCLK = 48 MHz - 89.48 - s DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Table 65. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 66. WWDG min/max timeout value at 48 MHz (PCLK) 6.3.22 Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0853 5.4613 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 Unit ms Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: DocID025004 Rev 5 93/128 99 Electrical characteristics STM32F072x8 STM32F072xB Table 67. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 68 for SPI or in Table 69 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 24: General operating conditions. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 68. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Max Master mode - 18 Slave mode - 18 - 6 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 15 pF tsu(NSS) NSS setup time Slave mode 4Tpclk - th(NSS) NSS hold time Slave mode 2Tpclk + 10 - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 Tpclk/2 -2 Tpclk/2 + 1 Master mode 4 - Slave mode 5 - Master mode 4 - Slave mode 5 - Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk Data output disable time Slave mode 0 18 tv(SO) Data output valid time Slave mode (after enable edge) - 22.5 tv(MO) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 11.5 - Master mode (after enable edge) 2 - Slave mode 25 75 tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO)(2) tdis(SO) (3) th(SO) th(MO) DuCy(SCK) Data input setup time Data input hold time Data output hold time SPI slave input clock duty cycle Unit MHz ns ns % 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 94/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics Figure 30. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF 6&. 6&.LQSXW WVX 166 WK 166 WZ 6&.+ WU 6&. &3+$  &32/  &3+$  &32/  WD 62 WZ 6&./ 0,62RXWSXW WY 62 WK 62 )LUVWELW287 WI 6&. 1H[WELWV287 WGLV 62 /DVWELW287 WK 6, WVX 6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 Figure 31. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 &3+$  &32/  &3+$  &32/  0,62RXWSXW WY 62 )LUVWELW287 WVX 6, 026,LQSXW WK 62 1H[WELWV287 WU 6&. WGLV 62 /DVWELW287 WK 6, )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DocID025004 Rev 5 95/128 99 Electrical characteristics STM32F072x8 STM32F072xB Figure 32. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF 6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WZ 6&.+ WZ 6&./ WVX 0, 0,62 ,13 87 WU 6&. WI 6&. %,7,1 06%,1 /6%,1 WK 0, 026, 287387 % , 7287 06%287 WY 02 /6%287 WK 02 DLF 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 69. I2S characteristics(1) Symbol fCK 1/tc(CK) Parameter I2S clock frequency Conditions Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode tr(CK) I2S clock rise time tf(CK) I2S clock fall time Capacitive load CL = 15 pF Min Max 1.597 1.601 0 6.5 - 10 - 12 306 - 312 - tw(CKH) I2S tw(CKL) 2 I S clock low time Master fPCLK= 16 MHz, audio frequency = 48 kHz tv(WS) WS valid time Master mode 2 - th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 7 - th(WS) WS hold time Slave mode 0 - Slave mode 25 75 DuCy(SCK) 96/128 I2S clock high time slave input clock duty cycle DocID025004 Rev 5 Unit MHz ns % STM32F072x8 STM32F072xB Electrical characteristics Table 69. I2S characteristics(1) (continued) Symbol tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Parameter Conditions Data input setup time (2) (2) tv(SD_MT)(2) tv(SD_ST)(2) th(SD_MT) th(SD_ST) Data input hold time Data output valid time Data output hold time Min Max Master receiver 6 - Slave receiver 2 - Master receiver 4 - Slave receiver 0.5 - Master transmitter - 4 Slave transmitter - 20 Master transmitter 0 - Slave transmitter 13 - Unit ns 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns. Figure 33. I2S slave timing diagram (Philips protocol) &.,QSXW WF &. &32/  &32/  WZ &.+ WK :6 WZ &./ :6LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6%WUDQVPLW  06%WUDQVPLW WVX 6'B65 6'UHFHLYH /6%UHFHLYH  WK 6'B67 %LWQWUDQVPLW WK 6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID025004 Rev 5 97/128 99 Electrical characteristics STM32F072x8 STM32F072xB Figure 34. I2S master timing diagram (Philips protocol)   WI &. WU &. &.RXWSXW WF &. &32/  WZ &.+ &32/  WY :6 WK :6 WZ &./ :6RXWSXW WY 6'B07 6'WUDQVPLW /6%WUDQVPLW  06%WUDQVPLW /6%UHFHLYH  /6%WUDQVPLW WK 6'B05 WVX 6'B05 6'UHFHLYH %LWQWUDQVPLW WK 6'B07 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH 06Y9 1. Data based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 98/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Electrical characteristics USB characteristics The STM32F072x8/xB USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 70. USB electrical characteristics Symbol Conditions Min. Typ Max. Unit USB transceiver operating voltage - 3.0(1) - 3.6 V tSTARTUP(2) USB transceiver startup time - - - 1.0 µs RPUI Embedded USB_DP pull-up value during idle - 1.1 1.26 1.5 RPUR Embedded USB_DP pull-up value during reception - ZDRV(2) Output driver impedance(3) VDDIO2 Parameter kΩ Driving high and low 2.0 2.26 2.6 28 40 44 Ω 1. The STM32F072x8/xB USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range. 2. Guaranteed by design, not tested in production. 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. CAN (controller area network) interface Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). DocID025004 Rev 5 99/128 99 Package information 7 STM32F072x8 STM32F072xB Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA100 package information UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array package. Figure 35. UFBGA100 package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( $EDOO $EDOO LGHQWLILHU LQGH[DUHD = H ; ( $ = ' ' H < 0   %277209,(: ‘E EDOOV ‘ HHH 0 = < ; ‘ III 0 = 7239,(: $&B0(B9 1. Drawing is not to scale. Table 71. UFBGA100 package mechanical data inches(1) millimeters Symbol 100/128 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.450 - - 0.0177 - A3 - 0.130 - - 0.0051 0.0094 A4 - 0.320 - - 0.0126 - DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Table 71. UFBGA100 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 6.850 7.000 7.150 0.2697 0.2756 0.2815 D1 - 5.500 - - 0.2165 - E 6.850 7.000 7.150 0.2697 0.2756 0.2815 E1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 36. Recommended footprint for UFBGA100 package 'SDG 'VP $&B)3B9 Table 72. UFBGA100 recommended PCB design rules Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DocID025004 Rev 5 101/128 124 Package information STM32F072x8 STM32F072xB Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 37. UFBGA100 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ 670) ;ϭͿ 9%+ ĂƚĞĐŽĚĞ < :: WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ 5 ZĞǀŝƐŝŽŶĐŽĚĞ D^ϯϱϱϴϱsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 102/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB LQFP100 package information LQFP100 is a100-pin, 14 x 14 mm low-profile quad flat package. Figure 38. LQFP100 package outline PP F $ $ 6($7,1*3/$1( & $ *$8*(3/$1( ' $ . FFF & / ' / '       3,1  ,'(17,),&$7,21 ( ( ( E 7.2 Package information  H /B0(B9 1. Drawing is not to scale. Table 73. LQPF100 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 DocID025004 Rev 5 103/128 124 Package information STM32F072x8 STM32F072xB Table 73. LQPF100 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 39. Recommended footprint for LQFP100 package                DLF 1. Dimensions are expressed in millimeters. 104/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 40. LQFP100 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670) 9%7 5 ZĞǀŝƐŝŽŶĐŽĚĞ ĂƚĞĐŽĚĞ < :: WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ D^ϯϱϱϴϲsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID025004 Rev 5 105/128 124 Package information 7.3 STM32F072x8 STM32F072xB UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array package. Figure 41. UFBGA64 package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < +   %277209,(: ‘E EDOOV ‘ HHH 0 = < ; ‘ III 0 = 7239,(: $B0(B9 1. Drawing is not to scale. Table 74. UFBGA64 package mechanical data inches(1) millimeters Symbol 106/128 Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Table 74. UFBGA64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42. Recommended footprint for UFBGA64 package 'SDG 'VP $B)3B9 Table 75. UFBGA64 recommended PCB design rules Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID025004 Rev 5 107/128 124 Package information STM32F072x8 STM32F072xB Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 43. UFBGA64 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ (65%+ ĂƚĞĐŽĚĞ < :: 5 ĂůůϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ZĞǀŝƐŝŽŶĐŽĚĞ D^ϯϱϱϴϳsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 108/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 44. LQFP64 package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / /      ( ( E ( 7.4 Package information  3,1 ,'(17,),&$7,21   H :B0(B9 1. Drawing is not to scale. Table 76. LQFP64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID025004 Rev 5 109/128 124 Package information STM32F072x8 STM32F072xB Table 76. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45. Recommended footprint for LQFP64 package                 DLF 1. Dimensions are expressed in millimeters. 110/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. LQFP64 package marking example ZĞǀŝƐŝŽŶĐŽĚĞ WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ 5 ;ϭͿ 670) 5%7 ĂƚĞĐŽĚĞ < :: WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ D^ϯϱϱϴϴsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID025004 Rev 5 111/128 124 Package information 7.5 STM32F072x8 STM32F072xB WLCSP49 package information WLCSP49 is a 49-ball, 3.277 x 3.109 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 47. WLCSP49 package outline H EEE = ) $EDOOORFDWLRQ   $ * 'HWDLO$ H ( H * $ $ H %XPSVLGH 6LGHYLHZ $ )URQWYLHZ %XPS ' $ HHH = E 6HDWLQJSODQH ( 'HWDLO$ URWDWHGƒ $RULHQWDWLRQ UHIHUHQFH DDD ; :DIHUEDFNVLGH 1. Drawing is not to scale. 112/128 DocID025004 Rev 5 $;/B0(B9 STM32F072x8 STM32F072xB Package information Table 77. WLCSP49 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.242 3.277 3.312 0.1276 0.1290 0.1304 E 3.074 3.109 3.144 0.1210 0.1224 0.1238 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - F - 0.4385 - - 0.0173 - G - 0.3545 - - 0.0140 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. DocID025004 Rev 5 113/128 124 Package information STM32F072x8 STM32F072xB Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 48. WLCSP49 package marking example WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ )&%< ĂƚĞĐŽĚĞ < ZĞǀŝƐŝŽŶĐŽĚĞ :: 5 D^ϯϱϱϵϭsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 114/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 49. LQFP48 package outline 6($7,1* 3/$1( & F $ $ $ PP *$8*(3/$1( FFF & ' . $ ' / / '      3,1 ,'(17,),&$7,21 ( ( E ( 7.6 Package information    H %B0(B9 1. Drawing is not to scale. DocID025004 Rev 5 115/128 124 Package information STM32F072x8 STM32F072xB Table 78. LQFP48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 50. Recommended footprint for LQFP48 package                    DLG 1. Dimensions are expressed in millimeters. 116/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 51. LQFP48 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670 )&%7 ĂƚĞĐŽĚĞ < :: WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ZĞǀŝƐŝŽŶĐŽĚĞ 5 D^ϯϱϱϴϵsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID025004 Rev 5 117/128 124 Package information 7.7 STM32F072x8 STM32F072xB UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 52. UFQFPN48 package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < '  /  &[ƒ SLQFRUQHU ( 5W\S 'HWDLO=  =  $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 118/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Table 79. UFQFPN48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 53. Recommended footprint for UFQFPN48 package                      $%B)3B9 1. Dimensions are expressed in millimeters. DocID025004 Rev 5 119/128 124 Package information STM32F072x8 STM32F072xB Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 54. UFQFPN48 package marking example WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670) &%8 ĂƚĞĐŽĚĞ < :: WŝŶϭŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ZĞǀŝƐŝŽŶĐŽĚĞ 5 D^ϯϱϱϵϬsϭ 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 120/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB 7.8 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 80. Package thermal characteristics Symbol ΘJA 7.8.1 Parameter Value Thermal resistance junction-ambient UFBGA100 - 7 × 7 mm 55 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm 42 Thermal resistance junction-ambient UFBGA64 - 5 × 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 44 Thermal resistance junction-ambient LQFP48 - 7 × 7 mm 54 Thermal resistance junction-ambient UFQFPN48 - 7 × 7 mm 32 Thermal resistance junction-ambient WLCSP49 - 0.4 mm pitch 49 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.8.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. DocID025004 Rev 5 121/128 124 Package information STM32F072x8 STM32F072xB Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F072x8/xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax= 175 + 272 = 447 mW Using the values obtained in Table 80 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Ordering information). Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 122/128 DocID025004 Rev 5 STM32F072x8 STM32F072xB Package information Using the values obtained in Table 80 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 55 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements. Figure 55. LQFP64 PD max versus TA  3' P:    6XIIL[  6XIIL[          7$ ƒ& DocID025004 Rev 5   06Y9 123/128 124 Ordering information 8 STM32F072x8 STM32F072xB Ordering information For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 81. Ordering information scheme STM32 Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 072 = STM32F072xx Pin count C = 48/49 pins R = 64 pins V = 100 pins User code memory size 8 = 64 Kbyte B = 128 Kbyte Package H = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = –40 to 85 °C 7 = –40 to 105 °C Options xxx = code ID of programmed parts (includes packing type) TR = tape and reel packing blank = tray packing 124/128 DocID025004 Rev 5 F 072 R 8 T 6 x STM32F072x8 STM32F072xB 9 Revision history Revision history Table 82. Document revision history Date Revision 13-Jan-2014 1 Initial release. 2 Updated “Reset and power management“ data in Features. Updated tS_vrefint in Table: Embedded internal reference voltage. Updated VHSEH and VHSEL in Table: High-speed external user clock characteristics. Updated VLSEH and VLSEL in Table: Low-speed external user clock characteristics. Updated tS_temp in Table: TS characteristics. Updated tS_vbat in Table: VBAT monitoring characteristics. Updated Section: I2C interface characteristics. Updated Figure: UFBGA100 package top view and Figure: WLCSP49 package top view. Modified value of ts_sc and removed row VBG in Table: Comparator characteristics. 3 Section 2: Description: – Figure 1: Block diagram - AF number corrected – UFBGA64 package added Section 3: Functional overview: – Table 7: Timer feature comparison - added number of complementary outputs for TIM1, 15, 16 and TIM17 Section 4: Pinouts and pin descriptions: UFBGA64 added Section 5: Memory mapping: – Figure 10: STM32F072xB memory map updated Section 6: Electrical characteristics: – Table 21: Voltage characteristics and Table 22: Current characteristics updated – Table 24: General operating conditions - footnote for VIN – Table 28: Embedded internal reference voltage - tSTART parameter added – Table 31: Typical and maximum consumption in Stop and Standby modes updated – Merger of tables 33 and 34 into Table 33: Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal – Table 37: High-speed external user clock characteristics: replaced VDD with VDDIOX – Table 38: Low-speed external user clock characteristics and Table 40: LSE oscillator characteristics (fLSE = 32.768 kHz): replaced VDD with VDDIOX – Table 41: HSI oscillator characteristics and Figure 19: HSI oscillator accuracy characterization results for soldered parts updated 21-Feb-2014 18-Sep-2015 Changes DocID025004 Rev 5 125/128 127 Revision history STM32F072x8 STM32F072xB Table 82. Document revision history (continued) Date 18-Sep-2015 17-Dec-2015 126/128 Revision Changes 3 (continued) – Table 42: HSI14 oscillator characteristics: changed the min value for ACCHSI14 – Table 46: Flash memory characteristics: removed Vprog – Table 49: EMI characteristics updated – Table 50: ESD absolute maximum ratings updated – Table 57: ADC characteristics - updated some parameter values, test conditions and added footnotes (3) and (4) – Table 60: DAC characteristics - IDDA max value (DAC DC current consumption) updated – Table 61: Comparator characteristics: changed the description and values for tS_SC parameter – Table 62: TS characteristics: changed the min value for tS-temp – Table 63: VBAT monitoring characteristics: changed the typical value for R parameter – Table 69: I2S characteristics: updated the min value for data input hold time (master and slave receiver) Section 7: Package information: – information generally updated, UFBGA64 added Section 8: Part numbering: UFBGA64 added 4 Section 2: Description: – Figure 1: Block diagram updated Section 3: Functional overview: – Figure 2: Clock tree updated Section 4: Pinouts and pin descriptions – Package pinout figures updated (look and feel) – Figure 9: WLCSP49 package pinout - now presented in top view Section 5: Memory mapping: – added information on STM32F072x8 difference versus STM32F072xB map in Figure 10 – Table 28: Embedded internal reference voltage: removed -40°-to-85° condition for VREFINT and associated note Section 6: Electrical characteristics: – Table 61: Comparator characteristics - min value for VDDA replaced with VDD – Figure 29: Maximum VREFINT scaler startup time from power down added – Table 53: I/O static characteristics - note removed – Table 69: I2S characteristics: table reorganized Section 8: Ordering information: – added tray packing to options DocID025004 Rev 5 STM32F072x8 STM32F072xB Revision history Table 82. Document revision history (continued) Date 10-Jan-2017 Revision Changes 5 Section 6: Electrical characteristics: – Table 40: LSE oscillator characteristics (fLSE = 32.768 kHz) - information on configuring different drive capabilities removed. See the corresponding reference manual. – Table 28: Embedded internal reference voltage - VREFINT values – Table 60: DAC characteristics - min. RLOAD to VDDA defined – Figure 30: SPI timing diagram - slave mode and CPHA = 0 and Figure 31: SPI timing diagram - slave mode and CPHA = 1 enhanced and corrected Section 8: Ordering information: – The name of the section changed from the previous “Part numbering” DocID025004 Rev 5 127/128 127 STM32F072x8 STM32F072xB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 128/128 DocID025004 Rev 5
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