STM32F100xC STM32F100xD
STM32F100xE
High-density value line, advanced Arm®-based 32-bit MCU with
256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces
Datasheet −production data
Features
• Core: Arm® 32-bit Cortex®-M3 CPU
– 24 MHz maximum frequency, 1.25 DMIPS
/MHz (Dhrystone 2.1) performance
– Single-cycle multiplication and hardware
division
• Memories
– 256 to 512 Kbytes of Flash memory
– 24 to 32 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Selects. Supports SRAM, PSRAM
and NOR memories
– LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-24 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• Serial wire debug (SWD) and JTAG I/F
• DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs, USARTs and DACs
• 1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)
– Conversion range: 0 to 3.6 V
– Temperature sensor
• 2 × 12-bit D/A converters
• Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
October 2018
This is information on a product in full production.
LQFP144
20 × 20 mm
LQFP100
14 × 14 mm
LQFP64
10 × 10 mm
• Up to 16 timers
– Up to seven 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– One 16-bit, 6-channel advanced-control
timer: up to 6 channels for PWM output,
dead time generation and emergency stop
– One 16-bit timer, with 2 IC/OC, 1
OCN/PWM, dead-time generation and
emergency stop
– Two 16-bit timers, each with
IC/OC/OCN/PWM, dead-time generation
and emergency stop
– Two watchdog timers
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
• Up to 11 communications interfaces
– Up to two I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 UARTs
– Up to 3 SPIs (12 Mbit/s)
– Consumer electronics control (CEC) I/F
• CRC calculation unit, 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32F100xC
STM32F100RC, STM32F100VC,
STM32F100ZC
STM32F100xD
STM32F100RD, STM32F100VD,
STM32F100ZD
STM32F100xE
STM32F100RE, STM32F100VE,
STM32F100ZE
DS5944 Rev 11
1/107
www.st.com
Contents
STM32F100xC, STM32F100xD, STM32F100xE
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2/107
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1
Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 14
2.2.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14
2.2.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.5
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.6
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.7
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
2.2.8
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.10
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.11
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.12
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.13
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.15
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.16
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17
2.2.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.18
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.19
Universal synchronous/asynchronous receiver transmitter (USART) . . 20
2.2.20
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 20
2.2.21
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.22
HDMI (high-definition multimedia interface) consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.23
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.24
Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.25
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.26
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.27
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.28
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Contents
3
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
6
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 40
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.10
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.12
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 69
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.16
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.18
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DS5944 Rev 11
3/107
4
Contents
STM32F100xC, STM32F100xD, STM32F100xE
6.1
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.4.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 102
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High-density STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 46
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DS5944 Rev 11
5/107
6
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
6/107
STM32F100xC, STM32F100xD, STM32F100xE
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LQPF - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
STM32F100 Value Line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F100 Value Line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F100 Value Line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F100 Value Line in LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 57
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 61
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 87
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 87
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP - 144-pin, 20 x 20 mm low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP - 144-pin, 20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LQFP – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 95
LQFP - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98
LQFP - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . 99
DS5944 Rev 11
7/107
8
List of figures
Figure 46.
Figure 47.
8/107
STM32F100xC, STM32F100xD, STM32F100xE
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F100xC, STM32F100xD and STM32F100xE value line microcontrollers. In the
rest of the document, the STM32F100xC, STM32F100xD and STM32F100xE are referred
to as high-density value line devices.
This STM32F100xC, STM32F100xD and STM32F100xE datasheet should be read in
conjunction with the STM32F100xx high-density Arm®-based 32-bit MCUs reference
manual (RM0059). For information on programming, erasing and protection of the internal
Flash memory please refer to the STM32F100xx high-density value line Flash programming
manual (PM0072). The reference and Flash programming manuals are both available from
the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M3 core, please refer to the Cortex®-M3 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS5944 Rev 11
9/107
34
Description
2
STM32F100xC, STM32F100xD, STM32F100xE
Description
The STM32F100 Value Line family incorporates the high-performance Arm® Cortex®-M3
32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash
memory up to 512 Kbytes and SRAM up to 32 Kbytes), a flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive
range of enhanced peripherals and I/Os connected to two APB buses. All devices offer
standard communication interfaces (up to two I2Cs, three SPIs, one HDMI CEC, up to three
USARTs and 2 UARTS), one 12-bit ADC, two 12-bit DACs, up to 9 general-purpose 16-bit
timers and an advanced-control PWM timer.
The STM32F100xx high-density value line family operates in the –40 to +85 °C and –40 to
+105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F100 Value Line family includes devices in three different packages ranging
from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the STM32F100xx value line microcontroller family suitable for a wide
range of applications such as motor drives, application control, medical and handheld
equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs,
inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
10/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
2.1
Description
Device overview
Table 2. STM32F100xx features and peripheral counts
Peripheral
STM32F100Rx
STM32F100Vx
STM32F100Zx
Flash - Kbytes
256
384
512
256
384
512
256
384
512
SRAM - Kbytes
24
32
32
24
32
32
24
32
32
No
Yes(1)
Yes
Advanced-control
1
1
1
General-purpose
10
10
10
SPI
3
3
3
I2C
2
2
2
3
3
3
2
2
2
1
1
1
1
16 channels
1
16 channels
1
16 channels
GPIOs
51
80
112
12-bit DAC
Number of channels
2
2
2
2
2
2
FSMC
Timers
Communication
USART
interfaces
UART
CEC
12-bit synchronized ADC
number of channels
CPU frequency
24 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient operating temperature: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to +125 °C
LQFP64
LQFP100
LQFP144
1. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory.
DS5944 Rev 11
11/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
Figure 1. STM32F100 Value Line block diagram
Ibus
Cortex-M3 CPU
Fmax : 24 MHz
NVIC
GP DMA
Power
VDD18
Voltage reg.
3.3 V to 1.8 V
Flash 512 KB
32 bit
SRAM
32 KB
POR
Reset
Supply
supervision
Int
POR / PDR
@VDDA
RC HS
@VDDA
12 channels
80 AF
EXT.I T
WKUP
PA[15:0]
GPIO port A
PB[15:0]
GPIO port B
PC[15:0]
GPIO port C
PD[15:0]
GPIO port D
@VDD
XTAL OSC
4-24 MHz
PLL
Reset &
clock
control
VSS
NRST
VDDA
VSSA
PVD
RC LS
FSMC
VDD= 2.0 V to 3.6 V
@VDD33
Dbus
System
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[3:0]
NBL[1:0]
NWAIT
NADV
as AF
Trace
controller
pbus
Flash obl
interface
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
JTAG & SW
AHB : F max = 24 MHz
as AF
Bus matrix
TRACECLK
TRACED[0:3]
OSC_IN
OSC_OUT
IWDG
PCLK1
PCLK2
HCLK
FCLK
Standby
interface
VBA T = 1.8
. V to 3.6 V
@VBAT
XTAL 32 kHz
RTC
AWU
Backup
register
OSC32_IN
OSC32_OUT
TAM PER-RTC
(ALARM OUT)
Backup interface
PF[15:0]
GPIO port F
PG[15:0]
GPIO port G
2 channels, 1 compl. channel
and BKIN as AF
TIM15
1 channel, 1 compl. channel
and BKIN as AF
TIM16
1 channel, 1 compl. channel
and BKIN as AF
TIM17
4 channels, 3 compl. channels,
ETR and BKIN as AF
TIM1
MOSI, MISO, SCK, NSS
as AF
RX, TX, CTS, RTS, CK
as AF
16 ADC channels
(ADC_INx)
V
APB1: Fmax = 24 MHz
GPIO port E
AHB2
APB1
APB2: Fmax = 24 MHz
PE[15:0]
AHB2
APB 2
TIM2
4 channels
as AF
TIM3
4 channels
as AF
TIM4
4 channels
as AF
TIM5
4 channels
TIM12
2 channels
as AF
TIM13
1 channel
as AF
TIM14
USART2
USART3
RX,TX, CTS, RTS,
CK as AF
UART4
RX,TX, CTS, RTS,
CK as AF
UART5
RX,TX, CTS, R
CK as AF
SPI1
USART1
Temp sensor
WWDG
12-bit ADC1 IF
SPI2
MOSI, MISO,
SCK, NSS as AF
SPI3
MOSI, MISO,
SCK, NSS as AF
REF+
V
REF–
TIM6
HDMI CEC
@VDDA
TIM7
1 channel
as AF
RX,TX, CTS, RTS,
CK as AF
HDMI CEC as AF
I2C1
SCL, SDA, SMBA as AF
I2C2
SCL, SDA, SMBA as AF
12-bit DAC1
DAC1_OUT as AF
12-bit DAC2
DAC2 _OUT as AF
IF
@VDDA
ai17515b
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C) or TA = –40 °C to +105 °C (junction temperature
up to 125 °C).
12/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Description
Figure 2. Clock tree
&,)4,+
TO&LASHPROGRAMMINGINTERFACE
-(Z
(3)2#
(3)
0ERIPHERALCLOCK
&3-#,+
(#,+
TO!("BUSCORE
MEMORYAND$-!
-(ZMAX
0,,32#
37
0,,-5,
(3)
X
XXX
0,,
393#,+
!("
0RESCALER
-(Z
MAX
0,,#,+
#LOCK
%NABLE
!0"
0RESCALER
(3%
-(Z
!0"
0RESCALER
(3%/3#
/3#?/54
0ERIPHERAL#LOCK
%NABLE
,3%/3#
K(Z
TO24#
,3%
0#,+
TO!0"
PERIPHERALS
TO4)-
4)-X#,+
24##,+
!$#
0RESCALER
0#,+
-(ZMAX
0ERIPHERAL#LOCK
%NABLE
4)-TIMERS
)F!0"PRESCALER X
ELSEX
/3#?).
-(ZMAX
0ERIPHERAL#LOCK
%NABLE
02%$)6
/3#?).
TO#ORTEX3YSTEMTIMER
,+#ORTEX
FREERUNNINGCLOCK
4)-
)F!0"PRESCALER X
ELSEX
#33
/3#?/54
TO&3-#
%NABLE
PERIPHERALSTO!0"
TO4)-4)-
4)-AND4)-
4)-X#,+
0ERIPHERAL#LOCK
%NABLE
TO!$#
!$##,+-(ZMAX
24#3%,;=
,3)2#
K(Z
TOINDEPENDENTWATCHDOG)7$'
,3)
)7$'#,+
-AIN
CLOC KOUT PUT
-#/
0,,#,+
,EGEND
(3%(IGH
SPEEDEXTERNALCLOCKSIGNAL
(3)
(3) (IGH
SPEEDINTERNALCLOCKSIGNAL
(3%
,3),OW
SPEEDINTERNALCLOCKSIGNAL
393#,+
,3%,OW
SPEEDEXTERNALCLOCKSIGNAL
-#/
AI
1. To obtain an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.
DS5944 Rev 11
13/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
2.2
Overview
2.2.1
Arm® Cortex®-M3 core with embedded Flash and SRAM
The Arm Cortex®-M3 processor is the latest generation of Arm processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an Arm core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F100 Value Line family having an embedded Arm core, is therefore compatible
with all Arm tools and software.
2.2.2
Embedded Flash memory
Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.
2.2.3
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.2.4
Embedded SRAM
Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.2.5
FSMC (flexible static memory controller)
The FSMC is embedded in the high-density value line family. It has four Chip Select outputs
supporting the following modes: SRAM, PSRAM, and NOR.
Functionality overview:
2.2.6
•
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
•
No read FIFO
•
Code execution from external memory
•
No boot capability
•
The targeted frequency is HCLK/2, so external access is at 12 MHz when HCLK is at
24 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
14/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Description
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
2.2.7
Nested vectored interrupt controller (NVIC)
The STM32F100 Value Line embeds a nested vectored interrupt controller able to handle
up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3)
and 16 priority levels.
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.2.8
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
2.2.9
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
2.2.10
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
DS5944 Rev 11
15/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.2.11
2.2.12
Power supply schemes
•
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or
DAC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
•
VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.2.13
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
•
MR is used in the nominal regulation mode (Run)
•
LPR is used in the Stop mode
•
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.2.14
Low-power modes
The STM32F100 Value Line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
16/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Description
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.2.15
DMA
The flexible 12-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The two DMA controllers support
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and
ADC.
2.2.16
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.2.17
Timers and watchdogs
The STM32F100xx devices include an advanced-control timer, nine general-purpose
timers, two basic timers and two watchdog timers.
Table 3 compares the features of the advanced-control, general-purpose and basic timers.
DS5944 Rev 11
17/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
Table 3. Timer feature comparison
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request Capture/compare Complementary
generation
channels
outputs
TIM1
16-bit
Up,
down,
up/down
16 bits
Yes
4
Yes
TIM2,
TIM3,
TIM4,
TIM5
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
No
TIM13,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
Yes
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
Yes
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes)
•
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIM2..5, TIM12..17)
There are ten synchronizable general-purpose timers embedded in the STM32F100xx
devices (see Table 3 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
18/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Description
TIM2, TIM3, TIM4, TIM5
STM32F100xx devices feature four synchronizable 4-channel general-purpose timers.
These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM1
advanced-control timer via the Timer Link feature for synchronization or event chaining.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM12 has two independent channels, whereas TIM13 and TIM14 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
Their counters can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
DS5944 Rev 11
19/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
2.2.18
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
I²C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.2.19
Universal synchronous/asynchronous receiver transmitter (USART)
The STM32F100 Value Line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.2.20
Universal asynchronous receiver transmitter (UART)
The STM32F100 Value Line embeds 2 universal asynchronous receiver transmitters
(UART4, and UART5).
The available UART interfaces support IrDA SIR ENDEC, the multiprocessor
communication mode, the single-wire half-duplex communication mode and have LIN
Master/Slave capability.
The UART interfaces can be served by the DMA controller.
2.2.21
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
The SPIs can be served by the DMA controller.
20/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
2.2.22
Description
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware
support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI
standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
2.2.23
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.2.24
Remap capability
This feature allows the use of a maximum number of peripherals in a given application.
Indeed, alternate functions are available not only on the default pins but also on other
specific pins onto which they are remappable. This has the advantage of making board
design and port usage much more flexible.
For details refer to Table 4: High-density STM32F100xx pin definitions; it shows the list of
remappable alternate functions and the pins onto which they can be remapped. See the
STM32F100xx reference manual for software considerations.
2.2.25
ADC (analog-to-digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.2.26
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in noninverting configuration.
DS5944 Rev 11
21/107
34
Description
STM32F100xC, STM32F100xD, STM32F100xE
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
up to 10-bit output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channels’ independent or simultaneous conversions
•
DMA capability for each channel
•
external triggers for conversion
•
input voltage reference VREF+
Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
2.2.27
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.2.28
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
22/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
6$$?
633?
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0'
6$$?
633?
0'
0'
0'
0'
0'
0'
0$
0$
6$$?
633?
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 3. STM32F100 Value Line LQFP144 pinout
,1&0
6$$?
633?
.#
0!
0!
0!
0!
0!
0!
0#
0#
0#
0#
6$$?
633?
0'
0'
0'
0'
0'
0'
0'
0$
0$
6$$?
633?
0$
0$
0$
0$
0$
0$
0"
0"
0"
0"
633?
6$$?
0&
0&
0&
0'
0'
0%
0%
0%
633?
6$$?
0%
0%
0%
0%
0%
0%
0"
0"
633?
6$$?
0%
0%
0%
0%
0%
6"!4
0#
4!-0%2
24#
0#
/3#?).
0#
/3#?/54
0&
0&
0&
0&
0&
0&
633?
6$$?
0&
0&
0&
0&
0&
/3#?).
/3#?/54
.234
0#
0#
0#
0#
633!
62%&
62%&
6$$!
0!
7+50
0!
0!
0!
633?
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
0"
0&
0&
3
Pinouts and pin descriptions
AI
DS5944 Rev 11
23/107
34
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
6$$?
633?
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 4. STM32F100 Value Line LQFP100 pinout
,1&0
6$$?
633?
.#
0!
0!
0!
0!
0!
0!
0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
0"
0"
0!
633?
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
0"
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
0"
633?
6$$?
0%
0%
0%
0%
0%
6"!4
0#
4!-0%2
24#
0#
/3#?).
0#
/3#?/54
633?
6$$?
/3#?).
/3#?/54
.234
0#
0#
0#
0#
633!
62%&
62%&
6$$!
0!
7+50
0!
0!
AI
24/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
sͺϯ
s^^ͺϯ
W ϵ
W ϴ
KK d Ϭ
W ϳ
W ϲ
W ϱ
W ϰ
W ϯ
WϮ
WϭϮ
Wϭϭ
WϭϬ
W ϭϱ
W ϭϰ
Figure 5. STM32F100 Value Line in LQFP64 pinout
ϲϰ ϲϯ ϲϮ ϲϭ ϲϬ ϱϵ ϱϴ ϱϳ ϱϲ ϱϱ ϱϰ ϱϯ ϱϮ ϱϭ ϱϬ ϰϵ
ϰϴ
ϭ
ϰϳ
Ϯ
ϰϲ
ϯ
ϰϱ
ϰ
ϰϰ
ϱ
ϰϯ
ϲ
ϰϮ
ϳ
ϰϭ
ϴ
>Y&Wϲϰ
ϰϬ
ϵ
ϯϵ
ϭϬ
ϯϴ
ϭϭ
ϯϳ
ϭϮ
ϯϲ
ϭϯ
ϯϱ
ϭϰ
ϯϰ
ϭϱ
ϯϯ
ϭϲ
ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ
sͺϮ
s ^^ͺϮ
W ϭϯ
W ϭϮ
W ϭϭ
W ϭϬ
W ϵ
W ϴ
Wϵ
Wϴ
Wϳ
Wϲ
W ϭϱ
W ϭϰ
W ϭϯ
W ϭϮ
W ϯ
s ^^ͺϰ
sͺϰ
W ϰ
W ϱ
W ϲ
W ϳ
Wϰ
Wϱ
W Ϭ
W ϭ
W Ϯ
Wϭ Ϭ
Wϭ ϭ
s ^^ͺϭ
sͺϭ
sd
WϭϯͲdDWZͲZd
W ϭϰͲK ^ ϯϮͺ/E
W ϭϱͲK ^ ϯϮͺKh d
W ϬͲK^ ͺ/E
W ϭͲK^ ͺKhd
EZ^d
WϬ
Wϭ
WϮ
Wϯ
s^^
s
W ϬͲt< hW
W ϭ
W Ϯ
DL
Table 4. High-density STM32F100xx pin definitions
Alternate functions(4)
I/O Level(2)
Remap
LQFP64
Default
LQFP100
Main
function(3)
(after reset)
LQFP144
Type(1)
Pins
Pin name
1
1
-
PE2
I/O FT
PE2
TRACECK/ FSMC_A23
-
2
2
-
PE3
I/O FT
PE3
TRACED0/FSMC_A19
-
3
3
-
PE4
I/O FT
PE4
TRACED1/FSMC_A20
-
4
4
-
PE5
I/O FT
PE5
TRACED2/FSMC_A21
-
5
5
-
PE6
I/O FT
PE6
TRACED3/FSMC_A22
-
6
6
1
VBAT
S
-
VBAT
-
-
7
7
2
PC13-TAMPERRTC(5)
I/O
-
PC13(6)
TAMPER-RTC
-
8
8
3
PC14OSC32_IN(5)
I/O
-
PC14(6)
OSC32_IN
-
9
9
4
PC15OSC32_OUT(5)
I/O
-
PC15(6)
OSC32_OUT
-
10
-
-
PF0
I/O FT
PF0
FSMC_A0
-
11
-
-
PF1
I/O FT
PF1
FSMC_A1
-
12
-
-
PF2
I/O FT
PF2
FSMC_A2
-
13
-
-
PF3
I/O FT
PF3
FSMC_A3
-
DS5944 Rev 11
25/107
34
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
Table 4. High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
I/O Level(2)
Remap
LQFP64
Default
LQFP100
Main
function(3)
(after reset)
LQFP144
Type(1)
Pins
Pin name
14
-
-
PF4
I/O FT
PF4
FSMC_A4
-
15
-
-
PF5
I/O FT
PF5
FSMC_A5
-
16
10
-
VSS_5
S
-
VSS_5
-
-
17
11
-
VDD_5
S
-
VDD_5
-
-
18
-
-
PF6
I/O
-
PF6
-
-
19
-
-
PF7
I/O
-
PF7
-
-
20
-
-
PF8
I/O
-
PF8
-
-
21
-
-
PF9
I/O
-
PF9
-
-
22
-
-
PF10
I/O
-
PF10
-
-
23
12
5
OSC_IN
I
-
OSC_IN
-
PD0(7)
24
13
6
OSC_OUT
O
-
OSC_OUT
-
PD1(7)
25
14
7
NRST
I/O
-
NRST
-
-
26
15
8
PC0
I/O
-
PC0
ADC_IN10
-
27
16
9
PC1
I/O
-
PC1
ADC_IN11
-
28
17
10
PC2
I/O
-
PC2
ADC_IN12
-
29
18
11
PC3
I/O
-
PC3
ADC_IN13
-
30
19
12
VSSA
S
-
VSSA
-
-
31
20
-
VREF-
S
-
VREF-
-
-
32
21
-
VREF+
S
-
VREF+
-
-
33
22
13
VDDA
S
-
VDDA
-
-
PA0
WKUP/USART2_CTS(8)
ADC_IN0
TIM2_CH1_ETR
TIM5_CH1
-
PA1
USART2_RTS(8)
ADC_IN1/
TIM5_CH2/TIM2_CH2(8)
-
-
34
35
23
24
14
15
PA0-WKUP
PA1
I/O
I/O
-
-
36
25
16
PA2
I/O
-
PA2
USART2_TX(8)/TIM5_CH3
ADC_IN2/ TIM15_CH1
TIM2_CH3 (8)
37
26
17
PA3
I/O
-
PA3
USART2_RX(8)/TIM5_CH4
ADC_IN3/TIM2_CH4(8) /
TIM15_CH2
-
38
27
18
VSS_4
S
-
VSS_4
-
-
39
28
19
VDD_4
S
-
VDD_4
-
-
26/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
Table 4. High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
LQFP144
LQFP100
LQFP64
Pin name
Type(1)
I/O Level(2)
Pins
Main
function(3)
(after reset)
40
29
20
PA4
I/O
-
PA4
SPI1_NSS(8)/
USART2_CK(8)
DAC_OUT1/ADC_IN4
-
41
30
21
PA5
I/O
-
PA5
SPI1_SCK(8)
DAC_OUT2/ADC_IN5
-
PA6
SPI1_MISO(8)/
ADC_IN6 /
TIM3_CH1(8)
TIM1_BKIN /
TIM16_CH1
TIM1_CH1N/
TIM17_CH1
42
31
22
PA6
I/O
-
Default
Remap
43
32
23
PA7
I/O
-
PA7
SPI1_MOSI(8)/
ADC_IN7 /
TIM3_CH2(8)
44
33
24
PC4
I/O
-
PC4
ADC_IN14 / TIM12_CH1
-
45
34
25
PC5
I/O
-
PC5
ADC_IN15 / TIM12_CH2
-
46
35
26
PB0
I/O
-
PB0
ADC_IN8/TIM3_CH3
TIM1_CH2N /
TIM13_CH1
47
36
27
PB1
I/O
-
PB1
ADC_IN9/TIM3_CH4(8)
TIM1_CH3N /
TIM14_CH1
48
37
28
PB2
I/O FT
PB2/BOOT1
-
-
49
-
-
PF11
I/O FT
PF11
-
-
50
-
-
PF12
I/O FT
PF12
FSMC_A6
-
51
-
-
VSS_6
S
-
VSS_6
-
-
52
-
-
VDD_6
S
-
VDD_6
-
-
53
-
-
PF13
I/O FT
PF13
FSMC_A7
-
54
-
-
PF14
I/O FT
PF14
FSMC_A8
-
55
-
-
PF15
I/O FT
PF15
FSMC_A9
-
56
-
-
PG0
I/O FT
PG0
FSMC_A10
-
57
-
-
PG1
I/O FT
PG1
FSMC_A11
-
58
38
-
PE7
I/O FT
PE7
FSMC_D4
TIM1_ETR
59
39
-
PE8
I/O FT
PE8
FSMC_D5
TIM1_CH1N
60
40
-
PE9
I/O FT
PE9
FSMC_D6
TIM1_CH1
61
-
-
VSS_7
S
-
VSS_7
-
-
62
-
-
VDD_7
S
-
VDD_7
-
-
63
41
-
PE10
I/O FT
PE10
FSMC_D7
TIM1_CH2N
64
42
-
PE11
I/O FT
PE11
FSMC_D8
TIM1_CH2
65
43
-
PE12
I/O FT
PE12
FSMC_D9
TIM1_CH3N
DS5944 Rev 11
27/107
34
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
Table 4. High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
I/O Level(2)
Remap
LQFP64
Default
LQFP100
Main
function(3)
(after reset)
LQFP144
Type(1)
Pins
Pin name
66
44
-
PE13
I/O FT
PE13
FSMC_D10
TIM1_CH3
67
45
-
PE14
I/O FT
PE14
FSMC_D11
TIM1_CH4
68
46
-
PE15
I/O FT
PE15
FSMC_D12
TIM1_BKIN
69
47
29
PB10
I/O FT
PB10
I2C2_SCL/USART3_TX(8)
TIM2_CH3 /
HDMI_CEC
70
48
30
PB11
I/O FT
PB11
I2C2_SDA/USART3_RX(8)
TIM2_CH4
71
49
31
VSS_1
S
-
VSS_1
-
-
72
50
32
VDD_1
S
-
VDD_1
-
-
TIM12_CH1
73
51
33
PB12
I/O FT
PB12
SPI2_NSS/
I2C2_SMBA/
USART3_CK(8)/
TIM1_BKIN(8)
74
52
34
PB13
I/O FT
PB13
SPI2_SCK/
USART3_CTS(8)/
TIM1_CH1N
TIM12_CH2
75
53
35
PB14
I/O FT
PB14
SPI2_MISO/TIM1_CH2N
USART3_RTS(8)/
TIM15_CH1
76
54
36
PB15
I/O FT
PB15
SPI2_MOSI/
TIM1_CH3N(8)/
TIM15_CH1N
TIM15_CH2
77
55
-
PD8
I/O FT
PD8
FSMC_D13
USART3_TX
78
56
-
PD9
I/O FT
PD9
FSMC_D14
USART3_RX
79
57
-
PD10
I/O FT
PD10
FSMC_D15
USART3_CK
80
58
-
PD11
I/O FT
PD11
FSMC_A16
USART3_CTS
81
59
-
PD12
I/O FT
PD12
FSMC_A17
TIM4_CH1 /
USART3_RTS
82
60
-
PD13
I/O FT
PD13
FSMC_A18
TIM4_CH2
83
-
-
VSS_8
S
-
VSS_8
-
-
84
-
-
VDD_8
S
-
VDD_8
-
-
85
61
-
PD14
I/O FT
PD14
FSMC_D0
TIM4_CH3
86
62
-
PD15
I/O FT
PD15
FSMC_D1
TIM4_CH4
87
-
-
PG2
I/O FT
PG2
FSMC_A12
-
88
-
-
PG3
I/O FT
PG3
FSMC_A13
-
89
-
-
PG4
I/O FT
PG4
FSMC_A14
-
90
-
-
PG5
I/O FT
PG5
FSMC_A15
-
28/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
Table 4. High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
I/O Level(2)
Remap
LQFP64
Default
LQFP100
Main
function(3)
(after reset)
LQFP144
Type(1)
Pins
Pin name
91
-
-
PG6
I/O FT
PG6
-
-
92
-
-
PG7
I/O FT
PG7
-
-
93
-
-
PG8
I/O FT
PG8
-
-
94
-
-
VSS_9
S
-
VSS_9
-
-
95
-
-
VDD_9
S
-
VDD_9
-
-
96
63
37
PC6
I/O FT
PC6
-
TIM3_CH1
97
64
38
PC7
I/O FT
PC7
-
TIM3_CH2
98
65
39
PC8
I/O FT
PC8
TIM13_CH1
TIM3_CH3
99
66
40
PC9
I/O FT
PC9
TIM14_CH1
TIM3_CH4
100
67
41
PA8
I/O FT
PA8
USART1_CK/
TIM1_CH1(8)/MCO
-
101
68
42
PA9
I/O FT
PA9
USART1_TX(8)/
TIM1_CH2(8) / TIM15_BKIN
-
102
69
43
PA10
I/O FT
PA10
USART1_RX(8)/
TIM1_CH3(8) / TIM17_BKIN
-
103
70
44
PA11
I/O FT
PA11
USART1_CTS / TIM1_CH4(8)
-
TIM1_ETR(8)
-
104
71
45
PA12
I/O FT
PA12
USART1_RTS /
105
72
46
PA13
I/O FT
JTMS-SWDIO
106
73
-
107
74
47
VSS_2
S
-
VSS_2
-
-
108
75
48
VDD_2
S
-
VDD_2
-
-
109
76
49
PA14
I/O FT JTCK-SWCLK
-
-
110
77
50
PA15
I/O FT
JTDI
SPI3_NSS
TIM2_CH1_ETR /
SPI1_NSS
111
78
51
PC10
I/O FT
PC10
UART4_TX
USART3_TX
112
79
52
PC11
I/O FT
PC11
UART4_RX
USART3_RX
113
80
53
PC12
I/O FT
PC12
UART5_TX
USART3_CK
-
-
Not connected
-
114
81
-
PD0
I/O FT
PD0
FSMC_D2(9)
115
82
-
PD1
I/O FT
PD1
FSMC_D3(9)
-
116
83
54
PD2
I/O FT
PD2
TIM3_ETR/UART5_RX
-
117
84
-
PD3
I/O FT
PD3
FSMC_CLK
USART2_CTS
118
85
-
PD4
I/O FT
PD4
FSMC_NOE
USART2_RTS
119
86
-
PD5
I/O FT
PD5
FSMC_NWE
USART2_TX
DS5944 Rev 11
29/107
34
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
Table 4. High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
LQFP144
LQFP100
LQFP64
Pin name
Type(1)
I/O Level(2)
Pins
Main
function(3)
(after reset)
120
-
-
VSS_10
S
-
VSS_10
-
-
121
-
-
VDD_10
S
-
VDD_10
-
-
122
87
-
PD6
I/O FT
PD6
FSMC_NWAIT
USART2_RX
123
88
-
PD7
I/O FT
PD7
FSMC_NE1
USART2_CK
124
-
-
PG9
I/O FT
PG9
FSMC_NE2
-
125
-
-
PG10
I/O FT
PG10
FSMC_NE3
-
126
-
-
PG11
I/O FT
PG11
-
-
127
-
-
PG12
I/O FT
PG12
FSMC_NE4
-
128
-
-
PG13
I/O FT
PG13
FSMC_A24
-
129
-
-
PG14
I/O FT
PG14
FSMC_A25
-
130
-
-
VSS_11
S
-
VSS_11
-
-
131
-
-
VDD_11
S
-
VDD_11
-
-
132
-
-
PG15
I/O FT
PG15
-
-
133
89
55
PB3/
I/O FT
JTDO
SPI3_SCK
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
134
90
56
PB4
I/O FT
NJTRST
SPI3_MISO
TIM3_CH1
SPI1_MISO
135
91
57
PB5
I/O
PB5
I2C1_SMBA/ SPI3_MOSI
TIM16_BKIN
TIM3_CH2 /
SPI1_MOSI
136
92
58
PB6
I/O FT
PB6
I2C1_SCL(8)/ TIM4_CH1(8) /
TIM16_CH1N
USART1_TX
137
93
59
PB7
I/O FT
PB7
I2C1_SDA(8) / FSMC_NADV /
TIM4_CH2(8) / TIM17_CH1N
USART1_RX
138
94
60
BOOT0
-
-
I
-
-
BOOT0
Default
Remap
TIM4_CH3(8)/TIM16_CH1
/
139
95
61
PB8
I/O FT
PB8
140
96
62
PB9
I/O FT
PB9
TIM4_CH4(8)/ TIM17_CH1
I2C1_SDA
141
97
-
PE0
I/O FT
PE0
TIM4_ETR / FSMC_NBL0
-
142
98
-
PE1
I/O FT
PE1
FSMC_NBL1
-
143
99
63
VSS_3
S
-
VSS_3
-
-
144 100 64
VDD_3
S
-
VDD_3
-
-
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
30/107
DS5944 Rev 11
HDMI_CEC
I2C1_SCL
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F100xx reference manual, available from the
STMicroelectronics website: www.st.com.
7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F100xx reference manual.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F100xx reference manual, available
from the STMicroelectronics website: www.st.com.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
Table 5. FSMC pin definition
FSMC
LQFP100(1)
Pins
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PE2
A23
A23
Yes
PE3
A19
A19
Yes
PE4
A20
A20
Yes
PE5
A21
A21
Yes
PE6
A22
A22
Yes
PF0
A0
-
-
PF1
A1
-
-
PF2
A2
-
-
PF3
A3
-
-
PF4
A4
-
-
PF5
A5
-
-
PF6
-
-
-
PF7
-
-
-
PF8
-
-
-
PF9
-
-
-
PF10
-
-
-
PF11
-
-
-
PF12
A6
-
-
PF13
A7
-
-
PF14
A8
-
-
PF15
A9
-
-
DS5944 Rev 11
31/107
34
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
Table 5. FSMC pin definition (continued)
FSMC
LQFP100(1)
Pins
32/107
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PG0
A10
-
-
PG1
A11
-
-
PE7
D4
DA4
Yes
PE8
D5
DA5
Yes
PE9
D6
DA6
Yes
PE10
D7
DA7
Yes
PE11
D8
DA8
Yes
PE12
D9
DA9
Yes
PE13
D10
DA10
Yes
PE14
D11
DA11
Yes
PE15
D12
DA12
Yes
PD8
D13
DA13
Yes
PD9
D14
DA14
Yes
PD10
D15
DA15
Yes
PD11
A16
A16
Yes
PD12
A17
A17
Yes
PD13
A18
A18
Yes
PD14
D0
DA0
Yes
PD15
D1
DA1
Yes
PG2
A12
-
-
PG3
A13
-
-
PG4
A14
-
-
PG5
A15
-
-
PG6
-
-
-
PG7
-
-
-
PD0
D2
DA2
Yes
PD1
D3
DA3
Yes
PD3
CLK
CLK
Yes
PD4
NOE
NOE
Yes
PD5
NWE
NWE
Yes
PD6
NWAIT
NWAIT
Yes
PD7
NE1
NE1
Yes
PG9
NE2
NE2
-
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
Table 5. FSMC pin definition (continued)
FSMC
LQFP100(1)
Pins
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PG10
NE3
NE3
-
PG11
-
-
-
PG12
NE4
NE4
-
PG13
A24
A24
-
PG14
A25
A25
-
PB7
NADV
NADV
Yes
PE0
NBL0
NBL0
Yes
PE1
NBL1
NBL1
Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
DS5944 Rev 11
33/107
34
Memory mapping
4
STM32F100xC, STM32F100xD, STM32F100xE
Memory mapping
The memory map is shown in Figure 6.
Figure 6. Memory map
APB memory space
0xFFFF FFFF
0x4002 3400
0x4002 3000
0x4002 2400
0xFFFF FFFF
7
0xE010 0000
0xE000 0000
Flash interface
0x4002 1400
reserved
0x4002 1000
RCC
0x4002 0400
DMA2
0x4001 4C00
0x4001 4800
0x4001 4400
6
CRC
reserved
0x4002 2000
0x4002 0000
Cortex-M3 internal
peripherals
reserved
0x4001 4000
DMA1
reserved
TIM17
TIM16
TIM15
reserved
0x4001 3C00
0xC000 0000
0x4001 3800
0x4001 3400
0x4001 3000
5
0x4001 2C00
0xA000 0000
FSMC regs
0x4001 2800
0x4001 2400
0x4001 2000
4
0x1FFF FFFF
reserved
0x1FFF F80F
0x8000 0000
Option Bytes
0x1FFF F800
3
0x7000 0000
0x6000 0000
System memory
FSMC
external
memory
0x1FFF F000
0x4000 0000
reserved
0x4001 1000
Port C
0x4001 0C00
Port B
0x4001 0800
Port A
0x4001 0400
EXTI
0x4001 0000
AFIO
0x4000 7C00
reserved
0x4000 7000
0x4000 5800
SRAM
Flash memory
0x0000 0000
Reserved
Aliased to Flash or
system memory
depending on
0x0000 0000
BOOT pins
BKP
I2C2
reserved
I2C1
UART5
UART4
0x4000 4400
0x4000 3C00
0x0800 0000
PWR
0x4000 5400
0x4000 4800
0
CEC
DAC
0x4000 5000
0x4000 4C00
0x0801 FFFF
Port G
Port F
Port E
0x4000 5C00
0x2000 0000
ADC1
Port D
0x4000 6C00
1
TIM1
reserved
0x4001 1400
0x4000 7400
Peripherals
SPI1
0x4001 1C00
0x4001 1800
0x4000 7800
2
USART1
reserved
0x4000 3800
0x4000 3400
USART3
USART2
SPI3
SPI2
reserved
0x4000 3000
IWDG
0x4000 2C00
WWDG
0x4000 2800
0x4000 2000
0x4000 1C00
0x4000 1800
0x4000 1400
0x4000 1000
RTC
TIM14
TIM13
TIM12
TIM7
TIM6
0x4000 0C00
TIM5
0x4000 0800
TIM4
0x4000 0400
TIM3
0x4000 0000
TIM2
ai18400
34/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
5
Electrical characteristics
5.1
Parameter conditions
Electrical characteristics
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
DS5944 Rev 11
35/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 7. Pin loading conditions
Figure 8. Pin input voltage
STM32F10xxx pin
STM32F10xxx pin
C = 50 pF
VIN
ai14123b
ai14124b
5.1.6
Power supply scheme
Figure 9. Power supply scheme
9%$7
%DFNXSFLUFXLWU\
26&.57&
:DNHXSORJLF
%DFNXSUHJLVWHUV
287
*3 ,2V
,1
/HYHOVKLIWHU
3R ZHU VZL WFK
9
,2
/RJLF
.HUQHOORJLF
&38
'LJLWDO
0HPRULHV
9''
9''
îQ)
î)
9''
9''$
95()
Q)
)
5HJXODWRU
966
Q)
)
95()
95()
!$#$!#
$QDORJ
5&V3//
966$
AIE
Caution:
36/107
In Figure 9, the 4.7 µF capacitor must be connected to VDD3.
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
5.1.7
Electrical characteristics
Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,
Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 6. Voltage characteristics
Symbol
VDD −VSS
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin
VSS −0.3
VDD +4.0
Input voltage on any other pin
VSS − 0.3
4.0
Variations between different VDD power pins
-
50
Variations between all the different ground
pins
-
50
External main supply voltage (including
VDDA and VDD)(1)
Electrostatic discharge voltage (human body
model)
see Section 5.3.12: Absolute
maximum ratings (electrical
sensitivity)
Unit
V
mV
-
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 7: Current characteristics for the maximum
allowed injected current values.
DS5944 Rev 11
37/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 7. Current characteristics
Symbol
IVDD
IVSS
IIO
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
150
(1)
Total current out of VSS ground lines (sink)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
−25
(3)
IINJ(PIN)(2)
ΣIINJ(PIN)
Unit
Injected current on five volt tolerant pins
mA
-5 / +0
(4)
±5
Injected current on any other pin
Total injected current (sum of all I/O and control pins)
(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See Note: on page 85.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 8 MHz.
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
External clock (2), all
peripherals enabled
External clock(2) all
peripherals disabled
IDD
Supply current
in Run mode
HSI clock(2), all
peripherals enabled
HSI clock(2), all
peripherals disabled
fHCLK
Unit
TA = 85 °C
TA = 105 °C
24 MHz
18.5
19
16 MHz
13.1
13.5
8 MHz
7.3
7.6
24 MHz
10.9
11.5
16 MHz
7.3
7.7
8 MHz
4.8
5.2
24 MHz
17.2
17.2
16 MHz
11.7
11.8
8 MHz
8.9
9
24 MHz
8.1
8.3
16 MHz
5.6
5.8
8 MHz
4.3
4.5
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.
42/107
DS5944 Rev 11
mA
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 15. STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2) all
peripherals enabled
External clock(2), all
peripherals disabled
IDD
Supply current
in Sleep mode
HSI clock(2), all
peripherals enabled
HSI clock(2), all
peripherals disabled
fHCLK
Unit
TA = 85 °C
TA = 105 °C
24 MHz
14.1
14.3
16 MHz
9.7
10.3
8 MHz
5.9
6.2
24 MHz
4.2
4.6
16 MHz
3.7
4.1
8 MHz
2.9
3.4
24 MHz
12.5
12.7
16 MHz
8.2
8.5
8 MHz
6.4
6.6
24 MHz
2.3
2.5
16 MHz
1.7
2
8 MHz
1.4
1.7
mA
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.
DS5944 Rev 11
43/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 16. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
Parameter
Conditions
VDD/VBAT VDD/ VBAT VDD/VBAT TA =
TA =
= 2.0 V
= 2.4 V
= 3.3 V 85 °C 105 °C
Regulator in Run mode,
Low-speed and high-speed
internal RC oscillators and
high-speed oscillator OFF (no
Supply current independent watchdog)
in Stop mode Regulator in Low-Power mode,
Low-speed and high-speed
internal RC oscillators and
high-speed oscillator OFF (no
independent watchdog)
IDD
Max
Low-speed internal RC
oscillator and independent
watchdog ON
Low-speed internal RC
Supply current
oscillator ON, independent
in Standby
watchdog OFF
mode
Low-speed internal RC
oscillator and independent
watchdog OFF, low-speed
oscillator and RTC OFF
Backup
Low-speed oscillator and RTC
IDD_VBAT domain supply
ON
current
-
-
31
320
670
-
-
24
305
650
-
-
3.2
-
-
-
-
3.1
-
-
-
-
2.2
3.9
5.7
1.0
1.2
1.4
2
2.3
1. Typical values are measured at TA = 25 °C.
Typical current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except if it is explicitly mentioned
•
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Table 17 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
44/107
DS5944 Rev 11
Unit
µA
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Typical values(1)
Symbol Parameter
Conditions
Running on high-speed
external clock with an
8 MHz crystal(3)
IDD
Supply
current in
Run mode
Running on high-speed
internal RC (HSI)
fHCLK
All peripherals All peripherals
enabled(2)
disabled
24 MHz
14.1
9.5
16 MHz
10
6.85
8 MHz
5.8
4.05
4 MHz
3.6
2.65
2 MHz
2.3
1.85
1 MHz
1.7
1.46
500 kHz
1.4
1.3
125 kHz
1.15
1.1
24 MHz
13.4
8.7
16 MHz
9.3
6.2
8 MHz
5.2
3.45
4 MHz
2.95
2.1
2 MHz
1.7
1.3
1 MHz
1.1
0.9
500 kHz
0.8
0.7
125 kHz
0.6
0.55
Unit
mA
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK < 8 MHz, the PLL is used when fHCLK > 8 MHz.
DS5944 Rev 11
45/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typical values(1)
Symbol Parameter
Conditions
Running on high-speed
external clock with an
8 MHz crystal(3)
IDD
Supply
current in
Sleep
mode
Running on high-speed
internal RC (HSI)
fHCLK
All peripherals All peripherals
enabled(2)
disabled
24 MHz
8.7
2.75
16 MHz
6.1
2.1
8 MHz
3.3
1.3
4 MHz
2.25
1.2
2 MHz
1.65
1.15
1 MHz
1.35
1.1
500 kHz
1.2
1.07
125 kHz
1.1
1.05
24 MHz
8
2.15
16 MHz
5.5
1.5
8 MHz
2.7
0.75
4 MHz
1.65
0.6
2 MHz
1.1
0.55
1 MHz
0.8
0.5
500 kHz
0.65
0.49
125 kHz
0.53
0.47
Unit
mA
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK > 8 MHz, the PLL is used when fHCLK > 8 MHz.
46/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
•
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 6.
Table 19. Peripheral current consumption
Peripheral
AHB (up to 24MHz)
Typical consumption at 25 °C
DMA1
12.50
DMA2
8.33
FSMC
28.33
CRC
Unit
µA/MHz
1.25
BusMatrix
(1)
DS5944 Rev 11
16.67
47/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 19. Peripheral current consumption (continued)
Peripheral
APB1 (up to 24 MHz)
Typical consumption at 25 °C
APB1-Bridge
3.75
TIM2
17.08
TIM3
17.50
TIM4
17.08
TIM5
17.08
TIM6
4.58
TIM7
4.17
TIM12
10.42
TIM13
7.08
TIM14
7.08
SPI2/I2S2
4.58
SPI3/I2S3
4.58
USART2
12.08
USART3
12.08
UART4
11.25
UART5
10.83
I2C1
10.42
I2C2
10.42
CEC
5.42
(2)
48/107
DAC
7.92
WWDG
2.92
PWR
1.25
BKP
2.08
IWDG
3.33
DS5944 Rev 11
Unit
µA/MHz
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 19. Peripheral current consumption (continued)
Peripheral
APB2 (up to 24 MHz)
Typical consumption at 25 °C
APB2-Bridge
4.17
GPIOA
6.67
GPIOB
6.25
GPIOC
6.67
GPIOD
6.67
GPIOE
6.67
GPIOF
5.42
GPIOG
6.67
SPI1
4.17
USART1
12.08
TIM1
22.08
TIM15
14.17
TIM16
10.00
TIM17
10.00
(3)
ADC1
1.
Unit
µA/MHz
15.83
The BusMatrix is automatically active when at least one master is ON.(CPU, DMA1 or DMA2).
2. When DAC_OUT1 or DAC_OUT2 is enabled, there is an additional current consumption equal to 0,42 mA
3. Specific conditions for measuring ADC current consumption: fHCLK = 24 MHz, fAPB1 = fHCLK, fAPB2 = fHCLK,
fADCCLK = fAPB2/2. When ADON bit in the ADC_CR2 register is set to 1, a current consumption of analog
part equal to 0.82 mA must be added.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.
DS5944 Rev 11
49/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 20. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
fHSE_ext
User external clock source
frequency(1)
1
8
24
VHSEH
OSC_IN input pin high level
voltage(1)
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level
voltage(1)
VSS
-
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
5
-
-
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1)
-
-
20
-
-
5
-
pF
-
45
-
55
%
VSS ≤VIN ≤VDD
-
-
±1
µA
Cin(HSE)
ns
OSC_IN input capacitance(1)
DuCy(HSE) Duty
IL
V
-
cycle(1)
OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.
Table 21. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
-
32.768
1000
kHz
-
VDD
fLSE_ext
User external clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage(1)
0.7VDD
VLSEL
OSC32_IN input pin low level
voltage(1)
VSS
-
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
-
-
tr(LSE)
tf(LSE)
Cin(LSE)
IL
V
ns
OSC32_IN rise or fall
time(1)
OSC32_IN input capacitance(1)
DuCy(LSE) Duty
cycle(1)
OSC32_IN Input leakage current
VSS ≤VIN ≤VDD
1. Guaranteed by design, not tested in production.
50/107
Min
DS5944 Rev 11
-
-
50
-
5
-
pF
30
-
70
%
-
-
±1
µA
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 11. High-speed external clock source AC timing diagram
9+6(+
9+6(/
WU+6(
W
W:+6(
W:+6(
7+6(
I+6(BH[W
([WHUQDOFORFNVRXUFH
,/
26&B,1
670)[[[
DLE
Figure 12. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
External
clock source
fLSE_ext
STM32F10xxx
ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 22. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 22. HSE 4-24 MHz oscillator characteristics(1)(2)
Symbol
fOSC_IN
RF
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator frequency
-
4
8
24
MHz
Feedback resistor
-
-
200
-
kΩ
DS5944 Rev 11
51/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 22. HSE 4-24 MHz oscillator characteristics(1)(2)
Symbol
Parameter
CL1
CL2(3)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(4)
i2
gm
tSU(HSE)
(5)
Conditions
Min
Typ
Max
Unit
RS = 30 Ω
-
30
-
pF
HSE driving current
VDD = 3.3 V
VIN = VSS with 30 pF
load
-
-
1
mA
Oscillator transconductance
Startup
25
-
-
mA/V
Startup time
VDD is stabilized
-
2
-
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 13. Typical application with an 8 MHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
0+ ]
UHVRQDWRU
&/
I+6(
26&B,1
5(;7
5)
26&B28 7
%LDV
FRQWUROOHG
JDLQ
670)[[[
DLE
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 23. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Note:
52/107
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
For further details, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Conditions
Min
Typ
Max
Unit
-
-
5
-
MΩ
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 KΩ
-
-
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
-
-
1.4
µA
gm
Oscillator transconductance
-
5
-
-
µA/V
TA = 50 °C
-
1.5
-
TA = 25 °C
-
2.5
-
TA = 10 °C
-
4
-
TA = 0 °C
-
6
-
TA = -10 °C
-
10
-
TA = -20 °C
-
17
-
TA = -30 °C
-
32
-
TA = -40 °C
-
60
-
RF
CL1
CL2(2)
tSU(LSE)(4)
Parameter
Feedback resistor
Startup time
VDD is
stabilized
s
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs above the table.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for
example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
DS5944 Rev 11
53/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 14. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
I/6(
26&B,1
.+ ]
UHVRQDWRU
%LDV
FRQWUROOHG
JDLQ
5)
670)[[[
26&B28 7
&/
DLE
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator
Table 24. HSI oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
8
-
MHz
-2.4
-
2.5
%
-2.2
-
1.3
%
-1.9
-
1.3
%
TA = 25 °C
-1
-
1
%
Frequency
fHSI
TA = –40 to 105
ACCHSI
tsu(HSI)
Accuracy of HSI oscillator
TA = –10 to 85
TA = 0 to 70
°C(2)
°C(2)
°C(2)
(3)
HSI oscillator startup time
-
1
-
2
µs
(3)
HSI oscillator power consumption
-
-
80
100
µA
IDD(HSI)
1. VDD = 3.3 V, TA = –40 to 105 °C °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design. Not tested in production
Low-speed internal (LSI) RC oscillator
Table 25. LSI oscillator characteristics (1)
Symbol
Min
Typ
Max
Unit
30
40
60
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.65
1.2
µA
Frequency
fLSI
tsu(LSI)(2)
IDD(LSI)
Parameter
(2)
1. VDD = 3 V, TA = –40 to 105 °C °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
54/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 26 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
•
Stop or Standby mode: the clock source is the RC oscillator
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 9.
Table 26. Low-power mode wakeup timings
Symbol
tWUSLEEP
Parameter
(1)
tWUSTOP(1)
tWUSTDBY(1)
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low-power mode)
5.4
Wakeup from Standby mode
50
µs
µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
Table 27. PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
24
MHz
PLL input clock duty cycle
40
-
60
%
fPLL_OUT
PLL multiplier output clock
16
-
24
MHz
tLOCK
PLL lock time
-
-
200
µs
Jitter
Cycle-to-cycle jitter
-
-
300
ps
fPLL_IN
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
DS5944 Rev 11
55/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 28. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
tprog
16-bit programming time
TA = –40 to +105 °C
40
52.5
70
µs
tERASE
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
Read mode
fHCLK = 24 MHz, VDD = 3.3 V
-
-
20
mA
Write / Erase modes
fHCLK = 24 MHz, VDD = 3.3 V
-
-
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
-
-
50
µA
2
-
3.6
V
tME
IDD
Vprog
Supply current
Programming voltage
-
1. Guaranteed by design, not tested in production.
Table 29. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Conditions
Unit
Min(1)
Typ
Max
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
-
-
1 kcycle(2) at TA = 85 °C
30
-
-
at TA = 105 °C
10
-
-
(2)
20
-
-
Data retention 1
kcycle(2)
10 kcycles
at TA = 55 °C
kcycles
Years
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
FSMC characteristics
Asynchronous waveforms and timings
Figure 15 through Figure 18 represent asynchronous waveforms and Table 30 through
Table 33 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
56/107
•
AddressSetupTime = 0
•
AddressHoldTime = 1
•
DataSetupTime = 1
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
)60&B1(
W Y12(B1(
W Z12(
W K1(B12(
)60&B12(
)60&B1:(
WY$B1(
)60&B$>@
W K$B12(
$GGUHVV
WY%/B1(
W K%/B12(
)60&B1%/>@
W K'DWDB1(
W VX'DWDB12(
WK'DWDB12(
W VX'DWDB1(
'DWD
)60&B'>@
W Y1$'9B1(
WZ1$'9
)60&B1$'9
069
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
DS5944 Rev 11
57/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2)
Symbol
Parameter
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1.5
5THCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
0.5
1.5
ns
tw(NOE)
FSMC_NOE low time
5THCLK – 1.5
5THCLK + 1.5
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time –1.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
th(A_NOE)
Address hold time after FSMC_NOE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
-
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
2THCLK + 25
-
ns
2THCLK + 25
-
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
-
0
0.1
ns
-
-
0
ns
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
5
ns
tw(NADV)
FSMC_NADV low time
-
THCLK + 1.5
ns
1. CL = 15 pF.
2. Preliminary values.
58/107
Min
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FSMC_NBL[3:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3THCLK – 1
3THCLK + 2
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
THCLK – 0.5
THCLK + 1.5
ns
tw(NWE)
FSMC_NWE low time
THCLK – 0.5
THCLK + 1.5
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK
tv(A_NE)
FSMC_NEx low to FSMC_A valid
th(A_NWE)
Address hold time after FSMC_NWE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NE)
FSMC_NEx low to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
5.5
ns
tw(NADV)
FSMC_NADV low time
-
THCLK + 1.5
ns
-
7.5
THCLK
ns
-
-
1.5
THCLK – 0.5
-
ns
ns
THCLK + 7
THCLK
ns
-
ns
ns
ns
1. CL = 15 pF.
2. Preliminary values.
DS5944 Rev 11
59/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms
TW.%
&3-#?.%
TV./%?.%
T H.%?./%
&3-#?./%
T W./%
&3-#?.7%
TV!?.%
&3-#?!;=
T H!?./%
!DDRESS
TV",?.%
TH",?./%
&3-#?.",;=
.",
TH$ATA?.%
TSU$ATA?.%
T V!?.%
TSU$ATA?./%
!DDRESS
&3-#? !$;=
T V.!$6?.%
TH$ATA?./%
$ATA
TH!$?.!$6
TW.!$6
&3-#?.!$6
AIB
Table 32. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
Parameter
Max
Unit
tw(NE)
FSMC_NE low time
7THCLK – 2
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
3THCLK – 0.5 3THCLK + 1.5
ns
tw(NOE)
FSMC_NOE low time
4THCLK – 1
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
–1
tv(A_NE)
FSMC_NEx low to FSMC_A valid
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
tw(NADV)
7THCLK + 2
4THCLK + 2
-
ns
ns
3
5
ns
FSMC_NADV low time
THCLK –1.5
THCLK + 1.5
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
THCLK
-
ns
th(A_NOE)
Address hold time after FSMC_NOE high
THCLK
-
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
tsu(Data_NE)
Data to FSMC_NEx high setup time
2THCLK + 24
-
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
2THCLK + 25
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
2. Preliminary values.
DS5944 Rev 11
-
ns
0
1. CL = 15 pF.
60/107
Min
0
ns
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms
WZ1(
)60&B1([
)60&B12(
WY1:(B1(
WZ1:(
W K1(B1:(
)60&B1:(
WK$B1:(
WY$B1(
)60&B$>@
$GGUHVV
WY%/B1(
WK%/B1:(
)60&B1%/>@
1%/
W Y$B1(
W Y'DWDB1$'9
$GGUHVV
)60&B$'>@
W Y1$'9B1(
WK'DWDB1:(
'DWD
WK$'B1$'9
WZ1$'9
)60&B1$'9
DL%
Table 33. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1
5THCLK + 2
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
2THCLK
2THCLK + 1
ns
tw(NWE)
FSMC_NWE low time
2THCLK – 1
2THCLK + 2
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK – 1
tv(A_NE)
FSMC_NEx low to FSMC_A valid
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
tw(NADV)
ns
7
ns
3
5
ns
FSMC_NADV low time
THCLK – 1
THCLK + 1
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
THCLK – 3
-
ns
th(A_NWE)
Address hold time after FSMC_NWE high
4THCLK
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
-
-
THCLK – 1.5
THCLK – 5
1.6
ns
-
ns
THCLK + 1.5
ns
-
ns
1. CL = 15 pF.
2. Preliminary values.
DS5944 Rev 11
61/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Synchronous waveforms and timings
Figure 19 through Figure 22 represent synchronous waveforms and Table 35 through
Table 37 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 19. Synchronous multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,
.%X,
T D#,+,
.%X(
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!)6
TD#,+,
!6
&3-#?!;=
TD#,+(
./%,
TD#,+,
./%(
&3-#?./%
TD#,+,
!$)6
TSU!$6
#,+(
TD#,+,
!$6
&3-#?!$;=
!$;=
TH#,+(
!$6
TSU!$6
#,+(
$
TSU.7!)46
#,+(
TH#,+(
!$6
$
$
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
TH#,+(
.7!)46
AII
62/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 34. Synchronous multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKH-NOEL)
FSMC_CLK high to FSMC_NOE low
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
6
-
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0
-
ns
8
-
ns
2
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
27.7
-
1.5
2
ns
-
-
4
5
0
2
1
0.5
ns
ns
-
ns
ns
-
ns
ns
-
ns
12
ns
ns
1. CL = 15 pF.
2. Preliminary values.
DS5944 Rev 11
63/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 20. Synchronous multiplexed PSRAM write timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,
.%X,
TD#,+,
.%X(
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!6
TD#,+,
!)6
&3-#?!;=
TD#,+,
.7%,
TD#,+,
.7%(
&3-#?.7%
TD#,+,
!$)6
TD#,+,
!$6
&3-#?!$;=
TD#,+,
$ATA
TD#,+,
$ATA
!$;=
$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
TH#,+(
.7!)46
TD#,+,
.",(
&3-#?.",
AIH
64/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 35. Synchronous multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
td(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
-
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
-
ns
27.7
-
2
2
ns
-
-
4
5
0
2
1
1
12
3
ns
ns
-
ns
ns
-
ns
ns
-
ns
ns
-
ns
6
ns
ns
1. CL = 15 pF.
2. Preliminary values
DS5944 Rev 11
65/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
TD#,+,
.%X,
TD#,+,
.%X(
$ATALATENCY
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!)6
TD#,+,
!6
&3-#?!;=
TD#,+(
./%,
TD#,+,
./%(
&3-#?./%
TSU$6
#,+(
TH#,+(
$6
TSU$6
#,+(
&3-#?$;=
TH#,+(
$6
$
TSU.7!)46
#,+(
$
$
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
T H#,+(
.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
TH#,+(
.7!)46
AIH
Table 36. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Parameter
Max
Unit
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
td(CLKH-NOEL)
FSMC_CLK high to FSMC_NOE low
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1.5
-
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK
high
6.5
-
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
7
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
7
-
ns
th(CLKH-NWAITV)
2
-
ns
FSMC_NWAIT valid after FSMC_CLK high
1. CL = 15 pF.
2. Preliminary values.
66/107
Min
DS5944 Rev 11
27.7
-
1.5
2
ns
-
-
4
5
ns
-
-
0
4
ns
ns
-
ns
1.5
ns
ns
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 22. Synchronous non-multiplexed PSRAM write timings
TW#,+
"53452.
TW#,+
&3-#?#,+
TD#,+,
.%X,
TD#,+,
.%X(
$ATALATENCY
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!6
TD#,+,
!)6
&3-#?!;=
TD#,+,
.7%,
TD#,+,
.7%(
&3-#?.7%
TD#,+,
$ATA
&3-#?$;=
TD#,+,
$ATA
$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46
#,+(
TD#,+,
.",(
TH#,+(
.7!)46
&3-#?.",
AII
Table 37. Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
-
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
-
ns
27.7
-
2
2
ns
-
-
4
5
0
2
1
1
ns
ns
-
ns
ns
-
ns
ns
-
ns
6
ns
ns
1. CL = 15 pF.
2. Preliminary values.
DS5944 Rev 11
67/107
106
Electrical characteristics
5.3.11
STM32F100xC, STM32F100xD, STM32F100xE
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 38. They are based on the EMS levels and classes
defined in application note AN1709.
Table 38. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 24 MHz, LQFP144
package, conforms to
IEC 61000-4-2
2B
VEFTB
VDD = 3.3 V, TA = +25 °C,
Fast transient voltage burst limits to be
f
= 24 MHz, LQFP144
applied through 100 pF on VDD and VSS pins HCLK
package, conforms to
to induce a functional disturbance
IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
68/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 39. EMI characteristics
Symbol Parameter
SEMI
5.3.12
Peak level
Conditions
Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/24 MHz
0.1 MHz to 30 MHz
VDD = 3.6 V, TA = 25°C,
30 MHz to 130 MHz
LQFP144 package
compliant with SAE
130 MHz to 1GHz
J1752/3
SAE EMI Level
16
25
dBµV
25
4
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 40. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C
conforming to JESD22-A114
2
2000
VESD(CDM)
Electrostatic discharge
TA = +25 °C
voltage (charge device model) conforming to JESD22-C101
II
500
V
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78 IC latch-up standard.
Table 41. Electrical sensitivities
Symbol
LU
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78
DS5944 Rev 11
Class
II level A
69/107
106
Electrical characteristics
5.3.13
STM32F100xC, STM32F100xD, STM32F100xE
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 42
Table 42. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
70/107
Description
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
Injected current on all FT pins
-5
+0
Injected current on any other pin
-5
+5
DS5944 Rev 11
Unit
mA
STM32F100xC, STM32F100xD, STM32F100xE
5.3.14
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 43. I/O static characteristics
Symbol
VIL
Parameter
Conditions
Min
Typ
Max
–0.3
-
0.28*(VDD–2 V)+0.8 V
–0.3
-
0.32*(VDD–2 V)+0.75 V
0.41*(VDD–2 V) +1.3 V
-
VDD+0.3
0.42*(VDD–2)+1 V
-
200
-
-
mV
5% VDD(3)
-
-
mV
VSS ≤VIN ≤VDD
Standard I/Os
-
-
±1
VIN = 5 V
I/O FT
-
-
3
Standard I/O input low
level voltage
I/O FT(1) input low
level voltage
-
V
Standard I/O input
high level voltage
VIH
Vhys
I/O FT(1) input high
level voltage
Standard I/O Schmitt
trigger voltage
hysteresis(2)
VDD > 2 V
VDD ≤2 V
Ilkg
5.5
5.2
-
I/O FT Schmitt trigger
voltage hysteresis(2)
Input leakage
current(4)
Unit
µA
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
DS5944 Rev 11
71/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 23. Standard I/O input characteristics - CMOS port
6)(6),6
3STAND
#-/
7)(MIN
7),MAX
6
6 )( $$
6 $$
T6 )(
IREMEN
ARDREQU
6
6), $$
T6 ),6 $$
REQUIREMEN
RD
#-/3STANDA
)NPUTRANGE
NOTGUARANTEED
6$$6
AIB
Figure 24. Standard I/O input characteristics - TTL port
6)(6),6
7)(MIN
44,REQUIREMENTS 6)( 6
6
6 )( $$
)NPUTRANGE
NOTGUARANTEED
7),MAX
6 ),6 $$
44,REQUIREMENTS 6),6
6$$6
AI
72/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 25. 5 V tolerant I/O input characteristics - CMOS port
6)(6),6
6 $
6 $
EMENTS )(
DARDRE
#-/3STAN
)NPUTRANGE
NOTGUARANTEED
6 ),6 $$
6 $$
QUIRMENT6 ),
6 )(6 $$
RDREQUIR
TANDA
#-/3S
6$$6
6$$
AIB
Figure 26. 5 V tolerant I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENT6 )(6
6
6 )(
$$
7)(MIN
7),MAX
)NPUTRANGE
NOTGUARANTEED
6 ),
6 $$
44,REQUIREMENTS6 ),6
6$$6
AI
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 it can sink
or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 7).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 7).
DS5944 Rev 11
73/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Output voltage levels
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9. All I/Os are CMOS and TTL compliant.
Table 44. Output voltage characteristics
Symbol
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
Parameter
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Conditions
Min
Max
CMOS port(2),
IIO = +8 mA,
2.7 V < VDD < 3.6 V
-
0.4
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA(4)
2.7 V < VDD < 3.6 V
IIO = +6 mA(4)
2 V < VDD < 2.7 V
Unit
V
VDD–0.4
-
-
0.4
V
2.4
-
-
1.3
V
VDD–1.3
-
-
0.4
V
VDD–0.4
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
74/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 45, respectively.
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
Table 45. I/O AC characteristics(1)
MODEx
[1:0] bit
value(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
10
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
tf(IO)out
Output high to low level fall
time
11
tr(IO)out
Conditions
CL = 50 pF, VDD = 2 V to 3.6 V
tEXTIpw
2(3)
MHz
CL = 50 pF, VDD = 2 V to 3.6 V
ns
(3)
125
CL= 50 pF, VDD = 2 V to 3.6 V
10(3)
MHz
25(3)
CL= 50 pF, VDD = 2 V to 3.6 V
ns
25(3)
CL = 50 pF, VDD = 2 V to 3.6 V
24
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6
V
5(3)
Output low to high level rise
CL = 50 pF, VDD = 2.7 V to 3.6 V
time
Pulse width of external
signals detected by the
EXTI controller
Unit
125(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
Max
-
MHz
ns
8(3)
12(3)
10(3)
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F100xx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 27.
3. Guaranteed by design, not tested in production.
DS5944 Rev 11
75/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 27. I/O AC characteristics definition
%84%2.!,
/54054
/.P&
TR)/ OUT
TF)/ OUT
4
-AXIMUMFREQUENCYISACHIEVEDIFT RTF 4ANDIFTHEDUTYCYCLEIS
WHENLOADEDBYP&
5.3.15
AIC
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 43).
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
Table 46. NRST pin characteristics
Symbol
VIL(NRST)(1)
VIH(NRST)
(1)
Vhys(NRST)
Conditions
Min
Typ
Max
NRST Input low level voltage
-
–0.5
-
0.8
NRST Input high level voltage
-
2
-
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
VIN = VSS
30
40
50
kΩ
NRST Input filtered pulse
-
-
-
100
ns
NRST Input not filtered pulse
-
300
-
-
ns
Weak pull-up equivalent resistor(2)
RPU
VF(NRST)
Parameter
(1)
VNF(NRST)
(1)
Unit
V
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
76/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 28. Recommended NRST pin protection
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal Reset
Filter
0.1 µF
STM32F10xxx
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
DS5944 Rev 11
77/107
106
Electrical characteristics
5.3.16
STM32F100xC, STM32F100xD, STM32F100xE
TIMx characteristics
The parameters given in Table 47 are guaranteed by design.
Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
Table 47. TIMx characteristics
Symbol
Conditions(1)
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 24 MHz
41.7
-
ns
0
fTIMxCLK/2
MHz
fTIMxCLK = 24 MHz
0
12
MHz
Timer resolution
-
-
16
bit
16-bit counter clock period
when the internal clock is
selected
-
1
65536
tTIMxCLK
fTIMxCLK = 24 MHz
-
2730
µs
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 24 MHz
-
178
s
Parameter
tres(TIM)
Timer resolution time
fEXT
Timer external clock
frequency on CHx(2)
ResTIM
tCOUNTER
tMAX_COUNT Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM5, TIM15, TIM16 and TIM17
timers.
2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3, TIM4 and TIM5, to the CH1 to
CH2 for TIM15, and to CH1 for TIM16 and TIM17.
5.3.17
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply
voltage conditions summarized in Table 9.
The STM32F100xx value line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 48. Refer also to Section 5.3.13: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
78/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 48. I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
0
-
0
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition setup
time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
µs
tw(STO:STA)
Stop to Start condition time (bus
free)
4.7
-
1.3
-
µs
Cb
Capacitive load for each bus line
-
400
-
400
pF
µs
ns
µs
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
DS5944 Rev 11
79/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 29. I2C bus AC waveforms and measurement circuit
9''B,&
9''B,&
5S
5S
,ð&EXV
670)[
5V
6'$
5V
6&/
6WDUWUHSHDWHG
6WDUW
6WDUW
WVX67$
6'$
WI6'$
WU6'$
WK67$
WVX6'$
WZ6&//
WK6'$
WVX67267$
6WRS
6&/
WZ6&/+
WU6&/
WI6&/
WVX672
DLI
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 49. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)(3)
RP = 4.7 kΩ
400
0x8011
300
0x8016
200
0x8021
100
0x0064
50
0x00C8
20
0x01F4
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 400 kHz, the tolerance on the achieved speed is of ±2%. For other speed ranges, the
tolerance on the achieved speed ±1%. These variations depend on the accuracy of the external
components used to design the application.
3. Guaranteed by design, not tested in production.
80/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 50 are preliminary values derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage conditions summarized in Table 9.
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 50. SPI characteristics
Symbol
fSCK
1/tc(SCK)
Parameter
Conditions
SPI clock frequency
Min
Max
Master mode
-
12
Slave mode
-
12
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
tsu(NSS)(1)
NSS setup time
th(NSS)(1)
(1)
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
th(MI)
ta(SO)(1)(2)
ns
30
70
%
Slave mode
4tPCLK
-
NSS hold time
Slave mode
2tPCLK
-
SCK high and low time
Master mode, fPCLK = 24 MHz,
presc = 4
50
60
Master mode
5
-
Slave mode
5
-
Master mode
5
-
Slave mode
4
-
0
3tPCLK
2
10
Data input setup time
Data input hold time
Data output access time Slave mode, fPCLK = 24 MHz
tdis(SO)(1)(3) Data output disable time Slave mode
(1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time
Master mode (after enable
edge)
-
5
Slave mode (after enable edge)
15
-
Master mode (after enable
edge)
2
-
tv(SO)
th(SO)(1)
th(MO)(1)
MHz
8
(1)
th(SI)(1)
Unit
Data output hold time
ns
1. Preliminary values.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
DS5944 Rev 11
81/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 30. SPI timing diagram - slave mode and CPHA = 0
Figure 31. SPI timing diagram - slave mode and CPHA = 1
166LQSXW
6&.LQSXW
W68166
&3+$
&32/
&3+$
&32/
WZ6&.+
WZ6&./
WK62
WY62
WD62
0,62
287387
06%287
%,7287
WU6&.
WI6&.
WGLV62
/6%287
WK6,
WVX6,
026,
,1387
WK166
WF6&.
06%,1
%,7,1
/6%,1
DLE
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
82/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 32. SPI timing diagram - master mode
+LJK
166LQSXW
6&.2XWSXW
&3+$
&32/
6&.2XWSXW
WF6&.
&3+$
&32/
&3+$
&32/
&3+$
&32/
WVX0,
0,62
,13 87
WZ6&.+
WZ6&./
WU6&.
WI6&.
%,7,1
06%,1
/6%,1
WK0,
026,
287387
% , 7287
06%287
WY02
/6%287
WK02
DLF
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
HDMI consumer electronics control (CEC)
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics.
5.3.18
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 51 are preliminary values derived
from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply
voltage conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
DS5944 Rev 11
83/107
106
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Table 51. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
-
2.4
-
3.6
V
VREF+
Positive reference voltage
-
2.4
-
VDDA
V
IVREF
Current on the VREF input
pin
-
-
160(1)
220(1)
µA
fADC
ADC clock frequency
-
0.6
-
12
MHz
fS(2)
Sampling rate
-
0.05
-
1
MHz
fADC = 12 MHz
-
-
823
kHz
-
-
-
17
1/fADC
fTRIG(2)
External trigger frequency
VAIN(3)
Conversion voltage range
-
0 (VSSA tied to
ground)
-
VREF+
V
RAIN(2)
External input impedance
See Equation 1 and
Table 52 for details
-
-
50
kΩ
RADC(2)
Sampling switch resistance
-
-
-
1
kΩ
CADC(2)
Internal sample and hold
capacitor
-
-
-
8
pF
tCAL(2)
Calibration time
fADC = 12 MHz
5.9
µs
-
83
1/fADC
tlat(2)
Injection trigger conversion
latency
fADC = 12 MHz
-
-
-
tlatr(2)
Regular trigger conversion
latency
fADC = 12 MHz
-
-
0.143
µs
-
-
2(4)
1/fADC
tS(2)
Sampling time
fADC = 12 MHz
0.125
-
17.1
µs
1.5
-
239.5
1/fADC
tSTAB(2)
Power-up time
-
0
0
1
µs
Total conversion time
(including sampling time)
fADC = 12 MHz
1.17
-
21
µs
tCONV(2)
-
-
-
-
0.214
(4)
3
14 to 252 (tS for sampling +12.5 for
successive approximation)
µs
1/fADC
1/fADC
1. Preliminary values.
2. Guaranteed by design, not tested in production.
3. VREF+ is internally connected to VDDA
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51.
Equation 1: RAIN max formula:
TS
- – R ADC
R AIN < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The above formula (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
84/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 52. RAIN max for fADC = 12 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.125
0.4
7.5
0.625
5.9
13.5
1.125
11.4
28.5
2.375
25.2
41.5
3.45
37.2
55.5
4.625
50
71.5
5.96
NA
239.5
20
NA
1. Guaranteed by design, not tested in production.
Table 53. ADC accuracy - limited test conditions(1)(2)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max
fPCLK2 = 24 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
VREF+ = VDDA
TA = 25 °C
Measurements made after
ADC calibration
±1.5
±2.5
±1
±2
±0.5
±1.5
±1.5
±2
±1.5
±2
Test conditions
Typ
Max
fPCLK2 = 24 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = Full operating range
Measurements made after
ADC calibration
±2
±5
±1.5
±2.5
±1.5
±3
±1.5
±2.5
±1.5
±4.5
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Preliminary values.
Table 54. ADC accuracy(1) (2) (3)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. Preliminary values.
Note:
ADC accuracy vs. negative injection current: Injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
DS5944 Rev 11
85/107
106
Electrical characteristics
Note:
STM32F100xC, STM32F100xD, STM32F100xE
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.13 does not affect the ADC accuracy.
Figure 33. ADC accuracy characteristics
9''$
95()
RUGHSHQGLQJRQSDFNDJH
>/6%,'($/
(*
([DPSOHRIDQDFWX DOWUDQVIH UFXUYH
7KHLGHDOWUDQVIHUFX UYH
(QGSRLQWFRUUHODWLRQOLQH
(7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ
EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV
(2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO
WUDQVLWLRQDQGWKHODVWDFWXDORQH
(* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO
WUDQVLWLRQDQGWKHODVWDFWXDORQH
(' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ
EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH
(/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ
EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW
FRUUHODWLRQOLQH
(7
(2
(/
('
/6%,'($/
966$
9''$
DLH
Figure 34. Typical connection diagram using the ADC
670)[[[
9''
5$,1
9$,1
6DPSOHDQGKROG$'&
FRQYHUWHU
97
9
5$'&
$,1[
97
9
&SDUDVLWLF
,/$
ELW
FRQYHUWHU
&$'&
DLG
1. Refer to Table 51 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 35 or Figure 36,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
86/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+
1 µF // 10 nF
V DDA
1 µF // 10 nF
V SSA/V REF-
ai14380b
1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin
packages only.
Figure 36. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
DS5944 Rev 11
87/107
106
Electrical characteristics
5.3.19
STM32F100xC, STM32F100xD, STM32F100xE
DAC electrical specifications
Table 55. DAC characteristics
Symbol
Parameter
Min
Typ
Max(1)
Unit
Comments
VDDA
Analog supply voltage
2.4
-
3.6
V
VREF+
Reference supply voltage
2.4
-
3.6
V
VSSA
Ground
0
-
0
V
-
RLOAD(1)
Resistive load with buffer ON
5
-
kΩ
-
-
VREF+ must always be below
VDDA
RO(1)
Impedance output with buffer OFF
-
-
15
kΩ
When the buffer is OFF, the
Minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 MΩ
CLOAD(1)
Capacitive load
-
-
50
pF
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
DAC_OUT
min(1)
Lower DAC_OUT voltage with buffer
ON
0.2
-
DAC_OUT
max(1)
Higher DAC_OUT voltage with buffer
ON
-
-
DAC_OUT
min(1)
Lower DAC_OUT voltage with buffer
OFF
-
0.5
DAC_OUT
max(1)
Higher DAC_OUT voltage with buffer
OFF
-
-
IDDVREF+
DAC DC current consumption in
quiescent mode (Standby mode)
IDDA
DNL(1)
INL(1)
88/107
DAC DC current consumption in
quiescent mode (2)
Differential non linearity Difference
between two consecutive code-1LSB)
Integral non linearity (difference
between measured value at Code i
and the value at Code i on a line
drawn between Code 0 and last Code
1023)
-
V
VDDA –
V
0.2
-
mV
VREF+
V
– 1LSB
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V
It gives the maximum output
excursion of the DAC.
-
-
220
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
-
-
380
µA
With no load, middle code
(0x800) on the inputs
-
-
480
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
-
-
±0.5
LSB
Given for the DAC in 10-bit
configuration
-
-
±2
LSB
Given for the DAC in 12-bit
configuration
-
-
±1
LSB
Given for the DAC in 10-bit
configuration
-
-
±4
LSB
Given for the DAC in 12-bit
configuration
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 55. DAC characteristics (continued)
Symbol
Offset(1)
Gain
error(1)
Parameter
Max(1)
Unit
-
±10
mV
Given for the DAC in 12-bit
configuration
-
-
±3
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
-
-
±12
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
-
-
±0.5
%
Given for the DAC in 12-bit
configuration
4
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Min
Typ
Offset error
(difference between measured value
at Code (0x800) and the ideal value =
VREF+/2)
Gain error
Settling time (full scale: for a 10-bit
input code transition between the
tSETTLING(1) lowest and the highest input codes
when DAC_OUT reaches final value
±1LSB
-
3
Comments
Update
rate(1)
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from code i
to i+1LSB)
-
-
tWAKEUP(1)
Wakeup time from off state (Setting
the ENx bit in the DAC Control
register)
-
6.5
10
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+ (1)
Power supply rejection ratio (to VDDA)
(static DC measurement
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. Preliminary values.
2. Quiescent mode refer to the state of the DAC keeping steady value on the output, so no dynamic consumption is involved.
Figure 37. 12-bit buffered /non-buffered DAC
%XIIHUHGQRQEXIIHUHG'$&
%XIIHU
5/2$'
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
'$&[B287
&/2$'
DLG
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
DS5944 Rev 11
89/107
106
Electrical characteristics
5.3.20
STM32F100xC, STM32F100xD, STM32F100xE
Temperature sensor characteristics
Table 56. TS characteristics
Symbol
TL(1)
Min
Typ
Max
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25°C
1.32
1.41
1.50
V
Startup time
4
-
10
µs
ADC sampling time when reading the temperature
-
-
17.1
µs
VSENSE linearity with temperature
Avg_Slope
(1)
V25(1)
tSTART(2)
TS_temp
Parameter
(3)(2)
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
90/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
LQFP144 package information
Figure 38. LQFP - 144-pin, 20 x 20 mm low-profile quad flat
package outline
6($7,1*
3/$1(
F
$
$
&
$
PP
*$8*(3/$1(
'
/
'
.
$
FFF &
/
'
(
3,1
(
(
E
6.1
,'(17,),&$7,21
H
$B0(B9
1. Drawing is not to scale.
DS5944 Rev 11
91/107
106
Package information
STM32F100xC, STM32F100xD, STM32F100xE
Table 57. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.8740
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
-
17.500
-
-
0.6890
-
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
-
17.500
-
-
0.6890
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
92/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Package information
Figure 39. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package
recommended footprint
DLH
1. Dimensions are expressed in millimeters.
DS5944 Rev 11
93/107
106
Package information
STM32F100xC, STM32F100xD, STM32F100xE
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 40.LQFP144 marking example (package top view)
2SWLRQDOJDWHPDUN
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
$
)
=&7%
'DWHFRGH
< ::
3LQLGHQWLILHU
06Y9
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
94/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
LQFP100 package information
Figure 41. LQFP – 14 x 14 mm 100 pin low-profile quad flat package outline
MM
C
!
!
3%!4).'0,!.%
#
!
'!5'%0,!.%
$
!
+
CCC #
,
$
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
6.2
Package information
E
,?-%?6
1. Drawing is not to scale.
Table 58. LQPF - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
DS5944 Rev 11
95/107
106
Package information
STM32F100xC, STM32F100xD, STM32F100xE
Table 58. LQPF - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. LQFP - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
96/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Package information
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 43.LQFP100 marking example (package top view)
2SWLRQDOJDWH
PDUN
3URGXFWLGHQWLILFDWLRQ
^dDϯϮ&ϭϬϬ
sdϲ
5HYLVLRQFRGH
y
'DWHFRGH
z tt
3LQLGHQWLILHU
06Y9
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS5944 Rev 11
97/107
106
Package information
6.3
STM32F100xC, STM32F100xD, STM32F100xE
LQFP64 package information
Figure 44.LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
$
FFF &
'
'
'
.
/
/
3,1
,'(17,),&$7,21
(
(
(
E
H
:B0(B9
1. Drawing is not in scale.
Table 59. LQFP - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
98/107
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Package information
Table 59. LQFP - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 45.LQFP - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
AIC
1. Dimensions are in millimeters.
DS5944 Rev 11
99/107
106
Package information
STM32F100xC, STM32F100xD, STM32F100xE
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 46.LQFP64 marking example (package top view)
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
y
^dDϯϮ&ϭϬϬ
Zdϲ
z tt
3LQLGHQWLILHU
'DWHFRGH
06Y9
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
100/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
6.4
Package information
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 9: General operating conditions on page 38.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 60. Package thermal characteristics
Symbol
ΘJA
6.4.1
Parameter
Value
Thermal resistance junction-ambient
LQFP 144 - 20 × 20 mm / 0.5 mm pitch
35
Thermal resistance junction-ambient
LQFP 100 - 14 × 14 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
LQFP 64 - 10 × 10 mm / 0.5 mm pitch
49
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DS5944 Rev 11
101/107
106
Package information
6.4.2
STM32F100xC, STM32F100xD, STM32F100xE
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 61: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F100xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 60 TJmax is calculated as follows:
–
For LQFP64, 49 °C/W
TJmax = 82 °C + (49 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 61: Ordering information).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
102/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
Package information
Using the values obtained in Table 60 TJmax is calculated as follows:
–
For LQFP100, 40 °C/W
TJmax = 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 61: Ordering information).
Figure 47. LQFP100 PD max vs. TA
700
PD (mW)
600
500
Suffix 6
400
Suffix 7
300
200
100
0
65
75
85
95
105
115
125
135
TA (°C)
DS5944 Rev 11
103/107
106
Ordering information
7
STM32F100xC, STM32F100xD, STM32F100xE
Ordering information
Table 61. Ordering information
Example:
STM32 F 100 V
C
T
6
B
xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
100 = value line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
C = 256 Kbytes of Flash memory
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Internal code
B
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
104/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
8
Revision history
Revision history
Table 62. Document revision history
Date
Revision
09-Oct-2008
1
Initial release.
31-Mar-2009
2
I/O information clarified on page 1.
Table 5: High-density STM32F100xx pin definitions modified.
Figure 5: Memory map on page 26 modified.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Table
21: Low-speed user external clock characteristics modified. ACCHSI
max values modified in Table 24: HSI oscillator characteristics.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Figure 10, Figure 11 and Figure 12 show typical curves (titles
changed).
Small text changes.
01-Sep-2010
3
Major revision of whole document.
Added LQFP144 package and additional peripherals (SPI3, UART4,
UART, TIM5, 12, 14, 13, FSMC).
18-Oct-2010
4
Updated Power consumption data in Table 13 to Table 16
Updated Section 5.3.11: EMC characteristics on page 68
5
Added Section 2.2.6: LCD parallel interface on page 13
In Table 4 on page 24 moved TIM15_BKIN and TIM17_BKIN from
remap to default column. Updated description of PA3, PA5 and PF6
to PF10.
Updated footnotes below Table 6: Voltage characteristics on page 37
and Table 7: Current characteristics on page 38
Added VBAT values in Table 16: Typical and maximum current
consumptions in Stop and Standby modes on page 44
Updated tw min in Table 20: High-speed external user clock
characteristics on page 50
Updated startup time in Table 23: LSE oscillator characteristics (fLSE
= 32.768 kHz) on page 53
Added HSI clock accuracy values in Table 24: HSI oscillator
characteristics on page 54
Updated FSMC Synchronous waveforms and timings on page 62
Updated Table 43: I/O static characteristics on page 71
Added Section 5.3.13: I/O current injection characteristics on
page 70
Corrected TTL and CMOS designations in Table 44: Output voltage
characteristics on page 74
11-Apr-2011
Changes
DS5944 Rev 11
105/107
106
Revision history
STM32F100xC, STM32F100xD, STM32F100xE
Table 62. Document revision history (continued)
Date
Revision
Changes
6
Updated Table 7: Current characteristics on page 38
Corrected “CLKL-NOEL” in Section 5.3.10: FSMC characteristics on
page 56
Updated Table 48: I2C characteristics on page 79
Corrected note “non-robust “ in Section 5.3.18: 12-bit ADC
characteristics on page 83
Updated Figure 1: STM32F100xx value line block diagram on
page 11
Updated Section 5.3.14: I/O port characteristics on page 71
Updated Section 2.2.22: GPIOs (general-purpose inputs/outputs) on
page 20
Updated Table 4: High-density STM32F100xx pin definitions on
page 24
Updated Section 5.3.1: General operating conditions on page 38
Updated PD0 and PD1 in Table 4: High-density STM32F100xx pin
definitions on page 24
7
Updated PD max specifications in Table 9: General operating
conditions
Added footnote to IDDA parameter description in Table 55: DAC
characteristics
10-Mar-2015
8
Updated Table 57: LQFP - 144-pin, 20 x 20 mm low-profile quad flat
package mechanical data, Table 58: LQPF - 100-pin, 14 x 14 mm
low-profile quad flat package mechanical data, Table 59: LQFP - 64pin, 10 x 10 mm low-profile quad flat package mechanical data
Updated Figure 38: LQFP - 144-pin, 20 x 20 mm low-profile quad flat
package outline on page 91, Figure 39: LQFP - 144-pin, 20 x 20 mm
low-profile quad flat package recommended footprint on page 93,
Figure 41: LQFP – 14 x 14 mm 100 pin low-profile quad flat package
outline on page 95, Figure 42: LQFP - 100-pin, 14 x 14 mm lowprofile quad flat recommended footprint on page 96, Figure 44:
LQFP - 64 pin, 10 x 10 mm low-profile quad flat package outline on
page 98, Figure 45: LQFP - 64-pin, 10 x 10 mm low-profile quad flat
recommended footprint on page 99
Added Figure 40: LQFP144 marking example (package top view) on
page 94, Figure 43: LQFP100 marking example (package top view)
on page 97, Figure 46: LQFP64 marking example (package top
view) on page 100
23-Sep-2015
9
Updated Table 19: Peripheral current consumption
Updated Section 6: Package information
29-Mar-2016
10
Updated Table 14: Maximum current consumption in Run mode,
code with data processing running from RAM
11
Updated:
– Section 1: Introduction
– Section 2.2.23: GPIOs (general-purpose inputs/outputs)
– Section 6: Package information
08-Jun-2012
17-Sep-2012
15-Oct-2018
106/107
DS5944 Rev 11
STM32F100xC, STM32F100xD, STM32F100xE
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS5944 Rev 11
107/107
107