STM32F101RB

STM32F101x6 STM32F101x8 STM32F101xB Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces Preliminary Data Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 36 MHz, 45 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware division – Nested interrupt controller with 43 maskable interrupt channels – Interrupt processing (down to 6 CPU cycles) with tail chaining Memories – 32-to-128 Kbytes of Flash memory – 6-to-16 Kbytes of SRAM Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR and programmable voltage detector (PVD) – 4-to-16 MHz high-speed quartz oscillator – Internal 8 MHz factory-trimmed RC – Internal 32 kHz RC – PLL for CPU clock – Dedicated 32 kHz oscillator for RTC with calibration Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers Debug mode – Serial wire debug (SWD) and JTAG interfaces DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 12-bit, 1 µs A/D converter (16-channel) – Conversion range: 0 to 3.6 V LQFP48 7 x 7 mm LQFP64 10 x 10 mm LQFP100 14 x 14 mm – Temperature sensor ■ ■ Up to 80 fast I/O ports – 32/49/80 5 V-tolerant I/Os – All mappable on 16 external interrupt vectors – Atomic read/modify/write operations Up to 6 timers – Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 2 x 16-bit watchdog timers (Independent and Window) – SysTick timer: 24-bit downcounter Up to 7 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) Device summary Root part number STM32F101C6, STM32F101R6 STM32F101C8, STM32F101R8 STM32F101V8 STM32F101RB, STM32F101VB ■ ■ ■ ■ Table 1. Reference STM32F101x6 STM32F101x8 STM32F101xB ■ ■ ■ July 2007 Rev 2 1/64 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STM32F101xx Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 26 Embedded reset and power control block characteristics . . . . . . . . . . . 27 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Internal Clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 40 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/64 STM32F101xx 5.3.14 5.3.15 5.3.16 5.3.17 Contents TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3/64 List of tables STM32F101xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features and peripheral counts (STM32F101xx access line) . . . . . . . . . . . . . . . . . . 7 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Maximum current consumption in Run and Sleep modes (TA = 85 °C) . . . . . . . . . . . . . . . 28 Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 29 Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 31 High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ADC accuracy (fPCLK2 = 10 MHz, fADC = 10 MHz, RAIN < 10 kΩ, VDDA = 3.3 V) . . . . . . . . 55 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 58 LQFP64 – 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 59 LQFP48 – 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 60 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/64 STM32F101xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. STM32F101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F101xx access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F101xx access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F101xx access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI timing diagram - slave mode and CPHA=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 56 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 56 LQPF100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 58 LQFP64 – 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LQFP48 – 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5/64 Introduction STM32F101xx 1 Introduction This datasheet contains the description of the STM32F101xx access line family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10x Flash Programming Reference Manual For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual. 2 Description The STM32F101xx access line family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general purpose 16-bit timers. The STM32F101 family operates in the − to +85°C temperature range, from a 2.0 to 3.6 V 40 power supply. A comprehensive set of power-saving mode allows to design low-power applications. The complete STM32F101xx access line family includes devices in 3 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F101xx access line microcontroller family suitable for a wide range of applications: ● ● ● ● ● Application control and user interface Medical and handheld equipment PC peripherals, gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 6/64 STM32F101xx Description 2.1 Device overview Table 2. Device features and peripheral counts (STM32F101xx access line) Peripheral Flash - Kbytes SRAM - Kbytes Communication Timers General purpose SPI IC USART 2 STM32F101Cx 32 6 2 1 1 2 64 10 3 2 2 3 1 1 2 32 6 STM32F101Rx 64 10 3 2 2 3 1 16 channels 49 36 MHz 2.0 to 3.6 V -40 to +85 °C 128 16 STM32F101Vx 64 10 3 2 2 3 128 16 12-bit synchronized ADC number of channels GPIOs CPU frequency Operating voltage Operating temperature Packages 1 10 channels 32 80 LQFP48 LQFP64 LQFP100 7/64 Description STM32F101xx 2.2 Overview ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xx access line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Embedded Flash memory Up to 128 Kbytes of embedded Flash is available for storing programs and data. Embedded SRAM Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F101xx access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● ● ● ● ● ● ● ● Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 8/64 STM32F101xx Description External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz. Boot modes At startup, boot pins are used to select one of five boot options: ● ● ● Boot from User Flash Boot from System Memory Boot from SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using the USART. Power supply schemes ● ● ● VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL. In VDD range (ADC is limited at 2.4 V). VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded Programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 9: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 9/64 Description STM32F101xx Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● ● ● MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes Power down is used in Standby Mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after RESET. It is disabled in Standby Mode, providing high impedance output. Low-power modes The STM32F101xx access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. ● Standby mode The Standby mode allows to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. 10/64 STM32F101xx Description RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present. The Real-Time Clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: ● ● ● ● A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source General purpose timers (TIMx) There are up to 3 synchronizable standard timers embedded in the STM32F101xx access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. They can work together via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. 11/64 Description STM32F101xx I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. GPIOs (general purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. ADC (analog to digital converter) The 12-bit Analog to Digital Converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. Temperature sensor The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2V < VDDA < 3.6V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 12/64 STM32F101xx Description Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Figure 1. STM32F101xx access line block diagram JTAG & SWD JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF pbus Ibus Trace Controller Flash obl Interface POWER VOLT. REG. 3.3V TO 1.8V @VDD VDD = 2 to 3.6V VSS Cortex M3 CPU Fmax: 36 MHz NVIC NVIC Dbus FLASH 128 KB 64 bit BusMatrix System SRAM 16 KB PCLK1 PCLK2 HCLK FCLK RC 8 MHz RC 32 kHz @VDDA @VBAT PLL & CLOCK MANAGT @VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT GP DMA 7 channels AHB:Fmax=36 MHz IWDG Standby interface VBAT OSC32_IN OSC32_OUT ANTI_TAMP @VDDA NRST VDDA VSSA SUPPLY SUPERVISION POR / PDR PVD Rst Int XTAL 32 kHz AHB2 APB2 AHB2 APB1 RTC AWU Backup reg 80AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] EXTI WAKEUP GPIOA Backup interface TIM2 TIM3 4 Channels 4 Channels 4 Channels RX,TX, CTS, RTS, SmartCard as AF RX,TX, CTS, RTS, SmartCard as AF MOSI,MISO,SCK,NSS as AF SCL,SDA,SMBAL as AF SCL,SDA as AF GPIOB GPIOC GPIOD APB2 : Fmax= 36 MHz GPIOE APB1 : Fmax=24 / 36 MHz TIM4 USART2 USART3 SPI2 2x(8x16bit) I2C1 I2C2 MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, SmartCard as AF 16AF VREF+ VREF- SPI1 USART1 @VDDA 12bit ADC1 IF WWDG Temp sensor ai14385 1. AF = alternate function on I/O port pin. 2. TA = –40 °C to +85 °C (junction temperature up to 125 °C). 13/64 Pin descriptions STM32F101xx 3 Pin descriptions Figure 2. STM32F101xx access line LQFP100 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LQFP100 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 ai14386 14/64 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 STM32F101xx Figure 3. STM32F101xx access line LQFP64 pinout Pin descriptions VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14387 Figure 4. STM32F101xx access line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14378 15/64 Pin descriptions Table 3. Pins LQFP100 LQFP48 LQFP64 Type(1) Pin name STM32F101xx Pin definitions I / O level(2) Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14OSC32_IN PC15OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 PA3 VSS_4 VDD_4 WKUP/USART2_CTS(7)/ ADC_IN0/ TIM2_CH1_ETR(7) USART2_RTS(7)/ADC_IN1/ TIM2_CH2(7) USART2_TX(7)/ADC_IN2/ TIM2_CH3(7) USART2_RX(7)/ADC_IN3/ TIM2_CH4(7) ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13 ANTI_TAMP Default alternate functions(3) 1 2 3 4 5 6 7 8 9 10 11 12 13 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PE2/TRACECK PE3/TRACED0 PE4/TRACED1 PE5/TRACED2 PE6/TRACED3 VBAT PC13-ANTI_TAMP(4) PC14-OSC32_IN(4) PC15-OSC32_OUT(4) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0/ADC_IN10 PC1/ADC_IN11 PC2/ADC_IN12 PC3/ADC_IN13 VSSA VREFVREF+ VDDA PA0-WKUP/USART2_CTS/ ADC_IN0/TIM2_CH1_ETR PA1/USART2_RTS/ADC_ IN1/TIM2_CH2 PA2/USART2_TX/ADC_IN2/ TIM2_CH3 PA3/USART2_RX/ADC_IN3/ TIM2_CH4 VSS_4 VDD_4 I/O I/O I/O I/O I/O S I/O I/O I/O S S I O I/O I/O I/O I/O I/O S S S S I/O I/O I/O I/O S S FT FT FT FT FT TRACECK TRACED0 TRACED1 TRACED2 TRACED3 16/64 STM32F101xx Table 3. Pins LQFP100 LQFP48 LQFP64 Type(1) Pin name Pin descriptions Pin definitions (continued) I / O level(2) Main function(3) (after reset) Default alternate functions(3) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 - 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PA4/SPI1_NSS/ USART2_CK/ADC_IN4 PA5/SPI1_SCK/ADC_IN5 PA6/SPI1_MISO/ADC_IN6/ TIM3_CH1 PA7/SPI1_MOSI/ADC_IN7/ TIM3_CH2 PC4/ADC_IN14 PC5/ADC_IN15 PB0/ADC_IN8/TIM3_CH3 PB1/ADC_IN9/TIM3_CH4 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10/I2C2_SCL USART3_TX PB11/I2C2_SDA USART3_RX VSS_1 VDD_1 PB12/SPI2_NSS/ I2C2_SMBAl/USART3_CK PB13/SPI2_SCK/ USART3_CTS PB14/SPI2_MISO/ USART3_RTS PB15/SPI2_MOSI PD8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD8 SPI1_NSS/USART2_CK(7)/ ADC_IN4 SPI1_SCK/ADC_IN5 SPI1_MISO/ADC_IN6/ TIM3_CH1(7) SPI1_MOSI/ADC_IN7/ TIM3_CH2(7) ADC_IN14 ADC_IN15 ADC_IN8/TIM3_CH3(7) ADC_IN9/TIM3_CH4(7) I2C2_SCL(5)/USART3_TX(5) (7) I2C2_SDA(5)/USART3_RX(5) (7) SPI2_NSS(5) (7)/I2C2_SMBAl(5)/ USART3_CK(5) (7) SPI2_SCK(5)(7)/USART3_CTS(5)(7) SPI2_MISO(5)(7)/USART3_RTS(5)(7) SPI2_MOSI(5) (7) 17/64 Pin descriptions Table 3. Pins LQFP100 LQFP48 LQFP64 Type(1) Pin name STM32F101xx Pin definitions (continued) I / O level(2) Main function(3) (after reset) PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMS-SWDIO USART1_CK/MCO USART1_TX(7) USART1_RX(7) USART1_CTS USART1_RTS PA13 Default alternate functions(3) - 37 38 39 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8/USART1_CK/MCO PA9/USART1_TX PA10/USART1_RX PA11/USART1_CTS PA12/USART1_RTS PA13/JTMS/SWDIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT 29 30 31 32 33 34 35 36 37 38 5 6 40 41 42 43 44 45 46 47 48 49 50 51 52 53 5 6 54 Not connected VSS_2 VDD_2 PA14/JTCK/SWCLK PA15/JTDI PC10 PC11 PC12 PD0 PD1 PD2/TIM3_ETR PD3 PD4 PD5 PD6 S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FT FT FT FT FT FT FT FT FT FT FT FT VSS_2 VDD_2 JTCK/SWCLK JTDI PC10 PC11 PC12 OSC_IN(6) OSC_OUT(6) PD2 PD3 PD4 PD5 PD6 TIM3_ETR PA14 PA15 - - 18/64 STM32F101xx Table 3. Pins LQFP100 LQFP48 LQFP64 Type(1) Pin name Pin descriptions Pin definitions (continued) I / O level(2) Main function(3) (after reset) PD7 JTDO JNTRST PB5 FT FT PB6 PB7 BOOT0 FT FT FT FT PB8 PB9 PE0 PE1 VSS_3 VDD_3 TIM4_CH3(5) (7) TIM4_CH4(5) (7) TIM4_ETR(5) PB3/TRACESWO PB4 I2C1_SMBAl I2C1_SCL(7)/TIM4_CH1(5) (7) I2C1_SDA(7)/TIM4_CH2(5) (7) Default alternate functions(3) 39 40 41 42 43 44 45 46 47 48 55 56 57 58 59 60 61 62 63 64 88 89 90 91 92 93 94 95 96 97 98 99 100 PD7 PB3/JTDO/TRACESWO PB4/JNTRST PB5/I2C1_SMBAl PB6/I2C1_SCL/TIM4_CH1 PB7/I2C1_SDA/TIM4_CH2 BOOT0 PB8/TIM4_CH3 PB9/TIM4_CH4 PE0/TIM4_ETR PE1 VSS_3 VDD_3 I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O S S FT FT FT 1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. Refer to Table 2 on page 7. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes. 6. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, UM0306, available from the STMicroelectronics website: www.st.com. 19/64 Memory mapping STM32F101xx 4 Memory mapping The memory map is shown in Figure 5. Figure 5. Memory map 0xFFFF FFFF 0xE010 0000 0x6000 0000 0x4002 3400 0xFFFF FFFF 0xFFFF F000 0x4002 3000 0x4002 2400 0x4002 2000 APB memory space reserved reserved reserved reserved reserved Flash interface reserved RCC reserved DMA reserved 4K 1K 3K 1K 3K 1K 3K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 1K 1K 1K 1K 1K 35K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 2K 1K 1K 1K 1K 1K 7K 1K 1K 1K 7 0xE010 0000 0xE000 0000 Cortex-M3 internal peripherals 0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000 6 0xC000 0000 0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000 USART1 reserved SPI1 reserved reserved ADC1 reserved 0x4001 1C00 5 0xA000 0000 0x4001 2C00 0x4001 2800 0x4001 2400 4 0x8000 0000 0x1FFF FFFF 0x1FFF F9FF 0x4001 1800 reserved Port E Port D Port C Port B Port A EXTI AFIO reserved 0x4001 1400 0x4001 1000 0x4001 0C00 0x4001 0800 Option bytes 0x1FFF F800 3 0x1FFF F000 0x6000 0000 System memory 0x4001 0400 0x4001 0000 0x4000 7400 2 0x4000 0000 Peripherals reserved 0x4000 7000 0x4000 6C00 0x4000 6800 0x4000 6400 0x4000 6000 PWR BKP reserved reserved reserved reserved I2C2 I2C1 reserved 1 0x2000 0000 SRAM 0x0801 FFFF 0x4000 5C00 0x4000 5800 0x4000 5400 0x4000 4C00 0 0x0000 0000 Code 0x0800 0000 Flash memory 0x4000 4800 0x4000 4400 USART3 USART2 reserved 0x4000 3C00 0x4000 3800 Reserved SPI2 reserved IWDG WWDG RTC reserved 0x4000 3400 0x4000 3000 0x4000 2C00 0x4000 2800 0x4000 0C00 0x4000 0800 0x4000 0400 ai14379 0x4000 0000 TIM4 TIM3 TIM2 20/64 STM32F101xx Electrical characteristics 5 5.1 Electrical characteristics Test conditions Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. 21/64 Electrical characteristics STM32F101xx Figure 6. Pin loading conditions Figure 7. Pin input voltage STM32F101 PIN C=50pF VIN STM32F101 PIN ai14123 ai14124 5.1.6 Power supply scheme Figure 8. Power supply scheme VBAT 3.3 V Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) 1.8-3.6V Po wer swi tch OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 VSS Regulator 5 × 100 nF + 1 × 10 µF VDD VREF 1/2/3/4/5 3.3V VDDA VREF+ VREFVSSA ai14125 10 nF + 1 µF 10 nF + 1 µF ADC Analog: RCs, PLL, ... 22/64 STM32F101xx Electrical characteristics 5.1.7 Current consumption measurement Figure 9. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 23/64 Electrical characteristics STM32F101xx 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4. Symbol V VDD− SS VIN |∆VDDx| |VSSX − VSS| Voltage characteristics Ratings External 3.3 V supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min − 0.3 VSS −0.3 VSS − 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 V Unit VESD(HBM) see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V supply. 2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN