STM32F102C8T6TR

STM32F102x8 STM32F102xB Medium-density USB access line, Arm®-based 32-bit MCU with 64/128 KB Flash, USB FS, 6 timers, ADC and 8 com. interfaces Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 10 or 16 Kbytes of SRAM • Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers • Debug mode – Serial wire debug (SWD) and JTAG interfaces LQFP48 (7 × 7 mm) • Up to six timers – Three 16-bit timers, each with up to four IC/OC/PWM or pulse counter – Two watchdog timers (Independent and Window) – SysTick timer: 24-bit downcounter • Up to eight communication interfaces – Up to two I2C interfaces (SMBus/PMBus) – Up to three USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to two SPIs (12 Mbit/s) – One USB 2.0 full speed interface • CRC calculation unit, 96-bit unique ID • ECOPACK packages Table 1. Device summary Reference • DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs LQFP64 (10 × 10 mm Part number STM32F102x8 STM32F102C8, STM32F102R8 STM32F102xB STM32F102CB, STM32F102RB • 1 × 12-bit, 1.2 µs A/D converter (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor • Up to 51 fast I/O ports – 37/51 I/Os all mappable on 16 external interrupt vectors and almost all 5 V-tolerant August 2019 This is information on a product in full production. DS5933 Rev 7 1/81 www.st.com Contents STM32F102x8, STM32F102xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2/81 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 Arm® Cortex®-M3 core with embedded Flash memory and SRAM . . . . 13 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 18 2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.22 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.23 GPIOs (general-purpose inputs / outputs) . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.24 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DS5933 Rev 7 STM32F102x8, STM32F102xB Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 30 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 49 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DS5933 Rev 7 3/81 4 Contents STM32F102x8, STM32F102xB 6.4 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.1 Evaluating the maximum junction temperature for an application . . . . . 76 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4/81 DS5933 Rev 7 STM32F102x8, STM32F102xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F102x8 and STM32F102xB medium-density USB access line features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Medium-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maximum current consumption in Run mode, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Max. current consumption in Sleep mode, code running from Flash memory or RAM. . . . 34 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34 Typical current consumption in Run mode, code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical current consumption in Sleep mode, code running from Flash memory or RAM . . 38 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DS5933 Rev 7 5/81 6 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. 6/81 STM32F102x8, STM32F102xB ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DS5933 Rev 7 STM32F102x8, STM32F102xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. STM32F102T8 medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 20 STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 20 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33 Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33 Typical current consumption on VBAT with RTC on versus temperature for different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption in Stop mode with regulator in Run mode versus temperature, VDD = 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature, VDD = 3.3 / 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Standby mode versus temperature, VDD = 3.3 / 3.6 V . . . 36 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 69 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 72 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DS5933 Rev 7 7/81 7 Introduction 1 STM32F102x8, STM32F102xB Introduction This datasheet provides the ordering information and mechanical device characteristics of STM32F102x8 and STM32F102xB medium-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F102xx datasheet must be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory refer to STM32F10xxx Flash memory microcontrollers (PM0075). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Arm® Cortex®-M3 core(a) refer to the Cortex®-M3 Technical Reference Manual, available from the Arm® website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 8/81 DS5933 Rev 7 STM32F102x8, STM32F102xB 2 Description Description The STM32F102xx medium-density USB access line incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory of 64 or 128 Kbytes and SRAM of 10 or 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, one USB and three USARTs), one 12-bit ADC and three general-purpose 16-bit timers. The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm and LQFP64 10 × 10 mm packages. The STM32F102xx medium-density USB access line microcontrollers are suitable for a wide range of applications. • Application control and user interface • Medical and handheld equipment • PC peripherals, gaming and GPS platforms • Industrial applications: PLC, inverters, printers, and scanners • Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. DS5933 Rev 7 9/81 68 Description 2.1 STM32F102x8, STM32F102xB Device overview Table 2. STM32F102x8 and STM32F102xB medium-density USB access line features and peripheral counts Peripheral STM32F102Cx Flash memory - Kbytes 64 128 64 128 SRAM - Kbytes 10 16 10 16 General-purpose 3 3 3 3 SPI 2 2 2 2 I2C 2 2 2 2 USART 3 3 3 3 USB 1 1 1 1 Timers Communication interfaces 12-bit synchronized ADC number of channels GPIOs 1 10 channels 1 16 channels 37 51 CPU frequency 48 MHz Operating voltage Operating temperatures 2.0 to 3.6 V Ambient temperature: –40 to +85 °C (see Table 8) Junction temperature: –40 to +105 °C (see Table 8) Packages 10/81 STM32F102Rx LQFP48 DS5933 Rev 7 LQFP64 STM32F102x8, STM32F102xB Description Figure 1. STM32F102T8 medium-density USB access line block diagram TPIU SW/JTAG Trace/trig SWD Trace Controller ont pbus Ibus Cortex M3 CPU Fmax: 48 MHz NVIC Dbus NVIC System AHB: Fmax =48 MHz 7 channels SUPPLY SUPERVISION NRST VDDA VSSA POR / PDR Rst GPIOA PB[15:0] GPIOB PC[15:0] GPIOC PLL & CLOCK MANAGT XTAL OSC 4-16 MHz IWDG Stand by in terface @VDDA RTC AWU AHB2 APB1 Backup reg @VDDA OSC32_IN OSC32_OUT TAMPER-RTC Backup interface APB1: Fmax = 24 MHz APB2 : Fmax = 48 MHz USART1 VBAT @VBAT GPIOD SPI1 OSC_IN OSC_OUT RC 8 MHz RC 40 kHz TIM2 4 Channels TIM3 4 Channels TIM4 MOSI,MISO, SCK,NSS as AF 16 AF @VDD EXTI WAKEUP PA[ 15:1] RX,TX, CTS, RTS, Smart Card as AF PCLK1 PCLK2 HCLK FCLK VDD = 2 to 3.6V VSS @VDD 64 bit Int AHB2 APB2 PD[2:0] Flash 128 KB XTAL 32 kHz PVD 51AF VOLT . REG. 3.3V TO 1.8V SRAM 16 KB GP DMA @VDDA POWER Flash obl Interface JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF BusM atrix TRACECLK TRACED[0:3] as AS 12bit ADC1 IF USART2 USART3 x16bit)SPI2 RX,TX, CTS, RTS, CK, Smartcard as AF MOSI,MISO,SCK,NSS as AF I2C1 SCL,SDA,SMBA as AF I2C2 SCL,SDA, SMBA as AF USB 2.0 FS Temp sen so r 4 Channels RX,TX, CTS, RTS, CK, Smartcard as AF USBDP, USBDM as AF WWDG ai14868f 1. AF = alternate function on I/O port pin. 2. TA = –40 °C to +85 °C (junction temperature up to 105 °C). DS5933 Rev 7 11/81 68 Description STM32F102x8, STM32F102xB Figure 2. Clock tree To Flash prog. if FLITFCLK 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz HCLK to AHB bus, core, memory and DMA 48 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 48 MHz /1, 2..512 max PLLCLK Clock Enable (3 bits) APB1 Prescaler /1, 2, 4, 8, 16 to Cortex System timer FCLK Cortex free running clock 24 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (13 bits) to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock CSS Enable (3 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz 48 MHz max HSE OSC Peripheral Clock Enable (11 bits) /2 ADC Prescaler /2, 4, 6, 8 /128 OSC32_IN OSC32_OUT PCLK2 to APB2 peripherals LSE OSC 32.768 kHz to ADC ADCCLK to RTC LSE RTCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK HSI Legend: HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal HSE SYSCLK MCO ai14994b 1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output (USBCLK) at 48 MHz. 2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz. 3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock. 12/81 DS5933 Rev 7 STM32F102x8, STM32F102xB 2.2 Description Full compatibility throughout the family The STM32F102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to as medium-density devices. Low-density devices are an extension of the STM32F102x8/B devices, they are specified in the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM capacities, a timer and a few communication interfaces less. The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx access line and STM32F103xx performance line devices. Table 3. STM32F102xx USB access line family Low-density STM32F102xx devices Pins 64 48 Medium-density STM32F102xx devices 16 KB Flash memory 32 KB Flash memory(1) 64 KB Flash memory 128 KB Flash memory 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 2 × USARTs, 2 × 16-bit timers 1 × SPI, 1 × I2C, 1 × ADC, 1 × USB 36 - - 3 × USARTs, 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB 2 × USARTs, 3 × 16-bit timers 1 × SPI, 1 × I2C, 1 × ADC, 1 × USB - 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is the one of the STM32F102x8/B medium-density devices. 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded Flash memory and SRAM The Arm® Cortex®-M3 processor is the latest generation of Arm® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The STM32F102xx medium-density USB access line having an embedded Arm® core is therefore compatible with all Arm® tools and software. DS5933 Rev 7 13/81 68 Description 2.3.2 STM32F102x8, STM32F102xB Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity, In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM 10 or 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F102xx medium-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Makes possible early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup. however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full 14/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Description interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of five boot options: • Boot from User Flash • Boot from System Memory • Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details refer to AN2606, available on www.st.com. 2.3.9 Power supply schemes • VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC. Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 8: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in Reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD / VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD / VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop mode • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) DS5933 Rev 7 15/81 68 Description STM32F102x8, STM32F102xB This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F102xx medium-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in Low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a 16/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock. it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 2.3.16 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 2.3.17 SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: 2.3.18 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source General-purpose timers (TIMx) There are three synchronizable general-purpose timers embedded in the STM32F102xx medium-density USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature four independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to twelve input captures / output compares / PWMs on the LQFP48 and LQFP64 packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. DS5933 Rev 7 17/81 68 Description 2.3.19 STM32F102x8, STM32F102xB I²C bus Two I²C bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. 2.3.21 Serial peripheral interface (SPI) Two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 2.3.22 Universal serial bus (USB) The STM32F102xx medium-density USB access line embeds an USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 2.3.23 GPIOs (general-purpose inputs / outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.24 ADC (analog to digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 18/81 DS5933 Rev 7 STM32F102x8, STM32F102xB 2.3.25 Description Temperature sensor The temperature sensor has to generate a a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel, which is used to convert the sensor output voltage into a digital value. 2.3.26 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DS5933 Rev 7 19/81 68 Pinout and pin description 3 STM32F102x8, STM32F102xB Pinout and pin description VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 ai14378d VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 ai14387c 20/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Pinout and pin description Table 4. Medium-density STM32F102xx pin definitions 1 1 VBAT (5) 2 2 PC13-TAMPER-RTC 3 3 PC14-OSC32_IN(5) (5) PC15-OSC32_OUT I / O level(2) LQFP64 Pin name Alternate functions(3) (4) Type(1) LQFP48 Pins Main function(3) (after reset) S - VBAT (6) I/O - PC13 I/O - PC14(6) I/O - (6) PC15 Default Remap - - TAMPER-RTC - OSC32_IN - OSC32_OUT - 4 4 5 5 OSC_IN I/O FT OSC_IN - PD0(7) 6 6 OSC_OUT I/O FT OSC_OUT - PD1(7) 7 7 NRST I/O - NRST - - - 8 PC0 I/O - PC0 ADC_IN10 - - 9 PC1 I/O - PC1 ADC_IN11 - - 10 PC2 I/O - PC2 ADC_IN12 - - 11 PC3 I/O - PC3 ADC_IN13 - 8 12 VSSA S - VSSA - - 9 13 VDDA S - VDDA - - 10 14 PA0-WKUP I/O - PA0 WKUP/USART2_CTS/ ADC_IN0/ TIM2_CH1_ETR(8) - 11 15 PA1 I/O - PA1 USART2_RTS/ ADC_IN1/TIM2_CH2(8) - 12 16 PA2 I/O - PA2 USART2_TX/ ADC_IN2/TIM2_CH3(8) - 13 17 PA3 I/O - PA3 USART2_RX/ ADC_IN3/TIM2_CH4(8) - - 18 VSS_4 S - VSS_4 - - - 19 VDD_4 S - VDD_4 - - 14 20 PA4 I/O - PA4 SPI1_NSS(8)/ADC_IN4 USART2_CK/ - 15 21 PA5 I/O - PA5 SPI1_SCK(8)/ADC_IN5 - (8)/ADC_IN6/ 16 22 PA6 I/O - PA6 SPI1_MISO TIM3_CH1(8) - 17 23 PA7 I/O - PA7 SPI1_MOSI(8)/ADC_IN7/ TIM3_CH2(8) - - 24 PC4 I/O - PC4 ADC_IN14 - - 25 PC5 I/O - PC5 ADC_IN15 (8) - 18 26 PB0 I/O - PB0 ADC_IN8/TIM3_CH3 19 27 PB1 I/O - PB1 ADC_IN9/TIM3_CH4(8) DS5933 Rev 7 21/81 68 Pinout and pin description STM32F102x8, STM32F102xB Table 4. Medium-density STM32F102xx pin definitions (continued) 20 28 PB2 I / O level(2) LQFP64 Pin name Alternate functions(3) (4) Type(1) LQFP48 Pins Main function(3) (after reset) I/O FT PB2/BOOT1 Default - Remap - I2C2_SCL/ USART3_TX (8) TIM2_CH3 21 29 PB10 I/O FT PB10 22 30 PB11 I/O FT PB11 I2C2_SDA/ USART3_RX(8) TIM2_CH4 23 31 VSS_1 S - VSS_1 - - 24 32 VDD_1 S - VDD_1 - - 25 33 PB12 I/O FT PB12 SPI2_NSS / I2C2_SMBA/ USART3_CK(8) - 26 34 PB13 I/O FT PB13 SPI2_SCK(8)/ USART3_CTS - 27 35 PB14 I/O FT PB14 SPI2_MISO/ USART3_RTS - 28 36 PB15 I/O FT PB15 SPI2_MOSI - - 37 PC6 I/O FT PC6 - TIM3_CH1 - 38 PC7 I/O FT PC7 - TIM3_CH2 - 39 PC8 I/O FT PC8 - TIM3_CH3 - 40 PC9 I/O FT PC9 - TIM3_CH4 29 41 PA8 I/O FT PA8 USART1_CK/MCO - 30 42 PA9 I/O FT PA9 USART1_TX(8) - (8) - 31 43 PA10 I/O FT PA10 32 44 PA11 I/O FT PA11 USART1_CTS/USB_DM - 33 45 PA12 I/O FT PA12 USART1_RTS/USB_DP - 34 46 PA13 I/O FT JTMSSWDIO - PA13 35 47 VSS_2 S - VSS_2 - - 36 48 VDD_2 S - VDD_2 - - 37 49 PA14 I/O FT JTCK/ SWCLK - PA14 38 50 PA15 I/O FT JTDI - TIM2_CH1_ETR / PA15 /SPI1_NSS - 51 PC10 I/O FT PC10 - USART3_TX - 52 PC11 I/O FT PC11 - USART3_RX - 53 PC12 I/O FT PC12 - USART3_CK - 54 PD2 I/O FT PD2 TIM3_ETR - 22/81 DS5933 Rev 7 USART1_RX STM32F102x8, STM32F102xB Pinout and pin description Table 4. Medium-density STM32F102xx pin definitions (continued) LQFP64 Pin name Type(1) I / O level(2) Alternate functions(3) (4) LQFP48 Pins Main function(3) (after reset) 39 55 PB3 I/O FT JTDO - TIM2_CH2/ PB3/ TRACESWO/ SPI1_SCK 40 56 PB4 I/O FT JNTRST - TIM3_CH1 / PB4 SPI1_MISO 41 57 PB5 I/O - PB5 I2C1_SMBA TIM3_CH2 / SPI1_MOSI 42 58 PB6 I/O FT PB6 I2C1_SCL(8)/ TIM4_CH1 USART1_TX I2C1_SDA(8)/ USART1_RX Default Remap 43 59 PB7 I/O FT PB7 44 60 BOOT0 I - BOOT0 - - 45 61 PB8 I/O FT PB8 TIM4_CH3 I2C1_SCL 46 62 PB9 I/O FT PB9 TIM4_CH4 I2C1_SDA 47 63 VSS_3 S - VSS_3 - - 48 64 VDD_3 S - VDD_3 - - TIM4_CH2 1. I = input, O = output, S = supply. 2. FT= 5 V-tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 9Table 3. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from www.st.com. 7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from www.st.com. DS5933 Rev 7 23/81 68 Memory mapping 4 STM32F102x8, STM32F102xB Memory mapping The memory map is shown in Figure 5. Figure 5. Memory map APB memory space 0xFFFF FFFF 0xE010 0000 0xFFFF FFFF 7 0xE010 0000 0xE000 0000 reserved Cortex-M3 internal peripherals 0xE000 0000 reserved 0x6000 0000 reserved 0x4002 3400 CRC 0x4002 3000 reserved 0x4002 2400 Flash interface 0x4002 2000 Cortex-M3 internal peripherals 6 3K 0x4002 1000 RCC 1K 0x4002 0400 reserved 3K 0x4002 0000 DMA 1K 0x4001 3400 reserved 1K USART1 1K reserved 1K SPI1 1K reserved 1K reserved 1K ADC1 1K reserved 2K reserved 1K 0x4001 1400 Port D 1K 0x4001 1000 Port C 1K 0x4001 0C00 Port B 1K 0x4001 0800 Port A 1K 0x4001 0400 EXTI 1K 0x4001 0000 AFIO 1K reserved 35K 0x4001 3000 0x4001 2C00 0x4001 2800 0x4001 2400 0xA000 0000 1K 0x4002 1400 0x4001 3800 5 3K reserved 0x4001 3C00 0xC000 0000 4K 1K 0x4001 1C00 4 0x4001 1800 0x1FFF FFFF reserved 0x1FFF F80F 0x8000 0000 Option Bytes 0x1FFF F800 3 System memory 0x1FFF F000 0x6000 0000 0x4000 7400 0x4000 7000 2 0x4000 0000 0x4000 6C00 reserved Peripherals 0x4000 6800 0x4000 6400 0x4000 6000 0x2000 3FFF 0x2000 0000 SRAM 0x0801FFFF 0 Flash memory 0x0000 0000 Reserved Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 1K reserved 1K reserved 1K 512 byte USB SRAM 1K USB registers 1K I2C2 1K 0x4000 5400 I2C1 1K 0x4000 4C00 reserved 2K 0x4000 4800 USART3 1K 0x4000 4400 USART2 1K reserved 2K SPI2 1K 0x4000 3400 reserved 1K 0x4000 3000 IWDG 1K 0x4000 2C00 WWDG 1K 0x4000 2800 RTC 1K reserved 7K 0x4000 0800 TIM4 1K 0x4000 0400 TIM3 1K 0x4000 0000 TIM2 1K 0x4000 3C00 0x0800 0000 1K BKP 0x4000 5800 0x4000 5C00 1 PWR 0x4000 3800 0x4000 0C00 ai14971c 24/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. DS5933 Rev 7 25/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 6. Pin loading conditions Figure 7. Pin input voltage STM32F102 pin STM32F102 pin C = 50 pF VIN ai14973 ai14972 5.1.6 Power supply scheme Figure 8. Power supply scheme VBAT GP I/Os IN VDD VDD VDD 1/2/3/4 Level shifter OUT 3 × 100 nF + 1 × 4.7 µF Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) Po wer swi tch 1.8-3.6 V IO Logic Kernel logic (CPU, Digital & Memories) Regulator VSS 1/2/3/4 VDDA VREF+ 10 nF + 1 µF ADC VREF- Analog: RCs, PLL, ... VSSA ai14882c Caution: 26/81 In Figure 8, the 4.7 µF capacitor must be connected to VDD3. DS5933 Rev 7 STM32F102x8, STM32F102xB 5.1.7 Electrical characteristics Current consumption measurement Figure 9. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5, Table 6, and Table 7 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 5. Voltage characteristics Symbol VDD −VSS VIN(2) |ΔVDDx| |VSSX − VSS| VESD(HBM) Ratings Min Max –0.3 4.0 Input voltage on 5 V-tolerant pin VSS − 0.3 VDD + 4.0 Input voltage on any other pin VSS − 0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 External main supply voltage (including VDDA and VDD)(1) Electrostatic discharge voltage (human body model) Unit V mV See Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 6 for the maximum allowed injected current values. DS5933 Rev 7 27/81 68 Electrical characteristics STM32F102x8, STM32F102xB Table 6. Current characteristics Symbol IVDD IVSS IIO IINJ(PIN) (2) ΣIINJ(PIN) Ratings Max. Total current into VDD/VDDA power lines (source)(1) 150 (1) Total current out of VSS ground lines (sink) 150 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin -25 Injected current five volt tolerant pins Unit (3) mA -5/+0 (4) ±5 Injected current on any other pin (5) Total injected current (sum of all I/O and control pins) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 8 MHz. Table 13. Maximum current consumption in Run mode, code with data processing running from RAM Max Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode External clock(2) all peripherals disabled fHCLK 48 MHz 31.5 36 MHz 24 24 MHz 17.5 16 MHz 12.5 8 MHz 7.5 48 MHz 20.5 36 MHz 16 24 MHz 11.5 16 MHz 8.5 8 MHz 5.5 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 32/81 DS5933 Rev 7 TA = 85 °C(1) Unit mA STM32F102x8, STM32F102xB Electrical characteristics Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals enabled 30 Consumption (mA) 25 20 48 MHz 36 MHz 15 16 MHz 8 MHz 10 5 0 -40 0 25 70 85 Temperature (°C) Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V), code with data processing running from RAM, peripherals disabled 20 18 Consumption (mA) 16 14 48 MHz 12 36 MHz 10 16 MHz 8 8 MHz 6 4 2 0 –40 0 25 70 85 Temperature (°C) DS5933 Rev 7 33/81 68 Electrical characteristics STM32F102x8, STM32F102xB Table 14. Max. current consumption in Sleep mode, code running from Flash memory or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C 48 MHz 20 36 MHz 15.5 24 MHz 11.5 16 MHz 8.5 8 MHz 5.5 48 MHz 6 36 MHz 5 24 MHz 4.5 16 MHz 4 8 MHz 3 mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions Regulator in Run mode. Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent Supply current watchdog) in Stop mode Regulator in Low Power mode. IDD Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator ON, independent watchdog OFF in Standby mode(2) Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current 1. Typical values are measured at TA = 25 °C. 34/81 DS5933 Rev 7 VDD/ VBAT = 2.4 V 23.5 Max VDD/VBAT VDD/VBAT TA = = 3.3 V = 2.0 V 85 °C 24 - Unit 200 µA 13.5 14 - 180 2.6 3.4 - - 2.4 3.2 - - 1.7 2 - 4 1.1 1.4 0.9 1.9(3) mA µA STM32F102x8, STM32F102xB Electrical characteristics 2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply). 3. Based on characterization, not tested in production. Figure 12. Typical current consumption on VBAT with RTC on versus temperature for different VBAT values Consumption ( µA ) 2.5 2 2V 1.5 2.4 V 1 3V 0.5 3.6 V 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17351 Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature, VDD = 3.3 / 3.6 V 140 Consumption (µA) 120 100 80 3.3 V 3.6 V 60 40 20 0 -45 25 70 90 Temperature (°C) DS5933 Rev 7 35/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature, VDD = 3.3 / 3.6 V 140 Consumption (µA) 120 100 80 3.3 V 3.6 V 60 40 20 0 -40 0 25 70 85 Temperature (°C) Figure 15. Typical current consumption in Standby mode versus temperature, VDD = 3.3 / 3.6 V Standby mode 3 Consumption (µA) 2.5 2 3.3 V 1.5 3.6 V 1 0.5 0 -45 25 70 Temperature (°C) 36/81 DS5933 Rev 7 90 STM32F102x8, STM32F102xB Electrical characteristics Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load) • All peripherals are disabled except if it is explicitly mentioned • The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz) • Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2 / 4 The parameters given in Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 16. Typical current consumption in Run mode, code with data processing running from Flash memory Symbol Parameter Conditions External clock(3) IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency Typ(1) Typ(1) All peripherals enabled(2) All peripherals disabled 48 MHz 24.2 18.6 36 MHz 19 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.8 2 MHz 2.2 1.9 1 MHz 1.6 1.45 500 kHz 1.3 1.25 125 kHz 1.08 1.06 48 MHz 23.5 17.9 36 MHz 18.3 14.1 24 MHz 12.2 9.5 16 MHz 8.5 6.8 8 MHz 4.9 4 4 MHz 2.7 2.2 2 MHz 1.6 1.4 1 MHz 1.02 0.9 500 kHz 0.73 0.67 125 kHz 0.5 0.48 fHCLK Unit mA 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). DS5933 Rev 7 37/81 68 Electrical characteristics STM32F102x8, STM32F102xB 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 17. Typical current consumption in Sleep mode, code running from Flash memory or RAM Typ(1) Symbol Parameter Conditions External clock(3) IDD Supply current in Sleep mode Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.95 48 MHz 9.3 3.3 36 MHz 7 2.5 24 MHz 4.8 1.8 16 MHz 3.2 1.2 8 MHz 1.6 0.6 4 MHz 1 0.5 2 MHz 0.72 0.47 1 MHz 0.56 0.44 500 kHz 0.49 0.42 125 kHz 0.43 0.41 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 38/81 DS5933 Rev 7 Unit mA STM32F102x8, STM32F102xB Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at VDD or VSS (no load) • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption • – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions as summarized in Table 5. Table 18. Peripheral current consumption(1) Peripheral AHB (up to 48 MHz) APB1 (up to 24 MHz) APB2 (up to 48 MHz) µA/MHz DMA1 16.53 BusMatrix(2) 8.33 APB1-Bridge 10.28 TIM2 32.50 TIM3 31.39 TIM4 31.94 SPI2 4.17 USART2 12.22 USART3 12.22 I2C1 10.00 I2C2 10.00 USB 17.78 WWDG 2.50 PWR 1.67 BKP 2.50 IWDG 11.67 APB2-Bridge 3.75 GPIOA 6.67 GPIOB 6.53 GPIOC 6.53 GPIOD 6.53 SPI1 4.72 USART1 11.94 ADC1(3) (4) 17.50 1. fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. DS5933 Rev 7 39/81 68 Electrical characteristics STM32F102x8, STM32F102xB 2. The BusMatrix is automatically active when at least one master is ON. 3. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4. 4. When ADON bit in the ADC_CR2 register is set to 1, there is an additional current consumption equal to 0.65 mA. When the ADC is enabled there is an additional current consumption of 0.05 mA. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 19. High-speed external user clock characteristics Symbol Parameter Min Typ Max Unit fHSE_ext User external clock source frequency(1) 1 8 25 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) Cin(HSE) DuCy(HSE) IL OSC_IN rise or fall Conditions - time(1) OSC_IN input capacitance(1) Duty cycle OSC_IN Input leakage current VSS ≤ VIN ≤ VDD ns - - 20 - 5 - pF 45 - 55 % - ±1 µA 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. 40/81 DS5933 Rev 7 V STM32F102x8, STM32F102xB Electrical characteristics Table 20. Low-speed external user clock characteristics Symbol Parameter fLSE_ext Min Typ Max Unit User external clock source frequency(1) - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) Cin(LSE) DuCy(LSE) IL OSC32_IN rise or fall time Conditions - (1) OSC32_IN input capacitance(1) Duty cycle VSS ≤ VIN ≤ VDD OSC32_IN Input leakage current V ns - - 50 - 5 - pF 30 - 70 % - - ±1 µA 1. Guaranteed by design, not tested in production. Figure 16. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F102xx ai14975b DS5933 Rev 7 41/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 17. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F102xx ai14976b 42/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 21. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol Conditions Min Typ Max Unit Oscillator frequency - 4 8 16 MHz RF Feedback resistor - - 200 - kΩ C Recommended load capacitance versus equivalent serial RS = 30 Ω resistance of the crystal (RS)(3) - 30 - pF i2 HSE driving current VDD = 3.3 V VIN = VSS with 30 pF load - - 1 mA gm Oscillator transconductance Startup 25 - - mA/V Startup time VDD is stabilized - 2 - ms fOSC_IN tSU(HSE)(4) Parameter 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance that is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to Oscillator design guide for ST microcontrollers (AN2867) available on www.st.com. DS5933 Rev 7 43/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF Bias controlled gain STM32F102xx OSC_OU T ai14977b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol Parameter Conditions Min Typ Max Unit - - 5 - MΩ RF Feedback resistor C(1) Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 kΩ - - 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS - - 1.4 µA gm Oscillator transconductance - 5 - - µA/V TA = 50 °C - 1.5 - TA = 25 °C - 2.5 - TA = 10 °C - 4.0 - TA = 0 °C - 6.0 - TA = -10 °C - 10.0 - TA = -20 °C - 17.0 - TA = -30 °C - 32.0 - TA = -40 °C - 60.0 - tSU(LSE)(2) Startup time VDD is stabilized s 1. Refer to the note and caution paragraphs below the table, and to Oscillator design guide for ST microcontrollers (AN2867). 2. tSU(LSE) is the startup time measured from the moment it is enabled by software to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer, PCB layout and humidity. 44/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: For a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fHSE OSC32_IN 32.768 kHz resonator RF Bias controlled gain OSC32_OUT STM32 CL2 ai17531c 5.3.7 Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. High-speed internal (HSI) RC oscillator Table 23. HSI oscillator characteristics(1) Symbol Conditions Min Typ Max Unit Frequency - - 8 - MHz DuCy(HSI) Duty cycle - 45 - 55 % - - 1(3) % –2.0 - 2.5 % –1.5 - 2.2 % –1.3 - 2 % –1.1 - 1.8 % fHSI Parameter User-trimmed with the RCC_CR register(2) ACCHSI TA = –40 to 105 °C Accuracy of the HSI TA = –10 to 85 °C oscillator Factory(4)(5) calibrated TA = 0 to 70 °C TA = 25 °C tsu(HSI)(4) HSI oscillator startup time - 1 - 2 µs IDD(HSI)(4) HSI oscillator power consumption - - 80 100 µA 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Refer to STM32F10xxx internal RC oscillator (HSI) calibration (AN2868) “” available from www.st.com. DS5933 Rev 7 45/81 68 Electrical characteristics STM32F102x8, STM32F102xB 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. 5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified range. Low-speed internal (LSI) RC oscillator Table 24. LSI oscillator characteristics (1) Symbol fLSI Parameter Frequency Min(2) Typ Max Unit 30 40 60 kHz tsu(LSI)(3) LSI oscillator startup time - - 85 µs IDD(LSI)(3) LSI oscillator power consumption - 0.65 1.2 µA 1. VDD = 3 V, TA = −40 to 85 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from Low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 25. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Wakeup from Sleep mode 1.8 Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 Unit µs 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. 46/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Table 26. PLL characteristics Value Symbol fPLL_IN fPLL_OUT Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 - 60 % PLL multiplier output clock 16 - 48 MHz tLOCK PLL lock time - - 200 µs Jitter Cycle-to-cycle jitter - - 300 ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 85 °C unless otherwise specified. Table 27. Flash memory characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog 16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs tERASE Page (1 KB) erase time TA = –40 to +85 °C 20 - 40 ms Mass erase time TA = –40 to +85 °C 20 - 40 ms Read mode fHCLK = 48 MHz with 2 wait states, VDD = 3.3 V - - 20 mA Write / Erase modes fHCLK = 48 MHz, VDD = 3.3 V - - 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V - - 50 µA - 2 - 3.6 V tME IDD Vprog Supply current Programming voltage 1. Guaranteed by design, not tested in production. Table 28. Flash memory endurance and data retention Value Symbol Parameter NEND Endurance tRET Data retention Conditions TA = 85 °C, 1000 cycles Unit Min(1) Typ Max 10 - - kcycles 30 - - Years 1. Based on characterization not tested in production. DS5933 Rev 7 47/81 68 Electrical characteristics 5.3.10 STM32F102x8, STM32F102xB EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling two LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29. EMS characteristics Symbol Parameter Conditions Level/Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK= 48 MHz conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 48 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations: the software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical data corruption (control registers, etc.) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for one second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 48/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling two LEDs through the I/O ports), This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 30. EMI characteristics Symbol Parameter SEMI 5.3.11 Peak level Monitored frequency band Conditions VDD = 3.3 V, TA = 25 °C. Max vs. [fHSE/fHCLK] Unit 8/48 MHz 0.1 MHz to 30 MHz 7 30 MHz to 130 MHz 8 130 MHz to 1GHz 13 SAE EMI Level 3.5 dBµV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming (charge device model) to ANSI/ESD STM5.3.1 II 500 Unit V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 32. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A DS5933 Rev 7 Class II level A 49/81 68 Electrical characteristics 5.3.12 STM32F102x8, STM32F102xB I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 33. Table 33. I/O current injection susceptibility Functional susceptibility Symbol IINJ 5.3.13 Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. 50/81 DS5933 Rev 7 Unit mA STM32F102x8, STM32F102xB Electrical characteristics Table 34. I/O static characteristics Symbol Parameter Conditions Standard IO input low level voltage VIL Low level input voltage IO FT(3) input low level voltage All I/Os except BOOT0 Vhys Ilkg High level input voltage Typ Max - - 0.28*(VDD-2 V)+0.8 V(1) - - 0.32*(VDD-2V)+0.75 V(1) - - 0.35VDD(2) 0.41*(VDD-2 V)+1.3 V (1) - - IO FT(3) input high level voltage 0.42*(VDD-2 V)+1 V(1) - - All I/Os except BOOT0 0.65VDD(2) - - 200 - - Standard IO Schmitt trigger voltage hysteresis(4) - IO FT Schmitt trigger voltage hysteresis(4) - 5% VDD(5) - - VSS ≤ VIN ≤ VDD Standard I/Os - - ±1 VIN = 5 V I/O FT - - 3 30 40 50 Input leakage current (6) Unit V Standard IO input high level voltage VIH Min mV µA RPU Weak pull-up equivalent resistor(7) VIN = VSS RPD Weak pull-down equivalent resistor(7) VIN = VDD 30 40 50 CIO I/O pin capacitance - - 5 - kΩ pF 1. Data based on design simulation. 2. Tested in production. 3. FT = 5-Volt tolerant, In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 5. With a minimum of 100 mV. 6. Leakage can be higher than max if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. The PMOS/NMOS contribution to the series resistance is small (~10%). DS5933 Rev 7 51/81 68 Electrical characteristics STM32F102x8, STM32F102xB All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 20 and Figure 21 for standard I/Os, and in Figure 22 and Figure 23 for 5 V tolerant I/Os. Figure 20. Standard I/O input characteristics - CMOS port VIH / VIL (V) Area not determined ent VIH uirem ard req VIH min VIL max 1.3 0.8 0.7 in Tested on producti tand MOS s C 1.71 1.08 uction 2.0 VDD 1.71 1.96 1.08 1.25 1.59 1.0 Tested in prod = 0.65 + 1.3 V (VDD - 2) VIH = 0.41 ns simulatio Based on 0.8 V + ) (VDD - 2 VIL = 0.28 t VIL = 0.35 VDD rd requiremen CMOS standa VDD (V) 2.7 3.0 3.3 3.6 MS52673V1 Figure 21. Standard I/O input characteristics - TTL port VIH / VIL (V) Area not determined VIH min TTL requirement VIH = 2.0 V 2.0 1.96 1.25 1.3 VIL max 0.8 + 1.3 V (VDD - 2) VIH = 0.41 ns o ti simula Based on 0.8 V + ) (VDD - 2 VIL = 0.28 TTL requirement VIL = 0.8 V 2.0 2.16 VDD (V) 3.6 MS52674V1 52/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Figure 22. 5 V tolerant I/O input characteristics - CMOS port VIH / VIL (V) t VIH = Area not determined VIH min 1.3 Tested ction in produ 1.42 1.07 0.975 0.75 0.7 rd standa 0.65 VDD 1.55 1.67 1.16 1.25 1.295 1.00 VIL max CMOS men require uction Tested in prod 2.0 + 1.0 V (VDD - 2) VIH = 0.42 ns simulatio Based on 0.75 V + ) (VDD - 2 VIL = 0.32 t VIL = 0.35 VDD rd requiremen CMOS standa VDD (V) 2.7 3.0 3.3 3.6 MS52672V1 Figure 23. 5 V tolerant I/O input characteristics - TTL port VIH / VIL (V) Area not determined TTL requirement VIH = 2.0 V 2.0 1.67 1.00 VIH min VIL max 0.80 0.75 + 1.0 V (VDD - 2) VIH = 0.42 ns o simulati Based on + 0.75 V ) 2 (VDD VIL = 0.32 TTL requirement VIL = 0.8 V VDD (V) 2.0 2.16 3.6 MS52675V1 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15, which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum ratings specified in Section 5.2. • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute maximum rating IVDD (see Table 6). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6). Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. DS5933 Rev 7 53/81 68 Electrical characteristics STM32F102x8, STM32F102xB Table 35. Output voltage characteristics Symbol Parameter VOL(1) Output Low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(3) Output High level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at the same time VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions Min Max CMOS port(2). IIO = +8 mA. 2.7 V < VDD < 3.6 V - 0.4 VDD–0.4 - - 0.4 2.4 - - 1.3 VDD–1.3 - - 0.4 VDD–0.4 - TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(4) 2.7 V < VDD < 3.6 V IIO = +6 mA(4) 2.0 V < VDD < 2.7 V Unit V V V V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. 54/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 24 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36. I/O AC characteristics(1) MODEx [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw Frequency(2) Output high to low level fall time Output low to high level rise time Pulse width of external signals detected by the EXTI controller Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 125 CL= 50 pF, VDD = 2 V to 3.6 V (3) 10 MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) - 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 24. 3. Guaranteed by design, not tested in production. DS5933 Rev 7 55/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 24. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 37. NRST pin characteristics Symbol VIL(NRST)(1) VIH(NRST) (1) Vhys(NRST) Conditions Min Typ Max NRST Input low level voltage - –0.5 - 0.8 NRST Input high level voltage - 2 - VDD+0.5 NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 30 40 50 kΩ - - - 100 ns - 300 - - ns Weak pull-up equivalent resistor(2) RPU VF(NRST) Parameter (1) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse Unit V 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10%). 56/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Figure 25. Recommended NRST pin protection VDD External reset circuit (1) NRST (2) RPU Internal Reset Filter 0.1 μF STM32F ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 39. Otherwise the reset will not be taken into account by the device. DS5933 Rev 7 57/81 68 Electrical characteristics 5.3.15 STM32F102x8, STM32F102xB TIM timer characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.13 for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 48 MHz 20.84 - ns - 0 fTIMxCLK/2 MHz fTIMxCLK = 48 MHz 0 24 MHz Timer resolution - - 16 bit 16-bit counter clock period when internal clock is selected - 1 65536 tTIMxCLK 1365 µs Timer resolution time Timer external clock frequency on CH1 to CH4 tMAX_COUNT Maximum possible count fTIMxCLK = 48 MHz 0.0208 - - 65536 × 65536 tTIMxCLK fTIMxCLK = 48 MHz - 89.48 s 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 5.3.16 Communications interfaces I2C interface characteristics The STM32F102xx medium-density USB access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 39. Refer also to Section 5.3.13 for more details on the input/output alternate function characteristics (SDA and SCL). 58/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Table 39. I2C characteristics Standard mode I2C(1)(2) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - - 900(3) (3) µs th(SDA) SDA data hold time - tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - µs Stop to Start condition time (bus free) 4.7 - 1.3 - µs tw(STO:STA) 3450 ns µs tSP Pulse width of spikes that are suppressed by the analog filter 0 50(4) 0 50(4) ns Cb Capacitive load for each bus line - 400 - 400 pF 1. Values guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. 4. The analog filter minimum filtered spikes is above tSP(max) to ensure that spikes width up to tSP(max) are filtered. DS5933 Rev 7 59/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 26. I2C bus AC waveforms and measurement circuit(1) VDD_I2C VDD_I2C Rp Rp STM32F10x Rs SDA I²C bus Rs SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) th(SDA) tw(SCLL) tsu(STO:STA) Stop SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14133e 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 40. SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. 60/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.13 for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics Symbol fSCK 1/tc(SCK) Parameter Conditions SPI clock frequency Min Max Master mode - 18 Slave mode - 18 - 8 ns % tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 2tPCLK - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK (1) tw(SCKH) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) (1) th(MI) th(SI)(1) ta(SO)(1)(2) tdis(SO) Data input setup time (1)(3) Data input hold time Data output disable time Slave mode 2 10 (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(SO) th(SO) (1) th(MO) (1) Data output hold time Unit MHz ns 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z DS5933 Rev 7 61/81 68 Electrical characteristics STM32F102x8, STM32F102xB Figure 27. SPI timing diagram - slave mode and CPHA=0 Figure 28. SPI timing diagram - slave mode and CPHA=1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 62/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Figure 29. SPI timing diagram - master mode(1) High NSS input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (full speed). Table 42. USB startup time Symbol tSTARTUP Parameter USB transceiver startup time DS5933 Rev 7 Max Unit 1 µs 63/81 68 Electrical characteristics STM32F102x8, STM32F102xB Table 43. USB DC electrical characteristics Symbol Conditions Min.(1) - 3.0(3) 3.6 I(USB_DP, USB_DM) 0.2 - Includes VDI range 0.8 2.5 - 1.3 2.0 - 0.3 2.8 3.6 Parameter VDD USB operating voltage(2) (4) Differential input sensitivity Input VDI (4) levels V Differential common mode range CM VSE(4) Single ended receiver threshold Output levels VOL VOH (5) RL of 1.5 kΩ to 3.6 V Static output level low RL of 15 kΩ to Static output level high VSS(5) Max.(1) Unit V V V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 30. USB timings: definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 44. USB: Full speed electrical characteristics of the driver(1) Symbol tr tf trfm VCRS Parameter Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr / tf 90 110 % - 1.3 2.0 V Rise time(2) Fall time(2) Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: 64/81 It is recommended to perform a calibration after each power-up. DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 V fADC ADC clock frequency - 0.6 - 12 MHz Sampling rate - 0.05 - 0.85 Msps fADC = 12 MHz - - 823 kHz - - - 17 1/fADC - 0 (VSSA or VREF- tied to ground) - VREF+ V See Equation 1 and Table 46 for details - - 50 κΩ (1) fS fTRIG(1) VAIN External trigger frequency Conversion voltage range(2) RAIN(1) External input impedance RADC(1) Sampling switch resistance - - - 1 κΩ CADC(1) Internal sample and hold capacitor - - - 8 pF tCAL(1) Calibration time fADC = 12 MHz 5.9 µs - 83 1/fADC tlat(1) Injection trigger conversion latency fADC = 12 MHz - - 0.214 µs - - - 3(3) 1/fADC tlatr(1) Regular trigger conversion latency fADC = 12 MHz - - 0.143 µs tS(1) Sampling time tSTAB(1) Power-up time tCONV(1) Total conversion time (including sampling time) 1/fADC - - - fADC = 12 MHz 0.125 - 19.95 µs - 1.5 - 239.5 1/fADC - 0 0 1 µs fADC = 12 MHz 1.2 - 21 µs - 2 (3) 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Guaranteed by design, not tested in production. 2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46. Equation 1: RAIN max formula: TS - – R ADC R AIN < -------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). DS5933 Rev 7 65/81 68 Electrical characteristics STM32F102x8, STM32F102xB Table 46. RAIN max for fADC = 12 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.13 0.4 7.5 0.63 5.9 13.5 1.13 11.4 28.5 2.38 25.2 41.5 3.46 37.2 55.5 4.63 50 71.5 5.96 NA 239.5 19.96 NA 1. Data guaranteed by design, not tested in production. Table 47. ADC accuracy - limited test conditions(1) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(2) fPCLK2 = 48 MHz. fADC = 12 MHz, RAIN < 10 kΩ. VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 48. ADC accuracy(1) (2) (3) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fPCLK2 = 48 MHz. fADC = 12 MHz, RAIN < 10 kΩ. VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 4. Based on characterization, not tested in production. 66/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Electrical characteristics Figure 31. ADC accuracy characteristics [1LSBIDEAL = VDDA 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET 7 (1) 6 5 4 ET=Total u nadjusted er ror: maximum deviation between the actual and the ideal transfer curves. EO=Offset e rror: deviation between the first actual transition and the first ideal one. EG=Gain er ror: deviation between the last ideal transition and the last actual one. ED=Differential linearity error: maximum deviation between actual steps and the ideal one. EL=Integral linearity error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai15497 Figure 32. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F102 Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14974b 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. DS5933 Rev 7 67/81 68 Electrical characteristics STM32F102x8, STM32F102xB General PCB design guidelines Power supply decoupling should be performed as shown in Figure 33. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 33. Power supply and reference decoupling STM32F102xx VDDA 1 µF // 10 nF VSSA ai14980b 5.3.18 Temperature sensor characteristics Table 49. TS characteristics Symbol Min Typ Max Unit VSENSE linearity with temperature - ±1.5 - °C Avg_Slope(1) Average slope - 4.35 - mV/°C V25(1) Voltage at 25°C - 1.42 - V Startup time 4 - 10 µs ADC sampling time when reading the temperature - - 17.1 µs TL(1) tSTART(2) TS_temp(3)(2) Parameter 1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 68/81 DS5933 Rev 7 STM32F102x8, STM32F102xB 6 Package characteristics Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. LQFP48 package information Figure 34. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K D A1 L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION E E1 b E3 6.1 13 1 12 e 5B_ME_V2 1. Drawing is not to scale. DS5933 Rev 7 69/81 77 Package characteristics STM32F102x8, STM32F102xB Table 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 70/81 DS5933 Rev 7 STM32F102x8, STM32F102xB Package characteristics Figure 35. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint 0.50 1.20 36 9.70 0.30 25 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. Device marking for LQFP48 Figure 36 gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. The printed markings may differ depending upon the supply chain. Figure 36. LQFP48 marking example (package top view) Product identification (1) STM32F Revision code 102C8T6 R Date code (year + week) Y Pin 1 identifier WW MS38210V1 1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. Only if ST has authorized in writing the customer qualification Engineering Samples can be used for DS5933 Rev 7 71/81 77 Package characteristics STM32F102x8, STM32F102xB reliability qualification trials. 6.2 LQFP64 package information Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 72/81 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - DS5933 Rev 7 STM32F102x8, STM32F102xB Package characteristics Table 51. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are expressed in millimeters. Device marking for LQFP64 Figure 39 is an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. The printed markings may differ depending upon the supply chain. DS5933 Rev 7 73/81 77 Package characteristics STM32F102x8, STM32F102xB Figure 39. LQFP64 marking example (package top view) Product identification (1) STM32F102 RBT6 Revision code R Date code (year + week) Y WW Pin 1 identifier MS38211V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 74/81 DS5933 Rev 7 STM32F102x8, STM32F102xB 6.3 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 52. Package thermal characteristics Symbol ΘJA 6.4 Parameter Value Thermal resistance junction-ambient LQFP48 - 7 × 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DS5933 Rev 7 75/81 77 Package characteristics 6.4.1 STM32F102x8, STM32F102xB Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in Section 7: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F102xx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 52 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C). Figure 40. LQFP64 PD max vs. TA 700 PD (mW) 600 500 400 Suffix 6 300 200 100 0 65 75 85 95 TA (°C) 76/81 DS5933 Rev 7 105 115 STM32F102x8, STM32F102xB 7 Ordering information scheme Ordering information scheme Example: STM32 F 102 C 8 T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 102 = USB access line, USB 2.0 full-speed interface Pin count C = 48 pins R = 64 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Options xxx = programmed parts TR = tape and reel DS5933 Rev 7 77/81 77 Revision history 8 STM32F102x8, STM32F102xB Revision history Table 53. Document revision history Date Revision 23-Sep-2008 1 Initial release. 2 I/O information clarified on page 1. Figure 1: STM32F102T8 mediumdensity USB access line block diagram and Figure 5: Memory map modified. In Table 4: Medium-density STM32F102xx pin definitions: PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column. PD value added for LQFP64 package in Table 8: General operating conditions. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 13, Figure 14 and Figure 15 show typical curves. Figure 31: ADC accuracy characteristics modified. Figure 33: Power supply and reference decoupling modified. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 24: HSI oscillator characteristics. Small text changes. 3 Note 5. updated in Table 4: Medium-density STM32F102xx pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 12: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings. Note 1. modified below Figure 18: Typical application with an 8 MHz crystal. Figure 25: Recommended NRST pin protection modified. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 48. Jitter added to Table 27: PLL characteristics. Table 43: SPI characteristics modified. CADC and RAIN parameters modified in Table 47: ADC characteristics. RAIN max values modified in Table 48: RAIN max for fADC = 12 MHz. Small text changes. 23-Apr-2009 22-Sep-2009 78/81 Changes DS5933 Rev 7 STM32F102x8, STM32F102xB Revision history Table 53. Document revision history (continued) Date 27-Sep-2012 Revision Changes 4 Figure 2: Clock tree: added FLITFCLK and Note 3., and modified Note 1.. Updated Note 2. in Table 41: I2C characteristics. Updated Figure 25: Recommended NRST pin protection. Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), tf(SCK) to tf(SCL), and tsu(STA:STO) to tw(STO:STA) in Figure 26: I2C bus AC waveforms and measurement circuit(1). Changed note for Ilkg and RPU and updated Note 1.content in Table 36: I/O static characteristics. Updated text related to CMOS and TTL compliance and added Figure 20, Figure 21, Figure 22, and Figure 23. Updated Section : Output driving current. In Table 43: SPI characteristics, removed note 1 related to SPI1 remapped characteristics. Added DuCy(HSI) in Table 24: HSI oscillator characteristics. Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz): removed note 2 related to oscillator selection, updated Note 2., and tSU(LSE) specified for various ambient temperature values. Updated Note 2. and Note 3. below Figure 35: Recommended footprint (dimensions in mm)(1)(2)(3). Table 37: Output voltage characteristics: updated VOL and VOH conditions for TTL and CMOS outputs and added Note 2.. Replaced “TBD” by “-” for “max” specification of “Supply current in Standby mode” in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Removed “except for analog inputs” from paragraph “GPIOS (generalpurpose inputs/outputs) in Chapter 2.3: Overview. Updated tw(HSE) min value in Table 20: High-speed external user clock characteristics. Added Note 2. in Table 5: Voltage characteristics. Updated Note 3., Note 4. and Note 5. in Table 6: Current characteristics. Updated Note 1. in Table 38: I/O AC characteristics. Added Chapter 5.3.12: I/O current injection characteristics. Updated Note 2. in Table 41: I2C characteristics. Updated “Output driving current” paragraph in Chapter 5.3.13: I/O port characteristics. Removed Note 4 and updated Note 3. in Table 41: I2C characteristics. Updated Figure 29: SPI timing diagram - master mode(1) (SCK Output instead of Input). Replaced every occurrence of USBDP or USBDM by USB_DP or USB_DM, respectively. DS5933 Rev 7 79/81 80 Revision history STM32F102x8, STM32F102xB Table 53. Document revision history (continued) Date 02-Aug-2013 03-Jun-2015 12-Aug-2019 80/81 Revision Changes 5 Removed sentence in “Unless otherwise specified the parameters ...” in I2C interface characteristics section. Added VIN in Table 8: General operating conditions. Added note 5 in Table 23: HSI oscillator characteristics Modified charge device model in Table 33: ESD absolute maximum ratings Updated ‘VIL’ and ‘VIH’ in Table 34: I/O static characteristics Added notes to Figure 20: Standard I/O input characteristics - CMOS port, Figure 21: Standard I/O input characteristics - TTL port, Figure 22: 5 V tolerant I/O input characteristics - CMOS port and Figure 23: 5 V tolerant I/O input characteristics - TTL port Updated Figure 24: I/O AC characteristics definition Updated note 2. and 3. in Table 39: I2C characteristics Updated Figure 26: I2C bus AC waveforms and measurement circuit(1) Updated title of Table 40: SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V) Updated Table 47: ADC characteristics Updated Section 6.1: Package mechanical data 6 Updated Table 18: Peripheral current consumption and Table 39: I2C characteristics Updated Section 6: Package characteristics Updated Section 6.2: LQFP64 package information with addition of Device marking for LQFP64 and Figure 39. Updated Section 6.1: LQFP48 package information with addition of Device marking for LQFP48 and Figure 36. Updated Disclaimer. 7 Updated Section 1: Introduction, Section 5.2: Absolute maximum ratings, Device marking for LQFP48 and Device marking for LQFP64. Updated Figure 19: Typical application with a 32.768 kHz crystal, Figure 20: Standard I/O input characteristics - CMOS port, Figure 21: Standard I/O input characteristics - TTL port, Figure 22: 5 V tolerant I/O input characteristics - CMOS port and Figure 23: 5 V tolerant I/O input characteristics - TTL port. Minor text edits across the whole document. DS5933 Rev 7 STM32F102x8, STM32F102xB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS5933 Rev 7 81/81 81