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STM32F102R4T6XXX

STM32F102R4T6XXX

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

  • 描述:

    STM32F102R4T6XXX - Low-density USB access line, ARM-based 32-bit MCU with 16/32 KB Flash, USB FS int...

  • 数据手册
  • 价格&库存
STM32F102R4T6XXX 数据手册
STM32F102x4 STM32F102x6 Low-density USB access line, ARM-based 32-bit MCU with 16/32 KB Flash, USB FS interface, 5 timers, ADC & 5 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 WS memory access – Single-cycle multiplication and hardware division Memories – 16 or 32 Kbytes of Flash memory – 4 or 6 Kbytes of SRAM Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers Debug mode – Serial wire debug (SWD) and JTAG interfaces DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 × 12-bit, 1.2 µs A/D converter (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor Up to 51 fast I/O ports – 37/51 IOs all mappable on 16 external interrupt vectors and almost all 5 V-tolerant ■ LQFP64 10 × 10 mm LQFP48 7 × 7 mm ■ ■ Up to 5 timers – Two 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 2 watchdog timers (Independent and Window) – SysTick timer: 24-bit downcounter Up to 5 communication interfaces – 1 x I2C interface (SMBus/PMBus) – 2 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – 1 SPI (12 Mbit/s) – USB 2.0 full speed interface CRC calculation unit, 96-bit unique ID ECOPACK® packages Device summary Part number STM32F102C4, STM32F102R4 STM32F102C6, STM32F102R6 ■ ■ ■ ■ ■ Table 1. Reference STM32F102x4 STM32F102x6 ■ ■ ■ September 2009 Doc ID 15057 Rev 3 1/69 www.st.com 1 Contents STM32F102x4, STM32F102x6 Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 5 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27 Embedded reset and power control block characteristics . . . . . . . . . . . 28 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 46 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 Contents NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1 6.2 6.3 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.1 Evaluating the maximum junction temperature for an application . . . . . 66 7 8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15057 Rev 3 3/69 List of tables STM32F102x4, STM32F102x6 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F102x4 and STM32F102x6 low-density USB access line features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 low-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 32 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 32 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 36 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. List of tables RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 63 LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 64 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15057 Rev 3 5/69 List of figures STM32F102x4, STM32F102x6 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. STM32F102xx low-density USB access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM32F102xx low-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F102xx low-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 18 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 31 Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 31 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 63 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 64 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F102x4 and STM32F102x6 low-density USB access line microcontrollers. For more details on the whole STMicroelectronics STM32F102xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F102xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 15057 Rev 3 7/69 Description STM32F102x4, STM32F102x6 2 Description The STM32F102xx low-density USB access line incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory of 16 or 32 Kbytes and SRAM of 4 or 6 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (one I2C, one SPI, one USB and two USARTs), one 12bit ADC and two general-purpose 16-bit timers. The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of lowpower applications. The STM32F102xx low-density USB access line is delivered in the LQFP48 7 × 7 mm and LQFP64 10 × 10 mm packages. The STM32F102xx low-density USB access line microcontrollers are suitable for a wide range of applications: ● ● ● ● ● Application control and user interface Medical and handheld equipment PC peripherals, gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 8/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Description 2.1 Device overview Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features and peripheral counts Peripheral Flash - Kbytes SRAM - Kbytes Timers General-purpose SPI Communication interfaces IC USART USB 12-bit synchronized ADC number of channels GPIOs CPU frequency Operating voltage Operating temperatures Packages 2 STM32F102Cx 16 4 2 1 1 2 1 1 10 channels 37 48 MHz 2.0 to 3.6 V 32 6 2 1 1 2 1 STM32F102Rx 16 4 2 1 1 2 1 1 16 channels 51 32 6 2 1 1 2 1 Ambient temperature: –40 to +85 °C (see Table 8) Junction temperature: –40 to +105 °C (see Table 8) LQFP48 LQFP64 Doc ID 15057 Rev 3 9/69 Description Figure 1. STM32F102x4, STM32F102x6 STM32F102xx low-density USB access line block diagram TRACECLK TRACED[0:3] as AS TPIU SW/JTAG Trace/trig SWD Cortex M3 CPU Fmax: 48 MHz NVIC NVIC Dbus Ibus Flash obl Inte rface JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF pbus Trace Controller ont POWER VOLT. REG. 3.3 V to 1.8 V @VDD VDD = 2 t o 3.6 V VSS Flash 32 KB 64 bit BusM atrix Syst em SRAM 6 KB PCLK1 PCLK 2 HCLK FCLK RC 8 MHz RC 40 kHz @VDDA @VBAT PLL & CLOCK MANAGT @VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT GP DMA 7 channels AHB: Fmax =48 MHz IWDG Stand by in terface @VDDA SUPPLY SUPERVISION POR / PDR PVD Rst Int VBAT OSC32_IN OSC32_OUT TAMPER-RTC NRST VDDA VSSA XTAL 32 kHz AHB2 APB2 AHB2 APB 1 RTC AWU Backup reg 51AF PA[ 15:1] PB[ 15:0] PC[15:0] PD[2:0] MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, Smart Card as AF EXTI WAKEUP GPIOA APB 1: Fmax = 24 MHz Backup interface TIM2 TIM3 USART2 I2C 4 Chann els 4 Chann els RX,TX, CTS, RTS, CK, SmartCard as AF SCL,SDA,SMBA L as AF GPIOB GPIOC GPIOD APB2 : Fmax = 48 MHz SPI USART1 USB 2.0 FS WWDG USBDP, USBDM as AF @VDDA 16AF 12bit ADC1 IF Temp sen so r ai15452b 1. AF = alternate function on I/O port pin. 2. TA = –40 °C to +85 °C (junction temperature up to 105 °C). 10/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Figure 2. Clock tree 8 MHz HSI RC Description HSI /2 USB Prescaler /1, 1.5 48 MHz USBCLK to USB interface HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock Enable (13 bits) 48 MHz max Clock Enable (3 bits) PLLSRC PLLMUL ..., x16 x2, x3, x4 PLL HSI PLLCLK HSE SW SYSCLK /8 48 MHz /1, 2..512 max AHB Prescaler APB1 Prescaler /1, 2, 4, 8, 16 24 MHz max CSS to TIM2, TIM3 TIM2, TIM3 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock Enable (2 bits) PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 APB2 Prescaler /1, 2, 4, 8, 16 48 MHz max Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz LSE to RTC ADC Prescaler /2, 4, 6, 8 RTCCLK to ADC ADCCLK RTCSEL[1:0] LSI RC 40 kHz LSI to Independent Watchdog (IWDG) IWDGCLK Legend: Main Clock Output /2 PLLCLK HSI HSE SYSCLK MCO HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal MCO ai15455 1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at 48 MHz. 2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz. Doc ID 15057 Rev 3 11/69 Description STM32F102x4, STM32F102x6 2.2 Full compatibility throughout the family The STM32F102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred to as medium-density devices. Low-density devices are an extension of the STM32F102x8/B devices, they are specified in the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM capacities, a timer and a few communication interfaces less. The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx access line and STM32F103xx performance line devices. Table 3. STM32F102xx USB access line family Low-density STM32F102xx devices Pinout 16 KB Flash 4 KB RAM 64 48 32 KB Flash(1) 6 KB RAM Medium-density STM32F102xx devices 64 KB Flash 10 KB RAM 128 KB Flash 16 KB RAM 2 × USARTs, 2 × 16-bit timers 1 × SPI, 1 × I2C, 1 × ADC, 1 × USB 3 × USARTs, 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices. 2.3 Overview ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F102xx low-density USB access line having an embedded ARM core, is therefore compatible with all ARM tools and software. Embedded Flash memory 16 or 32 Kbytes of embedded Flash is available for storing programs and data. 12/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Description CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. Embedded SRAM 4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F102xx low-density USB access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● ● ● ● ● ● ● ● Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 48 MHz. See Figure 2 for details on the clock tree. Doc ID 15057 Rev 3 13/69 Description STM32F102x4, STM32F102x6 Boot modes At startup, boot pins are used to select one of five boot options: ● ● ● Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. Power supply schemes ● ● VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. ● For more details on how to connect power pins, refer to Figure 8: Power supply scheme. Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● ● ● MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 14/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Description Low-power modes The STM32F102xx low-density USB access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare Doc ID 15057 Rev 3 15/69 Description STM32F102x4, STM32F102x6 register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: ● ● ● ● A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source General-purpose timers (TIMx) There are 2 synchronizable general-purpose timers embedded in the STM32F102xx lowdensity USB access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one-pulse mode output. This gives up to 12 input captures / output compares / PWMs on the LQFP48 and LQFP64 packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They both have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. I²C bus One I²C bus interface can operate in multi-master and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. The I2C interface can be served by DMA and they support SM Bus 2.0/PM Bus. 16/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Description Universal synchronous/asynchronous receiver transmitter (USART) The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. Serial peripheral interface (SPI) The SPI is able to communicate up to 12 Mbit/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPI can be served by the DMA controller. Universal serial bus (USB) The STM32F102xx low-density USB access line embeds a USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. ADC (analog to digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. Temperature sensor The temperature sensor has to generate a a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Doc ID 15057 Rev 3 17/69 Pinouts and pin description STM32F102x4, STM32F102x6 3 Pinouts and pin description Figure 3. STM32F102xx low-density USB access line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14378d Figure 4. STM32F102xx low-density USB access line LQFP64 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14387c 18/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Table 4. Pins LQFP48 LQFP64 Pin name Pinouts and pin description low-density STM32F102xx pin definitions I / O level(2) Main function(3) (after reset) VBAT PC13(6) PC14 PC15 FT FT (6) (6) Type(1) Alternate functions(3) (4) Default Remap 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VBAT PC13-TAMPER-RTC (5) S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O TAMPER-RTC OSC32_IN OSC32_OUT PC14-OSC32_IN(5) PC15-OSC32_OUT PD0 PD1 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP (5) OSC_IN(7) OSC_OUT(7) NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0 WKUP/USART2_CTS/ ADC_IN0/ TIM2_CH1_ETR(8) USART2_RTS/ ADC_IN1/TIM2_CH2(8) USART2_TX/ ADC_IN2/TIM2_CH3(8) USART2_RX/ ADC_IN3/TIM2_CH4(8) ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13 11 12 13 14 15 16 17 18 19 20 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O FT PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 SPI_NSS(8)/ADC_IN4 USART2_CK/ SPI_SCK(8)/ADC_IN5 SPI_MISO(8)/ADC_IN6/ TIM3_CH1(8) SPI_MOSI(8)/ADC_IN7/ TIM3_CH2(8) ADC_IN14 ADC_IN15 ADC_IN8/TIM3_CH3(8) ADC_IN9/TIM3_CH4(8) Doc ID 15057 Rev 3 19/69 Pinouts and pin description Table 4. Pins LQFP48 LQFP64 Pin name STM32F102x4, STM32F102x6 low-density STM32F102xx pin definitions (continued) I / O level(2) Main function(3) (after reset) PB10 PB11 VSS_1 VDD_1 FT FT FT FT FT FT FT FT FT FT FT FT FT FT PB12 PB13 PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMS-SWDIO VSS_2 VDD_2 FT FT FT FT FT FT FT JTCK/SWCLK JTDI PC10 PC11 PC12 PD2 JTDO TIM2_CH2/ PB3/ TRACESWO/ SPI_SCK TIM3_CH1 / PB4 SPI_MISO I2C_SMBA TIM3_CH2 / SPI_MOSI PA14 TIM2_CH1_ETR/ PA15 /SPI_NSS USART1_CK/MCO USART1_TX(8) USART1_RX(8) USART1_CTS/USBDM USART1_RTS/USBDP PA13 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 (8) Type(1) Alternate functions(3) (4) Default (8) (8) Remap TIM2_CH3 TIM2_CH4 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD2 PB3 I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O FT FT 40 41 56 57 PB4 PB5 I/O I/O FT JNTRST PB5 20/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Table 4. Pins LQFP48 LQFP64 Pin name Pinouts and pin description low-density STM32F102xx pin definitions (continued) I / O level(2) Main function(3) (after reset) PB6 PB7 BOOT0 FT FT PB8 PB9 VSS_3 VDD_3 I2C_SCL I2C_SDA Type(1) Alternate functions(3) (4) Default I2C_SCL(8) I2C_SDA(8) Remap USART1_TX USART1_RX 42 43 44 45 46 47 48 58 59 60 61 62 63 64 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 I/O I/O I I/O I/O S S FT FT 1. I = input, O = output, S = supply. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 3 on page 12. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the STMicroelectronics website: www.st.com. 7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. Doc ID 15057 Rev 3 21/69 Memory mapping STM32F102x4, STM32F102x6 4 Memory mapping The memory map is shown in Figure 5. Figure 5. Memory map APB memory space reserved 0xFFFF FFFF 0xFFFF FFFF 0xE010 0000 Cortex-M3 internal peripherals 0xE000 0000 0x4002 3400 reserved CRC reserved Flash interface reserved RCC reserved DMA reserved USART1 reserved SPI reserved reserved ADC1 reserved Port D Port C Port B Port A EXTI AFIO reserved PWR BKP reserved 512 byte USB SRAM USB registers reserved I2C reserved USART2 reserved IWDG WWDG RTC reserved TIM3 TIM2 7 0xE010 0000 0xE000 0000 Cortex-M3 internal peripherals 0x4002 3000 0x4002 2400 0x4002 2000 0x4002 1400 6 0xC000 0000 0x4002 1000 0x4002 0400 0x4002 0000 0x4001 3C00 0x4001 3800 5 0xA000 0000 0x4001 3400 0x4001 3000 0x4001 2C00 0x4001 2800 0x4001 2400 0x4001 1800 reserved 4 0x8000 0000 0x1FFF FFFF 0x1FFF F80F 0x4001 1400 0x4001 1000 0x4001 0C00 0x4001 0800 Option Bytes 0x1FFF F800 3 0x1FFF F000 0x6000 0000 System memory 0x4001 0400 0x4001 0000 0x4000 7400 0x4000 7000 2 0x4000 0000 Peripherals reserved 0x4000 6C00 0x4000 6400 0x4000 6000 0x4000 5C00 0x4000 5800 1 0x2000 17FF 0x2000 0000 SRAM 0x0800 FFFF 0x4000 5400 0x4000 4800 0x4000 4400 0x4000 3400 0x4000 3000 Flash memory 0x0800 0000 0x4000 2C00 0x4000 2800 0x4000 0800 0x4000 0400 0x4000 0000 0 0x0000 0000 Reserved Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins ai15454b 22/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics 5 5.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V  VDD  3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Doc ID 15057 Rev 3 23/69 Electrical characteristics STM32F102x4, STM32F102x6 Figure 6. Pin loading conditions Figure 7. Pin input voltage STM32F102 pin C = 50 pF VIN STM32F102 pin ai14972 ai14973 5.1.6 Power supply scheme Figure 8. Power supply scheme VBAT 1.8-3.6 V Po wer swi tch Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4 VSS 1/2/3/4 Regulator 3 × 100 nF + 1 × 4.7 µF VDD VDDA VREF+ 10 nF + 1 µF VSSA ADC VREF- Analog: RCs, PLL, ... ai14882c Caution: In Figure 8, the 4.7 µF capacitor must be connected to VDD3. 24/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics 5.1.7 Current consumption measurement Figure 9. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Symbol VDD VSS VIN |VDDx| |VSSX VSS| Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min –0.3 VSS  0.3 VSS 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit VESD(HBM) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VINVDD while a negative injection is induced by VIN 8 MHz. Table 13. Maximum current consumption in Run mode, code with data processing running from RAM Max Parameter Conditions fHCLK 48 MHz 36 MHz External clock (2), all peripherals enabled 24 MHz 16 MHz Unit Symbol TA = 85 °C(1) 27 20 14 10 6 IDD Supply current in Run mode External clock(2) all peripherals disabled 8 MHz 48 MHz 36 MHz 24 MHz 16 MHz 8 MHz mA 19 15 10 7 5 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 30/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled 30 25 Consumption (mA) 20 48 MHz 15 36MHz 16 MHz 8 MHz 10 5 0 –40 °C 25 °C 0 °C Temperature (°C) 70 °C 85 °C Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled 20 18 16 Consumption (mA) 14 12 10 8 6 4 2 0 –40 °C 25 °C 0 °C Temperature (°C) 70 °C 85 °C 48 MHz 36 MHz 16 MHz 8 MHz Doc ID 15057 Rev 3 31/69 Electrical characteristics Table 14. Symbol STM32F102x4, STM32F102x6 Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Parameter Conditions fHCLK TA = 85 °C 48 MHz 36 MHz External clock(2) all peripherals enabled 24 MHz 16 MHz 17 14 10 7 4 mA 48 MHz 36 MHz External clock(2), all peripherals disabled 24 MHz 16 MHz 8 MHz 6 5 4.5 4 3 Unit IDD Supply current in Sleep mode 8 MHz 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Symbol Typical and maximum current consumptions in Stop and Standby modes Typ(1) Parameter Conditions Max Unit VDD/ VBAT VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.3 V = 2.0 V 85 °C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator ON, independent watchdog OFF in Standby mode(2) Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Backup domain Low-speed oscillator and RTC ON supply current 21.3 21.7 - 160 11.3 11.7 - 145 IDD 2.75 2.55 3.4 3.2 - - µA 1.55 1.9 - 3.2 1.1 1.4 0.9 1.9(3) 1. Typical values are measured at TA = 25 °C. 2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply). 3. Based on characterization, not rested in production. 32/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Figure 12. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values 2.5 Consumption ( µA ) 2 1.5 1 0.5 0 –40 °C 25 °C 70 °C Temperature (°C) ai17351 2V 2.4 V 3V 3.6 V 85 °C 105 °C Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 45 40 35 Consumption (µA) 30 25 20 15 10 5 0 –45 °C 25 °C Temperature (°C) 85 °C 3.3 V 3.6 V Doc ID 15057 Rev 3 33/69 Electrical characteristics STM32F102x4, STM32F102x6 Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 30 25 Consumption (µA) 20 3.3 V 3.6 V 15 10 5 0 –45 °C 25 °C Temperature (°C) 85 °C Figure 15. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 3.5 3 2.5 Consumption (µA) 2 1.5 1 0.5 0 –45 °C 25 °C 85 °C Temperature (°C) 3.3 V 3.6 V 34/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● ● ● ● ● All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz) Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 The parameters given in Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 16. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions fHCLK All peripherals enabled(2) 21.9 17.2 11.2 8.1 5 3 2 1.5 1.2 1.05 21.2 16.5 10.5 7.4 4.3 2.4 1.5 1 0.7 0.5 Typ(1) All peripherals disabled 17.4 13.8 8.9 6.6 4.2 2.6 1.8 1.4 1.2 1 16.7 13.1 8.2 5.9 3.6 2 1.3 0.9 0.65 0.45 mA Unit 48 MHz 36 MHz 24 MHz 16 MHz External clock(3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 15057 Rev 3 35/69 Electrical characteristics Table 17. STM32F102x4, STM32F102x6 Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Typ(1) Unit Parameter Conditions fHCLK Symbol All peripherals All peripherals enabled(2) disabled 8.7 6.7 4.8 3.4 2 1.5 1.25 1.1 1.05 1 8.1 6.1 4.2 2.8 1.4 0.9 0.7 0.55 0.48 0.4 3.8 3.1 2.3 1.8 1.2 1.1 1 0.98 0.96 0.95 48 MHz 36 MHz 24 MHz 16 MHz External clock(3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 48 MHz 36 MHz 24 MHz Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. mA 3.2 2.5 1.7 1.2 0.55 0.5 0.45 0.42 0.4 0.38 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 36/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions: ● ● ● all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption – – with all peripherals clocked off with only one peripheral clocked on ● ambient operating temperature and VDD supply voltage conditions summarized in Table 5. Peripheral current consumption Peripheral TIM2 TIM3 Typical consumption at 25 °C(1) 0.6 0.6 0.21 0.65 0.18 0.21 mA GPIO B GPIO C 0.21 0.21 0.21 1.4 0.24 0.35 Unit Table 18. APB1 USART2 USB I2C GPIO A APB2 GPIO D ADC SPI USART (2) 1. fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. Doc ID 15057 Rev 3 37/69 Electrical characteristics STM32F102x4, STM32F102x6 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 19. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) DuCy(HSE) IL High-speed external user clock characteristics Parameter User external clock source frequency OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) Duty cycle OSC_IN Input leakage current VSS  VIN  VDD 45 5 55 ±1 (1) Conditions Min 1 0.7VDD VSS 16 Typ 8 Max 25 VDD 0.3VDD Unit MHz V ns 20 pF % µA 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 20. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) DuCy(LSE) IL Low-speed external user clock characteristics Parameter User external clock source frequency(1) 0.7VDD VSS 450 ns OSC32_IN rise or fall time(1) OSC32_IN input capacitance(1) Duty cycle OSC32_IN Input leakage current VSS  VIN  VDD 30 5 70 ±1 50 pF % µA Conditions Min Typ 32.768 Max 1000 VDD 0.3VDD Unit kHz V OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) 1. Guaranteed by design, not tested in production. 38/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Figure 16. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t External clock source fHSE_ext OSC _IN IL STM32F102xx ai14975b Figure 17. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t External clock source fLSE_ext OSC32_IN IL STM32F102xx ai14976b Doc ID 15057 Rev 3 39/69 Electrical characteristics STM32F102x4, STM32F102x6 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 21. Symbol fOSC_IN RF C HSE 4-16 MHz oscillator characteristics(1)(2) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial RS = 30 resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance Startup time VDD = 3.3 V VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF i2 gm tSU(HSE) (4) 1 mA mA/V ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. 40/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain Electrical characteristics fHSE STM32F102xx ai14977b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. Symbol RF C(1) LSE oscillator characteristics (fLSE = 32.768 kHz) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(2) LSE driving current Oscillator transconductance Startup time VDD is stabilized RS = 30 k VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF I2 gm tSU(LSE)(3) 1.4 µA µA/V s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Doc ID 15057 Rev 3 41/69 Electrical characteristics Caution: STM32F102x4, STM32F102x6 To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL  7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F102xx fLSE ai14978b 5.3.7 Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. High-speed internal (HSI) RC oscillator Table 23. Symbol fHSI HSI oscillator characteristics(1) Parameter Frequency User-trimmed with the RCC_CR register(2) Conditions Min Typ 8 1(3) –2 –1.5 –1.3 –1.1 1 80 2.5 2.2 2 1.8 2 100 Max Unit MHz % % % % % µs µA ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) TA = –40 to 105 °C TA = –10 to 85 °C TA = 0 to 70 °C TA = 25 °C tsu(HSI)(4) IDD(HSI)(4) HSI oscillator startup time HSI oscillator power consumption 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. 42/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics low-speed internal (LSI) RC oscillator Table 24. Symbol fLSI tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 LSI oscillator characteristics (1) Parameter Min(2) 30 Typ 40 Max 60 85 1.2 Unit kHz µs µA 1. VDD = 3 V, TA = 40 to 85 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● ● Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 25. Low-power mode wakeup timings Parameter Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(1) tWUSTDBY(1) Wakeup from Stop mode (regulator in low-power mode) Wakeup from Standby mode Typ 1.8 3.6 µs 5.4 50 µs Unit µs Symbol tWUSLEEP(1) 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26. Symbol PLL characteristics Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8.0 Max(1) 25 60 48 Unit MHz % MHz fPLL_IN fPLL_OUT PLL input clock duty cycle PLL multiplier output clock Doc ID 15057 Rev 3 43/69 Electrical characteristics Table 26. Symbol tLOCK Jitter PLL lock time Cycle-to-cycle jitter STM32F102x4, STM32F102x6 PLL characteristics (continued) Value Parameter Min(1) Typ Max(1) 200 300 Unit µs ps 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 85 °C unless otherwise specified. Table 27. Symbol tprog tERASE tME Flash memory characteristics Parameter 16-bit programming time Page (1 KB) erase time Mass erase time Conditions TA–40 to +85 °C TA –40 to +85 °C TA –40 to +85 °C Read mode fHCLK = 48 MHz with 2 wait states, VDD = 3.3 V Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 20 Unit µs ms ms mA IDD Supply current Write / Erase modes fHCLK = 48 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V 5 mA 50 2 3.6 µA V Vprog Programming voltage 1. Guaranteed by design, not tested in production. Table 28. Symbol NEND tRET Flash memory endurance and data retention Value Parameter Endurance Data retention TA = 85 °C, 1000 cycles Conditions Min(1) 10 30 Unit Typ Max kcycles Years 1. Based on characterization not tested in production. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 44/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29. Symbol VFESD EMS characteristics Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Conditions VDD 3.3 V, TA +25 °C, fHCLK 48 MHz conforms to IEC 61000-4-2 VDD3.3 V, TA +25 °C, fHCLK 48 MHz conforms to IEC 61000-4-4 Level/Class 2B VEFTB 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations: the software flowchart must include the management of runaway conditions such as: ● ● ● Corrupted program counter Unexpected reset Critical Data corruption (control registers, etc.) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Doc ID 15057 Rev 3 45/69 Electrical characteristics Table 30. EMI characteristics Conditions STM32F102x4, STM32F102x6 Symbol Parameter Monitored frequency band 0.1 MHz to 30 MHz Max vs. [fHSE/fHCLK] Unit 8/48 MHz 7 8 13 3.5 dBµV SEMI Peak level VDD 3.3 V, TA 25 °C, 30 MHz to 130 MHz 130 MHz to 1GHz SAE EMI Level 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31. Symbol VESD(HBM) VESD(CDM) ESD absolute maximum ratings Ratings Conditions Class 2 II Maximum value(1) 2000 V 500 Unit Electrostatic discharge voltage TA +25 °C, conforming (human body model) to JESD22-A114 Electrostatic discharge voltage TA +25 °C, conforming (charge device model) to JESD22-C101 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● ● A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 32. Symbol LU Electrical sensitivities Parameter Static latch-up class Conditions TA +105 °C conforming to JESD78A Class II level A 46/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 33. Symbol VIL VIH VIL VIH I/O static characteristics Parameter Conditions Min –0.5 TTL ports 2 2 –0.5 CMOS ports 0.65 VDD 200 5% VDD(3) VSS  VIN  VDD Standard I/Os VIN = 5 V, I/O FT 1 µA 3 30 30 40 40 5 50 50 k k pF Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit Input low level voltage Standard IO input high level voltage IO FT(1) input high level voltage Input low level voltage Input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) Vhys IO FT Schmitt trigger voltage hysteresis(2) (3) Ilkg Input leakage current RPU RPD CIO Weak pull-up equivalent resistor(4) Weak pull-down equivalent resistor(5) I/O pin capacitance VIN VSS VIN VDD 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: ● For VIH: – – if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included ● For VIL: – – Doc ID 15057 Rev 3 47/69 Electrical characteristics STM32F102x4, STM32F102x6 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 6). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6). ● Output voltage levels Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34. Symbol VOL(1) VOH(2) VOL(1) VOH(2) VOL(1) VOH (2) VOL(1) VOH(2) Output voltage characteristics Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD–0.4 0.4 V 2.4 1.3 V VDD–1.3 0.4 V VDD–0.4 Unit IIO = +20 mA(3) 2.7 V < VDD < 3.6 V IIO = +6 mA(3) 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 48/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 20 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 35. MODEx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125 CL= 50 pF, VDD = 2 V to 3.6 V (3) Unit MHz fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time ns fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time 10 25(3) MHz CL= 50 pF, VDD = 2 V to 3.6 V 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) 10 ns MHz MHz MHz Fmax(IO)out Maximum Frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V ns tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V - tEXTIpw ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 20. 3. Guaranteed by design, not tested in production. Doc ID 15057 Rev 3 49/69 Electrical characteristics Figure 20. I/O AC characteristics definition 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out T 10% STM32F102x4, STM32F102x6 50% 90% tr(I O)out Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33). Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36. Symbol VIL(NRST)(1) VIH(NRST)(1) Vhys(NRST) RPU VF(NRST)(1) VNF(NRST)(1) NRST pin characteristics Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse 300 VIN VSS 30 Conditions Min –0.5 2 200 40 50 100 Typ Max 0.8 V VDD+0.5 mV k ns ns Unit 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 21. Recommended NRST pin protection VDD NRST(2) RPU Filter 0.1 µF Internal Reset External reset circuit(1) STM32F10xxx ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device. 50/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics 5.3.14 TIM timer characteristics The parameters given in Table 37 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 37. Symbol tres(TIM) TIMx(1) characteristics Parameter Timer resolution time fTIMxCLK = 48 MHz Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period when internal clock is selected 1 fTIMxCLK = 48 MHz 0.0208 20.84 0 fTIMxCLK = 48 MHz 0 fTIMxCLK/2 24 16 65536 1365 65536 × 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count fTIMxCLK = 48 MHz 89.48 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 5.3.15 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8. The STM32F102xx low-density USB access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Doc ID 15057 Rev 3 51/69 Electrical characteristics Table 38. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb STM32F102x4, STM32F102x6 I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0 (3) Unit Max Min 1.3 µs 0.6 100 0(4) 1000 300 0.6 µs 0.6 0.6 1.3 400 µs µs pF 20+0.1Cb 900(3) 300 300 ns Max 1. Values guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 52/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics Figure 22. I2C bus AC waveforms and measurement circuit(1) VDD 4 .7 kΩ I²C bus VDD 4 .7 kΩ 100 Ω 100 Ω STM32F102xx SDA SCL S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai14979 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2) fSCL (kHz) 400 300 200 100 50 20 I2C_CCR value RP = 4.7 k 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 15057 Rev 3 53/69 Electrical characteristics STM32F102x4, STM32F102x6 SPI interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS)(2) th(NSS)(2) tw(SCKH)(2) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) SPI characteristics(1) Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Slave mode, fPCLK = 20 MHz 4 0 2 3tPCLK 10 25 5 15 2 ns 5 5 30 4tPCLK 2tPCLK 50 5 60 18 8 70 ns % Conditions Master mode Min Max 18 MHz Unit th(SI)(2) ta(SO) (2)(3) tdis(SO)(2)(4) Data output disable time Slave mode tv(SO) (2)(1) Data output valid time Data output valid time Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) tv(MO)(2)(1) th(SO)(2) th(MO)(2) Data output hold time Master mode (after enable edge) 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 54/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Figure 23. SPI timing diagram - slave mode and CPHA=0 NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) B I T1 IN Electrical characteristics th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT tv(SO) MS B O UT th(SO) BI T6 OUT tdis(SO) LSB IN ai14134c Figure 24. SPI timing diagram - slave mode and CPHA=1(1) NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15057 Rev 3 55/69 Electrical characteristics Figure 25. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 STM32F102x4, STM32F102x6 SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 41. USB startup time Parameter USB transceiver startup time Max 1 Unit µs Symbol tSTARTUP 56/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Table 42. Symbol VDD Input levels VDI (4) Electrical characteristics USB DC electrical characteristics Parameter USB operating voltage(2) Differential input sensitivity Differential common mode range I(USBDP, USBDM) Includes VDI range RL of 1.5 k to 3.6 V(5) RL of 15 k to VSS(5) 2.8 Conditions Min.(1) 3.0(3) 0.2 0.8 1.3 2.5 2.0 0.3 V 3.6 V Max.(1) Unit 3.6 V VCM(4) VSE(4) Single ended receiver threshold Output levels VOL VOH Static output level low Static output level high 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 26. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines V CRS VS S tf tr ai14137 Table 43. Symbol tr tf trfm VCRS USB: Full speed electrical characteristics of the driver(1) Parameter Rise time(2) Fall time(2) Conditions CL = 50 pF CL = 50 pF tr/tf Min 4 4 90 1.3 Max 20 20 110 2.0 Unit ns ns % V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.16 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Doc ID 15057 Rev 3 57/69 Electrical characteristics Table 44. Symbol VDDA fADC fS(1) fTRIG(1) STM32F102x4, STM32F102x6 ADC characteristics Parameter Power supply ADC clock frequency Sampling rate External trigger frequency fADC = 12 MHz Conditions Min 2.4 0.6 0.05 Typ Max 3.6 12 1 823 17 Conversion voltage range(2) See Equation 1 and Table 45 for details 0 (VSSA or VREF- tied to ground) VREF+ Unit V MHz MHz kHz 1/fADC V VAIN RAIN(1) RADC(1) CADC(1) tCAL(1) tlat(1) tlatr(1) tS(1) tSTAB(1) tCONV(1) External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) 50 1 8 k k pF µs 1/fADC fADC = 12 MHz 5.9 83 fADC = 12 MHz 0.214 3(3) µs 1/fADC µs 1/fADC µs 1/fADC µs µs 1/fADC fADC = 12 MHz 0.143 2 (3) fADC = 12 MHz 0.107 1.5 0 0 17.1 239.5 1 18 fADC = 12 MHz 1.2 14 to 252 (tS for sampling +12.5 for successive approximation) 1. Guaranteed by design, not tested in production. 2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA, 3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 44. Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------- – R ADC N+2 f ADC  C ADC  ln  2  The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). 58/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Table 45. RAIN max for fADC = 12 MHz(1) Ts (cycles) 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 0.13 0.63 1.13 2.38 3.46 4.63 5.96 19.96 tS (µs) 0.4 5.9 Electrical characteristics RAIN max (k) 11.4 25.2 37.2 50 NA NA 1. Data guaranteed by design, not tested in production. Table 46. Symbol ET EO EG ED EL ADC accuracy - limited test conditions(1) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 48 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration Typ ±1.3 ±1 ±0.5 ±0.7 ±0.8 Max(2) ±2 ±1.5 ±1.5 ±1 ±1.5 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 47. Symbol ET EO EG ED EL ADC accuracy(1) (2) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error fPCLK2 = 48 MHz, fADC = 12 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Test conditions Typ ±2 ±1.5 ±1.5 ±1 ±1.5 Max(3) ±5 ±2.5 ±3 ±2 ±3 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog pin. It is recommended to add a Schottky diode (pin to ground) to standard analog pins that may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Doc ID 15057 Rev 3 59/69 Electrical characteristics Figure 27. ADC accuracy characteristics [1LSBIDEAL = 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) STM32F102x4, STM32F102x6 VDDA 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total u nadjusted er ror: maximum deviation between the actual and the ideal transfer curves. EO=Offset e rror: deviation between the first actual transition and the first ideal one. EG=Gain er ror: deviation between the last ideal transition and the last actual one. ED=Differential linearity error: maximum deviation between actual steps and the ideal one. EL=Integral linearity error: maximum deviation between any actual transition and the end point correlation line. 5 6 7 4093 4094 4095 4096 VDDA ai15497 Figure 28. Typical connection diagram using the ADC VDD VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F102 Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) RAIN(1) VAIN ai14974b 1. Refer to Table 44 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 60/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 29. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 29. Power supply and reference decoupling STM32F102xx VDDA 1 µF // 10 nF VSSA ai14980b 5.3.17 Temperature sensor characteristics Table 48. Symbol TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25°C Startup time ADC sampling time when reading the temperature 4 Min Typ 1.5 4.35 1.42 10 17.1 Max Unit °C mV/°C V µs µs TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) 1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 15057 Rev 3 61/69 Package characteristics STM32F102x4, STM32F102x6 6 6.1 Package characteristics Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 62/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Package characteristics Figure 30. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 31. Recommended flat package outline(1) footprint(1)(2) A A2 A1 49 48 33 0.3 0.5 32 E E1 b 12.7 10.3 e 64 10.3 17 1.2 1 7.8 16 D1 D L1 L c 12.7 ai14909 ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 49. Symbol LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0° 0.45 3.5° 0.60 1.00 Number of pins 7° 0.75 0° 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5° 0.0236 0.0394 7° 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 A A1 A2 b c D D1 E E1 e  L L1 N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15057 Rev 3 63/69 Package characteristics STM32F102x4, STM32F102x6 Figure 32. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Seating plane C Figure 33. Recommended footprint(1)(2) A A2 A1 ccc b C D 37 c 0.25 mm Gage plane 36 0.50 1.20 25 24 0.30 D1 k D3 36 25 L1 7.30 A1 L 9.70 5.80 7.30 0.20 37 24 48 1 13 12 1.20 E3 E1 E 5.80 9.70 ai14911b 48 Pin 1 identification 1 12 13 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data millimeters inches(1) Max 1.600 0.050 1.350 0.170 0.090 8.800 6.800 9.000 7.000 5.500 8.800 6.800 9.000 7.000 5.500 0.500 0.450 0.600 1.000 0° 3.5° 0.080 7° 0° 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.220 0.150 1.450 0.270 0.200 9.200 7.200 0.0020 0.0531 0.0067 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3543 0.2756 0.2165 0.0197 0.0236 0.0394 3.5° 0.0031 7° 0.0295 0.3622 0.2835 0.0551 0.0087 Min Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 0.3622 0.2835 Symbol Min A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc Typ 1. Values in inches are converted from mm and rounded to 4 decimal digits. 64/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 27. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where: ● ● ● ● TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH), PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 51. Symbol Package thermal characteristics Parameter Thermal resistance junction-ambient LQFP48 - 7 × 7 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch Value 55 °C/W 45 Unit JA 6.3 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 15057 Rev 3 65/69 Package characteristics STM32F102x4, STM32F102x6 6.3.1 Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 52: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F102xx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 51 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C). Figure 34. LQFP64 PD max vs. TA 700 600 500 400 300 200 100 0 65 75 85 95 105 115 Suffix 6 PD (mW) TA (°C) 66/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Ordering information scheme 7 Ordering information scheme Table 52. Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 102 = USB access line, USB 2.0 full-speed interface Pin count C = 48 pins R = 64 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Internal code “A” or blank(1) Options xxx = programmed parts TR = tape and real 1. For STM32F102x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet available from the ST website: www.st.com. Ordering information scheme STM32 F 102 C 6 T 6 A xxx Doc ID 15057 Rev 3 67/69 Revision history STM32F102x4, STM32F102x6 8 Revision history Table 53. Date 23-Sep-2008 Document revision history Revision 1 Initial release. I/O information clarified on page 1. Figure 1: STM32F102xx low-density USB access line block diagram and Figure 5: Memory map modified. In Table 4: low-density STM32F102xx pin definitions: PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, Note 4 added. PD value added for LQFP64 package in Table 8: General operating conditions. Note modified in Table 12: Maximum current consumption in Run mode, code with data processing running from Flash and Table 14: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 13, Figure 14 and Figure 15 show typical curves. Figure 27: ADC accuracy characteristics modified. Figure 29: Power supply and reference decoupling modified. Small text changes. Table 19: High-speed external user clock characteristics and Table 20: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 23: HSI oscillator characteristics. Note 5 updated and Note 4 added in Table 4: low-density STM32F102xx pin definitions. Typical IDD_VBAT value added in Table 15: Typical and maximum current consumptions in Stop and Standby modes. Figure 12: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. fHSE_ext min modified in Table 19: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator characteristics and Table 22: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 23: HSI oscillator characteristics modified. Conditions removed from Table 25: Low-power mode wakeup timings. Note 1 modified below Figure 18: Typical application with an 8 MHz crystal. Figure 21: Recommended NRST pin protection modified. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 44. Jitter added to Table 26: PLL characteristics. CADC and RAIN parameters modified in Table 44: ADC characteristics. RAIN max values modified in Table 45: RAIN max for fADC = 12 MHz. Changes 09-Apr-2009 2 24-Sep-2009 3 68/69 Doc ID 15057 Rev 3 STM32F102x4, STM32F102x6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15057 Rev 3 69/69
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