STM32F103x4
STM32F103x6
Low-density performance line, ARM-based 32-bit MCU with 16 or
32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces
Datasheet − production data
Features
• ARM 32-bit Cortex™-M3 CPU Core
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
TFBGA64 (5 × 5 mm)
• Memories
– 16 or 32 Kbytes of Flash memory
– 6 or 10 Kbytes of SRAM
UFQFPN48 (7 × 7 mm)
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• 2 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
• DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
• Up to 51 fast I/O ports
– 26/37/51 I/Os, all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
June 2015
This is information on a product in full production.
)%*$
LQFP64 (10 × 10 mm)
LQFP48 (7 × 7mm)
VFQFPN36 (6 × 6 mm)
• Debug mode
– Serial wire debug (SWD) & JTAG
interfaces
• 6 timers
– Two 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 16-bit, motor control PWM timer with deadtime generation and emergency stop
– 2 watchdog timers (Independent and
Window)
– SysTick timer 24-bit downcounter
• 6 communication interfaces
– 1 x I2C interface (SMBus/PMBus)
– 2 × USARTs (ISO 7816 interface, LIN, IrDA
capability, modem control)
– 1 × SPI (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full-speed interface
• CRC calculation unit, 96-bit unique ID
• Packages are ECOPACK®
Table 1. Device summary
•
Reference
Part number
STM32F103x4
STM32F103C4, STM32F103R4,
STM32F103T4
STM32F103x6
STM32F103C6, STM32F103R6,
STM32F103T6
DocID15060 Rev 7
1/99
www.st.com
Contents
STM32F103x4, STM32F103x6
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
2.3.6
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.14
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.17
Universal synchronous/asynchronous receiver transmitter (USART) . . 20
2.3.18
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.19
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.20
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.21
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.22
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.23
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.24
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21
3
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
6
Contents
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 34
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 34
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 55
5.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.17
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.18
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.19
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1
VFQFPN36 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4
TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DocID15060 Rev 7
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Contents
STM32F103x4, STM32F103x6
6.5
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 93
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xx low-density device features and peripheral counts. . . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum current consumption in Sleep mode, code running from Flash
or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DocID15060 Rev 7
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List of tables
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
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STM32F103x4, STM32F103x6
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . . 86
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DocID15060 Rev 7
STM32F103x4, STM32F103x6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F103xx performance line UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 38
Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical current consumption in Standby mode versus temperature at
VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 73
Power supply and reference decoupling(VREF+ connected to VDDA) . . . . . . . . . . . . . . . . . 74
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch
quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
VFQFPN36 marking example (package view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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8
List of figures
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
8/10
STM32F103x4, STM32F103x6
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
UFQFPN48 marking example (package view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 82
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LQFP64 marking example (package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
grid array, recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TFBGA64 marking example (package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 88
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP48 marking example (package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DocID15060 Rev 7
STM32F103x4, STM32F103x6
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. For
more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The low-density STM32F103xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website.
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Description
2
STM32F103x4, STM32F103x6
Description
The STM32F103x4 and STM32F103x6 performance line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 6 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as
well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three
USARTs, an USB and a CAN.
The STM32F103xx low-density performance line family operates from a 2.0 to 3.6 V power
supply. It is available in both the –40 to +85 °C temperature range and the –40 to +105 °C
extended temperature range. A comprehensive set of power-saving mode allows the design
of low-power applications.
The STM32F103xx low-density performance line family includes devices in four different
package types: from 36 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx low-density performance line microcontroller family
suitable for a wide range of applications such as motor drives, application control, medical
and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and
HVACs.
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STM32F103x4, STM32F103x6
Device overview
Table 2. STM32F103xx low-density device features and peripheral counts
STM32F103Tx
STM32F103Cx
STM32F103Rx
Flash - Kbytes
16
32
16
32
16
32
SRAM - Kbytes
6
10
6
10
6
10
2
2
2
2
2
2
Timers
Peripheral
Communication
2.1
Description
General-purpose
Advanced-control
1
1
1
SPI
1
1
1
1
1
1
I2C
1
1
1
1
1
1
USART
2
2
2
2
2
2
USB
1
1
1
1
1
1
CAN
1
1
1
1
1
1
GPIOs
12-bit synchronized ADC
Number of channels
26
37
51
2
10 channels
2
10 channels
2
16 channels(1)
CPU frequency
72 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9)
Junction temperature: –40 to + 125 °C (see Table 9)
VFQFPN36
LQFP48, UFQFPN48
LQFP64, TFBGA64
1. On the TFBGA64 package only 15 channels are available (one analog input pin has been replaced by
‘Vref+’).
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Description
STM32F103x4, STM32F103x6
Figure 1. STM32F103xx performance line block diagram
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4EM PSENS OR
AIC
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
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STM32F103x4, STM32F103x6
Description
Figure 2. Clock tree
-(Z
(3)2#
(3)
53"
0RESCALER
53"#,+
TO53"INTERFACE
-(Z
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0,,32#
37
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SPEEDINTERNALCLOCKSIGNAL
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SPEEDEXTERNALCLOCKSIGNAL
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AI
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48
MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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Description
2.2
STM32F103x4, STM32F103x6
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F103x8/B devices, they are
specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and
peripherals. High-density devices have higher Flash memory and RAM capacities, and
additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with
the other members of the STM32F103xx family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE
are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user
to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F103xx family
Low-density
devices
Medium-density
devices
High-density
devices
16 KB
Flash
32 KB
Flash(1)
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
6 KB
RAM
10 KB
RAM
20 KB
RAM
20 KB
RAM
48 KB
RAM
64 KB
RAM
64 KB
RAM
144
-
-
-
-
100
-
-
Pinout
64
48
36
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C, USB,
CAN, 1 × PWM timer
2 × ADCs
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs, USB,
CAN, 1 × PWM timer
2 × ADCs
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO
FSMC (100 and 144 pins)
-
-
-
-
-
-
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.
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STM32F103x4, STM32F103x6
Description
2.3
Overview
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM® Cortex™-M3 processor is the latest generation of ARM® processors for
embedded systems. It has been developed to provide a low-cost platform that meets the
needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced system response to
interrupts.
The ARM® Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2
Embedded Flash memory
16 or 32 Kbytes of embedded Flash is available for storing programs and data.
2.3.3
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.3.4
Embedded SRAM
Six or ten Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a nested vectored interrupt controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
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Description
STM32F103x4, STM32F103x6
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.6
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from User Flash
•
Boot from System Memory
•
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9
Power supply schemes
•
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
•
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
2.3.10
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
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STM32F103x4, STM32F103x6
Description
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
2.3.11
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
•
MR is used in the nominal regulation mode (Run)
•
LPR is used in the Stop mode
•
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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Description
2.3.13
STM32F103x4, STM32F103x6
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and
advanced-control timers TIMx and ADC.
2.3.14
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low-power RC oscillator or the high-speed external clock divided by 128. The
internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long-term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15
Timers and watchdogs
The low-density STM32F103xx performance line devices include an advanced-control
timer, two general-purpose timers, two watchdog timers and a SysTick timer.
Table 4 compares the features of the advanced-control and general-purpose timers.
Table 4. Timer feature comparison
18/99
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request Capture/compare Complementary
generation
channels
outputs
TIM1
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
Yes
TIM2,
TIM3
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
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STM32F103x4, STM32F103x6
Description
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for
•
Input capture
•
Output compare
•
PWM generation (edge- or center-aligned modes)
•
One-pulse mode output
If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are up to two synchronizable general-purpose timers embedded in the STM32F103xx
performance line devices. These timers are based on a 16-bit auto-reload up/down counter,
a 16-bit prescaler and feature 4 independent channels each for input capture/output
compare, PWM or one-pulse mode output. This gives up to 12 input captures/output
compares/PWMs on the largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Description
STM32F103x4, STM32F103x6
SysTick timer
This timer is dedicated for OS, but could also be used as a standard downcounter. It
features:
2.3.16
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source
I²C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
It can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.17
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interface communicates at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
2.3.18
Serial peripheral interface (SPI)
The SPI interface is able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPI interface can be served by the DMA controller.
2.3.19
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
2.3.20
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function
interface. It has software-configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use
a HSE crystal oscillator).
20/99
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STM32F103x4, STM32F103x6
2.3.21
Description
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed.
2.3.22
ADC (analog-to-digital converter)
Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
•
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control timer
(TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA
trigger respectively, to allow the application to synchronize A/D conversion and timers.
2.3.23
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC12_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.24
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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Pinouts and pin description
3
STM32F103x4, STM32F103x6
Pinouts and pin description
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22/99
DocID15060 Rev 7
STM32F103x4, STM32F103x6
Pinouts and pin description
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