STM32F103C8T7

STM32F103x8 STM32F103xB Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4 to 16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration  Low-power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers  2x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor  DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs  Up to 80 fast I/O ports – 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant March 2022 This is information on a product in full production. VFQFPN36 6 × 6 mm BGA100 10 × 10 mm UFBGA100 7 x 7 mm BGA64 5 × 5 mm UFQFPN48 7 × 7 mm LQFP100 14 × 14 mm LQFP64 10 × 10 mm LQFP48 7 × 7 mm  Debug mode – Serial wire debug (SWD) and JTAG interfaces  Seven timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with  dead-time generation and emergency stop – Two watchdog timers (independent and window) – SysTick timer 24-bit downcounter  Up to nine communication interfaces – Up to two I2C interfaces (SMBus/PMBus®) – Up to three USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to two SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface  CRC calculation unit, 96-bit unique ID  Packages are ECOPACK® Table 1. Device summary Reference Part number STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB, STM32F103TB DS5319 Rev 18 1/116 www.st.com Contents STM32F103x8, STM32F103xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 19 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 6 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 39 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 59 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1 VFQFPN36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3 LFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DS5319 Rev 18 3/116 4 Contents STM32F103x8, STM32F103xB 6.5 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.7 TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.8 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 105 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4/116 DS5319 Rev 18 STM32F103x8, STM32F103xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SCL frequency (fPCLK1 = 36 MHz, VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DS5319 Rev 18 5/116 6 List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. 6/116 STM32F103x8, STM32F103xB USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC accuracy - Limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 VFQFPN36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LFBGA100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . . 87 LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 UFBGA100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 93 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TFBGA64 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . . 99 LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DS5319 Rev 18 STM32F103x8, STM32F103xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F103xx performance line UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32F103xx performance line UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42 Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42 Typical current consumption on VBAT (RTC on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical current consumption in Stop mode, with regulator in Run mode . . . . . . . . . . . . . . 45 Typical current consumption in Stop mode, with regulator in Low-power mode. . . . . . . . . 45 Typical current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 77 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 78 VFQFPN36 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VFQFPN36 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 VFPFPN36 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 UFQFPN48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DS5319 Rev 18 7/116 8 List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. 8/116 STM32F103x8, STM32F103xB LFBGA100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LFBGA100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LFBGA100 package top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LQFP100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 UFBGA100 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UFBGA100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 UFBGA100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TFBGA64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TFBGA64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 TFBGA64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LQFP48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP48 - 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DS5319 Rev 18 STM32F103x8, STM32F103xB 1 Introduction Introduction This document provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet must be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M3 core refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website. 2 Description The STM32F103xx medium-density performance line family incorporates the  high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS5319 Rev 18 9/116 115 Description 2.1 STM32F103x8, STM32F103xB Device overview Table 2. STM32F103xx medium-density device features and peripheral counts Peripheral Flash - Kbytes Communication Timers SRAM - Kbytes STM32F103Tx 64 128 STM32F103Cx 64 128 STM32F103Rx 64 128 STM32F103Vx 64 128 20 20 20 20 General-purpose 3 3 3 3 Advanced-control 1 1 1 1 SPI 1 2 2 2 I2C 1 2 2 2 USART 2 3 3 3 USB 1 1 1 1 CAN 1 1 1 1 26 37 51 80 2 10 channels 2 10 channels 2 16 channels(1) 2 16 channels GPIOs 12-bit synchronized ADC Number of channels CPU frequency 72 MHz Operating voltage Operating temperatures Packages 2.0 to 3.6 V Ambient temperatures: -40 to +85 °C / -40 to +105 °C (see Table 9) Junction temperature: -40 to + 125 °C (see Table 9) VFQFPN36 LQFP48, UFQFPN48 LQFP64, TFBGA64 LQFP100, LFBGA100, UFBGA100 1. On the TFBGA64 package only 15 channels are available (one analog input pin has been replaced by VREF+). 10/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Description Figure 1. STM32F103xx performance line block diagram TPIU SW/JTAG Trace Controlle r pbu s Trace/trig flash obl Interfac e Ibus Cortex-M3 CPU Fmax : 72MHz Dbus NVIC Syst em AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int PCLK1 PCLK2 HCLK FCLK AHB2 APB2 @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz PB[15:0] GPIOB PC[15:0] GPIOC PD[15:0] GPIOD PE[15:0] GPIOE 4 Channels 3 compl. Channels ETR and BKIN TIM1 MOSI,MISO, SCK,NSS as AF SPI1 IWDG Stand by in terface @VDDA AHB2 APB1 RTC AWU Backup reg 12bit ADC2 IF TAMPER-RTC TIM2 4 Channels TIM3 4 Channels TIM 4 4 Channels USART2 RX,TX, CTS, RTS, CK, SmartCard as AF USART3 RX,TX, CTS, RTS, CK, SmartCard as AF 2x(8x16bit)SPI2 MOSI,MISO,SCK,NSS as AF I2C1 SCL,SDA,SMBA as AF I2C2 SCL,SDA as AF bxCAN USB 2.0 FS VREF- OSC32_IN OSC32_OUT Backu p i nterface USART1 12bit ADC1 IF VBAT @VBAT @VDDA 16AF VREF+ OSC_IN OSC_OUT RC 8 MHz RC 40 kHz EXTI WAKEUP GPIOA VDD = 2 to 3.6V VSS @VDD 64 bit XTAL 32 kHz PA[ 15:0] RX,TX, CTS, RTS, Smart Card as AF Flash 128 KB APB2 : Fmax =48 / 72 MHz 80AF POR / PDR VOLT . REG. 3.3V TO 1.8V SRAM 20 KB GP DMA 7 channels POWER APB1 : Fmax =24 / 36 MHz NJTRST TRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF BusM atrix TRACECLK TRACED[0:3] as AS USBDP/CAN_TX USBDM/CAN_RX SRAM 512B WW DG Tem p sens or ai14390d 1. TA = –40 °C to +105 °C (junction temperature up to 125 °C). 2. AF = alternate function on I/O port pin. DS5319 Rev 18 11/116 115 Description STM32F103x8, STM32F103xB Figure 2. Clock tree FLITFCLK to Flash programming interface 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..512 max PLLCLK Clock Enable (3 bits) APB1 Prescaler /1, 2, 4, 8, 16 HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (13 bits) to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock CSS Enable (3 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz 72 MHz max HSE OSC /2 TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals to RTC LSE RTCCLK ADC Prescaler /2, 4, 6, 8 Enable (1 bit) to ADC ADCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK HSI Legend: HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal HSE SYSCLK MCO ai14903 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the availability of the USB function both HSE and PLL must be enabled, with USBCLK running at 48 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. 12/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively.  Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 - - 100 - - 64 48 36 2× USARTs 2× 16-bit timers 1× SPI, 1× I2C, USB, CAN, 1× PWM timer 2× ADCs - - 3× USARTs 3× 16-bit timers 2× SPIs, 2× I2Cs, USB, CAN, 1× PWM timer 2× ADCs DS5319 Rev 18 5× USARTs 4× 16-bit timers, 2× basic timers 3× SPIs, 2× I2Ss, 2× I2Cs USB, CAN, 2× PWM timers 3× ADCs, 2× DACs, 1× SDIO FSMC (100 and 144 pins) - - - - - - 13/116 115 Description STM32F103x8, STM32F103xB 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM The Arm® Cortex®-M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded Arm core, is therefore compatible with all Arm tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex®M3) and 16 priority levels. 14/116  Closely coupled NVIC gives low-latency interrupt processing  Interrupt entry vector table address passed directly to the core  Closely coupled NVIC core interface  Allows early processing of interrupts  Processing of late arriving higher priority interrupts  Support for tail-chaining  Processor state automatically saved  Interrupt entry restored on interrupt exit with no instruction overhead DS5319 Rev 18 STM32F103x8, STM32F103xB Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from user Flash  Boot from System memory  Boot from embedded SRAM The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1. For further details refer to AN2606, available on www.st.com. 2.3.9 Power supply schemes  VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.  Provided externally through VDD pins.  VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 14: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains DS5319 Rev 18 15/116 115 Description STM32F103x8, STM32F103xB in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11 for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down.  MR is used in the nominal regulation mode (Run)  LPR is used in the Stop mode  Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:  Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.  Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.  Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: 16/116 The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DS5319 Rev 18 STM32F103x8, STM32F103xB 2.3.13 Description DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Timers and watchdogs The medium-density STM32F103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No DS5319 Rev 18 17/116 115 Description STM32F103x8, STM32F103xB Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for  Input capture  Output compare  PWM generation (edge- or center-aligned modes)  One-pulse mode output If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from one to three Hall-effect sensors. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 18/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Description SysTick timer This timer is dedicated for OS, but can be used also as a standard downcounter. It features: 2.3.16  A 24-bit downcounter  Autoreload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 2.3.18 Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in  full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 2.3.19 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with three stages and 14 scalable filter banks. 2.3.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). DS5319 Rev 18 19/116 115 Description 2.3.21 STM32F103x8, STM32F103xB GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed. 2.3.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:  Simultaneous sample and hold  Interleaved sample and hold  Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 20/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 3 Pinouts and pin description Pinouts and pin description Figure 3. STM32F103xx performance line LFBGA100 ballout DS5319 Rev 18 21/116 115 Pinouts and pin description STM32F103x8, STM32F103xB 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4. STM32F103xx performance line LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14391 22/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description Figure 5. STM32F103xx performance line UFBGA100 pinout 2 1 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PC13 PE5 RTC_TAMPER PE0 PD2 PD0 PC11 NC PA10 VSS_3 PA9 PA8 PC9 VSS_4 PC8 PC7 PC6 VSS_2 VSS_1 VDD_2 VDD_1 C D PC14 PE6 VDD_3 PB5 OSC32_IN E F G VBAT PC15 OSC32_OUT OSC_IN VSS_5 OSC_OUT VDD_5 H PC0 NRST VDD_4 PD15 PD14 PD13 J VSSA PC1 PC2 PD12 PD11 PD10 K VREF- PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13 PB10 PB11 PB12 PE14 PE15 L VREF+ PA0 WKUP1 PA3 PA6 PC5 PB2 PE8 PE10 PE12 M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 MS30481V1 DS5319 Rev 18 23/116 115 Pinouts and pin description STM32F103x8, STM32F103xB VDD_3 VSS_3 PB 9 PB 8 BOO T 0 PB 7 PB 6 PB 5 PB 4 PB 3 PD2 PC12 PC11 PC10 PA 15 PA 14 Figure 6. STM32F103xx performance line LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 V SS_2 PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PB 15 PB 14 PB 13 PB 12 PA 3 V SS_4 VDD_4 PA 4 PA 5 PA 6 PA 7 PC4 PC5 PB 0 PB 1 PB 2 PB1 0 PB1 1 V SS_1 VDD_1 VBAT PC13-TAMPER-RTC PC 14-O SC 32_IN PC 15-O SC 32_OU T P D 0-OS C_IN P D 1-OS C_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA 0-WK UP PA 1 PA 2 ai14392 24/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description Figure 7. STM32F103xx performance line TFBGA64 ballout A 1 2 3 4 5 6 7 8 PC14- PC13- PB9 PB4 PB3 PA15 PA14 PA13 V BAT PB8 BOOT0 PD2 PC11 PC10 PA12 OSC32_IN TAMPER-RTC B PC15OSC32_OUT C OSC_IN V SS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT V DD_4 PB6 V SS_3 V SS_2 V SS_1 PA8 PC9 E NRST PC1 PC0 V DD_3 V DD_2 V DD_1 PC7 PC8 F V SSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G V REF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H V DDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 DS5319 Rev 18 25/116 115 Pinouts and pin description STM32F103x8, STM32F103xB VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 8. STM32F103xx performance line LQFP48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RT C PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 ai14393b VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 9. STM32F103xx performance line UFQFPN48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 3 34 4 33 32 5 6 QFPN48 7 31 30 8 29 9 28 10 27 11 26 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 MS31472V1 26/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description PB4 PB3 PA15 PA14 30 29 28 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 VSSA 5 23 PA11 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 10 11 12 13 14 15 PB0 PB5 31 PA7 PB6 32 PA6 PB7 33 PA5 34 1 PA4 35 VDD_3 PA3 36 BOOT0 VSS_3 Figure 10. STM32F103xx performance line VFQFPN36 pinout 17 PB2 PB1 16 19 18 VDD_1 VSS_1 QFN36 ai14654 DS5319 Rev 18 27/116 115 Pinouts and pin description STM32F103x8, STM32F103xB Table 5. Medium-density STM32F103xx pin definitions Alternate functions(4) LQFP48/UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 B2 - - - 1 - PE2 I/O FT PE2 TRACECK - B3 A1 - - - 2 - PE3 I/O FT PE3 TRACED0 - C3 B1 - - - 3 - PE4 I/O FT PE4 TRACED1 - D3 C2 - - - 4 - PE5 I/O FT PE5 TRACED2 - E3 D2 - - - 5 - PE6 I/O FT PE6 TRACED3 - B2 E2 1 B2 1 6 - VBAT S - VBAT - - A2 C1 2 A2 2 7 - PC13-TAMPERRTC(5) I/O - PC13(6) TAMPER-RTC - A1 D1 3 A1 3 8 - PC14-OSC32_IN(5) I/O - PC14(6) OSC32_IN - B1 E1 4 B1 4 9 - PC15OSC32_OUT(5) I/O - PC15(6) OSC32_OUT - C2 F2 - - - 10 - VSS_5 S - VSS_5 - - D2 G2 - - - 11 - VDD_5 S - VDD_5 - C1 F1 5 C1 5 12 2 OSC_IN I - OSC_IN - D1 G1 6 D1 6 13 3 OSC_OUT O - OSC_OUT E1 H2 7 E1 7 14 4 NRST I/O - NRST - - F1 H1 - E3 8 15 - PC0 I/O - PC0 ADC12_IN10 - F2 J2 - E2 9 16 - PC1 I/O - PC1 ADC12_IN11 - E2 J3 - F2 10 17 - PC2 I/O - PC2 ADC12_IN12 - 11 18 - PC3 I/O - PC3 ADC12_IN13 - I / O Level(2) UFBG100 A3 Pin name Type(1) LFBGA100 Pins Main function(3) (after reset) Default Remap PD0(7) PD1(7) F3 K2 - -(8) G1 J1 8 F1 12 19 5 VSSA S - VSSA - - H1 K1 - - - 20 - VREF- S - VREF- - - J1 L1 - G1(8) - 21 - VREF+ S - VREF+ - - K1 M1 9 H1 13 22 6 VDDA S - VDDA - - 28/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions (continued) Alternate functions(4) G2 H2 L2 M2 10 11 G2 H2 14 15 23 24 7 8 PA0-WKUP PA1 I/O I/O I / O Level(2) Pin name Type(1) VFQFPN36 LQFP100 LQFP64 TFBGA64 LQFP48/UFQFPN48 UFBG100 LFBGA100 Pins - - Main function(3) (after reset) Default Remap PA0 WKUP/ USART2_CTS(9)/ ADC12_IN0/ TIM2_CH1_ ETR(9) - PA1 USART2_RTS(9)/ ADC12_IN1/ TIM2_CH2(9) - - J2 K3 12 F3 16 25 9 PA2 I/O - PA2 USART2_TX(9)/ ADC12_IN2/ TIM2_CH3(9) K2 L3 13 G3 17 26 10 PA3 I/O - PA3 USART2_RX(9)/ ADC12_IN3/ TIM2_CH4(9) - E4 E3 - C2 18 27 - VSS_4 S - VSS_4 - - F4 H3 - D2 19 28 - VDD_4 S - VDD_4 - - SPI1_NSS(9)/ USART2_CK(9)/ ADC12_IN4 - G3 M3 14 H3 20 29 11 PA4 I/O - PA4 H3 K4 15 F4 21 30 12 PA5 I/O - PA5 SPI1_SCK(9)/ ADC12_IN5 - J3 L4 16 G4 22 31 13 PA6 I/O - PA6 SPI1_MISO(9)/ ADC12_IN6/ TIM3_CH1(9) TIM1_BKIN TIM1_CH1N PA7 I/O - PA7 SPI1_MOSI(9)/ ADC12_IN7/ TIM3_CH2(9) 33 PC4 I/O - PC4 ADC12_IN14 - 25 34 PC5 I/O - PC5 ADC12_IN15 - F5 26 35 15 PB0 I/O - PB0 ADC12_IN8/ TIM3_CH3(9) TIM1_CH2N G5 27 36 16 PB1 I/O - PB1 ADC12_IN9/ TIM3_CH4(9) TIM1_CH3N K3 M4 17 H4 23 32 G4 K5 - H5 24 H4 L5 - H6 J4 M5 18 K4 M6 19 14 DS5319 Rev 18 29/116 115 Pinouts and pin description STM32F103x8, STM32F103xB Table 5. Medium-density STM32F103xx pin definitions (continued) Alternate functions(4) LQFP48/UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 L6 20 G6 28 37 17 PB2 I/O FT PB2/BOOT1 - - H5 M7 - - - 38 - PE7 I/O FT PE7 - TIM1_ETR J5 L7 - - - 39 - PE8 I/O FT PE8 - TIM1_CH1N K5 M8 - - - 40 - PE9 I/O FT PE9 - TIM1_CH1 G6 L8 - - - 41 - PE10 I/O FT PE10 - TIM1_CH2N H6 M9 - - - 42 - PE11 I/O FT PE11 - TIM1_CH2 J6 L9 - - - 43 - PE12 I/O FT PE12 - TIM1_CH3N K6 M10 - - - 44 - PE13 I/O FT PE13 - TIM1_CH3 G7 M11 - - - 45 - PE14 I/O FT PE14 - TIM1_CH4 H7 M12 - - - 46 - PE15 I/O FT PE15 - TIM1_BKIN J7 L10 21 G7 29 47 - PB10 I/O FT PB10 I2C2_SCL/ USART3_TX(9) TIM2_CH3 K7 L11 22 H7 30 48 - PB11 I/O FT PB11 I2C2_SDA/ USART3_RX(9) TIM2_CH4 E7 F12 23 D6 31 49 18 VSS_1 S - VSS_1 - - F7 G12 24 E6 32 50 19 VDD_1 S - VDD_1 - - - I / O Level(2) UFBG100 G5 Pin name Type(1) LFBGA100 Pins Main function(3) (after reset) Default Remap 25 H8 33 51 - PB12 I/O FT PB12 SPI2_NSS/ I2C2_SMBAl/ USART3_CK(9)/ TIM1_BKIN(9) J8 K12 26 G8 34 52 - PB13 I/O FT PB13 SPI2_SCK/ USART3_CTS(9)/ TIM1_CH1N (9) - H8 K11 27 F8 35 53 - PB14 I/O FT PB14 SPI2_MISO/ USART3_RTS(9) TIM1_CH2N (9) - G8 K10 28 F7 36 54 - PB15 I/O FT PB15 SPI2_MOSI/ TIM1_CH3N(9) - K8 L12 K9 K9 - - - 55 - PD8 I/O FT PD8 - USART3_TX J9 K8 - - - 56 - PD9 I/O FT PD9 - USART3_RX 30/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions (continued) Alternate functions(4) LQFP100 VFQFPN36 - 57 - PD10 I/O FT PD10 - USART3_CK G9 J11 - - - 58 - PD11 I/O FT PD11 - USART3_CTS K10 J10 - - - 59 - PD12 I/O FT PD12 - TIM4_CH1 / USART3_RTS J10 H12 - - - 60 - PD13 I/O FT PD13 - TIM4_CH2 H10 H11 - - - 61 - PD14 I/O FT PD14 - TIM4_CH3 G10 H10 - - - 62 - PD15 I/O FT PD15 - TIM4_CH4 F10 E12 - F6 37 63 - PC6 I/O FT PC6 - TIM3_CH1 E10 E11 E7 38 64 - PC7 I/O FT PC7 - TIM3_CH2 F9 E10 E8 39 65 - PC8 I/O FT PC8 - TIM3_CH3 D8 40 66 - PC9 I/O FT PC9 - TIM3_CH4 D9 D11 29 D7 41 67 20 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1(9)/ MCO - C9 D10 30 C7 42 68 21 PA9 I/O FT PA9 USART1_TX(9)/ TIM1_CH2(9) - D10 C12 31 C6 43 69 22 PA10 I/O FT PA10 USART1_RX(9)/ TIM1_CH3(9) - PA11 USART1_CTS/ CANRX(9)/ USBDM/ TIM1_CH4(9) - PA12 USART1_RTS/ CANTX(9) /USBDP TIM1_ETR(9) - - PA13 E9 D12 - C10 B12 32 C8 44 70 23 PA11 I / O Level(2) LQFP64 - Pin name Type(1) TFBGA64 - UFBG100 H9 J12 LFBGA100 LQFP48/UFQFPN48 Pins I/O FT Main function(3) (after reset) Default Remap B10 A12 33 B8 45 71 24 PA12 I/O FT A10 A11 34 A8 46 72 25 PA13 I/O FT JTMS/SWDIO F8 C11 - - - 73 - E6 F11 35 D5 47 74 26 VSS_2 S - VSS_2 - - F6 G11 36 E5 48 75 27 VDD_2 S - VDD_2 - - Not connected DS5319 Rev 18 - 31/116 115 Pinouts and pin description STM32F103x8, STM32F103xB Table 5. Medium-density STM32F103xx pin definitions (continued) Alternate functions(4) LQFP100 VFQFPN36 76 28 PA14 I/O FT JTCK/SWCLK - PA14 A8 38 A6 50 77 29 PA15 I/O FT JTDI - TIM2_CH1_ ETR/ PA15 /SPI1_NSS B9 B11 - B7 51 78 PC10 I/O FT PC10 - USART3_TX B8 C10 - B6 52 79 PC11 I/O FT PC11 - USART3_RX C8 B10 - C5 53 80 PC12 I/O FT PC12 - USART3_CK D8 C9 - C1 - 81 2 PD0 I/O FT PD0 - CANRX E8 B9 - D1 - 82 3 PD1 I/O FT PD1 - CANTX B7 C8 B5 54 83 - PD2 I/O FT PD2 TIM3_ETR - C7 B8 - - - 84 - PD3 I/O FT PD3 - USART2_CTS D7 B7 - - - 85 - PD4 I/O FT PD4 - USART2_RTS B6 A6 - - - 86 - PD5 I/O FT PD5 - USART2_TX C6 B6 - - - 87 - PD6 I/O FT PD6 - USART2_RX D6 A5 - - - 88 - PD7 I/O FT PD7 - USART2_CK A9 I / O Level(2) LQFP64 49 Pin name Type(1) TFBGA64 A7 UFBG100 A9 A10 37 LFBGA100 LQFP48/UFQFPN48 Pins Main function(3) (after reset) Default Remap A7 A8 39 A5 55 89 30 PB3 I/O FT JTDO - TIM2_CH2 / PB3 TRACESWO SPI1_SCK A6 A7 40 A4 56 90 31 PB4 I/O FT JNTRST - TIM3_CH1/ PB4/ SPI1_MISO C5 C5 41 C4 57 91 32 PB5 I/O PB5 I2C1_SMBAl TIM3_CH2 / SPI1_MOSI B5 B5 42 D3 58 92 33 PB6 I/O FT PB6 I2C1_SCL(9)/ TIM4_CH1(9) USART1_TX A5 B4 43 C3 59 93 34 PB7 I/O FT PB7 I2C1_SDA(9)/ TIM4_CH2(9) USART1_RX D5 A4 44 B4 60 94 35 BOOT0 BOOT0 - - 32/116 I DS5319 Rev 18 STM32F103x8, STM32F103xB Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions (continued) Alternate functions(4) LQFP48/UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 A3 45 B3 61 95 - PB8 I/O FT PB8 TIM4_CH3(9) I2C1_SCL / CANRX A4 B3 46 A3 62 96 - PB9 I/O FT PB9 TIM4_CH4(9) I2C1_SDA/ CANTX D4 C3 - - - 97 - PE0 I/O FT PE0 TIM4_ETR - C4 A2 - - - 98 - PE1 I/O FT PE1 - - E5 D3 47 D4 63 99 36 VSS_3 S - VSS_3 - - F5 C4 48 E4 64 100 1 VDD_3 S - VDD_3 - - I / O Level(2) UFBG100 B4 Pin name Type(1) LFBGA100 Pins Main function(3) (after reset) Default Remap 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends upon the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they are called SPI1 and USART1 and USART2, respectively. Refer to Table 2. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive a LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48, UFQFP48 and LQFP64 packages, and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. DS5319 Rev 18 33/116 115 Memory mapping 4 STM32F103x8, STM32F103xB Memory mapping The memory map is shown in Figure 11. Figure 11. Memory map APB memory space reserved reserved reserved CRC 7 reserved Cortex- M3 Internal Peripherals Flash Interface reserved RCC reserved 6 DMA reserved USART1 reserved 5 SPI1 TIM1 ADC2 ADC1 rese rve d 4 rese rved Por t E Port D Option Bytes Port C Port B 3 System memory Port A EXTI AFIO reserved PWR 2 BKP rese rved Peripherals reserved bxCAN shared 512 byte USB/CAN SRAM USB Reg isters 1 I2C2 I2C1 SRAM reserved USART3 USART2 0 Flash memory reserved SPI2 Aliased to Flash or system memory depending on BOOT pins reserved IWDG WWDG RTC reserved Reserved TIM4 TIM3 TIM2 ai14394f 34/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V  VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 12. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 13. Figure 12. Pin loading conditions Figure 13. Pin input voltage STM32F103xx pin C = 50 pF STM32F103xx pin VIN ai14141 ai14142 DS5319 Rev 18 35/116 115 Electrical characteristics 5.1.6 STM32F103x8, STM32F103xB Power supply scheme Figure 14. Power supply scheme VBAT Backup circuitry (OSC32K, RTC, Backup registers, Wake-up logic) OUT GP I/Os IN Level shifter Power switch 1.8 - 3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.7 μF VDD 1/2/3/4/5 VDDA VREF 10 nF + 1 μF Regulator VSS 10 nF + 1 μF VREF+ ADC/ DAC VREF- Analog: RCs, PLL,... VSSA ai14125d Caution: In Figure 14, the 4.7 µF capacitor must be connected to VDD3. 5.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 36/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 5.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6, Table 7, and Table 8 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Voltage characteristics Symbol Ratings Min Max VDD VSS External main supply voltage (including VDDA and VDD)(1) –0.3 4.0 VIN(2) |VDDx| Input voltage on 5 V tolerant pin VSS  0.3 VDD  4.0 Input voltage on any other pin VSS 0.3 4.0 - 50 - 50 Variations between different VDD power pins |VSSX VSS| Variations between all the different ground pins VESD(HBM) Unit Electrostatic discharge voltage (human body model) V mV See Section 5.3.11 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 7 for the maximum allowed injected current values. Table 7. Current characteristics Symbol Ratings Max. IVDD Total current into VDD/VDDA power lines (source)(1) 150 IVSS Total current out of VSS ground lines (sink)(1) 150 Output current sunk by any I/O and control pin 25 IIO IINJ(PIN)(2) IINJ(PIN) Output current source by any I/Os and control pin  25 Injected current on five volt tolerant pins(3) -5/+0 Injected current on any other pin(4) Unit mA ±5 (5) Total injected current (sum of all I/O and control pins) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See footnote 2 of Table 48. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN VDD, while a negative injection is induced by VIN < VSS.  IINJ(PIN) must never be exceeded. Refer to Table 6 for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 8. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS5319 Rev 18 Value –65 to +150 150 Unit °C 37/116 115 Electrical characteristics STM32F103x8, STM32F103xB 5.3 Operating conditions 5.3.1 General operating conditions Table 9. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 2 3.6 2 3.6 VDD VDDA(1) VBAT Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Must be the same potential as VDD(2) 3.6 1.8 3.6 –0.3 VDD+ 0.3 2 V < VDD  3.6 V –0.3 5.5 VDD = 2 V –0.3 5.2 BOOT0 0 5.5 LFBGA100 - 454 LQFP100 - 434 UFBGA100 - 339 TFBGA64 - 308 LQFP64 - 444 LQFP48 - 363 UFQFPN48 - 624 VFQFPN36 - 1000 Standard IO VIN PD I/O input voltage FT IO(3) Power dissipation at  TA = 85 °C for suffix 6 or  TA = 105 °C for suffix 7(4) Ambient temperature for 6 suffix version Maximum power dissipation –40 85 Low-power dissipation(5) –40 105 Ambient temperature for 7 suffix version Maximum power dissipation –40 105 –40 125 6 suffix version –40 105 7 suffix version –40 125 TA TJ Junction temperature range Low-power dissipation (5) MHz V 2.4 Backup operating voltage Unit V mW °C 1. When the ADC is used, refer to Table 46. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. To sustain a voltage higher than VDD + 0.3 V, the internal pull-up/pull-down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.9). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.9). 38/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 5.3.2 Electrical characteristics Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD 5.3.3 Conditions Min Max 0  20  - VDD fall time rate Unit µs/V Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11. Embedded reset and power control block characteristics Symbol VPVD Parameter Conditions Min Typ Max PLS[2:0] = 000 (rising edge) 2.10 2.18 2.26 PLS[2:0] = 000 (falling edge) 2,00 2.08 2.16 PLS[2:0] = 001 (rising edge) 2.19 2.28 2.37 PLS[2:0] = 001 (falling edge) 2.09 2.18 2.27 PLS[2:0] = 010 (rising edge) 2.28 2.38 2.48 PLS[2:0] = 010 (falling edge) 2.18 2.28 2.38 PLS[2:0] = 011 (rising edge) 2.38 2.48 2.58 Programmable voltage PLS[2:0] = 011 (falling edge) detector level selection PLS[2:0] = 100 (rising edge) 2.28 2.38 2.48 2.47 2.58 2.69 PLS[2:0] = 100 (falling edge) 2.37 2.48 2.59 PLS[2:0] = 101 (rising edge) 2.57 2.68 2.79 PLS[2:0] = 101 (falling edge) 2.47 2.58 2.69 PLS[2:0] = 110 (rising edge) 2.66 2.78 2.90 PLS[2:0] = 110 (falling edge) 2.56 2.68 2.80 PLS[2:0] = 111 (rising edge) 2.76 2.88 3.00 PLS[2:0] = 111 (falling edge) 2.66 2.78 2.90 - - 100 - Falling edge 1.8(1) 1.88 1.96 Rising edge 1.84 1.92 2.0 - - 40 - mV - 1.0 2.5 4.5 ms VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst(2) PDR hysteresis TRSTTEMPO(2) Reset temporization Unit V mV V 1. The product behavior is specified by design down to the minimum VPOR/PDR value. 2. Specified by design, not tested in production. DS5319 Rev 18 39/116 115 Electrical characteristics 5.3.4 STM32F103x8, STM32F103xB Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol Conditions Min Typ Max –40 °C < TA < +105 °C 1.16 1.20 1.26 –40 °C < TA < +85 °C 1.16 1.20 1.24 ADC sampling time when TS_vrefint(1) reading the internal reference voltage - - 5.1 17.1(2) µs Internal reference voltage VRERINT(2) spread over the temperature range VDD = 3 V ±10 mV - - 10 mV - - - 100 ppm/°C VREFINT TCoeff(2) Parameter Internal reference voltage Temperature coefficient Unit V 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Specified by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory, and executed binary code. The current consumption is measured as described in Figure 15. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions:  All I/O pins are in input mode with a static value at VDD or VSS (no load)  All peripherals are disabled except when explicitly mentioned  The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, one wait state from 24 to 48 MHz and two wait states above)  Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)  When the peripherals are enabled fPCLK1 = fHCLK / 2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 40/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK External clock(2), all peripherals enabled IDD Supply current in Run mode External clock(2), all peripherals disabled Unit TA = 85 °C TA = 105 °C 72 MHz 50.0 50.3 48 MHz 36.1 36.2 36 MHz 28.6 28.7 24 MHz 19.9 20.1 16 MHz 14.7 14.9 8 MHz 8.6 8.9 72 MHz 32.8 32.9 48 MHz 24.4 24.5 36 MHz 19.8 19.9 24 MHz 13.9 14.2 16 MHz 10.7 11.0 8 MHz 6.8 7.1 mA 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Run mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 48 50 48 MHz 31.5 32 36 MHz 24 25.5 24 MHz 17.5 18 16 MHz 12.5 13 8 MHz 7.5 8 72 MHz 29 29.5 48 MHz 20.5 21 36 MHz 16 16.5 24 MHz 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 mA 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. DS5319 Rev 18 41/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 36 MHz 16 MHz 8 MHz 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (°C) Figure 17. Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals disabled 30 Consumption (mA) 25 20 72 MHz 36 MHz 16 MHz 8 MHz 15 10 5 0 -40 0 25 70 Temperature (°C) 42/116 DS5319 Rev 18 85 105 STM32F103x8, STM32F103xB Electrical characteristics Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Max(1) TA = 85 °C TA = 105 °C 72 MHz 30 32 48 MHz 20 20.5 36 MHz 15.5 16 24 MHz 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.5 8 MHz 3 4 Unit mA 1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. DS5319 Rev 18 43/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 16. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low-power mode, low- IDD Max speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF,  low-speed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current - 23.5 24 200 370 - 13.5 14 180 340 - 2.6 3.4 - - - 2.4 3.2 - - - 1.7 2 4 5 0.9 1.1 1.4 1.9(2) 2.2 1. Typical values are measured at TA = 25 °C. 2. Evaluated by characterization, not tested in production, unless otherwise specified. Figure 18. Typical current consumption on VBAT (RTC on) Consumption ( µA ) 2.5 2 2V 1.5 2.4 V 1 3V 0.5 3.6 V 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17351 44/116 DS5319 Rev 18 µA STM32F103x8, STM32F103xB Electrical characteristics Figure 19. Typical current consumption in Stop mode, with regulator in Run mode 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -45 25 70 90 110 Temperature (°C) Figure 20. Typical current consumption in Stop mode, with regulator in Low-power mode 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -40 0 25 70 85 105 Temperature (°C) DS5319 Rev 18 45/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 21. Typical current consumption in Standby mode 4.5 4 Consumption (µA) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.5 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Typical current consumption The MCU is placed under the following conditions: 46/116  All I/O pins are in input mode with a static value at VDD or VSS (no load)  All peripherals are disabled except if explicitly mentioned  The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, one wait state from 24 to 48 MHz and two wait states above)  Ambient temperature and VDD supply voltage conditions summarized in Table 9  Prefetch is ON (this bit must be set before clock setting and bus prescaling)  When the peripherals are enabled fPCLK1 = fHCLK / 4, fPCLK2 = fHCLK / 2,  fADCCLK = fPCLK2 / 4 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 36 27 48 MHz 24.2 18.6 36 MHz 19.0 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.8 2 MHz 2.2 1.9 1 MHz 1.6 1.45 500 kHz 1.3 1.25 125 kHz 1.08 1.06 64 MHz 31.4 23.9 48 MHz 23.5 17.9 36 MHz 18.3 14.1 24 MHz 12.2 9.5 16 MHz 8.5 6.8 8 MHz 4.9 4.0 4 MHz 2.7 2.2 2 MHz 1.6 1.4 1 MHz 1.02 0.9 500 kHz 0.73 0.67 125 kHz 0.5 0.48 Unit mA mA 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. DS5319 Rev 18 47/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD (3) Supply current in Sleep mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 14.4 5.5 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1.0 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.95 64 MHz 12.3 4.4 48 MHz 9.3 3.3 36 MHz 7 2.5 24 MHz 4.8 1.8 16 MHz 3.2 1.2 8 MHz 1.6 0.6 4 MHz 1.0 0.5 2 MHz 0.72 0.47 1 MHz 0.56 0.44 500 kHz 0.49 0.42 125 kHz 0.43 0.41 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 48/116 DS5319 Rev 18 Unit mA STM32F103x8, STM32F103xB Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is put under the following conditions:  all I/O pins are in input mode with a static value at VDD or VSS (no load)  all peripherals are disabled unless otherwise mentioned  the given value is calculated by measuring the current consumption  – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Table 19. Peripheral current consumption µA/MHz Peripherals AHB (up to 72 MHz) DMA1 16.53 BusMatrix(1) 8.33 APB1-Bridge 10.28 TIM2 32.50 TIM3 31.39 TIM4 31.94 SPI2 4.17 USART2 12.22 USART3 12.22 I2C1 10.00 I2C2 10.00 USB 17.78 CAN1 18.06 WWDG 2.50 PWR 1.67 BKP 2.50 IWDG 11.67 APB1 (up to 36 MHz) DS5319 Rev 18 49/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 19. Peripheral current consumption (continued) µA/MHz Peripherals APB2-Bridge 3.75 GPIOA 6.67 GPIOB 6.53 GPIOC 6.53 GPIOD 6.53 GPIOE 6.39 SPI1 4.72 USART1 11.94 TIM1 23.33 APB2 (up to 72 MHz) (2) 17.50 (2) 16.07 ADC1 ADC2 1. The BusMatrix is automatically active when at least one master peripheral is ON (CPU or DMA). 2. Specific conditions for measuring ADC current consumption: fHCLK = 56 MHz, fAPB1 = fHCLK / 2,  fAPB2 = fHCLK, fADCCLK = fAPB2 / 4, When ADON bit in the ADCx_CR2 register is set to 1, a current consumption of analog part equal to 0.65 mA must be added for each ADC. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using a high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. High-speed external user clock characteristics Symbol Parameter fHSE_ext User external clock source frequency(1) VHSEH Min Typ Max Unit 1 8 25 MHz OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 20 - - 5 - pF - 45 - 55 % VSS VIN VDD - - ±1 µA Cin(HSE) OSC_IN input capacitance(1) OSC_IN Input leakage current 1. Specified by design, not tested in production. 50/116 - V ns DuCy(HSE) Duty cycle IL Conditions DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 32.768 1000 kHz fLSE_ext User external clock source frequency(1) VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD 450 - - - - 50 - - 5 - pF - 30 - 70 % VSS  VIN  VDD - - ±1 µA tw(LSE) tw(LSE) OSC32_IN high or low tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) Cin(LSE) ns OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL - time(1) V OSC32_IN Input leakage current 1. Specified by design, not tested in production. Figure 22. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 DS5319 Rev 18 51/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 23. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE EXTER NAL CLOCK SOURC E fLSE_ext STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. HSE 4-16 MHz oscillator characteristics(1) (2) Symbol Conditions Min Typ Max Unit Oscillator frequency - 4 8 16 MHz RF Feedback resistor - - 200 - kΩ C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30Ω - 30 - pF i2 HSE driving current VDD = 3.3 V, VIN = VSS with 30 pF load - - 1 mA Startup 25 - - mA/V VDD is stabilized - 2 - ms fOSC_IN Oscillator transconductance gm tSU(HSE Parameter (4) Startup time 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Evaluated by characterization, not tested in production, unless otherwise specified. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startu.p time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 52/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 24). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to AN2867 “Oscillator design guide for ST microcontrollers”, available from the ST website www.st.com. Figure 24. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF Bias controlled gain STM32F103xx OSC_OU T ai14145 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Symbol Parameter RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) I2 LSE driving current gm Oscillator transconductance tSU(LSE)(3) Startup time Conditions Min Typ Max Unit - - 5 - MΩ RS = 30 KΩ - - 15 pF VDD = 3.3 V, VIN = VSS - - 1.4 µA - 5 - - µA/V TA = 50 °C - 1.5 - TA = 25 °C - 2.5 - TA = 10 °C - 4 - TA = 0 °C - 6 - TA = -10 °C - 10 - TA = -20 °C - 17 - TA = -30 °C - 32 - TA = -40 °C - 60 - VDD is stabilized DS5319 Rev 18 s 53/116 115 Electrical characteristics STM32F103x8, STM32F103xB 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Refer to the note and caution paragraphs below the table, and to AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance, which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray, where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: when choosing a resonator with a load capacitance of CL = 6 pF and  Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 25. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit MHz fHSI Frequency - - 8 - DuCy(HSI) Duty cycle - 45 - 55 - - 1(3) TA = –40 to 105 °C –2 - 2.5 TA = –10 to 85 °C –1.5 - 2.2 TA = 0 to 70 °C –1.3 - 2 TA = 25 °C –1.1 - 1.8 User-trimmed with the RCC_CR register(2) ACCHSI Accuracy of the HSI Factoryoscillator calibrated (4)(5) 54/116 DS5319 Rev 18 % STM32F103x8, STM32F103xB Electrical characteristics Table 24. HSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit tsu(HSI)(4) HSI oscillator startup time - 1 - 2 µs IDD(HSI)(4) HSI oscillator power consumption - - 80 100 µA 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Refer to AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from www.st.com. 3. Specified by design, not tested in production. 4. Evaluated by characterization, not tested in production, unless otherwise specified. 5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified range. Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) Parameter Frequency Min Typ Max Unit 30 40 60 kHz (3) LSI oscillator startup time - - 85 µs (3) LSI oscillator power consumption - 0.65 1.2 µA IDD(LSI) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Evaluated by characterization, not tested in production, unless otherwise specified. 3. Specified by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:  Stop or Standby mode: the clock source is the RC oscillator  Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. DS5319 Rev 18 55/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 26. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Wakeup from Sleep mode 1.8 Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 Unit µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 - 60 % fPLL_OUT PLL multiplier output clock 16 - 72 MHz tLOCK PLL lock time - - 200 µs Jitter Cycle-to-cycle jitter - - 300 ps fPLL_IN 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 28. Flash memory characteristics Symbol tprog tERASE tME 56/116 Min(1) Typ Max(1) Unit 16-bit programming time TA–40 to +105 °C 40 52.5 70 µs Page (1 KB) erase time TA –40 to +105 °C 20 - 40 Mass erase time TA –40 to +105 °C 20 - 40 Parameter Conditions DS5319 Rev 18 ms STM32F103x8, STM32F103xB Electrical characteristics Table 28. Flash memory characteristics (continued) Symbol IDD Vprog Conditions Min(1) Typ Max(1) Read mode fHCLK = 72 MHz with two wait states, VDD = 3.3 V - - 20 Write / Erase modes  fHCLK = 72 MHz, VDD = 3.3 V - - 5 Power-down mode / Halt, VDD = 3.0 to 3.6 V - - 50 µA 2 - 3.6 V Parameter Supply current Programming voltage - Unit mA 1. Specified by design, not tested in production. Table 29. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Conditions Unit Min(1) Typ Max TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 - - 1 kcycle(2) at TA = 85 °C 30 - - at TA = 105 °C 10 - - (2) 20 - - Data retention 1 kcycle(2) 10 kcycles at TA = 55 °C kcycles Years 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Cycling performed over the whole temperature range. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:  Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.  FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 30. They are based on the EMS levels and classes defined in application note AN1709, available on www.st.com. DS5319 Rev 18 57/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 30. EMS characteristics Symbol Parameter Conditions Level/Class VFESD VDD 3.3 V, TA +25 °C,  Voltage limits to be applied on any I/O pin fHCLK 72 MHz to induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, TA +25 °C,  fHCLK 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flow must include the management of runaway conditions such as:  Corrupted program counter  Unexpected reset  Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015, available on www.st.com). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 31. EMI characteristics Symbol Parameter SEMI 58/116 Conditions Monitored frequency band 0.1 to 30 MHz VDD 3.3 V, TA 25 °C, 30 to 130 MHz LQFP100 package Peak level compliant with 130 MHz to 1GHz IEC 61967-2 SAE EMI Level DS5319 Rev 18 Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 12 12 22 19 23 29 4 4 dBµV - STM32F103x8, STM32F103xB 5.3.11 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 32. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Class Maximum value(1) Unit TA +25 °C Electrostatic discharge conforming to voltage (human body model) JESD22-A114 Electrostatic discharge VESD(CDM) voltage (charge device model) TA +25 °C conforming to ANSI/ESD STM5.3.1 2 2000 V II 500 1. Guaranteed based on test during characterization Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance:  A supply overvoltage is applied to each power supply pin  A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 33. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA +105 °C conforming to JESD78A DS5319 Rev 18 Class II level A 59/116 115 Electrical characteristics 5.3.12 STM32F103x8, STM32F103xB I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 34 Table 34. I/O current injection susceptibility Functional susceptibility Symbol IINJ 60/116 Description Unit Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 DS5319 Rev 18 mA STM32F103x8, STM32F103xB 5.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. I/O static characteristics Symbol VIL Parameter Low level input voltage Conditions Min Typ Max Standard IO input low level voltage - - 0.28*(VDD-2 V)+0.8 V(1) IO FT(3) input low level voltage - - 0.32*(VDD-2V)+0.75 V(1) All I/Os except BOOT0 - - 0.35 VDD(2) V Standard IO input high level voltage VIH Vhys Ilkg High level input voltage (1) 0.41*(VDD-2 V)+1.3 V - - IO FT(3) input high level voltage 0.42*(VDD-2 V)+1 V(1) - - All I/Os except BOOT0 0.65 VDD(2) - - 200 - - Standard IO Schmitt trigger voltage hysteresis(4) - IO FT Schmitt trigger voltage hysteresis(4) - 5% VDD(5) - - VSS VIN VDD Standard I/Os - - 1 VIN = 5 V I/O FT - - 3 30 40 50 Input leakage current (6) Unit mV RPU Weak pull-up equivalent resistor(7) VIN VSS RPD Weak pull-down equivalent resistor(7) VIN VDD CIO I/O pin capacitance µA kΩ 30 40 50 - 5 - pF 1. Data based on design simulation. 2. Tested in production. 3. FT = 5 V tolerant. To sustain a voltage higher than VDD + 0.3 V the internal pull-up/pull-down resistors must be disabled. 4. Hysteresis voltage between Schmitt trigger switching levels. Evaluated by characterization, not tested in production, unless otherwise specified. 5. With a minimum of 100 mV. 6. Leakage can be higher than Max if negative current is injected on adjacent pins. DS5319 Rev 18 61/116 115 Electrical characteristics STM32F103x8, STM32F103xB 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10%). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 26 and Figure 27 for standard I/Os, and in Figure 28 and Figure 29 for 5 V tolerant I/Os. Figure 26. Standard I/O input characteristics - CMOS port Area not determined VIH/VIL (V) =0.65V DD nt V IH uireme CMOS VIHmin VILmax in Tested on producti 1.3 (V -2)+ V IH=0.41 DD simulations gn si on de 1.96 Based 1.71 0.8 1.71 (V -2)+ V =0.28 DD mulations si 1.25 IL gn 1.08 si de 1.08 Based on 5V ment V IL=0.3 DD dard require rd req standa 1.59 1.3 1 CMOS stan 0.8 0.7 uction Tested in prod 2 2.7 3 3.3 VDD (V) 3.6 ai17277c Figure 27. Standard I/O input characteristics - TTL port VIH/VIL (V) VIHmin Area not determined TTL requirements VIH =2V -2)+1.3 =0.41(V DD 2.0 ns V IH atio sign simul 1.96 Based on de -2)+0.8 1.25 V IL=0.28(V DD ations design simul 1.3 VILmax Based on 0.8 TTL requirements 2 VIL=0.8V 2.16 3.6 VDD (V) ai17278b 62/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Figure 28. 5 V tolerant I/O input characteristics - CMOS port Area not determined VIH/VIL (V) =0.65V DD nts V IH quireme dard re OS stan CM in Tested on producti 1.3 1.295 0.975 1 0.7 0.75 1.55 1.16 -2)+1 V IH=0.42(V DD simulations gn si de on d 1.67 Base -2)+0.75 1 V IL=0.32(V DD ions sign simulat Based on de 1.42 1.07 5V DD ent V IL =0.3 dard requirm CMOS stan oduction Tested in pr 2 2.7 3 3.3 VDD (V) 3.6 VDD ai17279c Figure 29. 5 V tolerant I/O input characteristics - TTL port VIH/VIL (V) Area not determined TTL requirement V IH=2V 1 (V DD-2)+ ions V IH=0.42* si gn simulat de on ed 1.67 Bas -2)+0.75 1 V IL=0.32*(V DD simulations design Based on 2.0 VIHmin VILmax 0.8 0.75 TTL requirements V IL=0.8V 2 2.16 3.6 VDD (V) ai17280b DS5319 Rev 18 63/116 115 Electrical characteristics STM32F103x8, STM32F103xB Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15, which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:  The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7).  The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 36. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions Min Max CMOS port(2), IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD–0.4 - - 0.4 2.4 - - 1.3 VDD–1.3 - - 0.4 VDD–0.4 - TTL port(2) IIO =+ 8mA 2.7 V < VDD < 3.6 V Unit V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Evaluated by characterization, not tested in production, unless otherwise specified. 64/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 30 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. I/O AC characteristics(1) MODEx[1:0] bit value(1) Symbol Parameter Conditions Min Max Unit - 2 MHz - 125(3) - 125(3) - 10 - 25(3) - 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 CL = 50 pF, VDD = 2.7 V to 3.6 V - 30 CL = 50 pF, VDD = 2 V to 2.7 V - 20 CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) 10 - fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time CL = 50 pF, VDD = 2 V to 3.6 V fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time ns CL = 50 pF, VDD = 2 V to 3.6 V Pulse width of external signals detected by the EXTI controller - MHz ns MHz ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO port configuration register. 2. The maximum frequency is defined in Figure 30. 3. Specified by design, not tested in production. DS5319 Rev 18 65/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 30. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35). Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38. NRST pin characteristics Symbol Parameter Conditions Min Typ Max - –0.5 - 0.8 NRST Input high level voltage - 2 - VDD+0.5 NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN VSS 30 40 50 kΩ NRST Input filtered pulse - - - 100 ns NRST Input not filtered pulse - 300 - - ns VIL(NRST)(1) NRST Input low level voltage VIH(NRST) (1) Vhys(NRST) Weak pull-up equivalent RPU VF(NRST)(1) VNF(NRST) (1) resistor(2) Unit V 1. Specified by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10%). 66/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Figure 31. Recommended NRST pin protection VDD External reset circuit (1) RPU NRST (2) Internal Reset Filter 0.1 μF STM32 ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38, otherwise the reset is not taken into account by the device. 5.3.15 TIM timer characteristics The parameters given in Table 39 are specified by design, not tested in production. Refer to Section 5.3.12 for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 39. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz Timer resolution - 16 bit 65536 tTIMxCLK 910 µs - 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected tMAX_COUNT Maximum possible count - - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.6 s 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. DS5319 Rev 18 67/116 115 Electrical characteristics 5.3.16 STM32F103x8, STM32F103xB Communications interfaces I2C interface characteristics The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40. Refer also to Section 5.3.12 for more details on the input/output alternate function characteristics (SDA and SCL). Table 40. I2C characteristics Standard mode I2C(1)(2) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max - tw(SCLL) SCL clock low time 4.7 - 1.3 tw(SCLH) SCL clock high time 4.0 - 0.6 tsu(SDA) SDA setup time 250 - 100 - - 900(3) µs th(SDA) SDA data hold time - 3450(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s ns µs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of spikes suppressed by the analog filter 0 50(4) 0 50(4) ns 1. Specified by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum Data hold time must be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 68/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Figure 32. I2C bus AC waveforms and measurement circuit VDD_I2C VDD_I2C Rp Rp STM32F10x Rs SDA I²C bus Rs SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) th(SDA) tw(SCLH) tsu(STO:STA) Stop SCL tw(SCLL) tr(SCL) tsu(STO) tf(SCL) ai14133g 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply. Table 41. SCL frequency (fPCLK1 = 36 MHz, VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend upon the accuracy of the external components used to design the application. DS5319 Rev 18 69/116 115 Electrical characteristics STM32F103x8, STM32F103xB SPI interface characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12 for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. SPI characteristics Symbol Min Max Master mode - 18 Slave mode - 18 - 8 ns Slave mode 30 70 % tsu(NSS)(1) NSS setup time Slave mode 4 tPCLK - th(NSS)(1) Slave mode 2 tPCLK - Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3 tPCLK tdis(SO)(1)(3) fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) Parameter Conditions SPI clock frequency SPI clock rise and fall time Capacitive load: C = 30 pF SPI slave input clock duty cycle NSS hold time (1) tw(SCKH) SCK high and low time tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) th(MI) Data input setup time (1) th(SI)(1) Data input hold time Data output disable time Slave mode 2 10 (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(SO) th(SO) (1) th(MO) (1) Data output hold time Unit MHz 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 70/116 DS5319 Rev 18 ns STM32F103x8, STM32F103xB Electrical characteristics Figure 33. SPI timing diagram - slave mode and CPHA = 0 SCK input NSS input MISO OUTPUT MSB OUT BIT6 OUT MSB IN BIT1 IN LSB OUT (SI) MOSI INPUT LSB IN (SI) Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DS5319 Rev 18 71/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 35. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 43. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time 1. Specified by design, not tested in production. 72/116 DS5319 Rev 18 Max Unit 1 µs STM32F103x8, STM32F103xB Electrical characteristics Table 44. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V Input levels USB operating voltage(2) VDD VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 - VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 V Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(5) - 0.3 VOH Static output level high RL of 15 kΩ to VSS(5) 2.8 3.6 V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin must be pulled up with a 1.5 kΩ resistor to a 3.0 to 3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V, but not the full USB electrical characteristics, which are degraded in the 2.7 to 3.0 V VDD voltage range. 4. Specified by design, not tested in production. 5. RL is the load connected on the USB drivers. Figure 36. USB timings: definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 45. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Driver characteristics tr tf trfm VCRS Rise time(2) (2) Fall time Rise/ fall time matching Output signal crossover voltage 1. Specified by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB specification Section 7 (version 2.0). 5.3.17 CAN (controller area network) interface Refer to Section 5.3.12 for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). DS5319 Rev 18 73/116 115 Electrical characteristics 5.3.18 STM32F103x8, STM32F103xB 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 46. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 VREF+ Positive reference voltage - 2.4 - VDDA IVREF Current on the VREF input pin - - 160(1) 220(1) fADC ADC clock frequency - 0.6 - 14 fS(2) Sampling rate - 0.05 - 1 fADC = 14 MHz - - 823 kHz - - 17 1 / fADC 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 and Table 47 for details - - 50 fTRIG(2) External trigger frequency VAIN(3) Conversion voltage range RAIN(2) External input impedance RADC(2) Sampling switch resistance - - - 1 CADC(2) Internal sample and hold capacitor - - - 8 tCAL(2) Calibration time MHz pF fADC = 14 MHz 5.9 µs - 83 1 / fADC Injection trigger conversion latency fADC = 14 MHz - - - tlatr(2) Regular trigger conversion latency fADC = 14 MHz - - tS(2) Sampling time tSTAB(2) Power-up time Total conversion time (including sampling time) µA kΩ tlat(2) tCONV(2) V - - 0.214 3 (4) µs 1 / fADC 0.143 (4) µs 1 / fADC - - - 2 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1 / fADC - 0 0 1 µs fADC = 14 MHz 1 - 18 µs - 14 to 252 (tS for sampling +12.5 for successive approximation) 1 / fADC 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Specified by design, not tested in production. 3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 5 and Figure 7. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46. 74/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------- – R ADC N+2 f ADC  C ADC  ln  2  The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 47. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Evaluated by characterization, not tested in production, unless otherwise specified. Table 48. ADC accuracy - Limited test conditions(1) (2) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V,  TA = 25 °C Measurements made after ADC calibration Typ Max(3) ±1.3 ±2 ±1.0 ±1.5 ±0.5 ±1.5 ±0.7 ±1.0 ±0.8 ±1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins that may potentially inject negative currents.  Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 3. Evaluated by characterization, not tested in production, unless otherwise specified. DS5319 Rev 18 75/116 115 Electrical characteristics STM32F103x8, STM32F103xB Table 49. ADC accuracy(1) (2) (3) Symbol Parameter Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance can be achieved in restricted VDD, frequency and temperature ranges. 3. Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.  Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 4. Evaluated by characterization, not tested in production, unless otherwise specified. Figure 37. ADC accuracy characteristics VREF+ [1LSB = 2n Output code VDDA (or )] 2n EG (1) Example of an actual transfer curve (2) Ideal transfer curve (3) End-point correlation line 2n-1 2n-2 2n-3 (1) EL EO ED (2n/2n)*VREF+ (2n-1/2n)*VREF+ (2n-2/2n)*VREF+ (2n-3/2n)*VREF+ (7/2n)*VREF+ (6/2n)*VREF+ (5/2n)*VREF+ (4/2n)*VREF+ (3/2n)*VREF+ 1 LSB ideal (2/2n)*VREF+ 0 VSSA n = ADC resolution ET = total unadjusted error: maximum deviation between the actual and ideal transfer curves EO = offset error: maximum deviation between the first actual transition and the first ideal one EG = gain error: deviation between the last ideal transition and the last actual one ED = differential linearity error: maximum deviation between actual steps and the ideal one EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line (3) ET (1/2n)*VREF+ 7 6 5 4 3 2 1 (2) VREF+ (VDDA) MSv19880V6 76/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Electrical characteristics Figure 38. Typical connection diagram using the ADC VREF+(4) VDDA(4) Sample-and-hold ADC converter I/O analog switch RAIN(1) RADC Converter VAIN Cparasitic(2) Ilkg(3) VSS CADC Sampling switch with multiplexing VSSA VSS MSv67871V3 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 35 for the value of the pad capacitance). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 35 for the values of Ilkg. 4. Refer to Figure 14. General PCB design guidelines Power supply decoupling must be performed as shown in Figure 39 or Figure 40, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality), and placed as close as possible to the chip. Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 μF // 10 nF VDDA 1 μF // 10 nF VSSA /VREF– (see note 1) ai14388b 1. VREF+ and VREF– inputs are available only on 100-pin packages. DS5319 Rev 18 77/116 115 Electrical characteristics STM32F103x8, STM32F103xB Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 μF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 5.3.19 Temperature sensor characteristics Table 50. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min Typ Max Unit - 1 2 °C Average slope 4.0 4.3 4.6 mV / °C Voltage at 25 °C 1.34 1.43 1.52 V Startup time 4 - 10 ADC sampling time when reading the temperature - - 17.1 VSENSE linearity with temperature µs 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. Specified by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 78/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 VFQFPN36 package information This VFQFPN is a 36-pin, 6x6 mm, 0.5 mm pitch, very thin profile fine pitch quad flat package. Figure 41. VFQFPN36 outline Seating plane C ddd C A2 A A1 A3 E2 b 27 19 18 28 e D2 D K 36 Pin # 1 ID R = 0.20 10 1 9 L L E ZR_ME_V2 1. Drawing is not to scale. DS5319 Rev 18 79/116 115 Package information STM32F103x8, STM32F103xB Table 51. VFQFPN36 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 - 0.020 0.050 - 0.0008 0.0020 A2 - 0.650 1.000 - 0.0256 0.0394 A3 - 0.250 - - 0.0098 - b 0.180 0.230 0.300 0.0071 0.0091 0.0118 D 5.875 6.000 6.125 0.2313 0.2362 0.2411 D2 1.750 3.700 4.250 0.0689 0.1457 0.1673 E 5.875 6.000 6.125 0.2313 0.2362 0.2411 E2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 L 0.350 0.550 0.750 0.0138 0.0217 0.0295 K 0.250 - - 0.0098 - - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 80/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Figure 42. VFQFPN36 recommended footprint 1.00 4.30 27 19 28 18 0.50 4.10 4.30 4.10 4.80 4.80 36 10 1 9 0.75 0.30 6.30 ZR_FP_V1 DS5319 Rev 18 81/116 115 Package information STM32F103x8, STM32F103xB Marking of engineering samples Figure 43 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 43. VFPFPN36 package top view example Product identification(1) STM32 F103T8U6 Date code Y WW Revision code Pin 1 indentifier R MSv37531V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 82/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 6.2 Package information UFQFPN48 package information This UFQFPN is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package. Figure 44. UFQFPN48 outline Pin 1 identifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner R 0.125 typ. Detail Z E2 1 48 Z A0B9_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to the VSS or VDD power pads. It is recommended to connect it to VSS. 3. All leads/pads should also be soldered to the PCB to improve the lead solder joint life. Table 52. UFQFPN48 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 DS5319 Rev 18 83/116 115 Package information STM32F103x8, STM32F103xB Table 52. UFQFPN48 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 45. UFQFPN48 recommended footprint 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 24 0.50 0.55 5.80 1. Dimensions are expressed in millimeters. 84/116 DS5319 Rev 18 0.75 A0B9_FP_V2 STM32F103x8, STM32F103xB Package information Marking of engineering samples Figure 46 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. UFQFPN48 package top view example Product identification (1) STM32F 103CBU6 Date code Y WW Pin 1 identifier Revision code R MS37524V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS5319 Rev 18 85/116 115 Package information 6.3 STM32F103x8, STM32F103xB LFBGA100 package information This LFBGA is a 100-ball, 10x10 mm, low-profile fine pitch ball grid array, 0.8 mm pitch Figure 47. LFBGA100 outline Z Seating plane ddd Z A4 A2 A1 A E1 e X A1 ball A1 ball identifier index area F E A F D1 D e Y K 10 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW H0_ME_V2 1. Drawing is not to scale. Table 53. LFBGA100 mechanical data inches(1) millimeters Symbol 86/116 Min Typ Max Min Typ Max A - - 1.700 - - 0.0669 A1 0.270 - - 0.0106 - - A2 - 0.300 - - 0.0118 - A4 - - 0.800 - - 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 7.200 - - 0.2835 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 1.400 - - 0.0551 - ddd - - 0.120 - - 0.0047 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 48. LFBGA100 recommended footprint Dpad Dsm H0_FP_V1 Table 54. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.500 mm Dsm 0.570 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.500 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DS5319 Rev 18 87/116 115 Package information STM32F103x8, STM32F103xB Marking of engineering samples Figure 49 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 49. LFBGA100 package top view example Revision code Product identification(1) R STM32F103 V8H6 Date code = year + week Y WW Ball A1 indentifier 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 88/116 DS5319 Rev 18 STM32F103x8, STM32F103xB LQFP100 package information This LQFP is a 100-pin, 14x14 mm, low-profile quad flat package. Figure 50. LQFP100 outline 0.25 mm c A1 A SEATING PLANE C A2 GAUGE PLANE D A1 K ccc C L D1 L1 D3 51 75 76 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 6.4 Package information 25 e 1L_ME_V5 Table 55. LQPF100 mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.2 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.00 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - DS5319 Rev 18 89/116 115 Package information STM32F103x8, STM32F103xB Table 55. LQPF100 mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc -8 - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits.. Figure 51. LQFP100 recommended footprint 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. 90/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Marking of engineering samples Figure 52 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 52. LQFP100 package top view example Product identification(1) STM32F103 V8T6 R Revision code Date code Y WW Pin 1 indentifier MSv37526V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS5319 Rev 18 91/116 115 Package information 6.5 STM32F103x8, STM32F103xB UFBGA100 package information This UFBGA is a 100-ball, 7x7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package. Figure 53. UFBGA100 - outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y M 12 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW A0C2_ME_V4 1. Drawing is not to scale. Table 56. UFBGA100 mechanical data Symbol 92/116 inches(1) millimeters Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.100 - - 0.0039 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Table 56. UFBGA100 mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - -- 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 54. UFBGA100 recommended footprint Dpad Dsm A0C2_FP_V1 Table 57. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DS5319 Rev 18 93/116 115 Package information STM32F103x8, STM32F103xB Marking of engineering samples Figure 46 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 55. UFBGA100 package top view example Product identification (1) STM32F 103VBI6 Date code Y WW Ball A1 identifier Revision code R MS37527V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 94/116 DS5319 Rev 18 STM32F103x8, STM32F103xB LQFP64 package information This LQFP is a 64-pin, 10x10 mm low-profile quad flat package. Figure 56. LQFP64 outline 0.25 mm GAUGE PLANE c A1 A SEATING PLANE C A2 A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 b E3 6.6 Package information 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 58. LQFP64 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS5319 Rev 18 95/116 115 Package information STM32F103x8, STM32F103xB Table 58. LQFP64 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 57. LQFP64 recommended footprint 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are expressed in millimeters. 96/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Marking of engineering samples Figure 58 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 58. LQFP64 package top view example Revision code Product identification(1) R STM32F103 R8T6 Date code Y WW Pin 1 indentifier MSv37530V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS5319 Rev 18 97/116 115 Package information 6.7 STM32F103x8, STM32F103xB TFBGA64 package information This TFBGA is a 64-ball, 5x5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package. Figure 59. TFBGA64 outline E1 A E F e H F D D1 Øb (64 balls) Ø eee M C B A Ø fff M C A B e 1 A1 ball index area TOP VIEW A1 ball identifier 8 BOTTOM VIEW C Seating plane ddd C A4 A2 A1 A SIDE VIEW R8_ME_V4 1. Drawing is not to scale. Table 59. TFBGA64 mechanical data inches(1) millimeters Symbol 98/116 Min Typ Max Min Typ Max A - - 1.200 - - 0.0472 A1 0.150 - - 0.0059 - - A2 - 0.200 - - 0.0079 - A4 - - 0.600 - - 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 - 3.500 - - 0.1378 - E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 - 3.500 - - 0.1378 - e - 0.500 - - 0.0197 - F - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Table 59. TFBGA64 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 60. TFBGA64 recommended footprint Dpad Dsm R8_FP_V1 Table 60. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 1.125 mm Pad trace width 0.100 mm Marking of engineering samples Figure 61 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. DS5319 Rev 18 99/116 115 Package information STM32F103x8, STM32F103xB Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 61. TFBGA64 package top view example Product identification(1) 32F10386 Date code Y WW Revision code Ball A1 indentifier R MSv37528V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 100/116 DS5319 Rev 18 STM32F103x8, STM32F103xB LQFP48 package information This LQFP is a 48-pin, 7x7 mm low-profile quad flat package. Figure 62. LQFP48 outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 E E1 b E3 6.8 Package information 13 PIN 1 IDENTIFICATION 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 61. LQFP48 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 DS5319 Rev 18 101/116 115 Package information STM32F103x8, STM32F103xB Table 61. LQFP48 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 63. LQFP48 - 48-pin recommended footprint 0.50 1.20 9.70 0.30 25 36 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. 102/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Package information Marking of engineering samples Figure 64 gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 64. LQFP48 package top view example Product identification (1) STM32 F103CBT6 Date code Y WW Pin 1 identification Revision code R MS37529V1 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS5319 Rev 18 103/116 115 Package information 6.9 STM32F103x8, STM32F103xB Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) where:  TA max is the maximum ambient temperature in C,  JA is the package junction-to-ambient thermal resistance, in C/W,  PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),  PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 62. Package thermal characteristics Symbol JA 6.9.1 Parameter Value Thermal resistance junction-ambient LFBGA100 - 10 × 10 mm / 0.8 mm pitch 44 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient UFBGA100 - 7 × 7 mm / 0.5 mm pitch 59 Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient TFBGA64 - 5 × 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient UFQFPN 48 - 7 × 7 mm / 0.5 mm pitch 32 Thermal resistance junction-ambient VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch 18 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 104/116 DS5319 Rev 18 STM32F103x8, STM32F103xB 6.9.2 Package information Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 7. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 62 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 7). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW DS5319 Rev 18 105/116 115 Package information STM32F103x8, STM32F103xB Using the values obtained in Table 62 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 7). Figure 65. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 TA (°C) 106/116 DS5319 Rev 18 115 125 135 STM32F103x8, STM32F103xB 7 Ordering information scheme Ordering information scheme  Example: STM32 F 103 C 8 T 7 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = General-purpose Device subfamily 103 = Performance line Pin count T = 36 pins C = 48 pins R = 64 pins V = 100 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package H = BGA I = UFBGA T = LQFP U = VFQFPN or UFQFPN Temperature range 6 = Industrial temperature range, –40 to 85 °C 7 = Industrial temperature range, –40 to 105 °C Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact your nearest ST sales office. DS5319 Rev 18 107/116 115 Revision history 8 STM32F103x8, STM32F103xB Revision history Table 63. Document revision history Date Revision 01-Jun-2007 1 Initial release. 2 Flash memory size modified in Note 9, Note 5, Note 7, Note 7 and BGA100 pins added to Table 5: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line LFBGA100 ballout added. THSE changed to TLSE in Figure 23: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes. tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator characteristics. IDD(HSI) max value added to Table 24: HSI oscillator characteristics. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latchup. 25 °C and 85 °C conditions removed and class name modified in Table 33: Electrical sensitivities. RPU and RPD min and max values added to Table 35: I/O static characteristics. RPU min and max values added to Table 38: NRST pin characteristics. Figure 32: I2C bus AC waveforms and measurement circuit and Figure 31: Recommended NRST pin protection corrected. Notes removed below Table 9, Table 38, Table 44. IDD typical values changed in Table 11: Maximum current consumption in Run and Sleep modes. Table 39: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 46: ADC characteristics. In Table : , typical endurance and data retention for TA = 85 °C added, data retention for TA = 25 °C removed. VBG changed to VREFINT in Table 12: Embedded internal reference voltage. Document title changed. Controller area network (CAN) section modified. Figure 14: Power supply scheme modified. Features on page 1 list optimized. Small text changes. 20-Jul-2007 108/116 Changes DS5319 Rev 18 STM32F103x8, STM32F103xB Revision history Table 63. Document revision history (continued) Date 18-Oct-2007 Revision Changes 3 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see Section 6: Package information). All packages are ECOPACK® compliant. Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package information). Table 5: Medium-density STM32F103xx pin definitions updated and clarified. Table 26: Low-power mode wakeup timings updated. TA min corrected in Table 12: Embedded internal reference voltage. Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics. VESD(CDM) value added to Table 32: ESD absolute maximum ratings. Note 4 added and VOH parameter description modified in Table 36: Output voltage characteristics. Note 1 modified under Table 37: I/O AC characteristics. Equation 1 and Table 47: RAIN max for fADC = 14 MHz added to Section 5.3.18: 12-bit ADC characteristics. VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified and tlatr added in Table 46: ADC characteristics. Figure 37: ADC accuracy characteristics updated. Note 1 modified below Figure 38: Typical connection diagram using the ADC. Electrostatic discharge (ESD) on page 59 modified. Number of TIM4 channels modified in Figure 1: STM32F103xx performance line block diagram. Maximum current consumption Table 13, Table 14 and Table 15 updated. Vhysmodified in Table 35: I/O static characteristics. Table 49: ADC accuracy updated. VFESD value added in Table 30: EMS characteristics. Values corrected, note 2 modified and note 3 removed in Table 26: Lowpower mode wakeup timings. Table 16: Typical and maximum current consumptions in Stop and Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2 modified, Note 2 added. Table 21: Typical current consumption in Standby mode added. On-chip peripheral current consumption on page 49 added. ACCHSI values updated in Table 24: HSI oscillator characteristics. Vprog added to Table 28: Flash memory characteristics. Upper option byte address modified in Figure 11: Memory map. Typical fLSI value added in Table 25: LSI oscillator characteristics and internal RC value corrected from 32 to 40 kHz in entire document. TS_temp added to Table 50: TS characteristics. NEND modified in Table : . TS_vrefint added to Table 12: Embedded internal reference voltage. Handling of unused pins specified in General input/output characteristics on page 61. All I/Os are CMOS and TTL compliant. Figure 39: Power supply and reference decoupling (VREF+ not connected to VDDA) modified. tJITTER and fVCO removed from Table 27: PLL characteristics. Appendix A: Important notes on page 81 added. Added Figure 16, Figure 17, Figure 19 and Figure 21. DS5319 Rev 18 109/116 115 Revision history STM32F103x8, STM32F103xB Table 63. Document revision history (continued) Date 22-Nov-2007 110/116 Revision Changes 4 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 15 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-density device features and peripheral counts. Main function and default alternate function modified for PC14 and PC15 in, Note 6 added and Remap column added in Table 5: Medium-density STM32F103xx pin definitions. VDD–VSS ratings and Note 1 modified in Table 6: Voltage characteristics, Note 1 modified in Table 7: Current characteristics. Note 1 and Note 2 added in Table 11: Embedded reset and power control block characteristics. IDD value at 72 MHz with peripherals enabled modified in Table 14: Maximum current consumption in Run mode, code with data processing running from RAM. IDD value at 72 MHz with peripherals enabled modified in Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM on page 43. IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Note added in Table 17 on page 47 and Table 18 on page 48. ADC1 and ADC2 consumption and notes modified in Table 19: Peripheral current consumption. tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23, respectively. Maximum values removed from Table 26: Low-power mode wakeup timings. tRET conditions modified in Table : . Figure 14: Power supply scheme corrected. Figure 20: Typical current consumption in Stop mode, with regulator in Low-power mode added. Note removed below Figure 33: SPI timing diagram - slave mode and CPHA = 0. Note added below Figure 34: SPI timing diagram - slave mode and CPHA = 1(1). Details on unused pins removed from General input/output characteristics on page 61. Table 42: SPI characteristics updated. Table 43: USB startup time added. VAIN, tlat and tlatr modified, note added and Ilkg removed in Table 46: ADC characteristics. Test conditions modified and note added in Table 49: ADC accuracy. Note added below Table 47 and Table 50. Inch values corrected in Table 55: LQPF100 mechanical data, Table 58: LQFP64 mechanical data and Table 60: LQFP48, 7 x 7 mm, 48-pin lowprofile quad flat package mechanical data. JAvalue for VFQFPN36 package added in Table 62: Package thermal characteristics Order codes replaced by Section 7: Ordering information scheme. MCU ‘s operating conditions modified in Typical current consumption on page 46. Avg_Slope and V25 modified in Table 50: TS characteristics. I2C interface characteristics on page 68 modified. Impedance specified in A.4: Voltage glitch on ADC input 0 on page 81. DS5319 Rev 18 STM32F103x8, STM32F103xB Revision history Table 63. Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 22-May-2008 Revision Changes 5 Figure 2: Clock tree on page 12 added. Maximum TJ value given in Table 8: Thermal characteristics on page 37. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 11: Memory map on page 34 for address). IDD modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. ACCHSI modified in Table 24: HSI oscillator characteristics on page 54, note 2 removed. PD, TA and TJ added, tprog values modified and tprog description clarified in Table 28: Flash memory characteristics on page 56. tRET modified in Table : . VNF(NRST) unit corrected in Table 38: NRST pin characteristics on page 66. Table 42: SPI characteristics on page 70 modified. IVREF added to Table 46: ADC characteristics on page 74. Table 48: ADC accuracy - Limited test conditions added. Table 49: ADC accuracy modified. LQFP100 package specifications updated (see Section 6: Package information on page 79). Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36 footprints added (see Figure 55, Figure 60, Figure 64 and Figure 44). Section 6.9: Thermal characteristics on page 104 modified, Section 6.9.1 and Section 6.9.2 added. Appendix A: Important notes on page 81 removed. 6 Small text changes. Figure 11: Memory map clarified. In Table : : – NEND tested over the whole temperature range – cycling conditions specified for tRET – tRET min modified at TA = 55 °C V25, Avg_Slope and TL modified in Table 50: TS characteristics. CRC feature removed. 7 CRC feature added back. Small text changes. Section 1: Introduction modified. Section 2.2: Full compatibility throughout the family added. IDD at TA max = 105 °C added to Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 44. IDD_VBAT removed from Table 21: Typical current consumption in Standby mode on page 47. Values added to Table 41: SCL frequency (fPCLK1 = 36 MHz, VDD_I2C = 3.3 V) on page 69. Figure 33: SPI timing diagram - slave mode and CPHA = 0 on page 71 modified. Equation 1 corrected. tRET at TA = 105 °C modified in Table : on page 57. VUSB added to Table 44: USB DC electrical characteristics on page 73. Figure 65: LQFP100 PD max vs. TA on page 106 modified. Axx option added to Table 63: Ordering information scheme on page 110. DS5319 Rev 18 111/116 115 Revision history STM32F103x8, STM32F103xB Table 63. Document revision history (continued) Date 21-Jul-2008 22-Sep-2008 112/116 Revision Changes 8 Power supply supervisor updated and VDDA added to Table 9: General operating conditions. Capacitance modified in Figure 14: Power supply scheme on page 36. Table notes revised in Section 5: Electrical characteristics. Table 16: Typical and maximum current consumptions in Stop and Standby modes modified. Data added to Table 16: Typical and maximum current consumptions in Stop and Standby modes and Table 21: Typical current consumption in Standby mode removed. fHSE_ext modified in Table 20: High-speed external user clock characteristics on page 50. fPLL_IN modified in Table 27: PLL characteristics on page 56. Minimum SDA and SCL fall time value for Fast mode removed from Table 40: I2C characteristics on page 68, note 1 modified. th(NSS) modified in Table 42: SPI characteristics on page 70 and Figure 33: SPI timing diagram - slave mode and CPHA = 0 on page 71. CADC modified in Table 46: ADC characteristics on page 74 and Figure 38: Typical connection diagram using the ADC modified. Typical TS_temp value removed from Table 50: TS characteristics on page 78. LQFP48 package specifications updated (see Table 60 and Table 64), Section 6: Package information revised. Axx option removed from Table 63: Ordering information scheme on page 110. Small text changes. 9 STM32F103x6 part numbers removed (see Table 63: Ordering information scheme). Small text changes. General-purpose timers (TIMx) and Advanced-control timer (TIM1) on page 18 updated. Notes updated in Table 5: Medium-density STM32F103xx pin definitions on page 28. Note 2 modified below Table 6: Voltage characteristics on page 37, |VDDx| min and |VDDx| min removed. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 40. IDD in standby mode at 85 °C modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 44. General input/output characteristics on page 61 modified. fHCLK conditions modified in Table 30: EMS characteristics on page 58. JA and pitch value modified for LFBGA100 package in Table 62: Package thermal characteristics. Small text changes. DS5319 Rev 18 STM32F103x8, STM32F103xB Revision history Table 63. Document revision history (continued) Date 23-Apr-2009 22-Sep-2009 03-Jun-2010 Revision Changes 10 I/O information clarified on page 1. Figure 3: STM32F103xx performance line LFBGA100 ballout modified. Figure 11: Memory map modified. Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column in Table 5: Medium-density STM32F103xx pin definitions. PD for LFBGA100 corrected in Table 9: General operating conditions. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Figure 20 shows a typical curve (title modified). ACCHSI max values modified in Table 24: HSI oscillator characteristics. TFBGA64 package added (see Table 59 and Table 60). Small text changes. 11 Note 5 updated and Note 4 added in Table 5: Medium-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. IDD_VBAT value added to Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 18: Typical current consumption on VBAT (RTC on) added. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings. Note 1 modified below Figure 24: Typical application with an 8 MHz crystal. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 57. Jitter added to Table 27: PLL characteristics. Table 42: SPI characteristics modified. CADC and RAIN parameters modified in Table 46: ADC characteristics. RAIN max values modified in Table 47: RAIN max for fADC = 14 MHz. Figure 47: LFBGA100 outline updated. 12 Added STM32F103TB devices. Added VFQFPN48 package. Updated note 2 below Table 40: I2C characteristics Updated Figure 32: I2C bus AC waveforms and measurement circuit Updated Figure 31: Recommended NRST pin protection Updated Section 5.3.12: I/O current injection characteristics DS5319 Rev 18 113/116 115 Revision history STM32F103x8, STM32F103xB Table 63. Document revision history (continued) Date Revision Changes 19-Apr-2011 13 Updated footnotes below Table 6: Voltage characteristics on page 37 and Table 7: Current characteristics on page 37 Updated tw min in Table 20: High-speed external user clock characteristics on page 50 Updated startup time in Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 53 Added Section 5.3.12: I/O current injection characteristics Updated Section 5.3.13: I/O port characteristics 07-Dec-2012 14 Added UFBGA100 7 x 7 mm. Updated Figure 59: LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline to add pin 1 identification. 15 Replaced VQFN48 package with UQFN48 in cover page packages, Table 2: STM32F103xx medium-density device features and peripheral counts, Figure 9: STM32F103xx performance line UFQFPN48 pinout, Table 2: STM32F103xx medium-density device features and peripheral counts, Table 56: UFBGA100 mechanical data, Table 63: Ordering information scheme and updated Table 62: Package thermal characteristics Added footnote for TFBGA ADC channels in Table 2: STM32F103xx medium-density device features and peripheral counts Updated ‘All GPIOs are high current...’ in Section 2.3.21: GPIOs (general-purpose inputs/outputs) Updated Table 5: Medium-density STM32F103xx pin definitions Corrected Sigma letter in Section 5.1.1: Minimum and maximum values Removed the first sentence in Section 5.3.16: Communications interfaces Added ‘VIN’ in Table 9: General operating conditions Updated first sentence in Output driving current Added note 5. in Table 24: HSI oscillator characteristics Updated ‘VIL’ and ‘VIH’ in Table 35: I/O static characteristics Added notes to Figure 26: Standard I/O input characteristics - CMOS port, Figure 27: Standard I/O input characteristics - TTL port, Figure 28: 5 V tolerant I/O input characteristics - CMOS port and Figure 29: 5 V tolerant I/O input characteristics - TTL port Updated Figure 32: I2C bus AC waveforms and measurement circuit Updated note 2. and 3.,removed note “the device must internally...” in Table 40: I2C characteristics Updated title of Table 41: SCL frequency (fPCLK1 = 36 MHz, VDD_I2C = 3.3 V) Updated note 2. in Table 49: ADC accuracy Updated Figure 53: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline and Table 56: UFBGA100 mechanical data Updated Figure 47: LFBGA100 outline and Table 53: LFBGA100 mechanical data Updated Figure 60: TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline and Table 59: TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data 14-May-2013 114/116 DS5319 Rev 18 STM32F103x8, STM32F103xB Revision history Table 63. Document revision history (continued) Date 05-Aug-2013 21-Aug-2015 29-Mar-2022 Revision Changes 16 Updated the reference for ‘VESD(CDM)’ in Table 32: ESD absolute maximum ratings Corrected ‘tf(IO)out’ in Figure 30: I/O AC characteristics definition Updated Table 52: UFQFPN48 mechanical data 17 Updated Table 3: STM32F103xx family removing the note. Updated Table 63: Ordering information scheme removing the note. Updated Section 6: Package information and added Section : Marking of engineering samples for all packages. Updated I2C characteristics, added tSP parameter and note 4 in Table 40: I2C characteristics. Updated Figure 32: I2C bus AC waveforms and measurement circuit swapping SCLL and SCLH. Updated Figure 33: SPI timing diagram - slave mode and CPHA = 0. Updated min/max value notes replacing ‘Guaranteed by design, not tested in production” by “guaranteed by design”. Updated min/max value notes replacing ‘based on characterization, not tested in production” by “Guaranteed based on test during characterization”. Updated Table 19: Peripheral current consumption. 18 Updated Table 5: Medium-density STM32F103xx pin definitions. Updated Figure 37: ADC accuracy characteristics, Figure 38: Typical connection diagram using the ADC and its footnotes. Minor text edits across the whole document. DS5319 Rev 18 115/116 115 STM32F103x8, STM32F103xB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved 116/116 DS5319 Rev 18