STM32F103x8
STM32F103xB
Medium-density performance line ARM®-based 32-bit MCU with 64
or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
Datasheet - production data
Features
• ARM® 32-bit Cortex®-M3 CPU Core
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
• Memories
– 64 or 128 Kbytes of Flash memory
– 20 Kbytes of SRAM
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
• Low-power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• 2 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
• DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
• Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
August 2015
This is information on a product in full production.
VFQFPN36 6 × 6 mm
BGA100 10 × 10 mm
UFBGA100 7 x 7 mm
BGA64 5 × 5 mm
UFQFPN48 7 × 7 mm
LQFP100 14 × 14 mm
LQFP64 10 × 10 mm
LQFP48 7 × 7 mm
• Debug mode
– Serial wire debug (SWD) & JTAG
interfaces
• 7 timers
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 16-bit, motor control PWM timer with deadtime generation and emergency stop
– 2 watchdog timers (Independent and
Window)
– SysTick timer 24-bit downcounter
• Up to 9 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full-speed interface
• CRC calculation unit, 96-bit unique ID
• Packages are ECOPACK®
Table 1. Device summary
Reference
Part number
STM32F103x8
STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xB
STM32F103RB STM32F103VB,
STM32F103CB, STM32F103TB
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Contents
STM32F103x8, STM32F103xB
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 14
2.3.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14
2.3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14
2.3.6
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.7
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.8
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.9
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.10
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.11
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.12
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.13
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17
2.3.15
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.16
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.17
Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.18
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.19
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.21
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.22
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.23
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.24
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
6
Contents
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 39
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 40
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 60
5.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.17
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.18
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.19
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.1
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package information . . . . . . . . . . . 80
6.2
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . . 84
6.3
LFBGA100 10 x 10 mm, low-profile fine pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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STM32F103x8, STM32F103xB
6.4
LQFP100 14 x 14 mm, 100-pin low-profile quad flat package information 90
6.5
UFBGA100 7x 7 mm, ultra fine pitch ball grid array package information 93
6.6
LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information . . 96
6.7
TFBGA64 5 x 5 mm, thin profile fine pitch package information . . . . . . . 99
6.8
LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information . . . 102
6.9
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.9.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.9.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 106
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 44
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 45
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
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USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . . 88
LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 90
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 94
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 100
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DocID13587 Rev 17
STM32F103x8, STM32F103xB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F103xx performance line UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F103xx performance line UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 43
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 43
Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical current consumption in Standby mode versus temperature at
VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 78
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 79
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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8
List of figures
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
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STM32F103x8, STM32F103xB
VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VFPFPN36 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . . 86
LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LFBGA100 package top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 90
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UFBGA100 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 96
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TFBGA64 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 102
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DocID13587 Rev 17
STM32F103x8, STM32F103xB
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers.
For more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F103xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference
Manual, available from the www.arm.com website.
2
Description
The STM32F103xx medium-density performance line family incorporates the highperformance ARM® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as
well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three
USARTs, an USB and a CAN.
The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to
+85 °C temperature range and the –40 to +105 °C extended temperature range. A
comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F103xx medium-density performance line family includes devices in six different
package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx medium-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and
HVACs.
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Description
2.1
STM32F103x8, STM32F103xB
Device overview
Table 2. STM32F103xx medium-density device features and peripheral
counts
Peripheral
Flash - Kbytes
Communication
Timers
SRAM - Kbytes
STM32F103Tx
64
128
STM32F103Cx
64
128
STM32F103Rx
64
128
STM32F103Vx
64
128
20
20
20
20
General-purpose
3
3
3
3
Advanced-control
1
1
1
1
SPI
1
2
2
2
I2C
1
2
2
2
USART
2
3
3
3
USB
1
1
1
1
CAN
1
1
1
1
26
37
51
80
2
10 channels
2
10 channels
2
16 channels(1)
2
16 channels
GPIOs
12-bit synchronized ADC
Number of channels
CPU frequency
72 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient temperatures: -40 to +85 °C / -40 to +105 °C (see Table 9)
Junction temperature: -40 to + 125 °C (see Table 9)
VFQFPN36
LQFP48,
UFQFPN48
LQFP64,
TFBGA64
LQFP100,
LFBGA100,
UFBGA100
1. On the TFBGA64 package only 15 channels are available (one analog input pin has been replaced by
‘Vref+’).
10/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Description
Figure 1. STM32F103xx performance line block diagram
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116
Description
STM32F103x8, STM32F103xB
Figure 2. Clock tree
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DocID13587 Rev 17
STM32F103x8, STM32F103xB
Pinouts and pin description
Figure 7. STM32F103xx performance line TFBGA64 ballout
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DocID13587 Rev 17
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116
Electrical characteristics
STM32F103x8, STM32F103xB
Figure 38. Typical connection diagram using the ADC
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#PARASITIC
64
6
),!
#!$#
AIC
1. Refer to Table 46 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 39 or Figure 40,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA)
670)[[
95()
VHHQRWH
)Q)
9''$
)Q)
966$ 95()±
VHHQRWH
DLE
1. VREF+ and VREF– inputs are available only on 100-pin packages.
78/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Electrical characteristics
Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA)
670)[[
95()9''$
6HHQRWH
)Q)
95()±966$
6HHQRWH
DL
1. VREF+ and VREF– inputs are available only on 100-pin packages.
5.3.19
Temperature sensor characteristics
Table 50. TS characteristics
Symbol
TL(1)
Avg_Slope(1)
V25(1)
tSTART(2)
TS_temp(3)(2)
Parameter
Min
Typ
Max
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25 °C
1.34
1.43
1.52
V
Startup time
4
-
10
µs
ADC sampling time when reading the
temperature
-
-
17.1
µs
VSENSE linearity with temperature
1. Guaranteed based on test during characterization.
2. Guaranteed by design.
3. Shortest sampling time can be determined in the application by multiple iterations.
DocID13587 Rev 17
79/117
116
Package information
6
STM32F103x8, STM32F103xB
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package information
Figure 41. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline
6HDWLQJSODQH
&
GGG
&
$ $
$
$
(
E
H
'
'
.
3LQ,'
5
(
/
/
:2?-%?6
1. Drawing is not to scale.
80/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Table 51. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
-
0.020
0.050
-
0.0008
0.0020
A2
-
0.650
1.000
-
0.0256
0.0394
A3
-
0.250
-
-
0.0098
-
b
0.180
0.230
0.300
0.0071
0.0091
0.0118
D
5.875
6.000
6.125
0.2313
0.2362
0.2411
D2
1.750
3.700
4.250
0.0689
0.1457
0.1673
E
5.875
6.000
6.125
0.2313
0.2362
0.2411
E2
1.750
3.700
4.250
0.0689
0.1457
0.1673
e
0.450
0.500
0.550
0.0177
0.0197
0.0217
L
0.350
0.550
0.750
0.0138
0.0217
0.0295
K
0.250
-
-
0.0098
-
-
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID13587 Rev 17
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116
Package information
STM32F103x8, STM32F103xB
Figure 42. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint
:2?&0?6
82/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 43. VFPFPN36 package top view example
3URGXFWLGHQWLILFDWLRQ
670
)78
'DWHFRGH
< ::
5HYLVLRQFRGH
3LQ
LQGHQWLILHU
5
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID13587 Rev 17
83/117
116
Package information
6.2
STM32F103x8, STM32F103xB
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information
Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
3LQLGHQWLILHU
ODVHUPDUNLQJDUHD
'
$
(
(
7
GGG
$
6HDWLQJ
SODQH
E
H
'HWDLO<
'
([SRVHGSDG
DUHD
<
'
/
&[
SLQFRUQHU
5W\S
'HWDLO=
(
=
$% B0(B9
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to
the VSS or VDD power pads. It is recommended to connect it to VSS.
3. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
Table 52. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
inches(1)
millimeters
Symbol
84/117
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
D
6.900
7.000
7.100
0.2717
0.2756
0.2795
E
6.900
7.000
7.100
0.2717
0.2756
0.2795
D2
5.500
5.600
5.700
0.2165
0.2205
0.2244
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Table 52. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E2
5.500
5.600
5.700
0.2165
0.2205
0.2244
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 45. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
!"?&0?6
1. Dimensions are expressed in millimeters.
DocID13587 Rev 17
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116
Package information
STM32F103x8, STM32F103xB
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 46. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example
3URGXFW
LGHQWLILFDWLRQ
45.'
$#6
'DWHFRGH
: 88
3LQ
LGHQWLILHU
5HYLVLRQFRGH
3
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
86/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
6.3
Package information
LFBGA100 10 x 10 mm, low-profile fine pitch ball grid array
package information
Figure 47. LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10 x10 mm,
0.8 mm pitch, package outline
= 6HDWLQJSODQH
GGG =
$ $
$ $
(
H
;
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
(
$
)
'
'
H
<
.
%277209,(:
E EDOOV
HHH 0 = < ;
III 0 =
7239,(:
+B0(B9
1. Drawing is not to scale.
Table 53. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.700
-
-
0.0669
A1
0.270
-
-
0.0106
-
-
A2
-
0.300
-
-
0.0118
-
A4
-
-
0.800
-
-
0.0315
b
0.450
0.500
0.550
0.0177
0.0197
0.0217
D
9.850
10.000
10.150
0.3878
0.3937
0.3996
D1
-
7.200
-
-
0.2835
-
E
9.850
10.000
10.150
0.3878
0.3937
0.3996
E1
-
7.200
-
-
0.2835
-
e
-
0.800
-
-
0.0315
-
F
-
1.400
-
-
0.0551
-
ddd
-
-
0.120
-
-
0.0047
DocID13587 Rev 17
87/117
116
Package information
STM32F103x8, STM32F103xB
Table 53. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 48. LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package recommended footprint
'SDG
'VP
+B)3B9
Table 54. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
Dimension
88/117
Recommended values
Pitch
0.8
Dpad
0.500 mm
Dsm
0.570 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
0.500 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.120 mm
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 49. LFBGA100 package top view example
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
5
670)
9+
'DWHFRGH \HDUZHHN
< ::
%DOO$
LQGHQWLILHU
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID13587 Rev 17
89/117
116
Package information
6.4
STM32F103x8, STM32F103xB
LQFP100 14 x 14 mm, 100-pin low-profile quad flat package
information
Figure 50. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
MM
C
!
!
!
3%!4).'0,!.%
#
'!5'%0,!.%
$
!
+
CCC #
,
$
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
,?-%?6
Table 55. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical
data
Symbol
90/117
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.2
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.00
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Table 55. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data
(continued)
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-8
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits..
Figure 51. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
package recommended footprint
AIC
1. Dimensions are expressed in millimeters.
DocID13587 Rev 17
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116
Package information
STM32F103x8, STM32F103xB
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 52. LQFP100 package top view example
3URGXFWLGHQWLILFDWLRQ
670)
975
5HYLVLRQFRGH
'DWHFRGH
< ::
3LQ
LQGHQWLILHU
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
92/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
6.5
Package information
UFBGA100 7x 7 mm, ultra fine pitch ball grid array package
information
Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline
= 6HDWLQJSODQH
GGG =
$ $ $
$ $
(
H
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
;
(
$
)
'
'
H
<
0
%277209,(:
E EDOOV
HHH 0 = < ;
III 0 =
7239,(:
$&B0(B9
1. Drawing is not to scale.
Table 56. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
0.080
0.130
0.180
0.0031
0.0051
0.0071
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.450
5.500
5.550
0.2146
0.2165
0.2185
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.450
5.500
5.550
0.2146
0.2165
0.2185
e
-
0.500
-
-
0.0197
-
F
0.700
0.750
0.800
0.0276
0.0295
0.0315
DocID13587 Rev 17
93/117
116
Package information
STM32F103x8, STM32F103xB
Table 56. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data (continued)
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
--
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package recommended footprint
'SDG
'VP
$&B)3B9
Table 57. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension
94/117
Recommended values
Pitch
0.5
Dpad
0.280 mm
Dsm
0.370 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
0.280 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 55. UFBGA100 package top view example
3URGXFW
LGHQWLILFDWLRQ
45.'
7#*
'DWHFRGH
: 88
%DOO$
LGHQWLILHU
5HYLVLRQFRGH
3
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID13587 Rev 17
95/117
116
Package information
6.6
STM32F103x8, STM32F103xB
LQFP64 10 x 10 mm, 64-pin low-profile quad flat package
information
Figure 56. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
$
FFF &
'
'
'
.
/
/
3,1
,'(17,),&$7,21
(
(
(
E
H
:B0(B9
1. Drawing is not to scale.
Table 58. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
96/117
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Table 58. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 57. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
DocID13587 Rev 17
97/117
116
Package information
STM32F103x8, STM32F103xB
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 58. LQFP64 package top view example
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
5
670)
57
'DWHFRGH
< ::
3LQ
LQGHQWLILHU
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
98/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
6.7
Package information
TFBGA64 5 x 5 mm, thin profile fine pitch package
information
Figure 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline
(
$
(
)
H
+
)
'
'
E EDOOV
HHH 0 & % $
III 0 &
$
%
H
$EDOO
LQGH[DUHD
7239,(:
$EDOO
LGHQWLILHU
%277209,(:
& 6HDWLQJSODQH
GGG &
$
$
$ $
6,'(9,(:
5B0(B9
1. Drawing is not to scale.
Table 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
array package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.200
-
-
0.0472
A1
0.150
-
-
0.0059
-
-
A2
-
0.200
-
-
0.0079
-
A4
-
-
0.600
-
-
0.0236
b
0.250
0.300
0.350
0.0098
0.0118
0.0138
D
4.850
5.000
5.150
0.1909
0.1969
0.2028
D1
-
3.500
-
-
0.1378
-
E
4.850
5.000
5.150
0.1909
0.1969
0.2028
E1
-
3.500
-
-
0.1378
-
e
-
0.500
-
-
0.0197
-
F
-
0.750
-
-
0.0295
-
DocID13587 Rev 17
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116
Package information
STM32F103x8, STM32F103xB
Table 59. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
array package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
ddd
-
-
0.080
-
-
0.0031
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 60. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid
array package recommended footprint
'SDG
'VP
5B)3B9
Table 60. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension
100/117
Recommended values
Pitch
0.5
Dpad
0.280 mm
Dsm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.280 mm
Stencil thickness
Between 0.100 mm and 1.125 mm
Pad trace width
0.100 mm
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Marking of engineering samples
The following gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 61. TFBGA64 package top view example
3URGXFWLGHQWLILFDWLRQ
)
'DWHFRGH
< ::
5HYLVLRQFRGH
%DOO$
LQGHQWLILHU
5
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID13587 Rev 17
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116
Package information
6.8
STM32F103x8, STM32F103xB
LQFP48 7 x 7 mm, 48-pin low-profile quad flat package
information
Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
'!5'%0,!.%
CCC #
+
!
$
$
,
,
$
%
%
%
B
0).
)$%.4)&)#!4)/.
E
"?-%?6
1. Drawing is not to scale.
Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
102/117
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 63. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
AID
1. Dimensions are expressed in millimeters.
DocID13587 Rev 17
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116
Package information
STM32F103x8, STM32F103xB
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 64. LQFP48 package top view example
3URGXFW
LGHQWLILFDWLRQ
45.
'$#5
'DWHFRGH
: 88
3LQ
LGHQWLILFDWLRQ
5HYLVLRQFRGH
3
06 9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
104/117
DocID13587 Rev 17
STM32F103x8, STM32F103xB
6.9
Package information
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 9: General operating conditions on page 38.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 62. Package thermal characteristics
Symbol
ΘJA
6.9.1
Parameter
Value
Thermal resistance junction-ambient
LFBGA100 - 10 × 10 mm / 0.8 mm pitch
44
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
UFBGA100 - 7 × 7 mm /0.5 mm pitch
59
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
TFBGA64 - 5 × 5 mm / 0.5 mm pitch
65
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
UFQFPN 48 - 7 × 7 mm / 0.5 mm pitch
32
Thermal resistance junction-ambient
VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch
18
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID13587 Rev 17
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Package information
6.9.2
STM32F103x8, STM32F103xB
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 63: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 62 TJmax is calculated as follows:
–
For LQFP100, 46 °C/W
TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 63: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
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DocID13587 Rev 17
STM32F103x8, STM32F103xB
Package information
Using the values obtained in Table 62 TJmax is calculated as follows:
–
For LQFP100, 46 °C/W
TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 63: Ordering information scheme).
Figure 65. LQFP100 PD max vs. TA
700
PD (mW)
600
500
Suffix 6
400
Suffix 7
300
200
100
0
65
75
85
95
105
115
125
135
TA (°C)
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Ordering information scheme
7
STM32F103x8, STM32F103xB
Ordering information scheme
Table 63. Ordering information scheme
Example:
STM32
F 103 C 8
T
7 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
I = UFBGA
T = LQFP
U = VFQFPN or UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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DocID13587 Rev 17
STM32F103x8, STM32F103xB
8
Revision history
Revision history
Table 64. Document revision history
Date
Revision
01-jun-2007
1
Initial release.
2
Flash memory size modified in Note 9, Note 5, Note 7, Note 7 and
BGA100 pins added to Table 5: Medium-density STM32F103xx pin
definitions. Figure 3: STM32F103xx performance line LFBGA100
ballout added.
THSE changed to TLSE in Figure 23: Low-speed external clock source
AC timing diagram. VBAT ranged modified in Power supply schemes.
tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator
characteristics. IDD(HSI) max value added to Table 24: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name
modified in Table 33: Electrical sensitivities. RPU and RPD min and max
values added to Table 35: I/O static characteristics. RPU min and max
values added to Table 38: NRST pin characteristics.
Figure 32: I2C bus AC waveforms and measurement circuit and
Figure 31: Recommended NRST pin protection corrected.
Notes removed below Table 9, Table 38, Table 44.
IDD typical values changed in Table 11: Maximum current consumption
in Run and Sleep modes. Table 39: TIMx characteristics modified.
tSTAB, VREF+ value, tlat and fTRIG added to Table 46: ADC
characteristics.
In Table : , typical endurance and data retention for TA = 85 °C added,
data retention for TA = 25 °C removed.
VBG changed to VREFINT in Table 12: Embedded internal reference
voltage. Document title changed. Controller area network (CAN)
section modified.
Figure 14: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
20-Jul-2007
Changes
DocID13587 Rev 17
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116
Revision history
STM32F103x8, STM32F103xB
Table 64. Document revision history (continued)
Date
18-Oct-2007
110/117
Revision
Changes
3
STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
numbers added (see Table 2: STM32F103xx medium-density device
features and peripheral counts)
VFQFPN36 package added (see Section 6: Package information). All
packages are ECOPACK® compliant. Package mechanical data inch
values are calculated from mm and rounded to 4 decimal digits (see
Section 6: Package information).
Table 5: Medium-density STM32F103xx pin definitions updated and
clarified.
Table 26: Low-power mode wakeup timings updated.
TA min corrected in Table 12: Embedded internal reference voltage.
Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics.
VESD(CDM) value added to Table 32: ESD absolute maximum ratings.
Note 4 added and VOH parameter description modified in Table 36:
Output voltage characteristics.
Note 1 modified under Table 37: I/O AC characteristics.
Equation 1 and Table 47: RAIN max for fADC = 14 MHz added to
Section 5.3.18: 12-bit ADC characteristics.
VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified
and tlatr added in Table 46: ADC characteristics.
Figure 37: ADC accuracy characteristics updated. Note 1 modified
below Figure 38: Typical connection diagram using the ADC.
Electrostatic discharge (ESD) on page 60 modified.
Number of TIM4 channels modified in Figure 1: STM32F103xx
performance line block diagram.
Maximum current consumption Table 13, Table 14 and Table 15
updated. Vhysmodified in Table 35: I/O static characteristics.
Table 49: ADC accuracy updated. VFESD value added in Table 30:
EMS characteristics.
Values corrected, note 2 modified and note 3 removed in Table 26:
Low-power mode wakeup timings.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2
modified, Note 2 added.
Table 21: Typical current consumption in Standby mode added. Onchip peripheral current consumption on page 50 added.
ACCHSI values updated in Table 24: HSI oscillator characteristics.
Vprog added to Table 28: Flash memory characteristics.
Upper option byte address modified in Figure 11: Memory map.
Typical fLSI value added in Table 25: LSI oscillator characteristics and
internal RC value corrected from 32 to 40 kHz in entire document.
TS_temp added to Table 50: TS characteristics. NEND modified in
Table : .
TS_vrefint added to Table 12: Embedded internal reference voltage.
Handling of unused pins specified in General input/output
characteristics on page 62. All I/Os are CMOS and TTL compliant.
Figure 39: Power supply and reference decoupling (VREF+ not
connected to VDDA) modified.
tJITTER and fVCO removed from Table 27: PLL characteristics.
Appendix A: Important notes on page 81 added.
Added Figure 16, Figure 17, Figure 19 and Figure 21.
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Revision history
Table 64. Document revision history (continued)
Date
22-Nov-2007
Revision
Changes
4
Document status promoted from preliminary data to datasheet.
The STM32F103xx is USB certified. Small text changes.
Power supply schemes on page 15 modified. Number of
communication peripherals corrected for STM32F103Tx and number of
GPIOs corrected for LQFP package in Table 2: STM32F103xx
medium-density device features and peripheral counts.
Main function and default alternate function modified for PC14 and
PC15 in, Note 6 added and Remap column added in Table 5: Mediumdensity STM32F103xx pin definitions.
VDD–VSS ratings and Note 1 modified in Table 6: Voltage
characteristics, Note 1 modified in Table 7: Current characteristics.
Note 1 and Note 2 added in Table 11: Embedded reset and power
control block characteristics.
IDD value at 72 MHz with peripherals enabled modified in Table 14:
Maximum current consumption in Run mode, code with data
processing running from RAM.
IDD value at 72 MHz with peripherals enabled modified in Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM on page 44.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values
added in Table 16: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 17 on page 48 and Table 18
on page 49. ADC1 and ADC2 consumption and notes modified in
Table 19: Peripheral current consumption.
tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23,
respectively.
Maximum values removed from Table 26: Low-power mode wakeup
timings. tRET conditions modified in Table : . Figure 14: Power supply
scheme corrected.
Figure 20: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 33: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 34: SPI timing diagram - slave
mode and CPHA = 1(1).
Details on unused pins removed from General input/output
characteristics on page 62.
Table 42: SPI characteristics updated. Table 43: USB startup time
added. VAIN, tlat and tlatr modified, note added and Ilkg removed in
Table 46: ADC characteristics. Test conditions modified and note
added in Table 49: ADC accuracy. Note added below Table 47 and
Table 50.
Inch values corrected in Table 55: LQPF100, 14 x 14 mm 100-pin lowprofile quad flat package mechanical data, Table 58: LQFP64 - 64-pin,
10 x 10 mm low-profile quad flat package mechanical data and
Table 60: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package
mechanical data.
ΘJAvalue for VFQFPN36 package added in Table 62: Package thermal
characteristics.
Order codes replaced by Section 7: Ordering information scheme.
MCU ‘s operating conditions modified in Typical current consumption
on page 47. Avg_Slope and V25 modified in Table 50: TS
characteristics. I2C interface characteristics on page 69 modified.
Impedance specified in A.4: Voltage glitch on ADC input 0 on page 81.
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Revision history
STM32F103x8, STM32F103xB
Table 64. Document revision history (continued)
Date
14-Mar-2008
21-Mar-2008
22-May-2008
112/117
Revision
Changes
5
Figure 2: Clock tree on page 12 added.
Maximum TJ value given in Table 8: Thermal characteristics on
page 38.
CRC feature added (see CRC (cyclic redundancy check) calculation
unit on page 9 and Figure 11: Memory map on page 34 for address).
IDD modified in Table 16: Typical and maximum current consumptions
in Stop and Standby modes.
ACCHSI modified in Table 24: HSI oscillator characteristics on page 56,
note 2 removed.
PD, TA and TJ added, tprog values modified and tprog description
clarified in Table 28: Flash memory characteristics on page 57.
tRET modified in Table : .
VNF(NRST) unit corrected in Table 38: NRST pin characteristics on
page 67.
Table 42: SPI characteristics on page 71 modified.
IVREF added to Table 46: ADC characteristics on page 75.
Table 48: ADC accuracy - limited test conditions added. Table 49: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
information on page 80).
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see Figure 55, Figure 60, Figure 64 and Figure 44).
Section 6.9: Thermal characteristics on page 105 modified,
Section 6.9.1 and Section 6.9.2 added.
Appendix A: Important notes on page 81 removed.
6
Small text changes. Figure 11: Memory map clarified.
In Table : :
– NEND tested over the whole temperature range
– cycling conditions specified for tRET
– tRET min modified at TA = 55 °C
V25, Avg_Slope and TL modified in Table 50: TS characteristics.
CRC feature removed.
7
CRC feature added back. Small text changes. Section 1: Introduction
modified. Section 2.2: Full compatibility throughout the family added.
IDD at TA max = 105 °C added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes on page 45.
IDD_VBAT removed from Table 21: Typical current consumption in
Standby mode on page 47.
Values added to Table 41: SCL frequency (fPCLK1= 36
MHz.,VDD_I2C = 3.3 V) on page 70.
Figure 33: SPI timing diagram - slave mode and CPHA = 0 on page 72
modified. Equation 1 corrected.
tRET at TA = 105 °C modified in Table : on page 58.
VUSB added to Table 44: USB DC electrical characteristics on page 74.
Figure 65: LQFP100 PD max vs. TA on page 107 modified.
Axx option added to Table 63: Ordering information scheme on
page 108.
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Revision history
Table 64. Document revision history (continued)
Date
21-Jul-2008
22-Sep-2008
Revision
Changes
8
Power supply supervisor updated and VDDA added to Table 9: General
operating conditions.
Capacitance modified in Figure 14: Power supply scheme on page 36.
Table notes revised in Section 5: Electrical characteristics.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes modified.
Data added to Table 16: Typical and maximum current consumptions in
Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
fHSE_ext modified in Table 20: High-speed external user clock
characteristics on page 51. fPLL_IN modified in Table 27: PLL
characteristics on page 57.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 40: I2C characteristics on page 69, note 1 modified.
th(NSS) modified in Table 42: SPI characteristics on page 71 and
Figure 33: SPI timing diagram - slave mode and CPHA = 0 on page 72.
CADC modified in Table 46: ADC characteristics on page 75 and
Figure 38: Typical connection diagram using the ADC modified.
Typical TS_temp value removed from Table 50: TS characteristics on
page 79.
LQFP48 package specifications updated (see Table 60 and Table 64),
Section 6: Package information revised.
Axx option removed from Table 63: Ordering information scheme on
page 108.
Small text changes.
9
STM32F103x6 part numbers removed (see Table 63: Ordering
information scheme). Small text changes.
General-purpose timers (TIMx) and Advanced-control timer (TIM1) on
page 18 updated.
Notes updated in Table 5: Medium-density STM32F103xx pin
definitions on page 28.
Note 2 modified below Table 6: Voltage characteristics on page 37,
|ΔVDDx| min and |ΔVDDx| min removed.
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 41.
IDD in standby mode at 85 °C modified in Table 16: Typical and
maximum current consumptions in Stop and Standby modes on
page 45.
General input/output characteristics on page 62 modified.
fHCLK conditions modified in Table 30: EMS characteristics on page 59.
ΘJA and pitch value modified for LFBGA100 package in Table 62:
Package thermal characteristics. Small text changes.
DocID13587 Rev 17
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116
Revision history
STM32F103x8, STM32F103xB
Table 64. Document revision history (continued)
Date
23-Apr-2009
22-Sep-2009
03-Jun-2010
114/117
Revision
Changes
10
I/O information clarified on page 1.
Figure 3: STM32F103xx performance line LFBGA100 ballout modified.
Figure 11: Memory map modified. Table 4: Timer feature comparison
added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column in Table 5: Medium-density STM32F103xx
pin definitions.
PD for LFBGA100 corrected in Table 9: General operating conditions.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
Figure 20 shows a typical curve (title modified). ACCHSI max values
modified in Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Table 59 and Table 60). Small text
changes.
11
Note 5 updated and Note 4 added in Table 5: Medium-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 12: Embedded internal reference
voltage. IDD_VBAT value added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes. Figure 18: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables. Table 24:
HSI oscillator characteristics modified. Conditions removed from
Table 26: Low-power mode wakeup timings.
Note 1 modified below Figure 24: Typical application with an 8 MHz
crystal.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 58.
Jitter added to Table 27: PLL characteristics.
Table 42: SPI characteristics modified.
CADC and RAIN parameters modified in Table 46: ADC characteristics.
RAIN max values modified in Table 47: RAIN max for fADC = 14 MHz.
Figure 47: LFBGA100 - 100-ball low-profile fine pitch ball grid array, 10
x10 mm, 0.8 mm pitch, package outline updated.
12
Added STM32F103TB devices.
Added VFQFPN48 package.
Updated note 2 below Table 40: I2C characteristics
Updated Figure 32: I2C bus AC waveforms and measurement circuit
Updated Figure 31: Recommended NRST pin protection
Updated Section 5.3.12: I/O current injection characteristics
DocID13587 Rev 17
STM32F103x8, STM32F103xB
Revision history
Table 64. Document revision history (continued)
Date
Revision
Changes
19-Apr-2011
13
Updated footnotes below Table 6: Voltage characteristics on page 37
and Table 7: Current characteristics on page 37
Updated tw min in Table 20: High-speed external user clock
characteristics on page 51
Updated startup time in Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz) on page 54
Added Section 5.3.12: I/O current injection characteristics
Updated Section 5.3.13: I/O port characteristics
07-Dec-2012
14
Added UFBGA100 7 x 7 mm.
Updated Figure 59: LQFP64, 10 x 10 mm, 64-pin low-profile quad flat
package outline to add pin 1 identification.
15
Replaced VQFN48 package with UQFN48 in cover page packages,
Table 2: STM32F103xx medium-density device features and peripheral
counts, Figure 9: STM32F103xx performance line UFQFPN48 pinout,
Table 2: STM32F103xx medium-density device features and peripheral
counts, Table 56: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra
fine pitch ball grid array package mechanical data, Table 63: Ordering
information scheme and updated Table 62: Package thermal
characteristics
Added footnote for TFBGA ADC channels in Table 2: STM32F103xx
medium-density device features and peripheral counts
Updated ‘All GPIOs are high current...’ in Section 2.3.21: GPIOs
(general-purpose inputs/outputs)
Updated Table 5: Medium-density STM32F103xx pin definitions
Corrected Sigma letter in Section 5.1.1: Minimum and maximum values
Removed the first sentence in Section 5.3.16: Communications
interfaces
Added ‘VIN’ in Table 9: General operating conditions
Updated first sentence in Output driving current
Added note 5. in Table 24: HSI oscillator characteristics
Updated ‘VIL’ and ‘VIH’ in Table 35: I/O static characteristics
Added notes to Figure 26: Standard I/O input characteristics - CMOS
port, Figure 27: Standard I/O input characteristics - TTL port, Figure 28:
5 V tolerant I/O input characteristics - CMOS port and Figure 29: 5 V
tolerant I/O input characteristics - TTL port
Updated Figure 32: I2C bus AC waveforms and measurement circuit
Updated note 2. and 3.,removed note “the device must internally...” in
Table 40: I2C characteristics
Updated title of Table 41: SCL frequency (fPCLK1= 36 MHz.,VDD_I2C
= 3.3 V)
Updated note 2. in Table 49: ADC accuracy
14-May-2013
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Revision history
STM32F103x8, STM32F103xB
Table 64. Document revision history (continued)
Date
Revision
Changes
Updated Figure 53: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch,
ultra fine pitch ball grid array package outline and Table 56: UFBGA100
- 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
Updated Figure 47: LFBGA100 - 100-ball low-profile fine pitch ball grid
15
14-May-2013
array, 10 x10 mm, 0.8 mm pitch, package outline and Table 53:
(continued)
LFBGA100 – 100-ball low-profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package mechanical data
Updated Figure 60: TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5
mm pitch, package outline and Table 59: TFBGA64 - 8 x 8 active ball
array, 5 x 5 mm, 0.5 mm pitch, package mechanical data
05-Aug-2013
21-Aug-2015
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16
Updated the reference for ‘VESD(CDM)’ in Table 32: ESD absolute
maximum ratings
Corrected ‘tf(IO)out’ in Figure 30: I/O AC characteristics definition
Updated Table 52: UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra
thin fine pitch quad flat package mechanical data
17
Updated Table 3: STM32F103xx family removing the note.
Updated Table 63: Ordering information scheme removing the note.
Updated Section 6: Package information and added Section : Marking
of engineering samples for all packages.
Updated I2C characteristics, added tSP parameter and note 4 in
Table 40: I2C characteristics.
Updated Figure 32: I2C bus AC waveforms and measurement circuit
swapping SCLL and SCLH.
Updated Figure 33: SPI timing diagram - slave mode and CPHA = 0.
Updated min/max value notes replacing ‘Guaranteed by design, not
tested in production” by “guaranteed by design”.
Updated min/max value notes replacing ‘based on characterization, not
tested in production” by “Guaranteed based on test during
characterization”.
Updated Table 19: Peripheral current consumption.
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