STM32F103VBT6

STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration ■ Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers ■ 2 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor ■ ■ DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs Up to 80 fast I/O ports – 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant April 2009 LQFP48 7 × 7 m LQFP100 14 × 14 m LQFP64 10 × 10 m VFQFPN36 6 × 6 mm BGA100 10 × 10 mm BGA64 5 × 5 mm ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces ■ 7 timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with deadtime generation and emergency stop – 2 watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter ■ Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface ■ CRC calculation unit, 96-bit unique ID ■ Packages are ECOPACK® Table 1. Device summary Reference Part number STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB Doc ID 13587 Rev 10 1/91 www.st.com 1 Contents STM32F103x8, STM32F103xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . 12 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 17 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 6 7 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 36 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 55 5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 82 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Doc ID 13587 Rev 10 3/91 Contents 8 4/91 STM32F103x8, STM32F103xB Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 41 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 42 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Doc ID 13587 Rev 10 5/91 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/91 STM32F103x8, STM32F103xB ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 73 LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 74 LQPF100, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . 76 LQFP64, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 78 LQFP48, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 80 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F103xx Performance Line VFQFPN36 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 40 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 70 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 71 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 74 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 75 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LQFP64, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 78 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 79 Doc ID 13587 Rev 10 7/91 List of figures Figure 44. Figure 45. Figure 46. 8/91 STM32F103x8, STM32F103xB LQFP48, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F103x8 and STM32F103xB performance line family incorporates the highperformance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx medium-density performance line family operates from a 2.0 to 3.6 V power supply. It is available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications: ● Motor drive and application control ● Medical and handheld equipment ● PC peripherals gaming and GPS platforms ● Industrial applications: PLC, inverters, printers, and scanners ● Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. Doc ID 13587 Rev 10 9/91 Description 2.1 STM32F103x8, STM32F103xB Device overview Table 2. STM32F103xx medium-density device features and peripheral counts Peripheral STM32F103Tx STM32F103Cx 64 128 SRAM - Kbytes 20 20 20 20 20 General-purpose 3 3 3 3 3 Advanced-control 1 1 1 SPI 1 2 2 2 2 I2C 1 2 2 2 2 USART 2 3 3 3 3 USB 1 1 1 1 1 CAN 1 1 1 1 1 Communication Timers 64 12-bit synchronized ADC Number of channels 1 64 128 37 51 80 2 10 channels 2 10 channels 2 16 channels 2 16 channels 72 MHz Operating voltage Packages 128 26 CPU frequency Operating temperatures 64 STM32F103Vx Flash - Kbytes GPIOs 10/91 STM32F103Rx 2.0 to 3.6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9) Junction temperature: –40 to + 125 °C (see Table 9) VFQFPN36 LQFP48 Doc ID 13587 Rev 10 LQFP64, TFBGA64 LQFP100, LFBGA100 STM32F103x8, STM32F103xB 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, CAN, 1 × PWM timer 2 × ADC 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 1 × DAC, 1 × SDIO FSMC (100 and 144 pins) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. Doc ID 13587 Rev 10 11/91 Description STM32F103x8, STM32F103xB 2.3 Overview 2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. 12/91 ● Closely coupled NVIC gives low-latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving higher priority interrupts ● Support for tail-chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from User Flash ● Boot from System Memory ● Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.3.9 Power supply schemes ● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. ● VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. ● VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains Doc ID 13587 Rev 10 13/91 Description STM32F103x8, STM32F103xB in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop mode ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: 14/91 The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 2.3.13 Description DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Timers and watchdogs The medium-density STM32F103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It Doc ID 13587 Rev 10 15/91 Description STM32F103x8, STM32F103xB can also be seen as a complete general-purpose timer. The 4 independent channels can be used for ● Input capture ● Output compare ● PWM generation (edge- or center-aligned modes) ● One-pulse mode output If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 16/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Description SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: 2.3.16 ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 2.3.18 Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 2.3.19 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 2.3.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). Doc ID 13587 Rev 10 17/91 Description 2.3.21 STM32F103x8, STM32F103xB GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● Simultaneous sample and hold ● Interleaved sample and hold ● Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 18/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB STM32F103xx performance line block diagram TPIU SW/JTAG Ibus Cortex-M3 CPU Fmax : 7 2M Hz Trace Controlle r pbu s Trace/trig Dbus Syst em NVIC AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int PCLK1 PCLK2 HCLK FCLK AHB2 APB2 @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz GPIOA GPIOB PC[15:0] GPIOC PD[15:0] GPIOD PE[15:0] GPIOE 4 Chann els 3 co mpl. Chann els ETR and BKIN TIM1 MOSI,MISO, SCK,NSS as AF SPI1 IWDG Stand by in terface @VDDA AHB2 APB 1 RTC AWU Back up reg 12bi t ADC2 IF TAMPER-RTC TIM2 4 Chann els TIM3 4 Chann els TIM 4 4 Chann els USART2 RX,TX, CTS, RTS, CK, SmartCard as AF USART3 RX,TX, CTS, RTS, CK, SmartCard as AF 2x(8x16bit)SPI2 MOSI,MISO,SCK,NSS as AF I2C1 SCL,SDA,SMBA as AF I2C2 SCL,SDA as AF bx CAN USB 2.0 FS VREF- OSC32_IN OSC32_OUT Backu p i nterf ace USART1 12bit ADC1 IF VBAT @VBAT @VDDA 16AF VREF+ OSC_IN OSC_OUT RC 8 MHz RC 40 kHz EXTI WAKEUP PA[ 15:0] VDD = 2 to 3.6V VSS @VDD 64 bit XTAL 32 kHz PB[ 15:0] RX,TX, CTS, RTS, Smart Card as AF Flash 128 KB APB2 : F max =48 / 72 MHz 80AF POR / PDR VOLT. REG. 3.3V TO 1.8V SRAM 20 KB GP DMA 7 ch annels POWER APB1 : Fmax =24 / 36 MHz NJTRST TRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF flash obl Inte rfac e TRACECLK TRACED[0:3] as AS BusM atrix Figure 1. Description USBDP/CAN_TX USBDM/CAN_RX SRAM 512B WWDG Temp sensor ai14390d 1. TA = –40 °C to +105 °C (junction temperature up to 125 °C). 2. AF = alternate function on I/O port pin. Doc ID 13587 Rev 10 19/91 Description STM32F103x8, STM32F103xB Figure 2. Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..512 max PLLCLK Clock Enable (3 bits) APB1 Prescaler /1, 2, 4, 8, 16 HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (13 bits) to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock CSS Enable (3 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz 72 MHz max HSE OSC /2 TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals to RTC LSE RTCCLK ADC Prescaler /2, 4, 6, 8 Enable (1 bit) to ADC ADCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK HSI Legend: HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal HSE SYSCLK MCO ai14903 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. 20/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Pinouts and pin description 3 Pinouts and pin description Figure 3. STM32F103xx performance line LFBGA100 ballout 1 A 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 9 10 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI16001c Doc ID 13587 Rev 10 21/91 Pinouts and pin description STM32F103xx performance line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4. STM32F103x8, STM32F103xB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14391 22/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 STM32F103xx performance line LQFP64 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 Figure 5. Pinouts and pin description ai14392 Doc ID 13587 Rev 10 23/91 Pinouts and pin description Figure 6. STM32F103x8, STM32F103xB STM32F103xx performance line TFBGA64 ballout 1 A 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12 C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 24/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB STM32F103xx performance line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 7. Pinouts and pin description 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 ai14393b PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 VSS_3 STM32F103xx Performance Line VFQFPN36 pinout 35 34 33 32 31 30 29 28 VDD_3 1 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 23 PA11 VSSA 5 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 10 11 12 13 14 15 PA4 PA5 PA6 PA7 PB0 QFN36 PA3 19 18 VDD_1 VSS_1 17 PB2 16 PB1 Figure 8. ai14654 Doc ID 13587 Rev 10 25/91 Pinouts and pin description Medium-density STM32F103xx pin definitions Alternate functions LQFP100 VFQFPN36 A3 - - 1 - PE2 I/O FT PE2 TRACECK B3 - - 2 - PE3 I/O FT PE3 TRACED0 C3 - - 3 - PE4 I/O FT PE4 TRACED1 D3 - - 4 - PE5 I/O FT PE5 TRACED2 E3 - - 5 - PE6 I/O FT PE6 TRACED3 B2 1 B2 1 6 - VBAT S VBAT A2 2 A2 2 7 - PC13-TAMPERRTC(4) I/O PC13(5) TAMPER-RTC A1 3 A1 3 8 - PC14-OSC32_IN(4) I/O PC14(5) OSC32_IN B1 4 B1 4 9 - PC15OSC32_OUT(4) I/O PC15(5) OSC32_OUT C2 - - - 10 - VSS_5 S VSS_5 D2 - - - 11 - VDD_5 S VDD_5 C1 5 C1 5 12 2 OSC_IN I OSC_IN D1 6 D1 6 13 3 OSC_OUT O OSC_OUT E1 7 E1 7 14 4 NRST I/O NRST F1 - E3 8 15 - PC0 I/O PC0 ADC12_IN10 F2 - E2 9 16 - PC1 I/O PC1 ADC12_IN11 E2 - F2 10 17 - PC2 I/O PC2 ADC12_IN12 F3 - -(6) 11 18 - PC3 I/O PC3 ADC12_IN13 G1 8 F1 12 19 5 VSSA S VSSA H1 - - - 20 - VREF- S VREF- - 21 - VREF+ S VREF+ 13 22 6 VDDA S VDDA J1 - K1 9 G2 10 TFBGA64 LQFP64 Default LQFP48 Main function(3) (after reset) LFBGA100 Type(1) Pins I / O Level(2) Table 5. STM32F103x8, STM32F103xB (6) G1 H1 G2 14 23 7 Pin name PA0-WKUP I/O PA0 WKUP/ USART2_CTS(7)/ ADC12_IN0/ TIM2_CH1_ETR(7) H2 11 H2 15 24 8 PA1 I/O PA1 USART2_RTS(7)/ ADC12_IN1/ TIM2_CH2(7) J2 12 F3 16 25 9 PA2 I/O PA2 USART2_TX(7)/ ADC12_IN2/ TIM2_CH3(7) 26/91 Doc ID 13587 Rev 10 Remap STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) Alternate functions LQFP48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Main function(3) (after reset) LFBGA100 Type(1) Pins I / O Level(2) Table 5. Pinouts and pin description K2 13 G3 17 26 10 PA3 I/O PA3 E4 - C2 18 27 - VSS_4 S VSS_4 F4 - D2 19 28 - VDD_4 S VDD_4 G3 14 H3 20 29 11 PA4 I/O PA4 SPI1_NSS(7)/ USART2_CK(7)/ ADC12_IN4 H3 15 F4 21 30 12 PA5 I/O PA5 SPI1_SCK(7)/ ADC12_IN5 J3 16 G4 22 31 13 PA6 I/O PA6 SPI1_MISO(7)/ ADC12_IN6/ TIM3_CH1(7) TIM1_BKIN TIM1_CH1N Pin name Default Remap USART2_RX(7)/ ADC12_IN3/ TIM2_CH4(7) PA7 I/O PA7 SPI1_MOSI(7)/ ADC12_IN7/ TIM3_CH2(7) 33 PC4 I/O PC4 ADC12_IN14 25 34 PC5 I/O PC5 ADC12_IN15 F5 26 35 15 PB0 I/O PB0 ADC12_IN8/ TIM3_CH3(7) TIM1_CH2N 19 G5 27 36 16 PB1 I/O PB1 ADC12_IN9/ TIM3_CH4(7) TIM1_CH3N G5 20 G6 28 37 17 PB2 I/O FT PB2/BOOT1 H5 - - - 38 - PE7 I/O FT PE7 TIM1_ETR J5 - - - 39 - PE8 I/O FT PE8 TIM1_CH1N K5 - - - 40 - PE9 I/O FT PE9 TIM1_CH1 G6 - - - 41 - PE10 I/O FT PE10 TIM1_CH2N H6 - - - 42 - PE11 I/O FT PE11 TIM1_CH2 J6 - - - 43 - PE12 I/O FT PE12 TIM1_CH3N K6 - - - 44 - PE13 I/O FT PE13 TIM1_CH3 G7 - - - 45 - PE14 I/O FT PE14 TIM1_CH4 H7 - - - 46 - PE15 I/O FT PE15 TIM1_BKIN J7 21 G7 29 47 - PB10 I/O FT PB10 I2C2_SCL/ USART3_TX(7) TIM2_CH3 K7 22 H7 30 48 - PB11 I/O FT PB11 I2C2_SDA/ USART3_RX(7) TIM2_CH4 E7 23 D6 31 49 18 VSS_1 K3 17 H4 23 32 G4 - H5 24 H4 - H6 J4 18 K4 14 S VSS_1 Doc ID 13587 Rev 10 27/91 Pinouts and pin description Medium-density STM32F103xx pin definitions (continued) LQFP48 TFBGA64 LQFP64 LQFP100 VFQFPN36 F7 24 E6 32 50 19 Pin name VDD_1 Type(1) LFBGA100 Pins I / O Level(2) Table 5. STM32F103x8, STM32F103xB S Alternate functions Main function(3) (after reset) Default Remap VDD_1 K8 25 H8 33 51 - PB12 I/O FT PB12 SPI2_NSS/ I2C2_SMBAl/ USART3_CK(7)/ TIM1_BKIN(7) J8 26 G8 34 52 - PB13 I/O FT PB13 SPI2_SCK/ USART3_CTS(7)/ TIM1_CH1N (7) H8 27 F8 35 53 - PB14 I/O FT PB14 SPI2_MISO/ USART3_RTS(7) TIM1_CH2N (7) G8 28 F7 36 54 - PB15 I/O FT PB15 SPI2_MOSI/ TIM1_CH3N(7) K9 - - - 55 - PD8 I/O FT PD8 USART3_TX J9 - - - 56 - PD9 I/O FT PD9 USART3_RX H9 - - - 57 - PD10 I/O FT PD10 USART3_CK G9 - - - 58 - PD11 I/O FT PD11 USART3_CTS K10 - - - 59 - PD12 I/O FT PD12 TIM4_CH1 / USART3_RTS J10 - - - 60 - PD13 I/O FT PD13 TIM4_CH2 H10 - - - 61 - PD14 I/O FT PD14 TIM4_CH3 G10 - - - 62 - PD15 I/O FT PD15 TIM4_CH4 F10 - F6 37 63 - PC6 I/O FT PC6 TIM3_CH1 E10 E7 38 64 - PC7 I/O FT PC7 TIM3_CH2 F9 E8 39 65 - PC8 I/O FT PC8 TIM3_CH3 TIM3_CH4 E9 - D8 40 66 - PC9 I/O FT PC9 D9 29 D7 41 67 20 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1(7)/MCO C9 30 C7 42 68 21 PA9 I/O FT PA9 USART1_TX(7)/ TIM1_CH2(7) D10 31 C6 43 69 22 PA10 I/O FT PA10 USART1_RX(7)/ TIM1_CH3(7) C10 32 C8 44 70 23 PA11 I/O FT PA11 USART1_CTS/ CANRX(7)/ USBDM TIM1_CH4(7) B10 33 B8 45 71 24 PA12 I/O FT PA12 USART1_RTS/ CANTX(7) //USBDP TIM1_ETR(7) 28/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) LQFP64 LQFP100 VFQFPN36 A8 46 72 25 Pin name PA13 Type(1) TFBGA64 A10 34 LFBGA100 LQFP48 Pins I / O Level(2) Table 5. Pinouts and pin description Alternate functions Main function(3) (after reset) Default I/O FT JTMS/SWDIO Remap PA13 F8 - - - 73 - Not connected E6 35 D5 47 74 26 VSS_2 S VSS_2 F6 36 E5 48 75 27 VDD_2 S VDD_2 A9 37 A7 49 76 28 PA14 I/O FT JTCK/SWCLK A8 38 A6 50 77 29 PA15 I/O FT JTDI TIM2_CH1_ETR/ PA15 /SPI1_NSS B9 - B7 51 78 PC10 I/O FT PC10 USART3_TX B8 - B6 52 79 PC11 I/O FT PC11 USART3_RX C8 - C5 53 80 PC12 I/O FT PC12 USART3_CK OSC_IN(8) CANRX D8 5 C1 5 81 2 PD0 I/O FT E8 6 D1 6 82 3 PD1 I/O FT OSC_OUT(8) B5 54 83 - PD2 I/O FT PD2 B7 PA14 CANTX TIM3_ETR C7 - - - 84 - PD3 I/O FT PD3 USART2_CTS D7 - - - 85 - PD4 I/O FT PD4 USART2_RTS B6 - - - 86 - PD5 I/O FT PD5 USART2_TX C6 - - - 87 - PD6 I/O FT PD6 USART2_RX D6 - - - 88 - PD7 I/O FT PD7 USART2_CK A7 39 A5 55 89 30 PB3 I/O FT JTDO TIM2_CH2 / PB3 TRACESWO SPI1_SCK A6 40 A4 56 90 31 PB4 I/O FT JNTRST TIM3_CH1/ PB4/ SPI1_MISO C5 41 C4 57 91 32 PB5 I/O PB5 I2C1_SMBAl TIM3_CH2 / SPI1_MOSI B5 42 D3 58 92 33 PB6 I/O FT PB6 I2C1_SCL(7)/ TIM4_CH1(7) USART1_TX A5 43 C3 59 93 34 PB7 I/O FT PB7 I2C1_SDA(7)/ TIM4_CH2(7) USART1_RX D5 44 B4 60 94 35 BOOT0 B4 45 B3 61 95 - PB8 I/O FT PB8 TIM4_CH3(7) I2C1_SCL / CANRX A4 46 A3 62 96 - PB9 I/O FT PB9 TIM4_CH4(7) I2C1_SDA/ CANTX I BOOT0 Doc ID 13587 Rev 10 29/91 Pinouts and pin description Medium-density STM32F103xx pin definitions (continued) Alternate functions LQFP64 LQFP100 VFQFPN36 TIM4_ETR TFBGA64 Default LQFP48 Main function(3) (after reset) LFBGA100 Type(1) Pins I / O Level(2) Table 5. STM32F103x8, STM32F103xB D4 - - - 97 - PE0 I/O FT PE0 C4 - - - 98 - PE1 I/O FT PE1 E5 47 D4 63 99 36 VSS_3 S VSS_3 F5 48 E4 64 100 1 VDD_3 S VDD_3 Pin name Remap 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 10. 4. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 30/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 4 Memory mapping Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map APB memory space 0xFFFF FFFF reserved 0xE010 0000 reserved 0xFFFF FFFF 0x6000 0000 reserved 0x4002 3400 CRC 7 0xE010 0000 0xE000 0000 0x4002 3000 reserved 0x4002 2400 Cortex- M3 Internal Peripherals Flash Interface 0x4002 2000 reserved 0x4002 1400 0x4002 1000 RCC reserved 6 0x4002 0400 DMA 0x4002 0000 reserved 0xC000 0000 0x4001 3C00 0x4001 3800 0x4001 3400 5 USART1 reserved SPI1 0x4001 3000 TIM1 0x4001 2C00 ADC2 0xA000 0000 0x4001 2800 ADC1 0x4001 2400 rese rve d 4 0x4001 1C00 0x1FFF FFFF rese rved 0x1FFF F80F Por t E 0x4001 1800 Port D 0x8000 0000 Option Bytes 0x1FFF F800 0x4001 1400 Port C 0x4001 1000 Port B 0x4001 0C00 3 System memory Port A 0x4001 0800 EXTI 0x4001 0400 AFIO 0x1FFF F000 0x6000 0000 0x4001 0000 reserved 0x4000 7400 PWR 0x4000 7000 2 BKP 0x4000 6C00 rese rved 0x4000 0000 Peripherals reserved 0x4000 6800 0x4000 6400 0x4000 6000 bxCAN shared 512 byte USB/CAN SRAM USB Reg isters 0x4000 5C00 1 I2C2 0x4000 5800 I2C1 0x2000 0000 0x4000 5400 SRAM reserved 0x4000 4C00 0x0801 FFFF USART3 0x4000 4800 USART2 0 0x4000 4400 Flash memory reserved 0x4000 3C00 SPI2 0x0800 0000 0x0000 0000 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 0x4000 3800 reserved 0x4000 3400 IWDG 0x4000 3000 WWDG 0x4000 2C00 RTC 0x4000 2800 reserved Reserved 0x4000 0C00 TIM4 0x4000 0800 0x4000 0400 0x4000 0000 TIM3 TIM2 ai14394f Doc ID 13587 Rev 10 31/91 Electrical characteristics STM32F103x8, STM32F103xB 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V  VDD  3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. 32/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics Figure 10. Pin loading conditions Figure 11. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 12. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.7 µF VDD 1/2/3/4/5 VDDA VREF 10 nF + 1 µF Regulator VSS 10 nF + 1 µF VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA ai14125d Caution: In Figure 12, the 4.7 µF capacitor must be connected to VDD3. Doc ID 13587 Rev 10 33/91 Electrical characteristics 5.1.7 STM32F103x8, STM32F103xB Current consumption measurement Figure 13. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD–VSS VIN |VDDx| |VSSX VSS| VESD(HBM) Voltage characteristics Ratings Min Max –0.3 4.0 Input voltage on five volt tolerant pin(2) VSS  0.3 +5.5 Input voltage on any other pin(2) VSS 0.3 VDD+0.3 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS. 34/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 7. Electrical characteristics Current characteristics Symbol Ratings Max. Total current into VDD/VDDA power lines (source)(1) IVDD Total current out of VSS ground lines (sink) IVSS 150 (1) 150 Output current sunk by any I/O and control pin IIO Unit 25 Output current source by any I/Os and control pin  25 Injected current on NRST pin ±5 mA IINJ(PIN) (2)(3) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin IINJ(PIN)(2) ±5 (4) ±5 Total injected current (sum of all I/O and control pins)(4) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 8. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 9. Symbol Value Unit –65 to +150 °C 150 °C General operating conditions Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.8 3.6 VDD VDDA(1) VBAT Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Must be the same potential as VDD(2) Backup operating voltage Doc ID 13587 Rev 10 Unit MHz V V V 35/91 Electrical characteristics Table 9. Symbol PD STM32F103x8, STM32F103xB General operating conditions (continued) Parameter Conditions Min Max LFBGA100 454 LQFP100 434 Power dissipation at TA = 85 °C TFBGA64 for suffix 6 or TA = 105 °C for LQFP64 suffix 7(3) 308 Unit mW 444 LQFP48 363 VFQFPN36 1110 Ambient temperature for 6 suffix version Maximum power dissipation –40 85 Low power dissipation –40 105 Ambient temperature for 7 suffix version Maximum power dissipation –40 105 Low power dissipation(4) –40 125 6 suffix version –40 105 7 suffix version –40 125 (4) °C TA TJ °C Junction temperature range °C 1. When the ADC is used, refer to Table 45: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 81). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Symbol tVDD 5.3.3 Operating conditions at power-up / power-down Parameter Conditions Min VDD rise time rate 0 VDD fall time rate 20 Max Unit   µs/V Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 36/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 11. Embedded reset and power control block characteristics Symbol Parameter Programmable voltage detector level selection VPVD VPVDhyst Electrical characteristics (2) VPOR/PDR VPDRhyst (2) Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V PVD hysteresis 100 Power on/power down reset threshold mV Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis 40 TRSTTEMPO(2) Reset temporization 1 2.5 mV 4.5 ms 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 13587 Rev 10 37/91 Electrical characteristics 5.3.4 STM32F103x8, STM32F103xB Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.1(2) µs ADC sampling time when TS_vrefint(1) reading the internal reference voltage 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except when explicitly mentioned ● The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) ● Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 38/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 13. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 °C 72 MHz 50 50.3 48 MHz 36.1 36.2 36 MHz 28.6 28.7 24 MHz 19.9 20.1 16 MHz 14.7 14.9 8 MHz 8.6 8.9 72 MHz 32.8 32.9 48 MHz 24.4 24.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 19.8 19.9 13.9 14.2 16 MHz 10.7 11 8 MHz 6.8 7.1 External clock(2), all peripherals enabled IDD Unit TA = 85 °C Supply current in Run mode mA 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Run mode fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 48 50 48 MHz 31.5 32 36 MHz 24 25.5 24 MHz 17.5 18 16 MHz 12.5 13 8 MHz 7.5 8 72 MHz 29 29.5 48 MHz 20.5 21 External clock(2), all 36 MHz peripherals disabled 24 MHz 16 16.5 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 mA 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 10 39/91 Electrical characteristics STM32F103x8, STM32F103xB Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 36 MHz 16 MHz 8 MHz 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (°C) Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 30 Consumption (mA) 25 20 72 MHz 36 MHz 16 MHz 8 MHz 15 10 5 0 -40 0 25 70 Temperature (°C) 40/91 Doc ID 13587 Rev 10 85 105 STM32F103x8, STM32F103xB Table 15. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 30 32 48 MHz 20 20.5 36 MHz 15.5 16 24 MHz 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.5 8 MHz 3 4 mA 1. based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 10 41/91 Electrical characteristics Table 16. STM32F103x8, STM32F103xB Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no Supply current in independent watchdog) Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) IDD TA = Unit VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.3 V 85 °C 105 °C 23.5 24 200 370 13.5 14 180 340 2.6 3.4 - - 2.4 3.2 - - 1.7 2 4 5 1.1 1.4 1.9(2) 2.2 Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator ON, Supply current in independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Backup domain supply current Max Low-speed oscillator and RTC ON µA 1. Typical values are measured at TA = 25 °C. 2. Based on characterization, not tested in production. Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -45 25 70 Temperature (°C) 42/91 Doc ID 13587 Rev 10 90 110 STM32F103x8, STM32F103xB Electrical characteristics Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -40 0 25 70 85 105 Temperature (°C) Figure 18. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 Consumption (µA) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.5 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Doc ID 13587 Rev 10 43/91 Electrical characteristics STM32F103x8, STM32F103xB Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned. ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). ● Ambient temperature and VDD supply voltage conditions summarized in Table 9. ● Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 36 27 48 MHz 24.2 18.6 36 MHz 19 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.8 2 MHz 2.2 1.9 1 MHz 1.6 1.45 500 kHz 1.3 1.25 125 kHz 1.08 1.06 64 MHz 31.4 23.9 48 MHz 23.5 17.9 36 MHz 18.3 14.1 24 MHz 12.2 9.5 16 MHz 8.5 6.8 8 MHz 4.9 4 4 MHz 2.7 2.2 2 MHz 1.6 1.4 1 MHz 1.02 0.9 500 kHz 0.73 0.67 125 kHz 0.5 0.48 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 44/91 Doc ID 13587 Rev 10 Unit mA mA STM32F103x8, STM32F103xB Table 18. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD Supply current in Sleep mode (3) fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 14.4 5.5 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.95 64 MHz 12.3 4.4 48 MHz 9.3 3.3 36 MHz 7 2.5 4.8 1.8 3.2 1.2 1.6 0.6 1 0.5 0.72 0.47 1 MHz 0.56 0.44 500 kHz 0.49 0.42 125 kHz 0.43 0.41 Unit mA 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 10 45/91 Electrical characteristics STM32F103x8, STM32F103xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: ● all I/O pins are in input mode with a static value at VDD or VSS (no load) ● all peripherals are disabled unless otherwise mentioned ● the given value is calculated by measuring the current consumption ● – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Table 19. Peripheral current consumption(1) Peripheral Typical consumption at 25 °C TIM2 1.2 TIM3 1.2 TIM4 0.9 SPI2 0.2 USART2 0.35 USART3 0.35 I2C1 0.39 I2C2 0.39 USB 0.65 CAN 0.72 GPIO A 0.47 GPIO B 0.47 GPIO C 0.47 GPIO D 0.47 GPIO E 0.47 ADC1(2) 1.81 ADC2 1.78 TIM1 1.6 SPI1 0.43 USART1 0.85 APB1 APB2 Unit mA mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 46/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 5.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 0 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) OSC_IN rise or fall time(1) Cin(HSE) 16 ns 20 OSC_IN input capacitance(1) 5 DuCy(HSE) Duty cycle IL V pF 45 OSC_IN Input leakage current VSS  VIN  VD 55 % ±1 µA D 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 32.768 1000 kHz fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage 0.7VDD VDD VLSEL OSC32_IN input pin low level voltage VSS 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) V Cin(LSE) ns 50 OSC32_IN input capacitance(1) 5 DuCy(LSE) Duty cycle IL 30 OSC32_IN Input leakage current VSS  VIN  VD pF 70 % ±1 µA D Doc ID 13587 Rev 10 47/91 Electrical characteristics STM32F103x8, STM32F103xB 1. Guaranteed by design, not tested in production. Figure 19. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 20. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE EXTER NAL CLOCK SOURC E fLSE_ext STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 48/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 22. Symbol HSE 4-16 MHz oscillator characteristics(1) (2) Parameter fOSC_IN Conditions Min Typ Max Unit 4 8 16 MHz Oscillator frequency Feedback resistor RF Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) CL1 CL2(3) i2 RS = 30 Oscillator transconductance (5) 200 k 30 pF VDD = 3.3 V, VIN = VSS with 30 pF load HSE driving current gm tSU(HSE Electrical characteristics Startup startup time 1 25 mA mA/V VDD is stabilized 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 21. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F103xx ai14145 1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 13587 Rev 10 49/91 Electrical characteristics STM32F103x8, STM32F103xB Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL  7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Feedback resistor RF CL1 CL2(2) Max Unit 5 Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) I2 LSE driving current gm Oscillator Transconductance tSU(LSE)(4) Typ M RS = 30 k 15 pF VDD = 3.3 V, VIN = VSS 1.4 µA 5 startup time VDD is stabilized µA/V 3 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 22. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator CL2 RF Bias controlled gain OSC32_OU T STM32F103xx ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 50/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics High-speed internal (HSI) RC oscillator HSI oscillator characteristics(1) (2) Table 24. Symbol Parameter fHSI Conditions Min Frequency Typ Max 8 ACCHSI Accuracy of HSI oscillator tsu(HSI) HSI oscillator startup time IDD(HSI) HSI oscillator power consumption Unit MHz TA = –40 to 105 °C –2 1 2.5 % TA = –10 to 85 °C –1.5 1 2.2 % TA = 0 to 70 °C –1.3 1 2 % TA = 25 °C –1.1 1 1.8 % 2 µs 80 100 µA Min Typ Max Unit 30 40 60 kHz 85 µs 1.2 µA 1 1. Guaranteed by design, not tested in production. 2. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the RC oscillator ● Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Doc ID 13587 Rev 10 51/91 Electrical characteristics Table 26. STM32F103x8, STM32F103xB Low-power mode wakeup timings Symbol Parameter Conditions Typ Unit Wakeup on HSI RC clock 1.8 µs Wakeup from Stop mode (regulator in run mode) HSI RC wakeup time = 2 µs 3.6 Wakeup from Stop mode (regulator in low power mode) HSI RC wakeup time = 2 µs, Regulator wakeup from LP mode time = 5 µs 5.4 HSI RC wakeup time = 2 µs, Regulator wakeup from power down time = 38 µs 50 tWUSLEEP(1) Wakeup from Sleep mode tWUSTOP(1) µs tWUSTDBY(1) Wakeup from Standby mode µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Value Symbol Parameter Test conditions Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 72 MHz tLOCK PLL lock time 200 µs fPLL_IN 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 28. Symbol tprog tERASE tME 52/91 Flash memory characteristics Min(1) Typ Max(1) Unit 16-bit programming time TA–40 to +105 °C 40 52.5 70 µs Page (1 KB) erase time TA –40 to +105 °C 20 40 ms Mass erase time TA –40 to +105 °C 20 40 ms Parameter Conditions Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 28. Symbol IDD Vprog Electrical characteristics Flash memory characteristics (continued) Max(1) Unit Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 µA 3.6 V Parameter Supply current Conditions Programming voltage Min(1) Typ 2 1. Guaranteed by design, not tested in production. Table 29. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle(2) at TA = 105 °C 10 10 kcycles (2) at TA = 55 °C Unit Typ Max kcycles Years 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. ● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 30. They are based on the EMS levels and classes defined in application note AN1709. Doc ID 13587 Rev 10 53/91 Electrical characteristics Table 30. STM32F103x8, STM32F103xB EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD 3.3 V, TA +25 °C, Voltage limits to be applied on any I/O pin to fHCLK 72 MHz induce a functional disturbance conforms to IEC 1000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, TA +25 °C, fHCLK 72 MHz conforms to IEC 1000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 31. Symbol SEMI 54/91 EMI characteristics Parameter Peak level Conditions VDD 3.3 V, TA 25 °C, LQFP100 package compliant with SAE J 1752/3 Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 0.1 to 30 MHz 12 12 30 to 130 MHz 22 19 130 MHz to 1GHz 23 29 SAE EMI Level 4 4 Doc ID 13587 Rev 10 dBµV - STM32F103x8, STM32F103xB 5.3.11 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 32. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) TA +25 °C conforming to JESD22-A114 TA +25 °C conforming to JESD22-C101 Electrostatic discharge VESD(CDM) voltage (charge device model) Class Maximum value(1) 2 Unit 2000 V II 500 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 33. Symbol LU Electrical sensitivities Parameter Conditions Static latch-up class TA +105 °C conforming to JESD78A Doc ID 13587 Rev 10 Class II level A 55/91 Electrical characteristics 5.3.12 STM32F103x8, STM32F103xB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 34. I/O static characteristics Symbol VIL VIH Parameter Conditions Input low level voltage Standard IO input high level voltage Input low level voltage VIH Input high level voltage Ilkg IO FT Schmitt trigger voltage hysteresis(2) Input leakage current (4) Max –0.5 0.8 2 VDD+0.5 2 5.5V –0.5 0.35 VDD 0.65 VDD VDD+0.5 CMOS ports Standard IO Schmitt trigger voltage hysteresis(2) Vhys Typ Unit V TTL ports IO FT(1) input high level voltage VIL Min V 200 mV 5% VDD(3) mV VSS  VIN  VDD Standard I/Os 1 µA VIN= 5 V I/O FT 3 RPU Weak pull-up equivalent resistor(5) VIN VSS 30 40 50 k RPD Weak pull-down equivalent resistor(5) VIN VDD 30 40 50 k CIO I/O pin capacitance 5 pF 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: ● ● 56/91 For VIH: – if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included – if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included For VIL: – if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included – if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). ● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. Symbol Output voltage characteristics Parameter VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD–0.4 0.4 V 2.4 1.3 V VDD–1.3 0.4 V VDD–0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. Doc ID 13587 Rev 10 57/91 Electrical characteristics STM32F103x8, STM32F103xB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 36. I/O AC characteristics(1) MODEx[1:0] Symbol bit value(1) Parameter Conditions Min fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 125(3) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 Max 10 MHz 25(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 23. 3. Guaranteed by design, not tested in production. 58/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics Figure 23. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. Symbol NRST pin characteristics Parameter Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage –0.5 0.8 VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis VF(NRST) V Weak pull-up equivalent resistor(2) RPU (1) Unit 200 VIN VSS 30 NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse 300 40 mV 50 k 100 ns ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Doc ID 13587 Rev 10 59/91 Electrical characteristics STM32F103x8, STM32F103xB Figure 24. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset FILTER 0.1 µF STM32F10xxx ai14132b 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 37. Otherwise the reset will not be taken into account by the device. 5.3.14 TIM timer characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 13.9 ns Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz 16 bit 65536 tTIMxCLK 910 µs 65536 × 65536 tTIMxCLK 59.6 s Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 60/91 Doc ID 13587 Rev 10 Unit STM32F103x8, STM32F103xB 5.3.15 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 39. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line µs ns 300 µs 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 13587 Rev 10 61/91 Electrical characteristics STM32F103x8, STM32F103xB Figure 25. I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 kΩ 4 .7 kΩ 100Ω STM32F103xx SDA I2C bus 100Ω SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) tw(SCKL) th(STA) SCL tw(SCKH) tsu(SDA) tr(SCK) tsu(STA:STO) S TOP th(SDA) tsu(STO) tf(SCK) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 40. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. 62/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. Symbol fSCK 1/tc(SCK) SPI characteristics(1) Parameter Conditions Min Max Master mode 0 18 Slave mode 0 18 SPI clock frequency MHz SPI clock rise and fall time Capacitive load: C = 30 pF tsu(NSS)(2) NSS setup time Slave mode 4 tPCLK th(NSS)(2) NSS hold time Slave mode 73 tr(SCK) tf(SCK) Unit 8 (2) tw(SCKH) Master mode, fPCLK = 36 MHz, SCK high and low time tw(SCKL)(2) presc = 4 tsu(MI) (2) Data input setup time Master mode tsu(SI)(2) Data input setup time Slave mode th(MI) (2) Data input hold time Master mode th(SI)(2) Data input hold time Slave mode ta(SO)(2)(3) Data output access time tdis(SO)(2)(4) Data output disable time tv(SO) (2)(1) Data output valid time tv(MO) (2)(1) th(SO)(2) th(MO) (2) Data output valid time 50 SPI1 1 SPI2 5 60 1 SPI1 1 SPI2 5 ns 3 Slave mode, fPCLK = 36 MHz, presc = 4 0 55 Slave mode, fPCLK = 24 MHz 0 4 tPCLK Slave mode 10 Slave mode (after enable edge) 25 Master mode (after enable edge) 3 Slave mode (after enable edge) 25 Master mode (after enable edge) 4 Data output hold time 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 13587 Rev 10 63/91 Electrical characteristics STM32F103x8, STM32F103xB Figure 26. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 64/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics Figure 28. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Doc ID 13587 Rev 10 65/91 Electrical characteristics Table 43. STM32F103x8, STM32F103xB USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) VOH Static output level high RL of 15 k to VSS(5) 0.3 V 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 29. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 44. tr tf ai14137 USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Driver characteristics tr tf trfm VCRS Rise time(2) (2) Fall time Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.16 CAN (controller area network) interface Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 66/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 5.3.17 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) µA fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V fTRIG(2) External trigger frequency VAIN(3) Conversion voltage range RAIN(2) External input impedance RADC(2) 160(1) fADC = 14 MHz 0 (VSSA or VREFtied to ground) See Equation 1 and Table 46 k Sampling switch resistance 1 k CADC(2) Internal sample and hold capacitor 12 pF tCAL(2) Calibration time fADC = 14 MHz tlat(2) Injection trigger conversion latency fADC = 14 MHz tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) 5.9 µs 83 1/fADC 0.214 3 fADC = 14 MHz µs 1/fADC 0.143 µs 2(4) 1/fADC 0.107 17.1 µs 1.5 239.5 1/fADC 1 µs 18 µs 0 fADC = 14 MHz (4) 1 0 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 5 and Figure 6. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45. Doc ID 13587 Rev 10 67/91 Electrical characteristics STM32F103x8, STM32F103xB Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------- – R ADC N+2 f ADC  C ADC  ln  2  The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 46. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (k) 1.5 0.11 1.2 7.5 0.54 10 13.5 0.96 19 28.5 2.04 41 41.5 2.96 60 55.5 3.96 80 71.5 5.11 104 239.5 17.1 350 1. Based on characterization, not tested in production. Table 47. Symbol ADC accuracy - limited test conditions(1) (2) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. 68/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics ADC accuracy(1) (2) (3) Table 48. Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 4. Based on characterization, not tested in production. Figure 30. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET (3) 7 (1) 6 5 4 EO EL 3 ED 2 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA Doc ID 13587 Rev 10 ai14395b 69/91 Electrical characteristics STM32F103x8, STM32F103xB Figure 31. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 45 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 32 or Figure 33, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 µF // 10 nF VDDA 1 µF // 10 nF VSSA /VREF– (see note 1) ai14388b 1. VREF+ and VREF– inputs are available only on 100-pin packages. 70/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Electrical characteristics Figure 33. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 5.3.18 Temperature sensor characteristics Table 49. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min VSENSE linearity with temperature Typ Max Unit 1 2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V 10 µs 17.1 µs Startup time 4 ADC sampling time when reading the temperature 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 13587 Rev 10 71/91 Package characteristics STM32F103x8, STM32F103xB 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 72/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Package characteristics Figure 34. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 35. Recommended footprint (dimensions in mm)(1)(2)(3) Seating plane C ddd C 1.00 4.30 A2 A 27 19 A1 A3 E2 28 18 b 27 18 28 0.50 4.10 19 4.30 4.10 4.80 4.80 e D2 D 36 10 9 1 36 0.75 0.30 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2. The back-side pad is not internally connected to the VSS or VDD power pads. 3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should also be soldered to the PCB. Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.020 0.050 0.0008 0.0020 A2 0.650 1.000 0.0256 0.0394 A3 0.250 A 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 D 5.875 6.000 6.125 0.2313 0.2362 0.2411 D2 1.750 3.700 4.250 0.0689 0.1457 0.1673 E 5.875 6.000 6.125 0.2313 0.2362 0.2411 E2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 L 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 10 73/91 Package characteristics STM32F103x8, STM32F103xB Figure 36. LFBGA100 - low profile fine pitch ball grid array package outline C Seating plane ddd C A2 A4 A3 A1 A D B D1 F e A K J H G F E D C B A F E1 E e 1 2 3 4 5 6 7 8 9 10 A1 corner index area (see note 5) ∅b (100 balls) ∅eee M C A B ∅ fff M C Bottom view ai14396 1. Drawing is not to scale. Table 51. LFBGA100 - low profile fine pitch ball grid array package mechanical data inches(1) mm Dim. Min Typ A A1 Max Min 1.700 Max 0.0669 0.270 0.0106 A2 1.085 0.0427 A3 0.30 0.0118 A4 0.80 0.0315 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 D 9.85 10.00 10.15 0.3878 0.3937 0.3996 D1 E 7.20 9.85 10.00 0.2835 10.15 0.3878 0.3937 E1 7.20 0.2835 e 0.80 0.0315 F 1.40 0.0551 0.3996 ddd 0.12 0.0047 eee 0.15 0.0059 fff 0.08 0.0031 N (number of balls) 100 1. Values in inches are converted from mm and rounded to 4 decimal digits. 74/91 Typ Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Package characteristics Figure 37. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended – 4 to 6 mils screen print Dpad Dsm Doc ID 13587 Rev 10 75/91 Package characteristics STM32F103x8, STM32F103xB Figure 39. Recommended footprint(1)(2) Figure 38. LQFP100, 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 25 26 Pin 1 1 identification 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 52. LQPF100, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Min 1.6 A1 0.05 0.15 Max 0.063 0.002 0.0059 A2 1.4 1.35 1.45 0.0551 0.0531 0.0571 b 0.22 0.17 0.27 0.0087 0.0067 0.0106 0.09 0.2 0.0035 0.0079 c D 16 15.8 16.2 0.6299 0.622 0.6378 D1 14 13.8 14.2 0.5512 0.5433 0.5591 D3 12 E 16 15.8 16.2 0.6299 0.622 0.6378 E1 14 13.8 14.2 0.5512 0.5433 0.5591 E3 12 0.0177 0.0295 0.0° 7.0° e 0.5 L 0.6 L1 1 k 3.5° ccc 0.4724 0.4724 0.0197 0.45 0.75 0.0236 0.0394 0.0° 7.0° 0.08 3.5° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 76/91 Typ Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Package characteristics Figure 40. LQFP64, 64-pin low-profile quad flat package outline(1) Figure 41. Recommended footprint(1)(2) A A2 48 33 A1 0.3 49 E 32 0.5 b E1 12.7 10.3 10.3 e 64 17 1.2 1 16 7.8 D1 c 12.7 L1 D ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53. LQFP64, 64-pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197  0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 10 77/91 Package characteristics STM32F103x8, STM32F103xB Figure 42. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline B D D1 A A e A1 F H F G F E E1 E D C B A e 1 2 3 A1 ball pad corner(2) A3 4 5 6 7 8 Øb (64 balls) A4 A2 Seating C plane Bottom view ME_R8 1. Drawing is not to scale. Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ 1.200 A1 Max 0.0472 0.150 0.0059 A2 0.785 0.0309 A3 0.200 0.0079 A4 0.600 0.0236 b 0.300 0.250 0.350 0.0118 0.0098 0.0138 D 5.000 4.850 5.150 0.1969 0.1909 0.2028 D1 3.500 E 5.000 0.1909 0.2028 E1 3.500 0.1378 e 0.500 0.0197 F 0.750 0.0295 0.1378 4.850 5.150 0.1969 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 78/91 Min Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Package characteristics Figure 43. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process Doc ID 13587 Rev 10 79/91 Package characteristics STM32F103x8, STM32F103xB Figure 44. LQFP48, 48-pin low-profile quad flat package outline(1) Figure 45. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 0.25 mm Gage plane C 1.20 D 36 0.30 25 37 D1 24 k D3 36 A1 L 25 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 5.80 E3 E1 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 55. LQFP48, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Min 1.600 A1 0.050 0.150 Max 0.0630 0.0020 0.0059 A2 1.400 1.350 1.450 0.0551 0.0531 0.0571 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.090 0.200 0.0035 0.0079 c D 9.000 8.800 9.200 0.3543 0.3465 0.3622 D1 7.000 6.800 7.200 0.2756 0.2677 0.2835 D3 5.500 E 9.000 8.800 9.200 0.3543 0.3465 0.3622 E1 7.000 6.800 7.200 0.2756 0.2677 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.600 0.0177 0.0295 L1 1.000 k 3.5° 0° 7° ccc 0.2165 0.450 0.750 0.0236 0.0394 0° 7° 0.080 3.5° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 80/91 Typ Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 35. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where: ● TA max is the maximum ambient temperature in C, ● JA is the package junction-to-ambient thermal resistance, in C/W, ● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), ● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 56. Package thermal characteristics Symbol JA 6.2.1 Parameter Value Thermal resistance junction-ambient LFBGA100 - 10 × 10 mm / 0.8 mm pitch 44 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Unit °C/W Thermal resistance junction-ambient TFBGA64 - 5 × 5 mm / 0.5 mm pitch 65 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch 18 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 13587 Rev 10 81/91 Package characteristics 6.2.2 STM32F103x8, STM32F103xB Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 57: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 56 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 57: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 82/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Package characteristics Using the values obtained in Table 56 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 57: Ordering information scheme). Figure 46. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 115 125 135 TA (°C) Doc ID 13587 Rev 10 83/91 Ordering information scheme 7 STM32F103x8, STM32F103xB Ordering information scheme Table 57. Ordering information scheme Example: STM32 F 103 C 8 T 7 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count T = 36 pins C = 48 pins R = 64 pins V = 100 pins Flash memory size(1) 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and real 1. Although STM32F103x6 devices are not described in this datasheet, orderable part numbers that do not show the A internal code after temperature range code 6 or 7 should be referred to this datasheet for the electrical characteristics. The low-density datasheet only covers STM32F103x6 devices that feature the A code. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 84/91 Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB 8 Revision history Revision history Table 58. Document revision history Date Revision 01-jun-2007 1 Initial release. 2 Flash memory size modified in Note 7, Note 4, Note 7, Note 8 and BGA100 pins added to Table 5: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line LFBGA100 ballout added. THSE changed to TLSE in Figure 20: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes. tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator characteristics. IDD(HSI) max value added to Table 24: HSI oscillator characteristics. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latch-up. 25 °C and 85 °C conditions removed and class name modified in Table 33: Electrical sensitivities. RPU and RPD min and max values added to Table 34: I/O static characteristics. RPU min and max values added to Table 37: NRST pin characteristics. Figure 25: I2C bus AC waveforms and measurement circuit and Figure 24: Recommended NRST pin protection corrected. Notes removed below Table 9, Table 37, Table 43. IDD typical values changed in Table 11: Maximum current consumption in Run and Sleep modes. Table 38: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 45: ADC characteristics. In Table 29: Flash memory endurance and data retention, typical endurance and data retention for TA = 85 °C added, data retention for TA = 25 °C removed. VBG changed to VREFINT in Table 12: Embedded internal reference voltage. Document title changed. Controller area network (CAN) section modified. Figure 12: Power supply scheme modified. Features on page 1 list optimized. Small text changes. 20-Jul-2007 Changes Doc ID 13587 Rev 10 85/91 Revision history Table 58. STM32F103x8, STM32F103xB Document revision history (continued) Date 18-Oct-2007 86/91 Revision Changes 3 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see Section 6: Package characteristics). All packages are ECOPACK® compliant. Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package characteristics). Table 5: Medium-density STM32F103xx pin definitions updated and clarified. Table 26: Low-power mode wakeup timings updated. TA min corrected in Table 12: Embedded internal reference voltage. Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics. VESD(CDM) value added to Table 32: ESD absolute maximum ratings. Note 3 added and VOH parameter description modified in Table 35: Output voltage characteristics. Note 1 modified under Table 36: I/O AC characteristics. Equation 1 and Table 46: RAIN max for fADC = 14 MHz added to Section 5.3.17: 12-bit ADC characteristics. VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified and tlatr added in Table 45: ADC characteristics. Figure 30: ADC accuracy characteristics updated. Note 1 modified below Figure 31: Typical connection diagram using the ADC. Electrostatic discharge (ESD) on page 55 modified. Number of TIM4 channels modified in Figure 1: STM32F103xx performance line block diagram. Maximum current consumption Table 13, Table 14 and Table 15 updated. Vhysmodified in Table 34: I/O static characteristics. Table 48: ADC accuracy updated. tVDD modified in Table 10: Operating conditions at power-up / power-down. VFESD value added in Table 30: EMS characteristics. Values corrected, note 2 modified and note 3 removed in Table 26: Low-power mode wakeup timings. Table 16: Typical and maximum current consumptions in Stop and Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2 modified, Note 2 added. Table 21: Typical current consumption in Standby mode added. On-chip peripheral current consumption on page 46 added. ACCHSI values updated in Table 24: HSI oscillator characteristics. Vprog added to Table 28: Flash memory characteristics. Upper option byte address modified in Figure 9: Memory map. Typical fLSI value added in Table 25: LSI oscillator characteristics and internal RC value corrected from 32 to 40 kHz in entire document. TS_temp added to Table 49: TS characteristics. NEND modified in Table 29: Flash memory endurance and data retention. TS_vrefint added to Table 12: Embedded internal reference voltage. Handling of unused pins specified in General input/output characteristics on page 56. All I/Os are CMOS and TTL compliant. Figure 32: Power supply and reference decoupling (VREF+ not connected to VDDA) modified. tJITTER and fVCO removed from Table 27: PLL characteristics. Appendix A: Important notes on page 81 added. Added Figure 14, Figure 15, Figure 16 and Figure 18. Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 58. Revision history Document revision history (continued) Date 22-Nov-2007 Revision Changes 4 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 13 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: STM32F103xx mediumdensity device features and peripheral counts. Main function and default alternate function modified for PC14 and PC15 in, Note 5 added and Remap column added in Table 5: Mediumdensity STM32F103xx pin definitions. VDD–VSS ratings and Note 1 modified in Table 6: Voltage characteristics, Note 1 modified in Table 7: Current characteristics. Note 1 and Note 2 added in Table 11: Embedded reset and power control block characteristics. IDD value at 72 MHz with peripherals enabled modified in Table 14: Maximum current consumption in Run mode, code with data processing running from RAM. IDD value at 72 MHz with peripherals enabled modified in Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM on page 41. IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Note added in Table 17 on page 44 and Table 18 on page 45. ADC1 and ADC2 consumption and notes modified in Table 19: Peripheral current consumption. tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23, respectively. Maximum values removed from Table 26: Low-power mode wakeup timings. tRET conditions modified in Table 29: Flash memory endurance and data retention. Figure 12: Power supply scheme corrected. Figure 17: Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added. Note removed below Figure 26: SPI timing diagram - slave mode and CPHA = 0. Note added below Figure 27: SPI timing diagram - slave mode and CPHA = 1(1). Details on unused pins removed from General input/output characteristics on page 56. Table 41: SPI characteristics updated. Table 42: USB startup time added. VAIN, tlat and tlatr modified, note added and Ilkg removed in Table 45: ADC characteristics. Test conditions modified and note added in Table 48: ADC accuracy. Note added below Table 46 and Table 49. Inch values corrected in Table 52: LQPF100, 100-pin low-profile quad flat package mechanical data, Table 53: LQFP64, 64-pin low-profile quad flat package mechanical data and Table 55: LQFP48, 48-pin lowprofile quad flat package mechanical data. JAvalue for VFQFPN36 package added in Table 56: Package thermal characteristics Order codes replaced by Section 7: Ordering information scheme. MCU ‘s operating conditions modified in Typical current consumption on page 44. Avg_Slope and V25 modified in Table 49: TS characteristics. I2C interface characteristics on page 61 modified. Impedance size specified in A.4: Voltage glitch on ADC input 0 on page 81. Doc ID 13587 Rev 10 87/91 Revision history Table 58. STM32F103x8, STM32F103xB Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 22-May-2008 88/91 Revision Changes 5 Figure 2: Clock tree on page 20 added. Maximum TJ value given in Table 8: Thermal characteristics on page 35. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 9: Memory map on page 31 for address). IDD modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. ACCHSI modified in Table 24: HSI oscillator characteristics on page 51, note 2 removed. PD, TA and TJ added, tprog values modified and tprog description clarified in Table 28: Flash memory characteristics on page 52. tRET modified in Table 29: Flash memory endurance and data retention. VNF(NRST) unit corrected in Table 37: NRST pin characteristics on page 59. Table 41: SPI characteristics on page 63 modified. IVREF added to Table 45: ADC characteristics on page 67. Table 47: ADC accuracy - limited test conditions added. Table 48: ADC accuracy modified. LQFP100 package specifications updated (see Section 6: Package characteristics on page 72). Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36 footprints added (see Figure 39, Figure 41, Figure 45 and Figure 35). Section 6.2: Thermal characteristics on page 81 modified, Section 6.2.1 and Section 6.2.2 added. Appendix A: Important notes on page 81 removed. 6 Small text changes. Figure 9: Memory map clarified. In Table 29: Flash memory endurance and data retention: – NEND tested over the whole temperature range – cycling conditions specified for tRET – tRET min modified at TA = 55 °C V25, Avg_Slope and TL modified in Table 49: TS characteristics. CRC feature removed. 7 CRC feature added back. Small text changes. Section 1: Introduction modified. Section 2.2: Full compatibility throughout the family added. IDD at TA max = 105 °C added to Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 42. IDD_VBAT removed from Table 21: Typical current consumption in Standby mode on page 47. Values added to Table 40: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) on page 62. Figure 26: SPI timing diagram - slave mode and CPHA = 0 on page 64 modified. Equation 1 corrected. tRET at TA = 105 °C modified in Table 29: Flash memory endurance and data retention on page 53. VUSB added to Table 43: USB DC electrical characteristics on page 66. Figure 46: LQFP100 PD max vs. TA on page 83 modified. Axx option added to Table 57: Ordering information scheme on page 84. Doc ID 13587 Rev 10 STM32F103x8, STM32F103xB Table 58. Revision history Document revision history (continued) Date 21-Jul-2008 22-Sep-2008 Revision Changes 8 Power supply supervisor updated and VDDA added to Table 9: General operating conditions. Capacitance modified in Figure 12: Power supply scheme on page 33. Table notes revised in Section 5: Electrical characteristics. Table 16: Typical and maximum current consumptions in Stop and Standby modes modified. Data added to Table 16: Typical and maximum current consumptions in Stop and Standby modes and Table 21: Typical current consumption in Standby mode removed. fHSE_ext modified in Table 20: High-speed external user clock characteristics on page 47. fPLL_IN modified in Table 27: PLL characteristics on page 52. Minimum SDA and SCL fall time value for Fast mode removed from Table 39: I2C characteristics on page 61, note 1 modified. th(NSS) modified in Table 41: SPI characteristics on page 63 and Figure 26: SPI timing diagram - slave mode and CPHA = 0 on page 64. CADC modified in Table 45: ADC characteristics on page 67 and Figure 31: Typical connection diagram using the ADC modified. Typical TS_temp value removed from Table 49: TS characteristics on page 71. LQFP48 package specifications updated (see Table 55 and Table 45), Section 6: Package characteristics revised. Axx option removed from Table 57: Ordering information scheme on page 84. Small text changes. 9 STM32F103x6 part numbers removed (see Table 57: Ordering information scheme). Small text changes. General-purpose timers (TIMx) and Advanced-control timer (TIM1) on page 15 updated. Notes updated in Table 5: Medium-density STM32F103xx pin definitions on page 26. Note 2 modified below Table 6: Voltage characteristics on page 34, |VDDx| min and |VDDx| min removed. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 38. IDD in standby mode at 85 °C modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 42. General input/output characteristics on page 56 modified. fHCLK conditions modified in Table 30: EMS characteristics on page 54. JA and pitch value modified for LFBGA100 package in Table 56: Package thermal characteristics. Small text changes. Doc ID 13587 Rev 10 89/91 Revision history Table 58. STM32F103x8, STM32F103xB Document revision history (continued) Date 23-Apr-2009 90/91 Revision Changes 10 I/O information clarified on page 1. Figure 3: STM32F103xx performance line LFBGA100 ballout modified. Figure 9: Memory map modified. Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column in Table 5: Medium-density STM32F103xx pin definitions. PD for LFBGA100 corrected in Table 9: General operating conditions. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Figure 17 shows a typical curve (title modified). ACCHSI max values modified in Table 24: HSI oscillator characteristics. TFBGA64 package added (see Table 54 and Table 42). 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