STM32F103ZCH6

厂商：
STMICROELECTRONICS(意法半导体)
封装：
LFBGA144
描述：
IC MCU 32BIT 256KB FLSH 144LFBGA

数据手册：

下载STM32F103ZCH6.pdf

立即购买

数据手册
价格&库存

STM32F103ZCH6 数据手册

STM32F103xC, STM32F103xD, STM32F103xE High-density performance line Arm®-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Datasheet −production data Features • Core: Arm® 32-bit Cortex®-M3 CPU – – WLCSP64 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division • Memories – – – – 256 to 512 Kbytes of Flash memory up to 64 Kbytes of SRAM Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – – – – – – 2.0 to 3.6 V application supply and I/Os POR, PDR, and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC with calibration 32 kHz oscillator for RTC with calibration • Low power – – Sleep, Stop and Standby modes VBAT supply for RTC and backup registers – – – – – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 2 × 16-bit motor control PWM timers with deadtime generation and emergency stop 2 × watchdog timers (Independent and Window) SysTick timer: a 24-bit downcounter 2 × 16-bit basic timers to drive the DAC • Up to 13 communication interfaces – – – – – – Up to 2 × I2C interfaces (SMBus/PMBus) Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed CAN interface (2.0B Active) USB 2.0 full speed interface SDIO interface Table 1.Device summary Conversion range: 0 to 3.6 V Triple-sample and hold capability Temperature sensor Reference • DMA: 12-channel DMA controller Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs • Debug mode – – • Up to 11 timers • ECOPACK® packages • 2 × 12-bit D/A converters – LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm • CRC calculation unit, 96-bit unique ID • 3 × 12-bit, 1 µs A/D converters (up to 21 channels) – – – LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm Part number STM32F103xC STM32F103RC STM32F103VC STM32F103ZC STM32F103xD STM32F103RD STM32F103VD STM32F103ZD STM32F103xE STM32F103RE STM32F103ZE STM32F103VE Serial wire debug (SWD) & JTAG interfaces Cortex®-M3 Embedded Trace Macrocell™ • Up to 112 fast I/O ports – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant July 2018 DS5792 Rev 13 1/143 www.st.com Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/143 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 15 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 45 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DS5792 Rev 13 3/143 4 Contents 6 STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2 LFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 133 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High-density STM32F103xC/D/E pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 49 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 50 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 67 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 68 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 75 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 81 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 85 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DS5792 Rev 13 5/143 6 List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. 6/143 STM32F103xC, STM32F103xD, STM32F103xE Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LFBGA144 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 115 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 118 WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLCSP64 recommended PCB design rules (0.5 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 121 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 129 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F103xC/D/E BGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F103xC/D/E performance line BGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32F103xC/D/E performance line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32F103xC/D/E performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F103xC/D/E performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F103xC/D/E performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 48 Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 48 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 66 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 67 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 68 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 75 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 77 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 78 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 80 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 81 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DS5792 Rev 13 7/143 8 List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. 8/143 STM32F103xC, STM32F103xD, STM32F103xE NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 84 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 85 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 109 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 110 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 LFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 122 LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . 126 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 129 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 130 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xC/D/E family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xC/D/E datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS5792 Rev 13 9/143 135 Description 2 STM32F103xC, STM32F103xD, STM32F103xE Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xC/D/E high-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F103xC/D/E high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC. 10/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 2.1 Description Device overview The STM32F103xC/D/E high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Peripherals STM32F103Rx Flash memory in Kbytes 256 SRAM in Kbytes 48 FSMC Timers 384 STM32F103Vx 512 64 No 384 48 Yes 4 Advanced-control 2 Basic 2 I 512 64 General-purpose SPI(I2S)(2) Comm 256 (1) STM32F103Zx 256 384 48 64 Yes 3(2) 2C 2 USART 5 USB 1 CAN 1 SDIO 1 GPIOs 51 80 112 12-bit ADC Number of channels 3 16 3 16 3 21 12-bit DAC Number of channels 2 2 CPU frequency 72 MHz Operating voltage Operating temperatures Package 512 2.0 to 3.6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10) Junction temperature: –40 to + 125 °C (see Table 10) LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144 1. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. DS5792 Rev 13 11/143 135 Description STM32F103xC, STM32F103xD, STM32F103xE Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram 37*4!' 4RACETRIG 4RACE CONTROLLER 0BUS &LASH OBL INTERFACE .*4234 *4$) *4#+37#,+ *4-337$)/ *4$/ AS!& 6$$ 40)5 )BUS #ORTEX -#05 &MAX-(Z $BUS 3YSTEM .6)# "US -ATRIX 42!#%#,+ 42!#%$;= AS!3 6$$ &LASH+BYTES BIT 32!- +" 6$$! 2#-(Z '0$-! !;= $;= #,+ ./% .7% .%;= .",;= .7!)4 .,OR.!$6 AS!& 2#K(Z CHANNELS 0,, !("&MAX-(Z '0$-! CHANNELS &3-# $;= #-$ #+AS!& 0/2 2ESET 2ESET #LOCK CONTROL 0";= '0)/PORT" 0#;= '0)/PORT# 0$;= '0)/PORT$ 0%;= '0)/PORT% 0&;= '0)/PORT& 0';= '0)/PORT' CHANNELS COMPLCHANNELS "+).%42AS!& CHANNELS COMPLCHANNELS "+).%42AS!& -/3)-)3/ 3#+.33AS!& 2848#43 243#+AS!& !(" !0" 4)- !0"&MAX-(Z '0)/PORT! 62%&n 62%& /3#?). /3#?/54 6"!4 6TO6 /3#?). /3#?/54 4!-0%2 24# !,!2-3%#/.$/54 4)- CHANNELS%42AS!& 4)- CHANNELS%42AS!& 4)- CHANNELS%42AS!& 4)- 53!24 53!24 CHANNELSAS!& 2848#43243 #+AS!& 2848#43243 #+AS!& 5!24 2848AS!& 5!24 2848AS!& 30))3 XXB IT 4)- .234 6$$! 633! 24# "ACKUP REG !75 "ACKUPINTERFACE 30) XXB IT )3 -/3)3$-)3/ 3#+#+-#+.3373AS!& -/3)3$-)3/ 3#+#+-#+.3373AS!& )# 3#,3$!3-"!AS!& 30) 32!-" )# 3#,3$!3-"!AS!& 53!24 77$' BX#!.DEVICE 53"&3 DEVICE 4EMPSENSOR !$#?).S COMMONTOTHE!$#S !$#?).SCOMMON TO!$#!$# !$#?).SON!$# 6$$ 84!,/3# -(Z 84!,K(Z !0"&MAX-(Z !& 06$ 3TANDBY INTERFACE 6"!4 %84)4 7+50 0!;= 6$$! 3UPPLY SUPERVISION 0/20$2 633 )7$' 0#,+ 0#,+ (#,+ &#,+ 3$)/ !(" !0" )NT 0OWER 6OLTREG 6TO6 BIT!$# )& BIT!$# )& 53"?$0#!.?48 53"?$-#!.?28 4)- )& BIT $!# )& $!#?/54AS!& 4)- BIT$!# $!#?/54AS!& 6$$! BIT!$# )& 6 $$! AIG 1. TA = –40 °C to +85 °C (suffix 6, see Table 75) or –40 °C to +105 °C (suffix 7, see Table 75), junction temperature up to 105 °C or 125 °C, respectively. 2. AF = alternate function on I/O port pin.9 12/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Description Figure 2. Clock tree )/,7)&/. WR)ODVKSURJUDPPLQJLQWHUIDFH 86% 3UHVFDOHU 86%&/. WR86%LQWHUIDFH 0+] ,6&/. 3HULSKHUDOFORFN HQDEOH 0+] +6,5& ,6&/. 6: 3//08/ +6, [ [[[ 3// 6@ /6,5& N+] 0+]PD[ 3&/. WR$3% SHULSKHUDOV 3HULSKHUDO&ORFN WR7,0DQG 7,0;&/. 3&/. 0+]PD[ 3HULSKHUDO&ORFN (QDEOHELWV 7,0 WLPHUV ,I$3%SUHVFDOHU [ HOVH[ 26&B287 WR&RUWH[6\VWHPWLPHU )&/.&RUWH[ IUHHUXQQLQJFORFN 3HULSKHUDO&ORFN (QDEOHELWV $3% 3UHVFDOHU 0+] /6(26& N+] WR)60& (QDEOHELWV 3//;735( 26&B,1 WR6',2 +&/. WR$+%EXVFRUH PHPRU\DQG'0$ 7,0 ,I$3%SUHVFDOHU [ HOVH [ &66 +6(26& )60&&/. &ORFN (QDEOHELWV +6( 26&B,1 6',2&/. 3HULSKHUDOFORFN HQDEOH 0+]PD[ 26&B287 WR,6 3HULSKHUDOFORFN HQDEOH 3HULSKHUDOFORFN HQDEOH +6, 3//65& WR,6 SHULSKHUDOVWR$3% WR7,0DQG7,0 7,0[&/. 3HULSKHUDO&ORFN (QDEOHELW WR$'&RU $'&&/. +&/. 7R6',2$+%LQWHUIDFH 3HULSKHUDOFORFN HQDEOH ,:'*&/. 0DLQ &ORFN2XWSXW 0&2 3//&/. /HJHQG +6( +LJK6SHHG([WHUQDOFORFNVLJQDO +6, +6, +LJK6SHHG,QWHUQDOFORFNVLJQDO +6( /6, /RZ6SHHG,QWHUQDOFORFNVLJQDO 6Y&Wϲϰ ϰϬ ϵ ϯϵ ϭϬ ϯϴ ϭϭ ϯϳ ϭϮ ϯϲ ϭϯ ϯϱ ϭϰ ϯϰ ϭϱ ϯϯ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ sͺϮ s ^^ͺϮ W ϭϯ W ϭϮ W ϭϭ W ϭϬ W ϵ W ϴ Wϵ Wϴ Wϳ Wϲ W ϭϱ W ϭϰ W ϭϯ W ϭϮ W ϯ s ^^ͺϰ sͺϰ W ϰ W ϱ W ϲ W ϳ Wϰ Wϱ W Ϭ W ϭ W Ϯ Wϭ Ϭ Wϭ ϭ s ^^ͺϭ sͺϭ sd WϭϯͲdDWZͲZd W ϭϰͲK ^ ϯϮͺ/E W ϭϱͲK ^ ϯϮͺKh d W ϬͲK^ ͺ/E W ϭͲK^ ͺKhd EZ^d WϬ Wϭ WϮ Wϯ s^^ s W ϬͲt< hW W ϭ W Ϯ DL 1. The above figure shows the package top view. DS5792 Rev 13 29/143 135 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side 8 7 6 5 4 3 2 PB5 PB3 PD2 PC10 PC11 PA14 A V DD_3 VSS_3 B PC14 PC15 PB9 PB6 PB4 NRST VBAT PB7 PC12 OSC_OUT PC2 PB8 PA13 VSSA PA1 PA5 PC1 VREF+ PA0WKUP DDA PA3 V C PC13 D OSC_IN E PC0 F G H V PA2 PA4 BOOT0 DD_4 PC4 V DD_2 BYPASS/ VSS_2 PA12 PA11 PA10 PA9 PC9 PA8 PC8 PC7 PC6 VSS_4 PB1 PB11 PB14 PB15 PA6 PA7 PC5 PB0 PA15 1 PB10 PB2 PB12 V SS_1 PB13 V DD_1 ai15460b 30/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) A3 A3 - - 1 1 PE2 I/O FT PE2 TRACECK/ FSMC_A23 - A2 B3 - - 2 2 PE3 I/O FT PE3 TRACED0/FSMC_A19 - B2 C3 - - 3 3 PE4 I/O FT PE4 TRACED1/FSMC_A20 - B3 D3 - - 4 4 PE5 I/O FT PE5 TRACED2/FSMC_A21 - B4 E3 - - 5 5 PE6 I/O FT PE6 TRACED3/FSMC_A22 - C2 B2 C6 1 6 6 VBAT S - VBAT - - A1 A2 C8 2 7 7 PC13-TAMPERRTC(5) I/O - PC13(6) TAMPER-RTC - B1 A1 B8 3 8 8 PC14OSC32_IN(5) I/O - PC14(6) OSC32_IN - C1 B1 B7 4 9 9 PC15OSC32_OUT(5) I/O - PC15(6) OSC32_OUT - C3 - - - - 10 PF0 I/O FT PF0 FSMC_A0 - C4 - - - - 11 PF1 I/O FT PF1 FSMC_A1 - D4 - - - - 12 PF2 I/O FT PF2 FSMC_A2 - E2 - - - - 13 PF3 I/O FT PF3 FSMC_A3 - E3 - - - - 14 PF4 I/O FT PF4 FSMC_A4 - E4 - - - - 15 PF5 I/O FT PF5 FSMC_A5 - D2 C2 - - 10 16 VSS_5 S - VSS_5 - - D3 D2 - - 11 17 VDD_5 S - VDD_5 - - F3 - - - - 18 PF6 I/O - PF6 ADC3_IN4/FSMC_NIORD - F2 - - - - 19 PF7 I/O - PF7 ADC3_IN5/FSMC_NREG - G3 - - - - 20 PF8 I/O - PF8 ADC3_IN6/FSMC_NIOWR - G2 - - - - 21 PF9 I/O - PF9 ADC3_IN7/FSMC_CD - G1 - - - - 22 PF10 I/O - PF10 ADC3_IN8/FSMC_INTR - D1 C1 D8 5 12 23 OSC_IN I - OSC_IN - - E1 D1 D7 6 13 24 OSC_OUT O - OSC_OUT - - F1 E1 C7 7 14 25 NRST I/O - NRST - - H1 F1 E8 8 15 26 PC0 I/O - PC0 ADC123_IN10 - H2 F2 F8 9 16 27 PC1 I/O - PC1 ADC123_IN11 - H3 E2 D6 10 17 28 PC2 I/O - PC2 ADC123_IN12 - DS5792 Rev 13 Default Remap 31/143 135 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) H4 F3 - 11 18 29 PC3(7) I/O - PC3 ADC123_IN13 - J1 G1 E7 12 19 30 VSSA S - VSSA - - K1 H1 - - 20 31 VREF- S - VREF- - - L1 J1 - 21 32 VREF+ S - VREF+ - - M1 K1 22 33 VDDA S - VDDA - - F7 (8) G8 13 Default Remap WKUP/USART2_CTS(9) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR - J2 G2 F6 14 23 34 PA0-WKUP I/O - PA0 K2 H2 E6 15 24 35 PA1 I/O - PA1 USART2_RTS(9) ADC123_IN1/ TIM5_CH2/TIM2_CH2(9) - L2 J2 H8 16 25 36 PA2 I/O - PA2 USART2_TX(9)/TIM5_CH3 ADC123_IN2/ TIM2_CH3 (9) - M2 K2 G7 17 26 37 PA3 I/O - PA3 USART2_RX(9)/TIM5_CH4 ADC123_IN3/TIM2_CH4(9) - G4 E4 F5 18 27 38 VSS_4 S - VSS_4 - - F4 F4 G6 19 28 39 VDD_4 S - VDD_4 - (9) J3 G3 H7 20 29 40 PA4 I/O - PA4 SPI1_NSS / USART2_CK(9) DAC_OUT1/ADC12_IN4 - K3 H3 E5 21 30 41 PA5 I/O - PA5 SPI1_SCK(9) DAC_OUT2 ADC12_IN5 - L3 J3 G5 22 31 42 PA6 I/O - PA6 SPI1_MISO(9) TIM8_BKIN/ADC12_IN6 TIM3_CH1(9) TIM1_BKIN M3 K3 G4 23 32 43 PA7 I/O - PA7 SPI1_MOSI(9)/ TIM8_CH1N/ADC12_IN7 TIM3_CH2(9) TIM1_CH1N J4 G4 H6 24 33 44 PC4 I/O - PC4 ADC12_IN14 - K4 H4 H5 25 34 45 PC5 I/O - PC5 ADC12_IN15 - L4 J4 H4 26 35 46 PB0 I/O - PB0 ADC12_IN8/TIM3_CH3 TIM8_CH2N TIM1_CH2N M4 K4 F4 27 36 47 PB1 I/O - PB1 ADC12_IN9/TIM3_CH4(9) TIM8_CH3N TIM1_CH3N 32/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions (continued) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) J5 G5 H3 28 37 48 PB2 I/O FT PB2/BOOT1 - - M5 - - - - 49 PF11 I/O FT PF11 FSMC_NIOS16 - L5 - - - - 50 PF12 I/O FT PF12 FSMC_A6 - H5 - - - - 51 VSS_6 S - VSS_6 - - G5 - - - - 52 VDD_6 S - VDD_6 - - K5 - - - - 53 PF13 I/O FT PF13 FSMC_A7 - M6 - - - - 54 PF14 I/O FT PF14 FSMC_A8 - L6 - - - - 55 PF15 I/O FT PF15 FSMC_A9 - K6 - - - - 56 PG0 I/O FT PG0 FSMC_A10 - J6 - - - - 57 PG1 I/O FT PG1 FSMC_A11 - M7 H5 - - 38 58 PE7 I/O FT PE7 FSMC_D4 TIM1_ETR L7 J5 - - 39 59 PE8 I/O FT PE8 FSMC_D5 TIM1_CH1N K7 K5 - - 40 60 PE9 I/O FT PE9 FSMC_D6 TIM1_CH1 H6 - - - - 61 VSS_7 S - VSS_7 - - G6 - - - - 62 VDD_7 S - VDD_7 - - J7 G6 - - 41 63 PE10 I/O FT PE10 FSMC_D7 TIM1_CH2N H8 H6 - - 42 64 PE11 I/O FT PE11 FSMC_D8 TIM1_CH2 J8 J6 - - 43 65 PE12 I/O FT PE12 FSMC_D9 TIM1_CH3N K8 K6 - - 44 66 PE13 I/O FT PE13 FSMC_D10 TIM1_CH3 L8 G7 - - 45 67 PE14 I/O FT PE14 FSMC_D11 TIM1_CH4 M8 H7 - - 46 68 PE15 I/O FT PE15 FSMC_D12 TIM1_BKIN M9 J7 G3 29 47 69 PB10 I/O FT PB10 I2C2_SCL/USART3_TX(9) TIM2_CH3 M10 K7 F3 30 48 70 PB11 I/O FT PB11 I2C2_SDA/USART3_RX(9) TIM2_CH4 H7 E7 H2 31 49 71 VSS_1 S - VSS_1 - - G7 F7 H1 32 50 72 VDD_1 S - VDD_1 - - - - Default Remap M11 K8 G2 33 51 73 PB12 I/O FT PB12 SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK(9)/ TIM1_BKIN(9) M12 J8 G1 34 52 74 PB13 I/O FT PB13 SPI2_SCK/I2S2_CK USART3_CTS(9)/ TIM1_CH1N DS5792 Rev 13 33/143 135 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) L11 H8 F2 35 53 75 PB14 I/O FT PB14 SPI2_MISO/TIM1_CH2N USART3_RTS(9)/ - L12 G8 F1 36 54 76 PB15 I/O FT PB15 SPI2_MOSI/I2S2_SD TIM1_CH3N(9)/ - L9 K9 - - 55 77 PD8 I/O FT PD8 FSMC_D13 USART3_TX K9 J9 - - 56 78 PD9 I/O FT PD9 FSMC_D14 USART3_RX J9 H9 - - 57 79 PD10 I/O FT PD10 FSMC_D15 USART3_CK H9 G9 - - 58 80 PD11 I/O FT PD11 FSMC_A16 USART3_CTS L10 K10 - - 59 81 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS K10 J10 - - 60 82 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 G8 - - - - 83 VSS_8 S - VSS_8 - - F8 - - - - 84 VDD_8 S - VDD_8 - - K11 H10 - - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 K12 G10 - - 62 86 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 J12 - - - - 87 PG2 I/O FT PG2 FSMC_A12 - J11 - - - - 88 PG3 I/O FT PG3 FSMC_A13 - J10 - - - - 89 PG4 I/O FT PG4 FSMC_A14 - H12 - - - - 90 PG5 I/O FT PG5 FSMC_A15 - H11 - - - - 91 PG6 I/O FT PG6 FSMC_INT2 - H10 - - - - 92 PG7 I/O FT PG7 FSMC_INT3 - G11 - - - - 93 PG8 I/O FT PG8 - - G10 - - - - 94 VSS_9 S - VSS_9 - - F10 - - - - 95 VDD_9 S - VDD_9 - - G12 F10 E1 37 63 96 PC6 I/O FT PC6 I2S2_MCK/ TIM8_CH1/SDIO_D6 TIM3_CH1 F12 E10 E2 38 64 97 PC7 I/O FT PC7 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM3_CH2 F11 F9 E3 39 65 98 PC8 I/O FT PC8 TIM8_CH3/SDIO_D0 TIM3_CH3 E11 E9 D1 40 66 99 PC9 I/O FT PC9 TIM8_CH4/SDIO_D1 TIM3_CH4 E12 D9 E4 41 67 100 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1(9)/MCO - 34/143 DS5792 Rev 13 Default Remap STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5. High-density STM32F103xC/D/E pin definitions (continued) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) D12 C9 D2 42 68 101 PA9 I/O FT PA9 USART1_TX(9)/ TIM1_CH2(9) - D11 D10 D3 43 69 102 PA10 I/O FT PA10 USART1_RX(9)/ TIM1_CH3(9) - C12 C10 C1 44 70 103 PA11 I/O FT PA11 USART1_CTS/USBDM CAN_RX(9)/TIM1_CH4(9) - B12 B10 C2 45 71 104 PA12 I/O FT PA12 USART1_RTS/USBDP/ CAN_TX(9)/TIM1_ETR(9) - A12 A10 D4 46 72 105 PA13 I/O FT JTMS-SWDIO - PA13 C11 F8 - - 73 106 G9 E6 B1 47 74 107 VSS_2 S - VSS_2 - - F9 F6 A1 48 75 108 VDD_2 S - VDD_2 - - A11 A9 B2 49 76 109 PA14 I/O FT JTCK-SWCLK - PA14 A10 A8 C3 50 77 110 PA15 I/O FT JTDI SPI3_NSS/ I2S3_WS TIM2_CH1_ET R PA15 / SPI1_NSS B11 B9 A2 51 78 111 PC10 I/O FT PC10 UART4_TX/SDIO_D2 USART3_TX B10 B8 B3 52 79 112 PC11 I/O FT PC11 UART4_RX/SDIO_D3 USART3_RX C10 C8 C4 53 80 113 PC12 I/O FT PC12 UART5_TX/SDIO_CK USART3_CK E10 D8 D8 5 81 114 PD0 I/O FT OSC_IN(10) FSMC_D2(11) CAN_RX D10 E8 D7 6 82 115 PD1 I/O FT OSC_OUT(10) FSMC_D3(11) CAN_TX E9 B7 A3 54 83 116 PD2 I/O FT PD2 TIM3_ETR/UART5_RX SDIO_CMD - D9 C7 - - 84 117 PD3 I/O FT PD3 FSMC_CLK USART2_CTS C9 D7 - - 85 118 PD4 I/O FT PD4 FSMC_NOE USART2_RTS B9 B6 - - 86 119 PD5 I/O FT PD5 FSMC_NWE USART2_TX E7 - - - - 120 VSS_10 S - VSS_10 - - F7 - - - - 121 VDD_10 S - VDD_10 - - A8 C6 - - 87 122 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX A9 D6 - - 88 123 PD7 I/O FT PD7 FSMC_NE1/FSMC_NCE2 USART2_CK E8 - - - - 124 PG9 I/O FT PG9 FSMC_NE2/FSMC_NCE3 - D8 - - - - 125 PG10 I/O FT PG10 FSMC_NCE4_1/ FSMC_NE3 - Default Remap Not connected DS5792 Rev 13 - 35/143 135 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5. High-density STM32F103xC/D/E pin definitions (continued) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Pin name Type(1) I / O Level(2) Pins Main function(3) (after reset) C8 - - - - 126 PG11 I/O FT PG11 FSMC_NCE4_2 - B8 - - - - 127 PG12 I/O FT PG12 FSMC_NE4 - D7 - - - - 128 PG13 I/O FT PG13 FSMC_A24 - C7 - - - - 129 PG14 I/O FT PG14 FSMC_A25 - E6 - - - - 130 VSS_11 S - VSS_11 - - F6 - - - - 131 VDD_11 S - VDD_11 - - B7 - - - - 132 PG15 I/O FT PG15 - - Default Remap A7 A7 A4 55 89 133 PB3 I/O FT JTDO SPI3_SCK / I2S3_CK/ PB3/TRACES WO TIM2_CH2 / SPI1_SCK A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO B6 C5 A5 57 91 135 PB5 I/O - PB5 I2C1_SMBA/ SPI3_MOSI I2S3_SD TIM3_CH2 / SPI1_MOSI C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(9)/ TIM4_CH1(9) USART1_TX D6 A5 C5 59 93 137 PB7 I/O FT PB7 I2C1_SDA(9) / FSMC_NADV / TIM4_CH2(9) USART1_RX D5 D5 A6 60 94 138 BOOT0 I - BOOT0 - - C5 B4 D5 61 95 139 PB8 I/O FT PB8 TIM4_CH3(9)/SDIO_D4 I2C1_SCL/ CAN_RX B5 A4 B6 62 96 140 PB9 I/O FT PB9 TIM4_CH4(9)/SDIO_D5 I2C1_SDA / CAN_TX A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 - A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1 - E5 E5 A7 63 99 143 VSS_3 S - VSS_3 - - F5 F5 A8 64 10 0 144 VDD_3 S - VDD_3 - - 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 36/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. In the WCLSP64 package, the PC3 I/O pin is not bonded and it must be configured by software to output mode (Push-pull) and writing 0 to the data register in order to avoid an extra consumption during low-power modes. 8. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead. 9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 10. For the WCLSP64/LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 11. For devices delivered in LQFP64 packages, the FSMC function is not available. DS5792 Rev 13 37/143 135 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 6. FSMC pin definition FSMC Pins 38/143 NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM LQFP100 BGA100(1) CF CF/IDE PE2 - - A23 A23 - Yes PE3 - - A19 A19 - Yes PE4 - - A20 A20 - Yes PE5 - - A21 A21 - Yes PE6 - - A22 A22 - Yes PF0 A0 A0 A0 - - - PF1 A1 A1 A1 - - - PF2 A2 A2 A2 - - - PF3 A3 - A3 - - - PF4 A4 - A4 - - - PF5 A5 - A5 - - - PF6 NIORD NIORD - - - - PF7 NREG NREG - - - - PF8 NIOWR NIOWR - - - - PF9 CD CD - - - - PF10 INTR INTR - - - - PF11 NIOS16 NIOS16 - - - - PF12 A6 - A6 - - - PF13 A7 - A7 - - - PF14 A8 - A8 - - - PF15 A9 - A9 - - - PG0 A10 - A10 - - - PG1 - - A11 - - - PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 6. FSMC pin definition (continued) FSMC Pins NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM LQFP100 BGA100(1) CF CF/IDE PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 - - A16 A16 CLE Yes PD12 - - A17 A17 ALE Yes PD13 - - A18 A18 - Yes PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 - - A12 - - - PG3 - - A13 - - - PG4 - - A14 - - - PG5 - - A15 - - - PG6 - - - - INT2 - PG7 - - - - INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes PD3 - - CLK CLK - Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 - - NE1 NE1 NCE2 Yes PG9 - - NE2 NE2 NCE3 - PG10 NCE4_1 NCE4_1 NE3 NE3 - - PG11 NCE4_2 NCE4_2 - - - - PG12 - - NE4 NE4 - - PG13 - - A24 A24 - - PG14 - - A25 A25 - - PB7 - - NADV NADV - Yes PE0 - - NBL0 NBL0 - Yes PE1 - - NBL1 NBL1 - Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. DS5792 Rev 13 39/143 135 Memory mapping 4 STM32F103xC, STM32F103xD, STM32F103xE Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map Reserved FSMC register 0xA000 0000 - 0xA000 0FFF FSMC bank4 PCCARD 0x9000 0000 - 0x9FFF FFFF FSMC bank3 NAND (NAND2) 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF Reserved 0x4002 4400 - 0x5FFF FFFF 0x4002 3000 - 0x4002 33FF Reserved 0x4002 2400 - 0x4002 2FFF Flash interface Reserved 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0400 - 0x4002 0FFF DMA2 0x4002 0400 - 0x4002 07FF DMA1 Reserved SDIO 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF Reserved ADC3 USART1 TIM8 SPI1 TIM1 ADC2 0x4001 400 - 0x4001 7FFF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR BKP Reserved BxCAN Shared USB/CAN SRAM 512 bytes USB registers I2C2 I2C1 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 512-Mbyte block 0 Code Option Bytes System memory Reserved Flash Reserved Aliased to Flash or system memory depending on BOOT pins DS5792 Rev 13 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF USART3 USART2 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 2 SPI3/I S3 0x4000 3C00 - 0x4000 3FFF 2S2 0x4000 3800 - 0x4000 3BFF Reserved IWDG 0x4000 3400 - 0x4000 37FF WWDG 0x4000 2C00 - 0x4000 2FFF RTC 0x4000 2800 - 0x4000 2BFF Reserved 0x4000 1800 - 0x4000 27FF TIM7 0x2000 0000 0x1FFF FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF UART4 SPI2/I 512-Mbyte block 1 SRAM 0x4001 2800 - 0x4001 2BFF UART5 Reserved SRAM (64 KB aliased by bit-banding) 0x4002 2000 - 0x4002 23FF Reserved 0x4000 0000 0x3FFF FFFF 40/143 CRC RCC 512-Mbyte block 3 FSMC bank1 & bank2 Reserved 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 512-Mbyte block 2 Peripherals 0x0000 0000 0xA000 1000 - 0xBFFF FFFF 0x4000 3000 - 0x4000 33FF 0x4000 1400 - 0x4000 17FF TIM6 0x4000 1000 - 0x4000 13FF TIM5 0x4000 0C00 - 0x4000 0FFF TIM4 0x4000 0800 - 0x4000 0BFF TIM3 0x4000 0400 - 0x4000 07FF TIM2 0x4000 0000 - 0x4000 03FF 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 ai14753d STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage -#5PIN -#5PIN #P& 6). -36 DS5792 Rev 13 -36 41/143 135 Electrical characteristics 5.1.6 STM32F103xC, STM32F103xD, STM32F103xE Power supply scheme Figure 12. Power supply scheme s d ĂĐŬƵƉĐŝƌĐƵŝƚƌǇ ;K^ϯϮ@ $GGUHVV WY%/B1( )60&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )60&B'>@ W Y1$'9B1( )60&B1$'9 WZ1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. DS5792 Rev 13 67/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK – 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK – 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid th(Data_NWE) tHCLK – 0.5 tHCLK + 1.5 ns tHCLK - ns - 7.5 ns tHCLK - ns - 0 ns tHCLK – 0.5 - ns - tHCLK + 7 ns Data hold time after FSMC_NWE high tHCLK - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 5.5 ns tw(NADV) FSMC_NADV low time - tHCLK + 1.5 ns 1. CL = 15 pF. 2. Guaranteed by characterization results. Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T H.%?./% &3-#?./% T W./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% TH",?./% &3-#?.",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &3-#? !$;= TSU$ATA?./% !DDRESS T V.!$6?.% TH$ATA?./% $ATA TH!$?.!$6 TW.!$6 &3-#?.!$6 AIB 68/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 7tHCLK – 2 7tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3tHCLK – 0.5 3tHCLK + 1.5 ns tw(NOE) FSMC_NOE low time 4tHCLK – 1 4tHCLK + 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns tw(NADV) FSMC_NADV low time th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK - ns th(A_NOE) Address hold time after FSMC_NOE high tHCLK -2 - ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 24 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time 2tHCLK + 25 - ns tHCLK –1.5 tHCLK + 1.5 ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results. DS5792 Rev 13 69/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( WK%/B1:( )60&B1%/>@ 1%/ W Y$B1( W Y'DWDB1$'9 $GGUHVV )60&B$'>@ W Y1$'9B1( WK'DWDB1:( 'DWD WK$'B1$'9 WZ1$'9 )60&B1$'9 DL% Table 34. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Max 5tHCLK – 1 5tHCLK + 2 Unit tw(NE) FSMC_NE low time tv(NWE_NE) FSMC_NEx low to FSMC_NWE low 2tHCLK 2tHCLK + 1 ns tw(NWE) FSMC_NWE low time 2tHCLK – 1 2tHCLK + 2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns tw(NADV) FSMC_NADV low time tHCLK – 1 tHCLK + 1 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK – 3 - ns th(A_NWE) Address hold time after FSMC_NWE high 4tHCLK - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.6 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tHCLK – 1.5 - ns - tHCLK + 1.5 ns tHCLK – 5 - ns tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 15 pF. 2. BGuaranteed by characterization results. 70/143 Min DS5792 Rev 13 ns tHCLK – 1 - ns - 7 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Synchronous waveforms and timings Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 28. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+( ./%, TD#,+, ./%( &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 &3-#?!$;= !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AII DS5792 Rev 13 71/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 8 - ns 2 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Guaranteed by characterization results. 72/143 Min DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 29. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, !$6 &3-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG DS5792 Rev 13 73/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 36. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 3 - ns td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results. 74/143 Min DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+( ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIH Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 27.7 - ns FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 4 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 7 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 - ns th(CLKH-NWAITV) 2 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Guaranteed by characterization results. DS5792 Rev 13 75/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 31. Synchronous non-multiplexed PSRAM write timings %867851 WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\ WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 6 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results. 76/143 Min DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; Figure 32. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&(B )60&B1&(B WK1&([$, WY1&([$ )60&B$>@ WK1&([15(* WK1&([1,25' WK1&([1,2:5 WG15(*1&([ WG1,25'1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG1&(B12( )60&B12( WZ12( WVX'12( WK12(' )60&B'>@ DLE 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. DS5792 Rev 13 77/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 33. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ WK1&(B15(* WK1&(B1,25' WK1&(B1,2:5 WG15(*1&(B WG1,25'1&(B )60&B15(* )60&B1,2:5 )60&B1,25' WG1&(B1:( WZ1:( WG1:(1&(B )60&B1:( )60&B12( 0(0[+,= WG'1:( WY1:(' WK1:(' )60&B'>@ DLE 78/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&(B WY1&(B$ WK1&(B$, )60&B1&(B +LJK )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* )60&B1:( WG1&(B12( WZ12( WG12(1&(B )60&B12( WVX'12( WK12(' )60&B'>@ DLE 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DS5792 Rev 13 79/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* WG1&(B1:( WZ1:( )60&B1:( WG1:(1&(B )60&B12( WY1:(' )60&B'>@ DLE 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access )60&B1&(B )60&B1&(B WK1&(B$, WY1&([$ )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,2:5 WZ1,25' WG1,25'1&(B )60&B1,25' WVX'1,25' WG1,25'' )60&B'>@ DL% 80/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&(B )60&B1&(B WY1&([$ WK1&(B$, )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG1&(B1,2:5 WZ1,2:5 )60&B1,2:5 $77[+,= WY1,2:5' WK1,2:5' )60&B'>@ DLF Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) Symbol Parameter Min Max Unit - 0 ns tv(NCEx-A) tv(NCE4_1-A) FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) th(NCEx-AI) th(NCE4_1-AI) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) 2.5 - ns td(NREG-NCEx) td(NREG-NCE4_1) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid - 5 ns th(NCEx-NREG) th(NCE4_1-NREG) FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid tHCLK + 3 - ns td(NCE4_1-NOE) FSMC_NCE4_1 low to FSMC_NOE low - 5tHCLK + 2 ns tw(NOE) FSMC_NOE low width 8tHCLK –1.5 8tHCLK + 1 ns td(NOE-NCE4_1 FSMC_NOE high to FSMC_NCE4_1 high 5tHCLK + 2 - ns tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 25 - ns th(NOE-D) FSMC_D[15:0] valid data after FSMC_NOE high 15 - ns tw(NWE) FSMC_NWE low width 8tHCLK – 1 8tHCLK + 2 ns td(NWE-NCE4_1) FSMC_NWE high to FSMC_NCE4_1 high 5tHCLK + 2 - ns td(NCE4_1-NWE) FSMC_NCE4_1 low to FSMC_NWE low - 5tHCLK + 1.5 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 11tHCLK - ns td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13tHCLK - ns DS5792 Rev 13 81/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 td(NIORD-NCE4_1) low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high tw(NIORD) FSMC_NIORD low width 1. CL = 15 pF. 2. Guaranteed by characterization results. 82/143 DS5792 Rev 13 Min Max Unit 8tHCLK + 3 - ns - 5tHCLK +1 ns 11tHCLK - ns - 5tHCLK+3ns ns 5tHCLK – 5 - ns - 5tHCLK + 2.5 ns 5tHCLK – 5 - ns 4.5 - ns 9 - ns 8tHCLK + 2 - ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics NAND controller waveforms and timings Figure 38 through Figure 41 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; Figure 38. NAND controller waveforms for read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ )60&B1:( WK12($/( WG$/(12( )60&B12(15( WVX'12( WK12(' )60&B'>@ DLE DS5792 Rev 13 83/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 39. NAND controller waveforms for write access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(1:( WK1:($/( )60&B1:( )60&B12(15( WK1:(' WY1:(' )60&B'>@ AIC Figure 40. NAND controller waveforms for common memory read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(12( WK12($/( )60&B1:( WZ12( )60&B12( WVX'12( WK12(' )60&B'>@ DLE 84/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 41. NAND controller waveforms for common memory write access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(1:( WZ1:( WK1:($/( )60&B1:( )60&B12( WG'1:( WY1:(' WK1:(' )60&B'>@ DLE Table 40. Switching characteristics for NAND Flash read and write cycles(1) Symbol Parameter td(D-NWE)(2) FSMC_D[15:0] valid before FSMC_NWE high tw(NOE)(2) FSMC_NWE low width tsu(D-NOE)(2) FSMC_D[15:0] valid data before FSMC_NOE Min Max Unit 5tHCLK + 12 - ns 4tHCLK-1.5 4tHCLK+1.5 ns 25 - ns 7 - - 4tHCLK-1 4tHCLK+1 ns - 0 ns 2tHCLK + 4 - ns - 3tHCLK + 1.5 ns 3tHCLK + 4.5 - ns - 3tHCLK+ 2 ns 3tHCLK+ 4.5 - ns high th(NOE-D)(2) FSMC_D[15:0] valid data after FSMC_NOE high tw(NWE)(2) FSMC_NWE low width tv(NWE-D) (2) FSMC_NWE low to FSMC_D[15:0] valid (2) FSMC_NWE high to FSMC_D[15:0] invalid th(NWE-D) td(ALE-NWE)(3) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE)(3) FSMC_NWE high to FSMC_ALE invalid td(ALE-NOE) (3) FSMC_ALE valid before FSMC_NOE low (3) FSMC_NWE high to FSMC_ALE invalid th(NOE-ALE) 1. CL = 15 pF. 2. Guaranteed by characterization results. 3. Guaranteed by design. DS5792 Rev 13 85/143 135 Electrical characteristics 5.3.11 STM32F103xC, STM32F103xD, STM32F103xE EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions VFESD VDD = 3.3 V, LQFP144, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Level/ Class VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 72 MHz conforms to IEC 61000-4-4 2B 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. 86/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter SEMI 5.3.12 Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8/48 MHz 8/72 MHz 0.1 to 30 MHz VDD = 3.3 V, TA = 25 °C, 30 to 130 MHz LQFP144 package Peak level compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 8 12 31 21 28 33 4 4 dBµV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 43. ESD absolute maximum ratings Class Maximum value(1) Electrostatic discharge voltage TA = +25 °C, conforming to (human body model) JESD22-A114 2 2000 Electrostatic discharge voltage TA = +25 °C, conforming to VESD(CDM) (charge device model) JESD22-C101 III Symbol VESD(HBM) Ratings Conditions Unit V 500 1. Guaranteed by characterization results. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. DS5792 Rev 13 87/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 44. Electrical sensitivities Symbol LU 5.3.13 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 45 Table 45. I/O current injection susceptibility Functional susceptibility Symbol IINJ 88/143 Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 DS5792 Rev 13 Unit mA STM32F103xC, STM32F103xD, STM32F103xE 5.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46. I/O static characteristics Symbol VIL Parameter Standard IO input low level voltage IO FT(1) input low level voltage Standard IO input high level voltage VIH Vhys Conditions Min Typ Max Unit –0.3 - 0.28*(VDD-2 V)+0.8 V V –0.3 - 0.32*(VDD-2 V)+0.75 V V 0.41*(VDD-2 V)+1.3 V - VDD+0.3 V 0.42*(VDD-2 V)+1 V - 200 - - mV 5% VDD(3) - - mV VSS ≤VIN ≤VDD Standard I/Os - - ±1 VIN= 5 V, I/O FT - - 3 - - IO FT(1) input high level VDD > 2 V voltage VDD ≤2 V Standard IO Schmitt trigger voltage hysteresis(2) Input leakage current (4) V 5.2 - IO FT Schmitt trigger voltage hysteresis(2) Ilkg 5.5 µA RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 kΩ RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 kΩ CIO I/O pin capacitance - - 5 - pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and in Figure 44 and Figure 45 for 5 V tolerant I/Os. DS5792 Rev 13 89/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42. Standard I/O input characteristics - CMOS port 6)(6),6 /3STAN #- 7)(MIN 6 )( 6 6), $$ T6 ),6 $$ RDREQUIREMEN #-/3STANDA )NPUTRANGE NOTGUARANTEED 7),MAX 6 $$ 6 $$ NT6 )( UIREME DARDREQ 6$$6 AIB Figure 43. Standard I/O input characteristics - TTL port 6)(6),6 7)(MIN 44,REQUIREMENTS 6)( 6 6 6 )( $$ )NPUTRANGE NOTGUARANTEED 7),MAX 6 ),6 $$ 44,REQUIREMENTS 6),6 6$$6 AI Figure 44. 5 V tolerant I/O input characteristics - CMOS port 6)(6),6 6 $$ MENTS6 )( )NPUTRANGE NOTGUARANTEED 6 ),6 $$ 6 $$ IRMENT6 ), DARDREQU #-/3STAN 6 )(6 $$ REQUIRE TANDARD #-/3S 6$$6 6$$ AIB 90/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 45. 5 V tolerant I/O input characteristics - TTL port 6)(6),6 44,REQUIREMENT6 )(6 6 $$ 6 )( 7)(MIN 7),MAX )NPUTRANGE NOTGUARANTEED 6 ), 6 $$ 44,REQUIREMENTS6 ),6 6$$6 AI Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time DS5792 Rev 13 Conditions Min Max TTL port(3) IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD–0.4 - - 0.4 2.4 - CMOS port(3) IIO =+ 8mA 2.7 V < VDD < 3.6 V Unit V V 91/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 47. Output voltage characteristics (continued) Symbol Parameter VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Min Max - 1.3 Unit V VDD–1.3 - - 0.4 V VDD–0.4 - 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 4. Guaranteed by characterization results. 92/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48. I/O AC characteristics(1) MODEx[1:0] bit value(1) 10 01 Symbol Parameter fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - Conditions tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time Pulse width of external signals detected by the EXTI controller Min Max Unit - 2 MHz - 125(3) - 125(3) - 10 - 25(3) - 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V - 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V - 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) 10 - CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V ns MHz CL = 50 pF, VDD = 2 V to 3.6 V - ns ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 46. 3. Guaranteed by design. DS5792 Rev 13 93/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 46. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU,2RXW WI,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´ 5.3.15 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 49. NRST pin characteristics Symbol Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage - –0.5 - 0.8 VIH(NRST)(1) NRST Input high level voltage - 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 30 40 50 kΩ - - - 100 ns - 300 - - ns Weak pull-up equivalent resistor(2) RPU VF(NRST) Parameter (1) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse Unit V 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 94/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 47. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 538 1567 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device. 5.3.16 TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit 1 - tTIMxCLK 13.9 - ns Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz Timer resolution - 16 bit 16-bit counter clock 1 period when internal clock fTIMxCLK = 72 MHz 0.0139 is selected 65536 tTIMxCLK 910 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.6 s Timer resolution time fTIMxCLK = 72 MHz - tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. DS5792 Rev 13 95/143 135 Electrical characteristics 5.3.17 STM32F103xC, STM32F103xD, STM32F103xE Communications interfaces I2C interface characteristics The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 51. Refer also to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 51. I2C characteristics Symbol Standard mode I2C(1)(2) Parameter Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode 0 50(4) 0 50(4) μs 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region on the falling edge of SCL. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 96/143 DS5792 Rev 13 µs ns µs STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 48. I2C bus AC waveforms and measurement circuit 9''B,& 53 9''B,& 53 670 56 6'$ ,ð&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX67$ 6'$ WI6'$ WU6'$ WK67$ WVX6'$ WK6'$ WZ6&// 6&/ WZ6&/+ WU6&/ WI6&/ WZ67267$ 6 723 WVX672 DLG 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs: Series protection resistors. 3. Rp: Pull-up resistors. 4. VDD_I2C : I2C bus supply Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. DS5792 Rev 13 97/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53. SPI characteristics Symbol fSCK 1/tc(SCK) Parameter Conditions SPI clock frequency Min Max Master mode - 18 Slave mode - 18 - 8 ns % tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 2tPCLK - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tw(SCKH)(1) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) (1) th(MI) th(SI)(1) ta(SO)(1)(2) tdis(SO) Data input setup time (1)(3) Data input hold time Data output disable time Slave mode 2 10 (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(SO) th(SO)(1) th(MO)(1) Data output hold time Unit MHz 1. Guaranteed by characterization results. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 98/143 DS5792 Rev 13 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 49. SPI timing diagram - slave mode and CPHA = 0 Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68166 &3+$ &32/ &3+$ &32/ WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 %,7287 WU6&. WI6&. WGLV62 /6%287 WK6, WVX6, 026, ,1387 WK166 WF6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS5792 Rev 13 99/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 51. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ 06%,1 WU6&. WI6&. %,7,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 100/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 54. I2S characteristics Symbol DuCy(SCK) Parameter Conditions Min Max Unit 30 70 % 1.522 1.525 Slave mode 0 6.5 I2S slave input clock duty cycle Slave mode Master mode (data: 16 bits, Audio frequency = 48 kHz) fCK 1/tc(CK) I S clock frequency tr(CK) tf(CK) I2S clock rise and fall time Capacitive load CL = 50 pF - 8 tv(WS) (1) WS valid time Master mode 3 - th(WS) (1) WS hold time Master mode I2S2 2 - I2S3 0 - WS setup time Slave mode 4 - WS hold time Slave mode 0 - CK high and low time Master fPCLK= 16 MHz, audio frequency = 48 kHz 312.5 - 345 - tsu(SD_MR) (1) Data input setup time Master receiver I2S2 2 - I2S3 6.5 - tsu(SD_SR) (1) Data input setup time Slave receiver 1.5 - Master receiver 0 - Slave receiver 0.5 - tsu(WS) th(WS) 2 (1) (1) tw(CKH) (1) tw(CKL) (1) th(SD_MR)(1)(2) th(SD_SR) (1)(2) Data input hold time MHz tv(SD_ST) (1)(2) Data output valid time Slave transmitter (after enable edge) - 18 th(SD_ST) (1) Data output hold time Slave transmitter (after enable edge) 11 - tv(SD_MT) (1)(2) Data output valid time Master transmitter (after enable edge) - 3 th(SD_MT) (1) Data output hold time Master transmitter (after enable edge) 0 - ns 1. Guaranteed by design and/or characterization results. 2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. DS5792 Rev 13 101/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 52. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 53. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 102/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 54. SDIO high-speed mode Figure 55. SD default mode #+ T/6$ T/($ $#-$ OUTPUT AI Table 55. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit MHz Clock frequency in data transfer mode CL ≤ 30 pF 0 48 tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 - tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 30 - tr Clock rise time CL ≤ 30 pF - 4 tf Clock fall time CL ≤ 30 pF - 5 fPP DS5792 Rev 13 ns 103/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 55. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF 2 - tIH Input hold time CL ≤ 30 pF 0 - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF - 6 tOH Output hold time CL ≤ 30 pF 0 - ns CMD, D outputs (referenced to CK) in SD default mode(1) tOVD Output valid default time CL ≤ 30 pF - 7 tOHD Output hold default time CL ≤ 30 pF 0.5 - ns 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 56. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time 1. Guaranteed by design. 104/143 DS5792 Rev 13 Max Unit 1 µs STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 57. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V 0.2 - Input levels VDD VDI (4) USB operating voltage(2) - Differential input sensitivity I(USB_DP, USB_DM) VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 - V Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(5) VOH Static output level high RL of 15 kΩ to VSS(5) V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xC/D/E USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by characterization results. 5. RL is the load connected on the USB drivers Figure 56. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 58. USB: full-speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V trfm VCRS Fall Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). DS5792 Rev 13 105/143 135 Electrical characteristics 5.3.18 STM32F103xC, STM32F103xD, STM32F103xE CAN (controller area network) interface Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 59 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: It is recommended to perform a calibration after each power-up. Table 59. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 V VREF+ Positive reference voltage - 2.4 - VDDA V VREF- Negative reference voltage - IVREF Current on the VREF input pin - - 160(1) 220 µA fADC ADC clock frequency - 0.6 - 14 MHz fS(2) Sampling rate - 0.05 - 1 MHz fADC = 14 MHz - - 823 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 and Table 60 for details - - 50 κΩ fTRIG(2) VAIN External trigger frequency Conversion voltage range(3) 0 V RAIN(2) External input impedance RADC(2) Sampling switch resistance - - - 1 κΩ CADC(2) Internal sample and hold capacitor - - - 8 pF tCAL(2) Calibration time fADC = 14 MHz 5.9 µs - 83 1/fADC tlat(2) Injection trigger conversion latency fADC = 14 MHz - - 0.214 µs - - - 3(4) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 14 MHz - - 0.143 µs tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) 106/143 Total conversion time (including sampling time) (4) 1/fADC - - - 2 fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC - 0 0 1 µs fADC = 14 MHz 1 - 18 µs - DS5792 Rev 13 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC STM32F103xC, STM32F103xD, STM32F103xE 1. Electrical characteristics Guaranteed by characterization results. 2. Guaranteed by design. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59. Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 60. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design. Table 61. ADC accuracy - limited test conditions(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration VREF+ = VDDA ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy. 3. Guaranteed by characterization results. DS5792 Rev 13 107/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 62. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy. 4. Guaranteed by characterization results. Figure 57. ADC accuracy characteristics 6 2%& 6 $$! ;,3" )$%!, ORDEPENDINGONPACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AIC 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 108/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 58. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ELW FRQYHUWHU & $'& ,/$ DL 1. Refer to Table 59 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 59 or Figure 60, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA) 670)[[ 95() VHHQRWH )Q) 9''$ )Q) 966$ 95()± VHHQRWH DLE 1. VREF+ and VREF– inputs are available only on 100-pin packages. DS5792 Rev 13 109/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA) 670)[[ 95()9''$ 6HHQRWH )Q) 95()±966$ 6HHQRWH DL 1. VREF+ and VREF– inputs are available only on 100-pin packages. 110/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 Electrical characteristics DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V - RLOAD(1) Resistive load with buffer ON - - kΩ - 5 VREF+ must always be below VDDA Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum resistive load between kΩ DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(1) Capacitive load - - 50 pF DAC_OUT min(1) Lower DAC_OUT voltage with buffer ON 0.2 - - V DAC_OUT max(1) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC_OUT max(1) Higher DAC_OUT voltage with buffer OFF - - VREF+ – 1LSB V IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode) - - 220 µA - - 380 µA With no load, middle code (0x800) on the inputs IDDA DAC DC current consumption in quiescent mode(3) - - 480 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - ±0.5 LSB Given for the DAC in 10-bit configuration - - ±2 LSB Given for the DAC in 12-bit configuration - - ±1 LSB Given for the DAC in 10-bit configuration - - ±4 LSB Given for the DAC in 12-bit configuration RO (2) DNL(4) INL(3) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) DS5792 Rev 13 Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V It gives the maximum output excursion of the DAC. With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 111/143 135 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 63. DAC characteristics (continued) Symbol Min Typ Max Unit Comments - - ±10 mV - - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.5 % Given for the DAC in 12bit configuration Settling time (full scale: for a 10-bit input code transition between the tSETTLING(3) lowest and the highest input codes when DAC_OUT reaches final value ±1LSB - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(3) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/ CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ s tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF Offset(3) Gain error(3) Parameter Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error 1. Guaranteed by design. 2. Guaranteed by characterization. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 61. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 112/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 5.3.21 Electrical characteristics Temperature sensor characteristics Table 64. TS characteristics Symbol Parameter Min Typ Max Unit - ±1 ±2 °C TL VSENSE linearity with temperature Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V25 Voltage at 25 °C 1.34 1.43 1.52 V tSTART(1) Startup time 4 - 10 µs TS_temp(2)(1) ADC sampling time when reading the temperature - - 17.1 µs 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. DS5792 Rev 13 113/143 135 Package information 6 STM32F103xC, STM32F103xD, STM32F103xE Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LFBGA144 package information Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline & 6HDWLQJSODQH GGG & $ $ $ $ $ ' H $%$// 3$'&251(5 ) $%$// 3$'&251(5 % ' $ ) ( ( H $ 0 %277209,(: EEDOOV HHH 0 & $ % III 0 & 7239,(: /)%*$B;B0(B9 1. Drawing is not to scale. Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data inches(1) millimeters Symbol 114/143 Min Typ Max Typ Min Max A(2) - - 1.700 - - 0.0669 A1 0.250 0.300 0.350 0.098 0.0118 0.0138 A2 0.810 0.910 1.010 0.0319 0.0358 0.0398 A3 0.225 0.26 0.295 0.0089 0.0102 0.0116 A4 0.585 0.650 0.715 0.0230 0.0256 0.0281 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Typ Min Max b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 D1 - 8.800 - - 0.3465 - E 9.900 10.000 10.100 0.3898 0.3937 0.3976 E1 - 8.800 - - 0.3465 - e - 0.800 - - 0.0315 - F - 0.600 - - 0.0236 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. STATSChipPAC package dimensions. Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint 'SDG 'VP /)%*$B;B)3B9 Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 mm Dpad 0.400 mm DS5792 Rev 13 115/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) (continued) Dimension Recommended values UBM 0.350 mm Dsm 0.470 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm to 0.125 mm Pad trace width 0.120 mm Ball Diameter 0.400 mm Device marking for LFBGA144 package The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 64. LFBGA144 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) =&+ %DOO $LGHQWLILHU 'DWHFRGH < :: 06Y9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity 116/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 6.2 Package information LFBGA100 package information Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ $ ( H ; $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ( $ ) ' ' H < . EEDOOV HHH 0 = < ; III 0 = %277209,(: 7239,(: +B0(B9 1. Drawing is not to scale. Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.700 - - 0.0669 A1 0.270 - - 0.0106 - - A2 - 0.300 - - 0.0118 - A4 - - 0.800 - - 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 7.200 - - 0.2835 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 1.400 - - 0.0551 - ddd - - 0.120 - - 0.0047 DS5792 Rev 13 117/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline 'SDG 'VP +B)3B9 Table 68. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension 118/143 Recommended values Pitch 0.8 Dpad 0.500 mm Dsm 0.570 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.500 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LFBGA100 package The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 67. LFBGA100 marking example (package top view) $GGLWLRQDO LQIRUPDWLRQ ; 3URGXFWLGHQWLILFDWLRQ 670) 9+ 'DWHFRGH < :: %DOO$ LQGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 119/143 135 Package information 6.3 STM32F103xC, STM32F103xD, STM32F103xE WLCSP64 package information Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline H EEE = ) * $ 'HWDLO$ H H + * ) H $ $ %XPSVLGH 6LGHYLHZ ; ' < %XPS $ HHH = ( E $ 2ULHQWDWLRQ UHIHUHQFH FFF GGG DDD = ; < = = 6HDWLQJSODQH 'HWDLO$ URWDWHG [ :DIHUEDFNVLGH &5B0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the ball. Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data inches(1) millimeters Symbol Min 120/143 Typ Max Min Typ Max A 0.535 0.585 0.635 0.0211 0.0230 0.0250 A1 0.205 0.230 0.255 0.0081 0.0091 0.0100 A2 0.330 0.355 0.380 0.0130 0.0140 0.0150 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data inches(1) millimeters Symbol Min b(2) 0.290 Typ 0.320 Max 0.350 Min Typ Max 0.0114 0.0126 0.0138 e - 0.500 - - 0.0197 - e1 - 3.500 - - 0.1378 - F - 0.447 - - 0.0176 - G - 0.483 - - 0.0190 - D 4.446 4.466 4.486 0.1750 0.1758 0.1766 E 4.375 4.395 4.415 0.1722 0.1730 0.1738 H - 0.250 - - 0.0098 - L - 0.200 - - 0.0079 - eee - 0.05 - - 0.0020 - aaa - 0.10 - - 0.0039 - Number of balls 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum ball diameter parallel to primary datum Z. Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP :/&63B&5B)3B9 Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) Dimension Recommended values Pitch 0.5 Dpad 250 µm Dsm 300 µm Stencil Opening 320 µm DS5792 Rev 13 121/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) (continued) 6.4 Dimension Recommended values Stencil Thickness Between 100 µm to 125 µm Pad trace width 100 µm Ball Diameter 320 µm LQFP144 package information Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*(3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. 122/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Table 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS5792 Rev 13 123/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. 124/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP144 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 72. LQFP144 marking example (package top view) 2SWLRQDOJDWHPDUN 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ ; 670)=(7 'DWHFRGH < :: 3LQLGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 125/143 135 Package information 6.5 STM32F103xC, STM32F103xD, STM32F103xE LQFP100 package information Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline MM C ! ! ! 3%!4).'0,!.% # '!5'%0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 126/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 74. LQFP100 recommended footprint AIC 1. Dimensions are in millimeters. DS5792 Rev 13 127/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Device marking for LQFP100 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 75. LQFP100 marking example (package top view) 2SWLRQDOJDWH PDUN 3URGXFWLGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ sϴdϲ 5HYLVLRQFRGH y 'DWHFRGH z tt 3LQLGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity 128/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 6.6 Package information LQFP64 package information Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not in scale. Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS5792 Rev 13 129/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint AIC 1. Dimensions are in millimeters. 130/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP64 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 78. LQFP64 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ Zdϲ z tt 3LQLGHQWLILHU 'DWHFRGH 06Y9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity DS5792 Rev 13 131/143 135 Package information 6.7 STM32F103xC, STM32F103xD, STM32F103xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 44. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 74. Package thermal characteristics Symbol ΘJA 6.7.1 Parameter Value Thermal resistance junction-ambient LFBGA144 - 10 × 10 mm / 0.8 mm pitch 40 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 30 Thermal resistance junction-ambient LFBGA100 - 10 × 10 mm / 0.8 mm pitch 40 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient WLCSP64 50 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 132/143 DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE 6.7.2 Package information Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 75: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xC, STM32F103xD and STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 74 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 75: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW DS5792 Rev 13 133/143 135 Package information STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table 74 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 75: Ordering information scheme). Figure 79. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 TA (°C) 134/143 DS5792 Rev 13 115 125 135 STM32F103xC, STM32F103xD, STM32F103xE 7 Ordering information Ordering information Table 75. Ordering information scheme Example: STM32 F 103 R C T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS5792 Rev 13 135/143 135 Revision history 8 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 11. LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 38. Values and Figures added to Maximum current consumption on page 62 (see Table 18, Table 19, Table 20 and Table 21 and see Figure 14, Figure 15, Figure 17, Figure 18 and Figure 19). Values added to Typical current consumption on page 73 (see Table 22, Table 23 and Table 24). Table 19: Typical current consumption in Standby mode removed. Note 4 and Note 1 added to Table 65: USB DC electrical characteristics and Table 66: USB: full-speed electrical characteristics on page 129, respectively. VUSB added to Table 65: USB DC electrical characteristics on page 129. Figure 68: Recommended footprint(1) on page 143 corrected. Equation 1 corrected. Figure 73: LQFP100 PD max vs. TA on page 149 modified. Tolerance values corrected in Table 74: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 139. 22-May-2008 136/143 Changes DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 21-Jul-2008 Revision Changes 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 22 modified. Number of complementary channels corrected in Figure 1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram. Power supply supervisor on page 23 modified and VDDA added to Table 14: General operating conditions on page 59. Table notes revised in Section 5: Electrical characteristics. Capacitance modified in Figure 12: Power supply scheme on page 57. Table 60: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated. Table 61: SPI characteristics modified, th(NSS) modified in Figure 49: SPI timing diagram - slave mode and CPHA = 0 on page 123. Minimum SDA and SCL fall time value for Fast mode removed from Table 59: I2C characteristics on page 120, note 1 modified. IDD_VBAT values and some IDD values with regulator in run mode added to Table 21: Typical and maximum current consumptions in Stop and Standby modes on page 68. Table 34: Flash memory endurance and data retention on page 87 updated. tsu(NSS) modified in Table 61: SPI characteristics on page 122. EO corrected in Table 70: ADC accuracy on page 132. Figure 58: Typical connection diagram using the ADC on page 133 and note below corrected. Typical TS_temp value removed from Table 72: TS characteristics on page 137. Section 6.1: Package mechanical data on page 138 updated. Small text changes. DS5792 Rev 13 137/143 142 Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 12-Dec-2008 138/143 Revision Changes 4 Timers specified on page 1 (motor control capability mentioned). Section 2.2: Full compatibility throughout the family updated. Table 6: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page 27 updated. Figure 1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram modified. Note 10 added, main function after reset and Note 5 on page 44 updated in Table 8: High-density STM32F103xx pin definitions. Note 2 modified below Table 11: Voltage characteristics on page 58, |DVDDx| min and |DVDDx| min removed. Note 2 and PD values for LQFP144 and LFBGA144 packages added to Table 14: General operating conditions on page 59. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 62. Max values at TA = 85 °C and TA = 105 °C updated in Table 21: Typical and maximum current consumptions in Stop and Standby modes on page 68. Section 5.3.10: FSMC characteristics on page 87 updated. Data added to Table 50: EMI characteristics on page 111. IVREF added to Table 67: ADC characteristics on page 130. Table 81: Package thermal characteristics on page 146 updated. Small text changes. DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 30-Mar-2009 Revision Changes 5 I/O information clarified on page 1. Figure 4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1. In Table 5: High-density STM32F103xx pin definitions: – I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated – PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column PG14 pin description modified in Table 6: FSMC pin definition. Figure 9: Memory map on page 54 modified. Note modified in Table 18: Maximum current consumption in Run mode, code with data processing running from Flash and Table 20: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 17, Figure 18 and Figure 19 show typical curves (titles changed). Table 25: High-speed external user clock characteristics and Table 26: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 29: HSI oscillator characteristics. FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure 24: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms and Figure 25: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. tw(NADV) values modified in Table 35: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings and Table 39: Asynchronous multiplexed PSRAM/NOR write timings. th(Data_NWE) modified in Table 36: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings In Table 41: Synchronous multiplexed PSRAM write timings and Table 43: Synchronous non-multiplexed PSRAM write timings: – tv(Data-CLK) renamed as td(CLKL-Data) – td(CLKL-Data) min value removed and max value added – th(CLKL-DV) / th(CLKL-ADV) removed Figure 28: Synchronous multiplexed NOR/PSRAM read timings, Figure 29: Synchronous multiplexed PSRAM write timings and Figure 31: Synchronous non-multiplexed PSRAM write timings modified. Figure 52: I2S slave timing diagram (Philips protocol)(1) and Figure 53: I2S master timing diagram (Philips protocol)(1) modified. WLCSP64 package added (see Figure 8: STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side, Table 8: High-density STM32F103xx pin definitions, Figure 65: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and Table 76: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data). Small text changes. DS5792 Rev 13 139/143 142 Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 21-Jul-2009 24-Sep-2009 140/143 Revision Changes 6 Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note 5 updated and Note 4 added in Table 5: High-density STM32F103xC/D/E pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified. fHSE_ext min modified in Table 21: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 modified below Figure 29: Synchronous multiplexed PSRAM write timings. Table 25: HSI oscillator characteristics modified. Conditions removed from Table 27: Low-power mode wakeup timings. Jitter added to Table 28: PLL characteristics. Figure 47: Recommended NRST pin protection modified. In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings: th(BL_NOE) and th(A_NOE) modified. In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: th(A_NWE) and th(Data_NWE) modified. In Table 33: Asynchronous multiplexed PSRAM/NOR read timings: th(AD_NADV) and th(A_NOE) modified. In Table 34: Asynchronous multiplexed PSRAM/NOR write timings: th(A_NWE) modified. In Table 35: Synchronous multiplexed NOR/PSRAM read timings: th(CLKH-NWAITV) modified. In Table 40: Switching characteristics for NAND Flash read and write cycles: th(NOE-D) modified. Table 53: SPI characteristics modified. Values added to Table 54: I2S characteristics and Table 55: SD / MMC characteristics. CADC and RAIN parameters modified in Table 59: ADC characteristics. RAIN max values modified in Table 60: RAIN max for fADC = 14 MHz. Table 71: DAC characteristics modified. Figure 61: 12-bit buffered /nonbuffered DAC added. Figure 63: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and Table 75: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated. 7 Number of DACs corrected in Table 3: STM32F103xx family. IDD_VBAT updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes. Figure 16: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.11: EMC characteristics on page 86. Table 63: DAC characteristics modified. Small text changes. DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 19-Apr-2011 30-Sept-2014 23-Feb-2015 Revision Changes 8 Updated package choice for 103Rx in Table 2 Updated footnotes below Table 7: Voltage characteristics on page 43 and Table 8: Current characteristics on page 43 Updated tw min in Table 21: High-speed external user clock characteristics on page 58 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 61 Updated note 2 in Table 51: I2C characteristics on page 96 Updated Figure 48: I2C bus AC waveforms and measurement circuit Updated Figure 47: Recommended NRST pin protection Updated Section 5.3.14: I/O port characteristics Updated Table 35: Synchronous multiplexed NOR/PSRAM read timings on page 72 Updated FSMC Figure 26 thru Figure 31 Updated Figure 41.: NAND controller waveforms for common memory write access and Figure 48.: I2C bus AC waveforms and measurement circuit Added Section 5.3.13: I/O current injection characteristics Updated Figure 67 and added Table 69: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data on page 120 LQFP64 package mechanical data updated: see Figure 73.: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 73: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data on page 129. 9 Added Note 7 in Table 5: High-density STM32F103xC/D/E pin definitions on page 31. Updated Note 10 in Table 5: High-density STM32F103xC/D/E pin definitions on page 31. Modified Note 2 in Table 62: ADC accuracy on page 108 Modified Note 3 in Table 62: ADC accuracy on page 108 Modified notes in Table 51: I2C characteristics on page 96 Updated Figure 51: SPI timing diagram - master mode(1) on page 100 10 Updated Figure 66.: BGA pad footprint, Figure 70: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline, Figure 73.: LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline, Figure 74.: LQFP100 recommended footprint, Figure 76.: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline, Figure 77.: LQFP64 - 64pin, 10 x 10 mm low-profile quad flat recommended footprint Added Figure 72.: LQFP144 marking example (package top view), Figure 75.: LQFP100 marking example (package top view), Figure 78.: LQFP64 marking example (package top view) Updated Table 72: LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data, Table 73: LQFP64 – 10 x 10 mm 64 pin lowprofile quad flat package mechanical data DS5792 Rev 13 141/143 142 Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 31-08-2015 26-Nov-2015 10-Jul-2018 142/143 Revision Changes 11 Replaced USBDP and USBDM by USB_DP and USB_DM in the whole document. Updated: – Introduction – Reference standard in Table 43: ESD absolute maximum ratings. – Updated IDDA description in Table 63: DAC characteristics. – Section : I2C interface characteristics – Figure 62: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline – Updated sentence before Figure 78: LQFP64 marking example (package top view). – Figure 65: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and sentence before Figure 75: LQFP100 marking example (package top view) – Figure 68: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline – Figure 48: I2C bus AC waveforms and measurement circuit on page 97 – Section 6.1: LFBGA144 package information and Section 6.2: LFBGA100 package information. – Table 20: Peripheral current consumption Added: – Figure 63: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint – Figure 64: LFBGA144 marking example (package top view) – Figure 66: LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline – Figure 69: WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint – Table 66: LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) – Table 68: LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) – Table 70: WLCSP64 recommended PCB design rules (0.5 mm pitch). 12 Updated: – Table 59: ADC characteristics – Table 65: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data – Table 66: LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) Added: – Note 3 on Table 7: Voltage characteristics 13 Updated: – Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts – Section 7: Ordering information DS5792 Rev 13 STM32F103xC, STM32F103xD, STM32F103xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS5792 Rev 13 143/143 143

下载 PDF

STM32F103ZCH6 价格&库存

-> 查询更多价格&库存

很抱歉，暂时无法提供与“STM32F103ZCH6”相匹配的价格&库存，您可以联系我们找货

免费人工找货

搜索历史

STM32F103ZCH6

推荐型号

相关技术文章