STM32F103ZE

STM32F103xC STM32F103xD STM32F103xE Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces Preliminary Data Features FBGA ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division Memories – 256-to-512 Kbytes of Flash memory – up to 64 Kbytes of SRAM – Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration – 32 kHz oscillator for RTC with calibration Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers 3 × 12-bit, 1 µs A/D converters (up to 21 channels) – Conversion range: 0 to 3.6 V – Triple-sample and hold capability – Temperature sensor 2-channel 12-bit D/A converter DMA: 12-channel DMA controller – Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm ■ ■ Up to 112 fast I/O ports – 51/80/112 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs Up to 11 timers – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 2 × 16-bit, 6-channel timers with PWM output and dead-time generation – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC Up to 13 communication interfaces – Up to 2 × I2C interfaces (SMBus/PMBus) – Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed – CAN interface (2.0B Active) – USB 2.0 full speed interface – SDIO interface CRC calculation unit, 96-bit unique ID ECOPACK® packages Device summary Part number STM32F103RC STM32F103VC STM32F103ZC STM32F103RD STM32F103VD STM32F103ZD STM32F103RE STM32F103ZE STM32F103VE ■ ■ ■ ■ ■ ■ ■ Table 1. Reference STM32F103xC STM32F103xD STM32F103xE ■ ■ ■ May 2008 Rev 2 1/118 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 4 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38 Embedded reset and power control block characteristics . . . . . . . . . . . 39 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 83 2/118 STM32F103xC, STM32F103xD, STM32F103xE 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 Contents I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 98 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 114 7 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3/118 List of tables STM32F103xC, STM32F103xD, STM32F103xE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . . 9 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Switching characteristics for CF read and write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 81 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4/118 STM32F103xC, STM32F103xD, STM32F103xE Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. List of tables Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 107 LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . 108 LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . 110 LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . 111 LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5/118 List of figures STM32F103xC, STM32F103xD, STM32F103xE List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . 19 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout. . 21 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout. . 22 STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout. . . 23 STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout . . 24 STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42 Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PC-card controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . 71 PC-card controller timing for common memory write access . . . . . . . . . . . . . . . . . . . . . . . 72 PC-card controller timing for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . 73 PC-card controller timing for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . 74 PC-card controller timing for I/O space read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PC-card controller timing for I/O space write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 NAND controller timing for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 NAND controller timing for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 NAND controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . 80 NAND controller timing for common memory write access. . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. List of figures SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I2S slave timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2S master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 102 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 103 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . 108 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 109 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 110 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7/118 Introduction STM32F103xC, STM32F103xD, STM32F103xE 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE High-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The High-density STM32F103xx datasheet should be read in conjunction with the Mediumand High-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general purpose 16bit timers plus two PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx High-density performance line family operates in the − to +105 °C 40 temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx High-density performance line family offers devices in 5 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx High-density performance line microcontroller family suitable for a wide range of applications: ● ● ● ● ● Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 8/118 STM32F103xC, STM32F103xD, STM32F103xE Description 2.1 Device overview Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts STM32F103Rx 256 48 No Generalpurpose Timers Advancedcontrol Basic SPI(I2S)(1) I2C USART Comm USB CAN SDIO GPIOs 12-bit ADC Number of channels 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Package 51 3 16 1 1 1 80 3 16 1 2 72 MHz 2.0 to 3.6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9) Junction temperature: –40 to + 125 °C (see Table 9) LQFP64 LQFP100(2), BGA100 LQFP144, BGA144 112 3 21 384 64 512 STM32F103Vx 256 48 Yes 4 2 2 3(2) 2 5 384 64 512 STM32F103Zx 256 48 Yes 384 64 512 Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC 1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR Flash memory using the NE1 Chip Select. Bank2 can only support a 16- or 8bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 9/118 Description STM32F103xC, STM32F103xD, STM32F103xE 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x6, STM32F103x8 and STM32F103xB are referred to as Medium-density devices, while the STM32F103xC, STM32F103xD and STM32F103xE are referred to as High-density devices. High-density devices are an extension of the Medium-density STM32F103x6/8/B/C devices specified in the STM32F103xx datasheet. High-density STM32F103xx devices feature higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the family. The STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x6/8/A/B/C devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Table 3. STM32F103xx family Memory size Medium-density STM32F103xx devices Pinout 32 KB Flash 10 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 1 × ADC 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, CAN, 1 × PWM timer 1 × ADC 64 KB Flash 20 KB RAM 128 KB Flash 20 KB RAM High-density STM32F103xx devices 256 KB Flash 48 KB RAM 384 KB Flash 64 KB RAM 512 KB Flash 64 KB RAM 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 1 × DAC, 1 × SDIO FSMC (100- and 144-pin packages(1)) 1. Ports F and G are not available in devices delivered in 100-pin packages. 2.3 Overview ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 10/118 STM32F103xC, STM32F103xD, STM32F103xE Description Embedded Flash memory Up to 512 Kbytes of embedded Flash is available for storing programs and data. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. Embedded SRAM Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: RAM, PSRAM, NOR and NAND. Functionality overview: ● ● ● ● The three FSMC interrupt lines are ORed in order to be connected to the NVIC Write FIFO Code execution from external memory except for The targeted frequency is SYSCLK/2, so external access is at 36 MHz when the system is at 72 MHz and external access is at 24 MHz when the system is at 48 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 11/118 Description STM32F103xC, STM32F103xD, STM32F103xE Nested vectored interrupt controller (NVIC) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● ● ● ● ● ● ● ● Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. Boot modes At startup, boot pins are used to select one of three boot options: ● ● ● Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. 12/118 STM32F103xC, STM32F103xD, STM32F103xE Description Power supply schemes ● ● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. ● For more details on how to connect power pins, refer to Figure 11: Power supply scheme. Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● ● ● MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. 13/118 Description ● STM32F103xC, STM32F103xD, STM32F103xE Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S, SDIO and ADC. RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 14/118 STM32F103xC, STM32F103xD, STM32F103xE Description Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: ● ● ● ● A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source General-purpose timers (TIMx) There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Advanced control timers (TIM1 and TIM8) The two advanced control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for ● ● ● ● ● Input Capture Output Compare PWM generation (edge or center-aligned modes) One-pulse mode output Complementary PWM outputs with programmable inserted dead-times. If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. 15/118 Description STM32F103xC, STM32F103xD, STM32F103xE I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1. 16/118 STM32F103xC, STM32F103xD, STM32F103xE Description Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● ● ● Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 17/118 Description STM32F103xC, STM32F103xD, STM32F103xE DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: ● ● ● ● ● ● ● ● ● ● two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. Temperature sensor The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 18/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 1. Description STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram TRACECLK TRACED[0:3] as AS JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF TPIU SW/JTAG Trace/trig Pbus Ibus Cortex-M3 CPU Fmax: 48/72 MHz Dbus System NVIC Trace controller VDD Flash 512 Kbytes 64 bit @VDD Power Volt. reg. 3.3 V to 1.8 V @VDDA Supply supervision POR /PDR PVD @VDD XTAL OSC 4-16 MHz IWDG Standby interface @VBAT XTAL32kHz RTC Backup reg AWU Backup interface AHB2 APB1 TIM2 TIM3 VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT Flash obl interface VSS Bus Matrix SRAM 64 KB @V DDA RC 8 MHz RC 40 kHz PLL PCLK1 PCLK2 HCLK FCLK POR Reset Int NRST VDDA VSSA GP DMA2 5 channels AHB: Fmax = 48/72 MHz A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL (or NADV) as AF D[7:0] CMD CK as AF GP DMA1 7 channels OSC_IN OSC_OUT FSMC Reset & Clock control SDIO AHB2 APB2 EXT.IT WKUP 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels as AF RX, TX CTS, RTS, , CK as AF RX, TX, CTS, RTS, CK as AF RX,TX as AF RX,TX as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF 112AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] 4 channels 4 compl. channels BKIN as AF 4 channels 4 compl. channels BKIN as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS, CK as AF APB1: Fmax = 24/36 MHz GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G TIM1 TIM8 SPI1 USART1 Temp. sensor SRAM 512 B WWDG TIM4 TIM5 USART2 USART3 UART4 UART5 SPI2 / I2S2 2x(8x16b it) SPI3 / 2x(8x16b I2S3 it) I2C1 I2C2 bxCAN device USB 2.0 FS device APB2: Fmax = 48/72 MHz USBDP/CANTX USBDM/CANRX 8 ADC123_INs common to the 3 ADCs 8 ADC12_INs common to ADC1 & ADC2 5 ADC3_INs on ADC3 VREF– VREF+ TIM6 12-bit ADC1 IF 12-bit ADC2 IF 12-bit ADC3 IF @ VDDA TIM7 IF 12 bit DAC @VDDA DAC_OUT1 as AF DAC_OUT2 as AF VREF+ ai14666 1. TA = –40 °C to +85 °C (suffix 6, see Table 69) or –40 °C to +105 °C (suffix 7, see Table 69), junction temperature up to 105 °C or 125 °C, respectively. 2. AF = alternate function on I/O port pin. 19/118 Description Figure 2. Clock tree STM32F103xC, STM32F103xD, STM32F103xE USB Prescaler /1, 1.5 48 MHz USBCLK to USB interface I2S3CLK Peripheral clock enable to I2S3 I2S2CLK to I2S2 SDIOCLK FSMCCLK to SDIO to FSMC 8 MHz HSI RC HSI Peripheral clock enable Peripheral clock enable /2 Peripheral clock enable 72 MHz max Clock Enable (4 bits) HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock Enable (20 bits) PLLSRC PLLMUL ..., x16 x2, x3, x4 PLL HSI PLLCLK HSE SW SYSCLK /8 72 MHz /1, 2..512 max AHB Prescaler APB1 Prescaler /1, 2, 4, 8, 16 36 MHz max CSS TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2 to TIM2,3,4,5,6 and 7 TIMXCLK Peripheral Clock Enable (6 bits) PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 APB2 Prescaler /1, 2, 4, 8, 16 72 MHz max Peripheral Clock Enable (15 bits) PCLK2 peripherals to APB2 TIM1 & 8 timers If (APB2 prescaler =1) x1 else x2 to TIM1 and TIM8 TIMxCLK Peripheral Clock Enable (2 bit) to ADC1, 2 or 3 /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz LSE to RTC RTCCLK RTCSEL[1:0] ADC Prescaler /2, 4, 6, 8 /2 ADCCLK HCLK/2 LSI RC 40 kHz LSI to Independent Watchdog (IWDG) To SDIO AHB interface Peripheral clock enable IWDGCLK Main Clock Output /2 PLLCLK HSI HSE SYSCLK Legend: HSE = High Speed External clock signal HSI = High Speed Internal clock signal LSI = Low Speed Internal clock signal LSE = Low Speed External clock signal ai14752b MCO MCO 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. 20/118 STM32F103xC, STM32F103xD, STM32F103xE Pin descriptions 3 Figure 3. Pin descriptions STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 VSS_6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 ai14667 21/118 Pin descriptions Figure 4. STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14391 22/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 5. Pin descriptions STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 23/118 Pin descriptions Figure 6. 1 STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout 2 3 4 5 6 7 8 9 10 A PC14PC13OSC32_IN TAMPER-RTC PE2 PB9 PB7 PB4 PB3 PA15 PA14 APA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PCD PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI16001 24/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 7. 1 Pin descriptions STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout 2 3 4 5 6 7 8 9 10 11 12 A PC13TAMPER-RTC PE3 PE2 PE1 PE0 PB4 JTRST PB3 JTDO PD6 PD7 PA15 JTDI PA14 JTCK PA13 JTMS B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 NC PA11 D OSC_IN VSS_5 VDD_5 PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E OSC_OUT PF3 PF4 PF5 VSS_3 VSS_11 VSS_10 PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD_4 VDD_3 VDD_11 VDD_10 VDD_8 VDD_2 VDD_9 PC8 PC7 G PF10 PF9 PF8 VSS_4 VDD_6 VDD_7 VDD_1 VSS_8 VSS_2 VSS_9 PG8 PC6 H PC0 PC1 PC2 PC3 VSS_6 VSS_7 VSS_1 PE11 PD11 PG7 PG6 PG5 J VSSA PA0-WKUP PA4 PC4 PB2/ BOOT1 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF– PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 AI14789b 25/118 Pin descriptions Table 4. Pin definitions Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) STM32F103xC, STM32F103xD, STM32F103xE Alternate functions Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 ADC123_IN10 ADC123_IN11 ADC123_IN12 ADC3_IN4/ FSMC_NIORD ADC3_IN5/ FSMC_NREG ADC3_IN6/ FSMC_NIOWR ADC3_IN7/ FSMC_CD ADC3_IN8/ FSMC_INTR TAMPER-RTC OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 FSMC_A5 Default TRACECK/ FSMC_A23 TRACED0/FSMC_A19 TRACED1/FSMC_A20 TRACED2/FSMC_A21 TRACED3/FSMC_A22 Remap A3 A2 B2 B3 B4 C2 A1 B1 C1 C3 C4 D4 E2 E3 E4 D2 D3 F3 F2 G3 G2 G1 D1 E1 F1 H1 H2 H3 A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(4) I/O I/O I/O I/O I/O S I/O FT FT FT FT FT PC14-OSC32_IN(4) I/O PC15OSC32_OUT(4) PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 I/O I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O I/O I/O I/O I/O I O I/O I/O I/O I/O E2 10 26/118 STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued) Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) Pin descriptions Alternate functions Main function(3) (after reset) PC3 VSSA VREFVREF+ VDDA WKUP/USART2_CTS(6) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR USART2_RTS(6) ADC123_IN1/TIM5_CH2 TIM2_CH2(6) USART2_TX(6)/ TIM5_CH3/ADC123_IN2/ TIM2_CH3 (6) USART2_RX(6)/ TIM5_CH4/ADC123_IN3 TIM2_CH4(6) Default ADC123_IN13 Remap H4 J1 K1 L1 M1 F3 11 G1 12 H1 J1 - 18 19 20 21 22 29 30 31 32 33 PC3 VSSA VREFVREF+ VDDA I/O S S S S K1 13 J2 G2 14 23 34 PA0-WKUP I/O PA0 K2 H2 15 24 35 PA1 I/O PA1 L2 J2 16 25 36 PA2 I/O PA2 M2 G4 F4 J3 K2 17 E4 18 F4 19 G3 20 26 27 28 29 37 38 39 40 PA3 VSS_4 VDD_4 PA4 I/O S S I/O PA3 VSS_4 VDD_4 PA4 SPI1_NSS(6)/DAC_OUT1 USART2_CK(6) ADC12_IN4 SPI1_SCK(6) DAC_OUT2 ADC12_IN5 SPI1_MISO(6) TIM8_BKIN/ADC12_IN6 TIM3_CH1(6) SPI1_MOSI(6) TIM8_CH1N/ADC12_IN7 TIM3_CH2(6) ADC12_IN14 ADC12_IN15 ADC12_IN8/TIM3_CH3 TIM8_CH2N ADC12_IN9 TIM3_CH4(6) TIM8_CH3N TIM1_CH2N TIM1_BKIN K3 H3 21 30 41 PA5 I/O PA5 L3 J3 22 31 42 PA6 I/O PA6 M3 J4 K4 L4 K3 23 G4 24 H4 25 J4 26 32 33 34 35 43 44 45 46 PA7 PC4 PC5 PB0 I/O I/O I/O I/O PA7 PC4 PC5 PB0 TIM1_CH1N M4 J5 K4 27 G5 28 36 37 47 48 PB1 PB2/BOOT1 I/O I/O FT PB1 PB2/BOOT1 TIM1_CH3N 27/118 Pin descriptions Table 4. Pin definitions (continued) Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) STM32F103xC, STM32F103xD, STM32F103xE Alternate functions Main function(3) (after reset) Default FSMC_NIOS16 FSMC_A6 Remap M5 L5 H5 G5 K5 M6 L6 K6 J6 M7 L7 K7 H6 G6 J7 H8 J8 K8 L8 M8 M9 H5 J5 K5 G6 H6 J6 K6 G7 H7 J7 29 38 39 40 41 42 43 44 45 46 47 48 49 50 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 I/O I/O S S I/O I/O I/O I/O I/O I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PE7 PE8 PE9 FSMC_A7 FSMC_A8 FSMC_A9 FSMC_A10 FSMC_A11 FSMC_D4 FSMC_D5 FSMC_D6 TIM1_ETR TIM1_CH1N TIM1_CH1 FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 FSMC_D11 FSMC_D12 I2C2_SCL USART3_TX(6) I2C2_SDA USART3_RX(6) TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4 M10 K7 30 H7 G7 E7 31 F7 32 M11 K8 33 51 73 PB12 I/O FT PB12 SPI2_NSS/I2S2_WS/ I2C2_SMBAl/ USART3_CK(6)/ TIM1_BKIN(6) SPI2_SCK/I2S2_CK USART3_CTS(6)/ TIM1_CH1N SPI2_MISO/TIM1_CH2N USART3_RTS(6) M12 J8 34 52 74 PB13 I/O FT PB13 L11 H8 35 53 75 PB14 I/O FT PB14 28/118 STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued) Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) Pin descriptions Alternate functions Main function(3) (after reset) Default SPI2_MOSI/I2S2_SD TIM1_CH3N(6) FSMC_D13 FSMC_D14 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18 Remap L12 G8 36 L9 K9 J9 H9 K9 J9 H9 G9 - 54 55 56 57 58 59 60 61 62 63 64 65 66 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 PA9 PA10 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PB15 PD8 PD9 PD10 PD11 PD12 PD13 USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 L10 K10 K10 J10 G8 F8 - K11 H10 K12 G10 J12 J11 J10 H12 H11 H10 G11 G10 F10 - PD14 PD15 FSMC_D0 FSMC_D1 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3 TIM4_CH3 TIM4_CH4 G12 F10 37 F12 E10 38 F11 F9 39 E11 E9 40 E12 D9 41 D12 C9 42 D11 D10 43 PC6 PC7 PC8 PC9 PA8 PA9 PA10 I2S2_MCK/ TIM8_CH1/SDIO_D6 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM8_CH3/SDIO_D0 TIM8_CH4/SDIO_D1 USART1_CK/ TIM1_CH1(6)/MCO USART1_TX(6)/ TIM1_CH2(6) USART1_RX(6)/ TIM1_CH3(6) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 67 100 68 101 69 102 29/118 Pin descriptions Table 4. Pin definitions (continued) Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) STM32F103xC, STM32F103xD, STM32F103xE Alternate functions Main function(3) (after reset) Default USART1_CTS/CANRX TIM1_CH4(6)/USBDM USART1_RTS/USBDP/ CANTX(6)/TIM1_ETR(6) PA13 Remap C12 C10 44 B12 B10 45 A12 A10 46 C11 F8 G9 F9 - 70 103 71 104 PA11 PA12 I/O FT I/O FT PA11 PA12 72 105 PA13/JTMS-SWDIO I/O FT JTMS-SWDIO 73 106 74 107 75 108 VSS_2 VDD_2 S S Not connected VSS_2 VDD_2 E6 47 F6 48 A11 A9 49 A10 A8 50 B11 B9 51 B10 B8 52 C10 C8 53 E10 D8 D10 E8 E9 D9 C9 B9 E7 F7 A8 A9 E8 D8 C8 B8 D7 C7 E6 5 6 76 109 PA14/JTCK-SWCLK I/O FT JTCK-SWCLK 77 110 78 111 79 112 80 113 81 114 82 115 83 116 84 117 85 118 86 119 120 121 PA15/JTDI PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S PD6 PD7 JTDI PC10 PC11 PC12 OSC_IN(7) OSC_OUT(7) PD2 PD3 PD4 PD5 PA14 PA15/SPI3_NSS/ I2S3_WS UART4_TX/SDIO_D2 UART4_RX/SDIO_D3 UART5_TX/SDIO_CK FSMC_D2 FSMC_D3 TIM3_ETR/UART5_RX SDIO_CMD FSMC_CLK FSMC_NOE FSMC_NWE USART2_CTS USART2_RTS USART2_TX TIM2_CH1_ETR SPI1_NSS USART3_TX USART3_RX USART3_CK CANRX CANTX B7 54 C7 D7 B6 C6 D6 - 87 122 88 123 124 125 126 127 128 129 130 FSMC_NWAIT FSMC_NE1/ FSMC_NCE2 FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 FSMC_NCE4_2 FSMC_NE4 FSMC_A24 FSMC_A25 USART2_RX USART2_CK 30/118 STM32F103xC, STM32F103xD, STM32F103xE Table 4. Pin definitions (continued) Pins LQFP100 LQFP144 BGA144 BGA100 LQFP64 Pin name Type(1) I / O Level(2) Pin descriptions Alternate functions Main function(3) (after reset) Default Remap F6 B7 A7 - - - 131 132 VDD_11 PG15 PB3/JTDO S I/O I/O FT JTDO PB3/TRACESWO JTDO SPI3_SCK/I2S3_CK/ PB4/SPI3_MISO I2C1_SMBAl/ SPI3_MOSI/I2S3_SD I2C1_SCL(6)/ TIM4_CH1(6) I2C1_SDA(6)/ FSMC_NADV/ TIM4_CH2(6) TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX A7 55 89 133 A6 B6 C6 A6 56 C5 57 B5 58 90 134 91 135 92 136 PB4/JNTRST PB5 PB6 I/O FT I/O I/O FT JNTRST PB5 PB6 D6 D5 C5 B5 A5 A4 E5 F5 A5 59 D5 60 B4 61 A4 62 D4 C4 - 93 137 94 138 95 139 96 140 97 141 98 142 99 143 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 I/O FT I I/O FT I/O FT I/O FT I/O FT S S PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 USART1_RX TIM4_CH3(6)/SDIO_D4 TIM4_CH4(6)/SDIO_D5 TIM4_ETR FSMC_NBL0 FSMC_NBL1 I2C1_SCL/ CANRX I2C1_SDA / CANTX E5 63 F5 64 100 144 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 31/118 Pin descriptions Table 5. Pins CF PE2 PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 A3 A4 A5 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 NIORD NREG NIOWR CD INTR NIOS16 A6 A7 A8 A9 A10 A11 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 A2 CF/IDE STM32F103xC, STM32F103xD, STM32F103xE FSMC pin definition FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit A23 A19 A20 A21 A22 A0 A1 A2 A3 A4 A5 A23 A19 A20 A21 A22 LQFP100 BGA100(1) Yes Yes Yes Yes Yes DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 32/118 STM32F103xC, STM32F103xD, STM32F103xE Table 5. Pins CF PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 NCE4_1 NCE4_2 NCE4_1 NCE4_2 NE4 A24 A25 NADV NBL0 NBL1 NE4 A24 A25 NADV NBL0 NBL1 NOE NWE NWAIT NOE NWE NWAIT D2 D3 D2 D3 D2 D3 CLK NOE NWE NWAIT NE1 NE2 NE3 DA2 DA3 CLK NOE NWE NWAIT NE1 NE2 NE3 D0 D1 D0 D1 D14 D15 CF/IDE D14 D15 Pin descriptions FSMC pin definition (continued) FSMC NOR/PSRAM NOR/SRAM Mux NAND 16 bit D14 D15 A16 A17 A18 D0 D1 A12 A13 A14 A15 INT2 INT3 D2 D3 DA14 DA15 A16 A17 A18 DA0 DA1 D0 D1 D14 D15 CLE ALE LQFP100 BGA100(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NOE NWE NWAIT NCE2 NCE3 Yes Yes Yes Yes Yes Yes Yes Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. 33/118 Memory mapping STM32F103xC, STM32F103xD, STM32F103xE 4 Memory mapping The memory map is shown in Figure 8. Figure 8. Memory map Reserved FSMC register FSMC bank4 PCCARD FSMC bank3 NAND (NAND2) FSMC bank2 NAND (NAND1) FSMC bank1 NOR/PSRAM 4 FSMC bank1 NOR/PSRAM 3 FSMC bank1 NOR/PSRAM 2 FSMC bank1 NOR/PSRAM 1 Reserved CRC Reserved Flash interface Reserved RCC Reserved DMA2 DMA1 Reserved SDIO Reserved ADC3 USART1 TIM8 SPI1 TIM1 ADC2 ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR BKP Reserved BxCAN Shared USB/CAN SRAM 512 bytes USB registers I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2 S3 0xA000 1000 - 0xBFFF FFFF 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF 0x8000 0000 - 0x8FFF FFFF 0x7000 0000 - 0x7FFF FFFF 0x6C00 0000 - 0x6FFF FFFF 0x6800 0000 - 0x6BFF FFFF 0x6400 0000 - 0x67FF FFFF 0x6000 0000 - 0x63FF FFFF 0x4002 4400 - 0x5FFF FFFF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0400 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF 0x4001 400 - 0x4001 7FFF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reserved SRAM (64 KB aliased by bit-banding) Option Bytes System memory Reserved Flash Reserved Aliased to Flash, system memory or SRAM depending on BOOT pins 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF SPI2/I2S2 Reserved IWDG WWDG RTC Reserved TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 ai14753c 34/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5 5.1 Electrical characteristics Test conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage STM32F103xx pin C = 50 pF VIN STM32F103xx pin ai14141 ai14142 35/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.1.6 Power supply scheme Figure 11. Power supply scheme VBAT 1.8-3.6V Po wer swi tch Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 VSS Regulator 5 × 100 nF + 1 × 10 µF VDD VREF 1/2/3/4/5 VDDA VREF+ VREFVSSA ai14125c 10 nF + 1 µF 10 nF + 1 µF ADC Analog: RCs, PLL, ... 5.1.7 Current consumption measurement Figure 12. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 36/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD–VSS VIN |ΔVDDx| |VSSX − VSS| VESD(HBM) Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min –0.3 VSS −0.3 VSS − 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) V Unit 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS. Table 7. Symbol IVDD IVSS IIO Current characteristics Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin Max. 150 150 25 −25 ±5 ±5 ±5 pins)(4) ± 25 mA Unit IINJ(PIN) (2)(3) ΣIINJ(PIN) (2) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin(4) Total injected current (sum of all I/O and control 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. 37/118 Electrical characteristics Table 8. Thermal characteristics STM32F103xC, STM32F103xD, STM32F103xE Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Value –65 to +150 150 Unit °C °C 5.3 5.3.1 Operating conditions General operating conditions Table 9. Symbol fHCLK fPCLK1 fPCLK2 VDD VBAT General operating conditions Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Backup operating voltage LQFP144 Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(1) LQFP100 LQFP64 LFBGA100 LFBGA144 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation(3) Maximum power dissipation Low power dissipation 6 suffix version (3) Conditions Min 0 0 0 2 1.8 Max 72 36 72 3.6 3.6 TBD(2) 434 444 487 TBD(2) Unit MHz V V PD mW –40 –40 –40 –40 –40 –40 85 °C 105 105 °C 125 105 °C 125 TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version 1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 113). 2. TBD = to be determined. 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 113). 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 10 are derived from tests performed under the ambient temperature condition summarized in Table 9. 38/118 STM32F103xC, STM32F103xD, STM32F103xE Table 10. Symbol tVDD Electrical characteristics Operating conditions at power-up / power-down Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit µs/V ∞ ∞ 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11. Symbol Embedded reset and power control block characteristics Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.88 1.84 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV mS VPVD Programmable voltage detector level selection PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge) VPVDhyst (2) PVD hysteresis Power on/power down reset threshold PDR hysteresis VPOR/PDR VPDRhyst TRSTTEMPO(2) Reset temporization 2. Guaranteed by design, not tested in production. 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 39/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.4 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions − °C < TA < +105 °C 40 − °C < TA < +85 °C 40 Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1 Unit V V µs ADC sampling time when TS_vrefint(1) reading the internal reference voltage 1. Shortest sampling time can be determined in the application by multiple iterations. 5.3.5 Supply current characteristics The current consumption is measured as described in Figure 12: Current consumption measurement scheme. Maximum current consumption The MCU is placed under the following conditions: ● ● ● ● ● All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 40/118 STM32F103xC, STM32F103xD, STM32F103xE Table 13. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 °C 69 50 39 27 20 11 37 28 22 16.5 12.5 8 TA = 105 °C 70 50.5 39.5 28 20.5 11.5 37.5 28.5 22.5 17 13 8 mA Symbol IDD Supply current in Run mode 8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 1. Data based on characterization results, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max Parameter Conditions fHCLK 72 MHz(2) 48 all External clock peripherals enabled (1), Symbol Unit TA = 85 °C 66 43.5 33 23 16 9 33 23 18 13 10 6 TA = 105 °C 67 45.5 35 24.5 18 10.5 33.5 23.5 18.5 13.5 10.5 6.5 mA MHz(3) MHz(3) (3) 36 24 MHz 16 MHz(3) IDD Supply current in Run mode External clock(1), all peripherals disabled(3) 8 MHz(3) 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz 8 MHz 1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz. 2. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max, and code executed from RAM. 3. Based on characterization, not tested in production. 41/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 70 60 50 Consumption (mA) 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 40 30 20 10 0 -45 25 70 Temperature (°C) 85 105 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 35 30 25 Consumption (mA) 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 20 15 10 5 0 -45 25 70 Temperature (°C) 85 105 42/118 STM32F103xC, STM32F103xD, STM32F103xE Table 15. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max Parameter Conditions fHCLK TA = 85 °C 72 MHz(2) 48 MHz External clock(1), all peripherals enabled (3) Symbol Unit TA = 105 °C 67 45.5 35 24.5 18 10.5 mA 33.5 23.5 18.5 13.5 10.5 6.5 66 43.5 33 23 16 9 33 23 18 13 10 6 36 MHz(3) 24 MHz(3) (3) 16 MHz IDD Supply current in Sleep mode 8 MHz (3) 72 MHz 48 MHz External clock(1), all peripherals disabled(3) 36 MHz 24 MHz 16 MHz 8 MHz 1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz. 2. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max. 3. Based on characterization, not tested in production. 43/118 Electrical characteristics Table 16. Symbol STM32F103xC, STM32F103xD, STM32F103xE Typical and maximum current consumptions in Stop and Standby modes(1) Typ(2) Parameter Conditions Max Unit VDD/VBAT VDD/VBAT TA = TA = = 2.4 V = 3.3 V 85 °C 105 °C Regulator in main mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no Supply current in independent watchdog) Stop mode Regulator in low-power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator ON, Supply current in (4) independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Backup domain supply current Low-speed oscillator and RTC ON 34.5 35 TBD(3) TBD(3) 24.5 25 TBD(3) TBD(3) IDD 3 2.8 3.8 3.6 TBD TBD 5(5) TBD TBD 6.5(5) µA 1.9 2.1 1.1 1.4 TBD(5) TBD(5) 1. TBD stands for to be determined. 2. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified. 3. Data based on characterization results, tested in production at VDDmax and fHCLK max. 4. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply). 5. Data based on characterization results, not tested in production. 44/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 15. Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values 700 600 500 Consumption (µA) 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V -45 25 70 Temperature (°C) 85 105 100 0 Figure 16. Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 700 600 500 Consumption (µA) 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V -45 25 70 Temperature (°C) 85 105 100 0 45/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 17. Current consumption in Standby mode versus temperature at different VDD values 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -45 25 70 Temperature (°C) 85 105 2.4V 2.7V 3.0V 3.3V 3.6V Typical current consumption The MCU is placed under the following conditions: ● ● ● ● Consumption (µA) All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9. ● Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 46/118 STM32F103xC, STM32F103xD, STM32F103xE Table 17. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Parameter Conditions fHCLK 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) Symbol All peripherals All peripherals disabled enabled(2) 51 34.6 26.6 18.5 12.8 7.2 4.2 2.7 2 1.6 1.3 45 34 26 17.9 12.2 6.6 3.6 2.1 1.4 1 0.7 30.5 20.7 16.2 11.4 8.2 5 3.1 2.1 1.7 1.4 1.2 27 20.1 15.6 10.8 7.6 4.4 2.5 1.5 1.1 0.8 0.6 Unit 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz mA IDD Supply current in Run mode 125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz mA 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 47/118 Electrical characteristics Table 18. STM32F103xC, STM32F103xD, STM32F103xE Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM Typ(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 29.5 20 15.1 10.4 7.2 3.9 2.6 1.85 1.5 1.3 1.2 25.6 19.4 14.5 9.8 6.6 3.3 2 1.25 0.9 0.7 0.6 6.4 4.6 3.6 2.6 2 1.3 1.2 1.15 1.1 1.05 1.05 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz mA 5.1 4 3 2 1.4 0.7 0.6 0.55 0.5 0.45 0.45 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 48/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: ● ● ● all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption – – with all peripherals clocked off with only one peripheral clocked on ● ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Peripheral current consumption(1) Peripheral TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 SPI2 SPI3 Table 19. Typical consumption at 25 °C 1.2 1.2 1.2 1.2 0.4 0.4 0.2 0.2 0.4 0.4 0.5 0.6 0.4 0.4 0.65 0.72 0.72 Unit APB1 USART2 USART3 UART4 UART5 I2C1 I2C2 USB CAN DAC mA 49/118 Electrical characteristics Table 19. STM32F103xC, STM32F103xD, STM32F103xE Peripheral current consumption(1) (continued) Peripheral GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG Typical consumption at 25 °C 0.55 0.72 0.72 0.55 1 0.72 1 Unit APB2 ADC1 ADC2 TIM1 SPI1 TIM8 (2) mA 1.9 1.7 1.8 0.4 1.7 0.9 1.7 USART1 ADC3 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) IL High-speed external (HSE) user clock characteristics Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN Input leakage current VSS ≤VIN ≤VDD 0.7VDD VSS 16 ns 5 ±1 µA Conditions Min Typ 8 Max 25 VDD V 0.3VDD Unit MHz 1. Value based on design simulation and/or technology characteristics. It is not tested in production. 50/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external user clock The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL Low-speed external user clock characteristics Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) VSS ≤VIN ≤VDD 0.7VDD VSS 450 ns 5 ±1 µA Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz OSC32_IN Input leakage current 1. Value based on design simulation and/or technology characteristics. It is not tested in production. Figure 18. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 51/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 19. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t EXTER NAL CLOCK SOURC E fLSE_ext OSC32_IN IL STM32F103xx ai14144b 52/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics High-speed external clock The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. Symbol fOSC_IN RF CL1 CL2(2) i2 gm(4) HSE 4-16 MHz oscillator characteristics(1) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance RS = 30 Ω VDD= 3.3 V VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz kΩ pF 1 mA mA/V ms tSU(HSE)(5) startup time 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. Based on characterization results, not tested in production. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 20. Typical application with a 8-MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx fHSE CL2 ai14145 1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS. 53/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Low-speed external clock The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. Symbol RF CL1 CL2 I2 gm tSU(LSE)(2) LSE oscillator characteristics (fLSE = 32.768 kHz) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(1) LSE driving current Oscillator Transconductance startup time VDD is stabilized RS = 30 kΩ VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit MΩ pF 1.4 µA µA/V s 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE ai14146 54/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. Symbol fHSI HSI oscillator characteristics(1) Parameter Frequency TA = –40 to 105 °C TA = 25°C 1 80 ±1 Conditions Min Typ 8 ±3(2) ±2 2 100 Max Unit MHz % % µs µA ACCHSI Accuracy of HSI oscillator tsu(HSI) IDD(HSI) HSI oscillator start up time HSI oscillator power consumption 1. VDD = 3.3 V, TA = − to 105 °C unless otherwise specified. 40 2. Values based on device characterization, not tested in production. LSI low speed internal RC oscillator Table 25. Symbol fLSI tsu(LSI) IDD(LSI) LSI oscillator characteristics (1) Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 Conditions Min(2) 30 Typ 40 Max 60 85 1.2 Unit kHz µs µA 1. VDD = 3 V, TA = − to 105 °C unless otherwise specified. 40 2. Value based on device characterization, not tested in production. 55/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● ● Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26. Symbol Low-power mode wakeup timings Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 µs HSI RC wakeup time = 2 µs, Regulator wakeup from LP mode time = 5 µs HSI RC wakeup time = 2 µs, Regulator wakeup from power down time = 38 µs Typ 1.8 3.6 µs 5.4 Unit µs tWUSLEEP(1) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(1) Wakeup from Stop mode (regulator in low power mode) tWUSTDBY(1) Wakeup from Standby mode 50 µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. Symbol PLL characteristics Value Parameter PLL input clock Test conditions Min Typ 8.0 40 16 60 72 200 Max(1) Unit MHz % MHz µs fPLL_IN fPLL_OUT tLOCK PLL input clock duty cycle PLL multiplier output clock PLL lock time 1. Data based on device characterization, not tested in production. 56/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = − to 105 °C unless otherwise specified. 40 Table 28. Symbol tprog tERASE tME Flash memory characteristics Parameter Word programming time Page (2 KB) erase time Mass erase time Conditions TA = − to +105 °C 40 TA = − to +105 °C 40 TA = − to +105 °C 40 Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V Min 40 20 20 Typ 52.5 Max(1) 70 40 40 28 Unit µs ms ms mA IDD Supply current Write mode fHCLK = 72 MHz, VDD = 3.3 V Erase mode fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V 7 5 50 2 3.6 mA mA µA V Vprog Programming voltage 1. Values based on characterization and not tested in production. Table 29. Symbol NEND tRET Flash memory endurance and data retention Value Parameter Endurance TA = 85 °C, 1000 cycles Data retention TA = 105 °C, 1000 cycles Conditions Min(1) TBD(2) 30 Years 10 Unit Typ Max kcycles 1. Values based on characterization not tested in production. 2. TBD = to be determined. 57/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.10 FSMC characteristics All the timing characteristics are relative to the FSMC_CLK signal for synchronous SRAM/NOR Flash memory accesses. Figure 22. Asynchronous non-multiplexed SRAM/NOR write timings tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] Address th(A_NWE) tv(BL_NE) FSMC_NBL[3:0] tv(Data_NE) NBL th(BL_NWE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. Table 30. Asynchronous non-multiplexed SRAM/NOR write timings(1) VDD_IO = V and CL = 15 pF Symbol tw(NE) tv(WEN_NE) tw(NWE) th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE) th(BL_NWE) tv(Data_NE) th(Data_NWE) tv(NADV_NE) tw(NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high FSMC_NEx low to Data valid Data hold time after FSMC_NWE high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time Min TBD TBD TBD TBD Max TBD TBD TBD Unit tCK/ns tCK/ns tCK/ns tCK/ns TBD TBD TBD TBD TBD TBD TBD TBD ns tCK/ns ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns 1. TBD = to be determined. 58/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 23. Asynchronous non-multiplexed SRAM/NOR read timings tw(NE) FSMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FSMC_NOE FSMC_NWE tv(A_NE) FSMC_A[25:0] Address t h(A_NOE) tv(BL_NE) FSMC_NBL[3:0] NBL t h(BL_NOE) t h(Data_NE) t su(Data_NOE) t su(Data_NE) th(Data_NOE) FSMC_D[15:0] t v(NADV_NE) tw(NADV) Data FSMC_NADV(1) ai14991 1. Mode 2/B, C and D only. Table 31. Asynchronous non-multiplexed SRAM/NOR read timings(1) VDD_IO = V and CL = 15 pF Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) tv(BL_NE) th(BL_NOE) tsu(Data_NE) tsu(Data_NOE) th(Data_NOE) th(Data_NE) tv(NADV_NE) tw(NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NOE high Data to FSMC_NEx high setup time Data to FSMC_NOEx high setup time Data hold time after FSMC_NOE high Data hold time after FSMC_NEx high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time Min TBD TBD TBD TBD Max TBD TBD TBD Unit tCK/ns tCK/ns tCK/ns tCK/ns TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns tCK/ns ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns 1. TBD = to be determined. 59/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 24. Asynchronous multiplexed SRAM/NOR write timings twNE FSMC_NEx FSMC_NOE tv(NWE_NE) tw(WENL) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address th(A_NWE) tv(BL_NE) FSMC_NBL[3:0] t v(A_NE) NBL th(BL_NWE) tv(Data_NL) Data th(Data_NW) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NADV tdis(AD_NADV) ai14891 Table 32. Asynchronous multiplexed SRAM/NOR write timings(1) FSMC - Asynchronous multiplexed SRAM/NOR write timings VDD_IO = V and CL = 15 pF Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NE low time Parameter Min TBD TBD TBD TBD Max TBD TBD TBD Unit tCK/ns tCK/ns tCK/ns tCK/ns FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns tCK/ns tdis(AD_NADV) FSMC_AD (address) disable time after FSMC_NADV high th(A_NWE) tv(BL_NE) th(BL_NWE) Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. TBD = to be determined. 60/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 25. Asynchronous multiplexed SRAM/NOR read timings tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address t h(A_NOE) tv(BL_NE) FSMC_NBL[3:0] NBL th(BL_NOE) th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Data th(Data_NOE) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) tdis(AD_NADV) FSMC_NADV ai14892 61/118 Electrical characteristics Table 33. STM32F103xC, STM32F103xD, STM32F103xE Asynchronous multiplexed SRAM/NOR read timings VDD_IO = V and CL = 15 pF Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_WEN) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NE low time Parameter Min TBD TBD TBD TBD TBD Max TBD TBD TBD Unit tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_WEN high to FSMC_NE high hold time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns tCK/ns ns tCK/ns tCK/ns ns ns tdis(AD_NADV) FSMC_AD (address) disable time after FSMC_NADV high th(A_NOE) th(BL_NOE) tv(BL_NE) tsu(Data_NE) Address hold time after FSMC_NOE high FSMC_BL hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid Data to FSMC_NEx high setup time tsu(Data_NOE) Data to FSMC_NOE high setup time th(Data_NE) th(Data_NOE) Data hold time after FSMC_NEx high Data hold time after FSMC_NOE high 62/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 26. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) FSMC_CLK tw(CLK) Data latency = 1 td(CLKH-NExL) FSMC_NEx td(CLKH-NADVL) FSMC_NADV td(CLKH-AV) FSMC_A[24:16] td(CLKH-NWEH) FSMC_NWE td(CLKH-NOEL) FSMC_NOE td(CLKH-ADIV) td(CLKH-ADV) FSMC_AD[15:0] AD[15:0] tsu(NWAITV-CLKH) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) D1 D2 th(CLKH-NWAITV) td(CLKH-NADVH) td(CLKH-NExH) td(CLKH-AIV) td(CLKH-NWEL td(CLKH-NOEH) th(CLKH-ADV) ai14893 63/118 Electrical characteristics Table 34. STM32F103xC, STM32F103xD, STM32F103xE Synchronous multiplexed NOR/PSRAM read timings(1) VDD_IO = V and CL = 15 pF Symbol tw(CLK) td(CLKH-NExL) td(CLKH-NExH) td(CLKH-NADVL) td(CLKH-NADVH) td(CLKH-AV) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NWEH) td(CLKH-NOEL) td(CLKH-NOEH) td(CLKH-ADV) td(CLKH-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITVCLKH) Parameter FSMC_CLK period FSMC_CLK high to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK high to FSMC_NADV low FSMC_CLK high to FSMC_NADV high FSMC_CLK high to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK high to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK high to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_CLK high to FSMC_AD[15:0] valid FSMC_CLK high to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid data before FSMC_CLK high FSMC_A/D[15:0] valid data after FSMC_CLK high FSMC_NWAIT valid before FSMC_CLK high Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. TBD = to be determined. 64/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Synchronous multiplexed PSRAM write timings tw(CLK) FSMC_CLK Data latency = 1 td(CLKH-NExL) FSMC_NEx td(CLKH-NADVL) FSMC_NADV td(CLKH-AV) FSMC_A[24:16] td(CLKH-NWEH) FSMC_NWE td(CLKH-NOEL) FSMC_NOE td(CLKH-ADIV) td(CLKH-ADV) FSMC_AD[15:0] tv(Data-CLK) AD[15:0] D1 td(CLKH-NADVH) tw(CLK) Electrical characteristics BUSTURN = 0 td(CLKH-NExH) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NOEH) th(CLKH-ADV) th(CLKH-ADV) D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14992 65/118 Electrical characteristics Table 35. STM32F103xC, STM32F103xD, STM32F103xE Synchronous multiplexed PSRAM write timings(1) VDD_IO = V and CL = 15 pF Symbol tw(CLK) td(CLKH-NExL) td(CLKH-NExH) td(CLKH-NADVL) td(CLKH-NADVH) td(CLKH-AV) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NWEH) td(CLKH-NOEL) td(CLKH-NOEH) td(CLKH-ADV) td(CLKH-ADIV) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tv(Data-CLK) FSMC_CLK period Parameter Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FSMC_CLK high to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK high to FSMC_NADV low FSMC_CLK high to FSMC_NADV high FSMC_CLK high to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK high to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK high to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_CLK high to FSMC_AD[15:0] valid FSMC_CLK high to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid data after FSMC_CLK high FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK high to FSMC_CLK valid 1. TBD = to be determined. 66/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) FSMC_CLK td(CLKH-NExL) FSMC_NEx td(CLKH-NADVL) FSMC_NADV td(CLKH-AV) FSMC_A[24:0] td(CLKH-NWEH) FSMC_NWE td(CLKH-NOEL) FSMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FSMC_D[15:0] tsu(NWAITV-CLKH) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893 tw(CLK) BUSTURN = 0 Data latency = 1 td(CLKH-NExH td(CLKH-NADVH) td(CLKH-AIV) td(CLKH-NWEL td(CLKH-NOEH) th(CLKH-DV) D2 D1 th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) 67/118 Electrical characteristics Table 36. STM32F103xC, STM32F103xD, STM32F103xE Synchronous non-multiplexed NOR/PSRAM read timings(1) VDD_IO = V and CL = 15 pF Symbol tw(CLK) td(CLKH-NExL) td(CLKH-NExH) td(CLKH-NADVL) td(CLKH-NADVH) td(CLKH-AV) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NWEH) td(CLKH-NOEL) td(CLKH-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) FSMC_CLK period Parameter Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FSMC_CLK high to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK high to FSMC_NADV low FSMC_CLK high to FSMC_NADV high FSMC_CLK high to FSMC_Ax valid (x = 0...25) FSMC_CLK high to FSMC_Ax invalid (x = 0...25) FSMC_CLK high to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK high to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_D[15:0] valid data before FSMC_CLK high FSMC_D[15:0] valid data after FSMC_CLK high FSMC_NWAIT valid before FSMC_SMCLK high FSMC_NWAIT valid after FSMC_CLK high 1. TBD = to be determined. 68/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 29. Synchronous non-multiplexed PSRAM write timings tw(CLK) FSMC_CLK td(CLKH-NExL) FSMC_NEx td(CLKH-NADVL) FSMC_NADV td(CLKH-AV) FSMC_A[24:0] td(CLKH-NWEH) FSMC_NWE td(CLKH-NOEL) FSMC_NOE tv(Data-CLK) FSMC_D[15:0] th(CLKH-DV) D1 D2 th(CLKH-DV) td(CLKH-NOEH) td(CLKH-NWEL) td(CLKH-AIV) td(CLKH-NADVH) Data latency = 1 td(CLKH-NExH) tw(CLK) BUSTURN = 0 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14993 69/118 Electrical characteristics Table 37. STM32F103xC, STM32F103xD, STM32F103xE Synchronous non-multiplexed PSRAM write timings(1) VDD_IO = V and CL = 15 pF Symbol tw(CLK) td(CLKH-NExL) td(CLKH-NExH) td(CLKH-NADVL) td(CLKH-NADVH) td(CLKH-AV) td(CLKH-AIV) td(CLKH-NWEL) td(CLKH-NWEH) td(CLKH-NOEL) td(CLKH-NOEH) tsu(DV-CLKH) th(CLKH-DV) tv(Data-CLK) FSMC_CLK period Parameter Min TBD x TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FSMC_CLK high to FSMC_NEx low (x = 0...2) FSMC_CLK high to FSMC_NEx high (x = 0...2) FSMC_CLK high to FSMC_NADV low FSMC_CLK high to FSMC_NADV high FSMC_CLK high to FSMC_Ax valid (x = 16...25) FSMC_CLK high to FSMC_Ax invalid (x = 16...25) FSMC_CLK high to FSMC_NWE low FSMC_CLK high to FSMC_NWE high FSMC_CLK high to FSMC_NOE low FSMC_CLK high to FSMC_NOE high FSMC_D[15:0] valid data before FSMC_CLK high FSMC_D[15:0] valid data after FSMC_CLK high FSMC_CLK high to FSMC_CLK valid th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. TBD = to be determined. 70/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 30. PC-card controller timing for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 tv(NCEx-A) FSMC_A[10:0] td(NREG-NCEx) td(NIORD-NCEx) td(NIOWR-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) th(NCEx-AI) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0] td(NOE-NWAITH) td(NOE-NWAITL) FSMC_NWAIT (PWAITEN = 1b) td(NWAIT-NOE) th(NOE-D) tsu(D-NIORD) ai14895 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. 71/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 31. PC-card controller timing for common memory write access FSMC_NCE4_2(1) FSMC_NCE4_1 tv(NCEx-A) FSMC_A[10:0] td(NREG-NCEx) td(NIORD-NCEx) td(NIOWR-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCEx-NWE) FSMC_NWE th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) th(NCEx-AI) tw(NWE) td(NWE-NCEx) FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) FSMC_D[15:0] td(NWE-NWAITH) td(NWE-NWAITL) FSMC_NWAIT (PWAITEN = 1b) ai14896 td(NWAIT-NWE) th(NWE-D) 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. 72/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 32. PC-card controller timing for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 High th(NCE4_1-AI) FSMC_A[10:0] td(NIORD-NCE4_1) td(NIOWR-NCE4_1) FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) FSMC_NREG th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0](1) td(NOE-NWAITH) td(NOE-NWAITL) FSMC_NWAIT (PWAITEN = 1b) ai14897 th(NOE-D) tw(NOE) td(NOE-NCE4_1) td(NWAIT-NOE) 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 73/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 33. PC-card controller timing for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] td(NIORD-NCE4_1) td(NIOWR-NCE4_1) FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) FSMC_NREG td(NCE4_1-NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) td(NWE-NWAITH) td(NWE-NWAITl) FSMC_NWAIT (PWAITEN = 1b) ai14898 td(NWAIT-NWE) th(NCE4_1-D) tw(NWE) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). 74/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 34. PC-card controller timing for I/O space read access FSMC_NCE4_1 tv(NCEx-A) FSMC_A[10:0] th(NCE4_1-AI) FSMC_NCE4_2 FSMC_NREG FSMC_NWE FSMC_NOE assumes same level as FSMC_NIOS16(1) tELIWL FSMC_NIOWR td(NCE4_1-NIORD) FSMC_NIORD tsu(D-NIORD) FSMC_D[15:0](2) td(NCE4_1-NIOIS16) tAVISL/H(3) FSMC_NIOIS16 ai14899 th(NIORD-D) tw(NIORD) 1. FSMC_NCE4_2 is high independently of FSMC_NIOIS16 if the AHB transfer is for one byte. 2. Only data bits 0...7 are read (bits 8...15 are disregarded) if FSMC_NIOIS16 is high. 3. The CF card asserts FSMC_NIOIS16 after tAVISL/H. 4. FSMC_NWAIT not shown but behaves as in the previous figures. 75/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC-card controller timing for I/O space write access FSMC_NCE4_1 tv(NCEx-A) FSMC_A[10:0] th(NCE4_1-AI) FSMC_NCE4_2 assumes same level as FSMC_NIOS16(1) FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) FSMC_D[15:0](2) tAVISL/H(3) td(NCE4_1-NIOIS16) FSMC_NIOIS16 th(NIOWR-D) tw(NIOWR) ai14900 1. FSMC_NCE4_2 is high independently of FSMC_NIOIS16 if the AHB transfer is for one byte. 2. Only data bits 0...7 are driven (bits 8...15 remains HiZ) if FSMC_NIOIS16 is high. 3. The CF card asserts FSMC_NIOIS16 after tAVISL/H. 4. FSMC_NWAIT not shown but behaves as in the previous figures. 76/118 STM32F103xC, STM32F103xD, STM32F103xE Table 38. Symbol Electrical characteristics Switching characteristics for CF read and write cycles(1) Timing Parameter Min Max FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 low to FSMC_NIORD valid FSMC_NCEx high to FSMC_NIORD invalid FSMC_NCE4_1 high to FSMC_NIORD invalid FSMC_NIOWR valid to FSMC_NCEx low FSMC_NIOWR valid to FSMC_NCE4_1 low FSMC_NCEx high to FSMC_NIOWR invalid FSMC_NCE4_1 high to FSMC_NIOWR invalid FSMC_D[15:0] valid before FSMC_NIORD high FSMC_D[15:0] valid after FSMC_NIORD high FSMC_D[15:0] valid before FSMC_NWE high FSMC_NCE4_1 low to FSMC_NIOWR valid FSMC_NIOWR low width FSMC_NIOWR low to FSMC_D[15:0] valid FSMC_NIOWR high to FSMC_D[15:0] invalid TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns cycles/ns Unit tv(NCEx-A) tv(NCE4_1-A) - TBD ns th(NCEx-AI) th(NCE4_1-AI) td(NREG-NCEx) td(NREG-NCE4_1) th(NCEx-NREG) th(NCE4_1-NREG) td(NIORD-NCEx) td(NIORD-NCE4_1) th(NCEx-NIORD) th(NCE4_1-NIORD) td(NIOWR-NCEx) td(NIOWR-NCE4_1) th(NCEx-NIOWR) th(NCE4_1-NIOWR) tsu(D-NIORD) td(NIORD-D) td(D-NWE) td(NCE4_1-NIOWR) tw(NIOWR) tv(NIOWR-D) th(NIOWR-D) TBD - ns TBD TBD TBD TBD - ns ns ns ns td(NCE4_1-NIOIS16) FSMC_NIOS16 valid after FSMC_NCE4_1 low td(NCE4_1-NOE) tw(NOE) td(NOE-NCEx) td(NOE-NCE4_1 td(NOE-NWAITL) td(NOE-NWAITH) td(NWAIT-NOE) tsu(D-NOE) th(NOE-D) FSMC_NCE4_1 low to FSMC_NOE low FSMC_NOE low width FSMC_NOE high to FSMC_NCEx high FSMC_NOE high to FSMC_NCE4_1 high FSMC_NWAIT low after FSMC_NOE low(2) FSMC_NWAIT high after FSMC_NOE low(2) FSMC_NOE high after FSMC_NWAIT high FSMC_D[15:0] valid data before FSMC_NOE high FSMC_D[15:0] valid data after FSMC_NOE high 77/118 Electrical characteristics Table 38. Symbol td(NCEx-NWE) tw(NWE) td(NWE-NCEx) td(NWE-NCE4_1) td(NCE4_1-NWE) td(NWE-NWAITL) td(NWE-NWAITH) td(NWAIT-NWE) tv(NWE-D) th(NWE-D) th(NCE4_1-D) tw(NIORD) tELIWL tAVISL/H STM32F103xC, STM32F103xD, STM32F103xE Switching characteristics for CF read and write cycles(1) (continued) Timing Parameter Min FSMC_NCEx low to FSMC_NWE low FSMC_NWE low width FSMC_NWE high to FSMC_NCEx high FSMC_NWE high to FSMC_NCE4_1 high FSMC_NCE4_1 low to FSMC_NWE low FSMC_NWAIT low after FSMC_NWE low (2) (2) Unit Max TBD TBD ns cycles/ns ns ns TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns 35 ns TBD TBD FSMC_NWAIT high after FSMC_NWE low FSMC_NWE high after FSMC_NWAIT high FSMC_NWE low to FSMC_D[15:0] valid FSMC_NWE high to FSMC_D[15:0] invalid FSMC_NCE4_1 high to FSMC_D[15:0] invalid FSMC_NIORD low width FSMC_NCEx setup before FSMC_NWE low Address valid to FSMC_NIOIS16 valid 1. TBD = to be determined. 2. When one or more wait states are inserted. If no wait state needs inserted, NWAIT should be kept high or the wait feature should be disabled (WAITEN=0) in the control register. 78/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 36. NAND controller timing for read access Electrical characteristics FSMC_NCEx tv(NCEx-A) ALE (FSMC_A17) CLE (FSMC_A16) th(NCEx-AI) FSMC_NWE td(NCEx-NOE) FSMC_NOE (NRE) tsu(D-NOE) FSMC_D[15:0] td(NOE-NWAITL) td(NOE-NWAITH) FSMC_NWAIT (PWAITEN = 1b) ai14901 td(NWAIT-NOE) th(NOE-D) Figure 37. NAND controller timing for write access FSMC_NCEx tv(NCEx-A) ALE (FSMC_A17) CLE (FSMC_A16) td(NCEx-NWE) FSMC_NWE td(NWE-NCEx) FSMC_NOE (NRE) MEMxHIZ =1 tv(NWE-D) FSMC_D[15:0] td(NWE-NWAITH) td(NWE-NWAITL) FSMC_NWAITW (PWAITEN = 1b) ai14902 td(NWAIT-NWE) th(NWE-D) th(NCEx-AI) 79/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 38. NAND controller timing for common memory read access FSMC_NCEx tv(NCEx-A) ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) FSMC_D[15:0] td(NOE-NWAITH) td(NOE-NWAITL) FSMC_NWAIT (PWAITEN = 1b) td(NWAIT-NOE) th(NOE-D) tw(NOE) tiv(NCEx-AI) ai14912 Figure 39. NAND controller timing for common memory write access FSMC_NCEx tv(NCEx-A) ALE (FSMC_A17) CLE (FSMC_A16) tw(NWE) FSMC_NWE td(NWE-NCEx) th(NCEx-AI) FSMC_NOE MEMxHIZ =1 td(D-NWE) td(NWE-D) FSMC_D[15:0] td(NWE-NWAITH) td(NWE-NWAITL) FSMC_NWAIT (PWAITEN = 1b) ai14913 td(NWAIT-NWE) th(NWE-D) 80/118 STM32F103xC, STM32F103xD, STM32F103xE Table 39. Symbol tv(NCEx-A) th(NCEx-AI) td(D-NWE) td(NWE-D) td(NCEx-NOE) tw(NOE) th(NWE-D) td(NOE-NWAITL) Electrical characteristics Switching characteristics for NAND Flash read and write cycles(1) Timing Parameter Min FSMC_NCEx low (x = 2/3) to FSMC_Ay valid (y = 16/17) FSMC_NCEx high (x = 2/3) to FSMC_Ax invalid (x = 16/17) FSMC_D[15:0] valid before FSMC_NWE high FSMC_D[15:0] valid after FSMC_NWE high FSMC_NCEx low to FSMC_NOE low FSMC_NOE low width FSMC_NWE high to FSMC_D[15:0] invalid FSMC_NWAIT low after FSMC_NOE low(2) low(2) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns cycles/ns ns ns ns ns ns ns TBD TBD TBD TBD TBD Max TBD TBD TBD ns ns ns ns ns cycles/ns ns Unit td(NOE-NWAITH) FSMC_NWAIT high after FSMC_NOE td(NWAIT-NOE) tsu(D-NOE) th(NOE-D) td(NCEx-NWE) tw(NWE) td(NWE-NCEx) FSMC_NOE high after FSMC_NWAIT high FSMC_D[15:0] valid data before FSMC_NOE high FSMC_D[15:0] valid data after FSMC_NOE high FSMC_NCEx low to FSMC_NWE low FSMC_NWE low width FSMC_NWE high to FSMC_NCEx high td(NWE-NWAITL) FSMC_NWAIT low after FSMC_NWE low(2) td(NWE-NWAITH) FSMC_NWAIT high after FSMC_NWE td(NWAIT-NWE) tv(NWE-D) th(NWE-D) low(2) FSMC_NWE high after FSMC_NWAIT high FSMC_NWE low to FSMC_D[15:0] valid FSMC_NWE high to FSMC_D[15:0] invalid 1. TBD = to be determined. 2. When one or more wait states are inserted. If no wait state needs inserted, NWAIT should be kept high or the wait feature should be disabled (WAITEN=0) in the control register. 81/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 40. They are based on the EMS levels and classes defined in application note AN1709. Table 40. Symbol EMS characteristics Parameter Conditions Level/ Class 2B VFESD VDD = 3.3 V, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK=48 MHz induce a functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 48 MHz conforms to IEC 1000-4-4 VEFTB 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● ● ● Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 82/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 41. Symbol EMI characteristics(1) Parameter Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz TBD TBD TBD TBD TBD TBD TBD TBD dBµV SEMI Peak level 0.1 to 30 MHz VDD = 3.3 V, TA = 25 °C, 30 to 130 MHz LQFP100 package compliant with SAE J 130 MHz to 1GHz 1752/3 SAE EMI Level 1. TBD = to be determined. 5.3.12 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 42. Symbol VESD(HBM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Conditions TA = +25 °C conforming to JESD22-A114 TA = +25 °C conforming to JESD22-C101 Class 2 Maximum value(1) 2000 V II 500 Unit Electrostatic discharge VESD(CDM) voltage (charge device model) 1. Values based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● ● A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. 83/118 Electrical characteristics Table 43. Symbol LU STM32F103xC, STM32F103xD, STM32F103xE Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A Class II level A 5.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 44. Symbol VIL I/O static characteristics Parameter Input low level voltage(1) Standard IO input high level voltage(1) TTL ports Conditions Min –0.5 2 2 –0.5 CMOS ports 0.65 VDD 200 5% VDD(4) VSS ≤VIN ≤VDD Standard I/Os VIN= 5 V I/O FT Weak pull-up equivalent resistor(6) Weak pull-down equivalent resistor(6) I/O pin capacitance VIN = VSS VIN = VDD 30 30 40 40 5 ±1 µA 3 50 50 kΩ kΩ pF Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV Unit VIH IO FT(2) input high level voltage(1) Input low level voltage(1) Input high level voltage(1) Standard IO Schmitt trigger voltage hysteresis(3) VIL VIH V Vhys IO FT Schmitt trigger voltage hysteresis(3) Ilkg Input leakage current (5) RPU RPD CIO 1. Values based on characterization results, and not tested in production. 2. FT = Five-volt tolerant. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. With a minimum of 100 mV. 5. Leakage could be higher than max. if negative current is injected on adjacent pins. 6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 84/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). ● Output voltage levels Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 45. Symbol VOL(1) VOH(2) VOL (1) VOH (2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3) Output voltage characteristics Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD–0.4 0.4 V 2.4 1.3 V VDD–1.3 0.4 V VDD–0.4 Unit IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 85/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 40 and Table 46, respectively. Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 46. I/O AC characteristics(1) Parameter Conditions Min Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125(3) 10 25(3) CL = 50 pF, VDD = 2 V to 3.6 V 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) ns MHz MHz MHz ns MHz ns Unit MHz MODEx[1:0] Symbol bit value(1) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time - tEXTIpw 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 40. 3. Values based on design simulation and validated on silicon, not tested in production. 86/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 40. I/O AC characteristics definition Electrical characteristics 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out 10% 50% 90% tr(I O)out T Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 44). Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 47. Symbol VIL(NRST) VIH(NRST) Vhys(NRST) RPU VF(NRST) VNF(NRST) NRST pin characteristics Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(1) NRST Input filtered pulse (2) Conditions Min –0.5 2 Typ Max 0.8 Unit V VDD+0.5 200 VIN = VSS 30 40 50 100 kΩ ns ns NRST Input not filtered pulse(2) 300 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Values guaranteed by design, not tested in production. 87/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 41. Recommended NRST pin protection External reset circuit NRST VDD RPU FILTER 0.1 µF Internal Reset STM32F101xx ai14132b 5. The reset network protects the device against parasitic resets. 6. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 47. Otherwise the reset will not be taken into account by the device. 5.3.15 TIM timer characteristics The parameters given in Table 48 are guaranteed by fabrication. Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 48. Symbol tres(TIM) TIMx(1) characteristics Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected 13.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 × 65536 fTIMxCLK = 72 MHz 59.6 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 88/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.16 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F103xC performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 49. Refer also to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 49. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb I2C characteristics Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0(3) 1000 300 Max Min 1.3 µs 0.6 100 0(4) 20 + 0.1Cb 20 + 0.1Cb 0.6 µs 0.6 0.6 1.3 400 μs μs pF 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit 1. Values based on standard I2C protocol requirement, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 89/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42. I2C bus AC waveforms and measurement circuit VDD 4 .7 kΩ I2C bus VDD 4 .7 kΩ STM32F103xx SDA SCL 100Ω 100Ω S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 50. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3) I2C_CCR value fSCL (kHz) 400 300 200 100 50 20 RP = 4.7 kΩ TBD TBD TBD TBD TBD TBD 1. TBD = to be determined. 2. RP = External pull-up resistance, fSCL = I2C speed, 3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. 90/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 51. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(3) th(NSS)(3) tw(SCKH) tw(SCKL)(3) tsu(MI) (3) tsu(SI)(3) (3) SPI characteristics(1) (2) Parameter Master mode SPI clock frequency Slave mode SPI clock rise and fall time NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 Master mode Data input setup time Slave mode Master mode, fPCLK = 36 MHz, presc = 4 5 15 5 TBD(4) TBD(4) 0 0 5 60 TBD TBD 30 TBD 10 TBD 30 10 TBD ns tC(SCK) 0.5tC(SCK) 50 10 60 0 18 8 Conditions Min 0 Max 18 MHz Unit th(MI) (3) th(SI)(3) Data input hold time Slave mode, fPCLK = 36 MHz, presc = 4 Master mode, fPCLK = TBD Slave mode, fPCLK = TBD ta(SO)(3)(5) tdis(SO)(3)(6) tv(SO) (3)(1) Data output access time Slave mode, fPCLK = 36 MHz, presc = 4 Slave mode, fPCLK = TBD Data output disable time Slave mode Slave mode (after enable edge), fPCLK = 36 MHz, presc = 4 fPCLK = TBD Data output valid time tv(MO) (3)(1) Data output valid time Master mode (after enable edge), fPCLK = 36 MHz, presc = 4 fPCLK = TBD th(SO)(3) th(MO) (3) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) 1. TBD = to be determined. 2. Remapped SPI1 characteristics to be determined. 3. Values based on design simulation and/or characterization results, and not tested in production. 4. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns. 5. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 6. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 91/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 43. SPI timing diagram - slave mode and CPHA = 0 NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT ta(SO) MISO OUT P UT MOSI I NPUT th(SO) BI T6 OUT tdis(SO) M SB IN th(SI) B I T1 IN LSB IN ai14134 Figure 44. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 92/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 45. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input Electrical characteristics CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTPUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 93/118 Electrical characteristics Table 52. Symbol fCK 1/tc(CK) tr(CK) tf(CK) tv(WS) (2) th(WS) (2) tsu(WS) th(WS) (2) (2) (2) STM32F103xC, STM32F103xD, STM32F103xE I2S characteristics (1) Parameter I2S clock frequency I2S clock rise and fall time WS valid time WS hold time WS setup time WS hold time CK high and low time Data input setup time Data input hold time Data input hold time Conditions Master Slave capacitive load CL = 50 pF Master Master Slave Slave Master fPCLK= TBD, presc = TBD Master receiver Slave receiver Master receiver Slave receiver Master fPCLK = TBD Slave fPCLK = TBD Slave transmitter (after enable edge) fPCLK = TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Min TBD 0 Max TBD MHz TBD TBD Unit tw(CKH) tw(CKL) (2) tsu(SD_MR) (2) tsu(SD_SR) (2) th(SD_MR)(2)(3) th(SD_SR) (2)(3) th(SD_MR) (2) th(SD_SR) (2) tv(SD_ST) (2)(3) ns Data output valid time th(SD_ST) (2) Data output hold time Slave transmitter (after enable edge) Master transmitter (after enable edge) fPCLK = TBD tv(SD_MT) (2)(3) Data output valid time th(SD_MT) (2) Data output hold time Master transmitter (after enable edge) 1. TBD = to be determined. 2. Data based on design simulation and/or characterization results, not tested in production. 3. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. 94/118 STM32F103xC, STM32F103xD, STM32F103xE Figure 46. I2S slave timing diagram(1) Electrical characteristics tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) WS input tsu(WS) SDtransmit tsu(SD_SR) SDreceive MSB receive MSB transmit tv(SD_ST) Bitn transmit th(SD_SR) Bit1 receive LSB receive th(SD_ST) LSB transmit tw(CKL) th(WS) ai14881 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. Figure 47. I2S master timing diagram(1) tf(CK) tr(CK) tc(CK) CK output CPOL = 0 tw(CKH) CPOL = 1 tv(WS) WS output tsu(SD_MR) SDreceive MSB receive tv(SD_MT) Bitn receive th(SD_MR) SDtransmit MSB transmit Bitn transmit LSB transmit th(SD_MT) LSB receive tw(CKL) th(WS) ai14884 1. Data based on design simulation and/or characterization results, not tested in production. 95/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 48. SDIO high-speed mode tf tr tC tW(CKH) CK tOV D, CMD (output) tISU D, CMD (input) ai14887 tW(CKL) tOH tIH Figure 49. SD default mode CK tOVD D, CMD (output) tOHD ai14888 96/118 STM32F103xC, STM32F103xD, STM32F103xE Table 53. Symbol fPP tW(CKL) tW(CKH) tr tf tC CMD, D inputs (referenced to CK) tISU tIH Input setup time Input hold time CL ≤ 30 pF CL ≤ 30 pF Electrical characteristics SD / MMC characteristics Parameter Clock frequency in data transfer mode Clock low time Clock high time Clock rise time Clock fall time Conditions CL ≤ 30 pF CL ≤ 30 pF CL ≤ 30 pF CL ≤ 30 pF CL ≤ 30 pF Min 0 TBD TBD ns TBD TBD Max TBD Unit MHz TBD ns TBD CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV tOH Output valid time Output hold time CL ≤ 30 pF CL ≤ 30 pF TBD TBD ns CMD, D outputs (referenced to CK) in SD default mode(1) tOVD tOHD Output valid default time Output hold default time CL ≤ 30 pF CL ≤ 30 pF TBD TBD ns 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 54. USB startup time Parameter USB transceiver startup time Max 1 Unit µs Symbol tSTARTUP 97/118 Electrical characteristics Table 55. Symbol Input levels VUSB VDI (4) STM32F103xC, STM32F103xD, STM32F103xE USB DC electrical characteristics Parameter Conditions Min.(1) Max.(1) Unit USB voltage(2) Differential input sensitivity Within VDD voltage range I(USBDP, USBDM) 3.0(3) 0.2 0.8 1.3 3.6 V VCM(4) VSE(4) Differential common mode range Includes VDI range Single ended receiver threshold 2.5 2.0 V Output levels VOL VOH Static output level low Static output level high RL of 1.5 kΩ to 3.6 V(5) RL of 15 kΩ to VSS(5) 2.8 0.3 V 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by characterization, not tested in production. 5. RL is the load connected on the USB drivers Figure 50. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines V CRS VS S tf tr ai14137 Table 56. USB: full-speed electrical characteristics Driver characteristics(1) Symbol tr tf trfm VCRS Parameter Rise time(2) Fall Time (2) Conditions CL = 50 pF CL = 50 pF tr/tf Min 4 4 90 1.3 Max 20 20 110 2.0 Unit ns ns % V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by characterization, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.17 CAN (controller area network) interface Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 98/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5.3.18 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: Table 57. Symbol VDDA VREF+ fADC fS(1) fTRIG(1) VAIN RAIN(1) RADC(1) CADC(1) tCAL(1) tlat(1) tlatr(1) tS(1) tSTAB(1) tCONV(1) It is recommended to perform a calibration after each power-up. ADC characteristics Parameter ADC power supply Positive reference voltage ADC clock frequency Sampling rate External trigger frequency Conversion voltage range(2) External input impedance Sampling switch resistance Internal sample and hold capacitor 5.9 Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 14 MHz 83 0.214 fADC = 14 MHz 3(3) 0.143 fADC = 14 MHz 0.107 fADC = 14 MHz 1.5 0 1 fADC = 14 MHz 0 2 (3) Conditions Min 2.4 2.4 0.6 0.05 Typ Max 3.6 VDDA 14 1 823 Unit V V MHz MHz kHz 1/fADC V kΩ kΩ pF µs 1/fADC µs 1/fADC µs 1/fADC µs 1/fADC µs µs 1/fADC fADC = 14 MHz 0 (VSSA or VREFtied to ground) 17 VREF+ See Equation 1 and Table 58 1 5 17.1 239.5 1 18 14 to 252 (tS for sampling +12.5 for successive approximation) 1. Guaranteed by design, not tested in production. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pin descriptions for further details. 3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 57. 99/118 Electrical characteristics Equation 1: RAIN max formula: TS R AIN < --------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) STM32F103xC, STM32F103xD, STM32F103xE The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 58. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) 0.11 0.54 0.96 2.04 2.96 3.96 5.11 17.1 1.2 10 19 41 60 80 104 350 RAIN max (kΩ) 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Data guaranteed by design, not tested in production. Table 59. Symbol ET EO EG ED EL ADC accuracy - limited test conditions(1) Parameter Total unadjusted error(3) Offset error(3) (3) (3) Test conditions fPCLK2 = 56 MHz, , fADC = 14 MHz, RAIN < 10 kΩ VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration VREF+ = VDDA Typ ±1.3 ±1 ±0.5 ±0.7 ±0.8 Max(2) ±2 ±1.5 ±1.5 ±1 ±1.5 Unit Gain error LSB Differential linearity error Integral linearity error(3) 1. ADC DC accuracy values are measured after internal calibration. 2. Data based on characterization, not tested in production. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 100/118 STM32F103xC, STM32F103xD, STM32F103xE Table 60. Symbol ET EO EG ED EL Electrical characteristics ADC accuracy(1) (2) Parameter Total unadjusted error(4) Offset error(3) (3) Test conditions fPCLK2 = 56 MHz, , fADC = 14 MHz, RAIN < 10 kΩ VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ ±2 ±1.5 ±1.5 ±1 ±1.5 Max(3) ±5 ±25 ±3 ±2 ±3 Unit Gain error LSB Differential linearity error(3) Integral linearity error (3) 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. Data based on characterization, not tested in production. 4. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. Figure 51. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 5 6 7 4093 4094 4095 4096 VDDA ai14395b 101/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 52. Typical connection diagram using the ADC VDD VT 0.6 V AINx VT 0.6 V STM32F103xx RAIN(1) RADC(1) 12-bit A/D conversion CADC(1) VAIN CAIN IL±1 µA ai14150b 1. Refer to Table 57 for the values of CAIN, RAIN, RADC and CADC. 2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 53 or Figure 54, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 µF // 10 nF VDDA 1 µF // 10 nF VSSA /VREF– (see note 1) ai14388b 1. VREF+ and VREF– inputs are available only on 100-pin packages. 102/118 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 103/118 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.19 Table 61. Symbol VDD33A VDD18D VREF+ VSSA RL CL DAC electrical specifications DAC characteristics Parameter Analog supply voltage Digital supply voltage Reference supply voltage Ground Resistive load with buffer ON Capacitive load 0.2 Min 2.4 1.6 2.4 0 5 50 1.8 Typ Max(1) 3.6 2 3.6 0 Unit V V V V kΩ pF V Minimum resistive load between DAC_OUT and VSSA Maximum capacitive load at DAC_OUT pin. It gives the maximum output excursion of the DAC it corresponds to 12-bit input code (0E0)h to (F1C)h @ VREF+ = 3.6 V and (155)h and (EAB)h @ VREF+ = 2.4 V With no load, middle code (800)H on the inputs With no load, worst code (F1C)H @ VREF+ = 3.6 V in terms of DC consumption on the inputs VREF+ must always be below VDD33A Comments DAC_OUT Lower DAC_OUT voltage with min buffer ON DAC_OUT Higher DAC_OUT voltage with max buffer ON VREF+– 0.2 V V 425 IDD DAC DC current consumption in quiescent mode (Standby mode) (in VDD18D+VDD33A+ VREF+) DAC DC current consumption in Power Down mode (in VDD18D+VDD33A+VREF+) DAC DC current consumption in Power Down mode (in VDD33A+VREF+) Differential non linearity (Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (800)H and the ideal value = VREF+/2 Gain error 600 µA 500 700 µA 5 350 nA With no load. IDDQ 5 200 DNL ±0.5 LSB Given for the DAC in 10-bit configuration (B1=B0=0 always) INL ±1 LSB Given for the DAC in 10-bit configuration (B1=B0=0 always) ±10 ±3 ±0.5 mV LSB % Given for the DAC in 10-bit configuration (B1=B0=0 always) Given for the DAC in 10-bit @ VREF+ = 3.6 V Given for the DAC in 10-bit configuration (B1=B0=0 always) Offset Gain error 104/118 STM32F103xC, STM32F103xD, STM32F103xE Table 61. Symbol Amplifier gain Electrical characteristics DAC characteristics (continued) Parameter Gain of the amplifier in open loop Settling time (full scale: for an 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Wakeup time from off state (PDV18 from 1 to 0) Power supply rejection ratio (to VDD33A) (static DC measurement Min 80 Typ 85 Max(1) Unit dB Comments with a 5 kΩ load (worst case) tSETTLING 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. No RLOAD, CLOAD = 50 pF tWAKEUP 6.5 10 µs PSRR+ –67 –40 dB 1. Guaranteed by characterization, not tested in production. 5.3.20 Table 62. Symbol TL(1) Avg_Slope(1) V25 (1) Temperature sensor characteristics TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25 °C Startup time ADC sampling time when reading the temperature 4.0 1.34 4 2.2 Conditions Min Typ Max Unit °C mV/°C V µs µs ±1 4.3 1.43 ±2 4.6 1.52 10 17.1 tSTART(2) TS_temp(3)(2) 1. Guaranteed by characterization, not tested in production. 2. Data guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 105/118 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE 6 6.1 Package characteristics Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 106/118 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 55. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Seating plane C Figure 56. Recommended footprint(1)(2) A A2 A1 ccc C b c 0.25 mm gage plane D D1 D3 A1 73 72 k 0.5 0.35 L L1 22.6 19.9 108 109 19.9 1.35 E1 E3 E 17.85 22.6 ai14905b 144 37 1 36 Pin 1 identification e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 63. Symbol LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data millimeters Typ Min Max 1.60 0.05 1.40 0.22 1.35 0.17 0.09 22.00 20.00 17.50 22.00 20.00 17.50 0.50 0.60 1.00 3.5° 0° 0.08 7° 0.45 0.75 21.80 19.80 22.20 20.20 21.80 19.80 0.15 1.45 0.27 0.20 22.20 20.20 0.8661 0.7874 0.689 0.8661 0.7874 0.689 0.0197 0.0236 0.0394 3.5° 0° 0.0031 7° 0.0177 0.0295 0.8583 0.7795 0.874 0.7953 0.0551 0.0087 0.002 0.0531 0.0067 0.0035 0.8583 0.7795 Typ inches(1) Min Max 0.063 0.0059 0.0571 0.0106 0.0079 0.874 0.7953 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. 107/118 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 57. LFBGA100 - low profile fine pitch ball grid array package outline C Seating plane ddd C A2 A4 A3 B e D D1 F A1 A A K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 F E1 E e A1 corner index area (see note 5) ∅b (100 ∅eee balls) MCAB ∅ fff M C ai14396 Bottom view Table 64. Dim. LFBGA100 - low profile fine pitch ball grid array package mechanical data mm Min Typ Max 1.700 0.270 1.085 0.30 0.80 0.45 9.85 0.50 10.00 7.20 9.85 10.00 7.20 0.80 1.40 0.12 0.15 0.08 100 10.15 0.0153 0.55 10.15 0.0007 0.0153 0.0008 0.0155 0.0111 0.0155 0.0111 0.0012 0.0022 0.0002 0.0002 0.0001 0.0157 0.0004 0.0017 0.0005 0.0012 0.0009 0.0157 Min inches(1) Typ Max 0.0026 A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff N (number of balls) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 108/118 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended – 4 to 6 mils screen print Dpad Dsm 109/118 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60. Recommended footprint(1)(2) Figure 59. LQFP100, 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k D D1 D3 75 76 51 75 51 76 L L1 C 50 0.5 50 0.3 .3 b E3 E1 E 100 26 1.2 100 26 25 1 ccc C 25 12.3 16.7 ai14906 Pin 1 1 identification e A1 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 65. Symbol LQPF100 – 100-pin low-profile quad flat package mechanical data millimeters Typ Min Max 1.60 0.05 1.40 0.22 1.35 0.17 0.09 16.00 14.00 12.00 16.00 14.00 12.00 0.50 0.60 1.00 3.5° 0° 0.08 7° 0.45 0.75 15.80 13.80 16.20 14.20 15.80 13.80 0.15 1.45 0.27 0.20 16.20 14.20 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5° 0° 0.0031 7° 0.0177 0.0295 0.622 0.5433 0.6378 0.5591 0.0551 0.0087 0.002 0.0531 0.0067 0.0035 0.622 0.5433 Typ inches(1) Min Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. 110/118 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 62. Recommended footprint(1)(2) Figure 61. LQFP64 – 64 pin low-profile quad flat package outline(1) D D1 A1 A A2 48 33 0.3 49 0.5 32 b 12.7 10.3 E1 E e 10.3 64 17 1.2 1 c 16 7.8 12.7 L1 L ai14398 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 66. Dim. LQFP64 – 64 pin low-profile quad flat package mechanical data mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0° 0.45 3.5° 0.60 1.00 Number of pins 7° 0.75 0° 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5° 0.0236 0.0394 7° 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 A A1 A2 b c D D1 E E1 e θ L L1 N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 111/118 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline C Seating plane A2 A4 A3 B D D1 e M F F A A A1 ddd C E1 E e 12 Øb (144 balls) Ø eee M C A Ø fff M C B X3_ME 1. Drawing is not to scale. Table 67. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data millimeters inches(1) Max 1.70 0.21 1.07 0.27 0.85 0.35 9.85 0.40 10.00 8.80 9.85 10.00 8.80 0.80 0.60 0.10 0.15 0.08 10.15 0.3878 0.45 10.15 0.0138 0.3878 0.0157 0.3937 0.3465 0.3937 0.3465 0.0315 0.0236 0.0039 0.0059 0.0031 0.3996 0.0083 0.0421 0.0106 0.0335 0.0177 0.3996 Typ Min Max 0.0669 Symbol Typ A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Min 1. Values in inches are converted from mm and rounded to 4 decimal digits. 112/118 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 38. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: ● ● ● ● TA max is the maximum ambient temperature in °C, ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 68. Symbol Thermal characteristics Parameter Thermal resistance junction-ambient LFBGA144 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch Value TBD TBD 41 46 45 °C/W Unit ΘJA Thermal resistance junction-ambient LFBGA100 - 10 × 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 6.2.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 113/118 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 69: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xC at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 464 mW Using the values obtained in Table 68 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 69: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW 114/118 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Using the values obtained in Table 68 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 69: Ordering information scheme). Figure 64. LQFP100 PD max vs. TA 700 600 PD (mW) 500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7 TA (°C) 115/118 Part numbering STM32F103xC, STM32F103xD, STM32F103xE 7 Part numbering Table 69. Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = BGA T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and real Ordering information scheme STM32 F 103 R C T 6 xxx For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 116/118 STM32F103xC, STM32F103xD, STM32F103xE Revision history 8 Revision history Table 70. Date 07-Apr-2008 Document revision history Revision 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 9. LQPF100/BGA100 column added to Table 5: FSMC pin definition on page 32. Values and Figures added to Maximum current consumption on page 40 (see Table 13, Table 14, Table 15 and Table 16 and see Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17). Values added to Typical current consumption on page 46 (see Table 17, Table 18 and Table 19). Table 19: Typical current consumption in Standby mode removed. Note 4 and Note 1 added to Table 55: USB DC electrical characteristics and Table 56: USB: full-speed electrical characteristics on page 98, respectively. VUSB added to Table 55: USB DC electrical characteristics on page 98. Figure 56: Recommended footprint(1) on page 107 corrected. Equation 1 corrected. Figure 64: LQFP100 PD max vs. TA on page 115 modified. Tolerance values corrected in Table 67: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 112. Changes 22-May-2008 2 117/118 STM32F103xC, STM32F103xD, STM32F103xE Please Read Carefully: Information in this document is provided solely in connection with ST products. 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