STM32F103xF STM32F103xG
XL-density performance line ARM®-based 32-bit MCU with 768 KB
to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 com. interfaces
Datasheet − production data
Features
&"'!
®
®
• Core: ARM 32-bit Cortex -M3 CPU with MPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
• Memories
– 768 Kbytes to 1 Mbyte of Flash memory
– 96 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• 3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
• DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I2Ss, SPIs, I2Cs and USARTs
May 2015
This is information on a product in full production.
LFBGA144 10 × 10 mm
– Serial wire debug (SWD) & JTAG
interfaces
– Cortex®-M3 Embedded Trace Macrocell™
• Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
• Up to 17 timers
– Up to ten 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
• Up to 13 communication interfaces
– Up to 2 × I2C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I2S
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
• CRC calculation unit, 96-bit unique ID
• 2 × 12-bit D/A converters
• Debug mode
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
• ECOPACK® packages
Table 1. Device summary
Reference
Part number
STM32F103xF
STM32F103RF STM32F103VF STM32F103ZF
STM32F103xG
STM32F103RG STM32F103VG STM32F103ZG
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Contents
STM32F103xF, STM32F103xG
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2/136
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 15
2.3.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.6
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19
2.3.18
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.19
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.20
Universal synchronous/asynchronous receiver transmitters (USARTs) . 21
2.3.21
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.22
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.23
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.24
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.27
ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.28
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
2.3.29
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.30
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.31
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 45
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.10
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.12
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.3.16
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.18
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 108
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STM32F103xF, STM32F103xG
5.3.19
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.20
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.21
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.1
LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
6.2
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
6.3
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.4
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.5.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.5.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 130
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xF and STM32F103xG features and peripheral counts . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F103xF and STM32F103xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19
STM32F103xF and STM32F103xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 49
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 50
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 68
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 69
Asynchronous multiplexed read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 77
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 84
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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List of tables
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
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STM32F103xF, STM32F103xG
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 126
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
STM32F103xF and STM32F103xG ordering information scheme . . . . . . . . . . . . . . . . . . 132
DocID16554 Rev 4
STM32F103xF, STM32F103xG
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
STM32F103xF and STM32F103xG performance line block diagram. . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xF/G BGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F103xF/G performance line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F103xF/G performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F103xF/G performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 48
Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 48
Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical current consumption in Standby mode versus temperature at
different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 67
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 68
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 70
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 77
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 79
PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 80
PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 82
PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 83
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 86
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 86
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DocID16554 Rev 4
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8
List of figures
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
8/136
STM32F103xF, STM32F103xG
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 111
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 112
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 119
LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 123
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
LFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 126
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 127
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
DocID16554 Rev 4
STM32F103xF, STM32F103xG
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For
more details on the whole STMicroelectronics STM32F103xF/G family, please refer to
Section 2.2: Full compatibility throughout the family.
The XL-density STM32F103xF/G datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference
Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com.
DocID16554 Rev 4
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132
Description
2
STM32F103xF, STM32F103xG
Description
The STM32F103xF and STM32F103xG performance line family incorporates the highperformance ARM® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and
an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer three 12-bit ADCs, ten general-purpose 16-bit timers plus two PWM timers, as
well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two
I2Ss, one SDIO, five USARTs, an USB and a CAN.
The STM32F103xF/G XL-density performance line family operates in the –40 to +105 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
These features make the STM32F103xF/G high-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems and video intercom.
10/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
2.1
Description
Device overview
The STM32F103xF/G XL-density performance line family offers devices in four different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32F103xF and STM32F103xG features and peripheral counts
Peripherals
Flash memory
STM32F103Rx
768 KB
1 MB
STM32F103Vx
768 KB
1 MB
STM32F103Zx
768 KB
1 MB
SRAM in Kbytes
96
96
96
FSMC
No
Yes(1)
Yes
Timers
General-purpose
10
Advanced-control
2
Basic
2
SPI(I2S)(2)
3(2)
2C
Comm
I
2
USART
5
USB
1
CAN
1
SDIO
1
GPIOs
51
80
112
12-bit ADC
Number of channels
3
16
3
16
3
21
12-bit DAC
Number of channels
2
2
CPU frequency
72 MHz
Operating voltage
Operating temperatures
Package
2.0 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
Junction temperature: –40 to + 125 °C (see Table 10)
LQFP64
LQFP100
LQFP144, BGA144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND
Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available
in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the
I2S audio mode.
DocID16554 Rev 4
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132
Description
STM32F103xF, STM32F103xG
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1. TA = –40 °C to +85 °C (suffix 6, see Table 73) or –40 °C to +105 °C (suffix 7, see Table 73), junction
temperature up to 105 °C or 125 °C, respectively.
2. AF = alternate function on I/O port pin.9
12/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Description
Figure 2. Clock tree
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28/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Table 5. STM32F103xF and STM32F103xG pin definitions
Alternate functions(4)
I / O level(2)
LQFP144
Remap
LQFP100
Default
LQFP64
Main
function(3)
(after reset)
LFBGA144
Type(1)
Pins
Pin name
A3
-
1
1
PE2
I/O FT
PE2
TRACECK / FSMC_A23
-
A2
-
2
2
PE3
I/O FT
PE3
TRACED0 / FSMC_A19
-
B2
-
3
3
PE4
I/O FT
PE4
TRACED1/ FSMC_A20
-
B3
-
4
4
PE5
I/O FT
PE5
TRACED2/ FSMC_A21
TIM9_CH1
B4
-
5
5
PE6
I/O FT
PE6
TRACED3 / FSMC_A22
TIM9_CH2
C2
1
6
6
VBAT
S
VBAT
-
-
A1
2
7
7
PC13-TAMPERRTC(5)
I/O
PC13(6)
TAMPER-RTC
-
B1
3
8
8 PC14-OSC32_IN(5) I/O
PC14(6)
OSC32_IN
-
C1
4
9
9
PC15OSC32_OUT(5)
PC15(6)
OSC32_OUT
-
C3
-
-
10
PF0
I/O FT
PF0
FSMC_A0
-
C4
-
-
11
PF1
I/O FT
PF1
FSMC_A1
-
D4
-
-
12
PF2
I/O FT
PF2
FSMC_A2
-
E2
-
-
13
PF3
I/O FT
PF3
FSMC_A3
-
E3
-
-
14
PF4
I/O FT
PF4
FSMC_A4
-
E4
-
-
15
PF5
I/O FT
PF5
FSMC_A5
-
D2
-
10 16
VSS_5
S
VSS_5
-
-
D3
-
11 17
VDD_5
S
VDD_5
-
-
F3
-
-
18
PF6
I/O
PF6
ADC3_IN4 / FSMC_NIORD
TIM10_CH1
F2
-
-
19
PF7
I/O
PF7
ADC3_IN5 / FSMC_NREG
TIM11_CH1
G3
-
-
20
PF8
I/O
PF8
ADC3_IN6 / FSMC_NIOWR
TIM13_CH1
G2
-
-
21
PF9
I/O
PF9
ADC3_IN7 / FSMC_CD
TIM14_CH1
G1
-
-
22
PF10
I/O
PF10
ADC3_IN8 / FSMC_INTR
-
D1
5
12 23
OSC_IN
I
OSC_IN
-
PD0(7)
E1
6
13 24
OSC_OUT
O
OSC_OUT
-
PD1(7)
F1
7
14 25
NRST
I/O
NRST
-
-
H1
8
15 26
PC0
I/O
PC0
ADC123_IN10
-
H2
9
16 27
PC1
I/O
PC1
ADC123_IN11
-
I/O
DocID16554 Rev 4
29/136
132
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Table 5. STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
I / O level(2)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
Main
function(3)
(after reset)
Default
Remap
H3 10 17 28
PC2
I/O
PC2
ADC123_IN12
-
H4 11 18 29
PC3
I/O
PC3
ADC123_IN13
-
J1
VSSA
S
VSSA
-
-
12 19 30
K1
-
20 31
VREF-
S
VREF-
-
-
L1
-
21 32
VREF+
S
VREF+
-
-
M1 13 22 33
VDDA
S
VDDA
-
-
WKUP/USART2_CTS(8)
PA0-WKUP
I/O
PA0
/
ADC123_IN0 / TIM2_CH1_ETR /
TIM5_CH1 / TIM8_ETR
-
K2 15 24 35
PA1
I/O
PA1
USART2_RTS(7) / ADC123_IN1 /
TIM5_CH2 / TIM2_CH2(7)
-
L2 16 25 36
PA2
I/O
PA2
USART2_TX(7) / TIM5_CH3 /
ADC123_IN2 / TIM9_CH1 /
TIM2_CH3 (7)
-
-
J2
14 23 34
M2 17 26 37
PA3
I/O
PA3
USART2_RX(7) / TIM5_CH4 /
ADC123_IN3 / TIM2_CH4(7)/
TIM9_CH2
G4 18 27 38
VSS_4
S
VSS_4
-
-
F4 19 28 39
VDD_4
S
VDD_4
-
-
20 29 40
PA4
I/O
PA4
SPI1_NSS(7) / USART2_CK(7) /
DAC_OUT1 / ADC12_IN4
-
K3 21 30 41
PA5
I/O
PA5
SPI1_SCK(7) / DAC_OUT2 /
ADC12_IN5
-
L3 22 31 42
PA6
I/O
PA6
SPI1_MISO(7) / TIM8_BKIN /
ADC12_IN6 / TIM3_CH1(7)/
TIM13_CH1
TIM1_BKIN
TIM1_CH1N
J3
M3 23 32 43
PA7
I/O
PA7
SPI1_MOSI(7)/ TIM8_CH1N /
ADC12_IN7 / TIM3_CH2(7) /
TIM14_CH1
J4
24 33 44
PC4
I/O
PC4
ADC12_IN14
-
K4 25 34 45
PC5
I/O
PC5
ADC12_IN15
-
L4 26 35 46
PB0
I/O
PB0
ADC12_IN8 / TIM3_CH3 /
TIM8_CH2N
TIM1_CH2N
30/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Table 5. STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
I / O level(2)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
Main
function(3)
(after reset)
M4 27 36 47
PB1
I/O
J5
PB2
I/O FT PB2/BOOT1
28 37 48
PB1
Default
Remap
ADC12_IN9 / TIM3_CH4(7) /
TIM8_CH3N
TIM1_CH3N
-
-
M5
-
-
49
PF11
I/O FT
PF11
FSMC_NIOS16
-
L5
-
-
50
PF12
I/O FT
PF12
FSMC_A6
-
H5
-
-
51
VSS_6
S
VSS_6
-
-
G5
-
-
52
VDD_6
S
VDD_6
-
-
K5
-
-
53
PF13
I/O FT
PF13
FSMC_A7
-
M6
-
-
54
PF14
I/O FT
PF14
FSMC_A8
-
L6
-
-
55
PF15
I/O FT
PF15
FSMC_A9
-
K6
-
-
56
PG0
I/O FT
PG0
FSMC_A10
-
J6
-
-
57
PG1
I/O FT
PG1
FSMC_A11
-
M7
-
38 58
PE7
I/O FT
PE7
FSMC_D4
TIM1_ETR
L7
-
39 59
PE8
I/O FT
PE8
FSMC_D5
TIM1_CH1N
K7
-
40 60
PE9
I/O FT
PE9
FSMC_D6
TIM1_CH1
H6
-
-
61
VSS_7
S
VSS_7
-
-
G6
-
-
62
VDD_7
S
VDD_7
-
-
J7
-
41 63
PE10
I/O FT
PE10
FSMC_D7
TIM1_CH2N
H8
-
42 64
PE11
I/O FT
PE11
FSMC_D8
TIM1_CH2
J8
-
43 65
PE12
I/O FT
PE12
FSMC_D9
TIM1_CH3N
K8
-
44 66
PE13
I/O FT
PE13
FSMC_D10
TIM1_CH3
L8
-
45 67
PE14
I/O FT
PE14
FSMC_D11
TIM1_CH4
M8
-
46 68
PE15
I/O FT
PE15
FSMC_D12
TIM1_BKIN
USART3_TX(7)
TIM2_CH3
M9 29 47 69
PB10
I/O FT
PB10
I2C2_SCL /
M10 30 48 70
PB11
I/O FT
PB11
I2C2_SDA / USART3_RX(7)
TIM2_CH4
H7 31 49 71
VSS_1
S
VSS_1
-
-
G7 32 50 72
VDD_1
S
VDD_1
-
-
M11 33 51 73
PB12
PB12
SPI2_NSS / I2S2_WS /
I2C2_SMBA / USART3_CK(7) /
TIM1_BKIN(7)
-
I/O FT
DocID16554 Rev 4
31/136
132
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Table 5. STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
I / O level(2)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
Main
function(3)
(after reset)
Default
Remap
M12 34 52 74
PB13
I/O FT
PB13
SPI2_SCK / I2S2_CK /
USART3_CTS(7) / TIM1_CH1N
-
L11 35 53 75
PB14
I/O FT
PB14
SPI2_MISO / TIM1_CH2N /
USART3_RTS(7)/ TIM12_CH1
-
L12 36 54 76
PB15
I/O FT
PB15
SPI2_MOSI / I2S2_SD /
TIM1_CH3N(7) / TIM12_CH2
-
L9
-
55 77
PD8
I/O FT
PD8
FSMC_D13
USART3_TX
K9
-
56 78
PD9
I/O FT
PD9
FSMC_D14
USART3_RX
J9
-
57 79
PD10
I/O FT
PD10
FSMC_D15
USART3_CK
H9
-
58 80
PD11
I/O FT
PD11
FSMC_A16
USART3_CTS
L10
-
59 81
PD12
I/O FT
PD12
FSMC_A17
TIM4_CH1 /
USART3_RTS
K10
-
60 82
PD13
I/O FT
PD13
FSMC_A18
TIM4_CH2
G8
-
-
83
VSS_8
S
VSS_8
-
-
F8
-
-
84
VDD_8
S
VDD_8
-
-
K11
-
61 85
PD14
I/O FT
PD14
FSMC_D0
TIM4_CH3
K12
-
62 86
PD15
I/O FT
PD15
FSMC_D1
TIM4_CH4
J12
-
-
87
PG2
I/O FT
PG2
FSMC_A12
-
J11
-
-
88
PG3
I/O FT
PG3
FSMC_A13
-
J10
-
-
89
PG4
I/O FT
PG4
FSMC_A14
-
H12
-
-
90
PG5
I/O FT
PG5
FSMC_A15
-
H11
-
-
91
PG6
I/O FT
PG6
FSMC_INT2
-
H10
-
-
92
PG7
I/O FT
PG7
FSMC_INT3
-
G11
-
-
93
PG8
I/O FT
PG8
-
-
G10
-
-
94
VSS_9
S
VSS_9
-
-
F10
-
-
95
VDD_9
S
VDD_9
-
-
G12 37 63 96
PC6
I/O FT
PC6
I2S2_MCK / TIM8_CH1 /
SDIO_D6
TIM3_CH1
F12 38 64 97
PC7
I/O FT
PC7
I2S3_MCK / TIM8_CH2 /
SDIO_D7
TIM3_CH2
F11 39 65 98
PC8
I/O FT
PC8
TIM8_CH3 / SDIO_D0
TIM3_CH3
32/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Table 5. STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
E11 40 66 99
PC9
I / O level(2)
Pin name
Type(1)
LQFP144
LQFP100
LQFP64
LFBGA144
Pins
I/O FT
Main
function(3)
(after reset)
Default
Remap
PC9
TIM8_CH4 / SDIO_D1
TIM3_CH4
TIM1_CH1(7)
E12 41 67 100
PA8
I/O FT
PA8
USART1_CK /
MCO
D12 42 68 101
PA9
I/O FT
PA9
USART1_TX(7) / TIM1_CH2(7)
-
USART1_RX(7)
-
/
TIM1_CH3(7)
-
D11 43 69 102
PA10
I/O FT
PA10
C12 44 70 103
PA11
I/O FT
PA11
USART1_CTS / USB_DM /
CAN_RX(7) / TIM1_CH4(7)
-
B12 45 71 104
PA12
I/O FT
PA12
USART1_RTS / USB_DP /
CAN_TX(7) / TIM1_ETR(7)
-
A12 46 72 105
PA13
I/O FT
JTMSSWDIO
-
PA13
C11
-
73 106
/
Not connected
G9 47 74 107
VSS_2
S
VSS_2
-
-
F9 48 75 108
VDD_2
S
VDD_2
-
-
A11 49 76 109
PA14
I/O FT
JTCKSWCLK
-
PA14
A10 50 77 110
PA15
I/O FT
JTDI
SPI3_NSS / I2S3_WS
TIM2_CH1_ETR
PA15/ SPI1_NSS
B11 51 78 111
PC10
I/O FT
PC10
UART4_TX / SDIO_D2
USART3_TX
B10 52 79 112
PC11
I/O FT
PC11
UART4_RX / SDIO_D3
USART3_RX
C10 53 80 113
PC12
I/O FT
PC12
UART5_TX / SDIO_CK
USART3_CK
E10
-
81 114
PD0
I/O FT
PD0
FSMC_D2(9)
CAN_RX
D10
-
82 115
PD1
I/O FT
PD1
FSMC_D3(9)
CAN_TX
E9 54 83 116
PD2
I/O FT
PD2
TIM3_ETR / UART5_RX /
SDIO_CMD
-
D9
-
84 117
PD3
I/O FT
PD3
FSMC_CLK
USART2_CTS
C9
-
85 118
PD4
I/O FT
PD4
FSMC_NOE
USART2_RTS
B9
-
86 119
PD5
I/O FT
PD5
FSMC_NWE
USART2_TX
E7
-
- 120
VSS_10
S
VSS_10
-
-
F7
-
- 121
VDD_10
S
VDD_10
-
-
A8
-
87 122
PD6
PD6
FSMC_NWAIT
USART2_RX
I/O FT
DocID16554 Rev 4
33/136
132
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Table 5. STM32F103xF and STM32F103xG pin definitions (continued)
Alternate functions(4)
I / O level(2)
Default
Remap
-
88 123
PD7
I/O FT
PD7
FSMC_NE1 / FSMC_NCE2
USART2_CK
E8
-
- 124
PG9
I/O FT
PG9
FSMC_NE2 / FSMC_NCE3
-
D8
-
- 125
PG10
I/O FT
PG10
FSMC_NCE4_1 / FSMC_NE3
-
C8
-
- 126
PG11
I/O FT
PG11
FSMC_NCE4_2
-
B8
-
- 127
PG12
I/O FT
PG12
FSMC_NE4
-
D7
-
- 128
PG13
I/O FT
PG13
FSMC_A24
-
C7
-
- 129
PG14
I/O FT
PG14
FSMC_A25
-
E6
-
- 130
VSS_11
S
VSS_11
-
-
F6
-
- 131
VDD_11
S
VDD_11
-
-
B7
-
- 132
PG15
I/O FT
PG15
-
-
A7 55 89 133
PB3
I/O FT
JTDO
SPI3_SCK / I2S3_CK/
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
A6 56 90 134
PB4
I/O FT
NJTRST
SPI3_MISO
PB4/ TIM3_CH1
SPI1_MISO
B6 57 91 135
PB5
I/O
PB5
I2C1_SMBA / SPI3_MOSI /
I2S3_SD
TIM3_CH2 /
SPI1_MOSI
C6 58 92 136
PB6
I/O FT
PB6
I2C1_SCL(8)/ TIM4_CH1(8)
USART1_TX
D6 59 93 137
PB7
I/O FT
PB7
I2C1_SDA(8) / FSMC_NADV /
TIM4_CH2(8)
USART1_RX
D5 60 94 138
BOOT0
-
-
LQFP144
A9
LQFP100
LQFP64
Main
function(3)
(after reset)
LFBGA144
Type(1)
Pins
Pin name
I
BOOT0
(8)
C5 61 95 139
PB8
I/O FT
PB8
TIM4_CH3 / SDIO_D4 /
TIM10_CH1
I2C1_SCL/
CAN_RX
B5 62 96 140
PB9
I/O FT
PB9
TIM4_CH4(8) / SDIO_D5 /
TIM11_CH1
I2C1_SDA /
CAN_TX
A5
-
97 141
PE0
I/O FT
PE0
TIM4_ETR / FSMC_NBL0
-
A4
-
98 142
PE1
I/O FT
PE1
FSMC_NBL1
-
E5 63 99 143
VSS_3
S
VSS_3
-
-
F5 64 100 144
VDD_3
S
VDD_3
-
-
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
34/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144/BGA144
packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate
function I/O and debug configuration section in the STM32F10xxx reference manual.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
DocID16554 Rev 4
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132
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Table 6. FSMC pin definition
FSMC
Pins
36/136
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
LQFP100(1)
CF
CF/IDE
PE2
-
-
A23
A23
-
Yes
PE3
-
-
A19
A19
-
Yes
PE4
-
-
A20
A20
-
Yes
PE5
-
-
A21
A21
-
Yes
PE6
-
-
A22
A22
-
Yes
PF0
A0
A0
A0
-
-
-
PF1
A1
A1
A1
-
-
-
PF2
A2
A2
A2
-
-
-
PF3
A3
-
A3
-
-
-
PF4
A4
-
A4
-
-
-
PF5
A5
-
A5
-
-
-
PF6
NIORD
NIORD
-
-
-
PF7
NREG
NREG
-
-
-
PF8
NIOWR
NIOWR
-
-
-
PF9
CD
CD
-
-
-
PF10
INTR
INTR
-
-
-
PF11
NIOS16
NIOS16
-
-
-
PF12
A6
-
A6
-
-
-
PF13
A7
-
A7
-
-
-
PF14
A8
-
A8
-
-
-
PF15
A9
-
A9
-
-
-
PG0
A10
-
A10
-
-
-
PG1
-
-
A11
-
-
-
PE7
D4
D4
D4
DA4
D4
Yes
PE8
D5
D5
D5
DA5
D5
Yes
PE9
D6
D6
D6
DA6
D6
Yes
PE10
D7
D7
D7
DA7
D7
Yes
PE11
D8
D8
D8
DA8
D8
Yes
PE12
D9
D9
D9
DA9
D9
Yes
PE13
D10
D10
D10
DA10
D10
Yes
PE14
D11
D11
D11
DA11
D11
Yes
PE15
D12
D12
D12
DA12
D12
Yes
PD8
D13
D13
D13
DA13
D13
Yes
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Table 6. FSMC pin definition (continued)
FSMC
Pins
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
LQFP100(1)
CF
CF/IDE
PD9
D14
D14
D14
DA14
D14
Yes
PD10
D15
D15
D15
DA15
D15
Yes
PD11
-
-
A16
A16
CLE
Yes
PD12
-
-
A17
A17
ALE
Yes
PD13
-
-
A18
A18
PD14
D0
D0
D0
DA0
D0
Yes
PD15
D1
D1
D1
DA1
D1
Yes
PG2
-
-
A12
-
-
-
PG3
-
-
A13
-
-
-
PG4
-
-
A14
-
-
-
PG5
-
-
A15
-
-
-
PG6
-
-
-
-
INT2
-
PG7
-
-
-
-
INT3
-
PD0
D2
D2
D2
DA2
D2
Yes
PD1
D3
D3
D3
DA3
D3
Yes
PD3
-
-
CLK
CLK
-
Yes
PD4
NOE
NOE
NOE
NOE
NOE
Yes
PD5
NWE
NWE
NWE
NWE
NWE
Yes
PD6
NWAIT
NWAIT
NWAIT
NWAIT
NWAIT
Yes
PD7
-
-
NE1
NE1
NCE2
Yes
PG9
-
-
NE2
NE2
NCE3
-
PG10
NCE4_1
NCE4_1
NE3
NE3
-
-
PG11
NCE4_2
NCE4_2
-
-
-
-
PG12
-
-
NE4
NE4
-
-
PG13
-
-
A24
A24
-
-
PG14
-
-
A25
A25
-
-
PB7
-
-
NADV
NADV
-
Yes
PE0
-
-
NBL0
NBL0
-
Yes
PE1
-
-
NBL1
NBL1
-
Yes
Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
DocID16554 Rev 4
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132
Memory mapping
4
STM32F103xF, STM32F103xG
Memory mapping
The memory map is shown in Figure 7.
38/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Memory mapping
Figure 7. Memory map
2ESERVED
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DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V £ VDD £ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
-#5PIN
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40/136
DocID16554 Rev 4
-36
STM32F103xF, STM32F103xG
5.1.6
Electrical characteristics
Power supply scheme
Figure 10. Power supply scheme
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In Figure 10, the 4.7 µF capacitor must be connected to VDD3.
DocID16554 Rev 4
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132
Electrical characteristics
5.1.7
STM32F103xF, STM32F103xG
Current consumption measurement
Figure 11. Current consumption measurement scheme
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DocID16554 Rev 4
STM32F103xF, STM32F103xG
5.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 7. Voltage characteristics
Symbol
VDD–VSS
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin
VSS − 0.3
VDD + 4.0
Input voltage on any other pin
VSS − 0.3
4.0
Variations between different VDD power pins
-
50
Variations between all the different ground pins
-
50
External main supply voltage (including VDDA
and VDD)(1)
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 5.3.12:
Absolute maximum ratings
(electrical sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum
allowed injected current values.
Table 8. Current characteristics
Symbol
IVDD
IVSS
IIO
IINJ(PIN)(2)
ΣIINJ(PIN)
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines
150
(sink)(1)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
− 25
Injected current on five volt tolerant pins(3)
-5/+0
Injected current on any other
pin(4)
Total injected current (sum of all I/O and control pins)
Unit
mA
±5
(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note 3 below Table 65 on page 110.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 8 MHz.
CIAO
Table 15. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2), all
peripherals enabled
IDD
Supply current
in Run mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
65
65.5
48 MHz
46.5
47
36 MHz
37
37
24 MHz
26.5
27
16 MHz
19
20
8 MHz
11.5
13
72 MHz
34.5
36
48 MHz
25
26
20.5
21
15
16
16 MHz
11
13
8 MHz
7.5
9
External clock(2), all 36 MHz
peripherals disabled 24 MHz
mA
1. Guaranteed by characterization results, not tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
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Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled
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AI
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STM32F103xF, STM32F103xG
Electrical characteristics
Table 16. Maximum current consumption in Sleep mode, code running from Flash or
RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2), all
peripherals enabled
IDD
Supply current
in Sleep mode
External clock(2), all
peripherals disabled
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
47.5
48.5
48 MHz
34
35
36 MHz
27.5
27.5
24 MHz
20
20.5
16 MHz
15
16
8 MHz
9
11
72 MHz
9.5
11.2
48 MHz
7.7
9.5
36 MHz
6.9
8.5
24 MHz
5.9
7.8
16 MHz
5.4
7.2
8 MHz
4.7
6.4
mA
1. Guaranteed by characterization results, not tested in production at VDD max, fHCLK max with peripherals
enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
Parameter
Conditions
Max
VDD/VBA VDD/VBA VDD/VBA TA =
TA =
T = 2.0 V T = 2.4 V T = 3.3 V 85 °C 105 °C
Regulator in run mode, low-speed
and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog),
Supply current in f =8 MHz
CK
Stop mode
Regulator in low-power mode, lowspeed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
44.8
45.3
46.4
810
1680
37.4
37.8
38.7
790
1660
Low-speed internal RC oscillator
Supply current in
and independent watchdog OFF,
Standby mode
low-speed oscillator and RTC OFF
1.8
2.0
2.5
5(2)
8(2)
IDD_VBA Backup domain
Low-speed oscillator and RTC ON
supply current
T
1.05
1.1
1.4
2(2)
2.3(2)
IDD
Unit
µA
1. Typical values are measured at TA = 25 °C.
2. Guaranteed by characterization results, not tested in production..
Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at
different VBAT
values
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STM32F103xF, STM32F103xG
Electrical characteristics
Figure 15. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values
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6
6
6
6
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#
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AI
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 16. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values
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6
6
6
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Figure 17. Typical current consumption in Standby mode versus temperature at
different VDD values
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6
6
6
6
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52/136
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#
AI
STM32F103xF, STM32F103xG
Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load).
•
All peripherals are disabled except if it is explicitly mentioned.
•
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHZ and 2 wait states above).
•
Ambient temperature and VDD supply voltage conditions summarized in Table 10.
•
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
Table 18. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol
Parameter
Conditions
(3)
External clock
IDD
Supply
current in
Run mode
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
fHCLK
All peripherals All peripherals
disabled
enabled(2)
72 MHz
52.5
33.5
48 MHz
36.6
23.8
36 MHz
28.5
18.7
24 MHz
24.1
12.8
16 MHz
14
9.2
8 MHz
7.7
5.4
4 MHz
4.6
3.4
2 MHz
3
2.3
1 MHz
2.2
1.8
500 kHz
1.7
1.5
125 kHz
1.4
1.3
64 MHz
45.5
28.6
48 MHz
35.1
22.4
36 MHz
27.5
17.5
24 MHz
18.9
11.6
16 MHz
12.2
8.2
8 MHz
7.2
4.8
4 MHz
4
2.7
2 MHz
2.3
1.7
1 MHz
1.5
1.2
500 kHz
1.1
0.9
125 kHz
0.75
0.7
Unit
mA
mA
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103xF, STM32F103xG
Table 19. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol Parameter
Conditions
(3)
External clock
IDD
Supply
current in
Sleep mode
fHCLK
All peripherals All peripherals
enabled(2)
disabled
72 MHz
32.5
7
48 MHz
23
5
36 MHz
17.7
4
24 MHz
12.2
3.1
16 MHz
8.4
2.3
8 MHz
4.6
1.5
4 MHz
3
1.3
2 MHz
2.15
1.25
1 MHz
1.7
1.2
500 kHz
1.5
1.15
125 kHz
1.35
1.15
64 MHz
28.7
5.7
48 MHz
22
4.4
36 MHz
17
3.35
11.6
2.3
7.7
1.6
3.9
0.8
2.3
0.7
1.5
0.6
1 MHz
1.1
0.5
500 kHz
0.9
0.5
125 kHz
0.7
0.5
24 MHz
Running on high
16 MHz
speed internal RC
(HSI), AHB prescaler 8 MHz
used to reduce the
4 MHz
frequency
2 MHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Unit
mA
STM32F103xF, STM32F103xG
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed
under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
•
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 7
Table 20. Peripheral current consumption(1)
Peripheral
Current consumption
DMA1
23,06
DMA2
18,47
FSMC
55,14
CRC
2,08
SDIO
32,22
BusMatrix(2)
11,67
AHB (up to 72 MHz)
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Electrical characteristics
STM32F103xF, STM32F103xG
Table 20. Peripheral current consumption(1) (continued)
Peripheral
Current consumption
APB1-Bridge
8,61
TIM2
37,22
TIM3
36,39
TIM4
35,56
TIM5
33,61
TIM6
7,78
TIM7
7,78
TIM12
19,17
TIM13
12,22
TIM14
13,33
(3)
8,33
(3)
SPI3/I2S3
8,33
USART2
12,22
USART3
12,22
UART4
12,22
UART5
12,22
I2C1
10,28
I2C2
10,28
USB
18,89
CAN1
18,89
SPI2/I2S2
APB1 (up to 36 MHz)
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(4)
DAC
9,17
WWDG
3,06
PWR
2,50
BKP
2,78
IWDG
4,44
STM32F103xF, STM32F103xG
Electrical characteristics
Table 20. Peripheral current consumption(1) (continued)
Peripheral
APB2 (up to 72 MHz)
Current consumption
APB2-Bridge
2,78
GPIOA
7,64
GPIOB
7,64
GPIOC
7,64
GPIOD
8,47
GPIOE
8,47
GPIOF
8,19
GPIOG
8,19
SPI1
5,14
USART1
16,67
TIM1
28,47
TIM8
24,31
TIM9
11,81
TIM10
8,47
TIM11
8,47
(5)(6)
17,68
(5)(6)
ADC2
15,54
ADC3(5)(6)
16,43
ADC1
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. The BusMatrix is automatically active when at least one master peripheral is ON.
3. When the I2S is enabled, a current consumption equal to 0.02 mA must be added.
4. When DAC_OU1 or DAC_OUT2 is enabled, a current consumption equal to 0.36 mA must be added.
5. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4/ When
ADON bit in the ADC_CR2 register is set to 1, a current consumption equal to 0.59 mA must be added.
6. When the ADC is enabled, a current consumption equal to 0.1 mA must be added.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 21. High-speed external user clock characteristics
Symbol
Parameter
Conditions
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high level voltage
VHSEL
OSC_IN input pin low level voltage
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
tr(HSE)
tf(HSE)
Cin(HSE)
Typ
Max
Unit
1
8
25
MHz
0.7VDD
-
VDD
VSS
-
0.3VDD
5
-
-
-
V
ns
OSC_IN rise or fall time
(1)
-
-
20
-
-
5
-
pF
-
45
-
55
%
VSS ≤ VIN ≤ VDD
-
-
±1
µA
OSC_IN input capacitance(1)
DuCy(HSE) Duty cycle
IL
Min
OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 22 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Table 22. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
-
32.768
1000
kHz
0.7VDD
-
VDD
VSS
-
0.3VDD
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
-
-
5
-
pF
-
30
-
70
%
VSS ≤ VIN ≤ VD
-
-
±1
µA
Cin(LSE)
V
-
ns
OSC32_IN input capacitance(1)
DuCy(LSE) Duty cycle
IL
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production.
58/136
Min
DocID16554 Rev 4
D
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 18. High-speed external clock source AC timing diagram
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DocID16554 Rev 4
59/136
132
Electrical characteristics
STM32F103xF, STM32F103xG
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 23. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 23. HSE 4-16 MHz oscillator characteristics(1)(2)
Symbol
Conditions
Min
Typ
Max
Unit
Oscillator frequency
-
4
8
16
MHz
RF
Feedback resistor
-
-
200
-
kΩ
C
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 Ω
-
30
-
pF
i2
HSE driving current
VDD= 3.3 V, VIN = VSS
with 30 pF load
-
-
1
mA
gm
Oscillator transconductance
Startup
25
-
-
mA/V
VDD is stabilized
-
2
-
ms
fOSC_IN
tSU(HSE)(4)
Parameter
Startup time
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
60/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 20. Typical application with an 8 MHz crystal
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1. REXT value depends on the crystal characteristics.
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 24. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)(2)
Symbol
Parameter
RF
Feedback resistor
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)
I2
LSE driving current
gm
Oscillator transconductance
tSU(LSE)(3) Startup time
Conditions
Min
Typ
Max
Unit
-
-
5
-
MΩ
RS = 30 kΩ
-
-
15
pF
VDD = 3.3 V, VIN = VSS
-
-
1.4
µA
-
5
-
-
µA/V
TA = 50 °C
-
1.5
-
TA = 25 °C
-
2.5
-
TA = 10 °C
-
4
-
TA = 0 °C
-
6
-
TA = -10 °C
-
10
-
TA = -20 °C
-
17
-
TA = -30 °C
-
32
-
TA = -40 °C
-
60
-
VDD is
stabilized
s
1. Guaranteed by characterization results, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB
layout and humidity.
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 21).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
62/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 21. Typical application with a 32.768 kHz crystal
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5.3.7
Internal clock source characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
High-speed internal (HSI) RC oscillator
Table 25. HSI oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSI
Frequency
-
-
8
DuCy(HSI)
Duty cycle
-
45
-
55
%
-
-
1(3)
%
TA = –40 to 105 °C
–2
-
2.5
%
TA = –10 to 85 °C
–1.5
-
2.2
%
TA = 0 to 70 °C
–1.3
-
2
%
TA = 25 °C
–1.1
-
1.8
%
User-trimmed with the RCC_CR
register(2)
ACCHSI
Accuracy of the HSI
oscillator
Factorycalibrated(4)
MHz
tsu(HSI)(4)
HSI oscillator
startup time
-
1
-
2
µs
IDD(HSI)(4)
HSI oscillator power
consumption
-
80
100
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Guaranteed by characterization results, not tested in production.
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Low-speed internal (LSI) RC oscillator
Table 26. LSI oscillator characteristics (1)
Symbol
fLSI(2)
tsu(LSI)
(3)
IDD(LSI)(3)
Parameter
Min
Typ
Max
Unit
30
40
60
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.65
1.2
µA
Frequency
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
•
Stop or Standby mode: the clock source is the RC oscillator
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 10.
Table 27. Low-power mode wakeup timings
Symbol
tWUSLEEP(1)
tWUSTOP(1)
tWUSTDBY(1)
Parameter
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low-power mode)
5.4
Wakeup from Standby mode
50
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
64/136
DocID16554 Rev 4
µs
µs
STM32F103xF, STM32F103xG
5.3.8
Electrical characteristics
PLL characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 28. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
1
8.0
25
MHz
PLL input clock duty cycle
40
-
60
%
fPLL_OUT
PLL multiplier output clock
16
-
72
MHz
tLOCK
PLL lock time
-
-
200
µs
Jitter
Cycle-to-cycle jitter
-
-
300
ps
fPLL_IN
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 29. Flash memory characteristics
Symbol
tprog
tERASE
tME
IDD
Vprog
Min
Typ
Max(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
52.5
70
µs
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
-
-
28
mA
Write mode
fHCLK = 72 MHz, VDD = 3.3 V
-
-
7
mA
Erase mode
fHCLK = 72 MHz, VDD = 3.3 V
-
-
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
-
-
50
µA
-
2
-
3.6
V
Parameter
Supply current
Programming voltage
Conditions
1. Guaranteed by design, not tested in production.
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 30. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
1 kcycle
(2)
10 kcycles
at TA = 105 °C
10
(2)
20
at TA = 55 °C
1. Guaranteed by characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
66/136
Min(1)
DocID16554 Rev 4
Unit
kcycles
Years
STM32F103xF, STM32F103xG
5.3.10
Electrical characteristics
FSMC characteristics
Asynchronous waveforms and timings
Figure 22 through Figure 25 represent asynchronous waveforms and Table 31 through
Table 35 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
Note:
•
AddressSetupTime = 0
•
AddressHoldTime = 1
•
DataSetupTime = 1
On all tables, the tHCLK is the HCLK clock period.
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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Note:
FSMC_BusTurnAroundDuration = 0.
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
Unit
5tHCLK + 0.5
5tHCLK + 2
ns
0.5
1.5
ns
5tHCLK – 1
5tHCLK + 1
ns
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
tw(NOE)
FSMC_NOE low time
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
3
ns
th(A_NOE)
Address hold time after FSMC_NOE high
0
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0.5
-
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
2tHCLK - 1
-
ns
2tHCLK - 1
-
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
0
ns
tw(NADV)
FSMC_NADV low time
-
tHCLK + 2
ns
1. CL = 15 pF.
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
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1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
68/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3tHCLK + 0.5
3tHCLK + 1.5 ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tHCLK + 0.5
tHCLK + 1.5
ns
tw(NWE)
FSMC_NWE low time
tHCLK – 0.5
tHCLK + 1
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
tHCLK – 0.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
0
ns
th(A_NWE)
Address hold time after FSMC_NWE high
tHCLK
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
1.5
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tHCLK – 1.5
-
ns
tv(Data_NE)
FSMC_NEx low to Data valid
-
tHCLK
ns
th(Data_NWE)
Data hold time after FSMC_NWE high
tHCLK
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
0
ns
tw(NADV)
FSMC_NADV low time
-
tHCLK + 1.5
ns
1. CL = 15 pF.
Table 33. Asynchronous multiplexed read timings
Symbol
Parameter
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
tw(NOE)
FSMC_NOE low time
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
tv(A_NE)
Min
7tHCLK + 0.5
3tHCLK + 0.5
4tHCLK – 1
Max
7tHCLK + 2
3tHCLK + 1.5
4tHCLK + 1
0.5
-
FSMC_NEx low to FSMC_A valid
-
0
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC NADV high
tHCLK
-
th(A_NOE)
Address hold time after FSMC_NOE high
tHCLK – 2
-
th(BL_NOE)
FSMC_BL time after FSMC_NOE high
0.5
-
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
tsu(Data_NE)
Data to FSMC_NEx high setup time
4tHCLK – 0.5
-
4tHCLK – 1
-
tsu(Data_NOE) Data to FSMC_NOE high setup time
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
DocID16554 Rev 4
Unit
ns
69/136
132
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms
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Table 34. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
Parameter
Max
Unit
tw(NE)
FSMC_NE low time
7tHCLK + 0.5
7tHCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
3tHCLK + 0.5
3tHCLK + 1.5
ns
tw(NOE)
FSMC_NOE low time
4tHCLK – 1
4tHCLK + 1
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
0
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
ns
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
tHCLK
-
ns
th(A_NOE)
Address hold time after FSMC_NOE high
tHCLK -2
-
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0.5
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
4tHCLK - 0.5
-
ns
4tHCLK - 1
-
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
70/136
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DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Table 34. Asynchronous multiplexed PSRAM/NOR read timings(1) (continued)
Symbol
Parameter
Min
Max
Unit
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
1. CL = 15 pF.
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms
WZ 1(
)60&B1([
)60&B12(
WY 1:(B1(
WZ 1:(
W K 1(B1:(
)60&B1:(
WK $B1:(
WY $B1(
)60&B$> @
$GGUHVV
WY %/B1(
WK %/B1:(
)60&B1%/> @
1%/
W Y $B1(
W Y 'DWDB1$'9
$GGUHVV
)60&B$'> @
W Y 1$'9B1(
WK 'DWDB1:(
'DWD
WK $'B1$'9
WZ 1$'9
)60&B1$'9
DL %
Table 35. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
Parameter
Min
Max
Unit
5tHCLK + 0.5
5tHCLK + 2
ns
tHCLK + 1
tHCLK + 1.5
ns
3tHCLK + 0.5
3tHCLK + 1
ns
tHCLK – 0.5
-
ns
tw(NE)
FSMC_NE low time
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tw(NWE)
FSMC_NWE low time
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
3.5
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
0
1
ns
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 1.5
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
tHCLK – 0.5
-
ns
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 35. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
Parameter
th(A_NWE)
Address hold time after FSMC_NWE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
Min
Max
Unit
4tHCLK – 2
-
ns
-
0.5
ns
tHCLK – 1.5
-
ns
-
tHCLK + 6
ns
tHCLK – 0.5
-
ns
1. CL = 15 pF.
Synchronous waveforms and timings
Figure 26 through Figure 29 represent synchronous waveforms and Table 37 through
Table 39 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
72/136
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 26. Synchronous multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,
.%X,
T D#,+,
.%X(
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!)6
TD#,+,
!6
&3-#?!;=
TD#,+(
./%,
TD#,+,
./%(
&3-#?./%
TD#,+,
!$)6
TSU!$6
#,+(
TD#,+,
!$6
&3-#?!$;=
TH#,+(
!$6
!$;=
TSU!$6
#,+(
$
TSU.7!)46
#,+(
TH#,+(
!$6
$
$
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&' B 7!)40/, B
TSU.7!)46
#,+(
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&' B 7!)40/, B
TSU.7!)46
#,+(
TH#,+(
.7!)46
AII
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 36. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1.5
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
14
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1
-
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
11
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0.5
-
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
2
-
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high
0
-
ns
8
-
ns
2
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
1. CL = 15 pF.
74/136
Min
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 27. Synchronous multiplexed PSRAM write timings
"53452.
TW#,+
TW#,+
&3-#?#,+
$ATALATENCY
TD#,+,
.%X,
TD#,+,
.%X(
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!6
TD#,+,
!)6
&3-#?!;=
TD#,+,
.7%,
TD#,+,
.7%(
&3-#?.7%
TD#,+,
!$)6
TD#,+,
!$6
&3-#?!$;=
TD#,+,
$ATA
TD#,+,
$ATA
!$;=
$
$
&3-#?.7!)4
7!)4#&' B 7!)40/, B
TSU.7!)46
#,+(
TH#,+(
.7!)46
TD#,+,
.",(
&3-#?.",
AIG
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 37. Synchronous multiplexed PSRAM write timings(1)
Symbol
Parameter
Max
Unit
27.5
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
1
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
1.5
-
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
10
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
1
-
ns
td(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low
-
6
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
-
ns
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
-
ns
1. CL = 15 pF.
76/136
Min
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
TD#,+,
.%X,
TD#,+,
.%X(
$ATALATENCY
&3-#?.%X
TD#,+,
.!$6,
TD#,+,
.!$6(
&3-#?.!$6
TD#,+,
!)6
TD#,+,
!6
&3-#?!;=
TD#,+(
./%,
TD#,+,
./%(
&3-#?./%
TSU$6
#,+(
TH#,+(
$6
TSU$6
#,+(
&3-#?$;=
$
TSU.7!)46
#,+(
TH#,+(
$6
$
$
TH#,+(
.7!)46
&3-#?.7!)4
7!)4#&' B 7!)40/, B
TSU.7!)46
#,+(
T H#,+(
.7!)46
&3-#?.7!)4
7!)4#&' B 7!)40/, B
TSU.7!)46
#,+(
TH#,+(
.7!)46
AIH
Table 38. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Min
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
1.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
2
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
0.5
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
1
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
2
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
tHCLK + 1
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1.5
-
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high
3.5
-
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
0
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
7
-
ns
2
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
1. CL = 15 pF.
Figure 29. Synchronous non-multiplexed PSRAM write timings
%867851
WZ &/.
WZ &/.
)60&B&/.
'DWDODWHQF\
WG &/./1([/
W G &/./1([+
)60&B1([
WG &/./1$'9/
WG &/./1$'9+
)60&B1$'9
WG &/./$,9
WG &/./$9
)60&B$> @
WG &/.+12(/
WG &/./12(+
)60&B12(
WG &/./$'9
WG &/./$',9
WVX $'9&/.+
)60&B$'> @
$'> @
WK &/.+$'9
WVX $'9&/.+
'
WVX 1:$,79&/.+
WK &/.+$'9
'
WK &/.+1:$,79
)60&B1:$,7
:$,7&)* E:$,732/E
WVX 1:$,79&/.+
WK &/.+1:$,79
)60&B1:$,7
:$,7&)* E:$,732/E
WVX 1:$,79&/.+
WK &/.+1:$,79
DL K
Table 39. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
78/136
Parameter
Min
Max
Unit
27.6
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0.5
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1.5
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
1.5
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
1
ns
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
1.5
-
ns
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
-
2.5
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
0.5
-
ns
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
-
ns
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
1. CL = 15 pF.
PC Card/CompactFlash controller waveforms and timings
Figure 30 through Figure 35 represent synchronous waveforms and Table 42 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
•
COM.FSMC_SetupTime = 0x04;
•
COM.FSMC_WaitSetupTime = 0x07;
•
COM.FSMC_HoldSetupTime = 0x04;
•
COM.FSMC_HiZSetupTime = 0x00;
•
ATT.FSMC_SetupTime = 0x04;
•
ATT.FSMC_WaitSetupTime = 0x07;
•
ATT.FSMC_HoldSetupTime = 0x04;
•
ATT.FSMC_HiZSetupTime = 0x00;
•
IO.FSMC_SetupTime = 0x04;
•
IO.FSMC_WaitSetupTime = 0x07;
•
IO.FSMC_HoldSetupTime = 0x04;
•
IO.FSMC_HiZSetupTime = 0x00;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0;
Figure 30. PC Card/CompactFlash controller waveforms for common memory read
access
)60&B1&(B
)60&B1&(B
WK 1&([$,
WY 1&([$
)60&B$> @
WK 1&([15(*
WK 1&([1,25'
WK 1&([1,2:5
WG 15(*1&([
WG 1,25'1&([
)60&B15(*
)60&B1,2:5
)60&B1,25'
)60&B1:(
WG 1&(B12(
)60&B12(
WZ 12(
WVX '12(
WK 12('
)60&B'> @
DL E
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
DocID16554 Rev 4
79/136
132
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 31. PC Card/CompactFlash controller waveforms for common memory write
access
)60&B1&(B
)60&B1&(B +LJK
WY 1&(B$
WK 1&(B$,
)60&B$> @
WK 1&(B15(*
WK 1&(B1,25'
WK 1&(B1,2:5
WG 15(*1&(B
WG 1,25'1&(B
)60&B15(*
)60&B1,2:5
)60&B1,25'
WG 1&(B1:(
WZ 1:(
WG 1:(1&(B
)60&B1:(
)60&B12(
0(0[+,=
WG '1:(
WY 1:('
WK 1:('
)60&B'> @
DL E
80/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read
access
)60&B1&(B
WY 1&(B$
WK 1&(B$,
)60&B1&(B +LJK
)60&B$> @
)60&B1,2:5
)60&B1,25'
WG 15(*1&(B
WK 1&(B15(*
)60&B15(*
)60&B1:(
WG 1&(B12(
WZ 12(
WG 12(1&(B
)60&B12(
WVX '12(
WK 12('
)60&B'> @
DL E
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
DocID16554 Rev 4
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132
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write
access
)60&B1&(B
)60&B1&(B
+LJK
WY 1&(B$
WK 1&(B$,
)60&B$> @
)60&B1,2:5
)60&B1,25'
WG 15(*1&(B
WK 1&(B15(*
)60&B15(*
WG 1&(B1:(
WZ 1:(
)60&B1:(
WG 1:(1&(B
)60&B12(
WY 1:('
)60&B'> @
DL E
1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).
Figure 34. PC Card/CompactFlash controller waveforms for I/O space read access
)60&B1&(B
)60&B1&(B
WK 1&(B$,
WY 1&([$
)60&B$> @
)60&B15(*
)60&B1:(
)60&B12(
)60&B1,2:5
WZ 1,25'
WG 1,25'1&(B
)60&B1,25'
WVX '1,25'
WG 1,25''
)60&B'> @
DL %
82/136
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access
)60&B1&(B
)60&B1&(B
WY 1&([$
WK 1&(B$,
)60&B$> @
)60&B15(*
)60&B1:(
)60&B12(
)60&B1,25'
WG 1&(B1,2:5
WZ 1,2:5
)60&B1,2:5
$77[+,=
WY 1,2:5'
WK 1,2:5'
)60&B'> @
DL F
Table 40. Switching characteristics for PC Card/CF read and write cycles in
attribute/common space
Symbol
Parameter
Min
Max
tv(NCEx-A)
FSMC_NCEx low to FSMC_Ay valid
-
0
th(NCEx-AI)
FSMC_NCEx high to FSMC_Ax invalid
0
-
td(NREG-NCEx)
FSMC_NCEx low to FSMC_NREG valid
-
2
th(NCEx-NREG)
FSMC_NCEx high to FSMC_NREG invalid
tHCLK + 4
-
td(NCEx_NWE)
FSMC_NCEx low to FSMC_NWE low
-
5tHCLK + 1
td(NCEx_NOE)
FSMC_NCEx low to FSMC_NOE low
-
5tHCLK + 1
tw(NOE)
FSMC_NOE low width
8tHCLK - 0.5
8tHCLK + 1
td(NOE-NCEx
FSMC_NOE high to FSMC_NCEx high
5tHCLK - 0.5
-
tsu(D-NOE)
FSMC_D[15:0] valid data before FSMC_NOE high
32
-
th(NOE-D)
FSMC_NOE high to FSMC_D[15:0] invalid
tHCLK
-
tw(NWE)
FSMC_NWE low width
8tHCLK – 1
8tHCLK + 4
td(NWE_NCEx)
FSMC_NWE high to FSMC_NCEx high
5tHCLK + 1.5
-
td(NCEx-NWE)
FSMC_NCEx low to FSMC_NWE low
-
5tHCLK + 1
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
-
0
th(NWE-D)
FSMC_NWE high to FSMC_D[15:0] invalid
11tHCLK
-
td(D-NWE)
FSMC_D[15:0] valid before FSMC_NWE high
13tHCLK + 2.5
-
DocID16554 Rev 4
Unit
ns
83/136
132
Electrical characteristics
STM32F103xF, STM32F103xG
Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space
Symbol
Parameter
tw(NIOWR)
FSMC_NIOWR low width
tv(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
th(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
Min
Max
Unit
8 THCLK
-
ns
-
5 THCLK 4
ns
11THCLK 7
-
ns
td(NCE4_1-NIOWR)
FSMC_NCE4_1 low to FSMC_NIOWR valid
-
5THCLK +
1
ns
th(NCEx-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK 2.5
-
ns
td(NIORD-NCEx)
FSMC_NCEx low to FSMC_NIORD valid
-
5THCLK 0.5
ns
th(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD) valid
5 THCLK 0.5
-
ns
8THCLK
-
ns
tw(NIORD)
FSMC_NIORD low width
tsu(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
28
-
ns
td(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high
3
-
ns
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms and Table 43 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
84/136
•
COM.FSMC_SetupTime = 0x00;
•
COM.FSMC_WaitSetupTime = 0x02;
•
COM.FSMC_HoldSetupTime = 0x01;
•
COM.FSMC_HiZSetupTime = 0x00;
•
ATT.FSMC_SetupTime = 0x00;
•
ATT.FSMC_WaitSetupTime = 0x02;
•
ATT.FSMC_HoldSetupTime = 0x01;
•
ATT.FSMC_HiZSetupTime = 0x00;
•
Bank = FSMC_Bank_NAND;
•
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
•
ECC = FSMC_ECC_Enable;
•
ECCPageSize = FSMC_ECCPageSize_512Bytes;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0;
DocID16554 Rev 4
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 36. NAND controller waveforms for read access
)60&B1&([ /RZ
$/( )60&B$
&/( )60&B$
)60&B1:(
WK 12($/(
WG $/(12(
)60&B12( 15(
WVX '12(
WK 12('
)60&B'> @
DL E
Figure 37. NAND controller waveforms for write access
)60&B1&([
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WG $/(1:(
WK 1:($/(
)60&B1:(
)60&B12( 15(
WY 1:('
WK 1:('
)60&B'> @
AIC
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 38. NAND controller waveforms for common memory read access
)60&B1&([ /RZ
$/( )60&B$
&/( )60&B$
WG $/(12(
WK 12($/(
)60&B1:(
WZ 12(
)60&B12(
WVX '12(
WK 12('
)60&B'> @
DL E
Figure 39. NAND controller waveforms for common memory write access
)60&B1&([ /RZ
$/( )60&B$
&/( )60&B$
WG $/(1:(
WZ 1:(
WK 1:($/(
)60&B1:(
)60&B12(
WG '1:(
WY 1:('
WK 1:('
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DL E
Table 42. Switching characteristics for NAND Flash read cycles(1)
Symbol
Parameter
Max
Unit
3tHCLK – 1
3tHCLK + 1
ns
tw(NOE)
FSMC_NOE low width
tsu(D-NOE)
FSMC_D[15:0] valid data before FSMC_NOE
high
13
-
ns
th(NOE-D)
FSMC_D[15:0] valid data after FSMC_NOE high
0
-
ns
td(ALE-NOE)
FSMC_ALE valid before FSMC_NOE low
-
2tHCLK
ns
th(NOE-ALE)
FSMC_NWE high to FSMC_ALE invalid
2tHCLK
-
ns
1. CL = 15 pF.
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STM32F103xF, STM32F103xG
Electrical characteristics
Table 43. Switching characteristics for NAND Flash write cycles(1)
Symbol
Parameter
Min
Max
Unit
3tHCLK
3tHCLK
ns
-
0
ns
tw(NWE)
FSMC_NWE low width
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
th(NWE-D)
FSMC_NWE high to FSMC_D[15:0] invalid
2tHCLK + 2
-
ns
td(ALE-NWE)
FSMC_ALE valid before FSMC_NWE low
-
3tHCLK + 1.5
ns
th(NWE-ALE)
FSMC_NWE high to FSMC_ALE invalid
3tHCLK + 8
-
ns
td(ALE-NOE)
FSMC_ALE valid before FSMC_NOE low
-
2tHCLK
ns
th(NOE-ALE)
FSMC_NWE high to FSMC_ALE invalid
2tHCLK
-
ns
1. CL = 15 pF.
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Electrical characteristics
5.3.11
STM32F103xF, STM32F103xG
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, LQFP144, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 72 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25 °C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
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STM32F103xF, STM32F103xG
Electrical characteristics
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45. EMI characteristics
Symbol Parameter
SEMI
5.3.12
Conditions
Max vs. [fHSE/fHCLK]
Monitored
frequency band
Unit
8/48 MHz 8/72 MHz
0.1 to 30 MHz
VDD = 3.3 V, TA = 25 °C,
30 to 130 MHz
LQFP144 package
Peak level
compliant with IEC
130 MHz to 1GHz
61967-2
SAE EMI Level
8
12
31
21
28
33
4
4
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 46. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
Class
Maximum
value(1)
2
2000
III
500
Electrostatic discharge
TA = +25 °C, conforming
voltage (human body model) to JESD22-A114
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C, conforming
to JESD22-C101
Unit
V
1. Guaranteed by characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
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Electrical characteristics
STM32F103xF, STM32F103xG
Table 47. Electrical sensitivities
Symbol
LU
5.3.13
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 48
Table 48. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
90/136
Description
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
Injected current on all FT pins
-5
+0
Injected current on any other pin
-5
+5
DocID16554 Rev 4
Unit
mA
STM32F103xF, STM32F103xG
5.3.14
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 49. I/O static characteristics
Symbol
VIL
Parameter
Standard IO input low
level voltage
IO FT(1) input low level
voltage
Standard IO input high
level voltage
VIH
Vhys
IO FT(1) input high level
voltage
Standard IO Schmitt
trigger voltage
hysteresis(2)
Conditions
Min
Typ
Max
Unit
–0.3
-
0.28*(VDD-2
V)+0.8 V
V
–0.3
-
0.32*(VDD-2
V)+0.75 V
V
0.41*(VDD-2
V)+1.3 V
-
VDD+0.3
V
0.42*(VDD-2
V)+1 V
-
200
-
-
mV
5% VDD(3)
-
-
mV
VSS ≤ VIN ≤ VDD
Standard I/Os
-
-
±1
VIN= 5 V, I/O FT
-
-
3
-
VDD > 2 V
VDD ≤ 2 V
Input leakage current (4)
V
5.2
-
IO FT Schmitt trigger
voltage hysteresis(2)
Ilkg
5.5
µA
RPU
Weak pull-up equivalent
resistor(5)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in
production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 40 and Figure 41 for standard I/Os, and
in Figure 42 and Figure 43 for 5 V tolerant I/Os.
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STM32F103xF, STM32F103xG
Figure 40. Standard I/O input characteristics - CMOS port
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Figure 41. Standard I/O input characteristics - TTL port
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7)(MIN
44,REQUIREMENTS 6)( 6
6
6 )( $$
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7),MAX
6 ), 6 $$
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6$$6
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Figure 42. 5 V tolerant I/O input characteristics - CMOS port
6)(6),6
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NOTGUARANTEED
6 ), 6 $$
6 $$
IRMENT6 ),
DARDREQU
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6 )( 6 $$
REQUIRE
TANDARD
#-/3S
6$$6
6$$
AIB
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STM32F103xF, STM32F103xG
Electrical characteristics
Figure 43. 5 V tolerant I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENT6 )( 6
6 $$
6 )(
7)(MIN
7),MAX
)NPUTRANGE
NOTGUARANTEED
6 ),
6 $$
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6$$6
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 8).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 8).
Output voltage levels
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10. All I/Os are CMOS and TTL compliant.
Table 50. Output voltage characteristics
Symbol
Parameter
VOL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL (1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH (2)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
DocID16554 Rev 4
Conditions
Min
Max
TTL port(3)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD–0.4
-
-
0.4
2.4
-
CMOS port(3)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
Unit
V
V
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Electrical characteristics
STM32F103xF, STM32F103xG
Table 50. Output voltage characteristics (continued)
Symbol
Parameter
VOL(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
VOL(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
Conditions
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
Min
Max
-
1.3
Unit
V
VDD–1.3
-
-
0.4
V
VDD–0.4
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
4. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 44 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 51. I/O AC characteristics(1)
MODEx[1:0]
Symbol
bit value(1)
Parameter
Conditions
Min
Max
Unit
-
2
MHz
-
125(3)
-
125(3)
-
10
-
25(3)
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
-
20
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
10
-
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
10
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
CL = 50 pF, VDD = 2 V to 3.6 V
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
01
tf(IO)out
Output high to low
level fall time
tr(IO)out
Output low to high
level rise time
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
-
tEXTIpw
frequency(2)
Output high to low
level fall time
Output low to high
level rise time
ns
CL = 50 pF, VDD = 2 V to 3.6 V
Pulse width of external
signals detected by
the EXTI controller
MHz
ns
ns
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 44.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F103xF, STM32F103xG
Figure 44. I/O AC characteristics definition
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5.3.15
DLG
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 49).
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 52. NRST pin characteristics
Symbol
Conditions
Min
Typ
Max
VIL(NRST)(1) NRST Input low level voltage
-
–0.5
-
0.8
VIH(NRST)(1)
NRST Input high level voltage
-
2
-
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
VIN = VSS
30
40
50
kΩ
-
-
-
100
ns
-
300
-
-
ns
Weak pull-up equivalent resistor(2)
RPU
VF(NRST)
Parameter
(1)
NRST Input filtered pulse
VNF(NRST)(1) NRST Input not filtered pulse
Unit
V
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
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Electrical characteristics
Figure 45. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.
5.3.16
TIM timer characteristics
The parameters given in Table 53 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 53. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
fTIMxCLK = 72 MHz
Min
Max
Unit
1
-
tTIMxCLK
13.9
-
ns
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
0
fTIMxCLK/2
MHz
0
36
MHz
Timer resolution
-
16
bit
16-bit counter clock period 1
when internal clock is
fTIMxCLK = 72 MHz 0.0139
selected
65536
tTIMxCLK
910
µs
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 72 MHz
-
59.6
s
-
tMAX_COUNT Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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Electrical characteristics
5.3.17
STM32F103xF, STM32F103xG
Communications interfaces
I2C interface characteristics
The STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG
performance line I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 54. Refer also to Section 5.3.14: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 54. I2C characteristics
Symbol
Standard mode
I2C(1)(2)
Parameter
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
-
3450(3)
-
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
tSP
Pulse width of the spikes
that are suppressed by the
analog filter for standard and
fast mode
0
50(4)
0
50(4)
μs
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
mode maximum clock speed of 400 kHz.
3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region on the falling edge of SCL.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
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µs
ns
µs
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 46. I2C bus AC waveforms and measurement circuit
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
2. Rs: Series protection resistors.
3. Rp: Pull-up resistors.
4. VDD_I2C : I2C bus supply
Table 55. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
0x801E
300
0x8028
200
0x803C
100
0x00B4
50
0x0168
20
0x0384
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
STM32F103xF, STM32F103xG
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 56. SPI characteristics
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Min
Max
Master mode
-
18
Slave mode
-
18
-
8
ns
%
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
tsu(NSS)(1)
NSS setup time
Slave mode
4tPCLK
-
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
Master mode
5
-
Slave mode
5
-
Master mode
5
-
Slave mode
4
-
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tw(SCKH)(1)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
(1)
th(MI)
th(SI)(1)
ta(SO)(1)(2)
tdis(SO)
Data input setup time
(1)(3)
Data input hold time
Data output disable time
Slave mode
2
10
(1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time
Master mode (after enable edge)
-
5
Slave mode (after enable edge)
15
-
Master mode (after enable edge)
2
-
tv(SO)
th(SO)(1)
th(MO)(1)
Data output hold time
Unit
MHz
1. Guaranteed by characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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STM32F103xF, STM32F103xG
Electrical characteristics
Figure 47. SPI timing diagram - slave mode and CPHA = 0
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