STM32F207ZGT6

STM32F205xx STM32F207xx Arm®-based 32-bit MCU, 150 DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces and camera Datasheet - production data Features &"'!  Core: Arm® 32-bit Cortex®-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)  Memories – Up to 1 Mbyte of Flash memory – 512 bytes of OTP memory – Up to 128 + 4 Kbytes of SRAM – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes  Clock, reset and supply management – From 1.8 to 3.6 V application supply + I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration  Low-power modes – Sleep, Stop and Standby modes – VBAT supply for RTC, 20 × 32 bit backup registers, and optional 4 Kbytes backup SRAM LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) WLCSP64+2 (0.400 mm pitch) UFBGA176 (10 × 10 mm) LQFP144 (20 × 20mm) LQFP176 (24 × 24 mm)   Up to 140 I/O ports with interrupt capability: – Up to 136 fast I/Os up to 60 MHz – Up to 138 5 V-tolerant I/Os  Up to 15 communication interfaces – Up to three I2C interfaces (SMBus/PMBus) – Up to four USARTs and two UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to three SPIs (30 Mbit/s), two with muxed I2S to achieve audio class accuracy via audio PLL or external PLL – 2 × CAN interfaces (2.0B Active) – SDIO interface  2 × 12-bit D/A converters  Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII  General-purpose DMA: 16-stream controller with centralized FIFOs and burst support  8- to 14-bit parallel camera interface (48 Mbyte/s max.)  Up to 17 timers – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input  CRC calculation unit  3 × 12-bit, 0.5 µs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode  96-bit unique ID  Debug mode: Serial wire debug (SWD), JTAG, and Cortex®-M3 Embedded Trace Macrocell™ July 2020 This is information on a product in full production. DS6329 Rev 18 1/181 www.st.com STM32F20xxx Table 1. Device summary Reference Part numbers STM32F205xx STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF, STM32F205VG STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207xx STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG 2/181 DS6329 Rev 18 STM32F20xxx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . . . 20 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 20 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29 3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DS6329 Rev 18 3/181 6 Contents STM32F20xxx 3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 36 3.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 36 3.29 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 37 3.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.32 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.33 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.34 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.35 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1 4/181 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DS6329 Rev 18 STM32F20xxx Contents 6.1.7 7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 74 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 74 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 75 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.7 Wakeup time from Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 95 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 100 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 146 6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 146 6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.2 WLCSP64+2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.3 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 DS6329 Rev 18 5/181 6 Contents STM32F20xxx 7.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.6 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6/181 DS6329 Rev 18 STM32F20xxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F205xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F207xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F20x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 72 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 74 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 74 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . . 77 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 84 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 84 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DS6329 Rev 18 7/181 8 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. 8/181 STM32F20xxx Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 108 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 108 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 119 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 119 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 120 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 129 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 130 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 136 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 143 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SD/MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 WLCSP64+2 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 WLCSP64+2 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . 152 LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 164 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DS6329 Rev 18 STM32F20xxx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Compatible board design between STM32F10x and STM32F2xx for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design between STM32F10x and STM32F2xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design between STM32F10x and STM32F2xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F20x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Regulator OFF / internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Regulator OFF / internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF: slow VDD slope, power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup in regulator OFF: fast VDD slope, power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F20x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F20x WLCSP64+2 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F20x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F20x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F20x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F20x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Number of wait states versus fCPU and VDD range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 80 Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 80 Typical current consumption vs. temperature in Sleep mode, peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical current consumption vs. temperature in Sleep mode, peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical current consumption vs. temperature in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . 83 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DS6329 Rev 18 9/181 11 List of figures Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. 10/181 STM32F20xxx FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 117 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 124 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 125 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 129 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 130 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 131 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 132 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 136 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 141 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 142 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 145 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 145 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Device marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 WLCSP64+2 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 WLCSP64+2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DS6329 Rev 18 STM32F20xxx Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. List of figures LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 LQFP176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 UFBGA176+25 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 UFBGA176+25 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 DS6329 Rev 18 11/181 11 Introduction 1 STM32F20xxx Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers, based on Arm®(a) cores. For more details on the whole STMicroelectronics STM32 family refer to Section 2.1: Full compatibility throughout the family. The STM32F205xx and STM32F207xx datasheet must be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document. For information on programming, erasing and protection of the internal Flash memory, refer to the STM32F20x/STM32F21x Flash programming manual (PM0059). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex®-M3 core refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/181 DS6329 Rev 18 STM32F20xxx 2 Description Description The STM32F20x family is based on the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices also feature an adaptive real-time memory accelerator (ART Accelerator™) that allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. This performance has been validated using the CoreMark® benchmark. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true number random generator (RNG). They also feature standard and advanced communication interfaces. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), and a camera interface for CMOS sensors. The devices also feature standard peripherals.  Up to three I2Cs  Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization.  Four USARTs and two UARTs  A USB OTG high-speed with full-speed capability (with the ULPI)  A second USB OTG (full-speed)  Two CANs  An SDIO interface  Ethernet and camera interface available on STM32F207xx devices only. The STM32F205xx and STM32F207xx devices operate in the –40 to +105 °C temperature range from a 1.8 V to 3.6 V power supply. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). A comprehensive set of power-saving modes enables the design of low-power applications. STM32F205xx and STM32F207xx devices are offered in various packages, ranging from 64 to 176 pins. The set of included peripherals changes with the chosen device.These features make the STM32F205xx and STM32F207xx microcontroller family suitable for a wide range of applications:  Motor drive and application control  Medical equipment  Industrial applications: PLC, inverters, circuit breakers  Printers, and scanners  Alarm systems, video intercom, and HVAC  Home audio appliances Figure 4 shows the general block diagram of the device family. DS6329 Rev 18 13/181 180 Peripherals Flash memory in Kbytes System SRAM in Kbytes (SRAM1+SRAM2) Backup FSMC memory controller STM32F205Rx 128 256 64 (48+16) 96 (80+16) 512 1024 128 256 64 (48+16) 96 (80+16) 4 512 STM32F205Zx 768 1024 128 (112+16) 4 256 512 96 (80+16) 768 1024 128 (112+16) 4 Yes(1) No No General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes DS6329 Rev 18 Random number generator Yes 2 3/(2)(2) SPI/(I S) 2 I C 3 USART 4 2 Comm. interfaces UART USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface GPIOs No 51 SDIO 12-bit ADC Number of channels 12-bit DAC Number of channels 82 114 16 24 Yes 3 16 Yes 2 120 MHz 1.8 V to 3.6 V(3) STM32F20xxx Maximum CPU frequency Operating voltage 768 128 (112+16) Ethernet Timers STM32F205Vx Description 14/181 Table 2. STM32F205xx features and peripheral counts Peripherals STM32F205Rx STM32F205Zx Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F205Vx STM32F20xxx Table 2. STM32F205xx features and peripheral counts (continued) Junction temperature: –40 to + 125 °C LQFP64 LQFP64 LQFP64 LQFP64 WLCSP64+2 WLCSP64+2 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). Table 3. STM32F207xx features and peripheral counts Peripherals DS6329 Rev 18 Flash memory in Kbytes SRAM in Kbytes System (SRAM1+SRAM2) Backup FSMC memory controller Ethernet Timers STM32F207Vx 256 512 768 STM32F207Zx 1024 256 512 STM32F207Ix 768 1024 256 512 768 1024 128 (112+16) 4 Yes(1) Yes General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description 15/181 Peripherals STM32F207Vx STM32F207Zx 2 SPI/(I S) 3/(2) I2C 3 USART Comm. interfaces UART 4 2 USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface GPIOs Yes 82 114 140 SDIO 12-bit ADC Number of channels Yes 3 16 24 24 DS6329 Rev 18 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 120 MHz 1.8 V to 3.6 V(3) Operating voltage Ambient temperatures: –40 to +85 °C/–40 to +105 °C Operating temperatures Package STM32F207Ix (2) Description 16/181 Table 3. STM32F207xx features and peripheral counts (continued) Junction temperature: –40 to + 125 °C LQFP100 LQFP144 LQFP176/ UFBGA176 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). STM32F20xxx STM32F20xxx 2.1 Description Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family, whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F205xx and STM32F207xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F20x family remains simple as only a few pins are impacted. Figure 1, Figure 2 and Figure 3 provide compatible board designs between the STM32F20x and the STM32F10xxx family. Figure 1. Compatible board design between STM32F10x and STM32F2xx for LQFP64 package VSS 48 49 VSS 0 Ω resistor or soldering bridge present for the STM32F10x configuration, not present in the STM32F2xx configuration 33 32 47 31 LQFP64 VSS 64 VSS 17 1 16 MS41486V1 DS6329 Rev 18 17/181 180 Description STM32F20xxx Figure 2. Compatible board design between STM32F10x and STM32F2xx for LQFP100 package 0 Ω resistor or soldering bridge present for the STM32F10x configuration, not present in the STM32F2xx configuration VSS 51 75 76 50 73 Two 0 Ω resistors connected to - VSS for STM32F10x - VDD, VSS or NC for STM32F2xx 49 LQFP100 VSS VSS 99 (RFU) 19 100 20 26 1 VDD 25 VSS VSS VDD VSS for STM32F10x, VDD for STM32F2xx VSS MS41487V1 1. RFU = reserved for future use. Figure 3. Compatible board design between STM32F10x and STM32F2xx for LQFP144 package 0 Ω resistor or soldering bridge present for the STM32F10x configuration, not present in the STM32F2xx configuration VSS 108 109 106 73 72 71 LQFP144 VSS VSS 143 (RFU) 30 144 VDD 31 37 1 36 VSS Two 0 Ω resistors connected to - VSS for STM32F10x - VDD, VSS or NC for STM32F2xx VSS VDD VSS MS41488V1 1. RFU = reserved for future use. 18/181 DS6329 Rev 18 STM32F20xxx Description Figure 4. STM32F20x block diagram DP, DM ULPI: CK, D(7:0), DIR, STP, NXT SCL/SDA, INTN, ID, VBUS, SOF Ethernet MAC DMA/ FIFO 10/100 PHY MII or RMII as AF MDIO as AF DMA/ FIFO USB OTG HS 8 Streams DMA2 FIFO Flash 1 Mbyte RNG SRAM 112 KB SRAM 16 KB AHB2 120 MHz VDD12 FIFO RC HS GPIO PORT A RC LS PB[15:0] GPIO PORT B Power managmt Voltage regulator 3.3 V to 1.2 V DP DM SCL, SDA, INTN, ID, VBUS, SOF POR Reset Int Supply supervision POR/PDR/ BOR PVD GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E Reset & GPIO PORT F clock MANAGT control VSS VDDA, VSSA NRST PLL1&2 PC[15:0] VDD = 1.8 to 3.6 V VCAP1, VCAP2 @VDD @VDDA PA[15:0] USB OTG FS HSYNC, VSYNC PIXCLK, D[13:0] AHB1 120 MHz 8 Streams DMA1 Camera interface PHY S-BUS SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash FIFO AHB3 Arm Cortex-M3 I-BUS 120 MHz ART accelerator D-BUS FIFO ETM CLK, NE [3:0], A[23:0] D[31:0], OEN, WEN, NBL[3:0], NL, NREG NWAIT/IORDY, CD NIORD, IOWR, INT[2:3] INTN, NIIS16 as AF External memory controller (FSMC) MPU NVIC ACCEL/ CACHE JTAG & SW AHB bus-matrix 8S7M NJTRST, JTDI, JTCK/SWCLK JTDO/SWD JTDO/TRACESWO TRACECLK TRACED[3:0] @VDDA @VDD OSC_IN OSC_OUT VBAT = 1.65 to 3.6 V @VBAT LS XTAL 32 kHz RTC GPIO PORT I LS PI[11:0] GPIO PORT H PWR interface PCLKx PH[15:0] GPIO PORT G FCLK PG[15:0] HCLKx PF[15:0] XTAL OSC 4- 26 MHz IWDG AWU Backup register OSC32_IN OSC32_OUT RTC_AF1 RTC_AF1 4 KB BKSPRAM TIM2 32b TIM3 DMA1 DMA2 1 channel as AF SDIO / MMC TIM13 16b TIM8 / PWM 16b TIM9 TIM10 16b TIM11 16b smcard USART 1 irDA RX, TX, CK, CTS, RTS as AF smcard USART 6 irDA MOSI, MISO SCK, NSS as AF SPI1 TIM6 TIM7 16b 16b @VDDA VDDREF_ADC 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 8 analog inputs to ADC3 USART 2MBps Temperature sensor ADC1 @VDDA ADC2 DAC1 ADC 3 IF ITF smcard irDA RX, TX, CK, CTS, RTS as AF USART3 smcard irDA RX, TX, CK CTS, RTS as AF UART4 RX, TX as AF UART5 RX, TX as AF SPI2/I2S2 MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF SPI3/I2S3 MOSI/DOUT, MISO/DIN, SCK/CK NSS/WS, MCK as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF bxCAN1 DAC2 bxCAN2 DAC1_OUT as AF DAC2_OUT as AF 1 channel as AF USART2 WWDG 16b RX, TX, CK, CTS, RTS as AF 1 channel as AF TIM14 16b 16b TIM1 / PWM 2 channels as AF FIFO 1 channel as AF TIM12 APB1 30MHz APB1 30MHz 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF 2 channels as AF 4 channels 16b EXT IT. WKUP APB2 60MHz APB2 60MHz D[7:0] CMD, CK as AF 4 channels, ETR as AF TIM5 32b FIFO 140 AF 4 channels, ETR as AF 16b TIM4 AHB/APB2 AHB/APB1 4 channels, ETR as AF 16b TX, RX TX, RX ai17614d 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 60 MHz. 2. The camera interface and Ethernet are available only in STM32F207xx devices. DS6329 Rev 18 19/181 180 Functional overview STM32F20xxx 3 Functional overview 3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM The Arm® Cortex®-M3 processor is the latest generation of processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. With its embedded Arm® core, the STM32F20x family is compatible with all Arm® tools and software. Figure 4 shows the general block diagram of the STM32F20x family. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M3 processors. It balances the inherent performance advantage of the Arm® Cortex®-M3 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full 150 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 20/181 DS6329 Rev 18 STM32F20xxx 3.4 Functional overview Embedded Flash memory The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbyte available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All STM32F20x products embed:  Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0 wait states  4 Kbytes of backup SRAM. The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DS6329 Rev 18 21/181 180 Functional overview STM32F20xxx Figure 5. Multi-AHB matrix S1 S2 S3 S4 DMA_P2 S5 S6 USB_HS_M MAC USB OTG Ethernet HS ETHERNET_M GP DMA2 DMA_MEM2 DMA_MEM1 DMA_P1 S-bus GP DMA1 S7 M0 ICODE M1 DCODE ART ACCEL. S0 D-bus I-bus ARM Cortex-M3 Flash memory M2 SRAM 112 Kbyte M3 SRAM 16 Kbyte AHB1 periph AHB2 periph M4 M5 M6 APB1 APB2 FSMC Static MemCtl Bus matrix-S ai15963c 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. 22/181 DS6329 Rev 18 STM32F20xxx Functional overview The DMA can be used with the main peripherals: 3.9  SPI and I2S  I2C  USART and UART  General-purpose, basic and advanced-control timers TIMx  DAC  SDIO  Camera interface (DCMI)  ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview:  Write FIFO  Code execution from external memory except for NAND Flash and PC Card  Maximum frequency (fHCLK) for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 Nested vectored interrupt controller (NVIC) The STM32F20x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M3. The NVIC main features are the following:  Closely coupled NVIC gives low-latency interrupt processing  Interrupt entry vector table address passed directly to the core  Closely coupled NVIC core interface  Allows early processing of interrupts  Processing of late arriving, higher-priority interrupts  Support tail chaining  Processor state automatically saved  Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. DS6329 Rev 18 23/181 180 Functional overview 3.11 STM32F20xxx External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the system clock. Several prescalers and PLLs allow the configuration of the three AHB buses, the highspeed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz. The devices embed a dedicate PLL (PLLI2S) that allow them to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.13 Boot modes At startup, boot pins are used to select one out of three boot options:  Boot from user Flash memory  Boot from system memory  Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 3.14 Power supply schemes  24/181 VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates DS6329 Rev 18 STM32F20xxx Functional overview in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16).  VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 19: Power supply scheme for more details. 3.15 Power supply supervisor The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. On devices in WLCSP64+2 package, the BOR, POR and PDR features can be disabled by setting IRROFF pin to VDD. In this mode an external power supply supervisor is required (see Section 3.16). The devices also feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.16 Voltage regulator The regulator has five operating modes:   3.16.1 Regulator ON – Main regulator mode (MR) – Low-power regulator (LPR) – Power-down Regulator OFF – Regulator OFF / internal reset ON – Regulator OFF / internal reset OFF Regulator ON The regulator ON modes are activated by default on LQFP packages.On WLCSP64+2 package, they are activated by connecting both REGOFF and IRROFF pins to VSS, while only REGOFF must be connected to VSS on UFBGA176 package (IRROFF is not available). VDD minimum value is 1.8 V. DS6329 Rev 18 25/181 180 Functional overview STM32F20xxx There are three power modes configured by software when the regulator is ON:  MR is used in the nominal regulation mode  LPR is used in Stop modes The LP regulator mode is configured by software when entering Stop mode.  Power-down is used in Standby mode. The Power-down mode is activated only when entering Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost). Two external ceramic capacitors must be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 19: Power supply scheme and Table 16: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. 3.16.2 Regulator OFF This feature is available only on packages featuring the REGOFF pin. The regulator is disabled by holding REGOFF high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. The two 2.2 µF ceramic capacitors must be replaced by two 100 nF decoupling capacitors. Refer to Figure 19: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor must be used to monitor the V12 of the logic power domain. PA0 pin must be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported:  PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic power domain which is not reset by the NRST pin.  As long as PA0 is kept low, the debug mode cannot be used at power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection at reset or pre-reset is required. Regulator OFF / internal reset ON On WLCSP64+2 package, this mode is activated by connecting REGOFF pin to VDD and IRROFF pin to VSS. On UFBGA176 package, only REGOFF must be connected to VDD (IRROFF not available). In this mode, VDD/VDDA minimum value is 1.8 V. The regulator OFF / internal reset ON mode allows the user to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. 26/181 DS6329 Rev 18 STM32F20xxx Functional overview Figure 6. Regulator OFF / internal reset ON Power-down reset risen before VCAP_1/VCAP_2 stabilization External VCAP_1/2 power supply supervisor Application reset signal (optional) Ext. reset controller active when VCAP_1/2 < 1.08 V VDD (1.8 to 3.6 V) PA0 VDD NRST REGOFF 1.2 V VCAP_1 IRROFF VCAP_2 ai18476b The following conditions must be respected:  VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.  If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V, then PA0 must be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 8).  Otherwise, If the time for VCAP_1 and VCAP_2 to reach 1.08 V is slower than the time for VDD to reach 1.8 V, then PA0 must be asserted low externally (see Figure 9).  If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Regulator OFF / internal reset OFF On WLCSP64+2 package, this mode activated by connecting REGOFF to VSS and IRROFF to VDD. IRROFF cannot be activated in conjunction with REGOFF. This mode is available only on the WLCSP64+2 package. It allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins. In this mode, the integrated power-on reset (POR)/ powerdown reset (PDR) circuitry is disabled. An external power supply supervisor must monitor both the external 1.2 V and the external VDD supply voltage, and must maintain the device in reset mode as long as they remain below a specified threshold. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V. This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications. DS6329 Rev 18 27/181 180 Functional overview STM32F20xxx Figure 7. Regulator OFF / internal reset OFF VDD 1.2 V External VDD/VCAP_1/2 power supply supervisor Ext. reset controller active when VDD