STM32F217VGT6

STM32F215xx STM32F217xx ARM®-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features . ® &"'! ® • Core: ARM 32-bit Cortex -M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) • Memories – Up to 1 Mbyte of Flash memory – 512 bytes of OTP memory – Up to 128 + 4 Kbytes of SRAM – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – From 1.8 to 3.6 V application supply + I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power modes – Sleep, Stop and Standby modes – VBAT supply for RTC, 20 × 32 bit backup registers, and optional 4 Kbytes backup SRAM • 3 × 12-bit, 0.5 µs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode • 2 × 12-bit D/A converters • General-purpose DMA: 16-stream controller with centralized FIFOs and burst support • Up to 17 timers – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode: Serial wire debug (SWD), JTAG, and Cortex®-M3 Embedded Trace Macrocell™ August 2016 This is information on a product in full production. LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) UFBGA176 (10 × 10 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) • • Up to 140 I/O ports with interrupt capability: – Up to 136 fast I/Os up to 60 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to three I2C interfaces (SMBus/PMBus) – Up to four USARTs and two UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to three SPIs (30 Mbit/s), two with muxed I2S to achieve audio class accuracy via audio PLL or external PLL – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface (48 Mbyte/s max.) • Cryptographic acceleration – Hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1) – Analog true random number generator • CRC calculation unit • 96-bit unique ID DocID17050 Rev 13 1/180 www.st.com STM32F21xxx Table 1. Device summary Reference Part numbers STM32F215xx STM32F215RG, STM32F215VG, STM32F215ZG STM32F215RE, STM32F215VE, STM32F215ZE STM32F217xx STM32F217VG, STM32F217IG, STM32F217ZG STM32F217VE, STM32F217IE, STM32F217ZE 2/180 DocID17050 Rev 13 STM32F21xxx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . . 20 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 20 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 29 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID17050 Rev 13 3/180 6 Contents STM32F21xxx 3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 35 3.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 36 3.29 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 36 3.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.31.1 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.32 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.33 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.34 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.35 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 4/180 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DocID17050 Rev 13 STM32F21xxx 7 Contents 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 75 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 75 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 76 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 97 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 102 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 149 6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 149 6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DocID17050 Rev 13 5/180 6 Contents STM32F21xxx 7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.5 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6/180 DocID17050 Rev 13 STM32F21xxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F215xx and STM32F217xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 15 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F21x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 73 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 75 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 75 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 78 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 85 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 85 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DocID17050 Rev 13 7/180 9 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/180 STM32F21xxx I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 110 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 122 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 122 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 123 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 132 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 133 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 139 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 146 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SD/MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 163 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 164 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DocID17050 Rev 13 STM32F21xxx Table 93. Table 94. List of tables Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DocID17050 Rev 13 9/180 9 List of figures STM32F21xxx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. 10/180 Compatible board design between STM32F10x and STM32F2xx for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design between STM32F10x and STM32F2xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design between STM32F10x and STM32F2xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F21x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Startup in regulator OFF: slow VDD slope, power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF: fast VDD slope, power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F21x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F21x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F21x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F21x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F21x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Number of wait states versus fCPU and VDD range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 81 Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 81 Typical current consumption vs. temperature in Sleep mode, peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical current consumption vs. temperature in Sleep mode, peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical current consumption vs. temperature in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . 84 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DocID17050 Rev 13 STM32F21xxx Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. List of figures Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 120 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 127 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 128 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 132 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 133 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 134 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 135 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 139 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 142 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 142 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . 143 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . 144 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 144 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 145 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 148 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 148 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 151 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 153 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 156 LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . . 160 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, DocID17050 Rev 13 11/180 12 List of figures Figure 86. Figure 87. 12/180 STM32F21xxx ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 UFBGA176+25 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 DocID17050 Rev 13 STM32F21xxx 1 Introduction Introduction This datasheet provides the description of the STM32F215xx and STM32F217xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32 family, refer to Section 2.1: Full compatibility throughout the family. The STM32F215xx and STM32F217xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F21x devices throughout the document. For information on programming, erasing and protection of the internal Flash memory, refer to the STM32F20x/STM32F21x Flash programming manual (PM0059). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex®-M3 core refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website. DocID17050 Rev 13 13/180 179 Description 2 STM32F21xxx Description The STM32F21x family is based on the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices also feature an adaptive real-time memory accelerator (ART Accelerator™) that allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. This performance has been validated using the CoreMark® benchmark. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true number random generator (RNG). They also feature standard and advanced communication interfaces. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a cryptographic acceleration cell, and a camera interface for CMOS sensors. The devices also feature standard peripherals. Note: • Up to three I2Cs • Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization. • Four USARTs and two UARTs • A USB OTG high-speed with full-speed capability (with the ULPI) • A second USB OTG (full-speed) • Two CANs • An SDIO interface • Ethernet and camera interface available on STM32F217xx devices only. The STM32F215xx and STM32F217xx devices operate in the –40 to +105 °C temperature range from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allow the design of low-power applications. STM32F215xx and STM32F217xx devices are offered in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.These features make the STM32F215xx and STM32F217xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. 14/180 DocID17050 Rev 13 Peripherals Flash memory in Kbytes STM32F215Rx STM32F215Vx STM32F215Zx 512 512 512 1024 1024 1024 System SRAM in Kbytes Backup FSMC memory controller STM32F217Zx 512 512 1024 1024 4 4 4 4 512 1024 4 4 Yes(1) No No Timers STM32F217Ix 128(112+16) Ethernet(2) Yes General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes DocID17050 Rev 13 Random number generator SPI / Communication interfaces Yes (I2S) 3/(2)(3) I2C 3 USART UART 4 2 USB OTG FS Yes USB OTG HS Yes CAN Camera interface STM32F217Vx STM32F21xxx Table 2. STM32F215xx and STM32F217xx: features and peripheral counts 2 (2) No Yes Yes Encryption GPIOs 51 82 114 SDIO 12-bit ADC Number of channels 12-bit DAC Number of channels Maximum CPU frequency 114 140 16 24 24 3 16 16 24 Yes 2 120 MHz 1.8 V to 3.6 V 15/10 Description Operating voltage 82 Yes Peripherals STM32F215Rx STM32F215Vx STM32F217Vx STM32F217Zx STM32F217Ix Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F215Zx Junction temperature: –40 to + 125 °C LQFP64 LQFP100 LQFP144 LQFP100 LQFP144 Description 16/10 Table 2. STM32F215xx and STM32F217xx: features and peripheral counts (continued) UFBGA176, LQFP176 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. Camera interface and Ethernet are available only in STM32F217x devices. 3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. DocID17050 Rev 13 STM32F21xxx STM32F21xxx 2.1 Description Full compatibility throughout the family The STM32F215xx and STM32F217xx constitute the STM32F21x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F215xx and STM32F217xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F215xx and STM32F217xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F21x family remains simple as only a few pins are impacted. Figure 1, Figure 2 and Figure 3 provide compatible board designs between the STM32F21x and the STM32F10xxx family. Figure 1. Compatible board design between STM32F10x and STM32F2xx for LQFP64 package 966   966 ȍUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ     /4)3 966  966    069 DocID17050 Rev 13 17/180 179 Description STM32F21xxx Figure 2. Compatible board design between STM32F10x and STM32F2xx for LQFP100 package ȍUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ 966     7ZRȍUHVLVWRUVFRQQHFWHGWR 966IRU670)[ 9''966RU1&IRU670)[[   /4)3 966 966 5)8      9''  966 966 9'' 966 966IRU670)[ 9''IRU670)[[ 069 1. RFU = reserved for future use. Figure 3. Compatible board design between STM32F10x and STM32F2xx for LQFP144 package ȍUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ 966       /4)3 966 966 5)8 9''      966 7ZRȍUHVLVWRUVFRQQHFWHGWR 966IRU670)[ 9''966RU1&IRU670)[[  966 9'' 966 069 1. RFU = reserved for future use. 18/180 DocID17050 Rev 13 STM32F21xxx Description Figure 4. STM32F21x block diagram %XTERNALMEMORY CONTROLLER&3-# $0$5,0)#+$ $)2340.84 3#,3$!).4.)$6"533/& %THERNET-!# $-! &)&/  0(9 -))OR2-))AS!& -$)/AS!& $-! &)&/ 53" /4'(3 3TREAMS $-! &)&/ &LASH -BYTE 32!-+" !("-(Z 6$$ 2#(3 '0)/0/24! 2#,3 0";= '0)/0/24" 0#;= '0)/0/24# 0$;= '0)/0/24$ 0%;= '0)/0/24% (!3( #AMERA INTERFACE 53" /4'&3 0OWERMANAGMT 6OLTAGE REGULATOR 6TO6 6$$ /2 0 2ESET )NT 0,, 3UPPLY SUPERVISION 0/20$2 "/2 06$ '0)/0/24& ,3 '0)/0/24( 84!,K(Z 24# '0)/0/24) !75 "ACKUP REGISTER $-! 4)- CHANNEL AS!& 53!24 SMCARD IR$! 2848#+ #43243AS!& 53!24 SMCARD IR$! 2848#+ #43243AS!& 5!24 2848AS!& B 5!24 2848AS!& 4)- 2848#+ #43243AS!& SMCARD 53!24 IR$! 30) 4)- 4)- B B 53!24-"PS 4EMPERATURESENSOR 6$$! !$# !$# !$# $!# )& 30))3 -/3)$/54 -)3/$).3#+#+ .3373-#+AS!& 30))3 -/3)$/54 -)3/$).3#+#+ .3373-#+AS!& 3#,3$!3-"!AS!& )#3-"53 6$$! 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The camera interface and Ethernet are available only in STM32F217xx devices. DocID17050 Rev 13 19/180 179 Functional overview STM32F21xxx 3 Functional overview 3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM® Cortex®-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM® core, the STM32F21x family is compatible with all ARM® tools and software. Figure 4 shows the general block diagram of the STM32F21x family. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M3 processors. It balances the inherent performance advantage of the ARM® Cortex®-M3 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full 150 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 20/180 DocID17050 Rev 13 STM32F21xxx 3.4 Functional overview Embedded Flash memory The STM32F21x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbyte available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All STM32F21x products embed: • Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0 wait states • 4 Kbytes of backup SRAM. The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID17050 Rev 13 21/180 179 Functional overview STM32F21xxx Figure 5. Multi-AHB matrix 3 3 3 3 3 3 53"?(3?- -!# 53"/4' %THERNET (3 %4(%2.%4?- $-!?0 '0 $-! $-!?-%- $-!?-%- $-!?0 3 BUS '0 $-! 3 - )#/$% - $#/$% !24 !##%, 3 $ BUS ) BUS !2#ORTEX - &LASH MEMORY - 32!- +BYTE - 32!+BYTE !(" PERIPH !(" PERIPH - - - !0" !0" &3-# 3TATIC-EM#TL "USMATRIX 3 AIC 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. 22/180 DocID17050 Rev 13 STM32F21xxx Functional overview The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART and UART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Cryptographic acceleration • Camera interface (DCMI) • ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F21x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Code execution from external memory except for NAND Flash and PC Card • Maximum frequency (fHCLK) for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 Nested vectored interrupt controller (NVIC) The STM32F21x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M3. The NVIC main features are the following: • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead DocID17050 Rev 13 23/180 179 Functional overview STM32F21xxx This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the system clock. Several prescalers and PLLs allow the configuration of the three AHB buses, the highspeed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz. The devices embed a dedicate PLL (PLLI2S) that allow them to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 24/180 DocID17050 Rev 13 STM32F21xxx 3.14 Functional overview Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 17: Power supply scheme for more details. 3.15 Power supply supervisor The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. . The devices also feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.16 Voltage regulator The regulator has four operating modes: • • Regulator ON – Main regulator mode (MR) – Low-power regulator (LPR) – Power-down Regulator OFF – 3.16.1 Regulator OFF/internal reset ON Regulator ON The regulator ON modes are activated by default on LQFP packages. On UFBGA176 package, they are activated by connecting REGOFF to VSS. VDD minimum value is 1.8 V. DocID17050 Rev 13 25/180 179 Functional overview STM32F21xxx There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode • LPR is used in Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost). Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 17: Power supply scheme and Table 15: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. 3.16.2 Regulator OFF This feature is available only on packages featuring the REGOFF pin. The regulator is disabled by holding REGOFF high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 17: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used at power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection at reset or pre-reset is required. Regulator OFF/internal reset ON On UFBGA176 package, REGOFF must be connected to VDD. The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. 26/180 DocID17050 Rev 13 STM32F21xxx Functional overview Figure 6. Regulator OFF/internal reset ON 0OWER DOWNRESETRISEN BEFORE6#!0?6#!0?STABILIZATION %XTERNAL6#!0? POWERSUPPLYSUPERVISOR !PPLICATIONRESET SIGNALOPTIONAL %XTRESETCONTROLLERACTIVE WHEN6#!0?6 6$$ TO6 0! 6$$ .234 2%'/&& 6 6#!0? 6#!0? -36 The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 7). • Otherwise, If the time for VCAP_1 and VCAP_2 to reach 1.08 V is slower than the time for VDD to reach 1.8 V, then PA0 should be asserted low externally (see Figure 8). • If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. integrated power-on reset (POR)/ power-down reset (PDR) circuitry is disabled. An external power supply supervisor should monitor both the external 1.2 V and the external VDD supply voltage, and should maintain the device in reset mode as long as they remain below a specified threshold. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V. This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications. DocID17050 Rev 13 27/180 179 Functional overview STM32F21xxx Figure 7. Startup in regulator OFF: slow VDD slope, power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 9 3$WLHGWR1567 WLPH 1567 WLPH DL 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 8. Startup in regulator OFF: fast VDD slope, power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B  9&$3B 9 9 WLPH 3$DVVHUWHGH[WHUQDOO\ 1567 WLPH DL 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability Table 3. Regulator ON/OFF and internal reset ON/OFF availability Package LQFP64 LQFP100 LQFP144 LQFP176 UFBGA176 28/180 Regulator ON/internal reset ON Regulator ON/internal reset OFF Regulator OFF/internal reset ON Yes No No Yes REGOFF set to VSS No Yes REGOFF set to VDD DocID17050 Rev 13 STM32F21xxx 3.17 Functional overview Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F21x devices includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the following: • Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 day of the month. • Programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. • It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal lowpower RC oscillator or the high-speed external clock divided by 128. The internal lowspeed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. • Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. • A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 3.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin. 3.18 Low-power modes The STM32F21x family supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC DocID17050 Rev 13 29/180 179 Functional overview STM32F21xxx and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device enters the Stop or Standby mode. 3.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery or an external supercapacitor. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.20 Timers and watchdogs The STM32F21x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Advanced- TIM1, control TIM8 30/180 Counter Counter Prescaler resolution type factor 16-bit Up, Any integer Down, between 1 Up/down and 65536 DMA Capture/ Max Max Complementary request compare interface timer output generation channels clock clock Yes DocID17050 Rev 13 4 Yes 60 MHz 120 MHz STM32F21xxx Functional overview Table 4. Timer feature comparison (continued) Timer type Timer General purpose Basic General purpose 3.20.1 Counter Counter Prescaler resolution type factor DMA Capture/ Max Max Complementary request compare interface timer output generation channels clock clock TIM2, TIM5 32-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 30 MHz 60 MHz TIM3, TIM4 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 30 MHz 60 MHz TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 30 MHz 60 MHz TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 60 MHz 120 MHz TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 60 MHz 120 MHz TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 30 MHz 60 MHz TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 30 MHz 60 MHz Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture. The advanced-control timer can therefore work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. DocID17050 Rev 13 31/180 179 Functional overview 3.20.2 STM32F21xxx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F21x devices (see Table 4 for differences). TIM2, TIM3, TIM4, TIM5 The STM32F21x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 halleffect sensors. TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.20.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. 3.20.4 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout 32/180 DocID17050 Rev 13 STM32F21xxx Functional overview management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.20.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.21 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source Inter-integrated circuit interface (I²C) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 3.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) The STM32F21x devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at up to 3.75 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. DocID17050 Rev 13 33/180 179 Functional overview STM32F21xxx Table 5. USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Max baud rate Max baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max. 30 MHz) UART5 X - X - X - 3.75 3.75 APB1 (max. 30 MHz) USART6 X X X X X X 3.75 7.5 APB2 (max. 60 MHz) 3.23 Serial peripheral interface (SPI) The STM32F21x devices feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, while SPI2 and SPI3 can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 3.24 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, in half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. 3.25 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. 34/180 DocID17050 Rev 13 STM32F21xxx Functional overview The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F217xx devices. The STM32F217xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F217xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F217xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F217xx. The STM32F217xx includes the following features: 3.27 • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F20x and STM32F21x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one DocID17050 Rev 13 35/180 179 Functional overview STM32F21xxx CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. 3.28 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 3.29 • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected • Internal FS OTG PHY support Universal serial bus on-the-go high-speed (OTG_HS) The STM32F21x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 36/180 • Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID17050 Rev 13 STM32F21xxx 3.30 Functional overview Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 3.31 Digital camera interface (DCMI) The camera interface is not available in STM32F215xx devices. STM32F217xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image DocID17050 Rev 13 37/180 179 Functional overview 3.31.1 STM32F21xxx Cryptographic acceleration The STM32F215xx and STM32F217xx devices embed a cryptographic accelerator. This cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer. • These algorithms consists of: Encryption/Decryption – DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key – AES (advanced encryption standard): ECB, CBC and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key Universal hash • 3.32 – SHA-1 (secure hash algorithm) – MD5 It also provides a true random number generator that deliver 32-bit random numbers produced by an integrated analog circuit. True random number generator (RNG) All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers produced by an integrated analog circuit. 3.33 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to 120 MHz that leads to a maximum I/O toggling speed of 60 MHz. 3.34 ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: 38/180 • Simultaneous sample and hold • Interleaved sample and hold DocID17050 Rev 13 STM32F21xxx Functional overview The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.35 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.37 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DocID17050 Rev 13 39/180 179 Functional overview 3.38 STM32F21xxx Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F21x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 40/180 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 9. STM32F21x LQFP64 pinout 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 7+50 0! 0!                                 ,1&0                                 6$$ 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6#!0? 6$$ 4 Pinouts and pin description AIC 1. The above figure shows the package top view. DocID17050 Rev 13 41/180 179 Pinouts and pin description STM32F21xxx                          6$$ 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 10. STM32F21x LQFP100 pinout                          ,1&0                          6$$ 633 6#!0? 0! 0! 0! 0! 0!  0!  0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$                          0% 0% 0% 0% 0% 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 633 6$$ 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 7+50 0! 0! AIE 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. 42/180 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0!  0!                                      6$$ Figure 11. STM32F21x LQFP144 pinout                                     ,1&0                                     6$$ 633 6#!0? 0!  0!  0!  0!  0!  0!  0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6#!0? 6$$ 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 633 0!  633 6$$ 0!  0!  0!  0!  0# 0# 0" 0" 0" 0& 0&                                     0% 0% 0% 0% 0% 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0!  7+50 0!  0!  AIE 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. DocID17050 Rev 13 43/180 179 Pinouts and pin description STM32F21xxx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0)                                             0) 0) 0) 0) 6 $$ Figure 12. STM32F21x LQFP176 pinout                                             ,1&0                                             0) 0) 0( 0( 0( 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$ 633 0( 6#!0? 6$$ 0( 0( 0( 0( 0( 0( 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0( 0( 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0&                                             0% 0% 0% 0% 0% 6"!4 0) 24#?!& 0# 24#?!& 0# /3#?). 0# /3#?/54 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 7+50 0! 0! 0( 0( AIE 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. 44/180 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Figure 13. STM32F21x UFBGA176 ballout                $ 3( 3( 3( 3( 3% 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$ 9'' 5)8 9'' 9'' 9'' 3* 3' 3' 3, 3, 3$ %227 966 966 966 3' 3' 3' 3+ 3, 3$ 3+ 3+ 3, 3$ & 9%$7 3, 3, 3, ' 3& 7$03 3, 7$03 3, 3, ( 3& 26&B,1 3) 3, 3, ) 3& 26&B287 966 966 9'' 3+ 966 966 966 966 966 966 9&$3B 3& 3$ 966 9'' 3+ 966 966 966 966 966 966 9'' 3& 3& * 3+ 26&B,1 + 3+ 26&B287 3) 3) 3+ 966 966 966 966 966 966 9'' 3* 3& - 1567 3) 3) 3+ 966 966 966 966 966 9'' 9'' 3* 3* . 3) 3) 3) 966 966 966 966 966 / 3) 3) 3) 5(*2)) 0 966$ 3& 3& 3& 3& 3% 3* 966 966 9&$3B 3$ 3& 3) 3* 9'' 9'' 9'' 9'' 3+ 3* 3* 3* 3+ 3+ 3' 3* 3+ 3+ 3+ 3' 3' 3( 3+ 3' 3' 3' 1 95() 3$ 3$ :.83 3 95() 3$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3' 5 9''$ 3$ 3$ 3% 3% 3) 3) 3( 3( 3( 3( 3% 3% 3% 3% AIC 1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. 2. The above figure shows the package top view. Table 6. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input/ output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID17050 Rev 13 45/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions LQFP64 LQFP100 LQFP144 LQFP176 UFBGA176 (function after reset)(1) Pin type I / O structure Note Pins Alternate functions - 1 1 1 A2 PE2 I/O FT - TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT - - 2 2 2 A1 PE3 I/O FT - TRACED0, FSMC_A19, EVENTOUT - - 3 3 3 B1 PE4 I/O FT - TRACED1, FSMC_A20, DCMI_D4/ EVENTOUT - - 4 4 4 B2 PE5 I/O FT - TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT - - 5 5 5 B3 PE6 I/O FT - TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT - 1 6 6 6 C1 VBAT S - - - - FT (2)(3) EVENTOUT RTC_AF2 (2)(3) EVENTOUT RTC_AF1 - - - 7 D2 Pin name PI8 I/O Additional functions 2 7 7 8 D1 PC13 I/O FT 3 8 8 9 E1 PC14/OSC32_IN (PC14) I/O FT (2)(3) EVENTOUT OSC32_IN(4) 4 9 9 10 F1 PC15/ OSC32_OUT (PC15) I/O FT (2)(3) EVENTOUT OSC32_OUT(4) - - - 11 D3 PI9 I/O FT - CAN1_RX, EVENTOUT - - - - 12 E3 PI10 I/O FT - ETH_MII_RX_ER, EVENTOUT - - - - 13 E4 PI11 I/O FT - OTG_HS_ULPI_DIR, EVENTOUT - - - - 14 F2 VSS S - - - - - - 15 F3 VDD S - - - - - 10 16 E2 PF0 I/O FT - FSMC_A0, I2C2_SDA, EVENTOUT - - - 11 17 H3 PF1 I/O FT - FSMC_A1, I2C2_SCL, EVENTOUT - - - 12 18 H2 PF2 I/O FT - FSMC_A2, I2C2_SMBA, EVENTOUT - - - 13 19 J2 PF3 I/O FT (4) FSMC_A3, EVENTOUT ADC3_IN9 46/180 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) PF4 Note J3 I / O structure 14 20 Pin type UFBGA176 - LQFP176 LQFP100 - Pin name (function after reset)(1) LQFP144 LQFP64 Pins Alternate functions I/O FT (4) FSMC_A4, EVENTOUT ADC3_IN14 FSMC_A5, EVENTOUT ADC3_IN15 Additional functions - - 15 21 K3 PF5 I/O FT (4) - 10 16 22 G2 VSS S - - - - - 11 17 23 G3 VDD S - - - - - - 18 24 K2 PF6 I/O FT (4) TIM10_CH1, FSMC_NIORD, EVENTOUT ADC3_IN4 - - 19 25 K1 PF7 I/O FT (4) TIM11_CH1, FSMC_NREG, EVENTOUT ADC3_IN5 - - 20 26 L3 PF8 I/O FT (4) TIM13_CH1, FSMC_NIOWR, EVENTOUT ADC3_IN6 - - 21 27 L2 PF9 I/O FT (4) TIM14_CH1, FSMC_CD, EVENTOUT ADC3_IN7 - - 22 28 L1 PF10 I/O FT (4) FSMC_INTR, EVENTOUT ADC3_IN8 5 12 23 29 G1 PH0/OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN(4) 6 13 24 30 H1 PH1/OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT(4) 7 14 25 31 J1 NRST - - - 8 15 26 32 M2 PC0 I/O FT (4) OTG_HS_ULPI_STP, EVENTOUT ADC123_ IN10 9 16 27 33 M3 PC1 I/O FT (4) ETH_MDC, EVENTOUT ADC123_ IN11 10 17 28 34 M4 PC2 I/O FT (4) SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, EVENTOUT ADC123_ IN12 SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, EVENTOUT ADC123_ IN13 I/O RST 11 18 29 35 M5 PC3 I/O FT (4) - 19 30 36 - VDD S - - - - 12 20 31 37 M1 VSSA S - - - - - - N1 VREF- S - - - - - 21 P1 VREF+ S - - - - - - 32 38 DocID17050 Rev 13 47/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions (continued) LQFP144 LQFP176 UFBGA176 22 33 39 R1 VDDA 14 23 34 40 N3 PA0/WKUP (PA0) S - I/O Note LQFP100 13 I / O structure LQFP64 Pin name (function after reset)(1) Pin type Pins Alternate functions Additional functions - - - USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, EVENTOUT ADC123_IN0, WKUP USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2, EVENTOUT ADC123_IN1 FT (4)(5) 15 24 35 41 N2 PA1 I/O FT (4) 16 25 36 42 P2 PA2 I/O FT (4) USART2_TX,TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO, EVENTOUT ADC123_IN2 - - - 43 F4 PH2 I/O FT - ETH_MII_CRS, EVENTOUT - - - - 44 G4 PH3 I/O FT - ETH_MII_COL, EVENTOUT - - - - 45 H4 PH4 I/O FT - I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - - 46 J4 PH5 I/O FT - I2C2_SDA, EVENTOUT - USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL, EVENTOUT ADC123_IN3 17 26 37 47 R2 PA3 I/O FT (4) 18 27 38 48 - VSS S - - - - L4 REGOFF I/O - - - - K4 VDD S - - - - (4) SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS, EVENTOUT ADC12_IN4, DAC_OUT1 (4) SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N, EVENTOUT ADC12_IN5 /DAC_OUT2 19 20 21 28 29 30 48/180 39 49 40 50 41 51 N4 P4 PA4 PA5 I/O TTa I/O TTa DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) P3 PA6 Pin type UFBGA176 LQFP176 LQFP144 42 52 I/O Note 31 Pin name (function after reset)(1) I / O structure 22 LQFP100 LQFP64 Pins Alternate functions Additional functions FT (4) SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN, EVENTOUT ADC12_IN6 ADC12_IN7 23 32 43 53 R3 PA7 I/O FT (4) SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV, EVENTOUT 24 33 44 54 N5 PC4 I/O FT (4) ETH_RMII_RXD0,/ ETH_MII_RXD0, EVENTOUT ADC12_IN14 25 34 45 55 P5 PC5 I/O FT (4) ETH_RMII_RXD1, ETH_MII_RXD1, EVENTOUT ADC12_IN15 FT (4) TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N, EVENTOUT ADC12_IN8 TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N, EVENTOUT ADC12_IN9 26 35 46 56 R5 PB0 I/O 27 36 47 57 R4 PB1 I/O FT (4) 28 37 48 58 M6 PB2/BOOT1 (PB2) I/O FT - EVENTOUT - - - 49 59 R6 PF11 I/O FT - DCMI_D12, EVENTOUT - - - 50 60 P6 PF12 I/O FT - FSMC_A6, EVENTOUT - - - 51 61 M8 VSS S - - - - - - 52 62 N8 VDD S - - - - - - 53 63 N6 PF13 I/O FT - FSMC_A7, EVENTOUT - - - 54 64 R7 PF14 I/O FT - FSMC_A8, EVENTOUT - - - 55 65 P7 PF15 I/O FT - FSMC_A9, EVENTOUT - - - 56 66 N7 PG0 I/O FT - FSMC_A10, EVENTOUT - - - 57 67 M7 PG1 I/O FT - FSMC_A11, EVENTOUT - - 38 58 68 R8 PE7 I/O FT - FSMC_D4, TIM1_ETR, EVENTOUT - DocID17050 Rev 13 49/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions (continued) LQFP64 LQFP100 LQFP144 LQFP176 UFBGA176 (function after reset)(1) Pin type I / O structure Note Pins Alternate functions - 39 59 69 P8 PE8 I/O FT - FSMC_D5, TIM1_CH1N, EVENTOUT - - 40 60 70 P9 PE9 I/O FT - FSMC_D6, TIM1_CH1, EVENTOUT - - - 61 71 M9 VSS S - - - - - - 62 72 N9 VDD S - - - - - 41 63 73 R9 PE10 I/O FT - FSMC_D7, TIM1_CH2N, EVENTOUT - - 42 64 74 P10 PE11 I/O FT - FSMC_D8,TIM1_CH2, EVENTOUT - - 43 65 75 R10 PE12 I/O FT - FSMC_D9,TIM1_CH3N, EVENTOUT - - 44 66 76 N11 PE13 I/O FT - FSMC_D10,TIM1_CH3, EVENTOUT - - 45 67 77 P11 PE14 I/O FT - FSMC_D11,TIM1_CH4, EVENTOUT - - 46 68 78 R11 PE15 I/O FT - FSMC_D12,TIM1_BKIN, EVENTOUT - - SPI2_SCK, I2S2_SCK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3, EVENTOUT - - I2C2_SDA,USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN, ETH_MII_TX_EN, TIM2_CH4, EVENTOUT - 29 47 69 79 R12 Pin name PB10 I/O FT 30 48 70 80 R13 PB11 I/O 31 49 71 81 M10 VCAP_1 S - - - 32 50 72 82 N10 VDD S - - - - - - 83 M11 PH6 I/O FT - I2C2_SMBA, TIM12_CH1, ETH_MII_RXD2, EVENTOUT - - - - 84 N12 PH7 I/O FT - I2C3_SCL, ETH_MII_RXD3, EVENTOUT - 50/180 FT Additional functions DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) LQFP144 Pin type I / O structure Note - - - 85 M12 PH8 I/O FT - I2C3_SDA, DCMI_HSYNC, EVENTOUT - - - - 86 M13 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, DCMI_D0, EVENTOUT - - - - 87 L13 PH10 I/O FT - TIM5_CH1, DCMI_D1, EVENTOUT - - - - 88 L12 PH11 I/O FT - TIM5_CH2, DCMI_D2, EVENTOUT - - - - 89 K12 PH12 I/O FT - TIM5_CH3, DCMI_D3, EVENTOUT - - - - 90 H12 VSS S - - - - - - - 91 VDD S - - - - - SPI2_NSS,I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID, EVENTOUT - - SPI2_SCK, I2S2_SCK, USART3_CTS, TIM1_CH1N,CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1, ETH_MII_TXD1, EVENTOUT OTG_HS_ VBUS - SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM USART3_RTS, TIM8_CH2N, EVENTOUT - - 33 34 35 51 52 53 UFBGA176 LQFP100 Alternate functions LQFP176 LQFP64 Pins J12 73 92 P12 74 93 P13 75 94 R14 Pin name (function after reset)(1) PB12 PB13 PB14 I/O I/O I/O FT FT FT Additional functions 36 54 76 95 R15 PB15 I/O FT - SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, RTC_50Hz, EVENTOUT - 55 77 96 P15 PD8 I/O FT - FSMC_D13, USART3_TX, EVENTOUT - - 56 78 97 P14 PD9 I/O FT - FSMC_D14, USART3_RX, EVENTOUT - DocID17050 Rev 13 51/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions (continued) LQFP144 Pin type I / O structure Note - 57 79 98 N15 PD10 I/O FT - FSMC_D15, USART3_CK, EVENTOUT - - 58 80 99 N14 PD11 I/O FT - FSMC_A16,USART3_CTS, EVENTOUT - - 59 81 100 N13 PD12 I/O FT - FSMC_A17,TIM4_CH1, USART3_RTS, EVENTOUT - - 60 82 101 M15 PD13 I/O FT - FSMC_A18,TIM4_CH2, EVENTOUT - - - 83 102 VSS S - - - - - 84 103 J13 VDD S - - - - 61 85 104 M14 PD14 I/O FT - FSMC_D0,TIM4_CH3, EVENTOUT - - 62 86 105 L14 PD15 I/O FT - FSMC_D1,TIM4_CH4, EVENTOUT - - - 87 106 L15 PG2 I/O FT - FSMC_A12, EVENTOUT - - - 88 107 K15 PG3 I/O FT - FSMC_A13, EVENTOUT - - - 89 108 K14 PG4 I/O FT - FSMC_A14, EVENTOUT - - - 90 109 K13 PG5 I/O FT - FSMC_A15, EVENTOUT - - - 91 110 J15 PG6 I/O FT - FSMC_INT2, EVENTOUT - - - 92 111 J14 PG7 I/O FT - FSMC_INT3,USART6_CK, EVENTOUT - - - 93 112 H14 PG8 I/O FT - USART6_RTS, ETH_PPS_OUT, EVENTOUT - - - 94 113 G12 VSS S - - - - - - 95 114 H13 VDD S - - - - - I2S2_MCK, TIM8_CH1,SDIO_D6, USART6_TX, DCMI_D0,TIM3_CH1, EVENTOUT - 37 63 52/180 UFBGA176 LQFP100 Alternate functions LQFP176 LQFP64 Pins - 96 115 H15 Pin name (function after reset)(1) PC6 I/O FT DocID17050 Rev 13 Additional functions STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) Additional functions - 97 116 G15 PC7 I/O FT - 39 65 98 117 G14 PC8 I/O FT - TIM8_CH3,SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2, EVENTOUT - - LQFP176 64 LQFP144 38 I2S3_MCK, TIM8_CH2,SDIO_D7, USART6_RX, DCMI_D1,TIM3_CH2, EVENTOUT LQFP100 Alternate functions LQFP64 Note I / O structure Pin name Pin type UFBGA176 Pins (function after reset)(1) 40 66 99 118 F14 PC9 I/O FT - I2S2_CKIN, I2S3_CKIN, MCO2, TIM8_CH4,SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4, EVENTOUT 41 67 100 119 F15 PA8 I/O FT - MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF, EVENTOUT - 42 68 101 120 E15 PA9 I/O FT - USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0, EVENTOUT OTG_FS_ VBUS 43 69 102 121 D15 PA10 I/O FT - USART1_RX, TIM1_CH3, OTG_FS_ID,DCMI_D1, EVENTOUT - 44 70 103 122 C15 PA11 I/O FT - USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM, EVENTOUT - 45 71 104 123 B15 PA12 I/O FT - USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP, EVENTOUT - 46 72 105 124 A15 PA13 (JTMS-SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - 47 73 106 125 F13 VCAP_2 S - - - - - 74 107 126 F12 VSS S - - - - 48 75 108 127 G13 VDD S - - - - - - - 128 E12 PH13 I/O FT - TIM8_CH1N, CAN1_TX, EVENTOUT - - - - 129 E13 PH14 I/O FT - TIM8_CH2N, DCMI_D4, EVENTOUT - DocID17050 Rev 13 53/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions (continued) LQFP144 Pin type I / O structure Note - - - 130 D13 PH15 I/O FT - TIM8_CH3N, DCMI_D11, EVENTOUT - - - - 131 E14 PI0 I/O FT - TIM5_CH4, SPI2_NSS, I2S2_WS, DCMI_D13, EVENTOUT - - - - 132 D14 PI1 I/O FT - SPI2_SCK, I2S2_SCK, DCMI_D8, EVENTOUT - - - - 133 C14 PI2 I/O FT - TIM8_CH4,SPI2_MISO, DCMI_D9, EVENTOUT - - - - 134 C13 PI3 I/O FT - TIM8_ETR, SPI2_MOSI, I2S2_SD, DCMI_D10, EVENTOUT - - - - 135 D9 VSS S - - - - - - - 136 C9 VDD S - - - - UFBGA176 LQFP100 Alternate functions LQFP176 LQFP64 Pins Pin name (function after reset)(1) Additional functions 49 76 109 137 A14 PA14 (JTCK-SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - 50 77 110 138 A13 PA15 (JTDI) I/O FT - JTDI, SPI3_NSS, I2S3_WS,TIM2_CH1_ETR, SPI1_NSS/ EVENTOUT - - SPI3_SCK, I2S3_SCK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX, EVENTOUT - - UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4,USART3_RX, EVENTOUT - - 51 52 78 111 139 B14 79 112 140 B13 PC10 PC11 I/O I/O FT FT 53 80 113 141 A12 PC12 I/O FT - UART5_TX,SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD, USART3_CK, EVENTOUT - 81 114 142 B12 PD0 I/O FT - FSMC_D2,CAN1_RX, EVENTOUT - - 82 115 143 C12 PD1 I/O FT - FSMC_D3, CAN1_TX, EVENTOUT - 54/180 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) Pin type I / O structure Note 83 116 144 D12 PD2 I/O FT - TIM3_ETR,UART5_RX SDIO_CMD, DCMI_D11, EVENTOUT - - 84 117 145 D11 PD3 I/O FT - FSMC_CLK,USART2_CTS, EVENTOUT - - 85 118 146 D10 PD4 I/O FT - FSMC_NOE,USART2_RTS, EVENTOUT - - 86 119 147 C11 PD5 I/O FT - FSMC_NWE,USART2_TX, EVENTOUT - UFBGA176 54 LQFP176 LQFP100 Alternate functions LQFP144 LQFP64 Pins Pin name (function after reset)(1) Additional functions - - 120 148 D8 VSS S - - - - - 121 149 C8 VDD S - - - - 87 122 150 B11 PD6 I/O FT - FSMC_NWAIT,USART2_RX, EVENTOUT - - 88 123 151 A11 PD7 I/O FT - USART2_CK,FSMC_NE1, FSMC_NCE2, EVENTOUT - - - 124 152 C10 PG9 I/O FT - USART6_RX, FSMC_NE2,FSMC_NCE3, EVENTOUT - - - 125 153 B10 PG10 I/O FT - FSMC_NCE4_1, FSMC_NE3, EVENTOUT - - - - 126 154 B9 PG11 I/O FT - FSMC_NCE4_2, ETH_MII_TX_EN, ETH _RMII_TX_EN, EVENTOUT - - 127 155 B8 PG12 I/O FT - FSMC_NE4, USART6_RTS, EVENTOUT - - - 128 156 A8 PG13 I/O FT - FSMC_A24, USART6_CTS, ETH_MII_TXD0, ETH_RMII_TXD0, EVENTOUT - - - 129 157 A7 PG14 I/O FT - FSMC_A25, USART6_TX, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT - - - 130 158 D7 VSS S - - - - - - 131 159 C7 VDD S - - - - DocID17050 Rev 13 55/180 179 Pinouts and pin description STM32F21xxx Table 7. STM32F21x pin and ball definitions (continued) I/O Note PG15 I / O structure 132 160 B7 Pin name (function after reset)(1) Pin type UFBGA176 - LQFP176 LQFP100 - LQFP144 LQFP64 Pins Alternate functions Additional functions FT - USART6_CTS, DCMI_D13, EVENTOUT - - 55 PB3 89 133 161 A10 I/O (JTDO/TRACESWO) FT - JTDO/TRACESWO, SPI3_SCK, I2S3_SCK, TIM2_CH2, SPI1_SCK, EVENTOUT 56 90 134 162 A9 FT - NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO, EVENTOUT - - I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT,TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10, I2S3_SD, EVENTOUT - - 57 91 135 163 A6 PB4 PB5 I/O I/O FT 58 92 136 164 B6 PB6 I/O FT - I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5,USART1_TX, EVENTOUT 59 93 137 165 B5 PB7 I/O FT - I2C1_SDA, FSMC_NL(6), DCMI_VSYNC, USART1_RX, TIM4_CH2, EVENTOUT - 60 94 138 166 D6 BOOT0 I B - - VPP - TIM4_CH3,SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX, EVENTOUT - - 61 95 139 167 A5 PB8 I/O FT 62 96 140 168 B4 PB9 I/O FT - SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX, EVENTOUT - 97 141 169 A4 PE0 I/O FT - TIM4_ETR, FSMC_NBL0, DCMI_D2, EVENTOUT - - 98 142 170 A3 PE1 I/O FT - FSMC_NBL1, DCMI_D3, EVENTOUT - VSS S - - - - - 56/180 - - D5 DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 7. STM32F21x pin and ball definitions (continued) LQFP144 LQFP176 UFBGA176 - - - - VSS Note LQFP100 63 I / O structure LQFP64 Pin name (function after reset)(1) Pin type Pins Alternate functions S - - - - - - Additional functions 99 143 171 C6 RFU - - (7) 64 100 144 172 C5 VDD S - - - - - - - - 173 D4 PI4 I/O FT - TIM8_BKIN, DCMI_D5, EVENTOUT - - - - 174 C4 PI5 I/O FT - TIM8_CH1, DCMI_VSYNC, EVENTOUT - - - - 175 C3 PI6 I/O FT - TIM8_CH2, DCMI_D6, EVENTOUT - - - - 176 C2 PI7 I/O FT - TIM8_CH3, DCMI_D7, EVENTOUT - 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used as an internal Reset (active low). 6. FSMC_NL pin is also named FSMC_NADV on memory devices. 7. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected. Table 8. FSMC pin definition FSMC Pins LQFP100 CF NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bit PE2 - A23 A23 - Yes PE3 - A19 A19 - Yes PE4 - A20 A20 - Yes PE5 - A21 A21 - Yes PE6 - A22 A22 - Yes PF0 A0 A0 - - - PF1 A1 A1 - - - DocID17050 Rev 13 57/180 179 Pinouts and pin description STM32F21xxx Table 8. FSMC pin definition (continued) FSMC Pins 58/180 LQFP100 CF NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bit PF2 A2 A2 - - - PF3 A3 A3 - - - PF4 A4 A4 - - - PF5 A5 A5 - - - PF6 NIORD - - - - PF7 NREG - - - - PF8 NIOWR - - - - PF9 CD - - - - PF10 INTR - - - - PF12 A6 A6 - - - PF13 A7 A7 - - - PF14 A8 A8 - - - PF15 A9 A9 - - - PG0 A10 A10 - - - PG1 - A11 - - - PE7 D4 D4 DA4 D4 Yes PE8 D5 D5 DA5 D5 Yes PE9 D6 D6 DA6 D6 Yes PE10 D7 D7 DA7 D7 Yes PE11 D8 D8 DA8 D8 Yes PE12 D9 D9 DA9 D9 Yes PE13 D10 D10 DA10 D10 Yes PE14 D11 D11 DA11 D11 Yes PE15 D12 D12 DA12 D12 Yes PD8 D13 D13 DA13 D13 Yes PD9 D14 D14 DA14 D14 Yes PD10 D15 D15 DA15 D15 Yes PD11 - A16 A16 CLE Yes PD12 - A17 A17 ALE Yes PD13 - A18 A18 - Yes PD14 D0 D0 DA0 D0 Yes PD15 D1 D1 DA1 D1 Yes PG2 - A12 - - - DocID17050 Rev 13 STM32F21xxx Pinouts and pin description Table 8. FSMC pin definition (continued) FSMC Pins LQFP100 CF NOR/PSRAM/SRAM NOR/PSRAM Mux NAND 16 bit PG3 - A13 - - - PG4 - A14 - - - PG5 - A15 - - - PG6 - - - INT2 - PG7 - - - INT3 - PD0 D2 D2 DA2 D2 Yes PD1 D3 D3 DA3 D3 Yes PD3 - CLK CLK - Yes PD4 NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes PD7 - NE1 NE1 NCE2 Yes PG9 - NE2 NE2 NCE3 - PG10 NCE4_1 NE3 NE3 - - PG11 NCE4_2 - - - - PG12 - NE4 NE4 - - PG13 - A24 A24 - - PG14 - A25 A25 - - PB7 - NADV NADV - Yes PE0 - NBL0 NBL0 - Yes PE1 - NBL1 NBL1 - Yes DocID17050 Rev 13 59/180 179 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 USART2_CTS UART4_TX Port PA0-WKUP Port A SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 - TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR - - SPI3/I2S3 AF9 AF10 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI - ETH_MII_CRS - CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 - PA1 - TIM2_CH2 TIM5_CH2 - - - USART2_RTS UART4_RX - - ETH_MII _RX_CLK ETH_RMII _REF_CLK PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - USART2_TX - - - ETH_MDIO PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - USART2_RX - - PA4 - - - - - SPI1_NSS SPI3_NSS I2S3_WS USART2_CK - - PA5 - TIM2_CH1_ETR - TIM8_CH1N - SPI1_SCK - - - - OTG_HS_ULPI_C K PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - - - TIM13_CH1 - - - EVENTOUT - - - EVENTOUT EVENTOUT DocID17050 Rev 13 - - - - OTG_HS_SOF DCMI_HSYNC - EVENTOUT - - - - EVENTOUT - - - DCMI_PIXCK - EVENTOUT TIM14_CH1 - ETH_MII _RX_DV ETH_RMII _CRS_DV - - - EVENTOUT OTG_FS_SOF - - - - EVENTOUT - - DCMI_D0 - EVENTOUT EVENTOUT MCO1 TIM1_CH1 - - I2C3_SCL PA9 - TIM1_CH2 - - I2C3_SMBA PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_ID - - DCMI_D1 - PA11 - TIM1_CH4 - - - - - USART1_CTS - CAN1_RX OTG_FS_DM - - - - EVENTOUT PA12 - TIM1_ETR - - - - - USART1_RTS - CAN1_TX OTG_FS_DP - - - - EVENTOUT - - - - - - - - - - - - - - EVENTOUT - - - - - - - - - - - - - - EVENTOUT TIM 2_CH1 TIM 2_ETR - - - SPI1_NSS SPI3_NSS I2S3_WS - - - - - - - - EVENTOUT JTDI - EVENTOUT PA8 PA15 SPI1_MOSI - TIM1_CH1N PA14 - - - JTMSSWDIO JTCKSWCLK TIM8_CH1N AF15 PA7 PA13 TIM3_CH2 - - - - USART1_CK - - - - USART1_TX - - OTG_HS_ULPI_D0 ETH _MII_COL AF014 Pinouts and pin description 60/10 Table 9. Alternate function mapping AF0 STM32F21xxx AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Port AF10 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI - - AF014 AF15 - EVENTOUT TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - - - PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - - - PB2 - - - - - - - - PB3 JTDO/ TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK I2S3_SCK - - - - - - - - EVENTOUT PB4 JTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO - - - - - - - - EVENTOUT PB5 - - TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI I2S3_SD - - CAN2_RX PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - CAN2_TX - PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - CAN1_RX PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - CAN1_TX PB10 - TIM2_CH3 - - I2C2_SCL - USART3_TX - - DocID17050 Rev 13 PB11 PB12 - TIM2_CH4 TIM1_BKIN - - SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 SYS PB0 Port B AF9 UART4/5/ USART6 - OTG_HS_ULPI_D1 ETH _MII_RXD2 - - OTG_HS_ULPI_D2 ETH _MII_RXD3 - - I2C2_SDA - - USART3_RX - - I2C2_SMBA SPI2_NSS I2S2_WS - USART3_CK - CAN2_RX - - OTG_HS_ULPI_D7 ETH _PPS_OUT - - - EVENTOUT - - - EVENTOUT - DCMI_D10 - EVENTOUT - - DCMI_D5 - EVENTOUT - - FSMC_NL DCMI_VSYNC - EVENTOUT - ETH _MII_TXD3 SDIO_D4 DCMI_D6 - EVENTOUT - - SDIO_D5 DCMI_D7 - EVENTOUT - - - EVENTOUT - - - EVENTOUT OTG_HS_ID - - EVENTOUT EVENTOUT OTG_HS_ULPI_D3 ETH_ MII_RX_ER ETH _MII_TX_EN OTG_HS_ULPI_D4 ETH _RMII_TX_EN ETH _MII_TXD0 OTG_HS_ULPI_D5 ETH _RMII_TXD0 ETH _MII_TXD1 OTG_HS_ULPI_D6 ETH _RMII_TXD1 PB13 - TIM1_CH1N - - - SPI2_SCK I2S2_SCK - USART3_CTS - CAN2_TX - - - PB14 - TIM1_CH2N - TIM8_CH2N - SPI2_MISO - USART3_RTS - TIM12_CH1 - - OTG_HS_DM - - EVENTOUT PB15 RTC_50Hz TIM1_CH3N - TIM8_CH3N - SPI2_MOSI I2S2_SD - - - TIM12_CH2 - - OTG_HS_DP - - EVENTOUT STM32F21xxx Table 9. Alternate function mapping (continued) AF0 Pinouts and pin description 61/10 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Port Port C AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI AF014 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 PC0 - - - - - - - - - - OTG_HS_ULPI_ STP - - - - EVENTOUT PC1 - - - - - - - - - - - ETH_MDC - - - EVENTOUT PC2 - - - - - SPI2_MISO - - - - ETH _MII_TXD2 - - - EVENTOUT - - - EVENTOUT - - - EVENTOUT - - - EVENTOUT SDIO_D6 DCMI_D0 - EVENTOUT OTG_HS_ULPI_ DIR OTG_HS_ULPI_ NXT ETH _MII_TX_CLK ETH_MII_RXD0 ETH_RMII_RXD0 ETH _MII_RXD1 ETH _RMII_RXD1 PC3 - - - - - SPI2_MOSI - - - - PC4 - - - - - - - - - - - PC5 - - - - - - - - - - - PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - - PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - - - SDIO_D7 DCMI_D1 - EVENTOUT PC8 - - TIM3_CH3 TIM8_CH3 - - - - USART6_CK - - - SDIO_D0 DCMI_D2 - EVENTOUT - DocID17050 Rev 13 PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN I2S3_CKIN - - - - - SDIO_D1 DCMI_D3 - EVENTOUT PC10 - - - - - - SPI3_SCK I2S3_SCK USART3_TX UART4_TX - - - SDIO_D2 DCMI_D8 - EVENTOUT EVENTOUT PC11 - - - - - - SPI3_MISO USART3_RX UART4_RX - - - SDIO_D3 DCMI_D4 - PC12 - - - - - - SPI3_MOSI I2S3_SD USART3_CK UART5_TX - - - SDIO_CK DCMI_D9 - EVENTOUT PC13 - - - - - - - - - - - - - - - EVENTOUT - - - - - - - - - - - - - - - EVENTOUT - - - - - - - - - - - - - - - EVENTOUT PC14OSC32_IN PC15OSC32_OU T Pinouts and pin description 62/10 Table 9. Alternate function mapping (continued) AF0 STM32F21xxx AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Port AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI FSMC_D2 - AF014 AF15 - EVENTOUT SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 PD0 - - - - - - - - - CAN1_RX - - PD1 - - - - - - - - - CAN1_TX - - FSMC_D3 - - EVENTOUT PD2 - - TIM3_ETR - - - - - UART5_RX - - - SDIO_CMD DCMI_D11 - EVENTOUT PD3 - - - - - - - USART2_CTS - - - - FSMC_CLK - - EVENTOUT PD4 - - - - - - - USART2_RTS - - - - FSMC_NOE - - EVENTOUT PD5 - - - - - - - USART2_TX - - - - FSMC_NWE - - EVENTOUT PD6 - - - - - - - USART2_RX - - - - FSMC_NWAIT - - EVENTOUT PD7 - - - - - - - USART2_CK - - - - FSMC_NE1/ FSMC_NCE2 - - EVENTOUT Port D PD8 - - - - - - - USART3_TX - - - - FSMC_D13 - - EVENTOUT PD9 - - - - - - - USART3_RX - - - - FSMC_D14 - - EVENTOUT PD10 - - - - - - - USART3_CK - - - - FSMC_D15 - - EVENTOUT DocID17050 Rev 13 PD11 - - - - - - - USART3_CTS - - - - FSMC_A16 - - EVENTOUT PD12 - - TIM4_CH1 - - - - USART3_RTS - - - - FSMC_A17 - - EVENTOUT - - TIM4_CH2 - - - - - - - - - FSMC_A18 - - EVENTOUT PD14 - - TIM4_CH3 - - - - - - - - - FSMC_D0 - - EVENTOUT PD15 - - TIM4_CH4 - - - - - - - - - FSMC_D1 - - EVENTOUT PE0 - - TIM4_ETR - - - - - - - - - FSMC_NBL0 DCMI_D2 - EVENTOUT PE1 - - - - - - - - - - - - FSMC_NBL1 DCMI_D3 - EVENTOUT PE2 TRACECLK - - - - - - - - - - ETH _MII_TXD3 FSMC_A23 - - EVENTOUT PE3 TRACED0 - - - - - - - - - - - FSMC_A19 - - EVENTOUT PE4 TRACED1 - - - - - - - - - - - FSMC_A20 DCMI_D4 - EVENTOUT PE5 TRACED2 - - TIM9_CH1 - - - - - - - - FSMC_A21 DCMI_D6 - EVENTOUT PE6 TRACED3 - - TIM9_CH2 - - - - - - - - FSMC_A22 DCMI_D7 - EVENTOUT PE7 - TIM1_ETR - - - - - - - - - - FSMC_D4 - - EVENTOUT PE8 - TIM1_CH1N - - - - - - - - - - FSMC_D5 - - EVENTOUT Port E PE9 - TIM1_CH1 - - - - - - - - - - FSMC_D6 - - EVENTOUT PE10 - TIM1_CH2N - - - - - - - - - - FSMC_D7 - - EVENTOUT 63/10 PE11 - TIM1_CH2 - - - - - - - - - - FSMC_D8 - - EVENTOUT PE12 - TIM1_CH3N - - - - - - - - - - FSMC_D9 - - EVENTOUT PE13 - TIM1_CH3 - - - - - - - - - - FSMC_D10 - - EVENTOUT PE14 - TIM1_CH4 - - - - - - - - - - FSMC_D11 - - EVENTOUT PE15 - TIM1_BKIN - - - - - - - - - - FSMC_D12 - - EVENTOUT Pinouts and pin description PD13 STM32F21xxx Table 9. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Port PF0 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 UART4/5/ USART6 - - - - I2C2_SDA - - - - - - - FSMC_A0 AF014 AF15 - - EVENTOUT PF1 - - - - I2C2_SCL - - - - - - FSMC_A1 - - EVENTOUT PF2 - - - - I2C2_SMBA - - - - - - - FSMC_A2 - - EVENTOUT PF3 - - - - - - - - - - - - FSMC_A3 - - EVENTOUT PF4 - - - - - - - - - - - - FSMC_A4 - - EVENTOUT PF5 - - - - - - - - - - - - FSMC_A5 - - EVENTOUT PF6 - - - TIM10_CH1 - - - - - - - - FSMC_NIORD - - EVENTOUT PF7 - - - TIM11_CH1 - - - - - - - - FSMC_NREG - - EVENTOUT PF8 - - - - - - - - - TIM13_CH1 - - FSMC_NIOWR - - EVENTOUT PF9 - - - - - - - - - TIM14_CH1 - - FSMC_CD - - EVENTOUT FSMC_INTR Pinouts and pin description 64/10 Table 9. Alternate function mapping (continued) AF0 Port F DocID17050 Rev 13 Port G PF10 - - - - - - - - - - - - PF11 - - - - - - - - - - - - PF12 - - - - - - - - - - - - PF13 - - - - - - - - - - - - PF14 - - - - - - - - - - - PF15 - - - - - - - - - - - PG0 - - - - - - - - - - PG1 - - - - - - - - - PG2 - - - - - - - - PG3 - - - - - - - - PG4 - - - - - - - PG5 - - - - - - PG6 - - - - - PG7 - - - - - PG8 - - - - PG9 - - - PG10 - - - - - - - EVENTOUT - EVENTOUT FSMC_A6 - - EVENTOUT FSMC_A7 - - EVENTOUT - FSMC_A8 - - EVENTOUT - FSMC_A9 - - EVENTOUT - - FSMC_A10 - - EVENTOUT - - - FSMC_A11 - - EVENTOUT - - - - FSMC_A12 - - EVENTOUT - - - - FSMC_A13 - - EVENTOUT - - - - - FSMC_A14 - - EVENTOUT - - - - - - FSMC_A15 - - EVENTOUT - - - - - - - FSMC_INT2 - - EVENTOUT - - - USART6_CK - - - FSMC_INT3 - - EVENTOUT - - - - USART6_RTS - - ETH _PPS_OUT - - - EVENTOUT - - - - - USART6_RX - - - - - EVENTOUT - - - - - - - - - - EVENTOUT - - EVENTOUT - - - - - - - - PG12 - - - - - - - - USART6_RTS - - PG13 - - - - - - - - UART6_CTS - - PG14 - - - - - - - - USART6_TX - - PG15 - - - - - - - - USART6_CTS - - - FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 ETH _MII_TX_EN ETH FSMC_NCE4_2 _RMII_TX_EN ETH _MII_TXD0 ETH _RMII_TXD0 ETH _MII_TXD1 ETH _RMII_TXD1 - FSMC_NE4 - - EVENTOUT FSMC_A24 - - EVENTOUT FSMC_A25 - - EVENTOUT - DCMI_D13 - EVENTOUT STM32F21xxx PG11 DCMI_D12 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS PH0 OSC_IN PH1 OSC_OUT Port H TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 - - - SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI AF014 AF15 - - - - - - - - - - - - EVENTOUT - - - - - - - - - - - - EVENTOUT PH2 - - - - - - - - ETH _MII_CRS - - - EVENTOUT PH3 - - - - - - - - ETH _MII_COL - - - EVENTOUT PH4 - - I2C2_SCL - - - - - OTG_HS_ULPI_N XT - - - - EVENTOUT PH5 - - I2C2_SDA - - - - - - - - - - EVENTOUT PH6 - - I2C2_SMBA - - - - TIM12_CH1 - ETH _MII_RXD2 - - - EVENTOUT PH7 - - I2C3_SCL - - - - - - ETH _MII_RXD3 - - - EVENTOUT PH8 - - I2C3_SDA - - - - - - - - DCMI_HSYNC - EVENTOUT PH9 - - I2C3_SMBA - - - - TIM12_CH2 - - - DCMI_D0 - EVENTOUT DocID17050 Rev 13 PH10 - - TIM5_CH1 - - - - - - - - DCMI_D1 - EVENTOUT PH11 - - TIM5_CH2 - - - - - - - - DCMI_D2 - EVENTOUT PH12 - - TIM5_CH3 - - - - - - - - DCMI_D3 - EVENTOUT PH13 - - TIM8_CH1N - - - - CAN1_TX - - - - - EVENTOUT PH14 - - TIM8_CH2N - - - - - - - - DCMI_D4 - EVENTOUT PH15 - - - - - - - - - - DCMI_D11 - EVENTOUT PI0 - - - - - - - - - DCMI_D13 - EVENTOUT PI1 - - - - - - - - - DCMI_D8 - EVENTOUT PI2 - - TIM8_CH3N SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK TIM5_CH4 TIM8_CH4 SPI2_MISO - - - - - - - DCMI_D9 - EVENTOUT EVENTOUT PI3 - - TIM8_ETR SPI2_MOSI I2S2_SD - - - - - - - DCMI_D10 - PI4 - - TIM8_BKIN - - - - - - - - DCMI_D5 - EVENTOUT PI5 - - TIM8_CH1 - - - - - - - - DCMI_VSYNC - EVENTOUT PI6 - - TIM8_CH2 - - - - - - - - DCMI_D6 - EVENTOUT TIM8_CH3 STM32F21xxx Table 9. Alternate function mapping (continued) AF0 Port I - - - - - - - - - - DCMI_D7 - EVENTOUT PI8 - - - - - - - - - - - - EVENTOUT EVENTOUT PI9 - - - - - - CAN1_RX - - - - - PI10 - - - - - - - - ETH _MII_RX_ER - - - EVENTOUT PI11 - - - - - - - OTG_HS_ULPI_ DIR - - - - EVENTOUT 65/10 Pinouts and pin description PI7 Memory mapping 5 STM32F21xxx Memory mapping The memory map is shown in Figure 14. 66/180 DocID17050 Rev 13 STM32F21xxx Memory mapping Figure 14. Memory map 2ESERVED &3-#CONTROLREGISTER X! X!&&& &3-#BANK0##ARD X X&&&&&&& &3-#BANK.!.$.!.$ X&&&&&&&& X% X$&&&&&&&  -BYTE BLOCK .OTUSED X# X"&&&&&&&  -BYTE BLOCK &3-#REGISTERS X! X&&&&&&& X X&&&&&&& X X&&&&&&&  -BYTE BLOCK &3-#BANK BANK  -BYTE BLOCK &3-#BANK BANK  -BYTE BLOCK 0ERIPHERALS X X&&&&&&&  -BYTE BLOCK 32!- 32!-+"ALIASED BYBIT BANDING X X&&&&&&&  -BYTE BLOCK #ODE X 2ESERVED 32!-+"ALIASED BYBIT BANDING 2ESERVED /PTION"YTES 2ESERVED 3YSTEMMEMORY/40 2ESERVED &LASH 2ESERVED !LIASEDTO&LASHSYSTEM MEMORYOR32!-DEPENDING ONTHE"//4PINS X X&&&&&&& X# X&&&& X X"&&& X&&&# X&&&&&&& X&&&# X&&&# X&&&! X&&&&&& X&&& X&&&!& X X&&&&&&& X X&&&&& X# X&&&&&& X X&&&&&&& &3-#BANK.!.$.!.$ X X&&&&&&& &3-#BANK./2032!- X# X&&&&&&& &3-#BANK./2032!- X X"&&&&&& &3-#BANK./2032!- X X&&&&&& &3-#BANK./2032!- X X&&&&&& 2ESERVED 2.' (!3( #290 2ESERVED $#-) 2ESERVED 53"/4'&3 2ESERVED 53"/4'(3 2ESERVED %4(%2.%4 2ESERVED $-! $-! 2ESERVED "+032!&LASHINTERFACE 2ESETCLOCKCONTROLLER2## 2ESERVED #2# 2ESERVED 0ORT) 0ORT( 0ORT' 0ORT& 0ORT% 0ORT$ 0ORT# 0ORT" 0ORT! 2ESERVED 4)- 4)- 4)- %84) 393#&' 2ESERVED 30) 3$)/ 2ESERVED  -BYTE BLOCK #ORTEX -gS INTERNAL PERIPHERALS X! X"&&&&&&& 2ESERVED !$# !$# !$# 2ESERVED 53!24 53!24 2ESERVED 4)-07- 4)-07- 2ESERVED $!#$!# 072 2ESERVED "X#!. "X#!. 2ESERVED )# )# )# 5!24 5!24 53!24 53!24 2ESERVED 30))3 30))3 2ESERVED )7$' 77$' 24#"+0REGISTERS 2ESERVED 4)- 4)- 4)- 4)- 4)- 4)- 4)- 4)- 4)- X# X&&&&&&& X X&&& X X&& X X&& X X&&& X X&& X X&&& X X&&&& X X&&&&&&& X X&&&& X X&&&& X X&& X X&&& X X&& X X&& X X&&& X X&&& X# X&&& X X"&& X X&& X X&& X X&&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X X&&& X X&& X X&& X X&& X X&& X X&&&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X# X&&& X X"&& X X&& X X&& X X&&&&& AIC DocID17050 Rev 13 67/180 179 Electrical characteristics STM32F21xxx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 15. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 16. Figure 15. Pin loading conditions Figure 16. Pin input voltage -#5PIN -#5PIN #P& 6). -36 68/180 DocID17050 Rev 13 -36 STM32F21xxx 6.1.6 Electrical characteristics Power supply scheme Figure 17. Power supply scheme 9%$7 287 *3,2V ,1 î—) ,2 /RJLF .HUQHOORJLF &38 GLJLWDO 5$0 9&$3B 9&$3B 9''  îQ) î—) /HYHOVKLIWHU 9 9'' %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 3R ZHUVZL WFK 9ROWDJH UHJXODWRU 966  )ODVKPHPRU\ 5(*2)) 9'' 9''$ 95() Q) —) Q) —) 95() 95() $'& $QDORJ 5&V3//  966$ 069 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect REGOFF pin, refer to Section 3.16: Voltage regulator. 3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB, to ensure good device operation. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect device operation. DocID17050 Rev 13 69/180 179 Electrical characteristics 6.1.7 STM32F21xxx Current consumption measurement Figure 18. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics, Table 11: Current characteristics, and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 10. Voltage characteristics Symbol Ratings VDD–VSS External main supply voltage (including VDDA, VDD)(1) VIN |ΔVDDx| |VSSX − VSS| VESD(HBM) Min Max –0.3 4.0 VSS–0.3 VDD+4 VSS–0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 Input voltage on five-volt tolerant pin(2) Input voltage on any other pin Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 11 for the values of the maximum allowed injected current. 70/180 DocID17050 Rev 13 - STM32F21xxx Electrical characteristics Table 11. Current characteristics Symbol Ratings Max IVDD Total current into VDD power lines (source)(1) 120 IVSS (1) Total current out of VSS ground lines (sink) 120 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IIO IINJ(PIN) (2) ΣIINJ(PIN) (4) Injected current on five-volt tolerant I/O (3) Unit mA –5/+0 (4) ±5 Injected current on any other pin Total injected current (sum of all I/O and control pins) (5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 4. In this case HCLK = system clock/2. DocID17050 Rev 13 79/180 179 Electrical characteristics STM32F21xxx Figure 21. Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals ON    # )$$25. M!   #  #   #  #  #   #          #05FREQUNECY-(Z -36 Figure 22. Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals OFF   )$$25. M!  #   #  #  #   #  #   #        #05&REQUENCY-(Z   -36 80/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 23. Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON   )$$25. M!       #  #         #05FREQUNECY-(Z    -36 Figure 24. Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF       ) $$25. M!   #   #          #05&REQUENCY-(Z   -36 DocID17050 Rev 13 81/180 179 Electrical characteristics STM32F21xxx Table 21. Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 °C TA = 85 °C TA = 105 °C 120 MHz 38 51 61 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.7 120 MHz 8 21 31 90 MHz 7 20 30 60 MHz 5 18 28 30 MHz 3.5 16.0 26.0 25 MHz 2.5 16.0 25.0 16 MHz 2.1 15.1 25.0 8 MHz 1.7 15.0 25.0 4 MHz 1.5 14.6 24.6 2 MHz 1.4 14.2 24.3 Unit mA 1. Guaranteed by characterization results, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 82/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 25. Typical current consumption vs. temperature in Sleep mode, peripherals ON   )$$3,%%0 M!   #   #   #  #   #   #  #         #05&REQUENCY-(Z    -36 Figure 26. Typical current consumption vs. temperature in Sleep mode, peripherals OFF   )$$3,%%0 M!   #  #   #  #   #  #   #        #05&REQUENCY-(Z    -36 DocID17050 Rev 13 83/180 179 Electrical characteristics STM32F21xxx Table 22. Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Conditions Supply current in Stop mode with main regulator in Run mode IDD_STOP Max TA = 25 °C TA = 25 °C TA = 85 °C Unit TA = 105 °C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.2 11.00 20.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.50 1.2 11.00 20.00 mA Flash in Stop mode, low-speed and high-speed Supply current internal RC oscillators and high-speed oscillator in Stop mode OFF (no independent watchdog) with main Flash in Deep power down mode, low-speed regulator in and high-speed internal RC oscillators and Low-power high-speed oscillator OFF (no independent mode watchdog) 0.35 1.1 8.00 15.00 0.30 1.1 8.00 15.00 Figure 27. Typical current consumption vs. temperature in Stop mode  )DD?STOP?MR?FLHSTOP )DD?STOP?MR?FLHDEEP )DD?STOP?LP?FLHSTOP  ) $$34/0 M! )DD?STOP?LP?FLHDEEP                   4EMPERATURE # -36 1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes 84/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 23. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.0 3.4 4.0 15.1 25.8 2.4 2.7 3.3 12.4 20.5 2.4 2.6 3.0 12.5 24.8 1.7 1.9 2.2 9.8 19.2 Backup SRAM ON, low-speed oscillator and RTC ON Supply current Backup SRAM OFF, lowIDD_STBY in Standby speed oscillator and RTC ON mode Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF Unit VDD = 3.6 V µA 1. Guaranteed by characterization results, not tested in production. Table 24. Typical and maximum current consumptions in VBAT mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 1.29 1.42 1.68 12 19 0.62 0.73 0.96 8 10 0.79 0.81 0.86 9 16 0.10 0.10 0.10 5 7 Backup SRAM ON, low-speed oscillator and RTC ON Backup Backup SRAM OFF, low-speed IDD_VBAT domain supply oscillator and RTC ON current Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF Unit VDD = 3.6 V µA 1. Guaranteed by characterization results, not tested in production. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 25. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware. • All peripherals are disabled unless otherwise mentioned • The given value is calculated by measuring the current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • The code is running from Flash memory and the Flash memory access time is equal to 3 wait states at 120 MHz • Prefetch and Cache ON • When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2 • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. DocID17050 Rev 13 85/180 179 Electrical characteristics STM32F21xxx Table 25. Peripheral current consumption Peripheral(1) AHB1 AHB2 AHB3 AHB2 86/180 Typical consumption at 25 °C GPIO A 0.45 GPIO B 0.43 GPIO C 0.46 GPIO D 0.44 GPIO E 0.44 GPIO F 0.42 GPIO G 0.44 GPIO H 0.42 GPIO I 0.43 OTG_HS + ULPI 3.64 CRC 1.17 BKPSRAM 0.21 DMA1 2.76 DMA2 2.85 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 2.99 OTG_FS 3.16 DCMI 0.60 FSMC 1.74 CRYPTO 0.39 HASH 0.50 RNG 0.43 DocID17050 Rev 13 Unit mA mA STM32F21xxx Electrical characteristics Table 25. Peripheral current consumption (continued) Peripheral(1) APB1 Typical consumption at 25 °C TIM2 0.61 TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 TIM14 0.25 USART2 0.25 USART3 0.25 UART4 0.25 UART5 0.26 I2C1 0.25 I2C2 0.25 I2C3 0.25 SPI2 0.20/0.10 SPI3 0.18/0.09 CAN1 0.31 CAN2 Unit mA 0.30 (2) 1.11 DAC channel 1(3) 1.11 PWR 0.15 WWDG 0.15 DAC channel 1 DocID17050 Rev 13 87/180 179 Electrical characteristics STM32F21xxx Table 25. Peripheral current consumption (continued) Peripheral(1) APB2 Typical consumption at 25 °C SDIO 0.69 TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 TIM11 0.39 (4) ADC1 2.13 ADC2(4) 2.04 (4) ADC3 2.12 SPI1 1.20 USART1 0.38 USART6 0.37 Unit mA 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register. 6.3.7 Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13. Table 26. Low-power mode wakeup timings Symbol tWUSLEEP(2) tWUSTOP(2) tWUSTDBY(2)(3) Min(1) Typ(1) Max(1) Unit Wakeup from Sleep mode - 1 - µs Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low-power mode) - 17 40 Wakeup from Stop mode (regulator in low-power mode and Flash memory in Deep power down mode) - 110 - 260 375 480 Parameter Wakeup from Standby mode µs µs 1. Guaranteed by characterization results, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. 88/180 DocID17050 Rev 13 STM32F21xxx 6.3.8 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 27 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 13. Table 27. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 - 26 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD 5 - - - - 20 - - 5 - pF - 45 - 55 % VSS ≤VIN ≤VDD - - ±1 µA tw(HSE) tw(HSE) OSC_IN high or low tr(HSE) tf(HSE) OSC_IN rise or fall time(1) Cin(HSE) - time(1) ns OSC_IN input capacitance(1) DuCy(HSE) Duty cycle IL V OSC_IN Input leakage current 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 28 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 13. Table 28. Low-speed external user clock characteristics Symbol Parameter fLSE_ext Min Typ Max Unit User External clock source frequency(1) - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) Cin(LSE) Conditions - ns OSC32_IN rise or fall time(1) - - 50 - - 5 - pF - 30 - 70 % VSS ≤VIN ≤VDD - - ±1 µA OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL V OSC32_IN Input leakage current 1. Guaranteed by design, not tested in production. DocID17050 Rev 13 89/180 179 Electrical characteristics STM32F21xxx Figure 28. High-speed external clock source AC timing diagram 6(3%(     6(3%, TR(3% TF(3% T7(3% T T7(3% 4(3% %XTERNAL CLOCKSOURCE F(3%?EXT /3#?). ), 34-& AI Figure 29. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/   WU/6( WI/6( W:/6( 26&B,1 ,/ W:/6( W 7/6( ([WHUQDO FORFNVRXUFH I/6(BH[W 670) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 90/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 29. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol fOSC_IN RF IDD gm tSU(HSE(3) Parameter Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - Startup 5 - - mA/V VDD is stabilized - 2 - ms HSE current consumption Oscillator transconductance Startup time µA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results, not tested in production. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 30. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) 26&B28 7 %LDV FRQWUROOHG JDLQ 670) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 30. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID17050 Rev 13 91/180 179 Electrical characteristics STM32F21xxx Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - - 18.4 - MΩ IDD LSE current consumption - - - 1 µA gm Oscillator Transconductance - 2.8 - - µA/V VDD is stabilized - 2 - s tSU(LSE)(2) startup time 1. Guaranteed by design, not tested in production. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 31. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26&B28 7 &/ 670) DL 6.3.9 Internal clock source characteristics The parameters given in Table 31 and Table 32 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13. High-speed internal (HSI) RC oscillator Table 31. HSI oscillator characteristics (1) Symbol fHSI Parameter Min Typ Max Unit - - 16 - MHz - - 1 % –8 - 4.5 % –4 - 4 % –1 - 1 % Frequency HSI user-trimming ACCHSI tsu(HSI) Conditions step(2) TA = –40 to 105 Accuracy of the HSI oscillator TA = –10 to 85 TA = 25 °C(4) °C(3) (2) HSI oscillator startup time - - 2.2 4.0 µs (2) HSI oscillator power consumption - - 60 80 µA IDD(HSI) 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. 92/180 °C(3) DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 32. ACCHSI versus temperature ŵĂdž ĂǀŐ ϲ ŵŝŶ EŽƌŵĂůŝnjĞĚĚĞǀŝĂƚŝŽŶ;йͿ ϰ Ϯ Ϭ ͲϮ Ͳϰ Ͳϲ Ͳϴ Ͳϰϱ Ͳϯϱ ͲϮϱ Ͳϭϱ Ͳϱ ϱ ϭϱ Ϯϱ ϯϱ ϰϱ ϱϱ ϲϱ ϳϱ ϴϱ ϵϱ ϭϬϱ ϭϭϱ ϭϮϱ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ -36 Low-speed internal (LSI) RC oscillator Table 32. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.4 0.6 µA Frequency 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization results, not tested in production. 3. Guaranteed by design, not tested in production. DocID17050 Rev 13 93/180 179 Electrical characteristics STM32F21xxx Figure 33. ACCLSI versus temperature  MAX  AVG MIN .ORMALIZEDDEVIATI ON                   4EMPERAT URE #       -36 6.3.10 PLL characteristics The parameters given in Table 33 and Table 34 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 13. Table 33. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10(2) MHz fPLL_OUT PLL multiplier output clock - 24 - 120 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - - - 48 MHz fVCO_OUT PLL VCO output - 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 94/180 DocID17050 Rev 13 µs STM32F21xxx Electrical characteristics Table 33. Main PLL characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 25 - peak to peak - ±150 - RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA Cycle-to-cycle jitter System clock 120 MHz Period Jitter (3) Jitter Unit ps 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization results, not tested in production. Table 34. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10(2) MHz fPLLI2S_OUT PLLI2S multiplier output clock - - - 216 MHz fVCO_OUT PLLI2S VCO output - 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 DocID17050 Rev 13 µs 95/180 179 Electrical characteristics STM32F21xxx Table 34. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - Average frequency of 12.288 MHz N=432, R=5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master I2S clock jitter (3) Jitter 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Guaranteed by characterization results, not tested in production. 96/180 DocID17050 Rev 13 Unit ps STM32F21xxx 6.3.11 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 41: EMI characteristics). It is available only on the main PLL. Table 35. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 MODEPER * INCSTEP - - −1 - 1. Guaranteed by design, not tested in production. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 15 – 1 ) × PLLN ) As a result: md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 DocID17050 Rev 13 15 – 1 ) × 240 ) = 2.0002%(peak) 97/180 179 Electrical characteristics STM32F21xxx Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 34. PLL output clock waveforms in center spread mode )UHTXHQF\ 3//B287 PG ) PG WPRGH [WPRGH 7LPH 069 Figure 35. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH [WPRGH 7LPH 069 6.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. 98/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 36. Flash memory characteristics Symbol IDD Parameter Conditions Supply current Min Typ Max Write / Erase 8-bit mode VDD = 1.8 V - 5 - Write / Erase 16-bit mode VDD = 2.1 V - 8 - Write / Erase 32-bit mode VDD = 3.3 V - 12 - Unit mA Table 37. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Mass erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V µs ms ms s s 1. Guaranteed by characterization results, not tested in production. 2. The maximum programming time is measured after 100K erase operations. DocID17050 Rev 13 99/180 179 Electrical characteristics STM32F21xxx Table 38. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.6 V VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 39. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C Unit kcycles Years 1. Guaranteed by characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. 100/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics The test results are given in Table 40. They are based on the EMS levels and classes defined in application note AN1709. Table 40. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP176, TA = Voltage limits to be applied on any I/O pin to +25 °C, fHCLK = 120 MHz, conforms induce a functional disturbance to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 120 MHz, conforms to IEC 61000-4-2 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). DocID17050 Rev 13 101/180 179 Electrical characteristics STM32F21xxx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 41. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/120 MHz VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, peripheral clock disabled SEMI 6.3.14 Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, PLL spread spectrum enabled, peripheral clock disabled 0.1 to 30 MHz 30 to 130 MHz 25 dBµV SAE EMI Level 4 - 0.1 to 30 MHz 28 30 to 130 MHz 26 130 MHz to 1GHz 22 SAE EMI level 4 130 MHz to 1GHz dBµV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 42. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) 2 2000(2) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 V 1. Guaranteed by characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. 102/180 Unit DocID17050 Rev 13 II 500 STM32F21xxx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 43. Electrical sensitivities Symbol LU 6.3.15 Parameter Conditions Static latch-up class Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 44. Table 44. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 pin –0 NA Injected current on NRST pin –0 NA Injected current on TTa pins: PA4 and PA5 –0 +5 Injected current on all FT pins –5 NA Unit mA 1. NA stands for “not applicable”. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DocID17050 Rev 13 103/180 179 Electrical characteristics 6.3.16 STM32F21xxx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 13: General operating conditions. All I/Os are CMOS and TTL compliant. Table 45. I/O static characteristics Symbol Parameter FT, TTa and NRST I/O input low level voltage VIL BOOT0 I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) VIH Ilkg 104/180 Typ 1.7 V≤VDD≤3.6 V - - 1.75 V≤VDD ≤3.6 V, –40 °C≤TA ≤105 °C - - 1.7 V≤VDD ≤3.6 V, 0 °C≤TA ≤105 °C - 1.75 V≤VDD ≤3.6 V, –40 °C≤TA ≤105 °C BOOT0 I/O input high level voltage I/O input leakage current (4) (5) Max Unit 0.35VDD–0.04(1) 0.3VDD(2) V 0.1VDD+0.1(1) 0.45VDD+0.3(1) 0.7VDD(2) - V 0.17VDD+0.7(1) - - 1.7 V≤VDD≤3.6 V 0.45VDD+0.3(1) - - 1.75 V≤VDD ≤3.6 V, –40 °C≤TA ≤105 °C 10%VDDIO(1)(3) - - 1.7 V≤VDD ≤3.6 V, 0 °C≤TA ≤105 °C 100(1) - - VSS ≤VIN ≤VDD - - ±1 VIN = 5 V - - 3 1.7 V≤VDD ≤3.6 V, 0 °C≤TA ≤105 °C BOOT0 I/O input hysteresis I/O FT input leakage current Min 1.7 V≤VDD≤3.6 V FT, TTa and NRST I/O input hysteresis VHYS Conditions DocID17050 Rev 13 V µA STM32F21xxx Electrical characteristics Table 45. I/O static characteristics (continued) Symbol RPU RPD CIO(8) Parameter Weak pull-up equivalent resistor(6) Conditions Min Typ Max All pins except for PA10/PB12 (OTG_FS_ID, OTG_HS_ID) VIN = VSS 30 40 50 PA10/PB12 (OTG_FS_ID, OTG_HS_ID) - 7 10 14 All pins except for PA10/PB12 Weak pull-down (OTG_FS_ID, equivalent OTG_HS_ID) resistor(7) PA10/PB12 (OTG_FS_ID, OTG_HS_ID) I/O pin capacitance Unit kΩ VIN = VDD 30 40 50 - 7 10 14 - - 5 - pF 1. Guaranteed by design, not tested in production. 2. Guaranteed by tests in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 44: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 44: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 36. DocID17050 Rev 13 105/180 179 Electrical characteristics STM32F21xxx Figure 36. FT I/O input characteristics 9,/9,+9  ' 9'   L P ,+ Q 9 QW H P LUH 77/UHTXLUHPHQW U 9,+PLQ 9  26 0   &  '  9' Q  R  WL  XF  LQ RG +P , SU  9  LQ QV WLR HG VW XOD P L 7H V LJQ HV  $UHDQRW Q' R  G   VH GHWHUPLQHG '' D % 9    D[ ,/P QV9 ODWLR X LP V  VLJQ Q'H HGR 77/UHTXLUHPHQW9,/PD[ %DV  9  7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' X HT 9''9       069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 11). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 11). Output voltage levels Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13. All I/Os are CMOS and TTL compliant. 106/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 46. Output voltage characteristics(1) Symbol Parameter VOL(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions Min Max CMOS ports IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD–0.4 - - 0.4 2.4 - - 1.3 VDD–1.3 - - 0.4 VDD–0.4 - Unit V TTL ports IIO =+ 8mA 2.7 V < VDD < 3.6 V V IIO = +20 mA 2.7 V < VDD < 3.6 V V IIO = +6 mA 2 V < VDD < 2.7 V V 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 47, respectively. Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 13. Table 47. I/O AC characteristics(1) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(2) 00 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD > 2.70 V - - 4 CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - 8 CL = 10 pF, VDD > 1.8 V - - 4 CL = 50 pF, VDD = 1.8 V to 3.6 V - - 100 DocID17050 Rev 13 Unit MHz ns 107/180 179 Electrical characteristics STM32F21xxx Table 47. I/O AC characteristics(1) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(2) 01 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(2) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(2) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD > 2.70 V - - 25 CL = 50 pF, VDD > 1.8 V - - 12.5 CL = 10 pF, VDD > 2.70 V - - 50(3) CL = 10 pF, VDD > 1.8 V - - 20 CL = 50 pF, VDD >2.7 V - - 10 CL = 50 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 6 CL = 10 pF, VDD > 1.8 V - - 10 CL = 40 pF, VDD > 2.70 V - - 25 CL = 40 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 100(3) CL = 10 pF, VDD > 1.8 V - - 50(3) CL = 40 pF, VDD > 2.70 V - - 6 CL = 40 pF, VDD > 1.8 V - - 10 CL = 10 pF, VDD > 2.70 V - - 4 CL = 10 pF, VDD > 1.8 V - -3 6 CL = 30 pF, VDD > 2.70 V - - 100(3) CL = 30 pF, VDD > 1.8 V - - 50(3) CL = 10 pF, VDD > 2.70 V - - 120(3) CL = 10 pF, VDD > 1.8 V - - 100(3) CL = 30 pF, VDD > 2.70 V - - 4 CL = 30 pF, VDD > 1.8 V - - 6 CL = 10 pF, VDD > 2.70 V - - 2.5 CL = 10 pF, VDD > 1.8 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller - 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 2. The maximum frequency is defined in Figure 37. 3. For maximum frequencies above 50 MHz and VDD above 2.4 V, the compensation cell should be used. 108/180 DocID17050 Rev 13 Unit MHz ns MHz ns MHz ns ns STM32F21xxx Electrical characteristics Figure 37. I/O AC characteristics definition       (;7(51$/ 287387 21&/ WU,2RXW WI,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´  6.3.17 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 48). Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 13. Table 48. NRST pin characteristics Symbol RPU Parameter Conditions Min Typ Max Unit VIN = VSS 30 40 50 kΩ - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs Weak pull-up equivalent resistor(1) VF(NRST)(2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design, not tested in production. Figure 38. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW  1567  538 ,QWHUQDO5HVHW )LOWHU —) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 48. Otherwise the reset is not taken into account by the device. DocID17050 Rev 13 109/180 179 Electrical characteristics 6.3.18 STM32F21xxx TIM timer characteristics The parameters given in Table 49 and Table 50 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 49. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Min Max Unit 1 - tTIMxCLK 16.7 - ns 1 - tTIMxCLK 33.3 - ns Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 30 MHz Timer resolution - 16/32 bit 65536 tTIMxCLK 1092 µs - tTIMxCLK 71582788 µs - 65536 × 65536 tTIMxCLK - 71.6 s Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 60 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 30 MHz fEXT ResTIM tCOUNTER 16-bit counter clock period 1 when internal clock is fTIMxCLK = 60 MHz 0.0167 selected APB1= 30 MHz 32-bit counter clock period 1 when internal clock is 0.0167 selected tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. 110/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 50. Characteristics of TIMx connected to the APB2 domain(1) Symbol tres(TIM) Parameter Timer resolution time Conditions AHB/APB2 prescaler distinct from 1, fTIMxCLK = 120 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 60 MHz fEXT ResTIM Timer external clock frequency on CH1 to CH4 Timer resolution fTIMxCLK = 120 MHz tCOUNTER 16-bit counter clock period APB2 = 60 MHz when internal clock is selected tMAX_COUNT Maximum possible count Min Max Unit 1 - tTIMxCLK 8.3 - ns 1 - tTIMxCLK 16.7 - ns 0 fTIMxCLK/2 MHz 0 60 MHz - 16 bit 1 65536 tTIMxCLK 0.0083 546 µs - 65536 × 65536 tTIMxCLK - 35.79 s 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 6.3.19 Communications interfaces I2C interface characteristics STM32F215xx and STM32F217xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 51. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). DocID17050 Rev 13 111/180 179 Electrical characteristics STM32F21xxx Table 51. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of the spikes that are suppressed by the analog filter 0 50(4) 0 50 ns µs ns µs 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 112/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 39. I2C bus AC waveforms and measurement circuit s ''B,& s ''B,& 53 53 670)[[ 56 6'$ ,ð&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX67$ 6'$ WI6'$ WU6'$ WK67$ WVX6'$ WZ67267$ 6723 WK6'$ WZ6&/+ 6&/ WU6&/ WZ6&// WI6&/ WVX672 DLF 1. RS= series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 52. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. DocID17050 Rev 13 113/180 179 Electrical characteristics STM32F21xxx I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 13. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53. SPI characteristics Symbol fSCK 1/tc(SCK) Parameter Conditions SPI clock frequency Min Max SPI1 master/slave mode - 30 SPI2/SPI3 master/slave mode - 15 - 8 ns % tr(SCL) tf(SCL) SPI clock rise and fall time Capacitive load: C = 30 pF, fPCLK = 30 MHz DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 2tPCLK - SCK high and low time Master mode, fPCLK = 30 MHz, presc = 2 tPCLK-3 tPCLK+3 (1) tw(SCLH) tw(SCLL)(1) Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 30 MHz 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tsu(MI) (1) tsu(SI)(1) Data input setup time th(MI) (1) th(SI)(1) Data input hold time th(SO) (1) th(MO) (1) Data output hold time Unit MHz ns 1. Guaranteed by characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 114/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 40. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 41. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW W68166 &3+$  &32/  &3+$  &32/  WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 %,7287 WU6&. WI6&. WGLV62 /6%287 WK6, WVX6, 026, ,1387 WK166 WF6&. 06%,1 %,7,1 /6%,1 DLE DocID17050 Rev 13 115/180 179 Electrical characteristics STM32F21xxx Figure 42. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 116/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 54. I2S characteristics Symbol Min Max 1.23 1.24 Slave 0 64FS(1) I2S clock rise and fall time Capacitive load CL = 50 pF - (2) tv(WS) (3) WS valid time Master 0.3 - (3) WS hold time Master 0 - WS setup time Slave 3 - WS hold time Slave 0 - tw(CKH) tw(CKL) (3) CK high and low time Master fPCLK= 30 MHz 396 - tsu(SD_MR) (3) tsu(SD_SR) (3) Data input setup time Master receiver Slave receiver 45 0 - th(SD_MR)(3)(4) th(SD_SR) (3)(4) Data input hold time Master receiver: fPCLK= 30 MHz, Slave receiver: fPCLK= 30 MHz 13 0 - tv(SD_ST) (3)(4) Data output valid time Slave transmitter (after enable edge) - 30 th(SD_ST) (3) Data output hold time Slave transmitter (after enable edge) 10 - tv(SD_MT) (3)(4) Data output valid time Master transmitter (after enable edge) - 6 th(SD_MT) (3) Data output hold time Master transmitter (after enable edge) 0 - fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) th(WS) tsu(WS) Parameter (3) th(WS) (3) (3) Conditions Master, 16-bit data, audio frequency = 48 kHz, main clock disabled Unit MHz ns 1. FS is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. fCK values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of (I2SDIV+ODD)/(2*I2SDIV+ODD) and FS maximum values for each mode/condition. 2. Refer to Table 47: I/O AC characteristics. 3. Guaranteed by design, not tested in production. 4. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. DocID17050 Rev 13 117/180 179 Electrical characteristics STM32F21xxx Figure 43. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Guaranteed by characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 118/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 55. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 56. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min(1) Typ Max(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels RPD RPU VOH Static output level high RL of 1.5 kΩ to 3.6 V(4) RL of 15 kΩ to PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VSS(4) V V V VIN = VDD kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F215xx and STM32F217xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers DocID17050 Rev 13 119/180 179 Electrical characteristics STM32F21xxx Figure 45. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S tr tf ai14137 Table 57. USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Rise/fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification Chapter 7 (version 2.0). USB HS characteristics Table 58 shows the USB HS operating voltage. Table 58. USB HS DC electrical characteristics Symbol Input level Min(1) Max(1) Unit 2.7 3.6 V Min Nominal Max Unit 54 60 66 MHz 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.4 ms Parameter VDD USB OTG HS operating voltage 1. All the voltages are measured from the local ground potential. Table 59. Clock timing parameters Parameter(1) Frequency (first transition) Symbol 8-bit ±10% FSTART_8BIT Frequency (steady state) ±500 ppm FSTEADY Duty cycle (first transition) DSTART_8BIT 8-bit ±10% Duty cycle (steady state) ±500 ppm DSTEADY Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 Host TSTART_HOST - - - - - - PHY preparation time after the first transition TPREP of the input clock 1. Guaranteed by design, not tested in production. 120/180 DocID17050 Rev 13 ms µs STM32F21xxx Electrical characteristics Figure 46. ULPI timing diagram #LOCK #ONTROL)N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA)N  BIT T$# T$# #ONTROLOUT 5,0)?340 T$$ DATAOUT  BIT AIC Table 60. ULPI timing Value(1) Symbol Parameter Unit Min Max Control in (ULPI_DIR) setup time - 2.0 Control in (ULPI_NXT) setup time - 1.5 tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0 - tSD Data in setup time - 2.0 tHD Data in hold time 0 - tDC Control out (ULPI_STP) setup time and hold time - 9.2 tDD Data out available from clock rising edge - 10.7 tSC ns 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Ethernet characteristics Table 61 shows the Ethernet operating voltage. Table 61. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage Min(1) Max(1) Unit 2.7 3.6 V 1. All the voltages are measured from the local ground potential. Table 62 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. DocID17050 Rev 13 121/180 179 Electrical characteristics STM32F21xxx Figure 47. Ethernet SMI timing diagram T-$# %4(?-$# TD-$)/ %4(?-$)// TSU-$)/ TH-$)/ %4(?-$)/) AID Table 62. Dynamics characteristics: Ethernet MAC signals for SMI Symbol Rating Min Typ Max Unit tMDC MDC cycle time (2.38 MHz) 411 420 425 ns td(MDIO) MDIO write data valid time 6 10 13 ns tsu(MDIO) Read data setup time 12 - - ns th(MDIO) 0 - - ns Read data hold time Table 63 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 63. Dynamics characteristics: Ethernet MAC signals for RMII Symbol 122/180 Rating Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 1.5 - - tsu(CRS) Carrier sense set-up time 0 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 9 11 13 td(TXD) Transmit data valid delay time 9 11.5 14 DocID17050 Rev 13 Unit ns STM32F21xxx Electrical characteristics Table 64 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Table 64. Dynamics characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 7.5 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(DV) Data valid setup time 4 - - ns tih(DV) Data valid hold time 0 - - ns tsu(ER) Error setup time 3.5 - - ns tih(ER) Error hold time 0 - - ns td(TXEN) Transmit enable valid delay time - 11 14 ns td(TXD) Transmit data valid delay time - 11 14 ns CAN (controller area network) interface Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). DocID17050 Rev 13 123/180 179 Electrical characteristics 6.3.20 STM32F21xxx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 65 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 13. Table 65. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 1.8 - 3.6 V VREF+ Positive reference voltage - 1.8(1) - VDDA V VDDA = 1.8 to 2.4 V 0.6 - 15 MHz VDDA = 2.4 to 3.6 V 0.6 - 30 MHz fADC = 30 MHz with 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 kΩ - 1.5 - 6 kΩ - - 4 - pF fADC = 30 MHz - - 0.100 µs 1/fADC fADC fTRIG(2) VAIN RAIN(2) ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor tlat(2) Injection trigger conversion latency tlatr(2) Regular trigger conversion latency tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) - - - 3(5) fADC = 30 MHz - - 0.067 µs 1/fADC - - - 2(5) fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC - - 2 3 µs fADC = 30 MHz 12-bit resolution 0.5 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.3 - 16.20 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 124/180 DocID17050 Rev 13 1/fADC STM32F21xxx Electrical characteristics Table 65. ADC characteristics (continued) Symbol fS(2) Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Sampling rate (fADC = 30 MHz) IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 2. Guaranteed by characterization results, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 65. Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 66. ADC accuracy (1) a Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8 to 3.6 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization results, not tested in production. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. DocID17050 Rev 13 125/180 179 Electrical characteristics STM32F21xxx Figure 50. ADC accuracy characteristics 6 $$! 6 2%& ;,3" )$%!, ORDEPENDINGONPACKAGE =   %'     %4      %/  %,  %$  , 3")$%!,   6 33!          6$$! AIC 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/“—$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 65 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 126/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) ^dDϯϮ& s Z&н ;ϭͿ ϭђ&ͬͬϭϬŶ& s  ϭђ&ͬͬϭϬŶ& s ^^ ͬsZ&Ͳ ;ϭͿ ĂŝϭϳϱϯϱĐ 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. DocID17050 Rev 13 127/180 179 Electrical characteristics STM32F21xxx Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$  —)Q) 95()966$  DLF 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.21 DAC electrical characteristics Table 67. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.8 - 3.6 V VREF+ Reference supply voltage 1.8 - 3.6 V VSSA Ground 0 - 0 V - RLOAD(1) Resistive load with buffer ON 5 - - kΩ - RO(1) Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum kΩ resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(1) Capacitive load - - 50 pF DAC_OUT Lower DAC_OUT voltage with buffer ON min(1) 0.2 - - V DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) - - VDDA – 0.2 V 128/180 DocID17050 Rev 13 VREF+ ≤VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V STM32F21xxx Electrical characteristics Table 67. DAC characteristics (continued) Symbol Min Typ Max Unit DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF - 0.5 - mV DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) - - VREF+ – 1LSB V - 170 240 IVREF+(3) IDDA(3) DNL(3) INL(3) Offset(3) Gain error(3) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode(2) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) It gives the maximum output excursion of the DAC. With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV - Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.5 % Given for the DAC in 12-bit configuration - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Settling time (full scale: for a 10-bit input code transition between the tSETTLING(3) lowest and the highest input codes when DAC_OUT reaches final value ±4LSB THD(3) µA Comments Total Harmonic Distortion Buffer ON DocID17050 Rev 13 129/180 179 Electrical characteristics STM32F21xxx Table 67. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s Wakeup time from off state tWAKEUP(3) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. - –67 –40 dB No RLOAD, CLOAD = 50 pF Update rate(1) PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement) Comments CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1. Guaranteed by design, not tested in production. 2. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 3. Guaranteed by characterization results, not tested in production. Figure 54. 12-bit buffered/non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL 12-bit digital to analog converter DAC_OUTx CL ai17157V2 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly, without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.22 Temperature sensor characteristics Table 68. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 130/180 DocID17050 Rev 13 STM32F21xxx 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 69. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT (1 mV accuracy) 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.24 Embedded reference voltage The parameters given in Table 70 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13. Table 70. Embedded internal reference voltage Symbol VREFINT Parameter Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.24 V - 10 - - µs VDD = 3 V - 3 5 mV Temperature coefficient - - 30 50 ppm/°C Startup time - - 6 10 µs Internal reference voltage ADC sampling time when TS_vrefint(1) reading the internal reference voltage VRERINT_s (2) TCoeff(2) tSTART (2) Internal reference voltage spread over the temperature range 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 6.3.25 FSMC characteristics Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 71 through Table 74 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 1 • DataSetupTime = 1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. DocID17050 Rev 13 131/180 179 Electrical characteristics STM32F21xxx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6  AIC 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max Unit 2THCLK– 0.5 2THCLK+0.5 ns 0.5 2.5 ns 2THCLK- 1 2THCLK+ 0.5 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 4 ns th(A_NOE) Address hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 0.5 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+ 2.5 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2.5 ns - THCLK– 0.5 ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(Data_NE) tw(NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NADV low time 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. 132/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( )60&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )60&B'>@ W Y1$'9B1( )60&B1$'9 WZ1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max Unit 3THCLK 3THCLK+ 4 ns FSMC_NEx low to FSMC_NWE low THCLK– 0.5 THCLK+ 0.5 ns FSMC_NWE low time THCLK– 0.5 THCLK+ 3 ns THCLK - ns - 0 ns THCLK- 3 - ns - 0.5 ns THCLK– 1 - ns FSMC_NE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+ 5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK+ 1.5 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. DocID17050 Rev 13 133/180 179 Electrical characteristics STM32F21xxx Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T H.%?./% &3-#?./% T W./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% TH",?./% &3-#?.",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &3-#? !$;= TSU$ATA?./% !DDRESS T V.!$6?.% TH$ATA?./% $ATA TH!$?.!$6 TW.!$6 &3-#?.!$6 AIB Table 73. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Min Max Unit 3THCLK-1 3THCLK+1 ns FSMC_NEx low to FSMC_NOE low 2THCLK 2THCLK+0.5 ns FSMC_NOE low time THCLK-1 THCLK+1 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 2 ns 1 2.5 ns THCLK– 1.5 THCLK ns FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 2 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+ 3 - ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) Parameter FSMC_NE low time tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) th(AD_NADV) 134/180 FSMC_NADV low time DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 73. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) Symbol Min Max Unit Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Parameter 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( WK%/B1:( )60&B1%/>@ 1%/ W Y$B1( )60&B$'>@ W Y'DWDB1$'9 $GGUHVV W Y1$'9B1( WK'DWDB1:( 'DWD WK$'B1$'9 WZ1$'9 )60&B1$'9 DL% Table 74. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK-1 4THCLK+1 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK- 1 THCLK ns tw(NWE) FSMC_NWE low tim e 2THCLK 2THCLK+1 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK- 1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 2 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns DocID17050 Rev 13 135/180 179 Electrical characteristics STM32F21xxx Table 74. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) (continued) Symbol Parameter Min Max Unit THCLK– 0.5 - ns THCLK- 1 - ns th(A_NWE) Address hold time after FSMC_NWE high th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK+2 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK– 0.5 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms, and Table 76 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. 136/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings %867851  WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\  WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK Table 75. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns DocID17050 Rev 13 137/180 179 Electrical characteristics STM32F21xxx Table 75. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 5 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 60. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, $ATA TD#,+, $ATA TD#,+, !$6 &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG Table 76. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) 138/180 Parameter FSMC_CLK period Min Max Unit 2THCLK- 1 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 7 - ns DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 76. Synchronous multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+( ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIG Table 77. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 2THCLK - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2.5 ns DocID17050 Rev 13 139/180 179 Electrical characteristics STM32F21xxx Table 77. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 4 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 3 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 8 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 62. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIG Table 78. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) td(CLKL-NExL) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 140/180 DocID17050 Rev 13 Min Max Unit 2THCLK- 1 - ns - 1 ns 1 - ns STM32F21xxx Electrical characteristics Table 78. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol Min Max Unit FSMC_CLK low to FSMC_NADV low - 5 ns FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns - 2 ns 2 - ns td(CLKLNADVL) td(CLKLNADVH) td(CLKL-Data) Parameter FSMC_D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, with Table 79 and Table 80 providing the corresponding timings. The results shown in these table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. DocID17050 Rev 13 141/180 179 Electrical characteristics STM32F21xxx Figure 63. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&(B )60&B1&(B WK1&([$, WY1&([$ )60&B$>@ WK1&([15(* WK1&([1,25' WK1&([1,2:5 WG15(*1&([ WG1,25'1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG1&(B12( )60&B12( WZ12( WVX'12( WK12(' )60&B'>@ DLE 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ WK1&(B15(* WK1&(B1,25' WK1&(B1,2:5 WG15(*1&(B WG1,25'1&(B )60&B15(* )60&B1,2:5 )60&B1,25' WG1&(B1:( WZ1:( WG1:(1&(B )60&B1:( )60&B12( 0(0[+,=  WG'1:( WY1:(' WK1:(' )60&B'>@ DLE 142/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&(B WY1&(B$ WK1&(B$, )60&B1&(B +LJK )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* )60&B1:( WG1&(B12( WZ12( WG12(1&(B )60&B12( WVX'12( WK12(' )60&B'>@ DLE 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID17050 Rev 13 143/180 179 Electrical characteristics STM32F21xxx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* WG1&(B1:( WZ1:( )60&B1:( WG1:(1&(B )60&B12( WY1:(' )60&B'>@ DLE 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access )60&B1&(B )60&B1&(B WK1&(B$, WY1&([$ )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,2:5 WZ1,25' WG1,25'1&(B )60&B1,25' WVX'1,25' WG1,25'' )60&B'>@ DL% 144/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&(B )60&B1&(B WY1&([$ WK1&(B$, )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG1&(B1,2:5 WZ1,2:5 )60&B1,2:5 $77[+,=  WY1,2:5' WK1,2:5' )60&B'>@ DLF Table 79. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns - 3.5 ns THCLK+ 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK ns tw(NOE) FSMC_NOE low width td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 8THCLK– 0.5 8THCLK+ 1 ns 5THCLK+ 2.5 - ns tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4 - ns th (N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 2 - ns 8THCLK- 1 8THCLK+ 4 ns 5THCLK+ 1.5 - ns FSMC_NCEx low to FSMC_NWE low - 5HCLK+ 1 ns tv (NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK - ns tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. DocID17050 Rev 13 145/180 179 Electrical characteristics STM32F21xxx Table 80. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK - 0.5 - ns - 5THCLK- 1 ns 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 1 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 0.5 - ns 8THCLK+ 1 - ns 9.5 - ns 0 - ns tw(NIORD) FSMC_NIORD low width tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, together with Table 81 and Table 82 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. 146/180 DocID17050 Rev 13 STM32F21xxx Electrical characteristics Figure 69. NAND controller waveforms for read access &3-#?.#%X !,%&3-#?! #,%&3-#?! &3-#?.7% TD!,% ./% TH./% !,% &3-#?./%.2% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 70. NAND controller waveforms for write access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(1:( WK1:($/( )60&B1:( )60&B12(15( WY1:(' WK1:(' )60&B'>@ AIC DocID17050 Rev 13 147/180 179 Electrical characteristics STM32F21xxx Figure 71. NAND controller waveforms for common memory read access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(12( WK12($/( )60&B1:( WZ12( )60&B12( WVX'12( WK12(' )60&B'>@ DLF Figure 72. NAND controller waveforms for common memory write access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(12( WZ1:( WK12($/( )60&B1:( )60&B12( WG'1:( WY1:(' WK1:(' )60&B'>@ DLF Table 81. Switching characteristics for NAND Flash read cycles(1)(2) Symbol tw(N0E) Parameter FSMC_NOE low width Max Unit 4THCLK- 1 4THCLK+ 2 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 9 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 3 - ns - 3THCLK ns 3THCLK+ 2 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. 148/180 Min DocID17050 Rev 13 STM32F21xxx Electrical characteristics Table 82. Switching characteristics for NAND Flash write cycles(1)(2) Symbol Parameter tw(NWE) FSMC_NWE low width Min Max Unit 4THCLK- 1 4THCLK+ 3 ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK - ns - 3THCLK+ 2 ns 3THCLK- 2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. 6.3.26 Camera interface (DCMI) timing specifications Table 83. DCMI characteristics Symbol - 6.3.27 Parameter Conditions Frequency ratio DCMI_PIXCLK/fHCLK DCMI_PIXCLK= 48 MHz Min Max - 0.4 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 84 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 13. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 73. SDIO high-speed mode TF TR T# T7#+( T7#+, #+ T/6 T/( $#-$ OUTPUT T)35 T)( $#-$ INPUT AI DocID17050 Rev 13 149/180 179 Electrical characteristics STM32F21xxx Figure 74. SD default mode #+ T/6$ T/($ $#-$ OUTPUT AI Table 84. SD/MMC characteristics Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 - tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 - tr Clock rise time CL ≤ 30 pF - 3.5 tf Clock fall time CL ≤ 30 pF - 5 ns CMD, D inputs (referenced to CK) tISU Input setup time CL ≤ 30 pF 2 - tIH Input hold time CL ≤ 30 pF 0 - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL ≤ 30 pF - 6 tOH Output hold time CL ≤ 30 pF 0.3 - ns CMD, D outputs (referenced to CK) in SD default mode(1) tOVD Output valid default time CL ≤ 30 pF - 7 tOHD Output hold default time CL ≤ 30 pF 0.5 - ns 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. 6.3.28 RTC characteristics Table 85. RTC characteristics 150/180 Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - DocID17050 Rev 13 STM32F21xxx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP64 package information Figure 75. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / /      3,1 ,'(17,),&$7,21 ( ( E ( 7.1    H :B0(B9 1. Drawing is not to scale. Table 86. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 DocID17050 Rev 13 151/180 179 Package information STM32F21xxx Table 86. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 76. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint                 AIC 1. Dimensions are expressed in millimeters. 152/180 DocID17050 Rev 13 STM32F21xxx LQFP100 package information Figure 77. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! 3%!4).'0,!.% # ! '!5'%0,!.% $ ! + CCC # , $ , $       0).  )$%.4)&)#!4)/. % % % B 7.2 Package information  E ,?-%?6 1. Drawing is not to scale. Table 87. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DocID17050 Rev 13 153/180 179 Package information STM32F21xxx Table 87. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 78. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint                AIC 1. Dimensions are expressed in millimeters. 154/180 DocID17050 Rev 13 STM32F21xxx Package information Device marking Figure 79 gives an example of topside marking orientation versus Pin 1 identifier location. Figure 79. LQFP100 marking (package top view) 3URGXFWLGHQWLILFDWLRQ 670) 9*7; 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID17050 Rev 13 155/180 179 Package information 7.3 STM32F21xxx LQFP144 package information Figure 80. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*(3/$1( ' / ' . $ FFF & / '    (   3,1 ( ( E    ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. 156/180 DocID17050 Rev 13 STM32F21xxx Package information Table 88. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID17050 Rev 13 157/180 179 Package information STM32F21xxx Figure 81. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint                 DLH 1. Dimensions are expressed in millimeters. 158/180 DocID17050 Rev 13 STM32F21xxx Package information Device marking Figure 82 gives an example of topside marking orientation versus Pin 1 identifier location. Figure 82. LQFP144 marking (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ ; 670)=*7 'DWHFRGH < :: 3LQLGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID17050 Rev 13 159/180 179 Package information 7.4 STM32F21xxx LQFP176 package information Figure 83. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline C ! ! ! # 3EATINGPLANE MM GAUGEPLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 89. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data Dimensions Symbol 160/180 inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 DocID17050 Rev 13 STM32F21xxx Package information Table 89. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data (continued) Dimensions Symbol inches(1) millimeters Min Typ Max Min Typ Max HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 7° 0° - 7° ccc - - 0.080 - - 0.0031 (2) L 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. DocID17050 Rev 13 161/180 179 Package information STM32F21xxx Figure 84. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint                 4?&0?6 1. Dimensions are expressed in millimeters. 162/180 DocID17050 Rev 13 STM32F21xxx 7.5 Package information UFBGA176+25 package information Figure 85. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline & ^ĞĂƚŝŶŐƉůĂŶĞ ϰ ĚĚĚ  Ϯ $ ϭ ď Ğ  $EDOO LGHQWLILHU ( $EDOO LQGH[ DUHD $     '  Ğ  Z ϭϱ ϭ KddKDs/t ‘EEDOOV dKWs/t ‘ HHH 0 & $  ‘ III 0 & $(B0(B9 1. Drawing is not to scale. Table 90. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.450 - - 0.0177 - A3 - 0.130 - - 0.0051 0.0094 A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.100 - - 0.3583 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - Z - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 DocID17050 Rev 13 163/180 179 Package information STM32F21xxx Table 90. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 86. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint 'SDG 'VP Ϭϳͺ&Wͺsϭ Table 91. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension 164/180 Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID17050 Rev 13 STM32F21xxx Package information Device marking Figure 87. UFBGA176+25 marking (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ 670 ),*+ 'DWHFRGH %DOO$ LGHQWLILHU 069 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID17050 Rev 13 165/180 179 Package information 7.6 STM32F21xxx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 92. Package thermal characteristics Symbol ΘJA Parameter Value Thermal resistance junction-ambient LQFP 64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.5 mm pitch 39 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 166/180 DocID17050 Rev 13 STM32F21xxx 8 Ordering information Ordering information Table 93. Ordering information scheme Example: STM32 F 215 R E T 6 V xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 215 = STM32F21x, connectivity, cryptographic acceleration 217= STM32F21x, connectivity, camera interface, cryptographic acceleration, Ethernet Pin count R = 64 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Software option Internal code or Blank Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact your nearest ST sales office. DocID17050 Rev 13 167/180 179 Revision history 9 STM32F21xxx Revision history Table 94. Document revision history Date Revision 02-Feb-2010 1 Initial release. 2 Updated datasheet status to PRELIMINARY DATA. Renamed high-speed SRAM, system SRAM. Added UFBGA176 package, and note 1 related to LQFP176 package in Table 2, Figure 12, and Table 93. Added information on ART accelerator and audio PLL (PLLI2S). Added Table 5: USART feature comparison. Several updates on Table 7: STM32F21x pin and ball definitions and Table 9: Alternate function mapping. ADC, DAC, oscillator, RTC_AF, WKUP and VBUS signals removed from alternate functions and moved to the “other functions” column in Table 7: STM32F21x pin and ball definitions. TRACESWO added in Figure 4: STM32F21x block diagram, Table 7: STM32F21x pin and ball definitions, and Table 9: Alternate function mapping. XTAL oscillator frequency updated on cover page, in Figure 4: STM32F21x block diagram and in Section 3.11: External interrupt/event controller (EXTI). Updated list of peripherals used for boot mode in Section 3.13: Boot modes. Added Regulator bypass mode in Section 3.16: Voltage regulator, and Section 6.3.4: Operating conditions at power-up / power-down (regulator OFF). Updated Section 3.17: Real-time clock (RTC), backup SRAM and backup registers. Added Note Note: in Section 3.18: Low-power modes. Added SPI TI protocol in Section 3.23: Serial peripheral interface (SPI). Updated Section 3.28: Universal serial bus on-the-go full-speed (OTG_FS), and Section 3.29: Universal serial bus on-the-go high-speed (OTG_HS). Added Section 6: Electrical characteristics, and Section 7.6: Thermal characteristics. Updated Table 89: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data and Figure 83: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline. Added Table 93: Main applications versus package for STM32F2xxx microcontrollers in A.1: Main applications versus package. Updated figures in Appendix A.2: USB OTG full speed (FS) interface solutions and A.3: USB OTG high speed (HS) interface solutions. Updated Figure 94: Audio player solution using PLL, PLLI2S, USB and 1 crystal and Figure 95: Audio PLL (PLLI2S) providing accurate I2S clock. Added random number generation feature. Added trademark for ART accelerator and updated Section 3.2: Adaptive real-time memory accelerator (ART Accelerator™). 13-Jul-2010 168/180 Changes DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date 25-Nov-2010 Revision Changes 3 Added WLCSP66 (64+2) package. Added note 1 related to LQFP176 on cover page. Update I/Os in Section : Features. Updated Table 5: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 3.15: Power supply supervisor. Reworked Section 3.16: Voltage regulator to clarify regulator off modes. Added Section 3.19: VBAT operation. Modified VDD_3 pin in Table 7: STM32F21x pin and ball definitions, and added note related to the FSMC_NL pin. Renamed BYPASS-REG REGOFF, and add IRROFF pin. Changed VSS_SA to VSS, and VDD_SA pin reserved for future use. Updated maximum HSE crystal frequency to 26 MHz. USART4/5 renamed UART4/5. USART4 pins renamed UART4 in Table 7: STM32F21x pin and ball definitions. Updated LIN and IrDA features for UART4/5 in Table 5: USART feature comparison. Section 6.2: Absolute maximum ratings: Updated VIN minimum and maximum values and note for non-five-volt tolerant pins in Table 10: Voltage characteristics. Updated IINJ(PIN) maximum values and related notes in Table 11: Current characteristics. Updated VDDA minimum value in Table 13: General operating conditions. Added Note 2 and updated Maximum CPU frequency in Table 14: Limitations depending on the operating power supply range; and added Figure 19: Number of wait states versus fCPU and VDD range. Renamed Brownout Low, medium and High reset thresholds, Renamed VBORL/VBORM/VBORH, VBOR1/VBOR2/VBOR3 in Table 18: Embedded reset and power control block characteristics. Changed fLSI typical value in Table 32: LSI oscillator characteristics. Added Figure 33: ACCLSI versus temperature. Changed fOSC_IN maximum value in Table 29: HSE 4-26 MHz oscillator characteristics. Changed fPLL_IN maximum value in Table 33: Main PLL characteristics, and updated jitter parameters in Table 34: PLLI2S (audio PLL) characteristics. Section 6.3.16: I/O port characteristics: updated VIH and VIL in Table 45: I/O static characteristics. Added Note 1 below Table 46: Output voltage characteristics. Updated RPD and RPU parameter description in Table 56: USB OTG FS DC electrical characteristics. Updated VREF+ minimum value in Table 65: ADC characteristics. Updated Table 70: Embedded internal reference voltage. Removed Ethernet and USB2 for 64-pin devices in Table 93: Main applications versus package for STM32F2xxx microcontrollers. Added A.2: USB OTG full speed (FS) interface solutions, removed “OTG FS connection with external PHY” figure, updated Figure 85, Figure 86, and Figure 87 to add STULPI01B. DocID17050 Rev 13 169/180 179 Revision history STM32F21xxx Table 94. Document revision history (continued) Date 22-Apr-2011 170/180 Revision Changes 4 Changed datasheet status to “Full Datasheet”. APB1 frequency changed form 36 MHz to 30 MHz. Introduced concept of SRAM1 and SRAM2. LQFP176 now in production. Removed WLCSP64+2 package. Updated Figure 3: Compatible board design between STM32F10x and STM32F2xx for LQFP144 package and Figure 2: Compatible board design between STM32F10x and STM32F2xx for LQFP100 package. Added camera interface for STM32F217Vx devices in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Removed 16 MHz internal RC oscillator accuracy in Section 3.12: Clocks and startup. Updated Section 3.16: Voltage regulator. Modified I2S sampling frequency range in Section 3.12: Clocks and startup, Section 3.24: Inter-integrated sound (I2S), and Section 3.30: Audio PLL (PLLI2S). Updated Section 3.17: Real-time clock (RTC), backup SRAM and backup registers and description of TIM2 and TIM5 in Section 3.20.2: General-purpose timers (TIMx). Modified maximum baud rate (oversampling by 16) for USART1 in Table 5: USART feature comparison. Updated note related to RFU pin below Figure 10: STM32F21x LQFP100 pinout, Figure 11: STM32F21x LQFP144 pinout, Figure 12: STM32F21x LQFP176 pinout, Figure 13: STM32F21x UFBGA176 ballout, and Table 7: STM32F21x pin and ball definitions. Added RTC_50Hz as PB15 alternate function, and TT (3.6 V tolerant I/O) in Table 7: STM32F21x pin and ball definitions and Table 9: Alternate function mapping. PA15 added in Table 7: STM32F21x pin and ball definitions. In Table 7: STM32F21x pin and ball definitions, changed I2S2_CK and I2S3_CK to I2S2_SCK and I2S3_SCK, respectively. Removed ETH _RMII_TX_CLK for PC3/AF11 in Table 9: Alternate function mapping. Updated Table 10: Voltage characteristics and Table 11: Current characteristics. TSTG updated to –65 to +150 in Table 12: Thermal characteristics. Added CEXT and ESR in Table 13: General operating conditions as well as Section 6.3.2: VCAP1/VCAP2 external capacitor. Modified Note 3 in Table 14: Limitations depending on the operating power supply range. Updated Table 16: Operating conditions at power-up / power-down (regulator ON), and Table 17: Operating conditions at power-up / powerdown (regulator OFF). Updated notes below and added OSC_OUT pin in Figure 15: Pin loading conditions. and Figure 16: Pin input voltage. Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and IRUSH, added ERUSH and Note 2 in Table 18: Embedded reset and power control block characteristics. DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date 22-Apr-2011 Revision Changes Updated Typical and maximum current consumption conditions, as well as Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 19: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure 21, Figure 22, Figure 23, and Figure 24. Updated Table 21: Typical and maximum current consumption in Sleep mode, and added Figure 25 and Figure 26. Updated Table 23: Typical and maximum current consumptions in Standby mode and Table 24: Typical and maximum current consumptions in VBAT mode. Updated Table 22: Typical and maximum current consumptions in Stop mode. Added Figure 27: Typical current consumption vs. temperature in Stop mode. Updated Table 23: Typical and maximum current consumptions in Standby mode and Table 24: Typical and maximum current consumptions in VBAT mode. Updated On-chip peripheral current consumption conditions and Table 25: Peripheral current consumption. Updated tWUSTDBY and tWUSTOP, and added Note 3 in Table 26: Lowpower mode wakeup timings. Maximum fHSE_ext and minimum tw(HSE) values updated in Table 27: High-speed external user clock characteristics. Updated C and gm in Table 29: HSE 4-26 MHz oscillator characteristics. 4 Updated RF, I2, gm, and tsu(LSE) in Table 30: LSE oscillator (continued) characteristics (fLSE = 32.768 kHz). Added Note 3 and updated ACCHSI, IDD(HSI) and tsu(HSI) in Table 31: HSI oscillator characteristics. Added Figure 32: ACCHSI versus temperature Updated fLSI, tsu(LSI) and IDD(LSI) in Table 32: LSI oscillator characteristics. Table 33: Main PLL characteristics: removed note 1, updated tLOCK, jitter, IDD(PLL) and IDDA(PLL), added Note 2 for fPLL_IN minimum and maximum values. Table 34: PLLI2S (audio PLL) characteristics: removed note 1, updated tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S), added Note 2 for fPLLI2S_IN minimum and maximum values. Added Note 1 in Table 35: SSCG parameters constraint. Updated Table 36: Flash memory characteristics. Modified Table 37: Flash memory programming and added Note 1 for tprog. Updated tprog and added Note 1 in Table 38: Flash memory programming with VPP. Modified Figure 38: Recommended NRST pin protection. Updated Table 41: EMI characteristics and EMI monitoring conditions in Section : Electromagnetic Interference (EMI). Added Note 2 related to VESD(HBM)in Table 42: ESD absolute maximum ratings. Added Section 6.3.15: I/O current injection characteristics. Updated Table 45: I/O static characteristics. Modified maximum frequency values and conditions in Table 47: I/O AC characteristics. DocID17050 Rev 13 171/180 179 Revision history STM32F21xxx Table 94. Document revision history (continued) Date 22-Apr-2011 172/180 Revision Changes Updated tres(TIM) in Table 49: Characteristics of TIMx connected to the APB1 domain. Modified tres(TIM) and fEXT Table 50: Characteristics of TIMx connected to the APB2 domain. Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 51: I2C characteristics and Figure 39: I2C bus AC waveforms and measurement circuit. Added Table 56: USB OTG FS DC electrical characteristics and updated Table 57: USB OTG FS electrical characteristics. Updated VDD minimum value in Table 61: Ethernet DC electrical characteristics. Updated Table 65: ADC characteristics and RAIN equation. Updated RAIN equation. Updated Table 67: DAC characteristics. Updated tSTART in Table 68: Temperature sensor characteristics. Updated Table 70: Embedded internal reference voltage. Modified FSMC_NOE waveform in Figure 55: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKLAIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-NWEH), and updated data latency from 1 to 0 in Figure 59: Synchronous 4 (continued) multiplexed NOR/PSRAM read timings, Figure 60: Synchronous multiplexed PSRAM write timings, Figure 61: Synchronous nonmultiplexed NOR/PSRAM read timings, and Figure 62: Synchronous non-multiplexed PSRAM write timings, Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV), td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and modified tw(CLK) minimum value in Table 75, Table 76, Table 77, and Table 78. Updated R typical value in Table 69: VBAT monitoring characteristics.Updated note 2 in Table 71, Table 72, Table 73, Table 74, Table 75, Table 76, Table 77, and Table 78. Modified th(NIOWR-D) in Figure 68: PC Card/CompactFlash controller waveforms for I/O space write access. Modified FSMC_NCEx signal in Figure 69: NAND controller waveforms for read access, Figure 70: NAND controller waveforms for write access, Figure 71: NAND controller waveforms for common memory read access, and Figure 72: NAND controller waveforms for common memory write access. Specified Full speed (FS) mode for Figure 86: USB OTG HS peripheralonly connection in FS mode and Figure 87: USB OTG HS host-only connection in FS mode. DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date 14-Jun-2011 Revision 5 Changes Added SDIO in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Updated VIN for 5V tolerant pins in Table 10: Voltage characteristics. Updated jitter parameters description in Table 33: Main PLL characteristics. Remove jitter values for system clock in Table 34: PLLI2S (audio PLL) characteristics. Updated Table 41: EMI characteristics. Update Note 2 in Table 51: I2C characteristics. Updated Avg_Slope typical value and TS_temp minimum value in Table 68: Temperature sensor characteristics. Updated TS_vbat minimum value in Table 69: VBAT monitoring characteristics. Updated TS_vrefint minimum value in Table 70: Embedded internal reference voltage. Added Software option in Section 8: Ordering information. In Table 93: Main applications versus package for STM32F2xxx microcontrollers, renamed USB1 and USB2, USB OTG FS and USB OTG HS, respectively; and removed USB OTG FS and camera interface for 64-pin package; added USB OTG HS on 64-pin package; and added Note 1 and Note 2. Updated disclaimer on cover page. DocID17050 Rev 13 173/180 179 Revision history STM32F21xxx Table 94. Document revision history (continued) Date 20-Dec-2011 174/180 Revision Changes 6 Updated SDIO register addresses in Figure 14: Memory map. Updated Figure 3: Compatible board design between STM32F10x and STM32F2xx for LQFP144 package, Figure 2: Compatible board design between STM32F10x and STM32F2xx for LQFP100 package, Figure 1: Compatible board design between STM32F10x and STM32F2xx for LQFP64 package, and added Figure 4: Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Section 3.3: Memory protection unit. Updated Section 3.6: Embedded SRAM. Updated Section 3.28: Universal serial bus on-the-go full-speed (OTG_FS) to remove external FS OTG PHY support. In Table 7: STM32F21x pin and ball definitions: changed SPI2_MCK and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added ETH _RMII_TX_EN alternate function to PG11. Added EVENTOUT in the list of alternate functions for I/O pin/balls. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. In Table 9: Alternate function mapping: changed I2S3_SCK to I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. Updated peripherals corresponding to AF12. Removed CEXT and ESR from Table 13: General operating conditions. Added maximum power consumption at TA=25 °C in Table 22: Typical and maximum current consumptions in Stop mode. Added CRYPTO, RNG, and HASH consumption in Table 25: Peripheral current consumption. Updated md minimum value in Table 35: SSCG parameters constraint. Added examples in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 53: SPI characteristics and Table 54: I2S characteristics. Updated Figure 46: ULPI timing diagram and Table 60: ULPI timing. Updated Table 62: Dynamics characteristics: Ethernet MAC signals for SMI, Table 63: Dynamics characteristics: Ethernet MAC signals for RMII, and Table 64: Dynamics characteristics: Ethernet MAC signals for MII. Updated maximum fS values in Table 65: ADC characteristics. Section 6.3.25: FSMC characteristics: updated Table 71 toTable 82, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 60: Synchronous multiplexed PSRAM write timings. UpdatedTable 83: DCMI characteristics. Updated Table 90: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date Revision Changes Appendix A.2: USB OTG full speed (FS) interface solutions: updated Figure 85: USB OTG FS (full speed) host-only connection and added Note 2, updated Figure 86: OTG FS (full speed) connection dual-role with internal PHY and added Note 3 and Note 4, modified Figure 87: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY and added Note 2. 6 Appendix A.3: USB OTG high speed (HS) interface solutions: 20-Dec-2011 (continued) removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, updated Figure 87: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY. Added Appendix A.4: Ethernet interface solutions. Updated disclaimer on last page. DocID17050 Rev 13 175/180 179 Revision history STM32F21xxx Table 94. Document revision history (continued) Date 24-Apr-2012 176/180 Revision Changes 7 Updated number of USB OTG HS and FS, added Note 1 related to FSMC and Note 3 related to SPI/I2S in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Added Note 2 and update TIM5 in Figure 4: STM32F21x block diagram. Updated maximum number of maskable interrupts in Section 3.10: Nested vectored interrupt controller (NVIC). Removed STM32F215xx in Section 3.28: Universal serial bus on-the-go full-speed (OTG_FS). Removed support of I2C for OTG PHY in Section 3.29: Universal serial bus on-the-go high-speed (OTG_HS). Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7: STM32F21x pin and ball definitions and Table 9: Alternate function mapping. PH10 alternate function TIM5_CH1_ETR renamed TIM5_CH1. Added Table 8: FSMC pin definition. Updated VPOR/PDR in Table 18: Embedded reset and power control block characteristics. Updated VDDA and VREF+ decoupling capacitor in Figure 17: Power supply scheme. Updated typical values in Table 23: Typical and maximum current consumptions in Standby mode and Table 24: Typical and maximum current consumptions in VBAT mode. Updated Table 29: HSE 4-26 MHz oscillator characteristics and Table 30: LSE oscillator characteristics (fLSE = 32.768 kHz). Updated Table 36: Flash memory characteristics, Table 37: Flash memory programming, and Table 38: Flash memory programming with VPP. Updated Section : Output driving current. Updated Note 3 and removed note related to minimum hold time value in Table 51: I2C characteristics. Updated Table 63: Dynamics characteristics: Ethernet MAC signals for RMII. Updated CADC, IVREF+, and IVDDA in Table 65: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 66: ADC accuracy. Updated Figure 85: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. Appendix A.1: Main applications versus package: removed number of address lines for FSMC/NAND in Table 93: Main applications versus package for STM32F2xxx microcontrollers. Appendix A.4: Ethernet interface solutions: updated Figure 92: Complete audio player solution 1 and Figure 93: Complete audio player solution 2. DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date 29-Oct-2012 Revision Changes 8 Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated number of AHB buses in Section 2: Description and Section 3.12: Clocks and startup. Updated Note 2 below Figure 4: STM32F21x block diagram. Changed System memory to System memory + OTP in Figure 14: Memory map. Added Note 1 below Table 15: VCAP1/VCAP2 operating conditions. Updated VDDA and VREF+ decoupling capacitor in Figure 17: Power supply scheme and updated Note 3. Changed simplex mode into half-duplex mode in Section 3.24: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively. Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and PA5 in Table 9: Alternate function mapping. Updated note applying to IDD (external clock and all peripheral disabled) in Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled). Updated Note 3 below Table 21: Typical and maximum current consumption in Sleep mode. Removed fHSE_ext typical value in Table 27: High-speed external user clock characteristics. Updated master I2S clock jitter conditions and values in Table 34: PLLI2S (audio PLL) characteristics. Updated equations in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Swapped TTL and CMOS port conditions for VOL and VOH in Table 46: Output voltage characteristics. Updated VIL(NRST) and VIH(NRST) in Table 48: NRST pin characteristics. Updated Table 53: SPI characteristics and Table 54: I2S characteristics.Removed note 1 related to measurement points below Figure 41: SPI timing diagram - slave mode and CPHA = 1, Figure 42: SPI timing diagram - master mode, and Figure 43: I2S slave timing diagram (Philips protocol)(1). Updated tHC in Table 60: ULPI timing. Updated Figure 47: Ethernet SMI timing diagram, Table 62: Dynamics characteristics: Ethernet MAC signals for SMI and Table 63: Dynamics characteristics: Ethernet MAC signals for RMII. Update fTRIG in Table 65: ADC characteristics. Updated IDDA description in Table 67: DAC characteristics. Updated note below Figure 52: Power supply and reference decoupling (VREF+ not connected to VDDA) and Figure 53: Power supply and reference decoupling (VREF+ connected to VDDA). Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 75: Synchronous multiplexed NOR/PSRAM read timings, Table 77: Synchronous nonmultiplexed NOR/PSRAM read timings, Figure 59: Synchronous multiplexed NOR/PSRAM read timings and Figure 61: Synchronous non-multiplexed NOR/PSRAM read timings. DocID17050 Rev 13 177/180 179 Revision history STM32F21xxx Table 94. Document revision history (continued) Date 29-Oct-2012 04-Nov-2013 178/180 Revision Changes Added Figure 84: LQFP176 recommended footprint. Added Note 2 below Figure 86: Regulator OFF/internal reset ON. 8 (continued) Updated device subfamily in Table 93: Ordering information scheme. Remove reference to note 2 for USB IOTG FS in Table 93: Main applications versus package for STM32F2xxx microcontrollers. 9 Updated Section 3.14: Power supply schemes, Section 3.15: Power supply supervisor, Section 3.16.1: Regulator ON and Section 3.16.2: Regulator OFF. Added Section 3.16.3: Regulator ON/OFF and internal reset ON/OFF availability. Restructured RTC features and added reference clock detection in Section 3.17: Real-time clock (RTC), backup SRAM and backup registers. Added note indicating the package view below Figure 9: STM32F21x LQFP64 pinout, Figure 10: STM32F21x LQFP100 pinout, Figure 11: STM32F21x LQFP144 pinout, and Figure 12: STM32F21x LQFP176 pinout. Added Table 6: Legend/abbreviations used in the pinout table. Table 7: STM32F21x pin and ball definitions: content reformatted, removed indexes on VSS and VDD, updated PA4, PA5, PA6, PC4, BOOT0; replaced DCMI_12 by DCMI_D12, ETH_MII_RX_D0 by ETH_MII_RXD0, ETH_MII_RX_D1 by ETH_MII_RXD1, ETH_RMII_RX_D0 by ETH_RMII_RXD0, and ETH_RMII_RX_D1 by ETH_RMII_RXD1 in . Table 9: Alternate function mapping: replaced FSMC_BLN1 by FSMC_NBL1, added EVENTOUT as AF15 alternated function for PC13, PC14, PC15, PH0, PH1, and PI8. Updated Figure 15: Pin loading conditions and Figure 16: Pin input voltage. Added VIN in Table 13: General operating conditions. Removed note applying to VPOR/PDR minimum value in Table 18: Embedded reset and power control block characteristics. Updated notes related to CL1 and CL2 in Section : Low-speed external clock generated from a crystal/ceramic resonator. Updated conditions in Table 40: EMS characteristics. Updated Table 41: EMI characteristics. Updated VIL, VIH and VHys in Table 45: I/O static characteristics. Added Section : Output driving current and updated Figure 37: I/O AC characteristics definition. Updated VIL(NRST) and VIH(NRST) in Table 48: NRST pin characteristics, updated Figure 37: I/O AC characteristics definition. Removed tests conditions in Section : I2C interface characteristics. Updated Table 51: I2C characteristics and Figure 39: I2C bus AC waveforms and measurement circuit. Updated IVREF+ and IVDDA in Table 65: ADC characteristics. Updated Offset comments in Table 67: DAC characteristics. Updated minimum th(CLKH-DV) value in Table 77: Synchronous nonmultiplexed NOR/PSRAM read timings. DocID17050 Rev 13 STM32F21xxx Revision history Table 94. Document revision history (continued) Date Revision Changes Updated Figure 75: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 86: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. Updated Figure 77: LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline, Figure 80: LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline, 9 Figure 83: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, 04-Nov-2013 (continued) package outline. Updated Figure 85: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline and Figure 85: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. Removed Appendix A Application block diagrams. 10 Updated VBAT voltage range in Figure 17: Power supply scheme. Added caution note in Section 6.1.6: Power supply scheme. Updated VIN in Table 13: General operating conditions. Removed note 1 in Table 22: Typical and maximum current consumptions in Stop mode. Updated Table 44: I/O current injection susceptibility, Section 6.3.16: I/O port characteristics and Section 6.3.17: NRST pin characteristics. Removed note 3 in Table 68: Temperature sensor characteristics. Added Figure 79: LQFP100 marking (package top view) and Figure 82: LQFP144 marking (package top view). 11 Updated Section 1: Introduction. Updated Table 31: HSI oscillator characteristics and its footnotes. Updated Figure 34: PLL output clock waveforms in center spread mode, Figure 35: PLL output clock waveforms in down spread mode, Figure 52: Power supply and reference decoupling (VREF+ not connected to VDDA) and Figure 53: Power supply and reference decoupling (VREF+ connected to VDDA). Updated Section 7: Package information and its subsections. 07-Jul-2016 12 Updated Features and Section 2: Description. Updated figures 1, 2 and 3 in Section 2.1: Full compatibility throughout the family. Updated Device marking and Figure 79 in Section 7.2: LQFP100 package information. Updated Device marking and Figure 82 in Section 7.3: LQFP144 package information. Updated Section 7.5: UFBGA176+25 package information with introduction of Device marking and Figure 87. Updated Table 93: Ordering information scheme. 16-Aug-2016 13 Updated Figure 52: Power supply and reference decoupling (VREF+ not connected to VDDA). Updated title of Section 8: Ordering information. 27-Oct-2014 23-Feb-2016 DocID17050 Rev 13 179/180 179 STM32F21xxx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 180/180 DocID17050 Rev 13