STM32F303xB STM32F303xC
ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+
48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V
Datasheet - production data
Features
• Core: ARM® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP
instruction and MPU (memory protection unit)
• Operating conditions:
– VDD, VDDA voltage range: 2.0 V to 3.6 V
• Memories
– 128 to 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM, with HW parity
check implemented on the first 16 Kbytes.
– Routine booster: 8 Kbytes of SRAM on
instruction and data bus, with HW parity
check (CCM)
• CRC calculation unit
• Reset and supply management
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and Standby
– VBAT supply for RTC and backup registers
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
– Internal 40 kHz oscillator
• Up to 87 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
• Interconnect matrix
• 12-channel DMA controller
• Four ADCs 0.20 µS (up to 39 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, single
ended/differential input, separate analog supply
from 2 to 3.6 V
• Two 12-bit DAC channels with analog supply
from 2.4 to 3.6 V
• Seven fast rail-to-rail analog comparators with
analog supply from 2 to 3.6 V
• Four operational amplifiers that can be used in
PGA mode, all terminals accessible with analog
supply from 2.4 to 3.6 V
• Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
May 2016
This is information on a product in full production.
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
WLCSP100 (0.4 mm pitch)
• Up to 13 timers
– One 32-bit timer and two 16-bit timers with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– Two 16-bit 6-channel advanced-control
timers, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
• Calendar RTC with Alarm, periodic wakeup
from Stop/Standby
• Communication interfaces
– CAN interface (2.0B Active)
– Two I2C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus, wakeup
from STOP
– Up to five USART/UARTs (ISO 7816
interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed
half/full duplex I2S interface, 4 to 16
programmable bit frames
– USB 2.0 full speed interface
– Infrared transmitter
• Serial wire debug, Cortex®-M4 with FPU ETM,
JTAG
• 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32F303xB
STM32F303CB, STM32F303RB, STM32F303VB
STM32F303xC
STM32F303CC, STM32F303RC, STM32F303VC
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Contents
STM32F303xB STM32F303xC
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . 13
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.2
Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12.1
3.13
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13.4
OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16
Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17.1
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Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3.17.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 23
3.17.3
Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24
3.19
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.20
Universal synchronous/asynchronous receiver transmitter (USART) . . . 26
3.21
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 26
3.22
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 27
3.23
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.24
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.25
Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.26
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.27
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27.2
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 60
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STM32F303xB STM32F303xC
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.16
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.18
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.20
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.21
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1
LQFP100 – 14 x 14 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.2
LQFP64 – 10 x 10 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.3
LQFP48 – 7 x 7 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4
WLCSP100 - 0.4 mm pitch wafer level chip scale package information 134
7.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.5.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.5.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 139
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 11
External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 16
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F303xB/STM32F303xC I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F303xB/STM32F303xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 29
No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices . 29
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32F303xB/STM32F303xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 53
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 63
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 64
Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 65
Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 65
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 66
Typical current consumption in Run mode, code with data processing running from Flash 67
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 68
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
6/148
STM32F303xB STM32F303xC
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 94
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ADC accuracy - limited test conditions, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . 108
ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 125
LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 128
LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 131
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 136
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DocID023353 Rev 13
STM32F303xB STM32F303xC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F303xB/STM32F303xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F303xB/STM32F303xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F303xB/STM32F303xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F303xB/STM32F303xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32F303xB/STM32F303xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 66
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 80
TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 88
Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 88
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . 120
OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 125
LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 126
LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 127
LQFP64 – 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 128
LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 129
LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 130
LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 131
LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 132
LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 133
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
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8
List of figures
Figure 49.
Figure 50.
8/148
STM32F303xB STM32F303xC
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
WLCSP100, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
DocID023353 Rev 13
STM32F303xB STM32F303xC
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F303xB/STM32F303xC microcontrollers.
This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the
STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The
reference manual is available from the STMicroelectronics website www.st.com.
For information on the Cortex®-M4 core with FPU, please refer to:
•
Cortex®-M4 with FPU Technical Reference Manual, available from ARM website
www.arm.com.
•
STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214)
available from our website www.st.com.
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54
Description
2
STM32F303xB STM32F303xC
Description
The STM32F303xB/STM32F303xC family is based on the high-performance
ARM® Cortex®-M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz,
and embedding a floating point unit (FPU), a memory protection unit (MPU) and an
embedded trace macrocell (ETM). The family incorporates high-speed embedded
memories (up to 256 Kbytes of Flash memory, up to 40 Kbytes of SRAM) and an extensive
range of enhanced I/Os and peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational
amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit
timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They
also feature standard and advanced communication interfaces: up to two I2Cs, up to three
SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN
and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an
external PLL.
The STM32F303xB/STM32F303xC family operates in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F303xB/STM32F303xC family offers devices in four packages ranging from
48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
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STM32F303xB STM32F303xC
Description
Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts
Peripheral
STM32F303Cx
STM32F303Rx
STM32F303Vx
Flash (Kbytes)
128
256
128
256
128
256
SRAM (Kbytes) on data bus
32
40
32
40
32
40
CCM (Core Coupled Memory)
RAM (Kbytes)
Timers
8
Advanced
control
2 (16-bit)
General purpose
5 (16-bit)
1 (32-bit)
Basic
2 (16-bit)
PWM channels (all) (1)
31
33
PWM channels (except
complementary)
22
24
SPI (I2S)(2)
I
Communication USART
interfaces
UART
GPIOs
3(2)
2C
2
3
0
2
CAN
1
USB
1
Normal I/Os
(TC, TTa)
20
27
45 in LQFP100
37 in WLCSP100
5-volt tolerant
I/Os (FT, FTf)
17
25
42 in LQFP100
40 in WLCSP100
DMA channels
Capacitive sensing channels
12
17
15
22
12-bit DAC channels
2
Analog comparator
7
Operational amplifiers
4
CPU frequency
Packages
39 in LQFP100
32 in WLCSP100
72 MHz
Operating voltage
Operating temperature
24
4
12-bit ADCs
Number of channels
18
2.0 to 3.6 V
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
LQFP48
LQFP64
LQFP100
WLCSP100
1. This total number considers also the PWMs generated on the complementary output channels
2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
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54
Description
STM32F303xB STM32F303xC
Figure 1. STM32F303xB/STM32F303xC block diagram
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STM32F303xB STM32F303xC
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash and
SRAM
The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F303xB/STM32F303xC family is compatible with
all ARM tools and software.
Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family
devices.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3
Embedded Flash memory
All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash
memory available for storing programs and data. The Flash memory access time is adjusted
to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz
and 2 wait states above).
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54
Functional overview
3.4
STM32F303xB STM32F303xC
Embedded SRAM
STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with
hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running
code from the CCM (Core Coupled Memory) RAM).
•
8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute
critical routines or to access data (parity check on all of CCM RAM).
•
3.5
40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU
(device firmware upgrade).
3.6
Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
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Functional overview
3.7
Power management
3.7.1
Power supply schemes
•
VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied
to VDDA differs from one analog peripheral to another. Table 3 provides the summary of
the VDDA ranges for analog peripherals. The VDDA voltage level must be always
greater or equal to the VDD voltage level and must be provided first.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Table 3. External analog supply values for analog peripherals
3.7.2
Analog peripheral
Minimum VDDA supply
Maximum VDDA supply
ADC / COMP
2.0 V
3.6 V
DAC / OPAMP
2.4 V
3.6V
Power supply supervision
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
•
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.7.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
•
The MR mode is used in the nominal regulation mode (Run)
•
The LPR mode is used in Stop mode.
•
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
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Functional overview
3.7.4
STM32F303xB STM32F303xC
Low-power modes
The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC
alarm, COMPx, I2Cx or U(S)ARTx.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.
Note:
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.8
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
ADCx
DAC1
Conversion triggers
DMA
Memory to memory transfer trigger
Compx
Comparator output blanking
COMPx
TIMx
Timer input: OCREF_CLR input, input capture
ADCx
TIMx
Timer triggered by analog watchdog
TIMx
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Interconnect
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Functional overview
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued)
Interconnect source
Interconnect
destination
Interconnect action
GPIO
RTCCLK
HSE/32
MC0
TIM16
Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
COMPx
PVD
GPIO
TIM1, TIM8,
TIM15, 16, 17
Timer break
TIMx
External trigger, timer break
GPIO
ADCx
DAC1
Conversion external trigger
DAC1
COMPx
Comparator inverting input
Note:
For more details about the interconnect actions, please refer to the corresponding sections
in the reference manual (RM0316).
3.9
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
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Functional overview
STM32F303xB STM32F303xC
Figure 2. Clock tree
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