STM32F318C8Y6TR

STM32F318C8 STM32F318K8 Arm®-based Cortex®-M4 32-bit MCU+FPU, 64 KB Flash, 16 KB SRAM, ADC, DAC, 3 COMP, Op-Amp, 1.8 V Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M4 CPU with FPU (72 MHz max.), single-cycle multiplication and HW division, DSP instruction • Memories – 64 Kbytes of Flash memory – 16 Kbytes of SRAM on data bus LQFP48 (7x7 mm) UFQFPN32 (5x5 mm) WLCSP49 (3.417x3.151 mm) • Up to 17 capacitive sensing channels supporting touchkey, linear and rotary sensors • CRC calculation unit • Power management – Supply: VDD = 1.8 V ± 8% VDDA voltage range = 1.65 V to 3.6 V – External POR pin – Low-power: Sleep, Stop – VBAT supply for RTC and backup registers • Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x 16 PLL option – Internal 40 kHz oscillator • Up to 36 fast I/O ports, all mappable on external interrupt vectors, several 5 V-tolerant • Interconnect matrix • 7-channel DMA controller supporting timers, ADCs, SPIs, I2Cs, USARTs and DAC • 1 × ADC 0.20 μs (up to 11 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, single ended/differential mode, separate analog supply from 1.8 to 3.6 V • Temperature sensor • Up to 9 timers – One 32-bit timer with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – One 16-bit 6-channel advanced-control timer, with up to 6 PWM channels, deadtime generation and emergency stop – Three 16-bit timers with IC/OC/OCN or PWM, deadtime gen. and emergency stop – One 16-bit basic timer to drive the DAC – 2 watchdog timers (independent, window) – SysTick timer: 24-bit downcounter • Calendar RTC with alarm, periodic wakeup from Stop • Communication interfaces – Three I2Cs with 20 mA current sink to support Fast mode plus – Up to 3 USARTs, 1 with ISO 7816 I/F, auto baudrate detect and Dual clock domain – Up to two SPIs with multiplexed full duplex I2S – Infrared transmitter • Serial wire debug (SWD), JTAG • 96-bit unique ID • 1 x 12-bit DAC channel with analog supply from 2.4 to 3.6 V • Three fast rail-to-rail analog comparators with analog supply from 1.8 to 3.6 V • 1 x operational amplifier that can be used in PGA mode, all terminal accessible with analog supply from 2.4 to 3.6 V April 2022 This is information on a product in full production. DS10315 Rev 7 1/122 www.st.com Contents STM32F318C8 STM32F318K8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Arm® Cortex®-M4 core with FPU, embedded Flash and SRAM . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 3.11 2/122 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15.1 Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 General-purpose timers (TIM2, TIM15, TIM16, TIM17) . . . . . . . . . . . . . 21 3.15.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DS10315 Rev 7 STM32F318C8 STM32F318K8 Contents 3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22 3.17 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 Universal synchronous/asynchronous receiver transmitter (USART) . . . 24 3.19 Serial peripheral interfaces (SPI)/inter-integrated sound interfaces (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.21 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.22 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.22.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 50 6.3.3 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DS10315 Rev 7 3/122 4 Contents 7 STM32F318C8 STM32F318K8 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.15 NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.1 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.3 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 116 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. STM32F318x8 device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F318x8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F318x8 I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F318x8 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Capacitive sensing GPIOs available on STM32F318x8 devices . . . . . . . . . . . . . . . . . . . . 25 No. of capacitive sensing channels available on STM32F318x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32F318x8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32F318x8 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical and maximum current consumption from VDD supply at VDD = 1.8V . . . . . . . . . . 52 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 54 Typical and maximum VDD consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical and maximum VDDA consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 55 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 57 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DS10315 Rev 7 5/122 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. 6/122 STM32F318C8 STM32F318K8 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 108 LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DS10315 Rev 7 STM32F318C8 STM32F318K8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. STM32F318x8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32F318x8 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F318x8 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F318x8 WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM32F318x8 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ‘00’) . . . . . . . . . . . 55 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 69 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ADC typical current consumption in single-ended and differential modes . . . . . . . . . . . . . 91 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . 100 OPAMP Voltage Noise versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 WLCSP49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DS10315 Rev 7 7/122 7 Introduction 1 STM32F318C8 STM32F318K8 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F318x8 microcontrollers. This datasheet should be read in conjunction with the STM32F301x6/8 and STM32F318x8 advanced Arm®-based 32-bit MCUs reference manual (RM0366). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference Manual, available from Arm website www.arm.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 8/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 2 Description Description The STM32F318x8 family is based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 72 MHz and embedding a floating point unit (FPU). The family incorporates high-speed embedded memories (64 Kbytes of Flash memory, 16 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer a fast 12-bit ADC (5 Msps), three comparators, an operational amplifier, up to 17 capacitive sensing channels, one DAC channel, a low-power RTC, one generalpurpose 32-bit timer, one timer dedicated to motor control, and up to three general-purpose 16-bit timers, and one timer to drive the DAC. They also feature standard and advanced communication interfaces: three I2Cs, up to three USARTs, up to two SPIs with multiplexed full-duplex I2S, and an infrared transmitter. The STM32F318x8 family operates in the –40 to +85°C and –40 to +105°C temperature ranges from at 1.8 V ± 8% power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F318x8 family offers devices in 32-, 48- and 49-pin packages. The set of included peripherals changes with the device chosen. DS10315 Rev 7 9/122 43 Description STM32F318C8 STM32F318K8 Table 1. STM32F318x8 device features and peripheral counts Peripheral STM32F318K8 STM32F318C8 Flash (Kbyte) 64 SRAM (Kbyte) 16 Timers Advanced control 1 (16-bit) General purpose 3 (16-bit) 1 (32 bit) Basic 1 SysTick timer 1 Watchdog timers (independent, window) 2 PWM channels (all) (1) 16 18 PWM channels (except complementary) 10 12 SPI/I2S Comm. interfaces I GPIOs 2 2C 3 USART 2 3 Normal I/Os (TC, TTa) 9 19 5-Volt tolerant I/Os (FT, FT1) 14 17 DMA channels 7 Capacitive sensing channels 17 12-bit ADC 1 Number of ADC channels 8 12-bit DAC channels 11 1 Analog comparator 2 Operational amplifier 3 1 CPU frequency 72 MHz Operating voltage VDD = 1.8 V ± 8% VDDA voltage range = 1.65 V to 3.6 V Operating temperature Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C Junction temperature: - 40 to 125 °C Packages UFQFPN32 LQFP48 WLCSP49 1. This total number considers also the PWMs generated on the complementary output channels. 10/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Description Figure 1. STM32F318x8 block diagram TPIU VDD18 OBL Flash interface SWJTAG FPU Ibus Cortex M4 CPU System NVIC GP DMA1 7 channels Reset SRAM 16 KB Fmax: 72 MHz VDDIO = 1.8 +/- 8% VSS @VDDIO FLASH 64 KB 64 bits Dbus BusMatrix JTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO As AF Power Supply Supervision @VDDA NRESET VDDA VSSA NPOR @VDDA RC HS 8MHz RC LS PLL @VDDIO XTAL OSC 4 -32 MHz OSC_IN OSC_OUT Ind. WDG32K Temp. sensor 12-bit ADC1 IF Reset & clock control GPIO PORT A PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PF[1:0] GPIO PORT F 2 Channels,1 Comp Channel, BRK as AF 1 Channel, 1 Comp Channel, BRK as AF 1 Channel, 1 Comp Channel, BRK as AF 4 Channels, 4 Comp channels, ETR, BRK as AF RX, TX, CTS, RTS, SmartCard as AF EXT.IT WKUP TIMER 15 TIMER 16 TIMER 17 TIMER 1 / PWM APB2 fmax = 72 MHz XX AF XTAL 32kHz Backup RTC Reg AWU (20Byte) Backup interface USARTCLK I2CCLK ADC SAR 1 CLK TIMER2 (32-bit/PWM) CRC OSC32_IN OSC32_OUT ANTI-TAMP 4 Channels, ETR as AF SPI2/I2S2 MOSI, MISO, SCK, NSS as AF SPI3/I2S3 MOSI, MISO, SCK, NSS as AF Touch Sensing Controller AHB2 APB2 VBAT = 1.65V to 3.6V @VSW AHB2 APB1 USART2 RX, TX, CTS, RTS, as AF USART3 RX, TX, CTS, RTS, as AF I2C1 SCL, SDA, SMBA as AF I2C2 SCL, SDA, SMBA as AF I2C3 SCL, SDA, SMBA as AF WinWATCHDOG bx CAN SRAM for USB and CAN 1 KB USB 2.0 FS USB_DP, USB_DM TIMER6 IF 12bit DAC1 DAC1_CH1 as AF CAN TX, CAN RX @VDDA SYSCFG CTL @VDDA USART1 GP Comparator 6 GP Comparator 4 INTERFACE 6 groups of 4 channels as AF Standby interface APB1 Fmax = 36 MHz PA[15:0] AHB decoder VREF+ VREF- AHBPCLK APBP1CLK APBP2CLK HCLK FCLK OpAmp2 INxx / OUTxx @VDDA GP Comparator 2 Xx Ins, 4 OUTs as AF MS33035V3 DS10315 Rev 7 11/122 43 Functional overview STM32F318C8 STM32F318K8 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU, embedded Flash and SRAM The Arm® Cortex®-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 32-bit RISC processor with FPU features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single-precision FPU speeds up software development by using metalanguage development tools while avoiding saturation. With its embedded Arm core, the STM32F318x8 family is compatible with all Arm tools and software. Figure 1 shows the general block diagram of the STM32F318x8 family devices. 3.2 Memories 3.2.1 Embedded Flash memory All STM32F318x8 devices feature 64 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 3.2.2 Embedded SRAM STM32F318x8 devices feature 16 Kbytes of embedded SRAM. 3.3 Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10) or USART2 (PA2/Pa3) or I2C1 (PB6/PB7) or I2C3 (PA8, PB5). 12/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.4 Functional overview Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Power management 3.5.1 Power supply schemes • VSS, VDD = 1.8 V ± 8% V: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins. • VSSA, VDDA = 1.65 to 3.6 V: external analog power supply for ADC, DAC, comparators, operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to VDDA differs from one analog peripheral to another. Table 3 provides the summary of the VDDA ranges for analog peripherals. The VDDA voltage level must always be greater than or equal to the VDD voltage level and must be provided first. Table 2. External analog supply values for analog peripherals Analog peripheral Minimum VDDA supply Maximum VDDA supply ADC/COMP 2.0 V 3.6 V DAC/OPAMP 2.4 V 3.6 V Table 3. External analog supply values for analog peripherals Analog peripheral Minimum VDDA supply Maximum VDDA supply ADC/COMP 1.8 V 3.6 V DAC/OPAMP 2.4 V 3.6 V • 3.5.2 VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch which is guaranteed in the full range of VDD) when VDD is not present. Power supply supervisor The device power-on reset (POR) is controlled through the external NPOR pin. The device remains in reset state when NPOR pin is held low. To guarantee a proper power-on reset, the NPOR pin must be held low when VDDA is applied. Then, when VDD is stable, the reset state can be exited by: • either putting the NPOR pin in high impedance, NPOR pin has an internal pull up • on forcing the pin to high level by connecting it to VDDA. DS10315 Rev 7 13/122 43 Functional overview 3.5.3 STM32F318C8 STM32F318K8 Low-power modes The STM32F318x8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx, I2C or USARTx. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop. 3.6 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Table 4. STM32F318x8 peripheral interconnect matrix Interconnect source Interconnect action TIMx Timers synchronization or chaining ADC1 DAC1 Conversion triggers DMA Memory to memory transfer trigger Compx Comparator output blanking COMPx TIMx Timer input: OCREF_CLR input, input capture ADC1 TIM1 Timer triggered by analog watchdog GPIO RTCCLK HSE/32 MC0 TIM16 Clock source used as input channel for HSI and LSI calibration CSS CPU (hard fault) COMPx PVD GPIO TIM1 TIM15, 16, 17 Timer break TIMx 14/122 Interconnect destination DS10315 Rev 7 STM32F318C8 STM32F318K8 Functional overview Table 4. STM32F318x8 peripheral interconnect matrix (continued) Interconnect source Interconnect destination Interconnect action TIMx External trigger, timer break GPIO ADC1 DAC1 Conversion external trigger DAC1 COMPx Comparator inverting input Note: For more details about the interconnect actions, refer to the corresponding sections in the STM32F301x6/8 and STM32F318x8 reference manual RM0366. 3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz. The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. To achieve audio class performance, an audio crystal can be used. DS10315 Rev 7 15/122 43 Functional overview STM32F318C8 STM32F318K8 Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2Cx (x = 1,2,3) SYSCLK I2SSRC SYSCLK to I2Sx (x = 2,3) Ext. clock I2S_CKIN 8 MHz HSI HSI RC /2 HCLK PLLSRC PLLMUL PLL x2,x3,.. x16 /8 SW HSI PLLCLK AHB AHB prescaler /1,2,..512 HSE APB1 prescaler /1,2,4,8,16 SYSCLK OSC_OUT OSC_IN OSC32_IN OSC32_OUT PCLK1 SYSCLK HSI LSE 4-32 MHz HSE OSC /32 LSE OSC 32.768kHz APB2 prescaler /1,2,4,8,16 RTCCLK LSI to APB2 peripherals If (APB2 prescaler =1) x1 else x2 IWDGCLK to IWDG /1,2 PLLCLK HSI LSI HSE SYSCLK LSE /1,2,4, .. 128 Main clock output to USART1 PLLNODIV MCOPRE MCO PCLK2 to TIM 2, 6, 7 to RTC LSE RTCSEL[1:0] LSI RC 40kHz FHCLK Cortex free running clock to APB1 peripherals PCLK1 If (APB1 prescaler =1) x1 else x2 CSS /2,/3,... /16 to AHB bus, core, memory and DMA to cortex System timer MCO x2 ADC Prescaler /1,2,4 TIM1,15,16,17 to ADC1 ADC Prescaler /1,2,4,6,8,10,12,16, 32,64,128,256 MS34979V2 16/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.8 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allows I/O toggling up to 36 MHz. 3.9 Direct memory access (DMA) The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, timers, DAC and ADC. 3.10 Interrupts and events 3.10.1 Nested vectored interrupt controller (NVIC) The STM32F318x8 devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. DS10315 Rev 7 17/122 43 Functional overview 3.11 STM32F318C8 STM32F318K8 Fast analog-to-digital converter (ADC) An analog-to-digital converter, with selectable resolution between 12 and 6 bit, is embedded in the STM32F318x8 family devices. The ADC has up to 11 external channels performing conversions in single-shot or scan modes. Channels can be configured to be either singleended input or differential input. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Single-shunt phase current reading techniques. The ADC can be served by the DMA controller. Three analog watchdogs are available. The analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.11.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. 3.11.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN18 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. 18/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.11.3 Functional overview VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.12 Digital-to-analog converter (DAC) One 12-bit buffered DAC channel (DAC1_OUT1) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 3.13 • One DAC output channel • 8-bit or 12-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • DMA capability • External triggers for conversion Operational amplifier (OPAMP) The STM32F318x8 devices embed one operational amplifier with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When the operational amplifier is selected, an external ADC channel is used to enable output measurement. The operational amplifier features: • 8.2 MHz bandwidth • 0.5 mA output capability • Rail-to-rail input/output • In PGA mode, the gain can be programmed to be 2, 4, 8 or 16. DS10315 Rev 7 19/122 43 Functional overview 3.14 STM32F318C8 STM32F318K8 Ultra-fast comparators (COMP) The STM32F318x8 devices embed up to three ultra-fast rail-to-rail comparators which offer the features below: • Programmable internal or external reference voltage • Selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output • Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded internal reference voltage for the value and precision of the internal reference voltage. All comparators can wake up from STOP mode, and also generate interrupts and breaks for the timers. 3.15 Timers and watchdogs The STM32F318x8 devices include advanced control timer, up to general-purpose timers, basic timer, two watchdog timers and a SysTick timer. Table 5 compares the features of the advanced control, general purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Advanced control TIM1(1) 16-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 Yes TIM2 32-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 No TIM15(1) 16-bit Up Any integer between 1 and 65536 Yes 2 1 TIM16(1), TIM17(1) 16-bit Up Any integer between 1 and 65536 Yes 1 1 TIM6 16-bit Up Any integer between 1 and 65536 Yes 0 No Generalpurpose Basic 1. Capture/ Complementary compare outputs Channels TIM1/15/16/17 can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively. 20/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.15.1 Functional overview Advanced timer (TIM1) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIM timers (described in Section 3.15.2 using the same architecture, so the advanced-control timers can work together with the TIM timers via the Timer Link feature for synchronization or event chaining. 3.15.2 General-purpose timers (TIM2, TIM15, TIM16, TIM17) There are up to four synchronizable general-purpose timers embedded in the STM32F318x8 devices (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. TIM2 TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler It features 4 independent channels for input capture/output compare, PWM or one-pulse mode output. It can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. It has independent DMA request generation and supports quadrature encoders. TIM15, TIM16 and TIM 17 These three timers general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. • TIM15 has 2 channels and 1 complementary channel • TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. DS10315 Rev 7 21/122 43 Functional overview 3.15.3 STM32F318C8 STM32F318K8 Basic timer (TIM6) This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base. 3.15.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop mode. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option byte. The counter can be frozen in debug mode. 3.15.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.16 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source Real-time clock (RTC) and backup registers The RTC and the 20 backup registers are supplied through a switch that takes power from either the VDD supply when present or the VBAT pin. The backup registers are five 32-bit registers used to store 20 byte of user application data when VDD power is not present. They are not reset by a system or power reset. The RTC is an independent BCD timer/counter. It supports the following features: 22/122 • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms with wake up from Stop mode capability. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. • Two anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop mode on tamper event detection. DS10315 Rev 7 STM32F318C8 STM32F318K8 Functional overview • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop mode on timestamp event detection. • 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP capability. The RTC clock sources can be: 3.17 • A 32.768 kHz external crystal • A resonator or oscillator • The internal low-power RC oscillator (typical frequency of 40 kHz) • The high-speed external clock divided by 32. Inter-integrated circuit interfaces (I2C) The devices feature three I2C bus interfaces which can operate in multimaster and slave mode. Each I2C interface can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes. All I2C interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 6. Comparison of I2C analog and digital filters - Analog filter Digital filter Pulse width of suppressed spikes ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. It also has a clock domain independent from the CPU clock, allowing the I2Cx (x=1,3) to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller. Refer to Table 7 for the features available in I2C1, I2C2 and I2C3. Table 7. STM32F318x8 I2C implementation I2C features(1) I2C1 I2C2 I2C3 7-bit addressing mode X X X 10-bit addressing mode X X X Standard mode (up to 100 kbit/s) X X X Fast mode (up to 400 kbit/s) X X X DS10315 Rev 7 23/122 43 Functional overview STM32F318C8 STM32F318K8 Table 7. STM32F318x8 I2C implementation (continued) I2C features(1) I2C1 I2C2 I2C3 Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Independent clock X X X SMBus X X X Wakeup from STOP X X X 1. X = supported. 3.18 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F318x8 devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3). The USART interfaces are able to communicate at speeds of up to 9 Mbit/s. All USARTs support hardware management of the CTS and RTS signals, multiprocessor communication mode, single-wire half-duplex communication mode and synchronous mode. USART1 supports SmartCard mode, IrDA SIR ENDEC, LIN Master capability and autobaudrate detection. All USART interfaces can be served by the DMA controller. Refer to Table 8 for the features available in all USARTs interfaces. Table 8. USART features USART modes/features(1) USART1 USART2 USART3 Hardware flow control for modem X X X Continuous communication using DMA X X X Multiprocessor communication X X X Synchronous mode X X X SmartCard mode X - - Single-wire half-duplex communication X X X IrDA SIR ENDEC block X - - LIN mode X - - Dual clock domain and wakeup from Stop mode X - - Receiver timeout interrupt X - - Modbus communication X - - Auto baud rate detection X - - Driver Enable X X X 1. X = supported. 24/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.19 Functional overview Serial peripheral interfaces (SPI)/inter-integrated sound interfaces (I2S) Two SPI interfaces (SPI2 and SPI3) allow communication up to 18 Mbit/s in slave and master modes in full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. Refer to Table 9 for the features available in SPI2 and SPI3. Table 9. STM32F318x8 SPI/I2S implementation SPI features(1) SPI2 SPI3 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X I2S mode X X TI mode X X 1. X = supported. 3.20 Touch sensing controller (TSC) The STM32F318x8 devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 17 capacitive sensing channels distributed over 6 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (for example glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. Table 10. Capacitive sensing GPIOs available on STM32F318x8 devices Group 1 Capacitive sensing signal name Pin name TSC_G1_IO1 PA0 TSC_G1_IO2 PA1 TSC_G1_IO3 PA2 TSC_G1_IO4 PA3 DS10315 Rev 7 25/122 43 Functional overview STM32F318C8 STM32F318K8 Table 10. Capacitive sensing GPIOs available on STM32F318x8 devices (continued) Group 2 3 4 5 6 Capacitive sensing signal name Pin name TSC_G2_IO1 PA4 TSC_G2_IO2 PA5 TSC_G2_IO3 PA6 TSC_G2_IO4 PA7 TSC_G3_IO2 PB0 TSC_G3_IO3 PB1 TSC_G4_IO1 PA9 TSC_G4_IO2 PA10 TSC_G4_IO3 PA13 TSC_G4_IO4 PA14 TSC_G5_IO1 PB3 TSC_G5_IO2 PB4 TSC_G5_IO3 PB6 TSC_G5_IO4 PB7 TSC_G6_IO1 PB11 TSC_G6_IO2 PB12 TSC_G6_IO3 PB13 TSC_G6_IO4 PB14 Table 11. No. of capacitive sensing channels available on STM32F318x8 devices Number of capacitive sensing channels Analog I/O group 26/122 STM32F318C8 STM32F318K8 G1 3 3 G2 3 3 G3 2 1 G4 3 3 G5 3 3 G6 3 0 Number of capacitive sensing channels 17 13 DS10315 Rev 7 STM32F318C8 STM32F318K8 3.21 Functional overview Infrared transmitter The STM32F318x8 devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13. To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels. Figure 3. Infrared transmitter TIMER 16 OC (for envelop) TIMER 17 PB9/PA13 OC (for carrier) MS30365V1 3.22 Development support 3.22.1 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DS10315 Rev 7 27/122 43 Pinouts and pin description 4 STM32F318C8 STM32F318K8 Pinouts and pin description VSS_1 BOOT0 NPOR PB6 PB5 PB4 PB3 PA15 Figure 4. STM32F318x8 UFQFPN32 pinout 32 31 30 29 28 27 26 25 VDD_1 1 24 PA14 PF0/OSC_IN 2 23 PA13 PF1/OSC_OUT 3 22 PA12 NRST 4 21 PA11 UFQFPN32 PA0 7 18 PA8 PA1 8 17 VDD_2 9 10 11 12 13 14 15 16 VSS_2 PA9 PB0 19 PA7 6 PA6 VSSA/VREF- PA5 PA10 PA4 20 PA3 5 PA2 VDDA/VREF+ MS33032V1 1. The above figure shows the package top view 28/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Pinouts and pin description VDD_1 VSS_1 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 5. STM32F318x8 LQFP48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_3 VSS_3 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VDD_2 PB10 PB11 VSS_2 NPOR 1 2 3 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VBAT PC13 PC14/OSC32_IN PC15/OSC32_OUT PF0/OSC_IN PF1/OSC_OUT NRST VSSA/VREFVDDA PA0 PA1 PA2 MS38390V1 1. The above figure shows the package top view. DS10315 Rev 7 29/122 43 Pinouts and pin description STM32F318C8 STM32F318K8 Figure 6. STM32F318x8 WLCSP49 ballout 1 2 3 4 5 6 A PA14 PA15 PB3 PB4 BOOT0 VDDA NC B VSS VDD PA13 PB5 PB8 VBAT VDD C PA11 PA10 PA12 PB6 PB9 PC15 PC14 D PA8 PA9 VSS PB7 PC13 E PB15 PB12 PB10 PA3 PA2 VSSA VREF- NRST F PB14 VDD PA7 PA6 PA5 PA0 VSS G PB13 PB11 NPOR PB1 PB0 PA4 PA1 7 PF1 PF0 OSC_OUT OSC_IN MS34978V2 1. The above figure shows the package top view. 30/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Pinouts and pin description Table 12. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Alternate functions Pin functions Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, I2C FM+ option TTa 3.3 V tolerant I/O directly connected to ADC1 TT 3.3 V tolerant I/O TC Standard 3.3V I/O POR Dedicated to NPOR pin B Dedicated BOOT0 pin RST Bi-directional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Functions selected through GPIOx_AFR registers Additional Functions directly selected/enabled through peripheral registers functions DS10315 Rev 7 31/122 43 WLCSP49 Pin name (function after reset) Pin type I/O structure Notes - 1 B6 VBAT S - - - 2 D5 PC13(1) TAMPER1 WKUP2 (PC13) I/O TC (1) TIM1_CH1N WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT - 3 C7 PC14(1) OSC32_IN (PC14) I/O TC (1) - OSC32_IN - 4 C6 PC15(1) OSC32_OUT (PC14) I/O TC (1) - OSC32_OUT 2 5 D7 PF0 OSC_IN (PF0) I/O FTf - I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N OSC_IN 3 6 D6 PF1 OSC_OUT (PF1) O FTf - I2C2_SCL, SPI2_SCK/I2S2_CK OSC_OUT 4 7 E7 NRST I/O RST - Device reset input/internal reset output (active low) 6 8 E6 VSSA/VREF- S - - Analog ground/Negative reference voltage 5 9 A6 VDDA/VREF+ S - - Analog power supply/Positive reference voltage 7 10 F6 PA0 -TAMPER2WKUP1 I/O TTa (2) TIM2_CH1/TIM2_ETR, TSC_G1_IO1, USART2_CTS, EVENTOUT ADC1_IN1, RTC_TAMP2, WKUP1 8 11 G7 PA1 I/O TTa (2) RTC_REFIN, TIM2_CH2, TSC_G1_IO2, USART2_RTS_DE, TIM15_CH1N, EVENTOUT ADC1_IN2 9 12 E5 PA2 I/O TTa (2) TIM2_CH3, TSC_G1_IO3, USART2_TX, COMP2_OUT, TIM15_CH1, EVENTOUT ADC1_IN3, COMP2_INM 10 13 E4 PA3 I/O TTa (2) TIM2_CH4, TSC_G1_IO4, USART2_RX, ADC1_IN4 TIM15_CH2, EVENTOUT Alternate functions Additional functions Backup power supply STM32F318C8 STM32F318K8 LQFP48 DS10315 Rev 7 UQFN32 Pin number Pinouts and pin description 32/122 Table 13. STM32F318x8 pin definitions WLCSP49 Pin name (function after reset) Pin type I/O structure Notes Alternate functions - - F7 VSS_4 S - - - - - - F2 VDD_4 S - - - - 11 14 G6 PA4 I/O TTa (2)(3) 12 15 F5 PA5 I/O TTa - 13 16 F4 PA6 I/O TTa (3) 14 17 F3 PA7 I/O TTa - TIM17_CH1, TSC_G2_IO4, TIM1_CH1N, ADC1_IN15, COMP2_INP, EVENTOUT OPAMP2_VINP 15 18 G5 PB0 I/O TTa - TSC_G3_IO2, TIM1_CH2N, EVENTOUT ADC1_IN11, COMP4_INP, OPAMP2_VINP - 19 G4 PB1 I/O TTa - TSC_G3_IO3, TIM1_CH3N, COMP4_OUT, EVENTOUT ADC1_IN12 - 21 E3 PB10 I/O TT - TIM2_CH3, TSC_SYNC, USART3_TX, EVENTOUT - 22 G2 PB11 I/O TTa - TIM2_CH4, TSC_G6_IO1, USART3_RX, ADC1_IN14, COMP6_INP EVENTOUT 16 23 D3 VSS_2 S - - Digital ground 17 24 B2 VDD_2 S - - Digital power supply Additional functions TSC_G2_IO1, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT ADC1_IN5, DAC1_OUT1, COMP2_INM, COMP4_INM, COMP6_INM TIM2_CH1/TIM2_ETR, TSC_G2_IO2, EVENTOUT OPAMP2_VINM TIM16_CH1, TSC_G2_IO3, TIM1_BKIN, EVENTOUT ADC1_IN10, OPAMP2_VOUT - 33/122 Pinouts and pin description LQFP48 DS10315 Rev 7 UQFN32 Pin number STM32F318C8 STM32F318K8 Table 13. STM32F318x8 pin definitions (continued) WLCSP49 Pin name (function after reset) Pin type I/O structure Notes - 25 E2 PB12 I/O TT - TSC_G6_IO2, I2C2_SMBAL, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, EVENTOUT - 26 G1 PB13 I/O TTa - TSC_G6_IO3, SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, EVENTOUT ADC1_IN13 - 27 F1 PB14 I/O TTa - TIM15_CH1, TSC_G6_IO4, SPI2_MISO/I2S2ext_SD, TIM1_CH2N, USART3_RTS_DE, EVENTOUT OPAMP2_VINP - 28 E1 PB15 I/O TTa - RTC_REFIN, TIM15_CH2, TIM15_CH1N, TIM1_CH3N, SPI2_MOSI/I2S2_SD, EVENTOUT COMP6_INM 18 29 D1 PA8 I/O FT - MCO, I2C3_SCL, I2C2_SMBAL, I2S2_MCK, TIM1_CH1, USART1_CK, EVENTOUT - 19 30 D2 PA9 I/O FTf - I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, EVENTOUT - - Alternate functions Additional functions - 20 31 C2 PA10 I/O FTf - TIM17_BKIN, TSC_G4_IO2, I2C2_SDA, SPI2_MISO/I2S2ext_SD, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4, EVENTOUT 21 32 C1 PA11 I/O FT - SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, TIM1_CH4, TIM1_BKIN2, EVENTOUT - 22 33 C3 PA12 I/O FT - TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, TIM1_ETR, EVENTOUT - STM32F318C8 STM32F318K8 LQFP48 DS10315 Rev 7 UQFN32 Pin number Pinouts and pin description 34/122 Table 13. STM32F318x8 pin definitions (continued) LQFP48 WLCSP49 Pin name (function after reset) Pin type I/O structure Notes DS10315 Rev 7 UQFN32 Pin number 23 34 B3 PA13 I/O FT - - 35 B1 VSS_3 S - - Digital ground - 36 B2 VDD_3 S - - Digital power supply 24 37 A1 PA14 I/O FTf - SWCLK-JTCK, TSC_G4_IO4, I2C1_SDA, TIM1_BKIN, USART2_TX, EVENTOUT - - Alternate functions Additional functions SWDIO, TIM16_CH1N, TSC_G4_IO3, IR-OUT, USART3_CTS, EVENTOUT - 38 A2 PA15 I/O FTf - 26 39 A3 PB3 I/O FT - JTDO-TRACESWO, TIM2_CH2, TSC_G5_IO1, SPI3_SCK/I2S3_CK, USART2_TX, EVENTOUT - 27 40 A4 PB4 I/O FT - JTRST, TIM16_CH1, TSC_G5_IO2, SPI3_MISO/I2S3ext_SD, USART2_RX, TIM17_BKIN, EVENTOUT - 28 41 B4 PB5 I/O FT - TIM16_BKIN, I2C1_SMBAl, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, TIM17_CH1, EVENTOUT - 29 42 C4 PB6 I/O FTf - TIM16_CH1N, TSC_G5_IO3, I2C1_SCL, USART1_TX, EVENTOUT - - 43 D4 PB7 I/O FTf - TIM17_CH1N, TSC_G5_IO4, I2C1_SDA, USART1_RX, EVENTOUT - 30 20 G3 NPOR I POR - Device power-on reset input Pinouts and pin description 35/122 25 JTDI, TIM2_CH1/TIM2_ETR, TSC_SYNC, I2C1_SCL, SPI3_NSS/I2S3_WS, USART2_RX, TIM1_BKIN, EVENTOUT STM32F318C8 STM32F318K8 Table 13. STM32F318x8 pin definitions (continued) LQFP48 WLCSP49 Pin name (function after reset) Pin type I/O structure Notes DS10315 Rev 7 UQFN32 Pin number 31 44 A5 BOOT0 I B - - 45 B5 PB8 I/O FTf - TIM16_CH1, TSC_SYNC, I2C1_SCL, USART3_RX TIM1_BKIN, EVENTOUT - 46 C5 PB9 I/O FTf - TIM17_CH1, I2C1_SDA, IR-OUT, USART3_TX, COMP2_OUT, EVENTOUT 32 47 D3 VSS_1 S - - Digital ground "1" 48 B7 VDD_1 S - - Digital power supply Alternate functions Additional functions Boot memory selection - Pinouts and pin description 36/122 Table 13. STM32F318x8 pin definitions (continued) 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0366 reference manual. 2. Fast ADC channel. 3. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O. STM32F318C8 STM32F318K8 EVENT - - TSC _G1_IO1 - - - USART2 _CTS - - - - - - - EVENT OUT PA1 RTC _REFIN TIM2 _CH2 - TSC _G1_IO2 - - - USART2 _RTS_D E - TIM15 _CH1N - - - - - EVENT OUT PA2 - TIM2 _CH3 - TSC _G1_IO3 - - - USART2 _TX COMP2 _OUT TIM15 _CH1 - - - - - EVENT OUT PA3 - TIM2 _CH4 - TSC _G1_IO4 - - - USART2 _RX - TIM15 _CH2 - - - - - EVENT OUT PA4 - - - TSC _G2_IO1 - - SPI3_NSS/ USART2 I2S3_WS _CK - - - - - - - EVENT OUT PA5 - TIM2 _CH1/ TIM2 _ETR - TSC _G2_IO2 - - - - - - - - - - - EVENT OUT PA6 - TIM16 _CH1 - TSC _G2_IO3 - - TIM1_BKIN - - - - - - - - EVENT OUT PA7 - TIM17 _CH1 - TSC _G2_IO4 - - TIM1 _CH1N - - - - - - - - EVENT OUT PA8 MCO - - I2C3 _SCL I2C2 _SMBAL I2S2 _MCK TIM1_CH1 USART1 _CK - - - - - - - EVENT OUT PA9 - - I2C3 _SMBAL TSC _G4_IO1 I2C2 _SCL I2S3 _MCK TIM1_CH2 USART1 _TX - TIM15 _BKIN TIM2 _CH3 - - - - EVENT OUT Port name PA0 TIM2 _CH1/ TIM2 _ETR DS10315 Rev 7 37/122 Pinouts and pin description - AF15 - AF13 AF14 TIM1 AF12 TIM1 AF11 TIM2/TIM17 AF10 TIM1/TIM15 AF9 I2C3/GPCOMP2/ GPCOMP4/GPCOMP6 AF8 USART1/USART2/US ART3/ GPCOMP6 AF7 SPI2/I2S2/SPI3/ I2S3/TIM1/Infrared AF6 SPI2/I2S2/ SPI3/I2S3/Infrared AF5 I2C1/I2C2/TIM1/ TIM16/TIM17 AF4 I2C3/TIM15/TSC AF3 I2C3/TIM1/TIM2/TIM15 AF2 TIM2/TIM15/TIM16 /TIM17/EVENT AF1 SYS_AF AF0 STM32F318C8 STM32F318K8 Table 14. Alternate functions for port A PA12 - TIM16 _CH1 - PA13 SWDATJTMS TIM16 _CH1N PA14 SWCLKJTCK PA15 JTDI DS10315 Rev 7 SPI2_MIS O/I2S2ext TIM1_CH3 _SD USART1 _RX COMP6 _OUT - TIM2 _CH4 - - - - EVENT OUT - SPI2_MO SI/I2S2 _SD TIM1 _CH1N USART1 _CTS - - - TIM1 _CH4 TIM1 _BKIN2 - - EVENT OUT - - I2SCKIN TIM1 _CH2N USART1 _RTS_D E COMP2 _OUT - - TIM1 _ETR - - - EVENT OUT - TSC _G4_IO3 - IR-OUT - USART3 _CTS - - - - - - - EVENT OUT - - TSC _G4_IO4 I2C1 _SDA - TIM1_BKIN USART2 _TX - - - - - - - EVENT OUT TIM2_C H1/ TIM2_E TR - TSC _SYNC I2C1 _SCL - SPI3_NSS/ USART2 I2S3_WS _RX - TIM1 _BKIN - - - - - EVENT OUT STM32F318C8 STM32F318K8 EVENT - AF15 - - AF13 AF14 - - AF12 TIM1 - AF11 TIM1 PA11 AF10 TIM2/TIM17 I2C2 _SDA AF9 TIM1/TIM15 TSC _G4_IO2 AF8 I2C3/GPCOMP2/ GPCOMP4/GPCOMP6 - AF7 USART1/USART2/US ART3/ GPCOMP6 TIM17 _BKIN AF6 SPI2/I2S2/SPI3/ I2S3/TIM1/Infrared - AF5 SPI2/I2S2/ SPI3/I2S3/Infrared PA10 Port name I2C1/I2C2/TIM1/ TIM16/TIM17 AF4 I2C3/TIM15/TSC AF3 I2C3/TIM1/TIM2/TIM15 AF2 TIM2/TIM15/TIM16 /TIM17/EVENT AF1 SYS_AF AF0 Pinouts and pin description 38/122 Table 14. Alternate functions for port A (continued) EVENT - - - TSC _G3_IO2 - - TIM1 _CH2N - - - - - - - - EVENT OUT PB1 - - - TSC _G3_IO3 - - TIM1 _CH3N - COMP4_ OUT - - - - - - EVENT OUT PB3 JTDOTRACE SWO TIM2 _CH2 - TSC _G5_IO1 - - SPI3_SC USART2 K/I2S3_ _TX CK - - - - - - - EVENT OUT PB4 JTRST TIM16 _CH1 - TSC _G5_IO2 - - SPI3_MI SO/I2S3 _SD USART2 _RX - - TIM17 _BKIN - - - - EVENT OUT PB5 - TIM16 _BKIN - - I2C1 _SMBAl - SPI3 _MOSI/ I2S3ext_ SD USART2 _CK I2C3 _SDA - TIM17 _CH1 - - - - EVENT OUT PB6 - TIM16 _CH1N - TSC _G5_IO3 I2C1 _SCL - - USART1 _TX - - - - - - - EVENT OUT PB7 - TIM17 _CH1N - TSC _G5_IO4 I2C1 _SDA - - USART1 _RX - - - - - - - EVENT OUT PB8 - TIM16 _CH1 - TSC _SYNC I2C1 _SCL - - USART3 _RX - - - - TIM1 _BKIN - - EVENT OUT PB9 - TIM17 _CH1 - - I2C1 _SDA - IR-OUT USART3 COMP2_ _TX OUT - - - - - - EVENT OUT PB10 - TIM2 _CH3 - TSC _SYNC - - - USART3 _TX - - - - - - - EVENT OUT PB11 - TIM2 _CH4 - TSC _G6_IO1 - - - USART3 _RX - - - - - - - EVENT OUT Port name PB0 DS10315 Rev 7 39/122 Pinouts and pin description - AF15 - AF13 AF14 TIM1 AF12 TIM1 AF11 TIM2/TIM17 AF10 TIM1/TIM15 AF9 I2C3/GPCOMP2/ GPCOMP4/GPCOMP6 AF8 USART1/USART2/US ART3/ GPCOMP6 AF7 SPI2/I2S2/SPI3/ I2S3/TIM1/Infrared AF6 SPI2/I2S2/ SPI3/I2S3/Infrared AF5 I2C1/I2C2/TIM1/ TIM16/TIM17 AF4 I2C3/TIM15/TSC AF3 I2C3/TIM1/TIM2/TIM15 AF2 TIM2/TIM15/TIM16 /TIM17/EVENT AF1 SYS_AF AF0 STM32F318C8 STM32F318K8 Table 15. Alternate functions for port B AF15 PB12 - - - TSC I2C2 _G6_IO2 _SMBAL SPI2_NS S/I2S2_ WS TIM1 _BKIN USART3 _CK - - - - - - - EVENT OUT PB13 - - - TSC _G6_IO3 - SPI2_SC K/ I2S2_CK TIM1 _CH1N USART3 _CTS - - - - - - - EVENT OUT PB14 - TIM15 _CH1 - TSC _G6_IO4 - SPI2_MI SO/I2S2 ext_SD TIM1 _CH2N USART3 _RTS _DE - - - - - - - EVENT OUT PB15 RTC _REFIN TIM15 _CH2 TIM15 _CH1N - TIM1 _CH3N SPI2_M OSI/ I2S2_SD - - - - - - - - - EVENT OUT Port name EVENT AF13 AF14 - AF12 - AF11 TIM1 AF10 TIM1 AF9 TIM2/TIM17 AF8 TIM1/TIM15 AF7 I2C3/GPCOMP2/ GPCOMP4/GPCOMP6 I2C1/I2C2/TIM1/ TIM16/TIM17 AF6 USART1/USART2/US ART3/ GPCOMP6 I2C3/TIM15/TSC AF5 SPI2/I2S2/SPI3/ I2S3/TIM1/Infrared AF4 SPI2/I2S2/ SPI3/I2S3/Infrared AF3 I2C3/TIM1/TIM2/TIM15 AF2 TIM2/TIM15/TIM16 /TIM17/EVENT AF1 SYS_AF AF0 Pinouts and pin description 40/122 Table 15. Alternate functions for port B (continued) DS10315 Rev 7 Table 16. Alternate functions for port F AF1 AF2 AF3 AF4 AF5 SYS_AF TIM2/TIM15/ TIM16/TIM17/ EVENT I2C3/TIM1/TIM2/ TIM15 I2C3/TIM15/TSC I2C1/I2C2/TIM1/ TIM16/TIM17 SPI2/I2S2/ SPI3/I2S3/ Infrared PF0 - - - - I2C2_SDA SPI2_NSS/ I2S2_WS TIM1_CH3N - PF1 - - - - I2C2_SCL SPI2_SCK/ I2S2_CK - - Port name AF6 AF7 SPI2/I2S2/SPI3/ USART1/USAR I2S3/TIM1/ T2/USART3/ Infrared GPCOMP6 STM32F318C8 STM32F318K8 AF0 STM32F318C8 STM32F318K8 5 Memory mapping Memory mapping Figure 7. STM32F318x8 memory mapping 0x5000 07FF AHB3 0xFFFF FFFF 7 Cortex-M4 with FPU Internal Peripherals 0xE000 0000 0x5000 0000 Reserved 0x4800 1800 AHB2 0x4800 0000 Reserved 6 0x4002 43FF AHB1 0xC000 0000 0x4002 0000 Reserved 5 0x4001 6C00 APB2 0xA000 0000 0x4001 0000 Reserved 4 0x4000 A000 APB1 0x8000 0000 0x4000 0000 3 0x1FFF FFFF Option bytes 0x6000 0000 0x1FFF F800 System memory 2 0x4000 0000 0x1FFF D800 Peripherals 1 0x2000 0000 0 Reserved 0x0804 0000 SRAM Flash memory 0x0800 0000 CODE Reserved 0x0001 0000 0x0000 0000 Reserved 0x0000 0000 Flash, system memory or SRAM, depending on BOOT configuration MSv30355V3 DS10315 Rev 7 41/122 43 Memory mapping STM32F318C8 STM32F318K8 Table 17. STM32F318x8 peripheral register boundary addresses (1) Bus Boundary address Size (byte) AHB3 0x5000 0000 - 0x5000 03FF 1K - 0x4800 1800 - 0x4FFF FFFF ~132 M 0x4800 1400 - 0x4800 17FF 1K GPIOF 0x4800 1000 - 0x4800 13FF 1K Reserved 0x4800 0C00 - 0x4800 0FFF 1K Reserved 0x4800 0800 - 0x4800 0BFF 1K GPIOC 0x4800 0400 - 0x4800 07FF 1K GPIOB 0x4800 0000 - 0x4800 03FF 1K GPIOA 0x4002 4400 - 0x47FF FFFF ~128 M 0x4002 4000 - 0x4002 43FF 1K TSC 0x4002 3400 - 0x4002 3FFF 3K Reserved 0x4002 3000 - 0x4002 33FF 1K CRC 0x4002 2400 - 0x4002 2FFF 3K Reserved 0x4002 2000 - 0x4002 23FF 1K Flash interface 0x4002 1400 - 0x4002 1FFF 3K Reserved 0x4002 1000 - 0x4002 13FF 1K RCC 0x4002 0400 - 0x4002 0FFF 3K Reserved 0x4002 0000 - 0x4002 03FF 1K DMA1 0x4001 8000 - 0x4001 FFFF 32 K Reserved 0x4001 4C00 - 0x4001 7FFF 13 K Reserved 0x4001 4800 - 0x4001 4BFF 1K TIM17 0x4001 4400 - 0x4001 47FF 1K TIM16 0x4001 4000 - 0x4001 43FF 1K TIM15 0x4001 3C00 - 0x4001 3FFF 1K Reserved 0x4001 3800 - 0x4001 3BFF 1K USART1 0x4001 3000 - 0x4001 37FF 2K Reserved 0x4001 2C00 - 0x4001 2FFF 1K TIM1 0x4001 0800 - 0x4001 2BFF 8K Reserved 0x4001 0400 - 0x4001 07FF 1K EXTI 0x4001 0000 - 0x4001 03FF 1K SYSCFG + COMP + OPAMP 0x4000 9C00 - 0x4000 FFFF 25 K Reserved AHB2 - AHB1 - APB2 - 42/122 DS10315 Rev 7 Peripheral ADC1 Reserved Reserved STM32F318C8 STM32F318K8 Memory mapping Table 17. STM32F318x8 peripheral register boundary addresses (continued)(1) Bus Boundary address Size (byte) 0x4000 7C00 - 0x4000 9BFF 8K Reserved 0x4000 7800 - 0x4000 7BFF 1K I2C3 0x4000 7400 - 0x4000 77FF 1K DAC1 0x4000 7000 - 0x4000 73FF 1K PWR 0x4000 5C00 - 0x4000 6FFF 5K Reserved 0x4000 5800 - 0x4000 5BFF 1K I2C2 0x4000 5400 - 0x4000 57FF 1K I2C1 0x4000 4C00 - 0x4000 53FF 2K Reserved 0x4000 4800 - 0x4000 4BFF 1K USART3 0x4000 4400 - 0x4000 47FF 1K USART2 0x4000 4000 - 0x4000 43FF 1K I2S3ext 0x4000 3C00 - 0x4000 3FFF 1K SPI3/I2S3 0x4000 3800 - 0x4000 3BFF 1K SPI2/I2S2 0x4000 3400 - 0x4000 37FF 1K I2S2ext 0x4000 3000 - 0x4000 33FF 1K IWDG 0x4000 2C00 - 0x4000 2FFF 1K WWDG 0x4000 2800 - 0x4000 2BFF 1K RTC 0x4000 1400 - 0x4000 27FF 5K Reserved 0x4000 1000 - 0x4000 13FF 1K TIM6 0x4000 0400 - 0x4000 0FFF 3K Reserved 0x4000 0000 - 0x4000 03FF 1K TIM2 - 0x2000 4000 - 3FFF FFFF ~512 M SRAM 0x2000 0000 - 0x2000 3FFF 16 K SRAM Option bytes 0x1FFF F800 - 0x1FFF FFFF 2K Option bytes Memory 0x1FFF D800 - 0x1FFF F7FF 8K System memory - 0x0801 0000 - 0x1FFF D7FF ~384 M Memory 0x0800 0000 - 0x0800 FFFF 64 K - 0x0001 0000 - 0x07FF FFFF ~128 M Memory or SRAM 0x0000 000 - 0x0000 FFFF 64 K APB1 Peripheral Reserved Reserved Main Flash memory Reserved Main Flash memory, system memory or SRAM depending on BOOT configuration 1. The gray color is used for reserved Flash memory addresses. DS10315 Rev 7 43/122 43 Electrical characteristics STM32F318C8 STM32F318K8 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 1.8 V,VDDA= 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Figure 8. Pin loading conditions Figure 9. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 44/122 DS10315 Rev 7 MS19211V1 STM32F318C8 STM32F318K8 6.1.6 Electrical characteristics Power supply scheme Figure 10. Power supply scheme VBAT Backup circuitry (LSE, RTC, Wakeup logic, Backup registers) OUT GP I/Os IN Level shifter Power switch 1.65 – 3.6 V VDD I/O logic Kernel logic (CPU, digital & memories) 4 x VDD Regulator 4 x 100 nF + 1 x 4.7 μF 4 x VSS VDDA VDDA VREF+ 10 nF + 1 μF ADC/DAC VREF- Analog: RCs, PLL, comparators, OPAMP, .... VSSA MS34995V1 Caution: Each power supply pair (for example VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS10315 Rev 7 45/122 104 Electrical characteristics 6.1.7 STM32F318C8 STM32F318K8 Current consumption measurement Figure 11. Current consumption measurement scheme I DD_VBAT VBAT IDD VDD IDDA VDDA MS19213V1 46/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics, and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 18. Voltage characteristics(1) Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDD and VBAT) -0.3 1.95 V VDDA–VSS External main supply voltage -0.3 4.0 V VDD–VDDA Allowed voltage difference for VDD > VDDA - 0.4 V Input voltage on FT and FTf pins VSS −0.3 VDD + 4.0 Input voltage on TTa and TT pins VSS −0.3 4.0 Input voltage on POR pin VSS − 0.3 VDDA + 4.0 Input voltage on any other pin VSS − 0.3 4.0 0 9 - 50 - 50 VIN(2) Input voltage on Boot0 pin |ΔVDDx| |VSSX − VSS| VESD(HBM) Variations between different VDD power pins Variations between all the different ground pins(3) Electrostatic discharge voltage (human body model) V mV see Section 6.3.11: Electrical sensitivity characteristics V 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. The following relationship must be respected between VDDA and VDD: VDDA must power on before or at the same time as VDD in the power up sequence. VDDA must be greater than or equal to VDD. 2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values. 3. Include VREF- pin. DS10315 Rev 7 47/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 19. Current characteristics Symbol Ratings Max. ΣIVDD Total current into sum of all VDD power lines (source) 130 ΣIVSS Total current out of sum of all VSS ground lines (sink) -130 IVDD (1) Maximum current into each VDD power line (source) 100 IVSS Maximum current out of each VSS ground line (sink)(1) -100 IIO(PIN) ΣIIO(PIN) Output current sunk by any I/O and control pin Injected current on TC and RST Injected current on TTa pins ΣIINJ(PIN) -25 (2) Total output current sourced by sum of all IOs and control pins(2) Injected current on TT, FT, FTf and B IINJ(PIN) 25 Output current sourced by any I/O and control pin Total output current sunk by sum of all IOs and control pins pins(3) pin(4) (5) Total injected current (sum of all I/O and control pins)(6) Unit 80 mA -80 -5/+0 +/-5 +/-5 +/-25 1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values. 5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note (2) below Table 62. 6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 20. Thermal characteristics Symbol TSTG TJ 48/122 Ratings Storage temperature range Maximum junction temperature DS10315 Rev 7 Value Unit –65 to +150 °C 150 °C STM32F318C8 STM32F318K8 Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 1.65 1.95 1.65 3.6 2.4 3.6 1.8 3.6 1.65 3.6 –0.3 VDD+0.3 -0.3 3.6 TTa I/O pins and POR pin –0.3 VDDA+0.3 FT and FTf I/O(1) –0.3 5.2 BOOT0 0 5.2 WLCSP49 - 408 LQFP48 - 364 UFQFPN32 - 540 –40 85 –40 105 Maximum power dissipation –40 105 Low power dissipation(3) –40 125 6 suffix version –40 105 7 suffix version –40 125 VDD Analog operating voltage (OPAMP and DAC not used) VDDA Analog operating voltage (OPAMP and DAC used) Must have a potential equal to or higher than VDD Analog operating voltage VBAT Backup operating voltage TC I/O TT VIN PD I/O input voltage Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(2) Ambient temperature for 6 suffix version TA Ambient temperature for 7 suffix version TJ Junction temperature range I/O(1) Maximum power dissipation Low power dissipation(3) Unit MHz V V V V mW °C °C °C 1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Table 75: Package thermal characteristics. 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. See Table 75: Package thermal characteristics DS10315 Rev 7 49/122 104 Electrical characteristics 6.3.2 STM32F318C8 STM32F318K8 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22. Operating conditions at power-up / power-down Symbol tVDD tVDDA 50/122 Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate DS10315 Rev 7 Min Max 0 ∞ 20 ∞ 0 ∞ 20 ∞ Unit µs/V STM32F318C8 STM32F318K8 6.3.3 Electrical characteristics Embedded reference voltage The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 21. Table 23. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.20 1.23 1.25 V TS_vrefint ADC sampling time when reading the internal reference voltage - 2.2 - - µs VRERINT Internal reference voltage spread over the temperature range VDD = 1.8 V ±10 mV - - 10(1) mV Temperature coefficient - - - 100 (1) ppm/° C Internal reference voltage temporization - 1.5 2.5 4.5 ms TCoeff TREFINT_RDY (2) 1. Guaranteed by design. 2. Guaranteed by design. Latency between the time when pin NPOR is set to 1 by the application and the time when VREFINTRDYF is set to 1 by the hardware. Table 24. Internal reference voltage calibration values Calibration value name VREFINT_CAL 6.3.4 Description Raw data acquired at temperature of 30 °C VDDA= 3.3 V Memory address 0x1FFF F7BA - 0x1FFF F7BB Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Note: The total current consumption is the sum of IDD and IDDA. DS10315 Rev 7 51/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load) • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz) • Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2 • When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or HSE (8 MHz) in bypass mode. The parameters given in Table 25 to Table 31 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21. Table 25. Typical and maximum current consumption from VDD supply at VDD = 1.8V All peripherals enabled Symbol Parameter Conditions IDD Supply current in Run mode, executing from Flash fHCLK Max @ TA(1) Typ 25°C 85°C 105°C 72 MHz 43.8 47.6 48.9 52.0 64 MHz 39.3 42.6 43.7 48 MHz 30.0 External clock (HSE 32 MHz 20.5 bypass) 24 MHz 15.7 32.3 Unit 25°C 85°C 105°C 24.7 26.3 26.9 28.1 46.2 22.1 23.6 24.1 25.0 33.2 34.8 16.9 18.0 18.4 19.0 21.8 22.5 23.4 11.6 12.3 12.6 12.9 16.6 17.2 17.7 8.9 9.4 9.7 10.0 8 MHz 5.3 5.6 5.8 6.4 3.11 3.24 3.45 3.59 1 MHz 0.99 1.13 1.19 1.36 0.71 0.84 0.88 1.03 64 MHz 36.2 39.0 39.8 41.8 21.9 23.3 23.7 24.5 48 MHz 27.7 Internal 32 MHz 19.0 clock (HSI) 24 MHz 14.6 29.7 30.4 31.6 16.7 17.8 18.1 18.6 20.3 20.7 21.4 11.5 12.2 12.3 12.6 15.5 15.9 16.3 6.0 6.4 6.5 6.7 5.5 5.7 5.8 3.09 3.31 3.38 3.51 8 MHz 52/122 Max @ TA(1) Typ All peripherals disabled 5.2 DS10315 Rev 7 mA STM32F318C8 STM32F318K8 Electrical characteristics Table 25. Typical and maximum current consumption from VDD supply at VDD = 1.8V (continued) All peripherals enabled Symbol Parameter Conditions fHCLK Max @ TA(1) Typ 25°C IDD Supply current in Run mode, executing from RAM 85°C 105°C 72 MHz 43.4 47.2(2) 48.5 51.3(2) 64 MHz 38.9 42.0 43.2 48 MHz 29.4 External clock (HSE 32 MHz 20.0 bypass) 24 MHz 15.1 31.6 IDD Max @ TA(1) Typ 25°C Unit 85°C 105°C 24.3 26.0(2) 26.5 27.6(2) 45.6 21.6 23.1 23.7 24.5 32.6 34.1 16.6 17.6 18.1 18.7 21.3 22.0 22.8 11.1 11.8 12.1 12.4 16.2 16.6 17.1 8.4 8.9 9.2 9.4 8 MHz 4.95 5.31 5.52 5.69 2.73 2.95 3.10 3.24 1 MHz 0.60 0.73 0.83 0.99 0.33 0.40 0.52 0.69 64 MHz 35.6 38.3 39.1 41.0 21.3 22.8 23.2 23.9 48 MHz 27.1 Internal 32 MHz 18.4 clock (HSI) 24 MHz 13.9 29.0 29.6 30.8 16.1 17.2 17.4 17.9 19.6 20.0 20.7 10.8 11.6 11.8 12.0 14.8 15.2 15.6 5.4 5.8 6.0 6.1 8 MHz 4.69 5.02 5.19 5.34 2.60 2.81 2.92 3.05 72 MHz 29.1 31.2 32.4 33.9(2) 5.9 6.3(2) 6.6 6.8(2) 64 MHz 26.0 27.9 28.8 30.1 5.3 5.6 5.9 6.1 48 MHz 16.5 External clock (HSE 32 MHz 13.3 bypass) 24 MHz 10.1 17.6 18.3 19.0 3.37 3.63 3.83 3.98 14.2 14.7 15.2 2.74 2.94 3.10 3.26 10.7 11.2 11.5 2.12 2.30 2.42 2.56 (2) Supply current in Sleep mode, executing from Flash or RAM All peripherals disabled 8 MHz 3.28 3.54 3.76 3.93 0.66 0.77 0.88 1.05 1 MHz 0.40 0.50 0.61 0.78 0.09 0.14 0.27 0.41 64 MHz 22.6 24.2 24.9 25.9 4.89 5.21 5.41 5.58 48 MHz 17.2 Internal 32 MHz 11.7 clock (HSI) 24 MHz 8.9 18.4 18.9 19.5 3.70 3.96 4.12 4.27 12.4 12.8 13.2 2.49 2.66 2.81 2.96 9.4 9.7 10.0 1.28 1.46 1.59 1.68 8 MHz 3.02 3.26 3.42 3.58 0.53 0.64 0.74 0.91 mA mA 1. Guaranteed by characterization results. 2. Data based on characterization results and tested in production with code executing from RAM. DS10315 Rev 7 53/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 26. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter IDDA Conditions (1) HSE bypass Supply current in Run mode, code executing from Flash or RAM HSI clock fHCLK Typ VDDA = 3.6 V Max @ TA(2) 25 °C 85 °C 105 °C Typ Max @ TA(2) 25 °C Unit 85 °C 105 °C 72 MHz 225 248(3) 261 266(3) 248 270(3) 290 296(3) 64 MHz 198 221 234 239 219 241 258 263 48 MHz 149 169 178 182 163 182 196 200 32 MHz 102 120 128 131 112 131 139 142 24 MHz 79 96 101 104 87 104 110 112 8 MHz 3.1 4.1 4.1 5.1 3.1 4.1 4.1 5.1 1 MHz 3.1 4.1 4.1 5.1 3.1 4.1 4.1 5.1 64 MHz 263 287 301 306 292 317 333 339 48 MHz 214 236 248 252 237 260 272 277 32 MHz 167 187 196 199 185 206 216 219 24 MHz 144 164 171 173 161 179 188 191 8 MHz 67 81 85 86 77 91 93 95 µA 1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the PLL is off, IDDA is independent from the frequency. 2. Guaranteed by characterization results. 3. Data based on characterization results and tested in production with code executing from RAM. Table 27. Typical and maximum VDD consumption in Stop mode Symbol IDD Parameter Conditions Typ @VDD (VDD= 1.8 V VDDA = 3.3 V) Max 1.8 V TA = 25°C TA = 85°C TA = 105°C Supply current in Stop mode All oscillators off Unit 3.11 7.3 160 359 µA Table 28. Typical and maximum VDDA consumption in Stop mode 54/122 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 0.70 0.71 0.73 0.76 0.81 0.87 0.94 DS10315 Rev 7 TA = 105°C All oscillators off TA = 85°C Supply current in Stop mode Conditions Max TA = 25°C IDDA Parameter 2.0 V Symbol 1.8 V Typ @VDD (VDD = 1.8 V) 1.6 2.1 2.7 Unit µA STM32F318C8 STM32F318K8 Electrical characteristics Table 29. Typical and maximum current consumption from VBAT supply Symbol Para meter Max. @VBAT= 3.6V(2) Typ.@VBAT Conditions 1.65V 1.8V LSE & RTC ON; “Xtal mode” lower driving capability; Backup LSEDRV[1: domain 0] = '00' IDD_VBAT supply LSE & RTC current ON; “Xtal mode” higher driving capability; LSEDRV[1: 0] = '11' Unit TA (°C) (1) 0.41 2V 0.43 0.46 2.4V 2.7V 0.54 3V 3.3V 3.6V 0.59 0.66 0.74 0.82 25 85 105 - - - µA 0.65 0.68 0.73 0.80 0.87 0.95 1.03 1.14 - - - 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization results. Figure 12. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ‘00’) 1.60 VBAT (μA) 1.40 1.20 1.65V 1.00 1.8V 2V 0.80 2.4V I 0.60 2.7V 0.40 3V 3.3V 0.20 3.6V 0.00 25°C 60°C 85°C TA (°C) 105°C MSxxxxxVy MS3452591 DS10315 Rev 7 55/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Typical current consumption The MCU is placed under the following conditions: • VDD = 1.8 V, VDDA = 3.3 V • All I/O pins available on each package are in analog input configuration • The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON • When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB • PLL is used for frequencies greater than 8 MHz • AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz, 500 kHz and 125 kHz respectively. Table 30. Typical current consumption in Run mode, code with data processing running from Flash Typ Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash IDDA (1) Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 42.6 24.0 64 MHz 38.2 21.6 48 MHz 29.1 16.5 32 MHz 19.9 11.3 24 MHz 15.2 8.6 16 MHz 10.2 5.9 8 MHz 5.2 3.08 4 MHz 2.97 1.79 2 MHz 1.76 1.13 1 MHz 1.16 0.80 500 kHz 0.86 0.63 125 kHz 0.63 0.50 72 MHz 237.3 64 MHz 208.7 48 MHz 154.6 32 MHz 105.1 24 MHz 81.3 16 MHz 57.7 8 MHz 0.87 4 MHz 0.87 2 MHz 0.87 1 MHz 0.87 500 kHz 0.87 125 kHz 0.87 Unit mA µA 1. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. 56/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA (1) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 27.5 5.6 64 MHz 24.5 5.0 48 MHz 18.5 3.82 32 MHz 12.5 2.62 24 MHz 9.4 2.02 16 MHz 6.3 1.42 8 MHz 3.08 0.65 4 MHz 1.93 0.55 2 MHz 1.24 0.48 1 MHz 0.90 0.44 500 kHz 0.73 0.42 125 kHz 0.59 0.41 72 MHz 237.3 64 MHz 208.7 48 MHz 154.6 32 MHz 105.1 24 MHz 81.3 16 MHz 57.7 8 MHz 0.87 4 MHz 0.87 2 MHz 0.87 1 MHz 0.87 500 kHz 0.87 125 kHz 0.87 Unit mA µA 1. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. DS10315 Rev 7 57/122 104 Electrical characteristics STM32F318C8 STM32F318K8 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (seeTable 33: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 58/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 1.8 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 1.8 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 1.8 V Cext = 22 pF C = CINT + CEXT +CS VDD = 1.8 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 1.8 V Cext = 47 pF C = CINT + CEXT+ CS I/O toggling frequency (fSW) Typ 2 MHz 0.10 4 MHz 0.17 8 MHz 0.40 18 MHz 0.78 36 MHz 1.51 48 MHz 2.06 2 MHz 0.14 4 MHz 0.25 8 MHz 0.57 18 MHz 1.16 36 MHz 2.45 48 MHz 3.03 2 MHz 0.19 4 MHz 0.36 8 MHz 0.75 18 MHz 1.59 36 MHz 3.25 2 MHz 0.23 4 MHz 0.45 8 MHz 0.94 18 MHz 1.97 36 MHz 3.62 2 MHz 0.28 4 MHz 0.55 8 MHz 1.15 18 MHz 2.42 Unit mA 1. CS = 5 pF (estimated value). DS10315 Rev 7 59/122 104 Electrical characteristics STM32F318C8 STM32F318K8 On-chip peripheral current consumption The MCU is placed under the following conditions: • all I/O pins are in analog input configuration • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption • 60/122 – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature at 25°C and VDD = 1.8 V, VDDA = 3.3 V. DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 33. Peripheral current consumption Peripheral Typical consumption(1) BusMatrix (2) 11.3 DMA1 6.7 CRC 2.0 GPIOA 8.5 GPIOB 8.3 GPIOC 8.6 GPIOD 1.5 GPIOF 1.0 TSC 4.7 ADC1 APB2-Bridge Unit IDD 15.9 (3) 2.7 SYSCFG 3.2 TIM1 27.6 USART1 21.0 TIM15 14.3 TIM16 10.1 TIM17 10.4 APB1-Bridge (3) 5.8 TIM2 40.7 TIM6 7.4 WWDG 4.6 SPI2 35.2 SPI3 34.2 USART2 13.9 USART3 13.1 I2C1 9.4 I2C2 9.4 PWR 4.5 DAC 8.3 I2C3 10.5 µA/MHz 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. 2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1). 3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus. DS10315 Rev 7 61/122 104 Electrical characteristics 6.3.5 STM32F318C8 STM32F318K8 Wakeup time from low-power mode The wakeup times given in Table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep mode: the wakeup event is WFE. • WKUP1 (PA0) pin is used to wakeup from Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 21. Table 34. Low-power mode wakeup timings Symbol Parameter Typ @ VDD = 1.8 V, VDDA = 3.3 V Max Unit tWUSTOP Wakeup from Stop mode 3.9 4.5 µs tWUSLEEP Wakeup from Sleep mode 6.0 - CPU clock cycles tWUPOR Wakeup from Power Off mode 72.8 103 µs 62/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 6.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 13. Table 35. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 32 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD 15 - - - - 20 tw(HSEH) tw(HSEL) tr(HSE) tf(HSE) OSC_IN high or low - time(1) V ns OSC_IN rise or fall time(1) 1. Guaranteed by design. Figure 13. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tw(HSEL) t THSE MS19214V2 DS10315 Rev 7 63/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 14 Table 36. Low-speed external user clock characteristics Symbol Parameter Conditions fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSEH) tw(LSEL) OSC32_IN high or low time(1) tr(LSE) tf(LSE) Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD V - VSS - 0.3VDD 450 - ns OSC32_IN rise or fall time(1) - - 50 1. Guaranteed by design. Figure 14. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 64/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 37. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 37. HSE oscillator characteristics Symbol fOSC_IN RF Conditions(1) Min(2) Typ Max(2) Unit Oscillator frequency - 4 8 32 MHz Feedback resistor - - 200 - kΩ - - 8.5 VDD=3.3 V, Rm= 30Ω, CL=10 pF@8 MHz - 0.4 - VDD=3.3 V, Rm= 45Ω, CL=10 pF@8 MHz - 0.5 - VDD=3.3 V, Rm= 30Ω, CL= 5 pF@32 MHz - 0.8 - VDD=3.3 V, Rm= 30Ω, CL=10 pF@32 MHz - 1 - VDD=3.3 V, Rm= 30Ω, CL=20 pF@32 MHz - 1.5 - Startup 10 - - mA/V VDD is stabilized - 2 - ms Parameter During startup IDD gm tSU(HSE)(4) HSE current consumption Oscillator transconductance Startup time (3) mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DS10315 Rev 7 65/122 104 Electrical characteristics STM32F318C8 STM32F318K8 For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 15. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. 66/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 38. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol IDD gm tSU(LSE)(3) Parameter LSE current consumption Oscillator transconductance Startup time Conditions(1) Min(2) Typ Max(2) LSEDRV[1:0]=00 lower driving capability - 0.5 0.9 LSEDRV[1:0]=10 medium low driving capability - - 1 LSEDRV[1:0]=01 medium high driving capability - - 1.3 LSEDRV[1:0]=11 higher driving capability - - 1.6 LSEDRV[1:0]=00 lower driving capability 5 - - LSEDRV[1:0]=10 medium low driving capability 8 - - LSEDRV[1:0]=01 medium high driving capability 15 - - LSEDRV[1:0]=11 higher driving capability 25 - - VDD is stabilized - 2 - Unit µA µA/V s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 2. Guaranteed by design. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. DS10315 Rev 7 67/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Figure 16. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: 68/122 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS10315 Rev 7 STM32F318C8 STM32F318K8 6.3.7 Electrical characteristics Internal clock source characteristics The parameters given in Table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21. High-speed internal (HSI) RC oscillator Table 39. HSI oscillator characteristics(1) Symbol Parameter fHSI TRIM DuCy(HSI) Conditions Min Typ Max Unit Frequency - - 8 - MHz HSI user trimming step - - - 1(2) % - (2) Duty cycle Accuracy of the HSI oscillator ACCHSI 45 IDDA(HSI) - 55 % TA = -40 to 105°C -2.8(3) - 3.8(3) TA = -10 to 85°C -1.9(3) - 2.3(3) TA = 0 to 85°C -1.9(3) - 2(3) TA = 0 to 70°C -1.3(3) - 2(3) TA = 0 to 55°C -1(3) - 2(3) -1 - 1 - 2(2) µs 80 100(2) µA TA = 25°C(4) tsu(HSI) (2) HSI oscillator startup time - 1(2) HSI oscillator power consumption - - % 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. Figure 17. HSI oscillator accuracy characterization results for soldered parts 4% MAX MIN 3% 2% 1% 0% -40 -20 0 20 40 60 80 100 T [ºC] 120 A -1% -2% -3% -4% MS30985V4 DS10315 Rev 7 69/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Low-speed internal (LSI) RC oscillator Table 40. LSI oscillator characteristics(1) Symbol fLSI Parameter Min Typ Max Unit 30 40 50 kHz Frequency tsu(LSI)(2) LSI oscillator startup time - - 85 µs IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design. 6.3.8 PLL characteristics The parameters given in Table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21. Table 41. PLL characteristics Value Symbol fPLL_IN fPLL_OUT Parameter Unit Min Typ Max 1(2) - 24(2) MHz PLL input clock duty cycle (2) 40 - 60(2) % PLL multiplier output clock 16(2) - 72 MHz PLL input clock(1) tLOCK PLL lock time - - 200(2) µs Jitter Cycle-to-cycle jitter - - 300(2) ps 1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design. 70/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 6.3.9 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 42. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs Page (2 KB) erase time TA = –40 to +105 °C 20 - 40 ms tME Mass erase time TA = –40 to +105 °C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design. Table 43. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 (2) 1 kcycle 10 at TA = 105 °C kcycles(2) at TA = 55 °C 10 Unit kcycles Years 20 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS10315 Rev 7 71/122 104 Electrical characteristics 6.3.10 STM32F318C8 STM32F318K8 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 44. They are based on the EMS levels and classes defined in application note AN1709. Table 44. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 1.8 V, LQFP64, TA = +25°C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 1.8 V, LQFP64, TA = +25°C, fHCLK = 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 72/122 • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 45. EMI characteristics Symbol Parameter SEMI 6.3.11 Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/72 MHz 0.1 to 30 MHz VDD = 1.8 V, TA = 25 °C, 30 to 130 MHz LQFP64 package Peak level compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 5 10 dBµV 25 4 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 46. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming (charge device model) to ANSI/ESD STM5.3.1 Maximum Unit value(1) Packages Class All 2 2000 WLCSP49 C3 250 All other C4 500 V V 1. Guaranteed by characterization results. DS10315 Rev 7 73/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 47. Electrical sensitivities Symbol LU 6.3.12 Parameter Conditions Class TA = +105 °C conforming to JESD78A Static latch-up class 2 level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The test results are given in Table 48 Table 48. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 -0 NA(1) Injected current on PC0 pin (TTa pin) -0 +5 Injected current PC0, PC1, PC2, PC3, PA0, PA1, PA2, PA3, PA4, PA6, PA7, PC4, PB0, PB10, PB11, PB13 with induced leakage current on other pins from this group less than -100 µA or more than +100 µA -5 +5 Injected current on any other TT, FT, FTf and NPOR pins -5 NA(1) Injected current on all other TC, TTa and RESET pins -5 +5 1. Injection is not possible. 74/122 DS10315 Rev 7 Unit mA STM32F318C8 STM32F318K8 Electrical characteristics Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.13 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 21. All I/Os are CMOS and TTL compliant. Table 49. I/O static characteristics Symbol VIL Parameter Low level input voltage Conditions Min Typ Max TTa and TT I/O - - 0.3 VDD + 0.07 (1) FT and FTf I/O - - 0.475 VDD -0.2 (1) NPOR I/O input low-level voltage - - 0.475 VDDA -0.2 BOOT0 I/O - - 0.3 VDD – 0.3 (1) All I/Os except BOOT0 - - 0.3 VDD (2) TTa and TT I/O 0.445 VDD+0.398 (1) - - - - FT and FTf I/O VIH High level input voltage 0.5 VDD+0.2 NPOR I/O input high-level voltage 0.5 VDDA+0.2 - - BOOT0 0.2 VDD+0.95 (1) - - All I/Os except BOOT0 0.7 VDD (2) - TC and TTa I/O Vhys Ilkg RPU Schmitt trigger hysteresis (1) FT, FTf I/O and NPOR pin - 200 - 100 (1) - (1) - - 300 TC, FT and FTf I/O TTa I/O in digital mode VSS ≤VIN ≤VDD - - ±0.1 TTa I/O in digital mode VDD ≤VIN ≤VDDA - - 1 TTa I/O in analog mode VSS ≤VIN ≤VDDA - - ±0.2 FT and FTf I/O(4) VDD ≤VIN ≤5 V - - 10 - POR VDDA ≤VIN ≤5 V - - 10 Weak pull-up equivalent resistor(5) VIN = VSS 25 40 55 DS10315 Rev 7 V V (1) BOOT0 Input leakage current (3) Unit mV µA kΩ 75/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 49. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit RPD Weak pull-down equivalent resistor(5) VIN = VDD 25 40 55 kΩ CIO I/O pin capacitance - - 5 - pF 1. Data based on design simulation 2. Tested in production. 3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 48: I/O current injection susceptibility. 4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os. Figure 18. TC and TTa I/O input characteristics VIL/VIH (V) VIHmin 1.3 Tested in production ments VIHmin CMOS standard require 98 +0.3 ulations 5V DD 0.44 sign sim = V IHmin d on de Base = 0.7VDD 1.1 s 0.07 ulation D+ 0.3V D sign sim e nd ed o Area not determined 0.9 = max V IL Bas 0.7 VILmax 0.5 Tested in production CMOS standard requirements VILmax = 0.3VDD VDD (V) 1.8 1.65 1.95 MS31122V3 Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics VIL/VIH (V) VIHmin 1.3 Tested in production V = 0.7VDD CMOS standard requirements IHmin ions 0.2 V DD+ simulat n = 0.5 V IHmin on desig d Base 1.1 0.9 - 0.2 tions 75V DD imula = 0.4 design s d on Base Area not determined V ILmax 0.7 VILmax 0.5 CMOS standard requirements VILmax = 0.3VDD Tested in production VDD (V) 1.65 1.8 1.95 MS31123V4 76/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 19). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 19). Output voltage levels Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 21. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL compliant. Table 50. Output voltage characteristics Symbol Parameter Conditions Min Max VOL(1) Output low level voltage for an I/O pin IIO = +4 mA 1.65 V < VDD < 1.95 V - 0.4 VOH(2) Output high level voltage for an I/O pin IIO = -4 mA 1.65 V < VDD < 1.95 V VDD–0.4 - - 0.4 VOLFM+(1)(3) Output low level voltage for an FTf I/O pin in IIO = +10 mA FM+ mode VDD = 1.65 V to 1.95 V Unit V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 19 and the sum of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN). 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 19 and the sum of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN). 3. Guaranteed by design. DS10315 Rev 7 77/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 20 and Table 51, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 21. Table 51. I/O AC characteristics(1) OSPEEDRy [1:0] value(1) x0 01 11 FM+ configuration(4) - Symbol Parameter fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Conditions Min Max Unit CL = 50 pF, VDD = 1.65 V to 1.95 V - 1 MHz - 125(3) - (3) CL = 50 pF, VDD = 1.65 V to 1.95 V CL = 50 pF, VDD = 1.65 V to 1.95 V ns 125 - 4(3) - 62.5(3) MHz CL = 50 pF, VDD = 1.65 V to 1.95 V ns (3) - 25 CL = 50 pF, VDD = 1.65 V to 1.95 V - 10(3) Output high to low level fall time CL = 50 pF, VDD = 1.65 V to 1.95 V - 25(3) tr(IO)out Output low to high level rise time CL = 50 pF, VDD = 1.65 V to 1.95 V - 25(3) fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller MHz ns CL = 50 pF, VDD = 1.65 V to 1.95 V - 0.5(3)(4) MHz - 16(4) - 44(3)(4) 10 -‘ ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0366 reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 20. 3. Guaranteed by design. 4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F318C8 STM32F318K8 reference manual RM0366 for a description of FM+ I/O mode configuration. 78/122 DS10315 Rev 7 ns STM32F318C8 STM32F318K8 Electrical characteristics Figure 20. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% External output on CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by CL (see note 1). MS34942V1 1. See Table 51: I/O AC characteristics. 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49). Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 21. Table 52. NRST pin characteristics Symbol Parameter VIL(NRST)(1) NRST Input low level voltage Conditions Min Typ Max - - - 0.3VDD+ 0.07(1) - - Unit V VIH(NRST)(1) NRST Input high level voltage - 0.445VDD+ 0.398(1) Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 25 40 55 kΩ ns ns RPU VF(NRST)(1) VNF(NRST)(1) Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse - - - 100(1) - 700(1) - - 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). DS10315 Rev 7 79/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Figure 21. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF(3) MS19878V4 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 52. Otherwise the reset will not be taken into account by the device. 3. The user must place the external capacitor on NRST as close as possible to the chip. 6.3.15 NPOR pin characteristics The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, Rpu (see Table 53) connected to VDDA supply. Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under ambient temperature and VDDA supply voltage conditions summarized in Table 21. Table 53. NPOR pin characteristics Symbol(1) Parameter Conditions Min Typ Max - - 0.475 VDDA - 0.2 Unit VIL(NPOR) NPOR Input low level voltage - VIH(NPOR) NPOR Input low level voltage - 0.5 VDDA +0.2 - - Vhys(NPOR) NPOR Schmitt trigger voltage hysteresis - - 100 - mV 25 40 55 kΩ RPU V Weak pull-up equivalent VIN = VSS resistor(2) 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 80/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 6.3.16 Electrical characteristics Timer characteristics The parameters given in Table 54 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 54. TIMx(1)(2) characteristics Symbol tres(TIM) Parameter Timer resolution time Timer external clock frequency on CH1 to CH4 fEXT ResTIM tCOUNTER tMAX_COUNT Timer resolution 16-bit counter clock period Maximum possible count with 32-bit counter Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns fTIMxCLK = 144 MHz, x = 1, 15,16, 17 6.95 - ns - 0 fTIMxCLK/2 MHz fTIMxCLK = 72 MHz 0 36 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 µs fTIMxCLK = 144 MHz, x= 1/15/16/17 0.0069 455 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.65 s fTIMxCLK = 144 MHz, x= 1/15/16/17 - 29.825 s bit 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM15, TIM16 and TIM17 timers. 2. Guaranteed by design. Table 55. IWDG min/max timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. DS10315 Rev 7 81/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 56. WWDG min-max timeout value @72 MHz (PCLK)(1) Prescaler WDGTB Min timeout value Max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 1. Guaranteed by design. 82/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 6.3.17 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.13: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 57. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered DS10315 Rev 7 83/122 104 Electrical characteristics STM32F318C8 STM32F318K8 SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 58 for SPI or in Table 59 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 21. Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 58. SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Master mode - - 18 Slave mode - - 18 Slave mode transmitter/full duplex - - 13(2) fSCK 1/tc(SCK) SPI clock frequency tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpcl k - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpcl k - - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 Tpclk2 Tpclk Tpclk+ 2 Master mode 0 - - Slave mode 1 - - Master mode 6.5 - - Slave mode 2.5 - - tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ta(SO) Data output access time Slave mode 8 - 40 tdis(SO) Data output disable time Slave mode 8 - 14 Slave mode - 23 38 Master mode - 1.5 4 Slave mode 9.5 - - Master mode 0 - - tv(SO) tv(MO) th(SO) th(MO) Data output valid time Data output hold time Unit MHz ns 1. Guaranteed by characterization results. 2. 2.Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. 84/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Figure 22. SPI timing diagram - slave mode and CPHA = 0 SCK input NSS input MISO OUTPUT MSB OUT BIT6 OUT MSB IN BIT1 IN LSB OUT (SI) MOSI INPUT LSB IN (SI) Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. DS10315 Rev 7 85/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Figure 24. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Table 59. I2S characteristics(1) Symbol Parameter fMCK I2S Main clock output fCK I2S clock frequency DCK I2S clock frequency duty cycle 86/122 Conditions - Min Max 256 x 8K 256xFs Unit (2) Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 Slave receiver DS10315 Rev 7 MHz MHz % STM32F318C8 STM32F318K8 Electrical characteristics Table 59. I2S characteristics(1) (continued) Symbol Parameter Conditions tv(WS) WS valid time Master mode - 20 th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 0 - th(WS) WS hold time Slave mode 4 - Master receiver 1 - Slave receiver 1 - Master receiver 8 - Slave receiver 2.5 - Slave transmitter (after enable edge) - 50 Master transmitter (after enable edge) - 22 Slave transmitter (after enable edge) 8 - Master transmitter (after enable edge) 1 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Data input setup time Data input hold time tv(SD_ST) tv(SD_MT) Data output valid time th(SD_ST) th(SD_MT) Data output hold time Min Max Unit ns 1. Guaranteed by characterization results. 2. 256xFs maximum is 36 MHz (APB1 Maximum frequency) Note: Refer to RM0366 Reference Manual I2S Section for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value. Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition. DS10315 Rev 7 87/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Figure 25. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 26. I2S master timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 3. 88/122 DS10315 Rev 7 ADC characteristics Unless otherwise specified, the parameters given in Table 60 to Table 62 are guaranteed by design, with conditions summarized in Table 21. Table 60. ADC characteristics Symbol VDDA IDDA DS10315 Rev 7 fADC fS(1) Analog supply voltage for ADC ADC current consumption (see Figure 27) ADC clock frequency Sampling rate External trigger frequency Conditions Min Typ Max Unit - 1.8 - 3.6 V Single-ended mode, 5 MSPS - 1011.3 1172.0 Single-ended mode, 1 MSPS - 214.7 322.3 Single-ended mode, 200 KSPS - 54.7 81.1 Differential mode, 5 MSPS - 1061.5 1243.6 Differential mode, 1 MSPS - 246.6 337.6 Differential mode, 200 KSPS - 56.4 83.0 - 0.14 - 72 Resolution = 12 bits, Fast Channel 0.01 - 5.14 Resolution = 10 bits, Fast Channel 0.012 - 6 Resolution = 8 bits, Fast Channel 0.014 - 7.2 Resolution = 6 bits, Fast Channel 0.0175 - 9 fADC = 72 MHz Resolution = 12 bits - - 5.14 MHz Resolution = 12 bits - - 14 1/fADC µA MHz MSPS 89/122 VAIN Conversion voltage range - 0 - VDDA V RAIN(1) External input impedance - - - 100 kΩ Electrical characteristics fTRIG(1) Parameter STM32F318C8 STM32F318K8 6.3.18 Symbol CADC(1) Parameter Internal sample and hold capacitor tCAL(1) Calibration time tlatr(1) Trigger conversion latency Regular and injected channels without conversion abort Conditions Min Typ Max Unit - - 5 - pF fADC = 72 MHz 1.56 µs - 112 1/fADC CKMODE = 00 1.5 2 2.5 1/fADC CKMODE = 01 - - 2 1/fADC CKMODE = 10 - - 2.25 1/fADC CKMODE = 11 - - 2.125 1/fADC CKMODE = 00 2.5 3 3.5 1/fADC CKMODE = 01 - - 3 1/fADC CKMODE = 10 - - 3.25 1/fADC CKMODE = 11 - - 3.125 1/fADC fADC = 72 MHz 0.021 - 8.35 µs - 1.5 - 601.5 1/fADC ADC Voltage Regulator Start-up time - - - 10 µs tSTAB(1) Power-up time - tCONV(1) Total conversion time (including sampling time) tlatrinj(1) DS10315 Rev 7 tS(1) (1) TADCVREG_STUP Sampling time Common mode input signal 1. Data guaranteed by design. fADC = 72 MHz Resolution = 12 bits Resolution = 12 bits ADC differential mode conversion cycle 1 0.19 - 8.52 14 to 614 (tS for sampling + 12.5 for successive approximation) (VSSA + VREF+)/2 - 0.18 (VSSA + VREF+)/2 (VSSA + VREF+)/2 + 0.18 µs 1/fADC V STM32F318C8 STM32F318K8 CMIR(1) Trigger conversion latency Injected channels aborting a regular conversion Electrical characteristics 90/122 Table 60. ADC characteristics (continued) STM32F318C8 STM32F318K8 Electrical characteristics Figure 27 illustrates the ADC current consumption as per the clock frequency in singleended and differential modes. ADC current consumption (μA) Figure 27. ADC typical current consumption in single-ended and differential modes Clock frequency (MSPS) MS34994V1 Table 61. Maximum ADC RAIN (1) Resolution 12 bits Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz 1.5 RAIN max (kΩ) Fast channels(2) Slow channels Other channels(3) 20.83 0.018 NA NA 2.5 34.72 0.150 NA 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 DS10315 Rev 7 91/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 61. Maximum ADC RAIN (1) (continued) Resolution Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz 1.5 10 bits 8 bits 6 bits RAIN max (kΩ) Fast channels(2) Slow channels Other channels(3) 20.83 0.082 NA NA 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 1.5 20.83 0.150 NA 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. Guaranteed by characterization results. 2. All fast channels, expect channel on PA6. 3. Channel available on PA6. 92/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 62. ADC accuracy - limited test conditions(1)(2) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (4) SINAD (4) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min Conditions ADC clock freq. ≤ 72 MHz Sampling freq. ≤ 5 Msps VDDA = 3.3 V 25°C Single ended Differential Single ended Differential Single ended Differential Single ended Differential DS10315 Rev 7 Max (3) Typ Fast channel 5.1 Ms - ±4 ±4.5 Slow channel 4.8 Ms - ±5.5 ±6 Fast channel 5.1 Ms - ±3.5 ±4 Slow channel 4.8 Ms - ±3.5 ±4 Fast channel 5.1 Ms - ±2 ±2 Slow channel 4.8 Ms - ±1.5 ±2 Fast channel 5.1 Ms - ±1.5 ±2 Slow channel 4.8 Ms - ±1.5 ±2 Fast channel 5.1 Ms - ±3 ±4 Slow channel 4.8 Ms - ±5 ±5.5 Fast channel 5.1 Ms - ±3 ±3 Slow channel 4.8 Ms - ±3 ±3.5 Fast channel 5.1 Ms - ±1 ±1 Slow channel 4.8 Ms - ±1 ±1 Fast channel 5.1 Ms - ±1 ±1 Slow channel 4.8 Ms - ±1 ±1 Fast channel 5.1 Ms - ±1.5 ±2 Slow channel 4.8 Ms - ±2 ±3 Fast channel 5.1 Ms - ±1.5 ±1.5 Slow channel 4.8 Ms - ±1.5 (3) Unit LSB ±2 Fast channel 5.1 Ms 10.8 10.8 - Slow channel 4.8 Ms 10.8 10.8 - Fast channel 5.1 Ms 11.2 11.3 - Slow channel 4.8 Ms 11.2 11.3 - Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - bit dB 93/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 62. ADC accuracy - limited test conditions(1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. ≤ 72 MHz Sampling freq ≤ 5 Msps VDDA = 3.3 V 25°C Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.1 Ms - -80 -80 Slow channel 4.8 Ms - -78 -77 Fast channel 5.1 Ms - -83 -82 Slow channel 4.8 Ms - -81 -80 (3) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC accuracy. 3. Guaranteed by characterization results. 4. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal. 94/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 63. ADC accuracy (1)(2)(3) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (5) SINAD (5) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min(4) Max Fast channel 5.1 Ms - ±6.5 Slow channel 4.8 Ms - ±6.5 Fast channel 5.1 Ms - ±4 Slow channel 4.8 Ms - ±4.5 Fast channel 5.1 Ms - ±3 Slow channel 4.8 Ms - ±3 Fast channel 5.1 Ms - ±2.5 Slow channel 4.8 Ms - ±2.5 Fast channel 5.1 Ms - ±6 Slow channel 4.8 Ms - ±6 Fast channel 5.1 Ms - ±3.5 Slow channel 4.8 Ms - ±4 Fast channel 5.1 Ms - ±1.5 Slow channel 4.8 Ms - ±1.5 Fast channel 5.1 Ms - ±1.5 Slow channel 4.8 Ms - ±1.5 Fast channel 5.1 Ms - ±3 Slow channel 4.8 Ms - ±3.5 Fast channel 5.1 Ms - ±2 Slow channel 4.8 Ms - ±2.5 Fast channel 5.1 Ms 10.4 - Slow channel 4.8 Ms 10.4 - Fast channel 5.1 Ms 10.8 - Slow channel 4.8 Ms 10.8 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Conditions ADC clock freq. ≤ 72 MHz, Sampling freq. ≤ 5 Msps 1.8 V ≤ VDDA ≤ 3.6 V Single ended Differential Single ended Differential Single ended Differential Single ended Differential DS10315 Rev 7 (4) Unit LSB bits dB 95/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 63. ADC accuracy (1)(2)(3) (continued) Symbol Parameter Single ended SNR(5) THD(5) Signal-tonoise ratio Total harmonic distortion Min(4) Max Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -75 Slow channel 4.8 Ms - -75 Fast channel 5.1 Ms - -79 Slow channel 4.8 Ms - -78 Conditions ADC clock freq. ≤ 72 MHz, Sampling freq ≤ 5 Msps, 1.8 V ≤ VDDA ≤ 3.6 V Differential Single ended Differential (4) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Guaranteed by characterization results. 5. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal. Table 64. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(3) Fast channel ±2.5 ±5 Slow channel ±3.5 ±5 Fast channel ±1 ±2.5 ±1.5 ±2.5 ±2 ±3 Test conditions Slow channel ADC Freq ≤ 72 MHz Fast channel Sampling Freq ≤ 1MSPS 2.4 V ≤ VDDA = VREF+ ≤ 3.6 V Slow channel Single-ended mode Fast channel ±3 ±4 ±0.7 ±2 Slow channel ±0.7 ±2 Fast channel ±1 ±3 Slow channel ±1.2 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.13: I/O port characteristics does not affect the ADC accuracy. 3. Guaranteed by characterization results. 96/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Figure 28. ADC accuracy characteristics 1LSBIDEAL = VDDA 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL =Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 L SBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA MS34980V1 Figure 29. Typical connection diagram using the ADC VDD Sample and hold ADC converter VT 0.6 V RAIN (1) VAIN RADC AINx Cparasitic VT 0.6 V 12-bit converter IL ± 1 μA CADC MS19881V3 1. Refer to Table 60 for the values of RAIN. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DS10315 Rev 7 97/122 104 Electrical characteristics 6.3.19 STM32F318C8 STM32F318K8 DAC electrical specifications Table 65. DAC characteristics Symbol VDDA RLOAD(1) Parameter Conditions Min Typ Max Unit 2.4 - 3.6 V Connected to VSSA 5 - - kΩ Connected to VDDA 25 - - - Analog supply voltage DAC output buffer ON Resistive load DAC output buffer ON Output impedance DAC output buffer ON - - 15 kΩ Capacitive load DAC output buffer ON - - 50 pF 0.2 - VDDA – 0.2 V DAC output buffer OFF - 0.5 VDDA 1LSB mV DAC DC current consumption in quiescent mode(2) With no load, middle code (0x800) on the input. - - 380 µA With no load, worst code (0xF1C) on the input. - - 480 µA Given for a 10-bit input code - - ±0.5 LSB DNL(3) Differential non linearity Difference between two consecutive code1LSB) Given for a 12-bit input code - - ±2 LSB - - ±1 LSB INL(3) Integral non linearity Given for a 10-bit input code (difference between measured value at Code i and the value Given for a 12-bit input code at Code i on a line drawn between Code 0 and last Code 4095) - - ±4 LSB Offset error (difference between measured Given for a 10-bit input code at VDDA = 3.6 V value at Code (0x800) and the ideal value = Given for a 12-bit input code at VDDA = 3.6 V VDDA/2) - - ±10 mV - - ±3 LSB - - ±12 LSB - - ±0.5 % - 3 4 µs RO(1) CLOAD (1) Corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V VDAC_OUT Voltage on DAC_OUT and (0x155) and (0xEAB) at VDDA = 2.4 V (1) DAC output buffer ON. output IDDA(3) Offset(3) Gain error(3) Gain error Given for a 12-bit input code Settling time (full scale: for a 12-bit input code transition CLOAD ≤50 pF, tSETTLING(3) between the lowest and the highest input RLOAD ≥ 5 kΩ codes when DAC_OUT reaches 98/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Electrical characteristics Table 65. DAC characteristics (continued) Symbol Min Typ Max Unit CLOAD ≤50 pF, RLOAD ≥ 5 kΩ - - 1 MS/s Wakeup time from off state (Setting the ENx CLOAD ≤50 pF, tWAKEUP(3) bit in the DAC Control RLOAD ≥ 5 kΩ register) - 6.5 10 µs Power supply rejection C LOAD = 50 pF, PSRR+ (1) ratio (to VDDA) (static No RLOAD ≥ 5 kΩ, DC measurement - –67 –40 dB Update rate(3) Parameter Conditions Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) 1. Guaranteed by design. 2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved. 3. Guaranteed by characterization results. Figure 30. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer (1) RL 12-bit digital to analog converter DAC_OUTx CL MS39009V1 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.20 Comparator characteristics Table 66. Comparator characteristics(1)(2) Symbol VDDA Parameter Analog supply voltage Conditions VREFINT scaler not in use VREFINT scaler in use Min. Typ. Max. 1.8 - 3.6 2 - 3.6 VIN Comparator input voltage range - 0 - VDDA VBG Scaler input voltage - - VREFINIT - VSC Scaler offset voltage - - ±5 ±10 DS10315 Rev 7 Unit V V mV 99/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 66. Comparator characteristics(1)(2) (continued) Symbol tS_SC tSTART Parameter Min. Typ. Max. Unit - - 1(3) s - - 0.2 ms VDDA ≥ 2.7 V - - 4 VDDA < 2.7 V - - 10 Propagation delay for 200 mV step with 100 mV overdrive VDDA ≥ 2.7 V - 25 28 - 28 30 Propagation delay for full range step with 100 mV overdrive VDDA ≥ 2.7 V - 32 35 - 35 40 - ±5 ±10 - - ±25 - - 3 mV - 400 600 µA VREFINT scaler activation after VREFINT scaler startup time device power on from power down Next activations Comparator startup time VDDA < 2.7 V Comparator offset error TVOFFSET Total offset variation IDD(COMP) COMP current consumption VDDA < 2.7 V VDDA ≥ 2.7 V VDDA < 2.7 V Full temperature range - 1. Guaranteed by design. 2. The comparators do not have built-in hysteresis. 3. For more details and conditions, see Figure 31: Maximum VREFINT scaler startup time from power down. Figure 31. Maximum VREFINT scaler startup time from power down 100/122 µs ns tD VOFFSET Conditions DS10315 Rev 7 mV STM32F318C8 STM32F318K8 6.3.21 Electrical characteristics Operational amplifier characteristics Table 67. Operational amplifier characteristics(1) Symbol Parameter Condition Min Typ Max Unit VDDA Analog supply voltage - 2.4 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25°C, No Load on output. - - 4 All voltage/Temp. - - 6 25°C, No Load on output. - - 1.6 All voltage/Temp. - - 3 Input offset voltage drift - - 5 - µV/°C ILOAD Drive current - - - 500 µA IDDOPAMP Consumption - 690 1450 µA - 90 - dB 73 117 - dB VIOFFSET Input offset voltage Maximum calibration range After offset calibration ΔVIOFFSET No load, quiescent mode CMRR Common mode rejection ratio PSRR Power supply rejection ratio GBW Bandwidth - - 8.2 - MHz SR Slew rate - - 4.7 - V/µs RLOAD Resistive load - 4 - - kΩ CLOAD Capacitive load - - - 50 pF Rload = min, Input at VDDA. VDDA-100 - - Rload = 20K, Input at VDDA. VDDA-20 - - Rload = min, input at 0V - - 100 Rload = 20K, input at 0V. - - 20 VOHSAT VOLSAT ϕm tOFFTRIM tWAKEUP tS_OPAM_VOUT High saturation voltage(2) Low saturation voltage(2) - mV DC mV Phase margin - - 62 - ° Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - - - 2 ms - 2.8 5 µs 400 - - ns Wake up time from OFF state. CLOAD ≤50 pf, RLOAD ≥ 4 kΩ, Follower configuration ADC sampling time when reading the OPAMP output DS10315 Rev 7 101/122 104 Electrical characteristics STM32F318C8 STM32F318K8 Table 67. Operational amplifier characteristics(1) (continued) Symbol PGA gain Rnetwork Parameter Condition PGA BW Vn Typ Max - 2 - - 4 - - 8 - - 16 - Gain=2 - 5.4/5.4 - Gain=4 - 16.2/5.4 - Gain=8 - 37.8/5.4 - Gain=16 - 40.5/2.7 - - -1% - 1% % - - - ±0.2(4) µA PGA Gain = 2, Cload = 50pF, Rload = 4 KΩ - 4 - PGA Gain = 4, Cload = 50pF, Rload = 4 KΩ - 2 - PGA Gain = 8, Cload = 50pF, Rload = 4 KΩ - 1 - PGA Gain = 16, Cload = 50pF, Rload = 4 KΩ - 0.5 - @ 1KHz, Output loaded with 4 KΩ - 109 - Non inverting gain value - R2/R1 internal resistance values in PGA mode (3) PGA gain error PGA gain error Ibias Min OPAMP input bias current PGA bandwidth for different non inverting gain Voltage noise density @ 10KHz, Output loaded with 4 KΩ 1. Guaranteed by design. 2. The saturation voltage can also be limited by the ILOAD (drive current). 3. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between OPAMP inverting input and ground. The PGA gain =1+R2/R1 4. Mostly TTa I/O leakage, when used in analog mode. 102/122 DS10315 Rev 7 Unit - kΩ MHz - 43 - nV ----------Hz STM32F318C8 STM32F318K8 Electrical characteristics Figure 32. OPAMP Voltage Noise versus Frequency DS10315 Rev 7 103/122 104 Electrical characteristics 6.3.22 STM32F318C8 STM32F318K8 Temperature sensor characteristics Table 68. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V 4 - 10 µs 2.2 - - µs VSENSE linearity with temperature (1) Avg_Slope V25 tSTART(1) Startup time TS_temp(1)(2) ADC sampling time when reading the temperature 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. Table 69. Temperature sensor calibration values Calibration value name 6.3.23 Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at temperature of 110 °C VDDA= 3.3 V 0x1FFF F7C2 - 0x1FFF F7C3 VBAT monitoring characteristics Table 70. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 2 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1mV accuracy 2.2 - - µs Er (1) TS_vbat(1)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 104/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS10315 Rev 7 105/122 117 Package information 7.1 STM32F318C8 STM32F318K8 WLCSP49 package information Figure 33. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package outline e1 bbb Z F A1 ball location A1 G Detail A e2 E e e A D A2 Bottom view Bump side Side view A2 A3 b Bump Front view A1 eee Z 49x E Note 2 A1 Orientation reference Seating plane Note 1 (4x) D Top view Wafer back side 1. Drawing is not to scale. 106/122 Detail A (rotated 90 ) DS10315 Rev 7 A0XJ_ME_V1 STM32F318C8 STM32F318K8 Package information Table 71. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.382 3.417 3.452 0.1331 0.1345 0.1359 E 3.116 3.151 3.186 0.1227 0.1241 0.1254 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - F - 0.5085 - - 0.0200 - G - 0.3755 - - 0.0148 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 34. WLCSP49 - 49-pin, 3.417 x 3.151 mm, 0.4 mm pitch wafer level chip scale package recommended footprint Dpad Dsm DS10315 Rev 7 MS18965V2 107/122 117 Package information STM32F318C8 STM32F318K8 Table 72. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 260 µm max. (circular) Dpad 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. WLCSP49 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 35. WLCSP49 marking example (package top view) Product identification (1) F318C86 Date code Y WW R Revision code MS36422V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 108/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 7.2 Package information LQFP48 package information This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package Note: See list of notes in the notes section. Figure 36. LQFP48 - Outline(15) BOTTOM VIEW 4x N/4 TIPS aaa C A-B D   (2) R1 R2 N TI O (6) B SE C D 1/4 BB H GAUGE PLANE 0.25 E 1/4 S B bbb H A-B D 4x  0.05 A (13) (N – 4)x e C A2 A1 (12) ddd b (10) (3) A (1) (11) SECTION A-A (4) D1 D (3) N 1 2 3 (L1) ccc C C A-B D D (2) (5) L b (9) (11) WITH PLATING E 1/4 B (3) (6) c D 1/4 E1 E (2) (5) A c1 (11) (11) (4) A b1 (Section A-A) (11) BASE METAL SECTION B-B TOP VIEW 5B_LQFP48_ME_V1 DS10315 Rev 7 109/122 117 Package information STM32F318C8 STM32F318K8 Table 73. LQFP48 - Mechanical data inches(14) millimeters Symbol A A1 (12) A2 Min Typ Max Min Typ Max - - 1.60 - - 0.0630 0.05 - 0.15 0.0020 - 0.0059 1.35 1.40 1.45 0.0531 0.0551 0.0571 (9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106 (11) 0.17 0.20 0.23 0.0067 0.0079 0.0090 0.09 - 0.20 0.0035 - 0.0079 0.09 - 0.16 0.0035 - 0.0063 b b1 (11) c c1(11) (4) 9.00 BSC 0.3543 BSC (2)(5) D 7.00 BSC 0.2756 BSC E(4) 9.00 BSC 0.3543 BSC E1(2)(5) 7.00 BSC 0.2756 BSC e 0.50 BSC 0.1970 BSC D1 L 0.45 L1 0.60 0.75 1.00 REF 0.0236 0.0295 0.0394 REF N(13) 48 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1)(7) 0.20 0.0079 bbb(1)(7) 0.20 0.0079 (1)(7) 0.08 0.0031 (1)(7) 0.08 0.0031 ccc ddd 110/122 0.0177 DS10315 Rev 7 STM32F318C8 STM32F318K8 Package information Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. Figure 37. LQFP48 - Recommended footprint 0.50 1.20 36 25 37 24 0.30 0.20 9.70 7.30 48 13 12 1 5.80 9.70 5B_LQFP48_FP_V1 1. Dimensions are expressed in millimeters. DS10315 Rev 7 111/122 117 Package information STM32F318C8 STM32F318K8 LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 38. LQFP48 marking example (package top view) Product identification (1) STM32F 318C8T6 Date code Y WW Pin 1 identification Revision code R MS38391V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 112/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 7.3 Package information UFQFPN32 package information This UFQFPN is a 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package. Figure 39. UFQFPN32 - Outline D A e A1 A3 ddd C C SEATINGPLANE D1 b e E2 b E1 E 1 L 32 D2 PIN 1 Identifier L A0B8_ME_V3 1. Drawing is not to scale. Note: There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. DS10315 Rev 7 113/122 117 Package information STM32F318C8 STM32F318K8 Table 74. UFQFPN32 - Mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.000 0.0007 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 (2) D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 (2) E 4.900 5.000 5.100 0.1929 0.1969 0.2008 E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm. Figure 40. UFQFPN32 - Recommended footprint 5.30 3.80 25 32 1 0.60 24 3.45 3.80 5.30 3.45 0.50 0.30 8 17 16 9 3.80 1. Dimensions are expressed in millimeters. 114/122 DS10315 Rev 7 0.75 A0B8_FP_V2 STM32F318C8 STM32F318K8 Package information UFQFPN32 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 41. UFQFPN32 marking example (package top view) Product identification (1) F318K8 Date code Y WW R Revision code Pin 1 identifier MS36421V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS10315 Rev 7 115/122 117 Package information 7.4 STM32F318C8 STM32F318K8 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 21: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 75. Package thermal characteristics Symbol ΘJA 7.4.1 Parameter Value Thermal resistance junction-ambient WCSP49 - 3.4 x 3.4 mm 49 Thermal resistance junction-ambient LQFP48 - 7 × 7 mm 55 Thermal resistance junction-ambient UFQPFN32 - 5 x 5 mm 37 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F318C8 STM32F318K8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. 116/122 DS10315 Rev 7 STM32F318C8 STM32F318K8 Package information The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 3 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 2 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW This gives: PINTmax = 175 mW and PIOmax = 61.6 mW: PDmax = 175 + 61.6 = 236.6 mW Thus: PDmax = 236.6 mW Using the values obtained in Table 75 TJmax is calculated as follows: – For WLCSP49, 49°C/W TJmax = 82 °C + (49°C/W x 236.6 mW) = 82°C + 11.6°C = 93.6°C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Ordering information). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 9 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 9 × 8 mA × 0.4 V = 28.8 mW This gives: PINTmax = 70 mW and PIOmax = 28.8 mW: PDmax = 70 + 28.8 = 98.8 mW Thus: PDmax = 98.8 mW Using the values obtained in Table 75 TJmax is calculated as follows: – For WLCSP49, 49°C/W TJmax = 115 °C + (49°C/W x 98.8 mW) = 115°C + 4.8°C = 119.8°C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information). DS10315 Rev 7 117/122 117 Ordering information 8 STM32F318C8 STM32F318K8 Ordering information Table 76. Ordering information scheme Example: STM32 F Device family STM32 = Arm®-based 32-bit microcontroller Product type F = general-purpose Device subfamily 318 = STM32F318xx, 1.65 to 1.94 V operating voltage Pin count K = 32 pins C = 48 or 49 pins Flash memory size 8 = 64 Kbytes of Flash memory Package T = LQFP Y= WLCSP U= UFQFPN Temperature range 6 = Industrial temperature range, –40 to 85 °C 7 = Industrial temperature range, –40 to 105 °C Options xxx = programmed parts TR = tape and reel 118/122 DS10315 Rev 7 318 K 8 T 6 xxx STM32F318C8 STM32F318K8 9 Important security notice Important security notice The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: • ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. • Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. • Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. • While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. • All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. DS10315 Rev 7 119/122 119 Revision history 10 STM32F318C8 STM32F318K8 Revision history Table 77. Document revision history Date Revision 27-May-2014 1 Initial release. 2 Added the number of comparators in the document title. Updated the position of VSSA/VREF- pin in WLCSP49 package in Table 12: STM32F318x8 pin definitions. Added the maximum value for wake up time from stop mode in Table 33: Low-power mode wakeup timings. 3 Applied the following changes: – updated the comparator analog supply range in Features, – added “Interconnect matrix” in Features, – added some information related to timers in Table 1: STM32F318x8 device features and peripheral counts – updated Section 3.5.1: Power supply schemes and added Table 2: External analog supply values for analog peripherals, – added the last footnote to Table 12: STM32F318x8 pin definitions, – updated Table 43: HSI oscillator characteristics and Figure 19: HSI oscillator accuracy characterization results for soldered parts, – updated VDDA min value in Table 69: Comparator characteristics, – updated Table 27: Typical and maximum VDDA consumption in Stop mode, – updated Table 33: Low-power mode wakeup timings, – updated UFQFPN32 and WLCSP49 marking in Chapter 7: Package information. 4 Updated: – the order of columns in Table 25: Typical and maximum current consumption from the VDDA supply, – Table 41: HSE oscillator characteristics, – Table 46: Flash memory characteristics, – Table 52: NPOR pin characteristics, – Table 69: Comparator characteristics. Added: – Figure 35: Maximum VREFINT scaler startup time from power down. 5 Added LQFP48 package, updated the following: – Section 2: Description, – Table 1: STM32F318x8 device features and peripheral counts, – Table 12: STM32F318x8 pin definitions, – Table 23: General operating conditions, – Table 50: ESD absolute maximum ratings, – Table 80: Package thermal characteristics, – Table 81: Ordering information scheme. Added: – Figure 5: STM32F318x8 LQFP48 pinout, – Section 7.3: LQFP48 package information. 10-Jun-2014 02-Dec-2014 09-Feb-2015 22-Jun-2015 120/122 Changes DS10315 Rev 7 STM32F318C8 STM32F318K8 Revision history Table 77. Document revision history (continued) Date 08-Jun-2017 15-Apr-2022 Revision Changes 6 – Updated all document table notes by removing the “not tested in production” specification. – Updated VREFINT line on Table 27: Embedded internal reference voltage. – Updated “Conditions” column on Table 42: LSE oscillator characteristics (fLSE = 32.768 kHz). – Added CMIR and tSTAB lines on Table 63: ADC characteristics. – Updated RLOAD line on Table 68: DAC characteristics. – Updated VOHSAT and VOLSAT lines on Table 70: Operational amplifier characteristics – Added Section 7.4: UFQFPN32 package information note 2. – Updated Section 7: Package information adding information about other optional marking or inset/upset marks. – Updated note 1 below all the package device marking figures. – Updated Table 52: I/O current injection susceptibility note by ‘injection is not possible’. – Updated Figure 25: Recommended NRST pin protection note about the 0.1uF capacitor. 7 Updated: – Section 7.2: LQFP48 package information – Section 7.3: UFQFPN32 package information – New Section 9: Important security notice DS10315 Rev 7 121/122 121 STM32F318C8 STM32F318K8 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved 122/122 DS10315 Rev 7