STM32F334x4 STM32F334x6
STM32F334x8
Arm®Cortex®-M4 32b MCU+FPU,up to 64KB Flash,16KB SRAM,
2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1)
Datasheet - production data
Features
• Core: Arm® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division DSP instruction
• Memories
– Up to 64 Kbytes of Flash memory
UFQFPN32 (5 x 5 mm)
LQFP32 (7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
WLCSP49
(3.89x3.74 mm)
– Up to 12 Kbytes of SRAM with HW parity
check
• Three ultra-fast rail-to-rail analog comparators
with analog supply from 2 to 3.6 V
– Routine booster: 4 Kbytes of SRAM on
instruction and data bus with HW parity
check (CCM)
• One operational amplifiers that can be used in
PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V
• CRC calculation unit
• Reset and supply management
– Low-power modes: Sleep, Stop, Standby
– VDD,VDDA voltage range: 2.0 to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– VBAT supply for RTC and backup registers
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC (up to 64 MHz with PLL
option)
– Internal 40 kHz oscillator
• Up to 51 fast I/O ports, all mappable on
external interrupt vectors, several 5 V-tolerant
• Interconnect matrix
• 7-channel DMA controller
• Up to two ADC 0.20 µs (up to 21 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, single-ended /
differential mode, separate analog supply from
2.0 to 3.6 V
• Temperature sensor
• Up to three 12-bit DAC channels with analog
supply from 2.4 V to 3.6 V
July 2018
This is information on a product in full production.
• Up to 18 capacitive sensing channels
supporting touchkeys, linear and rotary touch
sensors
• Up to 12 timers
– HRTIM: 6 x16-bit counters, 217 ps
resolution, 10 PWM, 5 fault inputs, 10 ext
event input, 1 synchro. input,1 synchro. out
– One 32-bit timer and one 16-bit timer with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– One 16-bit 6-channel advanced-control
timer, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs,
1 OCN/PWM, deadtime generation,
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent,
window)
– SysTick timer: 24-bit downcounter
– Up to two 16-bit basic timers to drive DAC
• Calendar RTC with alarm, periodic wakeup
from Stop
• Communication interfaces
– CAN interface (2.0 B Active) and one SPI
DS9994 Rev 9
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www.st.com
STM32F334x4 STM32F334x6 STM32F334x8
– One I2C with 20 mA current sink to support
Fast mode plus, SMBus/PMBus
• 96-bit unique ID
• All packages ECOPACK®2 compliant
– Up to 3 USARTs, one with ISO/IEC 7816
interface, LIN, IrDA, modem control
• Debug mode: serial wire debug (SWD), JTAG
Table 1. Device summary
2/125
Reference
Part number
STM32F334Kx
STM32F334K4/K6/K8
STM32F334Cx
STM32F334C4/C6/C8
STM32F334Rx
STM32F334R6/R8
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Arm® Cortex®-M4 core with FPU with embedded Flash
memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 15
3.4
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 20
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10.4
OPAMP2 reference voltage (VOPAMP2) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13
Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM32F334x4 STM32F334x6 STM32F334x8
3.14.1
217 ps high-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.2
Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.3
General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17) . . . . . 25
3.14.4
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.5
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.6
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.15
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 26
3.16
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.1
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.2
Universal synchronous / asynchronous
receivers / transmitters (USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.4
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1
Serial-wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
Pinout and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
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Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.5
Input voltage on a pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.6
Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.7
Measurement of the current consumption . . . . . . . . . . . . . . . . . . . . . . . 49
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 53
6.3.3
Characteristics of the embedded reset and power-control block . . . . . . 53
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
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Contents
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.16
High-resolution timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.17
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.18
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.20
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.21
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.22
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.23
Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.24
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.2
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.4
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.5
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.6
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
7.7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.7.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.7.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 120
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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5
List of tables
STM32F334x4 STM32F334x6 STM32F334x8
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F334x4/6/8 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11
VDDA ranges for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F334x4/6/8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F334x4/6/8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F334x4/6/8 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitive sensing GPIOs available on STM32F334x4/6/8 devices . . . . . . . . . . . . . . . . . 30
No. of capacitive sensing channels available on STM32F334x4/6/8 devices. . . . . . . . . . . 31
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32F334x4/6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32F334x4/6/8 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 53
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 56
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 57
Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 57
Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 58
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 58
Typical current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 61
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
List of tables
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HRTIM1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
HRTIM output response to fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HRTIM output response to external events 1 to 5 (Low-Latency mode). . . . . . . . . . . . . . . 83
HRTIM output response to external events 1 to 10 (Synchronous mode ) . . . . . . . . . . . . . 83
HRTIM synchronization input / output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
IWDG min./max. timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
WWDG min./max. timeout value at 72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Temperature sensor (TS) calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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7
List of figures
STM32F334x4 STM32F334x6 STM32F334x8
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
8/125
STM32F334x4/6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32F334x4/6/8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Scheme of the current-consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 59
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71
TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5V- tolerant (FT and FTf) I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . 78
5V-tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . 78
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADC typical current consumption in single-ended and differential modes . . . . . . . . . . . . . 91
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Maximum VREFINT scaler startup time from power-down . . . . . . . . . . . . . . . . . . . . . . . . . 100
OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Recommended footprint for the LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Recommended footprint for the LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Recommended footprint for the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
WLCSP49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Figure 47.
Figure 48.
Figure 49.
List of figures
UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
DS9994 Rev 9
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9
Introduction
1
STM32F334x4 STM32F334x6 STM32F334x8
Introduction
This datasheet provides the ordering information and the mechanical device characteristics
of the STM32F334x4/6/8 microcontrollers.
This document must be read in conjunction with the STM32F334xx, reference manual
(RM0364) available from the STMicroelectronics website www.st.com.
For information on the Cortex®-M4 core with FPU, refer to:
•
Arm®(a) Cortex®-M4 Processor Technical Reference Manual available from the
www.arm.com website.
•
STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214) available
from the www.st.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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STM32F334x4 STM32F334x6 STM32F334x8
2
Description
Description
The STM32F334x4/6/8 family incorporates the high-performance Arm® Cortex®-M4 32-bit
RISC core operating at up to 72 MHz frequency embedding a floating point unit (FPU),
high-speed embedded memories (up to 64 Kbytes of Flash memory, up to 12 Kbytes of
SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB
buses.
The STM32F334x4/6/8 microcontrollers offer two fast 12-bit ADCs (5 Msps), up to three
ultra-fast comparators, an operational amplifier, three DAC channels, a low-power RTC, one
high-resolution timer, one general-purpose 32-bit timer, one timer dedicated to motor
control, and four general-purpose 16-bit timers. They also feature standard and advanced
communication interfaces: one I2C, one SPI, up to three USARTs and one CAN.
The STM32F334x4/6/8 family operates in the –40 to +85 °C and –40 to +105 °C
temperature ranges from 2.0 to 3.6 V power supply. A comprehensive set of power-saving
modes allow the design of low-power applications.
The STM32F334x4/6/8 family offers devices in 32, 48 and 64-pin packages.
Depending on the device chosen, different sets of peripherals are included.
Table 2. STM32F334x4/6/8 family device features and peripheral counts
Peripheral
Flash memory (Kbyte)
STM32F334Kx
16
32
STM32F334Cx
64
16
32
SRAM on data bus (Kbyte)
12
Core coupled memory SRAM
on instruction bus (CCM
SRAM) (Kbyte)
4
High-resolution
timer
Timers
STM32F334Rx
64
16
32
64
1 (16-bit / 10 channels)
Advanced control
1 (16-bit)
General purpose
4 (16-bit)
1 (32 bit)
Basic
2 (16-bit)
SysTick timer
1
Watchdog timers
(independent,
window)
2
PWM channels
(all)(1)
20
26
28
PWM channels
(except
complementary)
14
20
22
DS9994 Rev 9
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46
Description
STM32F334x4 STM32F334x6 STM32F334x8
Table 2. STM32F334x4/6/8 family device features and peripheral counts (continued)
Peripheral
Comm.
interfaces
STM32F334Kx
STM32F334Cx
SPI
1
I2C
1
USART
2
STM32F334Rx
3
CAN
1
Normal I/Os (TC,
TTa)
10
20
26
5-Volt tolerant
I/Os (FT,FTf)
15
17
25
Capacitive sensing channels
14
17
18
GPIOs
DMA channels
12-bit ADCs
Number of channels
7
2
10
2
15
12-bit DAC channels
Ultra-fast analog comparator
3
2
3
Operational amplifiers
1
CPU frequency
72 MHz
Operating voltage
Operating temperature
Packages
2.0 to 3.6 V
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
LQFP32, UFQFPN32
LQFP48, WLCSP49
1. This total considers also the PWMs generated on the complementary output channels.
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2
21
DS9994 Rev 9
LQFP64
STM32F334x4 STM32F334x6 STM32F334x8
Description
Figure 1. STM32F334x4/6/8 block diagram
@VDD33
FPU
Ibus
CORTEX M4 CPU
Dbus
F
max
= 72MHz
System
bus
NVIC
BusMatrix
JTRST
JTDI
JTCK-SWCLK
JTMS-SWDAT
JTDO-TRACESWO
as AF
Obl
Flash
interface
TPIU
SWJTAG
Dbus
POWER
VDD18
Flash 64KB
64 bits
VOLT. REG.
3.3V TO 1.8V
V DD33 =2 to 3.6V
VSS
@VDDA
SRAM
12KB
@VDDA
CCM SRAM
4KB
SUPPLY
SUPERVISION
POR
Reset
Int
POR / PDR
RC HS 8MHz
PVD
RC LS
GP DMA1
7 channels
NRESET
VDDA
VSSA
@VDD33
XTAL OSC
4-32MHz
PLL
OSC_IN
OSC_OUT
Ind. WDG32K
Temp sensor
RESET&
CLOCK
CTRL
12bitADC1 IF
IF
12bitADC2 IF
IF
AHB DECODER
V REF+
V REF-
@VDDA
PA[15:0]
GPIOPORTA
PB[15:0]
GPIOPORTB
PC[15:0]
GPIOPORTC
PD2
GPIOPORTD
PF[1:0]
GPIOPORTF
6 Groups of
4 Channels as AF
Touch Sensing
Controller
AHBPCLK
APBP1CLK
APBP2CLK
HCLK
FCLK
USARTCLK
I2CCLK
ADC1/ADC2
Standby
interface
V BAT=
1.65 to 3.6V
XTAL 32kHz
RTC
AWU
Backup
reg (20B)
ANTI-TAMP
Backup interface
TIM2 (32-bit/PWM)
CRC
TIM3
AHB2
APB2
OSC32_IN
OSC32_OUT
4 Channels, ETR
as AF
4 Channels, ETR
as AF
USART2
RX,TX, CTS, RTS,
SmartCard as AF
USART3
RX,TX, CTS, RTS,
SmartCard as AF
AHB2
APB1
WinWATCHDOG
4 channels,
3 compl. channel,
ETR, BRK as AF
5 fault inputs as AF
10 PWM outputs
10 ext. event inputs
1 synchro. input
1 synchro. output
15
TIM15
TIM16
TIM17
TIM1
MOSI,MISO,
SCK,NSS as AF
SPI1
USART1
BxCAN
SCL,SDA,SMBA
as AF
CAN_TX
CAN_RX
TIM6
12-bit DAC1
channel 1 IF
DAC1_OUT1 as AF
TIM7
12-bit DAC1
IF
channel 2 IF
DAC1_OUT2 as AF
12-bit DAC2
channel 1
DAC2_OUT1 as AF
IF
HRTIM1
RX,TX, CTS, RTS,
SmartCard as AF
I2C1
APB1: Fmax = 36 MHz
EXT.IT
WKUP
APB2: Fmax = 72 MHz
up to 16 lines
2 channels,
1 compl. channel,
BRK as AF
1 channel,
1 compl. channel,
BRK as AF
1 channel,
1 compl. channel,
BRK as AF
IF
SYSCFG CTL
@VDDA
IF
Op-amp2
INM, INP, OUT as AF
@VDDA
GP Comparator 6
GP Comparator 4
GP Comparator 2
INM, INP, OUT as AF
MSv31953V3
1. AF: alternate function on I/O pins.
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46
Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU with embedded Flash
memory and SRAM
The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for
embedded systems. It has been developed to provide a low-cost platform that meets the
needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm 32-bit Cortex-M4 RISC processor with FPU features exceptional code-efficiency,
delivering the high performance expected from an Arm core, with memory sizes usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allows efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm core, the STM32F334x4/6/8 family is compatible with all Arm tools
and software.
Figure 1 shows the general block diagram of the STM32F334x4/6/8 family devices.
3.2
Memories
3.2.1
Embedded Flash memory
All STM32F334x4/6/8 devices feature up to 64 Kbytes of embedded Flash memory
available for storing programs and data. The Flash memory access time is adjusted to the
CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2
wait states above).
3.2.2
Embedded SRAM
The STM32F334x4/6/8 devices feature up to 12 Kbytes of embedded SRAM with hardware
parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait
states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz when running code from
CCM (core coupled memory) RAM.
The SRAM is organized as follows:
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•
4 Kbytes of SRAM on instruction and data bus with parity check (core coupled memory
or CCM) and used to execute critical routines or to access data
•
12 Kbytes of SRAM with parity check mapped on the data bus
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STM32F334x4 STM32F334x6 STM32F334x8
3.2.3
Functional overview
Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of the three boot
options:
•
Boot from user Flash memory
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PA2/PA3), I2C1 (PB6/PB7).
3.3
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.4
Power management
3.4.1
Power supply schemes
•
VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL.The minimum voltage to be applied
to VDDA differs from one analog peripherals to another. See Table 3 below,
summarizing the VDDA ranges for analog peripherals. The VDDA voltage level must be
always greater or equal to the VDD voltage level and must be provided first.
•
VDD18 = 1.65 to 1.95 V (VDD18 domain): power supply for digital core, SRAM and Flash
memory. VDD18 is internally generated through an internal voltage regulator.
Table 3. VDDA ranges for analog peripherals
Analog peripheral
Min. VDDAsupply
Max. VDDAsupply
ADC/COMP
2V
3.6 V
DAC/OPAMP
2.4 V
3.6 V
•
3.4.2
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
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Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA must arrive first and be greater than or equal to VDD.
•
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
•
The MR mode is used in the nominal regulation mode (Run)
•
The LPR mode is used in Stop mode.
•
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
3.4.4
Low-power modes
The STM32F334x4/6/8 supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,
I2C or USARTx.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
16/125
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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3.5
Functional overview
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F334x4/6/8 peripheral interconnect matrix
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
ADCx
DACx
Conversion triggers
DMA
Memory to memory transfer trigger
COMPx
Comparator output blanking
COMPx
TIMx
Timer input: ocrefclear input, input capture
ADCx
TIM/HRTIM1
Timer triggered by analog watchdog
GPIO
RTCCLK
HSE/32
MC0
TIM16
Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
RAM (parity error)
COMPx
PVD
GPIO
TIM1
TIM15, 16, 17
Timer break
TIMx
External trigger, timer break
GPIO
ADCx
DACx
Conversion external trigger
DACx
COMPx
Comparator inverting input
HRTIM1
DACx/ADCx
Conversion trigger
COMPx
HRTIM1
COMPx output is an input event or a fault input for
HRTIM1
OPAMP2
HRTIM1
OPAMP2 output is an input event for HRTIM1
GPIO
HRTIM1
External fault/event/ Synchro inputs for HRTIM1
HRTIM1
GPIO
Synchro output for HRTIM1
TIMx
Note:
Interconnect
destination
For more details about the interconnect actions, refer to the corresponding sections in the
RM0364 reference manual.
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Functional overview
3.6
STM32F334x4 STM32F334x6 STM32F334x8
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected on reset as default CPU clock. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high-speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the
high-speed APB domains is 72 MHz, while the maximum allowed frequency of the lowspeed APB domain is 36 MHz.
TIM1and HRTIM1 maximum frequency is 144 MHz.
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Functional overview
Figure 2. Clock tree
FLITFCLK
to Flash programming interface
HSI
to I2C1
SYSCLK
8 MHz
HSI
HSI RC
/2
HCLK
PLLSRC
to cortex System timer
/8
SW
PLLMUL
to AHB bus, core,
memory and DMA
FHCLK Cortex free
HSI
x2,x3,..
AHB
AHB
prescaler
prescaler
x16
/1,2,..512
/1,2,4,8,16
PLL
PLLCLK
APB1
running clock
PCLK1
to APB1 peripherals
HSE
SYSCLK
If (APB1 prescaler
CSS
/2,/3,...
to TIM 2, 3, 6, 7
=1) x1 else x2
/16
PCLK1
SYSCLK
HSI
OSC_OUT
4-32 MHz
OSC_IN
HSE OSC
APB2
PCLK2
to APB2 peripherals
prescaler
/1,2,4,8,16
/32
RTCCLK
OSC32_IN
LSE OSC
32.768kHz
OSC32_OUT
to USARTx (x = 1, 2, 3)
LSE
to RTC
If (APB2 prescaler
LSE
to TIM 15,16,17
=1) x1 else x2
RTCSEL[1:0]
LSI RC
LSI
IWDGCLK
to IWDG
40kHz
PLLNODIV
MCOPRE
/2
MCO
PLLCLK
x2
HSI
/1,2,4,
...128
TIM1/
HRTIM1
LSI
HSE
SYSCLK
Main clock
output
ADC
Prescaler
/1,2,4
MCO
to ADCx
(x = 1, 2)
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256
MS31933V5
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Functional overview
3.7
STM32F334x4 STM32F334x6 STM32F334x8
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed, following a specific
sequence to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.8
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
high-resolution timer, DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F334x4/6/8 devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 60 interrupt channels that can be masked and 16 priority levels.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved on interrupt entry and restored on interrupt exit
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 27 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
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Functional overview
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 51
GPIOs can be connected to the 16 external interrupt lines.
3.10
Fast analog-to-digital converter (ADC)
Two 5 MSPS fast analog-to-digital converters, with selectable resolution between 12 and 6
bit, are embedded in the STM32F334x4/6/8 family devices. The ADCs have up to 21
external channels. Some of the external channels are shared between ADC1 and ADC2,
performing conversions in single-shot or scan modes. The channels can be configured to be
either single-ended input or differential input. In scan mode, automatic conversion is
performed on a selected group of analog inputs.
The ADCs also have internal channels: temperature sensor connected to ADC1 channel 16,
VBAT/2 connected to ADC1 channel 17, voltage reference VREFINT connected to both ADC1
and ADC2 channel 18 and VOPAMP2 connected to ADC2 channel 17.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
•
Single-shunt phase current reading techniques.
Three analog watchdogs are available per ADC. The ADC can be served by the DMA
controller.
The analog watchdog feature allows very precise monitoring of the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIM2, TIM3, TIM6, TIM15), the
advanced-control timer (TIM1) and the High-resolution timer (HRTIM1) can be internally
connected to the ADC start trigger and injection trigger, respectively, to allow the application
to synchronize A/D conversion and timers.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC1_IN18 and ADC2_IN18
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Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
input channels. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.10.3
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.10.4
OPAMP2 reference voltage (VOPAMP2)
OPAMP2 reference voltage can be measured using ADC2 internal channel 17.
3.11
Digital-to-analog converter (DAC)
One 12-bit buffered DAC channel (DAC1_OUT1) and two 12-bit unbuffered DAC channels
(DAC1_OUT2 and DAC2_OUT1) can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
3.12
•
Three DAC output channels
•
8-bit or 12-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation (only on DAC1)
•
Triangular-wave generation (only on DAC1)
•
Dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
External triggers for conversion
Operational amplifier (OPAMP)
The STM32F334x4/6/8 embeds an operational amplifier (OPAMP2) with external or internal
follower routing and PGA capability (or even amplifier and filter capability with external
components). When an operational amplifier is selected, an external ADC channel is used
to enable output measurement.
The operational amplifier features:
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•
8 MHz GBP
•
•
•
0.5 mA output capability
Rail-to-rail input/output
In PGA mode, the gain can be programmed to 2, 4, 8 or 16.
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3.13
Functional overview
Ultra-fast comparators (COMP)
The STM32F334x4/6/8 devices embed three ultra-fast rail-to-rail comparators (COMP2/4/6)
that offer the features below:
•
Programmable internal or external reference voltage
•
Selectable output polarity.
The reference voltage can be one of the following:
•
External I/O
•
DAC output
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded
internal reference voltage for values and parameters of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers.
3.14
Timers and watchdogs
The STM32F334x4/6/8 includes advanced control timer, 5 general-purpose timers, basic
timer, two watchdog timers and a SysTick timer. The table below compares the features of
the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Timer type
Counter
resolution
Timer
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Yes
10
Yes
Highresolution
timer
HRTIM1
16-bit
Up
/1 /2 /4
(x2 x4 x8 x16
x32, with
DLL)
Advanced
control
TIM1(1)
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
Yes
Generalpurpose
TIM2
32-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM3
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
Generalpurpose
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
(1)
1. TIM1 can be clocked from the PLL x 2 running at 144 MHz .
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Functional overview
3.14.1
STM32F334x4 STM32F334x6 STM32F334x8
217 ps high-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
HRTIM1 timer is made of a digital kernel clocked at 144 MHz followed by delay lines. Delay
lines with closed loop control guarantee a 217 ps resolution whatever the voltage,
temperature or chip-to-chip manufacturing process deviation. The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, burst mode controller,
push-pull and resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
In debug mode, the HRTIM1 counters can be frozen and the PWM outputs enter safe state.
3.14.2
Advanced timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM multiplexed on 6 channels.
They have complementary PWM outputs with programmable inserted dead-times. They can
also be seen as complete general-purpose timers. The 4 independent channels can be
used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.14.3) using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
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3.14.3
Functional overview
General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17)
There are up to three general-purpose timers embedded in the STM32F334x4/6/8 (see
Table 5 for differences) that can be synchronized. Each general-purpose timer can be used
to generate PWM outputs, or act as a simple time base.
•
TIM2 and TIM3
They are full-featured general-purpose timers:
–
TIM2 has a 32-bit auto-reload up/down counter and 32-bit prescaler
–
TIM3 has a 16-bit auto-reload up/down counter and 16-bit prescaler
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
They are three general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has two channels and one complementary channel
–
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.14.4
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.14.5
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.14.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Functional overview
3.14.7
STM32F334x4 STM32F334x6 STM32F334x8
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.15
•
A 24-bit down counter
•
Auto reload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power from
either the VDD supply when present or the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms with wakeup from Stop and Standby mode capability.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
•
Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
•
17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
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•
A 32.768 kHz external crystal
•
A resonator or oscillator
•
The internal low-power RC oscillator (typical frequency of 40 kHz)
•
The high-speed external clock divided by 32.
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Functional overview
3.16
Communication interfaces
3.16.1
Inter-integrated circuit interface (I2C)
The devices feature an I2C bus interface that can operate in multimaster and slave mode. It
can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz)
modes.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
Table 6. Comparison of I2C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. It also has a clock domain independent from the CPU clock,
allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interface can be served by the DMA controller.
The features available in I2C1 are showed below in Table 7.
Table 7. STM32F334x4/6/8 I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
1. X = supported.
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46
Functional overview
3.16.2
STM32F334x4 STM32F334x6 STM32F334x8
Universal synchronous / asynchronous
receivers / transmitters (USARTs)
The STM32F334x4/6/8 devices have three embedded universal synchronous
receivers/transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
USART1 provides hardware management of the CTS and RTS signals. It supports IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and has LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
The features available in the USART interfaces are showed below in Table 8.
Table 8. USART features
USART1
USART2
USART3
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
X
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
-
LIN mode
X
-
Dual clock domain and wake up from Stop mode
X
-
Receiver timeout interrupt
X
-
Modbus communication
X
-
Auto baud rate detection
X
-
Driver Enable
X
X
USART modes/features(1)
1. X = supported.
3.16.3
Serial peripheral interface (SPI)
A SPI interface allows to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
The features available in SPI1 are showed below in Table 9.
Table 9. STM32F334x4/6/8 SPI implementation
SPI features(1)
28/125
SPI1
Hardware CRC calculation
X
Rx/Tx FIFO
X
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Functional overview
Table 9. STM32F334x4/6/8 SPI implementation (continued)
SPI features(1)
SPI1
NSS pulse mode
X
TI mode
X
1. X = supported.
3.16.4
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.17
Infrared transmitter
The STM32F334x4/6/8 devices provide an infrared transmitter solution. The solution is
based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes is obtained by programming the two timers of the output compare channels (see
Figure 3).
Figure 3. Infrared transmitter
TIMER 16
OC
(for envelop)
TIMER 17
PB9/PA13
OC
(for carrier)
MSv30365V1
3.18
Touch sensing controller (TSC)
The STM32F334x4/6/8 devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 18 capacitive sensing channels
distributed over 6 analog I/Os group.
Capacitive sensing technology is able to detect the presence of a finger near an electrode
that is protected from direct touch by a dielectric (glass, plastic and others). The capacitive
DS9994 Rev 9
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46
Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
variation introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the electrode capacitance and then transferring a part of the accumulated charges
into a sampling capacitor, until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 10. Capacitive sensing GPIOs available on STM32F334x4/6/8 devices
Group
1
2
3
4
5
6
30/125
Capacitive sensing group name
Pin name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
PA3
TSC_G2_IO1
PA4
TSC_G2_IO2
PA5
TSC_G2_IO3
PA6
TSC_G2_IO4
PA7
TSC_G3_IO1
PC5
TSC_G3_IO2
PB0
TSC_G3_IO3
PB1
TSC_G3_IO4
PB2
TSC_G4_IO1
PA9
TSC_G4_IO2
PA10
TSC_G4_IO3
PA13
TSC_G4_IO4
PA14
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
TSC_G5_IO4
PB7
TSC_G6_IO1
PB11
TSC_G6_IO2
PB12
TSC_G6_IO3
PB13
TSC_G6_IO4
PB14
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Functional overview
Table 11. No. of capacitive sensing channels available on STM32F334x4/6/8 devices
Number of capacitive sensing channels
Analog I/O group
STM32F334xRx
STM32F334xCx
STM32F334xKx
G1
3
3
3
G2
3
3
3
G3
3
2
2
G4
3
3
3
G5
3
3
3
G6
3
3
0
Total number of capacitive
sensing channels
18
17
14
3.19
Development support
3.19.1
Serial-wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
DS9994 Rev 9
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46
Pinout and pin descriptions
4
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
VSS
Figure 4. LQFP32 pinout
32 31 30 29 28 27 26 25
VDD
1
24
PF0/OSC_IN
2
23
PA13
PF1/OSC_OUT
3
22
PA12
PA14
NRST
4
21
PA11
VDDA/VREF+
5
20
PA10
PA0
6
19
PA9
PA1
7
18
PA8
PA2
8
17
VDD
VSS
PB1
PA7
PB0
PA4
PA6
10 11 12 13 14 15 16
PA5
9
PA3
LQFP32
MS31949V3
1. The above figure shows the package top view.
43
42
41
40
39
38
PA14
PA15
44
PB3
45
PB4
BOOT0
46
PB5
PB8
47
PB6
PB9
48
PB7
VDD
VSS
Figure 5. LQFP48 pinout
37
VBAT
1
36
VDD
PC13
2
35
VSS
PC14/OSC32_IN
3
34
PA13
PC15/OSC32_OUT
4
33
PA12
PF0/OSC_IN
5
32
PF1/OSC_OUT
6
31
PA11
PA10
NRST
7
30
PA9
VSSA/VREF-
8
29
PA8
VDDA/VREF+
9
28
PB15
PA0
10
27
PB14
PA1
11
26
PB13
PA2
12
25
PB12
PA6
PA7
20
21
22
23
24
VDD
PA5
19
VSS
PA4
18
PB11
17
PB10
16
PB2
15
PB1
14
PB0
13
PA3
LQFP48
MSv36901V2
1. The above figure shows the package top view.
32/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
VSS
PB9
VDD
Figure 6. LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
PC13
2
47
VSS
PC14/OSC32_IN
3
46
PA13
PC15/OSC32_OUT
4
45
PA12
PF0/OSC_IN
5
6
44
43
PA11
42
PA9
PF1/OSC_OUT
NRST
7
PC0
8
PC1
9
LQFP64
VDD
PA10
41
PA8
40
PC9
PC2
10
39
PC8
PC3
11
38
PC7
VSSA/VREF-
12
37
PC6
PB15
13
36
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
VDDA/VREF+
VDD
VSS
PB11
PB2
PB10
PB1
PB0
PC5
PC4
PA7
PA6
PA5
PA4
VDD
VSS
PA3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MS31951V2
1. The above figure shows the package top view.
DS9994 Rev 9
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Figure 7. WLCSP49 ballout
5
6
7
1
2
3
4
A
PA14
PA15
PB3
PB6
B
VSS
VDD
PB4
PB5
PB7
C
PA11
PA13
PA12
PA10
PC3
D
PA8
PA9
PB15
PC7
PA2
PA0
NRST
E
PB14
PB13
PC5
PA6
PA3
VDDA
VSSA
VREF-
F
PB12
PB2
PB0
PA7
PA4
VSS
VREF+
G
PB11
PB10
PB1
PC4
PA5
VDD
PA1
BOOT0
PB9
VDD
PB8
VSS
PF1
OSC_OUT
PF0
OSC_IN
MSv44311V1
1. The above figure shows the package top view.
34/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
32
31
30
29
28
27
26
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
VSS
Figure 8. UFQFPN32 pinout
25
VDD
1
24
PA14
PF0/OSC_IN
2
23
PA13
PF1/OSC_OUT
3
22
PA12
NRST
4
21
PA11
VDDA/VREF+
5
20
PA10
VSSA/VREF-
6
19
PA9
PA0
7
18
PA8
PA1
8
17
VDD
12
13
14
15
16
PA6
PA7
PB0
VSS
11
PA4
10
PA3
PA2
9
PA5
UFQFPN32
MSv44312V2
DS9994 Rev 9
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Table 12. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TT
3.3 V tolerant I/O
TC
Standard 3.3 V I/O
B
Dedicated BOOT0 pin
RST
Bi-directional reset pin with embedded weak pull-up resistor
Pin type
I/O structure
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset
Notes
Alternate
functions
Pin
functions
Definition
Functions selected through GPIOx_AFR registers
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 13. STM32F334x4/6/8 pin definitions
LQFP32
LQFP48
LQFP64
WLCSP49
Pin type
I/O structure
Pin functions
UFQFPN32
Pin Number
-
-
1
1
-
VBAT
S
-
-
-
2
2
-
PC13(1)
I/O
TC
TIM1_CH1N
RTC_TAMP1/RTC_TS/
RTC_OUT/WKUP2
-
-
3
3
-
PC14 / OSC32_IN(1)
I/O
TC
-
OSC32_IN
-
-
4
4
-
PC15 / OSC32_OUT(1)
I/O
TC
-
OSC32_OUT
2
2
5
5
C7
PF0 / OSC_IN
I/O
FT
TIM1_CH3N
OSC_IN
3
3
6
6
C6
PF1 / OSC_OUT
I/O
FT
-
OSC_OUT
4
4
7
7
D7
NRST
I/O
RST
-
-
-
8
-
PC0
I/O
TTa
36/125
Pin name
(function after
reset)
DS9994 Rev 9
Alternate
functions
Additional functions
Backup power supply
Device reset input / internal reset output
(active low)
EVENTOUT,
TIM1_CH1
ADC12_IN6
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
Table 13. STM32F334x4/6/8 pin definitions (continued)
LQFP32
LQFP48
LQFP64
WLCSP49
Pin type
I/O structure
Pin functions
UFQFPN32
Pin Number
-
-
-
9
-
PC1
I/O
TTa
EVENTOUT,
TIM1_CH2
ADC12_IN7
-
-
-
10
-
PC2
I/O
TTa
EVENTOUT,
TIM1_CH3
ADC12_IN8
-
-
-
11
C5
PC3
I/O
TTa
EVENTOUT,
TIM1_CH4,
TIM1_BKIN2
ADC12_IN9
6
-
8
12
E7
VSSA/VREF-
S
-
-
-
-
F7
VREF+
S
-
-
-
E6
VDDA
S
-
-
-
-
VDDA/VREF+
S
-
5
7
8
9
5
6
7
8
9
10
11
12
13
14
15
16
D6
G7
D5
Pin name
(function after
reset)
PA0
PA1
PA2
I/O
I/O
I/O
Alternate
functions
Additional functions
Analog ground/Negative reference voltage
Analog power supply/Positive reference voltage
TTa
TIM2_CH1/
TIM2_ETR,
TSC_G1_IO1,
USART2_CTS,
EVENTOUT
ADC1_IN1(2),
RTC_TAMP2/WKUP1
TTa
TIM2_CH2,
TSC_G1_IO2,
USART2_RTS_DE,
TIM15_CH1N,
EVENTOUT
ADC1_IN2(2), RTC_REFIN
TTa
TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
EVENTOUT
ADC1_IN3(2), COMP2_INM
ADC1_IN4(2)
10
9
13
17
E5
PA3
I/O
TTa
TIM2_CH4,
TSC_G1_IO4,
USART2_RX,
TIM15_CH2,
EVENTOUT
-
-
-
18
F6
VSS
S
-
-
-
-
-
-
19
G6
VDD
S
-
-
-
TTa
TIM3_CH2,
TSC_G2_IO1,
SPI1_NSS,
USART2_CK,
EVENTOUT
ADC2_IN1(2), DAC1_OUT1,
COMP2_INM, COMP4_INM,
COMP6_INM
TTa
TIM2_CH1/
TIM2_ETR,
TSC_G2_IO2,
SPI1_SCK,
EVENTOUT
ADC2_IN2(2), DAC1_OUT2,
OPAMP2_VINM
11
12
10
11
14
15
20
21
F5
G5
(3)
PA4
PA5(3)
I/O
I/O
DS9994 Rev 9
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
13
12
16
22
E4
Pin name
(function after
reset)
PA6(3)
Pin type
WLCSP49
LQFP64
LQFP48
LQFP32
UFQFPN32
Pin Number
I/O
I/O structure
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin functions
Alternate
functions
Additional functions
TTa
TIM16_CH1,
TIM3_CH1,
TSC_G2_IO3,
SPI1_MISO,
TIM1_BKIN,
OPAMP2_DIG,
EVENTOUT
ADC2_IN3(2), DAC2_OUT1,
OPAMP2_VOUT
ADC2_IN4(2), COMP2_INP,
OPAMP2_VINP
14
13
17
23
F4
PA7
I/O
TTa
TIM17_CH1,
TIM3_CH2,
TSC_G2_IO4,
SPI1_MOSI,
TIM1_CH1N,
EVENTOUT
-
-
-
24
G4
PC4
I/O
TTa
EVENTOUT,
TIM1_ETR,
USART1_TX
ADC2_IN5(2)
-
-
-
25
E3
PC5
I/O
TTa
EVENTOUT,
TIM15_BKIN,
TSC_G3_IO1,
USART1_RX
ADC2_IN11, OPAMP2_VINM
15
14
18
26
F3
PB0
I/O
TTa
TIM3_CH3,
TSC_G3_IO2,
TIM1_CH2N,
EVENTOUT
ADC1_IN11, COMP4_INP,
OPAMP2_VINP
ADC1_IN12
-
15
19
27
G3
PB1
I/O
TTa
TIM3_CH4,
TSC_G3_IO3,
TIM1_CH3N,
COMP4_OUT,
HRTIM1_SCOUT,
EVENTOUT
-
-
20
28
F2
PB2
I/O
TTa
TSC_G3_IO4,
HRTIM_SCIN,
EVENTOUT
ADC2_IN12, COMP4_INM
TT
TIM2_CH3,
TSC_SYNC,
USART3_TX,
HRTIM1_FLT3,
EVENTOUT
-
TIM2_CH4,
TSC_G6_IO1,
USART3_RX,
HRTIM1_FLT4,
EVENTOUT
COMP6_INP
-
-
21
29
G2
PB10
I/O
-
-
22
30
G1
PB11
I/O
TTa
16
16
23
31
-
VSS
S
-
Digital ground
17
17
24
32
B2
VDD
S
-
Digital power supply
-
-
38/125
-
25
26
33
34
F1
E2
PB12
PB13
I/O
I/O
DS9994 Rev 9
TTa
TSC_G6_IO2,
TIM1_BKIN,
USART3_CK,
HRTIM1_CHC1,
EVENTOUT
ADC2_IN13
TTa
TSC_G6_IO3,
TIM1_CH1N,
USART3_CTS,
HRTIM1_CHC2,
EVENTOUT
ADC1_IN13
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
-
-
27
35
E1
Pin name
(function after
reset)
PB14
Pin type
WLCSP49
LQFP64
LQFP48
LQFP32
UFQFPN32
Pin Number
I/O
I/O structure
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin functions
Alternate
functions
Additional functions
TTa
TIM15_CH1,
TSC_G6_IO4,
TIM1_CH2N,
USART3_RTS_DE,
HRTIM1_CHD1,
EVENTOUT
ADC2_IN14, OPAMP2_VINP
ADC2_IN15, COMP6_INM,
RTC_REFIN
-
-
28
36
D3
PB15
I/O
TTa
TIM15_CH2,
TIM15_CH1N,
TIM1_CH3N,
HRTIM1_CHD2,
EVENTOUT
-
-
-
37
-
PC6
I/O
FT
EVENTOUT,
TIM3_CH1,
HRTIM1_EEV10,
COMP6_OUT
-
-
-
-
38
D4
PC7
I/O
FT
EVENTOUT,
TIM3_CH2,
HRTIM1_FLT5
-
-
-
-
39
-
PC8
I/O
FT
EVENTOUT,
TIM3_CH3,
HRTIM1_CHE1
-
-
-
-
40
-
PC9
I/O
FT
EVENTOUT,
TIM3_CH4,
HRTIM1_CHE2
-
18
18
29
41
D1
PA8
I/O
FT
MCO, TIM1_CH1,
USART1_CK,
HRTIM1_CHA1,
EVENTOUT
-
FT
TSC_G4_IO1,
TIM1_CH2,
USART1_TX,
TIM15_BKIN,
TIM2_CH3,
HRTIM1_CHA2,
EVENTOUT
-
FT
TIM17_BKIN,
TSC_G4_IO2,
TIM1_CH3,
USART1_RX,
COMP6_OUT,
TIM2_CH4,
HRTIM1_CHB1,
EVENTOUT
-
FT
TIM1_CH1N,
USART1_CTS,
CAN_RX,
TIM1_CH4,
TIM1_BKIN2,
HRTIM1_CHB2,
EVENTOUT
-
FT
TIM16_CH1,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT,
CAN_TX, TIM1_ETR,
HRTIM1_FLT1,
EVENTOUT
-
19
20
21
22
19
20
21
22
30
31
32
33
42
43
44
45
D2
C4
C1
C3
PA9
PA10
PA11
PA12
I/O
I/O
I/O
I/O
DS9994 Rev 9
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Pin name
(function after
reset)
Pin type
WLCSP49
LQFP64
LQFP48
LQFP32
UFQFPN32
Pin Number
I/O structure
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin functions
Alternate
functions
Additional functions
-
23
23
34
46
C2
PA13
I/O
FT
JTMS/SWDAT,
TIM16_CH1N,
TSC_G4_IO3,
IR_OUT,
USART3_CTS,
EVENTOUT
-
-
35
47
B1
VSS
S
-
-
-
-
-
36
48
-
VDD
S
-
-
-
FTf
JTCK/SWCLK,
TSC_G4_IO4,
I2C1_SDA,
TIM1_BKIN,
USART2_TX,
EVENTOUT
-
-
24
24
37
49
A1
PA14
I/O
25
25
38
50
A2
PA15
I/O
FTf
JTDI,
TIM2_CH1/TIM2_ET
R, TSC_SYNC,
I2C1_SCL,
SPI1_NSS,
USART2_RX,
TIM1_BKIN,
HRTIM1_FLT2,
EVENTOUT
-
-
-
51
-
PC10
I/O
FT
EVENTOUT,
USART3_TX
-
-
-
-
52
-
PC11
I/O
FT
EVENTOUT,
HRTIM1_EEV2,
USART3_RX
-
-
-
-
53
-
PC12
I/O
FT
EVENTOUT,
HRTIM1_EEV1,
USART3_CK
-
-
-
-
54
-
PD2
I/O
FT
EVENTOUT,
TIM3_ETR
-
FT
JTDO/TRACE
SWO, TIM2_CH2,
TSC_G5_IO1,
SPI1_SCK,
USART2_TX,
TIM3_ETR,
HRTIM1_SCOUT,
HRTIM1_EEV9,
EVENTOUT
-
FT
NJTRST,
TIM16_CH1,
TIM3_CH1,
TSC_G5_IO2,
SPI1_MISO,
USART2_RX,
TIM17_BKIN,
HRTIM1_EEV7,
EVENTOUT
-
26
27
40/125
26
27
39
40
55
56
A3
B3
PB3
PB4
I/O
I/O
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
28
29
28
29
41
42
57
58
B4
A4
Pin name
(function after
reset)
PB5
PB6
Pin type
WLCSP49
LQFP64
LQFP48
LQFP32
UFQFPN32
Pin Number
I/O
I/O
I/O structure
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin functions
Alternate
functions
Additional functions
FT
TIM16_BKIN,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
USART2_CK,
TIM17_CH1,
HRTIM1_EEV6,
EVENTOUT
-
FTf
TIM16_CH1N,
TSC_G5_IO3,
I2C1_SCL,
USART1_TX,
HRTIM1_SCIN,
HRTIM1_EEV4,
EVENTOUT
-
-
30
30
43
59
B5
PB7
I/O
FTf
TIM17_CH1N,
TSC_G5_IO4,
I2C1_SDA,
USART1_RX,
TIM3_CH4,
HRTIM1_EEV3,
EVENTOUT
31
31
44
60
A5
BOOT0
I
B
-
-
FTf
TIM16_CH1,
TSC_SYNC,
I2C1_SCL,
USART3_RX,
CAN_RX,
TIM1_BKIN,
HRTIM1_EEV8,
EVENTOUT
-
-
-
-
45
61
B6
PB8
I/O
-
-
46
62
A6
PB9
I/O
FTf
TIM17_CH1,
I2C1_SDA, IR_OUT,
USART3_TX,
COMP2_OUT,
CAN_TX,
HRTIM1_EEV5,
EVENTOUT
32
32
47
63
B7
VSS
S
-
-
-
1
1
48
64
A7
VDD
S
-
-
-
1.
PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of
GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup
registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP
register description sections in the reference manual.
2.
Fast ADC channel.
3.
These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
DS9994 Rev 9
41/125
46
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
TIM2/TIM15/
TIM16/TIM17/
EVENT
TIM1/TIM3/
TIM15/
TIM16
HRTIM1/TSC
I2C1/TIM1
SPI1/
Infrared
TIM1/
Infrared
USART1/USA
RT2/USART3/
GPCOMP6
GPCOMP2/
GPCOMP4/
GPCOMP6
CAN/TIM1/
TIM15
TIM2/TIM3/TI
M17
TIM1
HRTIM1/
TIM1
HRTIM1/
OPAMP2
-
EVENT
PA0
-
TIM2_CH1/TI
M2_ETR
-
TSC_G1_IO1
-
-
-
USART2_CTS
-
-
-
-
-
-
-
EVENTOUT
PA1
-
TIM2_CH2
-
TSC_G1_IO2
-
-
-
USART2_RTS
_DE
-
TIM15_CH1N
-
-
-
-
-
EVENTOUT
Port
Port A
-
TIM2_CH3
-
TSC_G1_IO3
-
-
-
USART2_TX
COMP2_OUT
TIM15_CH1
-
-
-
-
-
EVENTOUT
PA3
-
TIM2_CH4
-
TSC_G1_IO4
-
-
-
USART2_RX
-
TIM15_CH2
-
-
-
-
-
EVENTOUT
PA4
-
-
TIM3_CH2
TSC_G2_IO1
-
SPI1_NSS
-
USART2_CK
-
-
-
-
-
-
-
EVENTOUT
PA5
-
TIM2_CH1/TI
M2_ETR
-
TSC_G2_IO2
-
SPI1_SCK
-
-
-
-
-
-
-
-
-
EVENTOUT
PA6
-
TIM16_CH1
TIM3_CH1
TSC_G2_IO3
-
SPI1_MISO
TIM1_BKIN
-
-
-
-
-
-
OPAMP2_DIG
-
EVENTOUT
PA7
-
TIM17_CH1
TIM3_CH2
TSC_G2_IO4
-
SPI1_MOSI
TIM1_CH1N
-
-
-
-
-
-
-
-
EVENTOUT
PA8
MCO
-
-
-
-
-
TIM1_CH1
USART1_CK
-
-
-
-
-
HRTIM1_CHA1
-
EVENTOUT
PA9
-
-
-
TSC_G4_IO1
-
-
TIM1_CH2
USART1_TX
-
TIM15_BKIN
TIM2_CH3
-
-
HRTIM1_CHA2
-
EVENTOUT
PA10
-
TIM17_BKIN
-
TSC_G4_IO2
-
-
TIM1_CH3
USART1_RX
COMP6_OUT
-
TIM2_CH4
-
-
HRTIM1_CHB1
-
EVENTOUT
PA11
-
-
-
-
-
-
TIM1_CH1N
USART1_CTS
-
CAN_RX
-
TIM1_CH4
TIM1_BKIN2
HRTIM1_CHB2
-
EVENTOUT
PA12
-
TIM16_CH1
-
-
-
-
TIM1_CH2N
USART1_RTS
_DE
COMP2_OUT
CAN_TX
-
TIM1_ETR
-
HRTIM1_FLT1
-
EVENTOUT
PA13
JTMS/SWDAT
TIM16_CH1N
-
TSC_G4_IO3
-
IR_OUT
-
USART3_CTS
-
-
-
-
-
-
-
EVENTOUT
PA14
JTCK/SWCLK
-
-
TSC_G4_IO4
I2C1_SDA
-
TIM1_BKIN
USART2_TX
-
-
-
-
-
-
-
EVENTOUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
-
TSC_SYNC
I2C1_SCL
SPI1_NSS
-
USART2_RX
-
TIM1_BKIN
-
-
-
HRTIM1_FLT2
-
EVENTOUT
PB0
-
-
TIM3_CH3
TSC_G3_IO2
-
-
TIM1_CH2N
-
-
-
-
-
-
-
-
EVENTOUT
PB1
-
-
TIM3_CH4
TSC_G3_IO3
-
-
TIM1_CH3N
-
COMP4_OUT
-
-
-
-
HRTIM1_SCOUT
-
EVENTOUT
PB2
-
-
-
TSC_G3_IO4
-
-
-
-
-
-
-
-
-
HRTIM1_SCIN
-
EVENTOUT
PB3
JTDO/TRACE
SWO
TIM2_CH2
-
TSC_G5_IO1
-
SPI1_SCK
-
USART2_TX
-
-
TIM3_ETR
-
HRTIM1_
SCOUT
HRTIM1_EEV9
-
EVENTOUT
PB4
NJTRST
TIM16_CH1
TIM3_CH1
TSC_G5_IO2
-
SPI1_MISO
-
USART2_RX
-
-
TIM17_BKIN
-
-
HRTIM1_EEV7
-
EVENTOUT
PB5
-
TIM16_BKIN
TIM3_CH2
-
I2C1_SMBA
SPI1_MOSI
-
USART2_CK
-
-
TIM17_CH1
-
-
HRTIM1_EEV6
-
EVENTOUT
PB6
-
TIM16_CH1N
-
TSC_G5_IO3
I2C1_SCL
-
-
USART1_TX
-
-
-
-
HRTIM1_
SCIN
HRTIM1_EEV4
-
EVENTOUT
PB7
-
TIM17_CH1N
-
TSC_G5_IO4
I2C1_SDA
-
-
USART1_RX
-
-
TIM3_CH4
-
-
HRTIM1_EEV3
-
EVENTOUT
PB8
-
TIM16_CH1
-
TSC_SYNC
I2C1_SCL
-
-
USART3_RX
-
CAN_RX
-
-
TIM1_BKIN
HRTIM1_EEV8
-
EVENTOUT
PB9
-
TIM17_CH1
-
-
I2C1_SDA
-
IR_OUT
USART3_TX
COMP2_OUT
CAN_TX
-
-
-
HRTIM1_EEV5
-
EVENTOUT
Port B
STM32F334x4 STM32F334x6 STM32F334x8
DS9994 Rev 9
PA2
Pinout and pin descriptions
42/125
Table 14. Alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
TIM2/TIM15/
TIM16/TIM17/
EVENT
TIM1/TIM3/
TIM15/
TIM16
HRTIM1/TSC
I2C1/TIM1
SPI1/
Infrared
TIM1/
Infrared
USART1/USA
RT2/USART3/
GPCOMP6
GPCOMP2/
GPCOMP4/
GPCOMP6
CAN/TIM1/
TIM15
TIM2/TIM3/TI
M17
TIM1
HRTIM1/
TIM1
HRTIM1/
OPAMP2
-
EVENT
PB10
-
TIM2_CH3
-
TSC_SYNC
-
-
-
USART3_TX
-
-
-
-
-
HRTIM1_FLT3
-
EVENTOUT
PB11
-
TIM2_CH4
-
TSC_G6_IO1
-
-
-
USART3_RX
-
-
-
-
-
HRTIM1_FLT4
-
EVENTOUT
PB12
-
-
-
TSC_G6_IO2
-
-
TIM1_BKIN
USART3_CK
-
-
-
-
-
HRTIM1_CHC1
-
EVENTOUT
PB13
-
-
-
TSC_G6_IO3
-
-
TIM1_CH1N
USART3_CTS
-
-
-
-
-
HRTIM1_CHC2
-
EVENTOUT
PB14
-
TIM15_CH1
-
TSC_G6_IO4
-
-
TIM1_CH2N
USART3_RTS
_DE
-
-
-
-
-
HRTIM1_CHD1
-
EVENTOUT
PB15
-
TIM15_CH2
TIM15_CH1N
-
TIM1_CH3N
-
-
-
-
-
-
-
-
HRTIM1_CHD2
-
EVENTOUT
PC0
-
EVENTOUT
TIM1_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC2
-
EVENTOUT
TIM1_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
PC3
-
EVENTOUT
TIM1_CH4
-
-
-
TIM1_BKIN2
-
-
-
-
-
-
-
-
-
Port
Port B
DS9994 Rev 9
Port C
-
EVENTOUT
TIM1_ETR
-
-
-
-
USART1_TX
-
-
-
-
-
-
-
-
PC5
-
EVENTOUT
TIM15_BKIN
TSC_G3_IO1
-
-
-
USART1_RX
-
-
-
-
-
-
-
-
PC6
-
EVENTOUT
TIM3_CH1
HRTIM1_
EEV10
-
-
-
COMP6_OUT
-
-
-
-
-
-
-
-
PC7
-
EVENTOUT
TIM3_CH2
HRTIM1_FLT5
-
-
-
-
-
-
-
-
-
-
-
-
PC8
-
EVENTOUT
TIM3_CH3
HRTIM1_CHE1
-
-
-
-
-
-
-
-
-
-
-
-
PC9
-
EVENTOUT
TIM3_CH4
HRTIM1_CHE2
-
-
-
-
-
-
-
-
-
-
-
-
PC10
-
EVENTOUT
-
-
-
-
-
USART3_TX
-
-
-
-
-
-
-
-
PC11
-
EVENTOUT
-
HRTIM1_EEV2
-
-
-
USART3_RX
-
-
-
-
-
-
-
-
PC12
-
EVENTOUT
-
HRTIM1_EEV1
-
-
-
USART3_CK
-
-
-
-
-
-
-
-
PC13
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD2
-
EVENTOUT
TIM3_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
PF0
-
-
-
-
-
-
TIM1_CH3N
-
-
-
-
-
-
-
-
-
PF1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port F
43/125
Pinout and pin descriptions
Port D
PC4
STM32F334x4 STM32F334x6 STM32F334x8
Table 14. Alternate functions (continued)
Memory mapping
5
STM32F334x4 STM32F334x6 STM32F334x8
Memory mapping
Figure 9. STM32F334x4/6/8 memory map
0x5000 03FF
AHB3
0xFFFF FFFF
7
Cortex-M4
with FPU
Internal
Peripherals
0xE000 0000
0x5000 0000
Reserved
0x4800 1800
AHB2
0x4800 0000
Reserved
6
0x4002 43FF
AHB1
0xC000 0000
0x4002 0000
Reserved
5
0x4001 6C00
APB2
0xA000 0000
0x4001 0000
Reserved
4
0x4000 A000
APB1
0x8000 0000
0x4000 0000
3
0x1FFF FFFF
Option bytes
0x6000 0000
0x1FFF F800
System memory
2
0x1FFF D800
Reserved
0x4000 0000
Peripherals
0x1000 1000
CCM RAM
0x1000 0000
Reserved
1
0x2000 0000
0
0x0801 0000
SRAM
Flash memory
0x0800 0000
CODE
Reserved
0x0001 0000
0x0000 0000
Reserved
0x0000 0000
Flash, system
memory or SRAM,
depending on BOOT
configuration
MSv33150V1
44/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
-
Memory mapping
Table 15. STM32F334x4/6/8 peripheral register boundary addresses
Bus
Boundary address
Size
(bytes)
Peripheral
AHB3
0x5000 0000 - 0x5000 03FF
1K
-
0x4800 1800 - 0x4FFF FFFF
~132 M
AHB2
0x4800 1400 - 0x4800 17FF
1K
GPIOF
-
0x4800 1000 - 0x4800 13FF
1K
Reserved
0x4800 0C00 - 0x4800 0FFF
1K
GPIOD
0x4800 0800 - 0x4800 0BFF
1K
GPIOC
0x4800 0400 - 0x4800 07FF
1K
GPIOB
0x4800 0000 - 0x4800 03FF
1K
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 M
0x4002 4000 - 0x4002 43FF
1K
TSC
0x4002 3400 - 0x4002 3FFF
3K
Reserved
0x4002 3000 - 0x4002 33FF
1K
CRC
0x4002 2400 - 0x4002 2FFF
3K
Reserved
0x4002 2000 - 0x4002 23FF
1K
Flash interface
0x4002 1400 - 0x4002 1FFF
3K
Reserved
0x4002 1000 - 0x4002 13FF
1K
RCC
0x4002 0400 - 0x4002 0FFF
3K
Reserved
0x4002 0000 - 0x4002 03FF
1K
DMA1
-
0x4001 8000 - 0x4001 FFFF
32 K
Reserved
APB2
0x4001 7400 - 0x4001 77FF
1K
HRTIM1
0x4001 4C00 - 0x4001 73FF
12 K
Reserved
0x4001 4800 - 0x4001 4BFF
1K
TIM17
0x4001 4400 - 0x4001 47FF
1K
TIM16
0x4001 4000 - 0x4001 43FF
1K
TIM15
0x4001 3C00 - 0x4001 3FFF
1K
Reserved
0x4001 3800 - 0x4001 3BFF
1K
USART1
0x4001 3400 - 0x4001 37FF
1K
Reserved
0x4001 3000 - 0x4001 33FF
1K
SPI1
0x4001 2C00 - 0x4001 2FFF
1K
TIM1
0x4001 0800 - 0x4001 2BFF
9K
Reserved
0x4001 0400 - 0x4001 07FF
1K
EXTI
0x4001 0000 - 0x4001 03FF
1K
SYSCFG + COMP + OPAMP
0x4000 9C00 - 0x4000 FFFF
25 K
Reserved
AHB2
-
AHB1
APB2
-
DS9994 Rev 9
ADC1 - ADC2
Reserved
Reserved
45/125
46
Memory mapping
STM32F334x4 STM32F334x6 STM32F334x8
Table 15. STM32F334x4/6/8 peripheral register boundary addresses (continued)
Bus
APB1
46/125
Boundary address
Size
(bytes)
Peripheral
0x4000 9800 - 0x4000 9BFF
1K
DAC2
0x4000 7800 - 0x4000 97FF
8K
Reserved
0x4000 7400 - 0x4000 77FF
1K
DAC1
0x4000 7000 - 0x4000 73FF
1K
PWR
0x4000 6800 - 0x4000 6FFF
2K
Reserved
0x4000 6400 - 0x4000 67FF
1K
bxCAN
0x4000 5800 - 0x4000 63FF
3K
Reserved
0x4000 5400 - 0x4000 57FF
1K
I2C1
0x4000 4C00 - 0x4000 53FF
2K
Reserved
0x4000 4800 - 0x4000 4BFF
1K
USART3
0x4000 4400 - 0x4000 47FF
1K
USART2
0x4000 3400 - 0x4000 43FF
2K
Reserved
0x4000 3000 - 0x4000 33FF
1K
IWDG
0x4000 2C00 - 0x4000 2FFF
1K
WWDG
0x4000 2800 - 0x4000 2BFF
1K
RTC
0x4000 1800 - 0x4000 27FF
4K
Reserved
0x4000 1400 - 0x4000 17FF
1K
TIM7
0x4000 1000 - 0x4000 13FF
1K
TIM6
0x4000 0800 - 0x4000 0FFF
2K
Reserved
0x4000 0400 - 0x4000 07FF
1K
TIM3
0x4000 0000 - 0x4000 03FF
1K
TIM2
-
0x2000 3000 - 3FFF FFFF
-
0x2000 0000 - 0x2000 2FFF
12 K
SRAM
-
0x1FFF F800 - 0x1FFF FFFF
2K
Option bytes
-
0x1FFF D800 - 0x1FFF F7FF
8K
System memory
-
0x1000 2000 - 0x1FFF D7FF
~256 M
Reserved
-
0x1000 0000 - 0x1000 0FFF
4K
CCM RAM
-
0x0804 0000 - 0x0FFF FFFF
~128 M
Reserved
-
0x0800 0000 - 0x0800 FFFF
64 K
-
0x0004 0000 - 0x07FF FFFF
~128 M
-
0x0000 000 - 0x0000 FFFF
DS9994 Rev 9
~512 M
64 K
Reserved
Main Flash memory
Reserved
Main Flash memory, system
memory or SRAM depending
on BOOT configuration
STM32F334x4 STM32F334x6 STM32F334x8
6
Electrical characteristics
6.1
Parameter conditions
Electrical characteristics
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V, VDDA =
3.3 V. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5
Input voltage on a pin
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
DS9994 Rev 9
MS19211V1
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103
Electrical characteristics
6.1.6
STM32F334x4 STM32F334x6 STM32F334x8
Power-supply scheme
Figure 12. Power-supply scheme
VBAT
GPIOs
IN
VDD
4xV
DD
VDDA
Level shifter
OUT
4 x 100 nF
+ 1 x 4.7 μF
Backup circuitry
(LSE, RTC,
Wake-up logic
Backup registers)
Power
switch
1.65 - 3.6V
I/O
Logic
Kernel logic
(CPU,
digital
& memories)
Regulator
4xV
SS
VDDA
10 nF
+ 1 μF
VREF+
VREF-
ADC/
DAC
Analog such as RCs, PLL,
comparators, OPAMP
VSSA
MS31954V1
Caution:
48/125
Each power-supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to or below the appropriate pins on the underside of the PCB, to ensure the good
functionality of the device.
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
6.1.7
Electrical characteristics
Measurement of the current consumption
Figure 13. Scheme of the current-consumption measurement
I DD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS19213V1
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103
Electrical characteristics
6.2
STM32F334x4 STM32F334x6 STM32F334x8
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics,
Table 17: Current characteristics, and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect the device reliability.
Table 16. Voltage characteristics(1)
Symbol
Ratings
Min.
Max.
VDD–VSS
External main supply voltage (including VDDA, VBAT
and VDD)
-0.3
4.0
-
0.4
Input voltage on FT and FTf pins
VSS −0.3
VDD + 4.0
Input voltage on TTa and TT pins
VSS −0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
Input voltage on Boot0 pin
0
9
Variations between different VDD power pins
-
50
Variations between all the different ground pins(3)
-
50
VDD–VDDA
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Allowed voltage difference for VDD > VDDA
Electrostatic discharge voltage (human body model)
Unit
V
mV
see Section 6.3.12: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD:
VDDA must power on before or at the same time as VDD in the power up sequence.
VDDA must be greater than or equal to VDD.
2. VIN maximum must always be respected. Refer to Table 17: Current characteristics for the maximum allowed injected
current values.
3. Include VREF- pin.
50/125
DS9994 Rev 9
-
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 17. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
140
ΣIVSS
(1)
-140
Total current out of sum of all VSS ground lines (sink)
(1)
IVDD
Maximum current into each VDD power line (source)
IVSS
Maximum current out of each VSS _x ground line (sink)(1)
100
Output current sunk by any I/O and control pin
25
IIO(PIN)
ΣIIO(PIN)
Injected current on TC and RST
Injected current on TTa pins
ΣIINJ(PIN)
-25
(2)
mA
80
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on TT, FT, FTf and B
IINJ(PIN)
100
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins
Unit
-80
pins(3)
-5 /+0
pin(4)
±5
(5)
±5
Total injected current (sum of all I/O and control pins)(6)
±25
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer to Table 16: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 16: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note 2.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 18. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DS9994 Rev 9
Value
Unit
–65 to +150
°C
150
°C
51/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
6.3
Operating conditions
6.3.1
General operating conditions
Table 19. General operating conditions
Symbol
Parameter
Conditions
Min.
Max.
Unit
fHCLK
Internal AHB clock frequency
-
0
72
fPCLK1
Internal APB1 clock frequency
-
0
36
fPCLK2
Internal APB2 clock frequency
-
0
72
Standard operating voltage
-
2
3.6
Core, SRAM and Flash memory
power supply
-
1.65
1.95
2
3.6
2.4
3.6
1.65
3.6
TC I/O
–0.3
VDD+0.3
TT I/O
-0.3
3.6
–0.3
VDDA+0.3
–0.3
5.5
BOOT0
0
5.5
LQFP64
-
444
mW
-
364
mW
-
333
mW
-
540
mW
-
414
mW
–40
85
–40
105
–40
105
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
VDD
VDD18
VDDA
VBAT
VIN
PD
Analog operating voltage
(OPAMP and DAC not used)
Analog operating voltage
(OPAMP and DAC used)
Must have a potential equal to
or higher than VDD
Backup operating voltage
I/O input voltage
-
TTa I/O
FT and FTf
I/O(1)
LQFP48
Power dissipation at TA = 85 °C for
LQFP32
suffix 6 or TA = 105 °C for suffix
7(2)
UFQFPN32
WLCSP49
Ambient temperature for 6 suffix
version
Maximum power dissipation
Ambient temperature for 7 suffix
version
Maximum power dissipation
TA
TJ
Junction temperature range
Low power dissipation
Low power dissipation
(3)
(3)
MHz
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 81: Package thermal
characteristics).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7:
Thermal characteristics).
52/125
DS9994 Rev 9
V
V
V
°C
°C
°C
STM32F334x4 STM32F334x6 STM32F334x8
6.3.2
Electrical characteristics
Operating conditions at power-up / power-down
The parameters given in Table 20 are derived from tests performed under the ambient
temperature condition summarized in Table 19.
Table 20. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
tVDD
-
VDD fall time rate
VDDA rise time rate
tVDDA
6.3.3
Conditions
Max.
Unit
0
∞
∞
∞
∞
µs/V
20
0
-
VDDA fall time rate
Min.
20
Characteristics of the embedded reset and power-control block
The parameters given in Table 21 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 19.
Table 21. Embedded reset and power control block characteristics
Symbol
VPOR/PDR(1)
VPDRhyst
(1)
tRSTTEMPO(3)
Parameter
Conditions
Power on/power down
reset threshold
Min.
Typ. Max.
Unit
Falling edge
1.8(2) 1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
PDR hysteresis
-
-
40
-
mV
POR reset
temporization
-
1.5
2.5
4.5
ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 22. Programmable voltage detector characteristics
Symbol
Parameter
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
Conditions
Min.(1)
Typ.
Max.(1)
Rising edge
2.1
2.18
2.26
Falling edge
2
2.08
2.16
Rising edge
2.19
2.28
2.37
Falling edge
2.09
2.18
2.27
Rising edge
2.28
2.38
2.48
Falling edge
2.18
2.28
2.38
Rising edge
2.38
2.48
2.58
Falling edge
2.28
2.38
2.48
Rising edge
2.47
2.58
2.69
Falling edge
2.37
2.48
2.59
Rising edge
2.57
2.68
2.79
Falling edge
2.47
2.58
2.69
Rising edge
2.66
2.78
2.9
Falling edge
2.56
2.68
2.8
Rising edge
2.76
2.88
3
Falling edge
2.66
2.78
2.9
Unit
V
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst(2)
PVD hysteresis
-
-
100
-
mV
IDD(PVD)
PVD current
consumption
-
-
0.15
0.26
µA
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 23 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 19.
Table 23. Embedded internal reference voltage
Symbol
Parameter
Conditions
Typ.
Max.
Unit
VREFINT
Internal reference voltage –40 °C < TA < +105 °C
1.20
1.23
1.25
V
TS_vrefint
ADC sampling time when
reading the internal
reference voltage
-
2.2
-
-
µs
VRERINT
Internal reference voltage
spread over the
temperature range
VDD = 31.8 V ±10 mV
-
-
10(1)
mV
-
-
-
100(1) ppm/°C
TCoeff
Temperature coefficient
1. Guaranteed by design, not tested in production.
54/125
Min.
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 24. Internal reference voltage calibration values
Calibration value name
VREFINT_CAL
6.3.5
Description
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
Memory address
0x1FFF F7BA - 0x1FFF F7BB
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Scheme of the currentconsumption measurement.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Note:
The total current consumption is the sum of the IDD and IDDA values.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
•
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2
•
When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
The parameters given in Table 25 to Table 29 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 19.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V
All peripherals enabled
Symbol Parameter Conditions
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
fHCLK
Typ.
Max. @
TA(1)
25 °C
85 °C
105 °C
All peripherals disabled
Typ.
25 °C
85 °C
105 °C
72 MHz
71.4
77.9
79.1
80.0
27.1
32.2
32.4
32.4
64 MHz
63.9
70.6
71.3
71.5
24.2
27.0
27.5
27.7
48 MHz
49.5
56.6
57.1
57.7
18.7
21.4
21.6
21.9
32 MHz
34.0
38.6
38.9
39.2
12.9
14.6
14.9
15.9
24 MHz
25.9
30.2
30.4
30.6
10.0
11.1
11.2
12.3
8 MHz
9.3
14.1
14.3
14.4
3.3
4.0
4.4
5.1
1 MHz
3.5
8.9
9.1
9.5
0.7
0.9
1.0
1.2
64 MHz
61.6
68.1
68.8
70.1
24.1
27.0
27.1
27.2
48 MHz
48.1
54.6
54.8
55.1
18.6
21.6
21.7
21.9
32 MHz
33.3
37.8
37.9
38.0
12.7
14.4
14.9
16.0
24 MHz
25.7
29.8
29.8
30.0
10.0
11.1
11.2
12.3
8 MHz
9.7
12.2
12.3
12.8
3.4
3.8
4.2
5.0
72 MHz
71.3
77.8
78.7
78.9
27.6
32.1
32.2
32.3
64 MHz
63.8
70.5
70.7
70.9
24.5
27.2
27.6
27.7
48 MHz
49.3
56.5
56.9
57.4
18.1
21.6
21.8
21.8
32 MHz
33.9
37.7
37.9
38.0
12.9
14.9
14.9
15.9
24 MHz
25.8
28.8
29.0
29.2
9.8
11.1
11.3
11.5
8 MHz
9.0
13.2
13.3
13.8
3.2
3.6
4.0
4.6
1 MHz
3.2
7.6
7.8
8.0
0.3
0.4
0.8
1.2
64 MHz
61.3
66.9
67.3
67.8
24.1
26.9
27.0
27.1
48 MHz
48.0
52.4
52.6
53.1
19.1
21.6
21.6
22.1
32 MHz
33.1
35.6
35.8
36.6
12.6
14.8
14.9
15.9
24 MHz
25.6
28.5
28.7
28.8
9.8
11.1
11.3
11.5
8 MHz
9.7
11.6
11.6
11.7
3.0
3.1
4.1
4.7
72 MHz
55.5
58.7
61.1
61.9
7.0
7.3
8.4
8.5
64 MHz
49.8
52.7
54.5
54.8
6.3
6.7
7.0
7.8
48 MHz
38.5
40.6
41.7
41.8
4.6
5.1
5.6
5.9
32 MHz
26.9
28.8
29.2
29.5
3.0
3.3
4.0
4.5
24 MHz
19.1
23.2
23.7
23.9
2.4
2.5
3.2
3.8
8 MHz
7.1
11.5
11.7
11.9
0.6
0.9
1.2
2.1
1 MHz
3.0
7.4
7.7
7.9
0.3
0.3
0.4
1.2
64 MHz
47.7
52.4
52.6
52.8
5.4
6.5
6.8
7.5
48 MHz
35.0
40.4
40.6
40.8
4.3
4.7
5.2
5.7
32 MHz
23.7
27.7
28.3
28.8
2.9
3.1
3.2
4.4
24 MHz
18.5
23.8
24.0
24.2
1.3
1.7
2.2
2.7
8 MHz
7.5
9.6
9.7
9.7
0.5
0.7
1.1
2.0
1. Data based on characterization results, not tested in production unless otherwise specified.
56/125
Max. @ TA(1)
DS9994 Rev 9
Unit
mA
mA
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 26. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol Parameter
IDDA
Supply
current in
Run/Sleep
mode,
code
executing
from Flash
or RAM
Conditions
(1)
HSE
bypass
HSI clock
fHCLK
Typ.
Max. @
25 °C
VDDA = 3.6 V
TA(2)
85 °C 105 °C
Typ.
Max. @ TA(2)
25 °C
Unit
85 °C 105 °C
72 MHz
224
252
265
269
245
272
288
295
64 MHz
196
225
237
241
214
243
257
263
48 MHz
147
174
183
186
159
186
196
201
32 MHz
100
126
133
135
109
133
142
145
24 MHz
79
102
107
108
85
108
113
116
8 MHz
3
5
5
6
4
6
6
7
1 MHz
3
5
5
6
3
5
6
6
64 MHz
259
288
304
309
285
315
332
338
48 MHz
208
239
251
254
230
258
271
277
32 MHz
162
190
198
202
179
206
216
219
24 MHz
140
168
175
178
155
181
188
191
8 MHz
62
85
88
89
71
94
96
98
µA
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
Table 27. Typical and maximum VDD consumption in Stop and Standby modes
Symbol Parameter
Typ. @VDD (VDD=VDDA)
Max.(1)
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
TA = TA = TA =
25 °C 85 °C 105 °C
17.51 17.68 17.84 18.17 18.57 19.39
30.6
232.5
612.2
6.44
6.51
6.60
6.73
6.96
7.20
20.0
246.4
585.0
LSI ON and
IWDG ON
0.73
0.89
1.02
1.14
1.28
1.44
-
-
-
LSI OFF and
IWDG OFF
0.55
0.66
0.75
0.85
0.93
1.01
4.9
7.0
7.9
Conditions
Regulator in run
mode, all
oscillators OFF
IDD
Supply
current in
Stop mode Regulator in lowpower mode, all
oscillators OFF
Supply
current in
Standby
mode
Unit
µA
1. Data based on characterization results, not tested in production unless otherwise specified.
DS9994 Rev 9
57/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 28. Typical and maximum VDDA consumption in Stop and Standby modes
Symbo
Parameter
l
Supply
current in
Standby
mode
Conditions
VDDA supervisor ON
Supply
current in
Stop mode
Supply
current in
Standby
mode
VDDA supervisor OFF
IDDA
Supply
current in
Stop mode
Max.(1)
Typ. @VDD (VDD = VDDA)
TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C
Regulator in
run/low-power
mode, all
oscillators OFF
1.67
1.79
1.91
2.04
2.19
2.35
2.5
5.9
6.2
LSI ON and
IWDG ON
2.06
2.24
2.41
2.60
2.80
3.04
-
-
-
LSI OFF and
IWDG OFF
1.54
1.68
1.78
1.92
2.06
2.22
2.6
3.0
3.8
Regulator in
run/low-power
mode, all
oscillators OFF
0.97
0.99
1.03
1.07
1.14
1.22
-
-
-
LSI ON and
IWDG ON
1.36
1.44
1.52
1.62
1.76
1.91
-
-
-
LSI OFF and
IWDG OFF
0.86
0.88
0.91
0.95
1.03
1.09
-
-
-
Uni
t
µA
1. Data based on characterization results, not tested in production.
Table 29. Typical and maximum current consumption from VBAT supply
Symbol
Para
meter
Max.
@VBAT= 3.6V(2)
Typ.@VBAT
Conditions
(1)
1.65V 1.8V
LSE & RTC
ON; “Xtal
mode” lower
driving
capability;
Backup LSEDRV[1:0]
domain = '00'
IDD_VBAT
supply LSE & RTC
current ON; “Xtal
mode” higher
driving
capability;
LSEDRV[1:0]
= '11'
0.42
2V
2.4V 2.7V
0.44 0.47 0.54
3V
0.60 0.66 0.74 0.82
-
-
-
µA
0.71
0.74 0.77 0.85
0.91 0.98 1.06 1.16
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
58/125
Unit
TA=
TA= TA=
3.3V 3.6V
25°C 85°C 105°C
DS9994 Rev 9
-
-
-
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Figure 14. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
1.40
1.20
1.65 V
1.00
I VBAT (μA)
1.8 V
0.80
2V
2.4 V
0.60
2.7 V
0.40
3V
0.20
3.3 V
3.6 V
0.00
25°C
60°C
85°C
105°C
TA (°C)
MS34525V1
Typical current consumption
The MCU is placed under the following conditions:
•
VDD = VDDA = 3.3 V
•
All I/O pins available on each package are in analog input configuration
•
The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
•
When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
•
PLL is used for frequencies greater than 8 MHz
•
AHB prescaler of 2, 4, 8, 16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
•
Typical current consumption in Run mode, code with data processing running from
Flash
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 30. Typical current consumption in Run mode, code with data processing
running from Flash memory
Typ.
Symbol
IDD
Parameter
Conditions
fHCLK
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash memory
IDDA(1) (2)
Supply current in
Run mode from
VDDA supply
Peripherals
enabled
Peripherals
disabled
72 MHz
70.6
25.2
64 MHz
60.3
22.6
48 MHz
46.0
17.3
32 MHz
31.3
12.0
24 MHz
25.0
9.3
16 MHz
16.2
6.5
8 MHz
8.4
3.55
4 MHz
4.75
2.21
2 MHz
2.81
1.52
1 MHz
1.82
1.17
500 kHz
1.34
0.94
125 kHz
0.93
0.82
72 MHz
240.0
234.0
64 MHz
209.9
208.6
48 MHz
154.5
153.5
32 MHz
104.1
103.6
24 MHz
80.2
80.0
16 MHz
56.8
56.6
8 MHz
1.14
1.14
4 MHz
1.14
1.14
2 MHz
1.14
1.14
1 MHz
1.14
1.14
500 kHz
1.14
1.14
125 kHz
1.14
1.14
Unit
mA
µA
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp and others, is not included. Refer to the tables of characteristics in the subsequent sections.
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Electrical characteristics
Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ.
Symbol
IDD
Parameter
Conditions
fHCLK
Supply current in
Sleep mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
IDDA(1) (2)
Supply current in
Sleep mode from
VDDA supply
Peripherals
enabled
Peripherals
disabled
72 MHz
51.8
6.3
64 MHz
46.4
5.7
48 MHz
35.0
4.40
32 MHz
23.7
3.13
24 MHz
18.0
2.49
16 MHz
12.2
1.85
8 MHz
6.2
0.99
4 MHz
3.68
0.88
2 MHz
2.26
0.80
1 MHz
1.55
0.76
500 kHz
1.20
0.74
125 kHz
0.89
0.72
72 MHz
239.0
236.7
64 MHz
209.4
207.8
48 MHz
154.0
152.9
32 MHz
103.7
103.2
24 MHz
80.1
79.8
16 MHz
56.7
56.6
8 MHz
1.14
1.14
4 MHz
1.14
1.14
2 MHz
1.14
1.14
1 MHz
1.14
1.14
500 kHz
1.14
1.14
125 kHz
1.14
1.14
Unit
mA
µA
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp and others, is not included. Refer to the tables of characteristics in the subsequent sections.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
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Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins that must be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
where:
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS
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DS9994 Rev 9
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Electrical characteristics
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 32. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDD = 3.3 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 10 pF
C = CINT + CEXT +CS
ISW
I/O current
consumption
VDD = 3.3 V
Cext = 22 pF
C = CINT + CEXT +CS
VDD = 3.3 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 47 pF
C = CINT + CEXT+ CS
I/O toggling
frequency (fSW)
Typ.
2 MHz
0.90
4 MHz
0.93
8 MHz
1.16
18 MHz
1.60
36 MHz
2.51
2 MHz
0.93
4 MHz
1.06
8 MHz
1.47
18 MHz
2.26
36 MHz
3.39
2 MHz
1.03
4 MHz
1.30
8 MHz
1.79
18 MHz
3.01
36 MHz
5.99
2 MHz
1.10
4 MHz
1.31
8 MHz
2.06
18 MHz
3.47
36 MHz
8.35
2 MHz
1.20
4 MHz
1.54
8 MHz
2.46
18 MHz
4.51
36 MHz
9.98
Unit
mA
1. CS = 5 pF (estimated value).
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input configuration
•
All peripherals are disabled unless otherwise mentioned
•
The given value is calculated by measuring the current consumption:
•
–
With all peripherals clocked off
–
With only one peripheral clocked on
Ambient operating temperature at 25°C and VDD = VDDA = 3.3 V
Table 33. Peripheral current consumption
Typical consumption(1)
Peripheral
Unit
IDD
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BusMatrix (2)
11.1
DMA1
8.0
CRC
2.1
GPIOA
8.7
GPIOB
8.4
GPIOC
8.4
GPIOD
2.6
GPIOF
1.7
TSC
4.7
ADC1&2
17.4
APB2-Bridge (3)
3.3
SYSCFG
4.2
TIM1
32.3
USART1
20.3
TIM15
13.8
TIM16
9.7
TIM17
10.3
HRTIM
324.2
APB1-Bridge (3)
5.3
TIM2
43.4
TIM3
34.0
TIM6
9.7
TIM7
10.3
WWDG
6.9
USART2
18.8
USART3
19.1
DS9994 Rev 9
µA/MHz
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 33. Peripheral current consumption (continued)
Typical consumption(1)
Peripheral
Unit
IDD
I2C1
13.3
CAN
31.3
PWR
4.7
DAC
15.4
DAC2
8.6
SPI1
8.2
µA/MHz
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
and others, is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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103
Electrical characteristics
6.3.6
STM32F334x4 STM32F334x6 STM32F334x8
Wakeup time from low-power mode
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
For Stop or Sleep mode: the wakeup event is WFE.
•
WKUP1 (PA0) pin is used to wake up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 19.
Table 34. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from
Stop mode
tWUSTOP
Typ. @VDD, VDD = VDDA
Conditions
Max.
2.0 V
2.4 V
2.7 V
3V
3.3 V
3.6 V
Regulator in
run mode
4.3
4.1
4.0
3.9
3.8
3.7
4.5
Regulator in
low-power
mode
7.8
6.7
6.1
5.9
5.5
5.3
9
74.4
64.3
60.0
56.9
54.3
51.1
103
tWUSTANDBY(1)
Wakeup from LSI and
Standby mode IWDG OFF
tWUSLEEP
Wakeup from
Sleep mode
-
6
-
Unit
µs
CPU
clock
cycles
1. Data based on characterization results, not tested in production.
Table 35. Wakeup time using USART(1)
Symbol
Parameter
tWUUSART
Wakeup time needed to calculate
the maximum USART baudrate
allowing to wake up from stop
mode when USART clock source is
HSI
Conditions
Typ
Max
Stop mode with main
regulator in low
power mode
-
13.125
Stop mode with main
regulator in run
mode
-
Unit
µs
3.125
1. Guaranteed by design.
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 15.
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Electrical characteristics
Table 36. High-speed external user clock characteristics
Symbol
Parameter
Conditions
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high-level voltage
VHSEL
OSC_IN input pin low-level voltage
tw(HSEH)
tw(HSEL)
tr(HSE)
tf(HSE)
Min.
Typ.
Max.
Unit
1
8
32
MHz
0.7VDD
-
VDD
VSS
-
0.3VDD
15
-
-
-
OSC_IN high or low time(1)
V
ns
(1)
OSC_IN rise or fall time
-
-
20
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
t
tw(HSEL)
THSE
MS19214V2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 16.
Table 37. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high-level
voltage
VLSEL
OSC32_IN input pin low-level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time(1)
tr(LSE)
tf(LSE)
Min.
Typ.
Max.
Unit
-
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
450
-
ns
OSC32_IN rise or fall
time(1)
-
-
50
1. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 16. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
VLSEL
10%
tr(LSE)
t
tf(LSE)
tw(LSEL)
TLSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 38. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 38. HSE oscillator characteristics
Conditions(1)
Min.(2)
Typ.
Max.(2)
Unit
Oscillator frequency
-
4
8
32
MHz
Feedback resistor
-
-
200
-
kΩ
During startup(3)
-
-
8.5
VDD= 3.3 V, Rm= 30Ω,
CL=10 pF@8 MHz
-
0.4
-
VDD= 3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz
-
0.5
-
VDD= 3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz
-
0.8
-
VDD= 3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
-
1
-
VDD= 3.3 V, Rm= 30Ω,
CL=20 pF@32 MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
Symbol
Parameter
fOSC_IN
RF
IDD
gm
tSU(HSE)(4)
HSE current consumption
Oscillator transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
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Electrical characteristics
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 17. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
8 MHz
resonator
CL2
fHSE
RF
Bias
controlled
gain
OSC_OUT
REXT (1)
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
Parameter
LSE current consumption
Conditions(1)
Min.(2)
Typ.
Max.(2)
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]=10
medium low driving
capability
-
-
1
LSEDRV[1:0]=01
medium high-driving
capability
-
-
1.3
LSEDRV[1:0]=11
higher-driving capability
-
-
1.6
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Unit
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) (continued)
Symbol
gm
Conditions(1)
Min.(2)
Typ.
Max.(2)
LSEDRV[1:0]=00
lower-driving capability
5
-
-
LSEDRV[1:0]=10
medium low-driving
capability
8
-
-
LSEDRV[1:0]=01
medium high-driving
capability
15
-
-
LSEDRV[1:0]=11
higher-driving capability
25
-
-
VDD is stabilized
-
2
-
Parameter
Oscillator
transconductance
tSU(LSE)(3) Startup time
Unit
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
Note:
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available at the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
8 MHz
resonator
CL2
REXT (1)
fHSE
RF
Bias
controlled
gain
OSC_OUT
MS19876V1
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8
Internal clock source characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
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High-speed internal (HSI) RC oscillator
Table 40. HSI oscillator characteristics(1)
Symbol
Parameter
fHSI
Conditions
Min.
Typ.
-
-
Frequency
TRIM
HSI user trimming step
DuCy(HSI)
Duty cycle
Accuracy of the HSI
oscillator (factory
calibrated)
ACCHSI
-
-
-
(2)
45
Max.
Unit
8
-
MHz
-
(2)
-
55
(2)
TA = –40 to 105 °C
(3)
–2.8
-
3.8
TA = –10 to 85 °C
–1.9(3)
-
2.3(3)
TA = 0 to 85 °C
-1.9(3)
-
2(3)
TA = 0 to 70 °C
-1.3(3)
-
2(3)
TA = 0 to 55 °C
–1(3)
-
2(3)
–1
-
1
TA = 25 °C(4)
%
1
%
(3)
%
tsu(HSI)
HSI oscillator startup
time
-
1(2)
-
2(2)
µs
IDDA(HSI)
HSI oscillator power
consumption
-
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered
Figure 19. HSI oscillator accuracy characterization results for soldered parts
4%
MAX
MIN
3%
2%
1%
0%
-40
-20
0
20
40
60
80
100
T [ºC]
120 A
-1%
-2%
-3%
-4%
MS30985V4
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Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Low-speed internal (LSI) RC oscillator
Table 41. LSI oscillator characteristics(1)
Symbol
fLSI
Parameter
Min.
Typ.
Max.
Unit
30
40
50
kHz
Frequency
tsu(LSI)(2)
LSI oscillator startup time
-
-
85
µs
IDD(LSI)(2)
LSI oscillator power consumption
-
0.75
1.2
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
Table 42. PLL characteristics
Value
Symbol
fPLL_IN
fPLL_OUT
Parameter
Unit
Min.
Typ.
Max.
1(2)
-
24(2)
MHz
PLL input clock duty cycle
(2)
40
-
60(2)
%
PLL multiplier output clock
16(2)
-
72
MHz
PLL input clock(1)
tLOCK
PLL lock time
-
-
200(2)
µs
Jitter
Cycle-to-cycle jitter
-
-
300(2)
ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
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6.3.10
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 43. Flash memory characteristics
Min.
Typ.
Max.(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
53.5
60
µs
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 44. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
(2)
1 kcycle
10
at TA = 105 °C
kcycles(2)
at TA = 55 °C
Unit
Min.(1)
10
kcycles
Years
20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
The device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in “EMC design guide for ST microcontrollers” application note (AN1709).
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STM32F334x4 STM32F334x6 STM32F334x8
Table 45. EMS characteristics
Symbol
Parameter
Level/
Class
Conditions
VFESD
VDD = 3.3 V, LQFP64, TA = +25°C,
Voltage limits to be applied on any I/O pin to
fHCLK = 72 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It must be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see the “Software techniques for improving
microcontrollers EMC performance” application note (AN1015)).
Electromagnetic interference (EMI)
The electromagnetic field emitted by the device are monitored, while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard that specifies the test board and the pin loading.
Table 46. EMI characteristics
Symbol Parameter
SEMI
74/125
Monitored
frequency band
Conditions
VDD = 3.6 V, TA =25 °C,
LQFP64 package
Peak level
compliant with IEC
61967-2
Max vs. [fHSE/fHCLK]
0.1 to 30 MHz
5
30 to 130 MHz
9
130 MHz to 1GHz
31
SAE EMI Level
4
DS9994 Rev 9
Unit
8/72 MHz
dBµV
-
STM32F334x4 STM32F334x6 STM32F334x8
6.3.12
Electrical characteristics
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Class
Maximum
value(1)
TA = +25 °C,
Electrostatic discharge
conforming to JESD22voltage (human body model)
A114
2
2000
TA = +25 °C,
conforming to JESD22C101
II
Symbol
VESD
(HBM)
VESD
(CDM)
Ratings
Conditions
Electrostatic discharge
voltage (charge device
model)
Unit
V
250
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
LU
6.3.13
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) must be avoided during normal product
operation. However, to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation). The test results are given in the table below.
Table 49. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0
–0
NA (Injection is not
possible)
Injected current on PC0, PC1, PC2, PC3 (TTa pins) and PF1
pin (FT pin)
-0
+5
mA
Injected current on PA0, PA1, PA2, PA3, PA4, PA5, PA6,
PA7, PC4, PC5, PB0, PB1, PB2, PB12, PB13, PB14, PB15
with induced leakage current on other pins from this group
less than -100 µA or more than +900 µA
-5
+5
Injected current on PB11, other TT, FT, and FTf pins
–5
Injection is not
possible
Injected current on all other TC, TTa and RESET pins
–5
+5
Note:
It is recommended to add a Schottky diode (pin to ground) to the analog pins that may
potentially inject negative currents.
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 19. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics
Symbol
VIL
VIH
Parameter
Low-level input
voltage
High-level input
voltage
Conditions
Min.
Max.
Unit
(1)
TT, TC and TTa I/O
-
-
0.3 VDD+0.07
FT and FTf I/O
-
-
0.475 VDD-0.2 (1)
BOOT0
-
-
0.3 VDD–0.3 (1)
All I/Os except BOOT0
-
-
0.3 VDD (2)
TTa and TT I/O
0.445 VDD+0.398 (1)
-
-
FT and FTf I/O
0.5 VDD+0.2 (1)
-
-
-
-
-
-
0.2 VDD+0.95
BOOT0
All I/Os except BOOT0
76/125
Typ.
DS9994 Rev 9
0.7 VDD (2)
(1)
V
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 50. I/O static characteristics (continued)
Symbol
Vhys
Ilkg
Parameter
Conditions
Min.
TT, TC and TTa I/O
Schmitt trigger
hysteresis
-
FT and FTf I/O
Input leakage
current (3)
Typ.
-
Max.
200
(1)
-
100
(1)
-
(1)
-
BOOT0
-
300
TC, FT, TT, FTf and TTa
I/O in digital mode
VSS ≤VIN ≤VDD
-
-
±0.1
TTa I/O in digital mode
VDD ≤VIN ≤VDDA
-
-
1
TTa I/O in analog mode
VSS ≤VIN ≤VDDA
-
-
±0.2
FT and FTf I/O(4)
VDD ≤VIN ≤5 V
-
-
10
Unit
mV
µA
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
25
40
55
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
25
40
55
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. If negative current is injected on adjacent pins. Refer to Table 49: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 and Figure 21 for standard I/Os.
Figure 20. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
VIHmin 2.0
Tested
S
CMO
uction
nts V
ireme
qu
ard re
stand
in prod
1.3
IHmin
= 0.7V
DD
98
ns
+0.3
5V DD imulatio
0.44
s
=
n
V IHmin on desig
d
Base
ons
7
+0.0 ulati
.3V DDsign sim
0
=
e
V ILmaxed on d
Bas
Area not determined
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
n
ductio
d in pro
Teste
2.0
VDD (V)
2.7
3.0
3.3
3.6
MS30255V2
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 21. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
98
+0.3 lations
5V DD
u
0.44 ign sim
=
V IHmin on des
d
Base
TTL standard requirements V IHmin = 2V
VIHmin 2.0
s
0.07 ulation
V DD+
im
= 0.3 esign s
d
d on
Base
V ILmax
1.3
Area not determined
VILmax 0.8
0.7
TTL standard requirements V ILmax = 0.8V
VDD (V)
2.0
2.7
3.0
3.6
3.3
MS30256V2
Figure 22. 5V- tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
D
.7VD
in = 0
S
CMO
2.0
ard
stand
IHm
nts V
eme
requir
0.2 ulations
V DD+
= 0.5 sign sim
e
on d
ased
V IHmin
B
-0.2
tions
75V DD simula
= 0.4
ign
V ILmax on des
d
Base
Area not determined
1.0
rd
CMOS standa
requirements
3VDD
VILmax = 0.
0.5
VDD (V)
2.0
2.7
3.6
MS30257V3
Figure 23. 5V-tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
TTL standard requirements VIHmin = 2V
2.0
Area not determined
1.0
0.8
ns
0.2
V DD+ simulatio
= 0.5
n
V IHmin n desig
do
Base
-0.2
tions
75V DD imula
= 0.4design s
in
m
V IL d on
Base
TTL standard requirements VILmax = 0.8V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V2
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DS9994 Rev 9
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Electrical characteristics
Output driving current
The GPIOs (general-purpose input/output) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 17).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 17).
Output voltage levels
Unless otherwise specified, the parameters given in Table 47: ESD absolute maximum
ratings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 19. All I/Os (FT, TTa and TC unless otherwise
specified) are CMOS and TTL compliant.
Table 51. Output voltage characteristics
Symbol
Parameter
VOL(1)
Low-level output voltage for an I/O pin
VOH(3)
High- level output voltage for an I/O pin
VOL (1)
Low-level output voltage for an I/O pin
VOH (3)
High-level output voltage for an I/O pin
VOL(1)(4)
Low-level output voltage for an I/O pin
VOH(3)(4)
High-level output voltage for an I/O pin
VOL(1)(4)
Low-level output voltage for an I/O pin
VOH(3)(4)
High-level output voltage for an I/O pin
VOLFM+(1)(4)
Low-level output voltage for an FTf I/O pin
in FM+ mode
Conditions
Min.
Max.
CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD–0.4
-
-
0.4
2.4
-
-
1.3
VDD–1.3
-
-
0.4
VDD–0.4
-
-
0.4
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
Unit
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 17 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 17 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
4. Data based on design simulation.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 66, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 19.
Table 52. I/O AC characteristics(1)
OSPEEDRy
[1:0] value(1)
x0
01
Symbol
Parameter
Conditions
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
fmax(IO)out
Output low to high level
rise time
Maximum frequency(2)
11
tf(IO)out
tr(IO)out
FM+
configuration(4)
-
Output high to low level
fall time
Output low to high level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
CL = 50 pF, VDD = 2 V to 3.6 V
Min.
Max.
Unit
-
2(3)
MH
z
-
125(3)
-
125(3)
-
10(3)
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
ns
CL = 50 pF, VDD = 2 V to 3.6 V
-
25
(3)
25
ns
(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50(3)
MH
z
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30(3)
MH
z
CL = 50 pF, VDD = 2 V to 2.7 V
-
20(3)
MH
z
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
-
2(4)
-
12(4)
-
34(4)
10
-
CL = 50 pF, VDD = 2 V to 3.6 V
2. The maximum frequency is defined in Figure 24.
3. Guaranteed by design, not tested in production.
DS9994 Rev 9
ns
MH
z
ns
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0364 reference manual for a description of
GPIO Port configuration register.
80/125
MH
z
ns
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the RM0364 reference manual for a description of FM+
I/O mode configuration.
Figure 24. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON CL
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.
ai14131d
6.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 50).
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 19.
Table 53. NRST pin characteristics
Symbol
VIL(NRST)(1)
VIH(NRST)
(1)
Vhys(NRST)
RPU
VF(NRST)
Parameter
NRST Input low level voltage
NRST Input high-level voltage
NRST Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
(1)
VNF(NRST)
(1)
NRST Input filtered pulse
NRST Input not filtered pulse
(2)
Conditions
Min.
Typ.
Max.
-
-
-
0.3VDD
+ 0.07(1)
-
0.445VDD +
0.398(1)
-
-
-
-
200
-
mV
VIN = VSS
25
40
55
kΩ
ns
ns
-
-
-
100(1)
-
500(1)
-
-
Unit
V
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 25. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW
9''
538
1567
,QWHUQDOUHVHW
)LOWHU
)
069
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset is not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
4. Place the external capacitor 0.1u F on NRST as close as possible to the chip.
6.3.16
High-resolution timer (HRTIM)
The parameters given in Table 54 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
Table 54. HRTIM1 characteristics
Symbol
TA
fHRTIM
tHRTIM
tRES(HRTIM)
ResHRTIM
tDTG
|tDTR| / |tDTF|
max
fCHPFRQ
t1STPW
Parameter
Timer ambient
temperature range
Conditions
fHRTIM=144MHz
(1)
fHRTIM=128MHz
(2)
Timer resolution
Dead time generator
clock period
Max.
Unit
-40
-
105
°C
-10
-
105
°C
-
144
MHz
6.9
-
7.8
ns
-
217
-
ps
fHRTIM=128MHz (2),TA from -10
to 105°C
-
244
-
ps
-
-
-
16
bit
-
0.125
-
16
tHRTIM
0.868
-
111.10
ns
-
-
511
tDTG
-
-
56.77
µs
fHRTIM=144MHz
40 to 105°C
(1),
TA from -
fHRTIM=144MHz (1)
-
Dead time range
(absolute value)
fHRTIM=144MHz
Chopper stage clock
frequency
fHRTIM=144MHz (1)
Chopper first pulse
length
Typ.
128
HRTIM input clock for
As per TA conditions
DLL calibration
Timer resolution time
Min.
(1)
fHRTIM=144MHz
(1)
1/256
-
1/16
fHRTIM
0.562
-
9
MHz
16
-
256
tHRTIM
0.111
-
1.77
µs
1. Using HSE with 8MHz XTAL as clock source, configuring PLL to get PLLCLK=144MHz, and selecting PLLCLKx2 as
HRTIM clock source. (Refer to Reset and clock control section in RM0364.)
2. Using HSI (internal 8MHz RC oscillator), configuring PLL to get PLLCLK=128MHz, and selecting PLLCLKx2 as HRTIM
clock source. (Refer to Reset and clock control section in RM0364.
82/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 55. HRTIM output response to fault protection(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.(2)
-
12
25
Propagation delay from
HRTIM1_FLTx digital input to
HRTIM_CHxy output pin
tLAT(DF)
Digital fault response
latency
tW(FLT)
Minimum Fault pulse
width
-
12.5
-
-
tLAT(AF)
Analog fault response
latency
Propagation delay from comparator
COMPx_INP input pin to
HRTIM_CHxy output pin
-
25
43
Unit
ns
1. Refer to Fault paragraph in HRTIM section of RM0364.
2. Data based on characterization results, not tested in production.
Table 56. HRTIM output response to external events 1 to 5 (Low-Latency mode(1))
Symbol
tLAT(DEEV)
tW(FLT)
Parameter
Digital external event
response latency
Minimum external event
pulse width
Min.
Typ.
Max.(2)
Unit
-
12
25
ns
-
12.5
-
-
ns
Propagation delay from comparator
COMPx_INP input pin to
HRTIM_CHxy output pin (30pF
load)
-
25
43
ns
Conditions
Propagation delay from
HRTIM1_EEVx digital input to
HRTIM_CHxy output pin (30pF
load)
tLAT(AEEV)
Analog external event
response latency
TJIT(EEV)
Jitter of the delay from
External event response HRTIM1_EEVx digital input or
jitter
COMPx_INP input pin to
HRTIM_CHxy output pin
-
-
0
tHRTIM(3)
TJIT(PW)
Jitter on output pulse
width in response to an
external event
-
-
1
tHRTIM(3)
-
1. EExFAST bit in HRTIM_EECR1 register is set (Low Latency mode). This functionality is available on external events
channels 1 to 5. Refer to Latency to external events paragraph in HRTIM section of RM0364.
2. Data based on characterization results, not tested in production.
3. THRTIM = 1 / fHRTIM with fHRTIM= 144 MHz or fHRTIM = 128 MHZ depending on the clock controller configuration. (Refer to
Reset and clock control section in RM0364.)
Table 57. HRTIM output response to external events 1 to 10 (Synchronous mode (1))
Symbol
TPROP(HRTIM)
tLAT(DEEV)
Parameter
Conditions
External event response
HRTIM internal propagation delay (3)
latency in HRTIM
Digital external event
response latency
Propagation delay from HRTIM1_EEVx
digital input to HRTIM_CHxy output pin
(30pF load) (4)
DS9994 Rev 9
Min. Typ. Max.(2)
Unit
6
-
7
tHRTIM
-
61
72
ns
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 57. HRTIM output response to external events 1 to 10 (Synchronous mode (1)) (continued)
Symbol
tLAT(AEEV)
tW(FLT)
Parameter
Analog external event
response latency
Conditions
Propagation delay from COMPx_INP
input pin to HRTIM_CHxy output pin
(30pF load) (4)
Minimum external event
pulse width
-
Min. Typ. Max.(2)
Unit
-
81
94
ns
12.5
-
-
ns
TJIT(EEV)
Jitter of the delay from HRTIM1_EEVx
External event response
digital input or COMPx_INP to
jitter
HRTIM_CHxy output pin
-
-
1
tHRTIM (5)
TJIT(PW)
Jitter on output pulse
width in response to an
external event
-
-
0
tHRTIM (5)
-
1. EExFAST bit in HRTIM_EECR1 or HRTIM_EECR2 register is cleared (synchronous mode). External event filtering is
disabled, i.e. EExF[3:0]=0000 in HRTIM_EECR2 register. Refer to Latency to external events paragraph in HRTIM section
of RM0364.
2. Data based on characterization results, not tested in production.
3. This parameter does not take into account latency introduced by GPIO or comparator. Refer to DEERL or SACRL
parameter for complete latency.
4. This parameter is given for fHRTIM = 144 MHz.
5. THRTIM = 1 / fHRTIM with fHRTIM= 144 MHz or fHRTIM = 128 MHZ depending on the clock controller configuration. (Refer to
Reset and clock control section in RM0364.)
Table 58. HRTIM synchronization input / output(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
tW(SYNCIN)
Minimum pulse width on
SYNCIN inputs, including
HRTIM1_SCIN
-
2
-
-
tHRTIM
tLAT(DF)
Response time to external
synchronization request
-
-
-
1
tHRTIM
tLAT(AF)
Pulse width on
HRTIM1_SCOUT output
-
-
16
-
tHRTIM
-
111.1
-
ns
fHRTIM=144 MHz
1. Guaranteed by design, not tested in production.
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6.3.17
Electrical characteristics
Timer characteristics
The parameters given in Table 59 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 59. TIMx(1)(2) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
Min.
Max.
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 72 MHz
13.9
-
ns
fTIM1CLK = 144 MHz
6.95
-
ns
0
fTIMxCLK/2
MHz
0
36
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
-
1
65536
tTIMxCLK
fTIMxCLK = 72 MHz
0.0139
910
µs
fTIM1CLK = 144 MHz
0.0069
455
µs
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 72 MHz
-
59.65
s
fTIM1CLK = 144 MHz
-
29.825
s
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
Timer resolution
16-bit counter clock
period
Maximum possible count
tMAX_COUNT
with 32-bit counter
bit
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design, not tested in production.
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 60. IWDG min./max. timeout period at 40 kHz (LSI) (1)
Prescaler divider
PR[2:0] bits
Min. timeout (ms)
RL[11:0] = 0x000
Max. timeout (ms)
RL[11:0] = 0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
7
6.4
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 61. WWDG min./max. timeout value at 72 MHz (PCLK)(1)
Prescaler
WDGTB
Min. timeout value
Max. timeout value
1
0
0.05687
3.6409
2
1
0.1137
7.2817
4
2
0.2275
14.564
8
3
0.4551
29.127
1. Guaranteed by design, not tested in production.
6.3.18
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 Kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 Kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Only FTf I/O pins
support Fm+ low-level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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Electrical characteristics
Table 62. I2C analog filter characteristics(1)
Symbol
tAF
Parameter
Maximum pulse width of spikes that are
suppressed by the analog filter.
Min.
Max.
Unit
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with width below tAF(min.) are filtered.
3. Spikes with width above tAF(max.) are not filtered.
SPI characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 19: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 63. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
24
18
Slave mode 2 < VDD < 3.6 V
NSS setup time
th(NSS)
tsu(SI)
th(MI)
th(SI)
-
-
Slave mode transmitter/full
duplex
2 < VDD < 3.6 V
tsu(NSS)
tsu(MI)
Max.
Master mode 2.7 < VDD < 3.6 V
Slave mode
tw(SCKH)
tw(SCKL)
Typ.
Master mode 2 < VDD < 3.6 V
Duty cycle of SPI clock
frequency
DuCy(SCK)
Min.
24
50
70
Slave mode, SPI presc = 2
4*Tpclk
-
-
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
0
-
-
Slave mode
3
-
-
Master mode
5
-
-
Slave mode
1
-
-
Data input hold time
ta(SO)
Data output access time
Slave mode
10
-
40
tdis(SO)
Data output disable time
Slave mode
10
-
17
Slave mode 2.7 < VDD < 3.6 V
-
12
20
Slave mode 2 < VDD < 3.6 V
-
12
27.5
tv(SO)
Data output valid time
tv(MO)
Master mode
-
1.5
5
th(SO)
Slave mode
7.5
-
-
Master mode
0
-
-
th(MO)
Data output hold time
MHz
18(2)
30
Data input setup time
Unit
%
ns
1. Data based on characterization results, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 26. SPI timing diagram - slave mode and CPHA = 0
Figure 27. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
th(SO)
tv(SO)
ta(SO)
MISO
OUTPUT
MSB OUT
BIT6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
tsu(SI)
MOSI
INPUT
th(NSS)
tc(SCK)
MSB IN
BIT 1 IN
LSB IN
ai14135b
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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DS9994 Rev 9
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Electrical characteristics
Figure 28. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
SCK Output
tc(SCK)
CPHA= 0
CPOL=0
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
BIT6 IN
MSB IN
LSB IN
th(MI)
MOSI
OUTPUT
B I T1 OUT
MSB OUT
tv(MO)
LSB OUT
th(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.19
ADC characteristics
Unless otherwise specified, the parameters showed from Table 64 to Table 67 are
guaranteed by design, with the conditions summarized in Table 19.
Table 64. ADC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDDA
Analog supply voltage for
ADC
-
2
-
3.6
V
Single ended mode,
5 MSPS
-
1011.3
1172.0
Single ended mode,
1 MSPS
-
214.7
322.3
ADC current consumption Single ended mode,
200 KSPS
(Figure 29)
-
54.7
81.1
Differential mode, 5 MSPS
-
1061.5
1243.6
Differential mode, 1 MSPS
-
246.6
337.6
Differential mode,
200 KSPS
-
56.4
83.0
-
0
-
IDDA
VREF-
Negative reference
voltage
-
DS9994 Rev 9
µA
V
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 64. ADC characteristics (continued)
Symbol
fADC
fS(1)
Parameter
ADC clock frequency
Sampling rate
fTRIG(1) External trigger frequency
Conditions
Min.
Typ.
Max.
Unit
-
0.14
-
72
MHz
Resolution = 12 bits,
Fast Channel
0.01
-
5.14
Resolution = 10 bits,
Fast Channel
0.012
-
6
Resolution = 8 bits,
Fast Channel
0.014
-
7.2
Resolution = 6 bits,
Fast Channel
0.0175
-
9
fADC = 72 MHz
Resolution = 12 bits
-
-
5.14
MHz
Resolution = 12 bits
-
-
14
1/fADC
Msps
VAIN
Conversion voltage range
-
0
-
VDDA
V
RAIN(1)
External input impedance
-
-
-
100
κΩ
CADC(1)
Internal sample and hold
capacitor
-
-
5
-
pF
tCAL(1)
Calibration time
tlatr(1)
Trigger conversion latency
Regular and injected
channels without
conversion abort
tADCVRE
(
G_STUP
1)
tSTAB
90/125
1.56
µs
-
112
1/fADC
CKMODE = 00
1.5
2
2.5
1/fADC
CKMODE = 01
-
-
2
1/fADC
CKMODE = 10
-
-
2.25
1/fADC
CKMODE = 11
-
-
2.125
1/fADC
CKMODE = 00
2.5
3
3.5
1/fADC
CKMODE = 01
-
-
3
1/fADC
CKMODE = 10
-
-
3.25
1/fADC
CKMODE = 11
-
-
3.125
1/fADC
fADC = 72 MHz
0.021
-
8.35
µs
-
1.5
-
601.5
1/fADC
ADC Voltage Regulator
Start-up time
-
-
-
10
µs
Power-up time
-
Trigger conversion latency
tlatrinj(1) Injected channels aborting
a regular conversion
tS(1)
fADC = 72 MHz
Sampling time
DS9994 Rev 9
1
conver
sion
cycle
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 64. ADC characteristics (continued)
Symbol
tCONV(1)
CMIR
Parameter
Total conversion time
(including sampling time)
Common Mode Input
signal
Conditions
Min.
Typ.
Max.
Unit
fADC = 72 MHz
Resolution = 12 bits
0.19
-
8.52
µs
14 to 614 (tS for sampling + 12.5 for
successive approximation)
Resolution = 12 bits
(VSSA+VREF+)/ (VSSA +
2-0.18
VREF+)/2
ADC differential mode
1/fADC
(VSSA +
VREF+)/2
+ 0.18
V
1. Data guaranteed by design, not tested in production.
ADC current consumption (μA)
Figure 29. ADC typical current consumption in single-ended and differential modes
Clock frequency (MSPS)
MS34994V1
Table 65. Maximum ADC RAIN(1)
Resolution
12 bits
RAIN max. (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Fast channels(2)
Slow channels
Other
channels(3)
1.5
20.83
0.018
NA
NA
2.5
34.72
0.150
NA
0.022
4.5
62.50
0.470
0.220
0.180
7.5
104.17
0.820
0.560
0.470
19.5
270.83
2.70
1.80
1.50
61.5
854.17
8.20
6.80
4.70
181.5
2520.83
22.0
18.0
15.0
601.5
8354.17
82.0
68.0
47.0
DS9994 Rev 9
91/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 65. Maximum ADC RAIN(1) (continued)
Resolution
10 bits
8 bits
6 bits
RAIN max. (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Fast channels(2)
Slow channels
Other
channels(3)
1.5
20.83
0.082
NA
NA
2.5
34.72
0.270
0.082
0.100
4.5
62.50
0.560
0.390
0.330
7.5
104.17
1.20
0.82
0.68
19.5
270.83
3.30
2.70
2.20
61.5
854.17
10.0
8.2
6.8
181.5
2520.83
33.0
27.0
22.0
601.5
8354.17
100.0
82.0
68.0
1.5
20.83
0.150
NA
0.039
2.5
34.72
0.390
0.180
0.180
4.5
62.50
0.820
0.560
0.470
7.5
104.17
1.50
1.20
1.00
19.5
270.83
3.90
3.30
2.70
61.5
854.17
12.00
12.00
8.20
181.5
2520.83
39.00
33.00
27.00
601.5
8354.17
100.00
100.00
82.00
1.5
20.83
0.270
0.100
0.150
2.5
34.72
0.560
0.390
0.330
4.5
62.50
1.200
0.820
0.820
7.5
104.17
2.20
1.80
1.50
19.5
270.83
5.60
4.7
3.90
61.5
854.17
18.0
15.0
12.0
181.5
2520.83
56.0
47.0
39.0
601.5
8354.17
100.00
100.0
100.0
1. Data based on characterization results, not tested in production.
2. All fast channels, expect channel on PA6.
3. Channels available on PA6.
92/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 66. ADC accuracy - limited test conditions(1)(2)
Symbol Parameter
ET
EO
Total
unadjusted
error
Offset
error
±4
±4.5
Slow channel 4.8 Ms
-
±5.5
±6
Fast channel 5.1 Ms
-
±3.5
±4
Slow channel 4.8 Ms
-
±3.5
±4
Fast channel 5.1 Ms
-
±2
±2
Slow channel 4.8 Ms
-
±1.5
±2
Fast channel 5.1 Ms
-
±1.5
±2
Slow channel 4.8 Ms
-
±1.5
±2
Fast channel 5.1 Ms
-
±3
±4
Slow channel 4.8 Ms
-
±5
±5.5
Fast channel 5.1 Ms
-
±3
±3
Slow channel 4.8 Ms
-
±3
±3.5
Fast channel 5.1 Ms
Single
ADC clock freq. ≤ 72 MHz
ended
Slow channel 4.8 Ms
Sampling freq. ≤ 5 Msps
VDDA = 3.3 V
Fast channel 5.1 Ms
Differential
25°C
Slow channel 4.8 Ms
-
±1
±1
-
±1
±1
-
±1
±1
-
±1
±1
Fast channel 5.1 Ms
-
±1.5
±2
Slow channel 4.8 Ms
-
±2
±3
Fast channel 5.1 Ms
-
±1.5
±1.5
Slow channel 4.8 Ms
-
±1.5
±2
Fast channel 5.1 Ms
10.8
10.8
-
Slow channel 4.8 Ms
10.8
10.8
-
Fast channel 5.1 Ms
11.2
11.3
-
Slow channel 4.8 Ms
11.2
11.3
-
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
Differential
Single
ended
Gain error
Differential
ED
EL
Integral
linearity
error
Effective
ENOB(4) number of
bits
SINAD
(4)
Signal-tonoise and
distortion
ratio
Typ. Max.(3) Unit
-
Single
ended
Differential
linearity
error
(3)
Fast channel 5.1 Ms
Single
ended
Differential
EG
Min.
Conditions
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
DS9994 Rev 9
LSB
bit
dB
93/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 66. ADC accuracy - limited test conditions(1)(2) (continued)
Symbol Parameter
SNR(4)
THD(4)
Signal-tonoise ratio
Total
harmonic
distortion
Min.
Conditions
Typ. Max.(3) Unit
(3)
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
ADC clock freq. ≤ 72 MHz Differential
Slow channel 4.8 Ms
Sampling freq. ≤ 5 Msps
VDDA = 3.3 V
Fast channel 5.1 Ms
Single
25°C
ended
Slow channel 4.8 Ms
69
70
-
69
70
-
-
-80
-80
-
-78
-77
Fast channel 5.1 Ms
-
-83
-82
Slow channel 4.8 Ms
-
-81
-80
Single
ended
Differential
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
Table 67. ADC accuracy (1)(2)(3)
Symbol Parameter
ET
EO
Single
ended
Total
unadjusted
error
Differential
Single
ended
Offset error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA ≤ 3.6 V
EG
Differential
Single
ended
Gain error
Differential
ED
94/125
Differential
linearity
error
Min.(4)
Max.(4)
Fast channel 5.1 Ms
-
±6.5
Slow channel 4.8 Ms
-
±6.5
Fast channel 5.1 Ms
-
±4
Slow channel 4.8 Ms
-
±4.5
Conditions
Single
ended
Differential
DS9994 Rev 9
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±2.5
Slow channel 4.8 Ms
-
±2.5
Fast channel 5.1 Ms
-
±6
Slow channel 4.8 Ms
-
±6
Fast channel 5.1 Ms
-
±3.5
Slow channel 4.8 Ms
-
±4
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Unit
LSB
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 67. ADC accuracy (1)(2)(3) (continued)
Symbol Parameter
EL
ENOB
(5)
SINAD
(5)
SNR(5)
THD(5)
Single
ended
Integral
linearity
error
Effective
number of
bits
Differential
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2.0 V ≤ VDDA ≤ 3.6 V
Single
ended
Differential
Single
ended
Signal-tonoise and
distortion
ratio
Differential
Single
ended
Signal-tonoise ratio
Total
harmonic
distortion
Min.(4)
Max.(4)
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3.5
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±2.5
Conditions
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
2.0 V ≤ VDDA ≤ 3.6 V
Differential
Single
ended
Differential
Fast channel 5.1 Ms
10.4
-
Slow channel 4.8 Ms
10.4
-
Fast channel 5.1 Ms
10.8
-
Slow channel 4.8 Ms
10.8
-
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
63
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
64
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
-
-75
Slow channel 4.8 Ms
-
-75
Fast channel 5.1 Ms
-
-79
Slow channel 4.8 Ms
-
-78
Unit
LSB
bits
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
DS9994 Rev 9
95/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 68. ADC accuracy(1)(2) at 1MSPS
Symbol
Parameter
Typ.
Max(3)
Fast channel
±2.5
±5
Slow channel
±3.5
±5
Fast channel
±1
±2.5
±1.5
±2.5
±2
±3
Test conditions
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Slow channel
ADC Freq. ≤ 72 MHz
Fast channel
Sampling Freq. ≤ 1MSPS
2.4 V ≤ VDDA = VREF+ ≤ 3.6 V Slow channel
Single-ended mode
Fast channel
±3
±4
±0.7
±2
Slow channel
±0.7
±2
Fast channel
±1
±3
Slow channel
±1.2
±3
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current
within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
Figure 30. ADC accuracy characteristics
1LSBIDEAL =
VDDA
4096
EG
4095
4094
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4093
(2)
ET
(3)
7
(1)
6
5
4
EO
EL
3
ED
2
1 L SBIDEAL
1
0
1
VSSA
96/125
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL =Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
DS9994 Rev 9
MS34980V1
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Figure 31. Typical connection diagram using the ADC
VDD
Sample and hold ADC
converter
VT
0.6 V
RAIN (1)
VAIN
RADC
AINx
VT
0.6 V
Cparasitic
12-bit
converter
IL ± 1 μA
CADC
MS19881V3
1. Refer to Table 64 for the values of RAIN.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC must be reduced.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 12: Power-supply scheme.
The 10 nF capacitor must be ceramic (good quality) and it must be placed as close as
possible to the chip.
6.3.20
DAC electrical specifications
Table 69. DAC characteristics
Symbol
VDDA
RLOAD(1)
RO(1)
CLOAD(1)
Parameter
Analog supply voltage
Resistive load
Conditions
Min.
Typ.
Max.
Unit
-
2.4
-
3.6
V
DAC output buffer ON (to VSSA)
5
DAC output buffer ON (to VDDA)
25
DAC output buffer OFF
-
-
15
kΩ
Capacitive load
DAC output buffer ON
-
-
50
pF
0.2
-
VDDA – 0.2
V
-
0.5
-
mV
-
-
VDDA– 1LSB
V
With no load, middle code (0x800)
on the input
-
-
380
µA
With no load, worst code (0xF1C) on
the input.
-
-
480
µA
Corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
and (0x155) and (0xEAB) at VDDA =
2.4 V
DAC output buffer OFF
IDDA
kΩ
Output impedance
VDAC_OUT( Voltage on DAC_OUT
1)
output
(3)
-
DAC DC current
consumption in quiescent
mode(2)
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 69. DAC characteristics (continued)
Symbol
Min.
Typ.
Max.
Unit
Given for a 10-bit input code
DAC1 channel 1
-
-
±0.5
LSB
Given for a 12-bit input code
DAC1 channel 1
-
-
±2
LSB
Given for a 10-bit input code
DAC1 channel 2 & DAC2 channel 1
-
-
-0.75/+0.25
LSB
Given for a 12-bit input code
DAC1 channel 2 & DAC2 channel 1
-
-
-3/+1
LSB
Integral non linearity
Given for a 10-bit input code
(difference between
measured value at Code i
and the value at Code i on a Given for a 12-bit input code
line drawn between Code 0
and last Code 4095)
-
-
±1
LSB
-
-
±4
LSB
Offset error
(difference between
Given for a 10-bit input code at
measured value at Code
VDDA = 3.6 V
(0x800) and the ideal value
Given for a 12-bit input code
= VDDA/2)
-
-
±10
mV
-
-
±3
LSB
-
-
±12
LSB
Gain error
-
-
±0.5
%
Settling time (full scale: for
a 12-bit input code
tSETTLING(3 transition between the
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
)
lowest and the highest input
codes when DAC_OUT
reaches final value ±1LSB
-
3
4
µs
Max frequency for a correct
DAC_OUT change when
small variation in the input CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
code (from code i to
i+1LSB)
-
-
1
MS/
s
DAC buffer ON
Output level higher than 0.2 V
100
-
-
µA
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
-
6.5
10
µs
-
–67
–40
dB
DNL(3)
INL(3)
Offset(3)
Gain
error(3)
Update
rate(3)
Iskink
Parameter
Differential non linearity
Difference between two
consecutive code-1LSB)
Output sink current
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
DAC Control register)
Conditions
Given for a 12-bit input code
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
No RLOAD, CLOAD = 50 pF
measurement
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
98/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Figure 32. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R L
DAC_OUTx
12-bit
digital to
analog
converter
C L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.21
Comparator characteristics
Table 70. Comparator characteristics(1)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage
-
2
-
3.6
V
VIN
Comparator input voltage
range
-
0
-
VDDA
-
VBG
Scaler input voltage
-
-
VREFINIT
-
-
VSC
Scaler offset voltage
-
-
±5
±10
mV
tS_SC
First VREFINT scaler activation
VREFINT scaler startup time after device power on
from power down
Next activations
-
-
1(2)
s
-
-
0.2
ms
VDDA < 2.7 V
-
-
4
VDDA < 2.7 V
-
-
10
Propagation delay for
200 mV step with 100 mV
overdrive
VDDA ≥ 2.7 V
-
25
28
-
28
30
Propagation delay for full
range step with 100 mV
overdrive
VDDA ≥ 2.7 V
-
32
35
-
35
40
VDDA ≥ 2.7 V
-
±5
±10
VDDA < 2.7 V
-
-
±25
Full temperature range
-
-
3
mV
-
400
600
µA
VDDA
tSTART
Parameter
Comparator startup time
VDDA < 2.7 V
tD
µs
ns
VOFFSET
Comparator offset error
TVOFFSET
Total offset variation
IDD(COMP)
COMP current
consumption
VDDA < 2.7 V
-
mV
1. Guaranteed by design, not tested in production.
2. For more details and conditions see Figure 33: Maximum VREFINT scaler startup time from power-down.
DS9994 Rev 9
99/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 33. Maximum VREFINT scaler startup time from power-down
6.3.22
Operational amplifier characteristics
Table 71. Operational amplifier characteristics(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDDA
Analog supply voltage
-
2.4
-
3.6
V
CMIR
Common mode input range
-
0
-
VDDA
V
-
-
4
-
-
6
25°C, No Load
on output.
-
-
1.6
All
voltage/Temp.
-
-
3
VIOFFSET
Input offset voltage
25°C, No Load
on output.
Maximum
calibration range All
voltage/Temp.
After offset
calibration
ΔVIOFFSET
mV
Input offset voltage drift
-
-
5
-
µV/°C
ILOAD
Drive current
-
-
-
500
µA
IDDOPAMP
Consumption
No load,
quiescent mode
-
690
1450
µA
-
-
90
-
dB
73
117
-
dB
CMRR
Common mode rejection ratio
PSRR
Power supply rejection ratio
GBW
Bandwidth
-
-
8.2
-
MHz
SR
Slew rate
-
-
4.7
-
V/µs
RLOAD
Resistive load
-
4
-
-
kΩ
CLOAD
Capacitive load
-
-
-
50
pF
100/125
DC
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Table 71. Operational amplifier characteristics(1) (continued)
Symbol
VOHSAT
VOLSAT
ϕm
tOFFTRIM
tWAKEUP
Parameter
Condition
High saturation voltage(2)
Low saturation voltage
Min.
Typ.
Rload = min,
Input at VDDA.
VDDA-100
-
Rload = 20K,
Input at VDDA.
VDDA-20
-
Rnetwork
PGA gain
error
Ibias
PGA BW
Unit
mV
Rload = min,
input at 0 V
-
-
100
Rload = 20K,
input at 0 V.
-
-
20
Phase margin
-
-
62
-
°
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
-
-
-
2
ms
-
2.8
5
µs
400
-
-
ns
-
2
-
-
-
4
-
-
-
8
-
-
-
16
-
-
Gain=2
-
5.4/5.4
-
Gain=4
-
16.2/5.4
-
Gain=8
-
37.8/5.4
-
Gain=16
-
40.5/2.7
-
CLOAD ≤50 pf,
RLOAD ≥ 4 kΩ,
Follower
configuration
Wakeup time from OFF state.
tS_OPAM_VOUT ADC sampling time when reading the OPAMP output
PGA gain
Max.
Non inverting gain value
-
R2/R1 internal resistance values in
PGA mode (3)
kΩ
PGA gain error
-
-1%
-
1%
-
OPAMP input bias current
-
-
-
±0.2(4)
µA
PGA Gain = 2,
Cload = 50pF,
Rload = 4 KΩ
-
4
-
PGA Gain = 4,
Cload = 50pF,
Rload = 4 KΩ
-
2
-
PGA Gain = 8,
Cload = 50pF,
Rload = 4 KΩ
-
1
-
PGA Gain = 16,
Cload = 50pF,
Rload = 4 KΩ
-
0.5
-
PGA bandwidth for different non
inverting gain
DS9994 Rev 9
MHz
101/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 71. Operational amplifier characteristics(1) (continued)
Symbol
en
Parameter
Voltage noise density
Condition
Min.
Typ.
Max.
@ 1KHz, Output
loaded with
4 KΩ
-
109
-
@ 10KHz,
Output loaded
with 4 KΩ
-
43
1. Guaranteed by design, not tested in production.
2. The saturation voltage can also be limited by the Iload.
3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
4. Mostly TTa I/O leakage, when used in analog mode.
Figure 34. OPAMP voltage noise versus frequency
102/125
DS9994 Rev 9
-
Unit
nV
----------Hz
STM32F334x4 STM32F334x6 STM32F334x8
6.3.23
Electrical characteristics
Temperature sensor (TS) characteristics
Table 72. Temperature sensor (TS) characteristics
Symbol
Parameter
TL(1)
Min.
Typ.
Max.
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25 °C
1.34
1.43
1.52
V
4
-
10
µs
2.2
-
-
µs
VSENSE linearity with temperature
(1)
Avg_Slope
V25
tSTART(1)
TS_temp(1)(2)
Startup time
ADC sampling time when reading the
temperature
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 73. Temperature sensor (TS) calibration values
Calibration value name
6.3.24
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
VBAT monitoring characteristics
Table 74. VBAT monitoring characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
R
Resistor bridge for VBAT
-
50
-
KΩ
Q
Ratio on VBAT measurement
-
2
-
-
Error on Q
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
2.2
-
-
µs
Er(1)
TS_vbat(1)(2)
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
DS9994 Rev 9
103/125
103
Package information
STM32F334x4 STM32F334x6 STM32F334x8
7
Package information
7.1
Package mechanical data
To meet the environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
104/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7mm low-profile quad flat package.
Figure 35. LQFP32 package outline
c
A1
A
A2
SEATING
PLANE
C
0.25 mm
ccc
GAUGE PLANE
C
K
D
A1
L
D1
L1
D3
24
17
25
16
32
9
PIN 1
IDENTIFICATION
1
E
E1
E3
b
7.2
Package information
8
e
5V_ME_V2
1. Drawing is not to scale.
Table 75. LQFP32 mechanical data
Inches(1)
Millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
DS9994 Rev 9
105/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Table 75. LQFP32 mechanical data (continued)
Inches(1)
Millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. Recommended footprint for the LQFP32 package
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
106/125
DS9994 Rev 9
5V_FP_V2
STM32F334x4 STM32F334x6 STM32F334x8
Package information
Device marking for LQFP32
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 37. LQFP32 marking example (package top view)
(1)
Product Identification
STM32F
334K6T6
Y WW
Revision code
R
Pin 1
indentifier
MSv33098V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS9994 Rev 9
107/125
121
Package information
7.3
STM32F334x4 STM32F334x6 STM32F334x8
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7mm low-profile quad flat package.
Figure 38. LQFP48 package outline
c
A1
A
A2
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc C
K
A1
D
L
D1
L1
D3
36
25
37
24
48
E
E1
E3
b
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
Table 76. LQFP48 package mechanical data
inches(1)
millimeters
Symbol
108/125
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Package information
Table 76. LQFP48 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. Recommended footprint for the LQFP48 package
0.50
1.20
9.70
0.30
25
36
37
24
0.20
7.30
5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DS9994 Rev 9
109/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 40. LQFP48 marking example (package top view)
(1)
Product Identification
STM32F
334C6T6
Y WW
Revision code
R
Pin 1
indentifier
MSv33099V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
110/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 41. LQFP64 package outline
0.25 mm
GAUGE PLANE
c
A1
A
SEATING PLANE
C
A2
A1
ccc C
D
D1
D3
K
L
L1
33
48
32
49
64
E
E1
b
E3
7.4
Package information
17
PIN 1
IDENTIFICATION
16
1
e
5W_ME_V3
1. Drawing is not to scale.
Table 77. LQFP64 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
11.800
12.000
-
-
0.4724
-
D1
9.800
10.000
-
-
0.3937
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
e
-
0.500
-
-
0.0197
-
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Package information
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Table 77. LQFP64 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. Recommended footprint for the LQFP64 package
48
33
0.3
0.5
49
32
12.7
10.3
10.3
17
64
1.2
16
1
7.8
12.7
ai14909c
1. Drawing is not to scale.
2. Dimensions are in millimeters.
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Package information
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 43. LQFP64 marking example (package top view)
Revision code
R
(1)
Engineering Sample marking
STM32F334
R6T6
Pin 1
indentifier
Y WW
MSv33100V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
7.5
STM32F334x4 STM32F334x6 STM32F334x8
WLCSP49 package information
Figure 44. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
package outline
bbb Z
A1 BALL LOCATION
e1
F
G
7
A1
1
A
DETAIL A
E
e2 E
e
G
aaa
e
A
TOP VIEW
BOTTOM VIEW
A3
A2
D
D
SIDE VIEW
A2
BUMP
FRONT VIEW
A2
SEATING PLANE
DETAIL A
ROTATED 90
B01F_WLCSP49_ME_V1
1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.
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Table 78. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
0.62
-
-
0.0244
A1
-
0.23
-
-
0.009
-
A2
-
0.36
-
-
0.014
-
-
-
0.001
-
0.025
(2)
A3
-
b
0.30
0.33
0.36
0.012
0.013
0.014
D
3.87
3.89
3.91
0.152
0.153
0.154
E
3.72
3.74
3.76
0.146
0.147
0.148
e
-
0.50
-
-
0.020
-
e1
-
3.00
-
-
0.118
-
e2
-
3.00
-
-
0.118
-
F
-
0.445(3)
-
-
0.017
-
G
-
0.370(4)
-
-
0.015
-
aaa
-
-
0.10
-
-
0.004
bbb
-
-
0.10
-
-
0.004
ccc
-
-
0.10
-
-
0.004
ddd
-
-
0.05
-
-
0.002
eee
-
-
0.05
-
-
0.002
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. A3 value is guaranteed by technology design value.
3. This value is calculated from over value D and e1.
4. This value is calculated from over value E and e2.
Figure 45. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended footprint
Dpad
Dsm
B01F_WLCSP49_FP_V1
1. Dimensions are expressed in millimeters.
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Table 79. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended PCB design rules
Dimension
Recommended values
Pitch
0.5 mm
Dpad
0.290 mm
Dsm
0.350 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.310 mm
Stencil thickness
0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 46. WLCSP49 marking example (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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7.6
Package information
UFQFPN32 package information
Figure 47. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
package outline
D1
E1
e
Pin 1 identifier
e
L
b
BOTTOM VIEW
A1
A3
FRONT VIEW
DETAIL A
Pin 1 identifier
LASER MARKING AREA
A3
E
e
b
A1
A
SEATING
PLANE
DETAIL A
D
TOP VIEW
A09E_ME_V1
1. Drawing is not in scale.
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Table 80. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A(2)
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0
0.020
0.050
0
0.0008
0.0020
A3
-
0.152
-
-
0.0060
-
b
0.180
0.250
0.280
0.0071
0.0098
0.0110
(3)
D
4.900
5.000
5.100
0.1929
0.1969
0.2008
D1
3.400
3.500
3.600
0.1339
0.1378
0.1417
E(3)
4.900
5.000
5.100
0.1929
0.1969
0.2008
E1
3.400
3.500
3.600
0.1339
0.1378
0.1417
e
-
0.500
-
-
0.0197
-
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. UFQFPN stands for Thermally Enhanced Ultrathin Fine pitch Quad Flat Package No lead.
3. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
Figure 48. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint
5.30
3.80
0.60
3.80
5.30
0.50
0.30
0.75
3.80
A09E_FP_V1
1. Dimensions are expressed in millimeters.
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Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 49. UFQFPN32 marking example (package top view)
Product identification (1)
E334K6U
Y WW
R
Revision code
Pin 1 identifier
MSv44309V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
7.7
STM32F334x4 STM32F334x6 STM32F334x8
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 81. Package thermal characteristics
Symbol
ΘJA
Parameter
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm / 0.8 mm pitch
60
Thermal resistance junction-ambient
UFQFN32 - 5 x 5 mm
37
Thermal resistance junction-ambient
WLCSP49 - 3.89 x 3.74 mm / 0.5 mm pitch
7.7.1
Value
Unit
°C/W
48.3
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available at the www.jedec.org website.
7.7.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 82: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use the STM32F334x4/6/8 microcontroller at maximum
dissipation, it is useful to calculate the exact power consumption and junction temperature
to determine which temperature range is best suited to the application.
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Package information
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 81: Package thermal characteristics, TJmax is calculated
as follows:
–
For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 82: Ordering information scheme).
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Ordering information
8
STM32F334x4 STM32F334x6 STM32F334x8
Ordering information
Table 82. Ordering information scheme
Example:
STM32
Device family
STM32 = Arm®-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
334 = STM32F334xx, 2.0 to 3.6 V operating voltage
Pin count
K = 32 pins
C = 48 or 49 pins
R = 64 pins
Flash memory size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
Package
T = LQFP
Y = WLCSP
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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9
Revision history
Revision history
Table 83. Document revision history
Date
Revision
19-Jun-2014
1
Initial release.
2
Updated:
– Table 54: TIMx characteristics
– Table 14: STM32F334x6/8 pin definitions
– Table 59: ADC characteristics
– Table 34: Peripheral current consumption
– Table 40: HSI oscillator characteristics
– Table 17: HSI oscillator accuracy characterization results
for soldered parts
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
3
Updated:
– Figure 1: STM32F334x4/6/8 block diagram
– Table 38: HSE oscillator characteristics
– Table 43: Flash memory characteristics
Added Figure 15: High-speed external clock source AC timing
diagram
4
Updated:
– Title
– Section 3.14.1: 217 ps high-resolution timer (HRTIM1)
– Section 6.1.6: Power-supply scheme
– Table 19: General operating conditions
5
Updated:
Section Table 69.: DAC characteristics, Section Table 64.:
ADC characteristics,Table 53: NRST pin characteristics,
Figure 2: Clock tree, Table 13: STM32F334x4/6/8 pin
definitions, Table 71: Operational amplifier characteristics,
Figure 22: 5V- tolerant (FT and FTf) I/O input characteristics CMOS port, Table 23: Embedded internal reference voltage,
Table 39: LSE oscillator characteristics (fLSE = 32.768 kHz)
Added Table 35: Wakeup time using USART.
6
Updated:
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
– Table 13: STM32F334x4/6/8 pin definitions
– Table 19: General operating conditions
– Table 81: Package thermal characteristics
– Table 82: Ordering information scheme
Added:
– Figure 7: WLCSP49 ballout
– Section 7.5: WLCSP49 package information
09-Dec-2014
2-Feb-2015
09-Jun-2015
27-Sep-2016
15-May-2017
Changes
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STM32F334x4 STM32F334x6 STM32F334x8
Table 83. Document revision history (continued)
Date
Changes
23-Nov--2017
7
Updated:
– Footnotes of Table 25: Typical and maximum current
consumption from VDD supply at VDD = 3.6V
– Footnotes of Table 26: Typical and maximum current
consumption from the VDDA supply
19-Dec-2017
8
Updated Table 1: Device summary: STM32F334R4 product
not covered by this datasheet
9
Updated:
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
– Table 13: STM32F334x4/6/8 pin definitions
– Table 19: General operating conditions
– Table 81: Package thermal characteristics
– Table 82: Ordering information scheme
Added:
– Figure 8: UFQFPN32 pinout
– Section 7.6: UFQFPN32 package information
16-Jul-2018
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Revision
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