STM32F405RGT6

STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data FBGA • LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) WLCSP90 UFBGA176 (10 × 10 mm) • Features • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM – Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4 June 2013 This is information on a product in full production. • • • • • • • IC/OC/PWM or pulse counter and quadrature (incremental) encoder input Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII 8- to 14-bit parallel camera interface up to 54 Mbytes/s True random number generator CRC calculation unit 96-bit unique ID RTC: subsecond accuracy, hardware calendar Table 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE DocID022152 Rev 4 1/185 www.st.com 1 Contents STM32F405xx, STM32F407xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/185 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID022152 Rev 4 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 80 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102 DocID022152 Rev 4 3/185 Contents 6 7 STM32F405xx, STM32F407xx 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 8 4/185 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 79 VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 80 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 88 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DocID022152 Rev 4 5/185 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. 6/185 STM32F405xx, STM32F407xx I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 115 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 128 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 128 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160 LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164 UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167 DocID022152 Rev 4 STM32F405xx, STM32F407xx Table 96. Table 97. Table 98. List of tables Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 7/185 List of figures STM32F405xx, STM32F407xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. 8/185 Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 15 Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F40x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F40x WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 85 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 85 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 86 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 86 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DocID022152 Rev 4 STM32F405xx, STM32F407xx Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. List of figures SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 124 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 133 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 133 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159 LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164 LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167 LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 171 DocID022152 Rev 4 9/185 List of figures Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. 10/185 STM32F405xx, STM32F407xx USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DocID022152 Rev 4 STM32F405xx, STM32F407xx 1 Introduction Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com. DocID022152 Rev 4 11/185 Description 2 STM32F405xx, STM32F407xx Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: 12/185 • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances DocID022152 Rev 4 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes SRAM in Kbytes 512 System 192(112+16+64) Backup 4 FSMC memory controller Ethernet DocID022152 Rev 4 Timers 1024 1024 512 Yes(1) No No 1024 512 1024 Yes Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator 512 STM32F405xx, STM32F407xx Figure 5 shows the general block diagram of the device family. Yes Description 13/185 Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix 3/2 (full duplex)(2) SPI / I2S I2C 3 USART/ UART 4/2 Communi USB cation OTG FS interfaces USB OTG HS Yes Yes CAN 2 SDIO Yes DocID022152 Rev 4 Camera interface GPIOs 12-bit ADC Number of channels No 51 72 Yes 82 114 72 82 114 140 13 16 24 24 LQFP144 UFBGA176 LQFP176 3 16 13 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz 1.8 to 3.6 V(3) Operating voltage Junction temperature: –40 to + 125 °C LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). STM32F405xx, STM32F407xx Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package Description 14/185 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts STM32F405xx, STM32F407xx 2.1 Description Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 VSS VSS 48 33 32 47 49 31 VSS VSS 17 64 1 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 16 ai18489 DocID022152 Rev 4 15/185 Description STM32F405xx, STM32F407xx Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package 76 75 73 VSS 51 50 49 VSS VSS 100 99 (VSS) 19 26 20 1 0Ω Ω resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration 25 VSS VDD V SS VSS for STM32F10xx VDD for STM32F4xx Two 0 Ω resistors connected to: VDD VSS - VSS for the STM32F10xx - VSS for the STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18488c Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package VSS 108 109 73 72 106 71 VSS VSS Signal from external power supply supervisor 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 143 (PDR_ON) 30 144 31 1 37 36 VSS VDD VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx VDD VSS VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx 16/185 DocID022152 Rev 4 ai18487d STM32F405xx, STM32F407xx Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages 132 89 88 133 Signal from external power supply supervisor 171 (PDR_ON) 176 45 1 44 VDD VSS Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx MS19919V3 DocID022152 Rev 4 17/185 Description 2.2 STM32F405xx, STM32F407xx Device overview Figure 5. STM32F40x block diagram CCM data RAM 64 KB NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO JTAG & SW ETM AHB3 MPU NVIC External memory controller (FSMC) SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash CLK, NE [3:0], A[23:0], D[31:0], OEN, WEN, NBL[3:0], NL, NREG, NWAIT/IORDY, CD NIORD, IOWR, INT[2:3] TRACECLK INTN, NIIS16 as AF D-BUS ARM Cortex-M4 168 MHz FPU I-BUS ART ACCEL/ CACHE FIFO DMA/ FIFO ID, VBUS, SOF DMA2 8 Streams FIFO DMA1 8 Streams FIFO RNG 1 MB SRAM 112 KB HSYNC, VSYNC Camera interface PUIXCLK, D[13:0] SRAM 16 KB AHB2 168 MHz AHB1 168 MHz VDD PHY DP, DM ULPI:CK, D[7:0], DIR, STP, NXT DMA/ USB OTG HS PHY MDIO as AF Flash up to FIFO Ethernet MAC 10/100 MII or RMII as AF AHB bus-matrix 8S7M S-BUS FIFO TRACED[3:0] USB OTG FS DP DM ID, VBUS, SOF Power managmt Voltage regulator 3.3 to 1.2 V VDD = 1.8 to 3.6 V VSS VCAP1, VCPA2 @VDD @VDDA PA[15:0] RC HS GPIO PORT A RC L S PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E POR reset Int Supply supervision POR/PDR BOR P L L1&2 NRST @VDD @VDDA XTAL OSC 4- 16MHz GPIO PORT F FCLK PCLKx PWR interface 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF TIM1 / PWM TIM8 / PWM 2 channels as AF 1 channel as AF TIM10 16b 1 channel as AF TIM11 16b USART1 RX, TX, CK, CTS, RTS as AF smcard irDA USART6 MOSI, MISO, SCK, NSS as AF AHB/APB1 16b 16b smcard irDA AHB/APB2 16b TIM9 RX, TX, CK, CTS, RTS as AF DMA1 DMA2 WWDG SPI1 @VDDA VDDREF_ADC Temperature sensor 8 analog inputs common to the 3 ADCs ADC1 8 analog inputs common to the ADC1 & 2 ADC2 8 analog inputs for ADC3 TIM6 16b TIM7 16b @VDDA DAC1 ITF DAC2 IF A P B(max) 1 3 0 M Hz APB142 MHz 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF EXT IT. WKUP SDIO / MMC OSC32_OUT 4 KB BKPSRAM TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels TIM12 16b 2 channels as AF TIM13 16b 1 channel as AF TIM14 16b 1 channel as AF USART2 smcard irDA RX, TX as AF CTS, RTS as AF USART3 smcard irDA RX, TX as AF CTS, RTS as AF UART4 RX, TX as AF UART5 RX, TX as AF as AF MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF SP3/I2S3 I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF bxCAN2 DAC1_OUT MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF SP2/I2S2 bxCAN1 ADC3 RTC_AF1 RTC_AF1 AWU Backup register FIFO LS GPIO PORT I APB2 84 MHz D[7:0] CMD, CK as AF OSC32_IN XTAL 32 kHz RTC FIFO 140 AF VBAT = 1.65 to 3.6 V @VBAT LS GPIO PORT H PI[11:0] OSC_OUT IWDG clockA G T M AN control GPIO PORT G PH[15:0] OSC_IN Reset & HCLKx PF[15:0] PG[15:0] VDDA, VSSA PVD TX, RX TX, RX DAC2_OUT as AF MS19920V3 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The camera interface and ethernet are available only on STM32F407xx devices. 18/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx 2.2.1 Description ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. DocID022152 Rev 4 19/185 Description 2.2.5 STM32F405xx, STM32F407xx CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 20/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix S1 S2 S4 S5 USB_HS_M MAC USB OTG Ethernet HS ETHERNET_M DMA_P2 DMA_MEM2 DMA_PI DMA_MEM1 S3 GP DMA2 S6 S7 M0 ICODE M1 DCODE ACCEL S0 GP DMA1 S-bus I-bus D-bus ARM Cortex-M4 64-Kbyte CCM data RAM Flash memory M2 SRAM1 112 Kbyte M3 SRAM2 16 Kbyte AHB1 peripherals AHB2 peripherals M4 M5 M6 APB1 APB2 FSMC Static MemCtl Bus matrix-S ai18490c 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. DocID022152 Rev 4 21/185 Description 2.2.9 STM32F405xx, STM32F407xx Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL 22/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. DocID022152 Rev 4 23/185 Description STM32F405xx, STM32F407xx The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V or 1.8 V (1) PDR_ON NRST Application reset signal (optional) VDD MS31383V3 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. 24/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF V DD PDR = 1.7 V or 1.8 V (1) time Reset by other source than power supply supervisor NRST PDR_ON PDR_ON time MS19009V6 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) DocID022152 Rev 4 25/185 Description STM32F405xx, STM32F407xx Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. Figure 9. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor signal (optional) Ext. reset controller active when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V4 26/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 14: General operating conditions). Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V (2) V12 Min V12 VCAP_1/VCAP_2 time NRST time ai18491e 1. This figure is valid both whatever the internal reset mode (onON or OFFoff). 2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges. DocID022152 Rev 4 27/185 Description STM32F405xx, STM32F407xx Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492d 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON LQFP64 LQFP100 Yes LQFP144 LQFP176 WLCSP90 UFBGA176 2.2.18 Regulator OFF Internal reset ON Internal reset OFF Yes No Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor No Yes Yes BYPASS_REG set BYPASS_REG set to VDD to VSS Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC 28/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.19 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V12 domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering DocID022152 Rev 4 29/185 Description STM32F405xx, STM32F407xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.20 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.2.21 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Counter Counter Prescaler Timer resolutio type factor n Advanced TIM1, -control TIM8 30/185 16-bit Up, Any integer Down, between 1 Up/dow and 65536 n DMA Max Max Capture/ request Complementar interface timer compare generatio y output clock clock channels n (MHz) (MHz) Yes DocID022152 Rev 4 4 Yes 84 168 STM32F405xx, STM32F407xx Description Table 4. Timer feature comparison (continued) Timer type Counter Counter Prescaler Timer resolutio type factor n 32-bit Up, Any integer Down, between 1 Up/dow and 65536 n Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Any integer Down, between 1 Up/dow and 65536 n Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10 , TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13 , TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 TIM2, TIM5 General purpose Basic DMA Max Max Capture/ request Complementar interface timer compare generatio y output clock clock channels n (MHz) (MHz) Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. DocID022152 Rev 4 31/185 Description STM32F405xx, STM32F407xx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 32/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.22 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. DocID022152 Rev 4 33/185 Description STM32F405xx, STM32F407xx Table 5. USART feature comparison Max. baud rate Max. baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) USART name Standard features Modem (RTS/ CTS) USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) 2.2.24 SPI LIN master irDA APB mapping Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.25 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.2.26 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. 34/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.27 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. The STM32F407xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time DocID022152 Rev 4 35/185 Description 2.2.29 STM32F405xx, STM32F407xx Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.31 • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 36/185 • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID022152 Rev 4 STM32F405xx, STM32F407xx 2.2.32 Description Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 2.2.33 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.35 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally DocID022152 Rev 4 37/185 Description STM32F405xx, STM32F407xx connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.37 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 38/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 12. STM32F40x LQFP64 pinout VBAT PC13 PC14 PC15 PH0 PH1 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD 3 Pinouts and pin description ai18493b DocID022152 Rev 4 39/185 Pinouts and pin description STM32F405xx, STM32F407xx 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 13. STM32F40x LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 VSS VDD PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 ai18495c 40/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 14. STM32F40x LQFP144 pinout LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 DocID022152 Rev 4 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 ai18496b 41/185 Pinouts and pin description STM32F405xx, STM32F407xx 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 Figure 15. STM32F40x LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 V 102 V 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD PH6 PH7 PH8 PH9 PH10 PH11 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDDA VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 42/185 DocID022152 Rev 4 MS19916V3 STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40x UFBGA176 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 VCAP_1 ai18497b 1. This figure shows the package top view. DocID022152 Rev 4 43/185 Pinouts and pin description STM32F405xx, STM32F407xx Figure 17. STM32F40x WLCSP90 ballout 10 8 7 6 5 4 PC13 PDR_ON BOOT0 PB4 PD7 PD4 PC12 PA14 VDD PC15 VDD PB7 PB3 PD6 PD2 PA15 PI1 VCAP_2 PA0 VSS PB9 PB6 PD5 PD1 PC11 PI0 PA12 PA11 PC2 BYPASS_ REG PB8 PB5 PD0 PC10 PA13 PA10 PA9 PA8 E PC0 PC3 VSS VSS VDD VSS VDD PC9 PC8 PC7 F PH0 PH1 PA1 VDD PE10 PE14 VCAP_1 PC6 PD14 PD15 G NRST VDDA PA5 PB0 PE7 PE13 PE15 PD10 PD12 PD11 H VSSA PA3 PA6 PB1 PE8 PE12 PB10 PD9 PD8 PB15 PA2 PA4 PA7 PB2 PE9 PE11 PB11 PB12 PB14 PB13 A VBAT PC14 B C D J 9 3 2 1 MS30402V1 1. This figure shows the package bump view. Table 6. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 44/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 (function after reset)(1) Pin type I / O structure - - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 A10 6 6 C1 6 VBAT S - - - - D2 7 PI8 I/O FT 2 A9 7 7 D1 8 PC13 I/O FT 3 B10 8 8 E1 9 PC14/OSC32_IN I/O (PC14) FT 4 B9 9 9 F1 10 PC15/ OSC32_OUT (PC15) I/O FT - - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - - F2 14 VSS S - - - - F3 15 VDD S - - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT Pin name Notes LQFP64 Pin number Alternate functions (2)( 3) (2) (3) (2)( 3) (2)( 3) DocID022152 Rev 4 Additional functions EVENTOUT RTC_TAMP1, RTC_TAMP2, RTC_TS EVENTOUT RTC_OUT, RTC_TAMP1, RTC_TS EVENTOUT OSC32_IN(4) EVENTOUT OSC32_OUT(4) 45/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 (function after reset)(1) Pin type I / O structure - - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 FT (4) FSMC_A4/EVENTOUT ADC3_IN14 FT (4) FSMC_A5/EVENTOUT ADC3_IN15 - - - 14 J3 20 Pin name PF4 I/O Notes LQFP64 Pin number Alternate functions Additional functions - - - 15 K3 21 PF5 I/O - C9 10 16 G2 22 VSS S - B8 11 17 G3 23 VDD S - - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG / EVENTOUT ADC3_IN5 - - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 F10 12 23 G1 29 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 H1 30 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 G10 14 25 J1 31 NRST I/O RS T 8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 9 - 16 10 D10 17 46/185 28 M4 34 PC2 I/O DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) 11 E9 18 29 M5 35 PC3 I/O - - 19 30 G3 36 VDD S 12 H10 20 31 M1 37 VSSA S - - - - N1 - VREF– S - - 21 32 P1 38 VREF+ S 13 G9 22 33 R1 39 VDDA S 14 C10 23 34 N3 40 PA0/WKUP (PA0) I/O Notes (function after reset)(1) I / O structure Pin name Pin type LQFP176 UFBGA176 LQFP144 LQFP100 WLCSP90 LQFP64 Pin number Alternate functions Additional functions FT (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 (5) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT ADC123_IN1 ADC123_IN2 FT 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT 16 J10 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT 15 F8 - - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOU T - - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOU T - - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT DocID022152 Rev 4 ADC123_IN0/WKUP(4 ) 47/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) Notes (function after reset)(1) Alternate functions Additional functions (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / ADC12_IN5/DAC_OU TIM2_CH1_ETR/ T2 TIM8_CH1N/ EVENTOUT (4) SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 ADC12_IN7 17 H9 26 37 R2 47 PA3 I/O 18 E5 27 38 - - VSS S L4 48 BYPASS_REG I K4 49 VDD S D9 19 20 21 22 E4 J9 G8 H8 28 29 30 31 39 40 41 42 N4 P4 P3 50 51 52 PA4 PA5 PA6 I / O structure Pin name Pin type LQFP176 UFBGA176 LQFP144 LQFP100 WLCSP90 LQFP64 Pin number I/O FT FT FT 23 J8 32 43 R3 53 PA7 I/O FT (4) SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT 24 - 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 - 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 26 G7 48/185 35 46 R5 56 PB0 I/O FT DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) Notes 57 PB1 I/O FT 28 J7 37 48 M6 58 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 R6 59 PF11 I/O FT DCMI_D12/ EVENTOUT - - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - - 51 M8 61 VSS S - - - 52 N8 62 VDD S - - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - G6 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - H6 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - J6 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT - - - 61 M9 71 VSS S - - - 62 N9 72 VDD S - F6 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - J5 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - H5 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - G5 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT Pin name (function after reset)(1) Pin type R4 LQFP176 47 UFBGA176 36 LQFP144 H7 TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT LQFP100 27 (4) WLCSP90 Alternate functions LQFP64 I / O structure Pin number DocID022152 Rev 4 Additional functions ADC12_IN9 49/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 (function after reset)(1) Pin type I / O structure - F5 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - G4 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 29 H4 47 69 R12 79 Pin name PB10 I/O Notes LQFP64 Pin number Alternate functions 30 J4 48 70 R13 80 PB11 I/O 31 F4 49 71 M10 81 VCAP_1 S 32 - 50 72 N10 82 VDD S - - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT - - - - K12 89 PH12 I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT - - - - H12 90 VSS S - - - - J12 91 VDD S 50/185 DocID022152 Rev 4 Additional functions STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) 33 34 35 J3 J1 J2 51 52 53 73 74 75 P12 P13 R14 92 93 94 PB12 PB13 PB14 I/O I/O I/O Notes (function after reset)(1) I / O structure Pin name Pin type LQFP176 UFBGA176 LQFP144 LQFP100 WLCSP90 LQFP64 Pin number Alternate functions FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT 36 H1 54 76 R15 95 PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT - H2 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - H3 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - G3 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - G1 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CT S/ EVENTOUT FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT - G2 59 81 N13 100 PD12 I/O DocID022152 Rev 4 Additional functions OTG_HS_VBUS RTC_REFIN 51/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) FT FSMC_A18/TIM4_CH2/ EVENTOUT I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - - 94 G12 113 VSS S - - - 95 H13 114 VDD S FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT WLCSP90 LQFP100 LQFP144 - - 60 82 - - - 83 - - - 84 J13 103 VDD S - F2 61 85 M14 104 PD14 - F1 62 86 L14 105 - - - 87 - - - - - - 37 F3 63 96 LQFP176 LQFP64 Pin name (function after reset)(1) PD13 102 VSS S M15 101 - H15 115 PC6 I/O Notes I / O structure I/O UFBGA176 Pin type Pin number Alternate functions 38 E1 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 E2 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT 52/185 DocID022152 Rev 4 Additional functions STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) 40 E3 66 99 F14 118 PC9 I/O Notes (function after reset)(1) I / O structure Pin name Pin type LQFP176 UFBGA176 LQFP144 LQFP100 WLCSP90 LQFP64 Pin number Alternate functions FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 D1 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 D2 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT 43 D3 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 44 C1 70 103 C15 122 PA11 I/O 45 C2 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 D4 72 105 A15 124 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 B1 73 106 F13 125 VCAP_2 S - E7 74 107 F12 126 VSS S 48 E6 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - C3 - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT DocID022152 Rev 4 Additional functions OTG_FS_VBUS 53/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) LQFP144 Pin type I / O structure - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - - D9 135 VSS S - - - - C9 136 VDD S 49 A2 76 109 A14 137 PA14 (JTCK/SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 77 110 A13 138 PA15 (JTDI) FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT 50 51 52 B3 D5 C4 78 111 B14 139 79 112 B13 140 Pin name (function after reset)(1) PC10 PC11 I/O I/O I/O Notes LQFP100 B2 LQFP176 WLCSP90 - UFBGA176 LQFP64 Pin number Alternate functions 53 A3 80 113 A12 141 PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - D6 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - C5 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 B4 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT 54/185 DocID022152 Rev 4 Additional functions STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) I / O structure I/O FT FSMC_CLK/ USART2_CTS/ EVENTOUT - A4 85 118 D10 146 PD4 I/O FT FSMC_NOE/ USART2_RTS/ EVENTOUT - C6 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX / EVENTOUT - - - 120 D8 148 VSS S - - - 121 C8 149 VDD S - B5 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - A5 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT - - - 124 C10 152 PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3 / EVENTOUT - - - 125 B10 153 PG10 I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT Pin name (function after reset)(1) Notes Pin type PD3 LQFP176 84 117 D11 145 UFBGA176 - LQFP144 WLCSP90 - LQFP100 LQFP64 Pin number Alternate functions - - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT - - - - - - 128 129 A8 A7 156 157 PG13 PG14 I/O I/O DocID022152 Rev 4 Additional functions 55/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 7. STM32F40x pin and ball definitions (continued) LQFP100 LQFP144 UFBGA176 LQFP176 - E8 - 130 D7 158 VSS S - F7 - 131 C7 159 VDD S - - - 132 B7 160 PG15 I/O 55 B6 89 133 A10 161 56 A6 90 134 57 58 D7 C7 91 135 92 136 A9 A6 B6 162 163 164 USART6_CTS / DCMI_D13/ EVENTOUT PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT PB5 PB6 I/O I/O B7 93 137 B5 165 PB7 I/O FT 60 A7 94 138 D6 166 BOOT0 I B 62 D8 C8 56/185 95 139 96 140 A5 B4 167 168 Alternate functions FT 59 61 Notes WLCSP90 (function after reset)(1) I / O structure LQFP64 Pin name Pin type Pin number PB8 PB9 I/O I/O Additional functions VPP FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions (continued) LQFP176 Pin type I / O structure - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT 63 - 99 - D5 - VSS S - A8 - 143 C6 171 PDR_ON I 64 A1 10 144 0 C5 172 VDD S - - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT Pin name Notes UFBGA176 - LQFP144 WLCSP90 (function after reset)(1) LQFP100 LQFP64 Pin number Alternate functions Additional functions FT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 8. FSMC pin definition FSMC Pins(1) CF NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM LQFP100(2) PE2 A23 A23 Yes PE3 A19 A19 Yes DocID022152 Rev 4 WLCSP90 (2) 57/185 Pinouts and pin description STM32F405xx, STM32F407xx Table 8. FSMC pin definition (continued) FSMC Pins (1) CF LQFP100(2) PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes WLCSP90 (2) PF0 A0 A0 - - PF1 A1 A1 - - PF2 A2 A2 - - PF3 A3 A3 - - PF4 A4 A4 - - PF5 A5 A5 - - PF6 NIORD - - PF7 NREG - - PF8 NIOWR - - PF9 CD - - PF10 INTR - - PF12 A6 A6 - - PF13 A7 A7 - - PF14 A8 A8 - - PF15 A9 A9 - - PG0 A10 A10 - - A11 - - PG1 PE7 D4 D4 DA4 D4 Yes Yes PE8 D5 D5 DA5 D5 Yes Yes PE9 D6 D6 DA6 D6 Yes Yes PE10 D7 D7 DA7 D7 Yes Yes PE11 D8 D8 DA8 D8 Yes Yes PE12 D9 D9 DA9 D9 Yes Yes PE13 D10 D10 DA10 D10 Yes Yes PE14 D11 D11 DA11 D11 Yes Yes PE15 D12 D12 DA12 D12 Yes Yes PD8 D13 D13 DA13 D13 Yes Yes PD9 D14 D14 DA14 D14 Yes Yes PD10 D15 D15 DA15 D15 Yes Yes A16 A16 CLE Yes Yes PD11 58/185 NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM DocID022152 Rev 4 STM32F405xx, STM32F407xx Pinouts and pin description Table 8. FSMC pin definition (continued) FSMC Pins (1) CF NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM PD12 A17 A17 PD13 A18 A18 ALE LQFP100(2) WLCSP90 Yes Yes (2) Yes PD14 D0 D0 DA0 D0 Yes Yes PD15 D1 D1 DA1 D1 Yes Yes PG2 A12 - - PG3 A13 - - PG4 A14 - - PG5 A15 - - PG6 INT2 - - PG7 INT3 - - PD0 D2 D2 DA2 D2 Yes Yes PD1 D3 D3 DA3 D3 Yes Yes CLK CLK PD3 Yes PD4 NOE NOE NOE NOE Yes Yes PD5 NWE NWE NWE NWE Yes Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes PD7 NE1 NE1 NCE2 Yes Yes PG9 NE2 NE2 NCE3 - - NE3 NE3 - - - - PG10 NCE4_1 PG11 NCE4_2 PG12 NE4 NE4 - - PG13 A24 A24 - - PG14 A25 A25 - - PB7 NADV NADV Yes Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column. 2. Ports F and G are not available in devices delivered in 100-pin packages. DocID022152 Rev 4 59/185 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 ETH_MDIO EVENTOUT ETH _MII_COL EVENTOUT Port PA3 TIM2_CH4 TIM5_CH4 TIM9_CH1 USART2_TX TIM9_CH2 USART2_RX PA4 DocID022152 Rev 4 Port A SPI1_NSS PA5 TIM2_CH1_E TR PA6 TIM1_BKIN PA7 PA8 TIM1_CH1N MCO1 PA9 TIM3_CH1 TIM3_CH2 OTG_HS_ULPI_ D0 TIM8_CH1N SPI1_SCK TIM8_BKIN SPI1_MISO TIM8_CH1N SPI3_NSS I2S3_WS OTG_HS_SO F USART2_CK AF14 DCMI_HSYN C OTG_HS_ULPI_ CK DCMI_PIXCK ETH_MII _RX_DV ETH_RMII _CRS_DV TIM14_CH1 TIM1_CH1 I2C3_SCL USART1_CK TIM1_CH2 I2C3_SMB A USART1_TX EVENTOUT EVENTOUT OTG_FS_SOF OTG_FS_ID EVENTOUT EVENTOUT TIM13_CH1 SPI1_MOSI AF15 EVENTOUT DCMI_D0 EVENTOUT DCMI_D1 EVENTOUT PA10 TIM1_CH3 USART1_RX PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI SPI1_NSS SPI3_NSS/ I2S3_WS EVENTOUT STM32F405xx, STM32F407xx PA13 TIM 2_CH1 TIM 2_ETR Pinouts and pin description 60/185 Table 9. Alternate function mapping AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT Port AF14 PB2 DocID022152 Rev 4 Port B EVENTOUT PB3 JTDO/ TRACES WO PB4 NJTRST TIM2_CH2 TIM3_CH1 SPI1_SCK SPI3_SCK I2S3_CK SPI1_MISO SPI3_MISO SPI1_MOSI SPI3_MOSI I2S3_SD EVENTOUT I2S3ext_SD PB5 TIM3_CH2 I2C1_SMB A PB6 TIM4_CH1 I2C1_SCL USART1_TX PB7 TIM4_CH2 I2C1_SDA USART1_RX PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK CAN2_RX OTG_HS_ULPI_ D7 I2C2_SCL PB11 TIM2_CH4 I2C2_SDA PB12 TIM1_BKIN I2C2_SMB A PB13 TIM1_CH1N PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD ETH _PPS_OUT DCMI_D10 EVENTOUT DCMI_D5 EVENTOUT FSMC_NL DCMI_VSYN C EVENTOUT SDIO_D4 DCMI_D6 EVENTOUT SDIO_D5 DCMI_D7 EVENTOUT CAN2_TX ETH _MII_TXD3 CAN1_TX USART3_TX OTG_HS_ULPI_ D3 ETH_ MII_RX_ER EVENTOUT USART3_RX OTG_HS_ULPI_ D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_ D5 ETH _MII_TXD0 ETH _RMII_TXD0 SPI2_SCK I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_ D6 ETH _MII_TXD1 ETH _RMII_TXD1 USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT TIM12_CH2 OTG_HS_DP EVENTOUT I2S2ext_SD OTG_HS_ID EVENTOUT EVENTOUT 61/185 Pinouts and pin description TIM2_CH3 RTC_ REFIN EVENTOUT CAN1_RX PB10 PB15 AF15 STM32F405xx, STM32F407xx Table 9. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port OTG_HS_ULPI_ STP PC0 PC1 Port C AF14 AF15 EVENTOUT ETH_MDC EVENTOUT OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC2 SPI2_MISO PC3 SPI2_MOSI I2S2_SD DocID022152 Rev 4 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 TIM3_CH4 TIM8_CH4 PC9 MCO2 I2S2_MCK PC12 USART6_TX I2S3_MCK I2C3_SDA I2S3ext_SD SDIO_D6 DCMI_D0 EVENTOUT USART6_RX SDIO_D7 DCMI_D1 EVENTOUT USART6_CK SDIO_D0 DCMI_D2 EVENTOUT SDIO_D1 DCMI_D3 EVENTOUT I2S_CKIN PC10 PC11 I2S2ext_SD SPI3_SCK/ I2S3_CK USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT SPI3_MISO/ USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT Pinouts and pin description 62/185 Table 9. Alternate function mapping (continued) AF0 STM32F405xx, STM32F407xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PD0 CAN1_RX PD1 PD2 CAN1_TX TIM3_ETR UART5_RX AF14 FSMC_D2 EVENTOUT FSMC_D3 SDIO_CMD AF15 EVENTOUT DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT Port D DocID022152 Rev 4 PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT USART3_RTS FSMC_A17 EVENTOUT PD12 TIM4_CH1 PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT STM32F405xx, STM32F407xx Table 9. Alternate function mapping (continued) AF0 Pinouts and pin description 63/185 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI FSMC_NBL0 DCMI_D2 EVENTOUT FSMC_NBL1 DCMI_D3 EVENTOUT Port PE0 TIM4_ETR PE1 Port E AF14 AF15 PE2 TRACECL K PE3 TRACED0 FSMC_A19 PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 ETH _MII_TXD3 FSMC_A23 EVENTOUT EVENTOUT Pinouts and pin description 64/185 Table 9. Alternate function mapping (continued) AF0 EVENTOUT DocID022152 Rev 4 PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT STM32F405xx, STM32F407xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port AF14 AF15 PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT FSMC_ NIOWR EVENTOUT STM32F405xx, STM32F407xx Table 9. Alternate function mapping (continued) AF0 Port F DocID022152 Rev 4 PF8 TIM13_CH1 PF9 TIM14_CH1 PF10 FSMC_CD EVENTOUT FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Pinouts and pin description 65/185 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PG0 Port G AF14 AF15 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT FSMC_INT3 EVENTOUT PG7 USART6_CK PG8 USART6_ RTS PG9 USART6_RX ETH _PPS_OUT DocID022152 Rev 4 PG10 ETH _MII_TX_EN ETH _RMII_ TX_EN PG11 Pinouts and pin description 66/185 Table 9. Alternate function mapping (continued) AF0 EVENTOUT FSMC_NE2/ FSMC_NCE3 EVENTOUT FSMC_ NCE4_1/ FSMC_NE3 EVENTOUT FSMC_NCE4_ 2 EVENTOUT FSMC_NE4 EVENTOUT PG12 USART6_ RTS PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_ CTS DCMI_D13 EVENTOUT STM32F405xx, STM32F407xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port AF14 PH0 AF15 EVENTOUT PH1 EVENTOUT PH2 PH3 PH4 I2C2_SDA PH6 I2C2_SMB A PH7 I2C3_SCL EVENTOUT ETH _MII_COL EVENTOUT OTG_HS_ULPI_ NXT I2C2_SCL PH5 ETH _MII_CRS EVENTOUT EVENTOUT TIM12_CH1 ETH _MII_RXD2 STM32F405xx, STM32F407xx Table 9. Alternate function mapping (continued) AF0 EVENTOUT ETH _MII_RXD3 EVENTOUT Port H DocID022152 Rev 4 PH8 I2C3_SDA PH9 I2C3_SMB A TIM12_CH2 DCMI_HSYN C EVENTOUT DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N PH14 TIM8_CH2N CAN1_TX DCMI_D4 EVENTOUT EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Pinouts and pin description 67/185 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PI0 TIM5_CH4 PI1 PI2 Port I AF14 AF15 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT DCMI_D9 EVENTOUT DCMI_D10 EVENTOUT TIM8_CH4 SPI2_MISO PI3 TIM8_ETR SPI2_MOSI I2S2_SD I2S2ext_SD PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_ VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 DocID022152 Rev 4 PI9 EVENTOUT CAN1_RX EVENTOUT PI10 PI11 Pinouts and pin description 68/185 Table 9. Alternate function mapping (continued) AF0 ETH _MII_RX_ER OTG_HS_ULPI_ DIR EVENTOUT EVENTOUT STM32F405xx, STM32F407xx STM32F405xx, STM32F407xx 4 Memory mapping Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40x memory map Reserved CORTEX-M4 internal peripherals Reserved AHB3 Reserved 0xE010 0000 - 0xFFFF FFFF 0xE000 0000 - 0xE00F FFFF 0xA000 1000 - 0xDFFF FFFF 0xA000 0FFF 0x6000 0000 0x5006 0C00 - 0x5FFF FFFF 0x5006 0BFF AHB2 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M4's internal peripherals Reserved 0x5000 0000 0x4008 0000 - 0x4FFF FFFF 0x4007 FFFF 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF AHB1 512-Mbyte block 5 FSMC registers 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 Reserved 0x4002 000 0x4001 5800 - 0x4001 FFFF 0x4001 57FF 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals APB2 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 Reserved SRAM (16 KB aliased by bit-banding) SRAM (112 KB aliased by bit-banding) Reserved Option Bytes Reserved System memory + OTP Reserved CCM data RAM (64 KB data SRAM) Reserved Flash Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins 0x2002 0000 - 0x3FFF FFFF 0x2001 C000 - 0x2001 FFFF Reserved 0x4001 0000 0x4000 7800 - 0x4000 FFFF 0x4000 7FFF 0x2000 0000 - 0x2001 BFFF 0x1FFF C008 - 0x1FFF FFFF 0x1FFF C000 - 0x1FFF C007 0x1FFF 7A10 - 0x1FFF 7FFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1001 0000 - 0x1FFE FFFF APB1 0x1000 0000 - 0x1000 FFFF 0x0810 0000 - 0x0FFF FFFF 0x0800 0000 - 0x080F FFFF 0x0010 0000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF 0x4000 0000 ai18513f DocID022152 Rev 4 69/185 Memory mapping STM32F405xx, STM32F407xx Table 10. STM32F40x register boundary addresses Bus Cortex-M4 AHB3 AHB2 70/185 Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 1000 - 0xDFFF FFFF Reserved 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF FSMC bank 4 0x8000 0000 - 0x8FFF FFFF FSMC bank 3 0x7000 0000 - 0x7FFF FFFF FSMC bank 2 0x6000 0000 - 0x6FFF FFFF FSMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF RNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4008 0000- 0x4FFF FFFF Reserved DocID022152 Rev 4 STM32F405xx, STM32F407xx Memory mapping Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9400 - 0x4003 FFFF Reserved 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF ETHERNET MAC 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF AHB1 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 5800- 0x4001 FFFF Reserved DocID022152 Rev 4 71/185 Memory mapping STM32F405xx, STM32F407xx Table 10. STM32F40x register boundary addresses (continued) Bus APB2 72/185 Boundary address Peripheral 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7800- 0x4000 FFFF Reserved DocID022152 Rev 4 STM32F405xx, STM32F407xx Memory mapping Table 10. STM32F40x register boundary addresses (continued) Bus APB1 Boundary address Peripheral 0x4000 7800 - 0x4000 7FFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 DocID022152 Rev 4 73/185 Electrical characteristics STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Pin input voltage STM32F pin STM32F pin C = 50 pF OSC_OUT (Hi-Z when using HSE or LSE) VIN OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 MS19011V1 74/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Power supply scheme Figure 21. Power supply scheme VBAT VBAT = 1.65 to 3.6V OUT GPIOs IN VCAP_1 VCAP_2 2 × 2.2 μF VDD VDD 1/2/...14/15 VSS 1/2/...14/15 15 × 100 nF + 1 × 4.7 μF Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch Level shifter 5.1.6 Electrical characteristics IO Logic Kernel logic (CPU, digital & RAM) Voltage regulator Flash memory BYPASS_REG PDR_ON VDD VDDA VREF 100 nF + 1 μF Reset controller 100 nF + 1 μF VREF+ VREF- ADC Analog: RCs, PLL,.. VSSA MS19911V2 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply supervisor. 3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. DocID022152 Rev 4 75/185 Electrical characteristics 5.1.7 STM32F405xx, STM32F407xx Current consumption measurement Figure 22. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 11. Voltage characteristics Symbol Ratings VDD–VSS External main supply voltage (including VDDA, VDD)(1) VIN |ΔVDDx| |VSSX − VSS| VESD(HBM) Min Max –0.3 4.0 VSS–0.3 VDD+4 VSS–0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 Input voltage on five-volt tolerant pin(2) Input voltage on any other pin Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. 76/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 12. Current characteristics Symbol Ratings Max. IVDD Total current into VDD power lines (source)(1) 150 IVSS (1) Total current out of VSS ground lines (sink) 150 Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IIO IINJ(PIN) (2) ΣIINJ(PIN) (4) Injected current on five-volt tolerant I/O (3) Unit mA –5/+0 (4) ±5 Injected current on any other pin Total injected current (sum of all I/O and control pins) (5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 84/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF 50 45 40 IDD RUN(mA) 35 -45 °C 30 0 °C 25 25 °C 20 55 °C 85 °C 15 105 °C 10 5 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19974V1 Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON 100 90 80 IDD RUN(mA) 70 -45°C 60 0°C 50 25°C 40 55°C 85°C 30 105°C 20 10 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19975V1 DocID022152 Rev 4 85/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF 60 50 IDD RUN(mA) 40 -45°C 0°C 30 25°C 55°C 20 85°C 105°C 10 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19976V1 Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON 120 100 IDD RUN(mA) 80 -45°C 0°C 60 25°C 55°C 40 85°C 105°C 20 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19977V1 86/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 22. Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 °C TA = 85 °C TA = 105 °C 168 MHz 59 77 84 144 MHz 46 61 67 120 MHz 38 53 60 90 MHz 30 44 51 60 MHz 20 34 41 30 MHz 11 24 31 25 MHz 8 21 28 16 MHz 6 18 25 8 MHz 3 16 23 4 MHz 2 15 22 2 MHz 2 14 21 168 MHz 12 27 35 144 MHz 9 22 29 120 MHz 8 20 28 90 MHz 7 19 26 60 MHz 5 17 24 30 MHz 3 16 23 25 MHz 2 15 22 16 MHz 2 14 21 8 MHz 1 14 21 4 MHz 1 13 21 2 MHz 1 13 21 Unit mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). DocID022152 Rev 4 87/185 Electrical characteristics STM32F405xx, STM32F407xx Table 23. Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Supply current in Stop mode with main regulator in Run mode IDD_STOP Supply current in Stop mode with main regulator in Low Power mode Conditions Max TA = 25 °C TA = 25 °C Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.40 1.5 11.00 20.00 Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.31 1.1 8.00 15.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.28 1.1 8.00 15.00 TA = TA = 85 °C 105 °C Unit mA Table 24. Typical and maximum current consumptions in Standby mode Max(1) Typ Symbol Parameter Backup SRAM ON, lowspeed oscillator and RTC ON Backup SRAM OFF, lowSupply current speed oscillator and RTC ON IDD_STBY in Standby Backup SRAM ON, RTC mode OFF Backup SRAM OFF, RTC OFF TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.0 3.4 4.0 20 36 2.4 2.7 3.3 16 32 2.4 2.6 3.0 12.5 24.8 1.7 1.9 2.2 9.8 19.2 Unit VDD = 3.6 V µA 1. Based on characterization, not tested in production. 88/185 TA = 85 °C TA = 25 °C Conditions DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 25. Typical and maximum current consumptions in VBAT mode Max(1) Typ Symbol Parameter Backup IDD_VBA domain supply T current TA = 85 °C TA = 25 °C Conditions TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.86 5 10 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 2 4 Unit µA 1. Based on characterization, not tested in production. Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) 3.5 3 IVBAT in (μA) 2.5 1.65V 1.8V 2 2V 2.4V 1.5 2.7V 3V 3.3V 1 3.6V 0.5 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (°C) MS19990V1 DocID022152 Rev 4 89/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) 6 5 IVBAT in (μA) 4 1.65V 1.8V 2V 3 2.4V 2.7V 3V 2 3.3V 3.6V 1 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (°C) MS19991V1 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 47: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 27: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU 90/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID022152 Rev 4 91/185 Electrical characteristics STM32F405xx, STM32F407xx Table 26. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ 2 MHz 0.02 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.82 60 MHz -(3) VDD = 3.3 V(2) C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS IDDIO I/O switching current VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP package pin (pad removal). 3. At 60 MHz, C maximum load is specified 30 pF. 92/185 DocID022152 Rev 4 Unit mA STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz. • The code is running from Flash memory and the Flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. • ART accelerator and Cache off. • The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 27. Peripheral current consumption Peripheral(1) AHB1 AHB2 168 MHz 144 MHz GPIO A 0.49 0.36 GPIO B 0.45 0.33 GPIO C 0.45 0.34 GPIO D 0.45 0.34 GPIO E 0.47 0.35 GPIO F 0.45 0.33 GPIO G 0.44 0.33 GPIO H 0.45 0.34 GPIO I 0.44 0.33 OTG_HS + ULPI 4.57 3.55 CRC 0.07 0.06 BKPSRAM 0.11 0.08 DMA1 6.15 4.75 DMA2 6.24 4.8 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 3.28 2.54 OTG_FS 4.59 3.69 DCMI 1.04 0.80 DocID022152 Rev 4 Unit mA mA 93/185 Electrical characteristics STM32F405xx, STM32F407xx Table 27. Peripheral current consumption (continued) Peripheral(1) AHB3 APB1 168 MHz 144 MHz FSMC 2.18 1.67 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 I2C3 0.18 0.13 (2) 0.17/0.16 0.13/0.12 (2) 0.16/0.14 0.12/0.12 CAN1 0.27 0.21 CAN2 0.26 0.20 SPI2/I2S2 SPI3/I2S3 DAC 0.14 0.10 (3) 0.91 0.89 2(4) 0.91 0.89 DAC channel 1 and 2(3)(4) 1.69 1.68 WWDG 0.04 0.04 DAC channel 1 DAC channel 94/185 DocID022152 Rev 4 Unit mA STM32F405xx, STM32F407xx Electrical characteristics Table 27. Peripheral current consumption (continued) Peripheral(1) APB2 168 MHz 144 MHz SDIO 0.64 0.54 TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 (5) 2.20 2.10 ADC2(5) 2.04 1.93 (5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 ADC1 ADC3 Unit mA 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 bit is set in DAC_CR register. 4. EN2 bit is set in DAC_CR register. 5. ADON bit set in ADC_CR2 register. 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 28 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 28. Low-power mode wakeup timings Symbol tWUSLEEP(2) tWUSTOP(2) tWUSTDBY(2)(3) Min(1) Typ(1) Max(1) Unit Wakeup from Sleep mode - 1 - µs Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - 260 375 480 Parameter Wakeup from Standby mode µs µs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. DocID022152 Rev 4 95/185 Electrical characteristics 5.3.8 STM32F405xx, STM32F407xx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 29. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 - 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 OSC_IN input capacitance(1) - 5 - pF 45 - 55 % - - ±1 µA V ns Cin(HSE) DuCy(HSE) Duty cycle VSS ≤ VIN ≤ VDD OSC_IN Input leakage current IL 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 30 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 30. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 OSC32_IN input capacitance(1) - 5 - pF 30 - 70 % - - ±1 µA Cin(LSE) DuCy(LSE) IL ns Duty cycle OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD 1. Guaranteed by design, not tested in production. 96/185 V DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32F ai17528 Figure 31. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F ai17529 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID022152 Rev 4 97/185 Electrical characteristics STM32F405xx, STM32F407xx Table 31. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol fOSC_IN RF IDD gm tSU(HSE(3) Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - Startup 5 - - mA/V VDD is stabilized - 2 - ms HSE current consumption Oscillator transconductance Startup time µA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MH z resonator CL2 fHSE OSC_IN REXT(1) RF OSC_OU T Bias controlled gain STM32F ai17530 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 98/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 µA gm Oscillator Transconductance 2.8 - - µA/V - 2 - s tSU(LSE)(2) startup time VDD is stabilized 1. Guaranteed by design, not tested in production. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator RF Bias controlled gain OSC32_OU T CL2 STM32F ai17531 5.3.9 Internal clock source characteristics The parameters given in Table 33 and Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 33. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit - 16 - MHz - - 1 % TA = –40 to 105 °C(2) –8 - 4.5 % TA = –10 to 85 °C(2) –4 - 4 % TA = 25 °C –1 - 1 % HSI oscillator startup time - 2.2 4 µs HSI oscillator power consumption - 60 80 µA Frequency User-trimmed with the RCC_CR register ACCHSI tsu(HSI)(3) IDD(HSI) Accuracy of the HSI oscillator Factorycalibrated DocID022152 Rev 4 99/185 Electrical characteristics STM32F405xx, STM32F407xx 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Low-speed internal (LSI) RC oscillator Table 34. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.6 µA IDD(LSI) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Figure 34. ACCLSI versus temperature 50 max 40 avg min Normalized deviati on (%) 30 20 10 0 -10 -20 -30 -40 -45 -35 -25 -15 -5 5 15 25 35 45 Temperat ure (°C) 55 65 75 85 95 105 MS19013V1 5.3.10 PLL characteristics The parameters given in Table 35 and Table 36 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. 100/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 35. Main PLL characteristics Symbol Parameter Min Typ Max Unit 0.95(2) 1 2.10 MHz 24 - 168 MHz - 48 75 MHz 192 - 432 MHz VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 25 - peak to peak - ±150 - RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA fPLL_IN PLL input clock(1) fPLL_OUT PLL multiplier output clock fPLL48_OUT 48 MHz PLL multiplier output clock fVCO_OUT PLL VCO output tLOCK PLL lock time Conditions Cycle-to-cycle jitter System clock 120 MHz Period Jitter Jitter(3) µs ps 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit 0.95(2) 1 2.10 MHz - - 216 MHz 192 - 432 MHz VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 clock(1) fPLLI2S_IN PLLI2S input fPLLI2S_OUT PLLI2S multiplier output clock fVCO_OUT PLLI2S VCO output tLOCK PLLI2S lock time DocID022152 Rev 4 µs 101/185 Electrical characteristics STM32F405xx, STM32F407xx Table 36. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz - 0.40 0.85 mA Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master I2S clock jitter Jitter(3) 0.30 0.55 Unit 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 43: EMI characteristics). It is available only on the main PLL. Table 37. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215−1 - MODEPER * INCSTEP - 1. Guaranteed by design, not tested in production. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ⁄ ( 4 × fMod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250 102/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 15 – 1 ) × PLLN ) As a result: md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 15 – 1 ) × 240 ) = 2.002%(peak) Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) md F0 md tmode 2 x tmode Time ai17291 DocID022152 Rev 4 103/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 36. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) F0 2 x md tmode Time 2 x tmode ai17292 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 38. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.8 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - Write / Erase 32-bit mode, VDD = 3.3 V - 12 - Unit mA Table 39. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time 104/185 Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 DocID022152 Rev 4 µs ms STM32F405xx, STM32F407xx Electrical characteristics Table 39. Flash memory programming (continued) Symbol tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Conditions Min(1) Typ Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V Parameter Mass erase time Programming voltage Max(1) Unit ms s s 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. DocID022152 Rev 4 105/185 Electrical characteristics STM32F405xx, STM32F407xx Table 40. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s 2.7 - 3.6 V TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(3) Cumulative time during which VPP is applied 1. Guaranteed by design, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 41. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C Unit kcycles Years 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: 106/185 • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP176, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK = 168 MHz, conforms to induce a functional disturbance IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. DocID022152 Rev 4 107/185 Electrical characteristics STM32F405xx, STM32F407xx Table 43. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/168 MHz VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled SEMI 5.3.14 Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and PLL spread spectrum enabled 0.1 to 30 MHz 32 30 to 130 MHz 25 130 MHz to 1GHz 29 SAE EMI Level 4 0.1 to 30 MHz 19 30 to 130 MHz 16 130 MHz to 1GHz 18 SAE EMI level 3.5 dBµV - dBµV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) 2 2000(2) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 V II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. 108/185 Unit DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 45. Electrical sensitivities Symbol LU 5.3.15 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 46. Table 46. I/O current injection susceptibility Functional susceptibility Symbol IINJ(1) Description Negative injection Positive injection Injected current on all FT pins –5 +0 Injected current on any other pin –5 +5 Unit mA 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. DocID022152 Rev 4 109/185 Electrical characteristics STM32F405xx, STM32F407xx Table 47. I/O static characteristics Symbol VIL VIH (1) Parameter Conditions Min Typ Max TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 2.0 - - - - 0.3VDD - - - - - 200 - 5% VDD(3) - - VSS ≤ VIN ≤ VDD - - ±1 VIN = 5 V - - 3 30 40 50 PA10 and PB12 8 11 15 All pins except for PA10 and PB12 30 40 50 8 11 15 Input low level voltage Input high level voltage VIL Input low level voltage VIH(1) Input high level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V (2) I/O Schmitt trigger voltage hysteresis Vhys Ilkg RPU RPD IO FT Schmitt trigger voltage hysteresis(2) I/O input leakage current (4) I/O FT input leakage current (4) Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor All pins except for PA10 and PB12 V mV µA VIN = VSS kΩ VIN = VDD PA10 and PB12 CIO(6) 0.7VDD Unit I/O pin capacitance 5 pF 1. Tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 6. Guaranteed by design, not tested in production. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. 110/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 48. Output voltage characteristics(1) Symbol Parameter VOL(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions Min Max CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Unit V VDD–0.4 - - 0.4 V 2.4 - - 1.3 V VDD–1.3 - - 0.4 V VDD–0.4 - 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 49, respectively. DocID022152 Rev 4 111/185 Electrical characteristics STM32F405xx, STM32F407xx Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49. I/O AC characteristics(1)(2)(3) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(4) 00 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(4) 01 Typ Max CL = 50 pF, VDD > 2.70 V - - 2 CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD - - TBD - - TBD CL = 50 pF, VDD > 2.70 V - - 25 CL = 50 pF, VDD > 1.8 V - - 12.5(5) CL = 10 pF, VDD > 2.70 V - - 50(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 50 pF, VDD = 1.8 V to 3.6 V Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 40 pF, VDD > 2.70 V - - 50(5) CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time DocID022152 Rev 4 Unit MHz ns tf(IO)out fmax(IO)out Maximum frequency(4) 112/185 Min MHz ns MHz ns STM32F405xx, STM32F407xx Electrical characteristics Table 49. I/O AC characteristics(1)(2)(3) (continued) OSPEEDRy [1:0] bit value(1) Symbol Fmax(IO)ou t 11 tf(IO)out tr(IO)out - tEXTIpw Parameter Conditions Maximum frequency(4) Output high to low level fall time Output low to high level rise time Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(5) CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 - - Pulse width of external signals detected by the EXTI controller Unit MHz ns ns 1. Based on characterization data, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. TBD stands for “to be defined”. 4. The maximum frequency is defined in Figure 37. 5. For maximum frequencies above 50 MHz, the compensation cell should be used. Figure 37. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tr(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 47). Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. DocID022152 Rev 4 113/185 Electrical characteristics STM32F405xx, STM32F407xx Table 50. NRST pin characteristics Symbol VIL(NRST)(1) Parameter NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) Min Typ Max TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 2 - - CMOS ports 1.8 V ≤ VDD ≤ 3.6 V NRST Schmitt trigger voltage hysteresis VF(NRST)(1) (1) TNRST_OUT Generated reset pulse duration 0.3VDD 0.7VDD - V 200 - mV 30 40 50 kΩ - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs VIN = VSS NRST Input filtered pulse NRST Input not filtered pulse - Unit - Weak pull-up equivalent resistor(2) RPU VNF(NRST) Conditions 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 38. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset Filter 0.1 μF STM32Fxxx ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50. Otherwise the reset is not taken into account by the device. 5.3.18 TIM timer characteristics The parameters given in Table 51 and Table 52 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). 114/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 51. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 23.8 - ns Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 42 MHz Timer resolution - 16/32 bit 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 780 µs - tTIMxCLK 0.0119 51130563 µs - 65536 × 65536 tTIMxCLK - 51.1 s 32-bit counter clock period when internal clock is selected fTIMxCLK = 84 MHz 0.0119 APB1= 42 MHz 1 tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. DocID022152 Rev 4 115/185 Electrical characteristics STM32F405xx, STM32F407xx Table 52. Characteristics of TIMx connected to the APB2 domain(1) Symbol tres(TIM) Parameter Conditions Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 5.95 - ns 1 - tTIMxCLK 11.9 - ns 0 fTIMxCLK/2 MHz 0 84 MHz - 16 bit 1 65536 tTIMxCLK - 32768 tTIMxCLK Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period when internal clock is selected fTIMxCLK = 168 MHz APB2 = 84 MHz tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 5.3.19 Communications interfaces I2C interface characteristics The STM32F405xx and STM32F407xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 53. I2C characteristics Standard mode I2C(1) Symbol 116/185 Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 DocID022152 Rev 4 µs ns STM32F405xx, STM32F407xx Electrical characteristics Table 53. I2C characteristics (continued) Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF µs 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. Figure 39. I2C bus AC waveforms and measurement circuit V DD_I2C V DD_I2C RP RP STM32Fxx RS SDA I²C bus RS SCL S T AR T REPEATED S T AR T S T AR T tsu(STA) SD A tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) th(SDA) tw(STO:STA) S TOP SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14979c 1. Rs= series protection resistor. 2. Rp = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. DocID022152 Rev 4 117/185 Electrical characteristics STM32F405xx, STM32F407xx Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 55. SPI dynamic characteristics(1) Symbol Parameter Master mode, SPI1, 2.7V < VDD < 3.6V fSCK SPI clock frequency 1/tc(SCK) Duty(SCK) 118/185 Conditions Slave mode, SPI1, 2.7V < VDD < 3.6V Master mode, SPI1/2/3, 1.7V < VDD < 3.6V Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V Duty cycle of SPI clock frequency Slave mode DocID022152 Rev 4 Min Typ Max Unit 42 - 42 MHz 21 - 21 30 50 70 % STM32F405xx, STM32F407xx Electrical characteristics Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Master mode, SPI presc = 2, 2.7V < VDD < 3.6V Master mode, SPI presc = 2, 1.7V < VDD < 3.6V Min TPCLK-2 NSS setup time Slave mode, SPI presc = 2 4 x TPCLK th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK Data input setup time tsu(SI) th(MI) Data input hold time th(SI) ta(SO) (2) tdis(SO) (3) Data output access time Data output disable time tv(SO) Data output valid/hold time th(SO) tv(MO) th(MO) Data output valid time Data output hold time Max Unit TPCLK-0.5 TPCLK TPCLK+0.5 tsu(NSS) tsu(MI) Typ TPCLK TPCLK+2 - - Master mode 6.5 - - Slave mode 2.5 - - Master mode 2.5 - - Slave mode 4 - - Slave mode, SPI presc = 2 0 - 4 x TPCLK Slave mode, SPI1, 2.7V < VDD < 3.6V 0 - 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0 - 16.5 Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V - 12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V - 18 20.5 Master mode (after enable edge), SPI1 , 2.7V < VDD < 3.6V - - 2.5 Master mode (after enable edge), SPI1/2/3 , 1.7V < VDD < 3.6V - - 4.5 Master mode (after enable edge) 0 - - ns 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID022152 Rev 4 119/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 40. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 41. SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) M SB IN B I T1 IN LSB IN ai14135 120/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 42. SPI timing diagram - master mode High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 DocID022152 Rev 4 121/185 Electrical characteristics STM32F405xx, STM32F407xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 56. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit 256 x 8K 256 x FS(2) MHz Master data: 32 bits - 64 x FS Slave data: 32 bits - 64 x FS fMCK I2S main clock output fCK I2S clock frequency DCK I2S clock frequency duty cycle Slave receiver 30 70 tv(WS) WS valid time Master mode 0 6 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - Master receiver 7.5 - Slave receiver 2 - Master receiver 0 - Slave receiver 0 - Slave transmitter (after enable edge) - 27 Master transmitter (after enable edge) - 20 Master transmitter (after enable edge) 2.5 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) Data input setup time Data input hold time Data output valid time tv(SD_MT) th(SD_MT) Data output hold time - MHz % ns 1. Data based on characterization results, not tested in production. 2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency). Note: 122/185 Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). FS maximum value is supported for each mode/condition. DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 43. I2S slave timing diagram (Philips protocol) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. DocID022152 Rev 4 123/185 Electrical characteristics STM32F405xx, STM32F407xx Table 57. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 58. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels RPD RPU VOH RL of 1.5 kΩ to 3.6 V(4) RL of 15 kΩ to Static output level high PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VSS(4) V V V VIN = VDD kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers Figure 45. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S 124/185 tf tr ai14137 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 59. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr Fall time tf (2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching trfm VCRS Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). USB HS characteristics Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 61 and VDD supply voltage conditions summarized in Table 60, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/outputcharacteristics. Table 60. USB HS DC electrical characteristics Symbol Input level Parameter VDD USB OTG HS operating voltage Min.(1) Max.(1) Unit 2.7 3.6 V 1. All the voltages are measured from the local ground potential. Table 61. USB HS clock timing parameters(1) Parameter Symbol fHCLK value to guarantee proper operation of USB HS interface Frequency (first transition) 8-bit ±10% FSTART_8BIT FSTEADY Duty cycle (first transition) DSTART_8BIT Duty cycle (steady state) ±500 ppm DSTEADY Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM Nominal Max 30 Frequency (steady state) ±500 ppm 8-bit ±10% Min MHz 54 60 66 MHz 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.4 ms Peripheral TSTART_DEV - - 5.6 Host TSTART_HOST - - - - - - PHY preparation time after the first transition TPREP of the input clock DocID022152 Rev 4 Unit ms µs 125/185 Electrical characteristics STM32F405xx, STM32F407xx 1. Guaranteed by design, not tested in production. Table 62. ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 ns 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Figure 46. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC Control out (ULPI_STP) tDC tDD data out (8-bit) ai17361c Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. 126/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 63. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Min.(1) Max.(1) Unit 2.7 3.6 V Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 Table 64. Dynamic characteristics: Ehternet MAC signals for SMI(1) Symbol Parameter Min Typ Max 411 420 425 tMDC MDC cycle time( 2.38 MHz) Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Data based on characterization results, not tested in production. Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 DocID022152 Rev 4 127/185 Electrical characteristics STM32F405xx, STM32F407xx Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Max tsu(RXD) Receive data setup time 9 - tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 1. Data based on characterization results, not tested in production. 128/185 Typ DocID022152 Rev 4 Unit ns STM32F405xx, STM32F407xx Electrical characteristics CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67. ADC characteristics Symbol VDDA VREF+ fADC fTRIG(4) VAIN RAIN(4) Parameter Conditions Min Typ Max Unit 1.8(1) - 3.6 V 1.8(1)(2)(3) - VDDA V VDDA = 1.8(1)(3) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 κΩ - - 6 κΩ - 4 - pF - - 0.100 µs - - 3(7) 1/fADC - - 0.067 µs Power supply Positive reference voltage ADC clock frequency External trigger frequency Conversion voltage range(5) External input impedance See Equation 1 for details RADC(4)(6) Sampling switch resistance CADC(4) Internal sample and hold capacitor tlat(4) Injection trigger conversion latency fADC = 30 MHz tlatr(4) Regular trigger conversion latency fADC = 30 MHz tS(4) Sampling time tSTAB(4) Power-up time fADC = 30 MHz DocID022152 Rev 4 (7) 1/fADC - - 2 0.100 - 16 µs 3 - 480 1/fADC - 2 3 µs 129/185 Electrical characteristics STM32F405xx, STM32F407xx Table 67. ADC characteristics (continued) Symbol tCONV(4) Parameter Conditions Min Typ Max Unit fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs Total conversion time (including sampling time) 9 to 492 (tS for sampling +n-bit resolution for successive approximation) fS(4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+(4) ADC VREF DC current consumption in conversion mode - 300 500 µA IVDDA(4) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Based on characterization, not tested in production. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = ------------------------------------------------------------f ADC × C ADC × ln ( 2 N+2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. 130/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 68. ADC accuracy at fADC = 30 MHz(1) a Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 V SSA 7 4093 4094 4095 4096 VDDA ai14395c 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. DocID022152 Rev 4 131/185 Electrical characteristics STM32F405xx, STM32F407xx EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC STM32F VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VAIN Cparasitic VT 0.6 V IL±1 µA 12-bit converter CADC(1) ai17534 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 132/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF(See note 1) ai17535 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai17536 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. DocID022152 Rev 4 133/185 Electrical characteristics 5.3.21 STM32F405xx, STM32F407xx Temperature sensor characteristics Table 69. Temperature sensor characteristics Symbol Parameter TL(1) Avg_Slope (1) V25(1) tSTART(2) TS_temp (3)(2) Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 mV/°C Voltage at 25 °C - 0.76 V Startup time - 6 10 µs 10 - - µs ADC sampling time when reading the temperature (1 °C accuracy) 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Table 70. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 5.3.22 VBAT monitoring characteristics Table 71. VBAT monitoring characteristics Symbol Parameter Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 134/185 Min DocID022152 Rev 4 STM32F405xx, STM32F407xx 5.3.23 Electrical characteristics Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 72. Embedded internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ –40 °C < TA < +105 °C 1.18 1.21 1.24 V 10 - - µs - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range VDD = 3 V Max Unit TCoeff(2) Temperature coefficient - 30 50 ppm/°C tSTART(2) Startup time - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. Table 73. Internal reference voltage calibration values Symbol VREFIN_CAL 5.3.24 Parameter Memory address Raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B DAC electrical characteristics Table 74. DAC characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VSSA Ground 0 - 0 V Resistive load with buffer ON 5 - - kΩ RLOAD(2) Comments VREF+ ≤ VDDA Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON 0.2 - - V DAC_OUT Higher DAC_OUT voltage with buffer ON max(2) - - VDDA – 0.2 V RO(2) CLOAD(2) DocID022152 Rev 4 It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V 135/185 Electrical characteristics STM32F405xx, STM32F407xx Table 74. DAC characteristics (continued) Symbol Min Typ Max Unit DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - 0.5 - mV DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) - - VREF+ – 1LSB V - 170 240 IVREF+(4) IDDA(4) DNL(4) INL(4) Offset(4) Gain error(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode(3) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) 136/185 It gives the maximum output excursion of the DAC. With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV Given for the DAC in 12-bit configuration Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.5 % Given for the DAC in 12-bit configuration - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Settling time (full scale: for a 10-bit input code transition (4) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value ±4LSB THD(4) µA Comments Total Harmonic Distortion Buffer ON DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Figure 54. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 FSMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. DocID022152 Rev 4 137/185 Electrical characteristics STM32F405xx, STM32F407xx Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FSMC_NOE FSMC_NWE tv(A_NE) FSMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FSMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14991c 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) 138/185 Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low Min Max 2THCLK–0.5 2 THCLK+1 Unit ns 0.5 3 ns 2THCLK–2 2THCLK+ 2 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 4.5 ns Address hold time after FSMC_NOE high 4 - ns FSMC_NOE low time DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK ns tw(NADV) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max Unit 3THCLK 3THCLK+ 4 ns THCLK–0.5 THCLK+0.5 ns FSMC_NWE low time THCLK–1 THCLK+2 ns FSMC_NWE high to FSMC_NE high hold time THCLK–1 - ns - 0 ns FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NEx low to FSMC_A valid DocID022152 Rev 4 139/185 Electrical characteristics STM32F405xx, STM32F407xx Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid THCLK– 2 - ns - 1.5 ns THCLK– 1 - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK–1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK+0.5 ns tw(NADV) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) 140/185 Parameter Min Max Unit 3THCLK–1 3THCLK+1 ns 2THCLK–0.5 2THCLK+0.5 ns THCLK–1 THCLK+1 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 3 ns FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) FSMC_NADV low time FSMC_AD(adress) valid hold time after FSMC_NADV high) th(AD_NADV) 1 2 ns THCLK– 2 THCLK+1 ns THCLK - ns THCLK–1 - ns th(A_NOE) Address hold time after FSMC_NOE high th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) Parameter Min Max Unit FSMC_NE low time 4THCLK–0.5 4THCLK+3 ns FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK -0.5 ns FSMC_NWE low tim e 2THCLK–0.5 2THCLK+3 ns DocID022152 Rev 4 141/185 Electrical characteristics STM32F405xx, STM32F407xx Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) th(NE_NWE) THCLK - ns FSMC_NEx low to FSMC_A valid - 0 ns FSMC_NEx low to FSMC_NADV low 1 2 ns FSMC_NADV low time THCLK– 2 THCLK+ 1 ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) THCLK–2 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK–2 - ns FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) FSMC_NWE high to FSMC_NE high hold time 1. CL = 30 pF. 2. Based on characterization, not tested in production. Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). 142/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FSMC_CLK Data latency = 0 td(CLKL-NExL) t d(CLKL-NExH) FSMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FSMC_NADV td(CLKL-AIV) td(CLKL-AV) FSMC_A[25:16] td(CLKL-NOEH) td(CLKL-NOEL) FSMC_NOE td(CLKL-ADIV) tsu(ADV-CLKH) td(CLKL-ADV) FSMC_AD[15:0] AD[15:0] th(CLKH-ADV) tsu(ADV-CLKH) D1 tsu(NWAITV-CLKH) th(CLKH-ADV) D2 th(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893g Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns 2 - ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns DocID022152 Rev 4 143/185 Electrical characteristics STM32F405xx, STM32F407xx Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high th(CLKH-NWAIT) 0 - ns 4 - ns 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 60. Synchronous multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FSMC_CLK Data latency = 0 td(CLKL-NExL) td(CLKL-NExH) FSMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FSMC_NADV td(CLKL-AV) td(CLKL-AIV) FSMC_A[25:16] td(CLKL-NWEL) td(CLKL-NWEH) FSMC_NWE td(CLKL-ADIV) td(CLKL-Data) td(CLKL-Data) td(CLKL-ADV) AD[15:0] FSMC_AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) FSMC_NBL ai14992g Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns 0 - ns - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) 144/185 Min FSMC_CLK low to FSMC_Ax valid (x=16…25) DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 80. Synchronous multiplexed PSRAM write timings(1)(2) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) 0 - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FSMC_CLK td(CLKL-NExL) td(CLKL-NExH) Data latency = 0 FSMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FSMC_NADV td(CLKL-AIV) td(CLKL-AV) FSMC_A[25:0] td(CLKL-NOEL) td(CLKL-NOEH) FSMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FSMC_D[15:0] D1 tsu(NWAITV-CLKH) th(CLKH-DV) D2 th(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) DocID022152 Rev 4 Min Max Unit 2THCLK –0.5 - ns - 0.5 ns 145/185 Electrical characteristics STM32F405xx, STM32F407xx Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) 0 - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 62. Synchronous non-multiplexed PSRAM write timings tw(CLK) BUSTURN = 0 tw(CLK) FSMC_CLK td(CLKL-NExL) td(CLKL-NExH) Data latency = 0 FSMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FSMC_NADV td(CLKL-AV) td(CLKL-AIV) FSMC_A[25:0] td(CLKL-NWEL) td(CLKL-NWEH) FSMC_NWE td(CLKL-Data) FSMC_D[15:0] td(CLKL-Data) D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKL-NBLH) th(CLKH-NWAITV) FSMC_NBL ai14993g 146/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) d(CLKL-NExL) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns t FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID022152 Rev 4 147/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 63. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1) FSMC_NWE FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14896b 148/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID022152 Rev 4 149/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 th(NCE4_1-AI) tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR tw(NIORD) td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) td(NIORD-D) FSMC_D[15:0] ai14899B 150/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 th(NIOWR-D) tv(NIOWR-D) FSMC_D[15:0] ai14900c Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+0.5 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK +0.5 ns 8THCLK–1 8THCLK+1 ns 5THCLK+2.5 - ns 4.5 - ns 3 - ns 8THCLK–0.5 8THCLK+ 3 ns 5THCLK–1 - ns tw(NOE) td(NOE_NCEx) tsu (D-NOE) FSMC_NOE low width FSMC_NOE high to FSMC_NCEx high FSMC_D[15:0] valid data before FSMC_NOE high th(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns FSMC_NWE low to FSMC_D[15:0] valid - 0 ns tv(NWE-D) th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK –1 - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK –1 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID022152 Rev 4 151/185 Electrical characteristics STM32F405xx, STM32F407xx Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK –1 - ns - 5THCLK– 1 ns 8THCLK– 2 - ns - 5THCLK+ 2.5 ns 5THCLK–1.5 - ns - 5THCLK+ 2 ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 1.5 - ns FSMC_NIORD low width 8THCLK–0.5 - ns tw(NIORD) tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 152/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 69. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901c Figure 70. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902c DocID022152 Rev 4 153/185 Electrical characteristics STM32F405xx, STM32F407xx Figure 71. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) th(NOE-ALE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14912c Figure 72. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913c Table 85. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FSMC_NOE low width Max Unit 4THCLK– 0.5 4THCLK+ 3 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK– 2 - ns 1. CL = 30 pF. 154/185 Min DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Table 86. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FSMC_NWE low width Min Max Unit 4THCLK–1 4THCLK+ 3 ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK –2 - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK–3 - ns - 3THCLK ns 3THCLK–2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 5.3.26 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 13, with the following configuration: • PCK polarity: falling • VSYNC and HSYNC polarity: high • Data format: 14 bits Figure 73. DCMI timing diagram 1/DCMI_PIXCLK Pixel clock tsu(HSYNC) th(HSYNC) tsu(VSYNC) th(HSYNC) HSYNC VSYNC tsu(DATA) th(DATA) DATA[0:13] MS32414V1 Table 87. DCMI characteristics(1) Symbol Parameter Min Max Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 DCMI_PIXCLK Pixel clock input - 54 MHz Dpixel Pixel clock input duty cycle 30 70 % DocID022152 Rev 4 Unit 155/185 Electrical characteristics STM32F405xx, STM32F407xx Table 87. DCMI characteristics(1) (continued) Symbol Parameter Min Max 2.5 - tsu(DATA) Data input setup time th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) HSYNC/VSYNC input setup time 2 - th(HSYNC), th(VSYNC) HSYNC/VSYNC input hold time 0.5 - Unit ns 1. Data based on characterization results, not tested in production. 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 88 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Figure 74. SDIO high-speed mode tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input) ai14887 156/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Electrical characteristics Figure 75. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 88. Dynamic characteristics: SD / MMC characteristics(1) Symbol fPP Parameter Conditions Min Typ Max Unit 48 MHz - Clock frequency in data transfer mode 0 SDIO_CK/fPCLK2 frequency ratio - - 8/3 tW(CKL) Clock low time fpp = 48 MHz 8.5 9 - tW(CKH) Clock high time fpp = 48 MHz 8.3 10 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp = 48 MHz 3 - - tIH Input hold time HS fpp = 48 MHz 0 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp = 48 MHz - 4.5 6 tOH Output hold time HS fpp = 48 MHz 1 - - ns CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp = 24 MHz 1.5 - - tIHD Input hold time SD fpp = 24 MHz 0.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp = 24 MHz - 4.5 7 tOHD Output hold default time SD fpp = 24 MHz 0.5 - - ns 1. Data based on characterization results, not tested in production. 5.3.28 RTC characteristics Table 89. RTC characteristics Symbol Parameter - fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register DocID022152 Rev 4 Min Max 4 - 157/185 Package characteristics STM32F405xx, STM32F407xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 158/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Package characteristics Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline e1 A1 ball location D e e Detail A E e2 G A2 F A Bump side Side view Wafer back side Detail A rotated by 90 °C A1 eee b Seating plane A0JW_ME Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.165 0.190 0.215 0.0065 0.0075 0.0085 A2 0.350 0.380 0.410 0.0138 0.015 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.178 4.218 4.258 0.1645 0.1661 0.1676 E 3.964 3.969 4.004 0.1561 0.1563 0.1576 e 0.400 0.0157 e1 3.600 0.1417 e2 3.200 0.126 F 0.312 0.0123 G 0.385 0.0152 eee 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 4 159/185 Package characteristics STM32F405xx, STM32F407xx Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline A A2 A1 E b E1 e D1 D c L1 L ai14398b 1. Drawing is not to scale. Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 N 1.000 0.0394 Number of pins 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 160/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Package characteristics Figure 78. LQFP64 recommended footprint 48 33 0.3 49 12.7 32 0.5 10.3 10.3 64 17 1.2 1 16 7.8 12.7 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022152 Rev 4 161/185 Package characteristics STM32F405xx, STM32F407xx Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE L D A1 K ccc C L1 D1 D3 51 75 50 100 E E3 E1 b 76 26 PIN 1 1 IDENTIFICATION 25 e 1L_ME_V4 1. Drawing is not to scale. Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1) millimeters inches Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 16.000 16.200 0.6220 0.6299 0.6378 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.0059 0.0079 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 1.000 0° 3.5° 0.0236 0.0295 0.0394 7° 0.080 1. Values in inches are converted from mm and rounded to 4 decimal digits. 162/185 0.0177 DocID022152 Rev 4 0° 3.5° 7° 0.0031 STM32F405xx, STM32F407xx Package characteristics Figure 80. LQFP100 recommended footprint 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022152 Rev 4 163/185 Package characteristics STM32F405xx, STM32F407xx Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline Seating plane C A A2 A1 c b 0.25 mm gage plane ccc C k D D1 A1 D3 L L1 108 73 72 109 E3 E1 144 E 37 Pin 1 identification 1 36 ME_1A e 1. Drawing is not to scale. Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 21.800 D1 19.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 22.000 22.200 0.8583 0.8661 0.874 20.000 20.200 0.7795 0.7874 0.7953 17.500 0.0059 0.0079 0.689 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 17.500 0.6890 e 0.500 0.0197 L L1 164/185 0.450 0.600 0.750 1.000 0.0177 0.0236 0.0394 DocID022152 Rev 4 0.0295 STM32F405xx, STM32F407xx Package characteristics Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol k Min Typ Max Min Typ Max 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. LQFP144 recommended footprint 108 109 73 1.35 72 0.35 0.5 17.85 19.9 144 22.6 37 1 36 19.9 22.6 ai14905c 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022152 Rev 4 165/185 Package characteristics STM32F405xx, STM32F407xx Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline C Seating plane A2 ddd A1 C A A A1 ball A1 ball identifier index area e E F A F D e B R 15 BOTTOM VIEW 1 TOP VIEW Øb (176 + 25 balls) Ø eee M C A B Ø fff M C A0E7_ME_V4 1. Drawing is not to scale. Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 E 9.900 10.000 10.100 0.3898 0.3937 0.3976 A2 e F 0.650 0.425 0.450 0.0256 0.475 0.0167 0.0187 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 166/185 0.0177 DocID022152 Rev 4 STM32F405xx, STM32F407xx Package characteristics Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline C Seating plane 0.25 mm gauge plane A A2 k c A1 ccc C A1 HD L D L1 ZD ZE 89 132 88 133 b E 176 Pin 1 identification HE 45 1 44 e 1T_ME 1. Drawing is not to scale. Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 C 0.090 0.200 0.0035 0.0079 D 23.900 24.100 0.9409 0.9488 E 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 HD 25.900 26.100 1.0200 1.0276 HE 25.900 26.100 1.0200 1.0276 L 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 DocID022152 Rev 4 167/185 Package characteristics STM32F405xx, STM32F407xx Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max ccc Min Typ Max 0.080 k 0° 0.0031 7° 0° 7° 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 85. LQFP176 recommended footprint 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters. 168/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx 6.2 Package characteristics Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 96. Package thermal characteristics Symbol ΘJA Parameter Value Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.65 mm pitch 39 Thermal resistance junction-ambient WLCSP90 - 0.400 mm pitch Unit °C/W 38.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID022152 Rev 4 169/185 Part numbering 7 STM32F405xx, STM32F407xx Part numbering Table 97. Ordering information scheme Example: STM32 F 405 R E T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity 407= STM32F40x, connectivity, camera interface, Ethernet Pin count R = 64 pins O = 90 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 170/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Appendix A Application block diagrams USB OTG full speed (FS) interface solutions Figure 86. USB controller configured as peripheral-only and used in Full speed mode VDD 5V to VDD Volatge regulator (1) VBUS DM OSC_IN PA11//PB14 DP PA12/PB15 VSS OSC_OUT USB Std-B connector STM32F4xx MS19000V5 1. External voltage regulator only needed when building a VBUS powered device. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 87. USB controller configured as host-only and used in full speed mode VDD EN GPIO GPIO+IRQ Overcurrent Current limiter power switch(1) 5 V Pwr STM32F4xx VBUS OSC_IN PA11//PB14 PA12/PB15 DM DP VSS OSC_OUT USB Std-A connector A.1 Application block diagrams MS19001V4 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. DocID022152 Rev 4 171/185 Application block diagrams STM32F405xx, STM32F407xx Figure 88. USB controller configured in dual mode and used in full speed mode VDD 5 V to VDD voltage regulator (1) VDD EN GPIO+IRQ Overcurrent Current limiter power switch(2) 5 V Pwr STM32F4xx VBUS PA9/PB13 DM PA11/PB14 OSC_IN OSC_OUT PA12/PB15 PA10/PB12 DP ID (3) VSS USBmicro-AB connector GPIO MS19002V3 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. 172/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx A.2 Application block diagrams USB OTG high speed (HS) interface solutions Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode STM32F4xx FS PHY USB HS OTG Ctrl DP DM not connected DP ULPI_CLK DM ULPI_D[7:0] ULPI ID(2) ULPI_DIR VBUS ULPI_STP USB connector VSS ULPI_NXT High speed OTG PHY PLL XT1 24 or 26 MHz XT(1) MCO1 or MCO2 XI MS19005V2 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. DocID022152 Rev 4 173/185 Application block diagrams A.3 STM32F405xx, STM32F407xx Ethernet interface solutions Figure 90. MII mode using a 25 MHz crystal STM32 MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MCU Ethernet MAC 10/100 HCLK(1) Ethernet PHY 10/100 MII = 15 pins MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MII + MDC = 17 pins MDIO MDC PPS_OUT(2) XTAL 25 MHz OSC HCLK PLL PHY_CLK 25 MHz MCO1/MCO2 XT1 MS19968V1 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 91. RMII with a 50 MHz oscillator STM32 Ethernet PHY 10/100 MCU RMII_TX_EN Ethernet MAC 10/100 RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII_REF_CLK IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator RMII = 7 pins RMII + MDC = 9 pins MDIO MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC 50 MHz HCLK PLL PHY_CLK 50 MHz XT1 50 MHz MS19969V1 1. fHCLK must be greater than 25 MHz. 174/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Application block diagrams Figure 92. RMII with a 25 MHz crystal and PHY with PLL STM32F Ethernet PHY 10/100 MCU RMII_TX_EN Ethernet MAC 10/100 RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII_REF_CLK IEEE1588 PTP RMII = 7 pins REF_CLK MDIO Timer input trigger Timestamp TIM2 comparator RMII + MDC = 9 pins MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz XTAL 25 MHz OSC PLL HCLK PLL MCO1/MCO2 PHY_CLK 25 MHz XT1 MS19970V1 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. DocID022152 Rev 4 175/185 Revision history 8 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history Date Revision 15-Sep-2011 1 Initial release. 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package and Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages, and removed note 1 and 2. Updated Section 2.2.9: Flexible static memory controller (FSMC). Modified I/Os used to reprogram the Flash memory for CAN2 and USB OTG FS in Section 2.2.13: Boot modes. Updated note in Section 2.2.14: Power supply schemes. PDR_ON no more available on LQFP100 package. Updated Section 2.2.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document. Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 5: USART feature comparison. Removed support of I2C for OTG PHY in Section 2.2.30: Universal serial bus on-the-go full-speed (OTG_FS). Added Table 6: Legend/abbreviations used in the pinout table. Table 7: STM32F40x pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 7: STM32F40x pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa. Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40x memory map. Added IVDD and IVSS maximum values in Table 12: Current characteristics. Added Note 1 related to fHCLK, updated Note 2 in Table 14: General operating conditions, and added maximum power dissipation values. Updated Table 15: Limitations depending on the operating power supply range. 24-Jan-2012 176/185 Changes DocID022152 Rev 4 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 24-Jan-2012 Revision Changes Added V12 in Table 19: Embedded reset and power control block characteristics. Updated Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 25, Figure 26, and Figure 27. Updated Table 22: Typical and maximum current consumption in Sleep mode and removed Note 1. Updated Table 23: Typical and maximum current consumptions in Stop mode and Table 24: Typical and maximum current consumptions in Standby mode, Table 25: Typical and maximum current consumptions in VBAT mode, and Table 26: Switching output I/O current consumption. Section : On-chip peripheral current consumption: modified conditions, and updated Table 27: Peripheral current consumption and Note 2. Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 29: High-speed external user clock characteristics. 2 Added Cin(LSE) in Table 30: Low-speed external user clock (continued) characteristics. Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 35: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 36: PLLI2S (audio PLL) characteristics. Updated Section : Flash memory to specify that the devices are shipped to customers with the Flash memory erased. Updated Table 38: Flash memory characteristics, and added tME in Table 39: Flash memory programming. Updated Table 42: EMS characteristics, and Table 43: EMI characteristics. Updated Table 56: I2S dynamic characteristics Updated Figure 46: ULPI timing diagram and Table 62: ULPI timing. Added tCOUNTER and tMAX_COUNT in Table 51: Characteristics of TIMx connected to the APB1 domain and Table 52: Characteristics of TIMx connected to the APB2 domain. Updated Table 65: Dynamic characteristics: Ethernet MAC signals for RMII. Removed USB-IF certification in Section : USB OTG FS characteristics. DocID022152 Rev 4 177/185 Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 24-Jan-2012 178/185 Revision Changes Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.25: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 60: Synchronous multiplexed PSRAM write timings. Updated Table 96: Package thermal characteristics. Appendix A.1: USB OTG full speed (FS) interface solutions: modified 2 (continued) Figure 86: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 87: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 88: USB controller configured in dual mode and used in full speed mode and added Note 3. Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 89: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2. Added Appendix A.3: Ethernet interface solutions. DocID022152 Rev 4 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 31-May-2012 Revision Changes 3 Updated Figure 5: STM32F40x block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices. Added full information on WLCSP90 package together with corresponding part numbers. Changed number of AHB buses to 3. Modified available Flash memory sizes in Section 2.2.4: Embedded Flash memory. Modified number of maskable interrupt channels in Section 2.2.10: Nested vectored interrupt controller (NVIC). Updated case of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 2.2.16: Voltage regulator. Updated standby mode description in Section 2.2.19: Low-power modes. Added Note 1 below Figure 16: STM32F40x UFBGA176 ballout. Added Note 1 below Figure 17: STM32F40x WLCSP90 ballout. Updated Table 7: STM32F40x pin and ball definitions. Added Table 8: FSMC pin definition. Removed OTG_HS_INTN alternate function in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Removed I2S2_WS on PB6/AF5 in Table 9: Alternate function mapping. Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table 9: Alternate function mapping. Added Table 10: STM32F40x register boundary addresses. Updated Figure 18: STM32F40x memory map. Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power supply scheme. Added power dissipation maximum value for WLCSP90 in Table 14: General operating conditions. Updated VPOR/PDR in Table 19: Embedded reset and power control block characteristics. Updated notes in Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, and Table 22: Typical and maximum current consumption in Sleep mode. Updated maximum current consumption at TA = 25 °n Table 23: Typical and maximum current consumptions in Stop mode. DocID022152 Rev 4 179/185 Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 31-May-2012 180/185 Revision Changes Removed fHSE_ext typical value in Table 29: High-speed external user clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator characteristics and Table 32: LSE oscillator characteristics (fLSE = 32.768 kHz). Added fPLL48_OUT maximum value in Table 35: Main PLL characteristics. Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 38: Flash memory characteristics, Table 39: Flash memory programming, and Table 40: Flash memory programming with VPP. Updated Section : Output driving current. Table 53: I2C characteristics: Note 4 updated and applied to th(SDA) in 3 Fast mode, and removed note 4 related to th(SDA) minimum value. (continued) Updated Table 67: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 68: ADC accuracy at fADC = 30 MHz. Added WLCSP90 thermal resistance in Table 96: Package thermal characteristics. Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data. Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. Added Figure 85: LQFP176 recommended footprint. Removed 256 and 768 Kbyte Flash memory density from Table 97: Ordering information scheme. DocID022152 Rev 4 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes 4 Modified Note 1 below Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 4 title. Updated Note 3 below Figure 21: Power supply scheme. Changed simplex mode into half-duplex mode in Section 2.2.25: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively. Updated pin 36 signal in Figure 15: STM32F40x LQFP176 pinout. Changed pin number from F8 to D4 for PA13 pin in Table 7: STM32F40x pin and ball definitions. Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table 9: Alternate function mapping. Changed system memory into System memory + OTP in Figure 18: STM32F40x memory map. Added Note 1 below Table 16: VCAP_1/VCAP_2 operating conditions. Updated IDDA description in Table 74: DAC characteristics. Removed PA9/PB13 connection to VBUS in Figure 86: USB controller configured as peripheral-only and used in Full speed mode and Figure 87: USB controller configured as host-only and used in full speed mode. Updated SPI throughput on front page and Section 2.2.24: Serial peripheral interface (SPI) Updated operating voltages in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated note in Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated “Regulator ON” paragraph in Section 2.2.16: Voltage regulator Removed note in Section 2.2.19: Low-power modes Corrected wrong reference manual in Section 2.2.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 support Updated Table 15: Limitations depending on the operating power supply range Updated Table 24: Typical and maximum current consumptions in Standby mode Updated Table 25: Typical and maximum current consumptions in VBAT mode Updated Table 36: PLLI2S (audio PLL) characteristics Updated Table 43: EMI characteristics Updated Table 48: Output voltage characteristics Updated Table 50: NRST pin characteristics Updated Table 55: SPI dynamic characteristics Updated Table 56: I2S dynamic characteristics Deleted Table 59 Updated Table 62: ULPI timing Updated Figure 47: Ethernet SMI timing diagram DocID022152 Rev 4 181/185 Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Updated Figure 5: STM32F40x block diagram Updated Section 2: Description Updated footnote (3) in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Updated Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages Updated Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated Section 2.2.16: Voltage regulator, including figures. Updated Table 14: General operating conditions, including footnote (2). Updated Table 15: Limitations depending on the operating power supply range, including footnote (3). Updated footnote (1) in Table 67: ADC characteristics. Updated footnote (3) in Table 68: ADC accuracy at fADC = 30 MHz. Updated footnote (1) in Table 74: DAC characteristics. Updated Figure 9: Regulator OFF. Updated Figure 7: Power supply supervisor interconnection with 4 internal reset OFF. (continued) Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF availability. Updated footnote (2) of Figure 21: Power supply scheme. Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by “I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 9: Alternate function mapping. Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14, PC15, PH0, PH1, PI8 in Table 9: Alternate function mapping Replaced “DCMI_12” by “DCMI_D12” in Table 7: STM32F40x pin and ball definitions. Removed the following sentence from Section : I2C interface characteristics: ”Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14.”. In Table 7: STM32F40x pin and ball definitions on page 45: – For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1, RTC_TS” – for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2, RTC_TS”. – for pin PB15, added RTC_REFIN in Alternate functions column. In Table 9: Alternate function mapping on page 60, for port PB15, replaced “RTC_50Hz” by “RTC_REFIN”. 182/185 DocID022152 Rev 4 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Figure 6: Multi-AHB matrix. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF Changed 1.2 V to V12 in Section : Regulator OFF Updated LQFP176 pin 48. Updated Section 1: Introduction. Updated Section 2: Description. Updated operating voltage in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Note 1. Updated Section 2.2.15: Power supply supervisor. Updated Section 2.2.16: Voltage regulator. Updated Figure 9: Regulator OFF. Updated Table 3: Regulator ON/OFF and internal reset ON/OFF availability. Updated Section 2.2.19: Low-power modes. Updated Section 2.2.20: VBAT operation. Updated Section 2.2.22: Inter-integrated circuit interface (I²C) . Updated pin 48 in Figure 15: STM32F40x LQFP176 pinout. Updated Table 6: Legend/abbreviations used in the pinout table. Updated Table 7: STM32F40x pin and ball definitions. Updated Table 14: General operating conditions. 4 Updated Table 15: Limitations depending on the operating power (continued) supply range. Updated Section 5.3.7: Wakeup time from low-power mode. Updated Table 33: HSI oscillator characteristics. Updated Section 5.3.15: I/O current injection characteristics. Updated Table 47: I/O static characteristics. Updated Table 50: NRST pin characteristics. Updated Table 53: I2C characteristics. Updated Figure 39: I2C bus AC waveforms and measurement circuit. Updated Section 5.3.19: Communications interfaces. Updated Table 67: ADC characteristics. Added Table 70: Temperature sensor calibration values. Added Table 73: Internal reference voltage calibration values. Updated Section 5.3.25: FSMC characteristics. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics. Updated Table 23: Typical and maximum current consumptions in Stop mode. Updated Section : SPI interface characteristics included Table 55. Updated Section : I2S interface characteristics included Table 56. Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. DocID022152 Rev 4 183/185 Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 04-Jun-2013 184/185 Revision Changes Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings. Updated Table 80: Synchronous multiplexed PSRAM write timings. Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read 4 timings. (continued) Updated Table 82: Synchronous non-multiplexed PSRAM write timings. Updated Section 5.3.26: Camera interface (DCMI) timing specifications including Table 87: DCMI characteristics and addition of Figure 73: DCMI timing diagram. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics including Table 88. Updated Chapter Figure 9. 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