STM32F407ZET6

STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions &"'! LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm) WLCSP90 (4.223x3.969 mm) UFBGA176 (10 × 10 mm) • Memories • Up to 1 Mbyte of Flash memory • Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM • Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power operation – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support September 2016 This is information on a product in full production. • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII DocID022152 Rev 8 1/202 www.st.com STM32F405xx, STM32F407xx • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit Reference • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar Table 1. Device summary Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE 2/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM . . 20 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 20 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 21 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 29 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 34 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 36 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 36 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID022152 Rev 8 3/202 Contents STM32F405xx, STM32F407xx 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 37 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 38 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1 4/202 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 82 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 82 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 83 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 106 DocID022152 Rev 8 STM32F405xx, STM32F407xx 6 7 Contents 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 112 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.20 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 161 5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 162 5.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.1 WLCSP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.3 LQPF100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.5 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.6 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 8 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 186 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 188 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DocID022152 Rev 8 5/202 List of tables STM32F405xx, STM32F407xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 6/202 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 14 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F40xxx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 81 VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 82 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 82 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 85 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 90 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 91 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DocID022152 Rev 8 STM32F405xx, STM32F407xx Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. List of tables ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 120 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Dynamic characteristics: Eternity MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 132 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 143 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 144 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 151 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 WLCSP90 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DocID022152 Rev 8 7/202 List of tables STM32F405xx, STM32F407xx Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 95. UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . . 178 Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 98. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 99. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 100. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64 . . . . . . . . . . 16 Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F40xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25 PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29 STM32F40xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F40xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F40xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F40xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F40xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F40xxx WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F40xxx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 87 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 87 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 88 Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 88 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 91 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 92 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DocID022152 Rev 8 9/202 List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. 10/202 STM32F405xx, STM32F407xx SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 129 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 137 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 138 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 143 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 144 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 145 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 146 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 150 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 153 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 154 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 156 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 157 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 160 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 160 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 167 LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 LPQF64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 170 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 173 LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package DocID022152 Rev 8 STM32F405xx, STM32F407xx Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. List of figures recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . . 180 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 182 LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 186 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 187 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DocID022152 Rev 8 11/202 Introduction 1 STM32F405xx, STM32F407xx Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual which is available from the STMicroelectronics website www.st.com. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com. 12/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx 2 Description Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances DocID022152 Rev 8 13/202 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes SRAM in Kbytes 512 System 192(112+16+64) Backup 4 FSMC memory controller Ethernet DocID022152 Rev 8 Timers 1024 1024 512 Yes(1) No No 1024 512 1024 Yes Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator 512 STM32F405xx, STM32F407xx Figure 5 shows the general block diagram of the device family. Yes Description 14/202 Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix 3/2 (full duplex)(2) SPI / I2S I2C 3 USART/ UART 4/2 Communi USB cation OTG FS interfaces USB OTG HS Yes Yes CAN 2 SDIO Yes DocID022152 Rev 8 Camera interface GPIOs 12-bit ADC Number of channels No 51 72 Yes 82 114 72 82 114 140 13 16 24 24 LQFP144 UFBGA176 LQFP176 3 16 13 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz 1.8 to 3.6 V(3) Operating voltage Junction temperature: –40 to + 125 °C LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). STM32F405xx, STM32F407xx Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package Description 15/202 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued) Description 2.1 STM32F405xx, STM32F407xx Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40xxx family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40xxx, STM32F2, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64 633 633       633 633    16/202  DocID022152 Rev 8 7RESISTORORSOLDERINGBRIDGE PRESENTFORTHE34-&XX CONFIGURATIONNOTPRESENTINTHE 34-&XXCONFIGURATION AI STM32F405xx, STM32F407xx Description Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package    966    966 966 966      ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ  966 966 966IRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 9''IRU670)[[ 9'' 966 966IRUWKH670)[[ 966IRUWKH670)[[ 966RU1&IRUWKH670)[[ DLG Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package 966  ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ      966 966 6LJQDOIURP H[WHUQDOSRZHU VXSSO\ VXSHUYLVRU 1RWSRSXODWHGZKHQŸ UHVLVWRURUVROGHULQJ EULGJHSUHVHQW 3'5B21       966 9'' 966 1RWSRSXODWHGIRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 966IRU670)[[ 966IRUWKH670)[[ 9'' 966 9''IRU670)[[ 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ DLG DocID022152 Rev 8 17/202 Description STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages     6LJQDOIURPH[WHUQDO SRZHUVXSSO\ VXSHUYLVRU 3'5B21     9'' 966 7ZRŸUHVLVWRUVFRQQHFWHGWR 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ 069 18/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx 2.2 Description Device overview Figure 5. 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The camera interface and ethernet are available only on STM32F407xx devices. DocID022152 Rev 8 19/202 Description 2.2.1 STM32F405xx, STM32F407xx ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40xxx family. Note: Cortex-M4 with FPU is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the ARM Cortex-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40xxx devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. 20/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx 2.2.5 Description CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40xxx products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID022152 Rev 8 21/202 Description STM32F405xx, STM32F407xx Figure 6. Multi-AHB matrix )#/$% $#/$% !##%, 53"?(3?- -!# 53"/4' %THERNET (3 %4(%2.%4?- $-!?0 '0 $-! $-!?-%- $-!?-%- '0 $-! $-!?0) 3 BUS ) BUS $ BUS !2#ORTEX -  +BYTE ##-DATA2!- &LASH MEMORY 32!- +BYTE 32!- +BYTE !(" PERIPHERALS !(" PERIPHERALS &3-# 3TATIC-EM#TL !0" !0" "USMATRIX 3 AID 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 22/202 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. DocID022152 Rev 8 STM32F405xx, STM32F407xx 2.2.9 Description Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL DocID022152 Rev 8 23/202 Description STM32F405xx, STM32F407xx clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. 24/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Description The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 3'5B21 1567 $SSOLFDWLRQUHVHW VLJQDORSWLRQDO 9'' 069 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. DocID022152 Rev 8 25/202 Description STM32F405xx, STM32F407xx Figure 8. PDR_ON and NRST control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • • Regulator ON – Main regulator mode (MR) – Low-power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) 26/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Description Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. The standby mode is not available • Figure 9. Regulator OFF 9 ([WHUQDO9&$3BSRZHU ƉƉůŝĐĂƚŝŽŶƌĞƐĞƚ VXSSO\VXSHUYLVRU ƐŝŐŶĂů;ŽƉƚŝŽŶĂůͿ ([WUHVHWFRQWUROOHUDFWLYH ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 μA/+0 μA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 47. DocID022152 Rev 8 113/202 Electrical characteristics STM32F405xx, STM32F407xx Table 47. I/O current injection susceptibility Functional susceptibility Symbol IINJ(1) Description Negative injection Positive injection Injected current on BOOT0 pin −0 NA Injected current on NRST pin −0 NA Injected current on PE2, PE3, PE4, PE5, PE6, PI8, PC13, PC14, PC15, PI9, PI10, PI11, PF0, PF1, PF2, PF3, PF4, PF5, PF10, PH0/OSC_IN, PH1/OSC_OUT, PC0, PC1, PC2, PC3, PB6, PB7, PB8, PB9, PE0, PE1, PI4, PI5, PI6, PI7, PDR_ON, BYPASS_REG −0 NA Injected current on all FT pins −5 NA Injected current on any other pin −5 +5 Unit mA 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 48. I/O static characteristics Symbol Parameter FT, TTa and NRST I/O input low level voltage VIL BOOT0 I/O input low level voltage FT, TTa and NRST I/O input low level voltage VIH 114/202 BOOT0 I/O input low level voltage Conditions Min Typ Max - - 0.3VDD-0.04(1) - - 0.3VDD(2) 1.75 V ≤VDD ≤3.6 V -40 °C≤TA ≤105 °C - - 1.7 V ≤VDD ≤3.6 V 0 °C≤TA ≤105 °C - - 0.45VDD+0.3(1) - - 0.7VDD(2) - - - - - - 1.7 V ≤VDD ≤3.6 V 1.7 V ≤VDD ≤3.6 V 1.75 V ≤VDD ≤3.6 V -40 °C≤TA ≤105 °C 1.7 V ≤VDD ≤3.6 V 0 °C≤TA ≤105 °C Unit 0.1VDD-+0.1(1) 0.17VDD DocID022152 Rev 8 +0.7(1) V STM32F405xx, STM32F407xx Electrical characteristics Table 48. I/O static characteristics (continued) Symbol Parameter FT, TTa and NRST I/O input hysteresis VHYS BOOT0 I/O input hysteresis Ilkg RPU RPD CIO(8) Conditions Min Typ Max 1.7 V ≤VDD ≤3.6 V 10%VDD(3) - - 1.75 V ≤VDD ≤3.6 V -40 °C≤TA ≤105 °C V 0.1 - - VSS ≤VIN ≤VDD - - ±1 I/O FT input leakage current (5) VIN = 5 V - - 3 All pins except for PA10 and PB12 (OTG_FS_ID, OTG_HS_ID) VIN = VSS 30 40 50 PA10 and PB12 (OTG_FS_ID, OTG_HS_ID) - 7 10 14 VIN = VDD 30 40 50 - 7 10 14 - 5 - I/O input leakage current (4) Weak pull-up equivalent resistor(6) All pins except for Weak pull-down PA10 and equivalent PB12 resistor(7) PA10 and PB12 1.7 V ≤VDD ≤3.6 V 0 °C≤TA ≤105 °C I/O pin capacitance Unit µA kΩ pF 1. Guaranteed by design. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 47: I/O current injection susceptibility 5. To sustain a voltage higher than VDD + 0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection susceptibility. 6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. DocID022152 Rev 8 115/202 Electrical characteristics STM32F405xx, STM32F407xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 49. Output voltage characteristics(1) Symbol Parameter VOL(2) Output low level voltage VOH(3) Output high level voltage VOL (2) Output low level voltage VOH (3) Output high level voltage VOL(2)(4) Output low level voltage VOH(3)(4) Output high level voltage Conditions Min Max CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD–0.4 - - 0.4 2.4 - - 1.3 VDD–1.3 - - 0.4 VDD–0.4 - TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V VOL(2)(4) Output low level voltage VOH(3)(4) Output high level voltage IIO = +6 mA 2 V < VDD < 2.7 V Unit V V V V 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization. 116/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 50, respectively. Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 50. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 00 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(3) 01 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD > 2.70 V - - 4 CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - 8 CL = 10 pF, VDD > 1.8 V - - 4 CL = 50 pF, VDD = 1.8 V to 3.6 V - - 100 CL = 50 pF, VDD > 2.70 V - - 25 CL = 50 pF, VDD > 1.8 V - - 12.5 CL = 10 pF, VDD > 2.70 V - - 50(4) CL = 10 pF, VDD > 1.8 V - - 20 CL = 50 pF, VDD >2.7 V - - 10 CL = 50 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 6 CL = 10 pF, VDD > 1.8 V - - 10 CL = 40 pF, VDD > 2.70 V - - 50(4) CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(4) CL = 10 pF, VDD > 1.8 V - - 50(4) CL = 40 pF, VDD > 2.70 V - - 6 CL = 40 pF, VDD > 1.8 V - - 10 CL = 10 pF, VDD > 2.70 V - - 4 CL = 10 pF, VDD > 1.8 V - - 6 DocID022152 Rev 8 Unit MHz ns MHz ns MHz ns 117/202 Electrical characteristics STM32F405xx, STM32F407xx Table 50. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(4) CL = 30 pF, VDD > 1.8 V - - 50(4) CL = 10 pF, VDD > 2.70 V - - 180(4) CL = 10 pF, VDD > 1.8 V - - 100(4) CL = 30 pF, VDD > 2.70 V - - 4 CL = 30 pF, VDD > 1.8 V - - 6 CL = 10 pF, VDD > 2.70 V - - 2.5 CL = 10 pF, VDD > 1.8 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller Unit MHz ns ns 1. Guaranteed by characterization. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 37. 4. For maximum frequencies above 50 MHz, the compensation cell should be used. Figure 37. I/O AC characteristics definition       (;7(51$/ 287387 21&/ WU,2RXW WI,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´  118/202 DocID022152 Rev 8 DLG STM32F405xx, STM32F407xx 5.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 48). Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 51. NRST pin characteristics Symbol VIL(NRST)(1) Parameter NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) Min Typ Max TTL ports 2.7 V ≤VDD ≤ 3.6 V - - 0.8 2 - - - 0.3VDD - - CMOS ports 1.8 V ≤VDD ≤ 0.7VDD 3.6 V NRST Schmitt trigger voltage hysteresis (1) VNF(NRST) (1) TNRST_OUT Generated reset pulse duration V - 200 - mV VIN = VSS 30 40 50 kΩ - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs NRST Input filtered pulse NRST Input not filtered pulse Unit - Weak pull-up equivalent resistor(2) RPU VF(NRST) Conditions 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 38. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW  1567  538 ,QWHUQDO5HVHW )LOWHU —) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 51. Otherwise the reset is not taken into account by the device. DocID022152 Rev 8 119/202 Electrical characteristics 5.3.18 STM32F405xx, STM32F407xx TIM timer characteristics The parameters given in Table 52 and Table 53 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 52. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 23.8 - ns Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 42 MHz Timer resolution - 16/32 bit 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 780 µs - tTIMxCLK 0.0119 51130563 µs - 65536 × 65536 tTIMxCLK - 51.1 s 32-bit counter clock period when internal clock is selected fTIMxCLK = 84 MHz 0.0119 APB1= 42 MHz 1 tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. 120/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Table 53. Characteristics of TIMx connected to the APB2 domain(1) Symbol tres(TIM) Parameter Timer resolution time Conditions AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz fEXT ResTIM tCOUNTER Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period when internal clock is selected fTIMxCLK = 168 MHz APB2 = 84 MHz tMAX_COUNT Maximum possible count Min Max Unit 1 - tTIMxCLK 5.95 - ns 1 - tTIMxCLK 11.9 - ns 0 fTIMxCLK/2 MHz 0 84 MHz - 16 bit 1 65536 tTIMxCLK - 32768 tTIMxCLK 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 5.3.19 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0090 reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. Refer to Section 5.3.16: I/O port characteristics for more details on the I2C I/O characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 54. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered DocID022152 Rev 8 121/202 Electrical characteristics STM32F405xx, STM32F407xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 55. SPI dynamic characteristics(1) Symbol Parameter Master mode, SPI1, 2.7V < VDD < 3.6V fSCK SPI clock frequency 1/tc(SCK) Duty(SCK) 122/202 Conditions Slave mode, SPI1, 2.7V < VDD < 3.6V Master mode, SPI1/2/3, 1.7V < VDD < 3.6V Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V Duty cycle of SPI clock frequency Slave mode DocID022152 Rev 8 Min Typ Max Unit 42 - 42 MHz 21 - 21 30 50 70 % STM32F405xx, STM32F407xx Electrical characteristics Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Master mode, SPI presc = 2, 2.7V < VDD < 3.6V Master mode, SPI presc = 2, 1.7V < VDD < 3.6V Min TPCLK-2 NSS setup time Slave mode, SPI presc = 2 4 x TPCLK th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK Data input setup time tsu(SI) th(MI) Data input hold time th(SI) ta(SO) (2) tdis(SO) (3) Data output access time Data output disable time tv(SO) Data output valid/hold time th(SO) tv(MO) th(MO) Data output valid time Data output hold time Max Unit TPCLK-0.5 TPCLK TPCLK+0.5 tsu(NSS) tsu(MI) Typ TPCLK TPCLK+2 - - Master mode 6.5 - - Slave mode 2.5 - - Master mode 2.5 - - Slave mode 4 - - Slave mode, SPI presc = 2 0 - 4 x TPCLK Slave mode, SPI1, 2.7V < VDD < 3.6V 0 - 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0 - 16.5 Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V - 12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V - 18 20.5 Master mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - - 2.5 Master mode (after enable edge), SPI1/2/3, 1.7V < VDD < 3.6V - - 4.5 Master mode (after enable edge) 0 - - ns 1. Guaranteed by characterization. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID022152 Rev 8 123/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 39. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. WVX166 WK166 WZ6&.+ WU6&. 6&.LQSXW &3+$  &32/  &3+$  &32/  WD62 WZ6&./ WY62 WK62 )LUVWELW287 0,62RXWSXW WI6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, WVX6, )LUVWELW,1 026,LQSXW 1H[WELWV,1 /DVWELW,1 06Y9 Figure 40. SPI timing diagram - slave mode and CPHA = 1 166LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 6&.LQSXW &3+$  &32/  &3+$  &32/  0,62RXWSXW WY62 )LUVWELW287 WVX6, 026,LQSXW WK62 1H[WELWV287 WU6&. WGLV62 /DVWELW287 WK6, )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 124/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 41. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$  &32/  6&.2XWSXW WF6&. &3+$  &32/  &3+$  &32/  &3+$  &32/  WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ WU6&. WI6&. %,7,1 06%,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF DocID022152 Rev 8 125/202 Electrical characteristics STM32F405xx, STM32F407xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 56. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit 256 x 8K 256 x FS(2) MHz Master data: 32 bits - 64 x FS Slave data: 32 bits - 64 x FS fMCK I2S main clock output fCK I2S clock frequency DCK I2S clock frequency duty cycle Slave receiver 30 70 tv(WS) WS valid time Master mode 0 6 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - Master receiver 7.5 - Slave receiver 2 - Master receiver 0 - Slave receiver 0 - Slave transmitter (after enable edge) - 27 Master transmitter (after enable edge) - 20 Master transmitter (after enable edge) 2.5 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) Data input setup time Data input hold time Data output valid time tv(SD_MT) th(SD_MT) Data output hold time - MHz % ns 1. Guaranteed by characterization. 2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency). Note: 126/202 Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). FS maximum value is supported for each mode/condition. DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 42. I2S slave timing diagram (Philips protocol) &.,QSXW WF&. &32/  &32/  WZ&.+ WK:6 WZ&./ :6LQSXW WY6'B67 WVX:6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW %LWQWUDQVPLW WVX6'B65 /6%UHFHLYH 6'UHFHLYH WK6'B67 /6%WUDQVPLW WK6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH DLE 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 43. I2S master timing diagram (Philips protocol)(1) TF#+ TR#+ #+OUTPUT TC#+ #0/, TW#+( #0/, TV73 TH73 TW#+, 73OUTPUT TV3$?-4 3$TRANSMIT ,3"TRANSMIT -3"TRANSMIT ,3"RECEIVE ,3"TRANSMIT TH3$?-2 TSU3$?-2 3$RECEIVE "ITNTRANSMIT TH3$?-4 -3"RECEIVE "ITNRECEIVE ,3"RECEIVE AIB 1. Guaranteed by characterization. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID022152 Rev 8 127/202 Electrical characteristics STM32F405xx, STM32F407xx USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 57. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 58. USB OTG FS DC electrical characteristics Symbol Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit - 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold - 1.3 - 2.0 VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 VDD Input levels Parameter Output levels RPD RPU VOH Static output level high RL of 15 kΩ to PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VSS(4) V V V VIN = VDD kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG FS drivers 128/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 44. USB OTG FS timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 59. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr tf Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Rise/ fall time matching trfm Output signal crossover voltage VCRS 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). USB HS characteristics Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 61 and VDD supply voltage conditions summarized in Table 60, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Table 60. USB HS DC electrical characteristics Symbol Input level Parameter USB OTG HS operating voltage VDD Min.(1) Max.(1) Unit 2.7 3.6 V 1. All the voltages are measured from the local ground potential. Table 61. USB HS clock timing parameters(1) Parameter Symbol Min Nominal Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz Frequency (first transition) 54 60 66 MHz 8-bit ±10% FSTART_8BIT DocID022152 Rev 8 129/202 Electrical characteristics STM32F405xx, STM32F407xx Table 61. USB HS clock timing parameters(1) Parameter Symbol Frequency (steady state) ±500 ppm FSTEADY Duty cycle (first transition) DSTART_8BIT 8-bit ±10% Duty cycle (steady state) ±500 ppm DSTEADY Min Nominal Max Unit 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.4 ms Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 Host TSTART_HOST - - - - - - PHY preparation time after the first transition TPREP of the input clock ms µs 1. Guaranteed by design. Table 62. ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 ns 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Figure 45. ULPI timing diagram #LOCK #ONTROL)N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA)N  BIT T$# #ONTROLOUT 5,0)?340 DATAOUT  BIT T$# T$$ AIC 130/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Table 63. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Min.(1) Max.(1) Unit 2.7 3.6 V Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 46 shows the corresponding timing diagram. Figure 46. Ethernet SMI timing diagram W0'& (7+B0'& WG0',2 (7+B0',22 WVX0',2 WK0',2 (7+B0',2, 069 Table 64. Dynamic characteristics: Eternity MAC signals for SMI(1) Symbol Parameter Min Typ Max 411 420 425 tMDC MDC cycle time(2.38 MHz) Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization. Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 47 shows the corresponding timing diagram. DocID022152 Rev 8 131/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 47. Ethernet RMII timing diagram 2-))?2%&?#,+ TD48%. TD48$ 2-))?48?%. 2-))?48$;= TSU28$ TSU#23 TIH28$ TIH#23 2-))?28$;= 2-))?#23?$6 AI Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 66 gives the list of Ethernet MAC signals for MII and Figure 47 shows the corresponding timing diagram. Figure 48. Ethernet MII timing diagram -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 TSU28$ TSU%2 TSU$6 TIH28$ TIH%2 TIH$6 -))?48?#,+ TD48%. TD48$ -))?48?%. -))?48$;= AI 132/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 9 - tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 Unit ns 1. Guaranteed by characterization. 5.3.20 CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.21 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67. ADC characteristics Symbol Parameter Conditions Min Typ Max - 3.6 Unit VDDA Power supply - 1.8(1) VREF+ Positive reference voltage - 1.8(1)(2)(3) - VDDA VREF− Negative reference voltage - - 0 - 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 κΩ - - - 6 κΩ - - 4 - pF (1)(3) fADC fTRIG(4) VAIN RAIN(4) ADC clock frequency External trigger frequency Conversion voltage range(5) External input impedance RADC(4)(6) Sampling switch resistance CADC(4) Internal sample and hold capacitor VDDA = 1.8 2.4 V to DocID022152 Rev 8 V 133/202 Electrical characteristics STM32F405xx, STM32F407xx Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 0.100 µs - - 3(7) 1/fADC - - 0.067 µs tlat(4) Injection trigger conversion latency fADC = 30 MHz tlatr(4) Regular trigger conversion latency fADC = 30 MHz tS(4) Sampling time tSTAB(4) Power-up time tCONV(4) Total conversion time (including sampling time) (7) - 2 fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC - - 2 3 µs fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) fS(4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 1/fADC - 1/fADC 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+(4) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(4) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Guaranteed by characterization. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. 134/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 68. ADC accuracy at fADC = 30 MHz Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(2) to 3.6 V Typ Max(1) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Guaranteed by characterization. 2. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and SIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. DocID022152 Rev 8 135/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 49. ADC accuracy characteristics 6 $$! 6 2%& ;,3" )$%!, ORDEPENDINGONPACKAGE =   %'     %4      %/  %,  %$  , 3")$%!,   6 33!          6$$! AIC 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 50. Typical connection diagram using the ADC 670) 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/“—$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 136/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() —)Q) 9''$ —)Q)  966$95() DLE 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. DocID022152 Rev 8 137/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$  —)Q) 95()966$  DLF 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 5.3.22 Temperature sensor characteristics Table 69. Temperature sensor characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART (2) TS_temp(2) Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 mV/°C Voltage at 25 °C - 0.76 V Startup time - 6 10 µs 10 - - µs ADC sampling time when reading the temperature (1 °C accuracy) 1. Guaranteed by characterization. 2. Guaranteed by design. Table 70. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 138/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx 5.3.23 Electrical characteristics VBAT monitoring characteristics Table 71. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 5.3.24 Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 72. Embedded internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.24 V - 10 - - µs VDD = 3 V - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range TCoeff(2) Temperature coefficient - - 30 50 ppm/°C tSTART(2) Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 73. Internal reference voltage calibration values Symbol VREFIN_CAL 5.3.25 Parameter Memory address Raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B DAC electrical characteristics Table 74. DAC characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VSSA Ground 0 - 0 V DocID022152 Rev 8 Comments VREF+ ≤VDDA 139/202 Electrical characteristics STM32F405xx, STM32F407xx Table 74. DAC characteristics (continued) Symbol RLOAD(2) Parameter Resistive load with buffer ON Min Typ Max Unit 5 - - kΩ Comments Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA – 0.2 V DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - 0.5 - mV DAC_OUT Higher DAC_OUT voltage max(2) with buffer OFF - - VREF+ – 1LSB V - 170 240 RO(2) CLOAD(2) IVREF+(4) IDDA(4) DNL(4) INL(4) 140/202 DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode(3) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) µA It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V It gives the maximum output excursion of the DAC. With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Table 74. DAC characteristics (continued) Symbol Offset(4) Gain error(4) Parameter Min Typ Max Unit Comments - - ±10 mV Given for the DAC in 12-bit configuration Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.5 % Given for the DAC in 12-bit configuration - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Settling time (full scale: for a 10-bit input code transition (4) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value ±4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization. DocID022152 Rev 8 141/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 53. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.26 FSMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 54 through Figure 57 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. 142/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6  AIC 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) Parameter FSMC_NE low time Max 2THCLK–0.5 2 THCLK+1 Unit ns 0.5 3 ns 2THCLK–2 2THCLK+ 2 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 4.5 ns th(A_NOE) Address hold time after FSMC_NOE high 4 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns - THCLK ns tw(NOE) th(NE_NOE) tv(A_NE) th(Data_NE) tw(NADV) FSMC_NEx low to FSMC_NOE low Min FSMC_NOE low time FSMC_NADV low time 1. CL = 30 pF. 2. Guaranteed by characterization. DocID022152 Rev 8 143/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( W K1(B1:( WZ1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( )60&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )60&B'>@ W Y1$'9B1( )60&B1$'9 WZ1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max Unit 3THCLK 3THCLK+ 4 ns THCLK–0.5 THCLK+0.5 ns FSMC_NWE low time THCLK–1 THCLK+2 ns FSMC_NWE high to FSMC_NE high hold time THCLK–1 - ns - 0 ns THCLK– 2 - ns - 1.5 ns THCLK– 1 - ns FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK–1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK+0.5 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization. 144/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T H.%?./% &3-#?./% T W./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% TH",?./% &3-#?.",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &3-#? !$;= TSU$ATA?./% !DDRESS T V.!$6?.% TH$ATA?./% $ATA TH!$?.!$6 TW.!$6 &3-#?.!$6 AIB Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter Min Max Unit 3THCLK–1 3THCLK+1 ns 2THCLK–0.5 2THCLK+0.5 ns THCLK–1 THCLK+1 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 3 ns FSMC_NEx low to FSMC_NADV low 1 2 ns THCLK– 2 THCLK+1 ns THCLK - ns THCLK–1 - ns FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NADV low time FSMC_AD(adress) valid hold time after FSMC_NADV high) th(A_NOE) Address hold time after FSMC_NOE high th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. DocID022152 Rev 8 145/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( WK%/B1:( )60&B1%/>@ 1%/ W Y$B1( )60&B$'>@ W Y'DWDB1$'9 $GGUHVV W Y1$'9B1( WK'DWDB1:( 'DWD WK$'B1$'9 WZ1$'9 )60&B1$'9 DL% Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max Unit FSMC_NE low time 4THCLK–0.5 4THCLK+3 ns FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK -0.5 ns FSMC_NWE low tim e 2THCLK–0.5 2THCLK+3 ns THCLK - ns FSMC_NEx low to FSMC_A valid - 0 ns FSMC_NEx low to FSMC_NADV low 1 2 ns FSMC_NADV low time THCLK– 2 THCLK+ 1 ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) THCLK–2 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK–2 - ns FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FSMC_NWE high to FSMC_NE high hold time 1. CL = 30 pF. 146/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics 2. Guaranteed by characterization. Synchronous waveforms and timings Figure 58 through Figure 61 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). Figure 58. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 &3-#?!$;= !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIG DocID022152 Rev 8 147/202 Electrical characteristics STM32F405xx, STM32F407xx Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns 2 - ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) 0 - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 2. Guaranteed by characterization. 148/202 Min DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, $ATA TD#,+, !$6 &3-#?!$;= TD#,+, $ATA !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns - 0 ns FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKLNADVH) DocID022152 Rev 8 149/202 Electrical characteristics STM32F405xx, STM32F407xx Table 80. Synchronous multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit 0 - ns 4 - ns 0 - ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high tsu(NWAIT- FSMC_NWAIT valid before FSMC_CLK high CLKH) th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 2. Guaranteed by characterization. Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIF 150/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 2THCLK –0.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns 4 - ns 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 2. Guaranteed by characterization. DocID022152 Rev 8 151/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 61. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIG Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. 152/202 Min DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 62 through Figure 67 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Figure 62. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&(B )60&B1&(B WK1&([$, WY1&([$ )60&B$>@ WK1&([15(* WK1&([1,25' WK1&([1,2:5 WG15(*1&([ WG1,25'1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG1&(B12( )60&B12( WZ12( WVX'12( WK12(' )60&B'>@ DLE 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. DocID022152 Rev 8 153/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 63. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ WK1&(B15(* WK1&(B1,25' WK1&(B1,2:5 WG15(*1&(B WG1,25'1&(B )60&B15(* )60&B1,2:5 )60&B1,25' WG1&(B1:( WZ1:( WG1:(1&(B )60&B1:( )60&B12( 0(0[+,=  WG'1:( WY1:(' WK1:(' )60&B'>@ DL 154/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&(B WY1&(B$ WK1&(B$, )60&B1&(B +LJK )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* )60&B1:( WG1&(B12( WZ12( WG12(1&(B )60&B12( WVX'12( WK12(' )60&B'>@ DLE 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID022152 Rev 8 155/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* WG1&(B1:( WZ1:( )60&B1:( WG1:(1&(B )60&B12( WY1:(' )60&B'>@ DLE 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access )60&B1&(B )60&B1&(B WK1&(B$, WY1&([$ )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,2:5 WZ1,25' WG1,25'1&(B )60&B1,25' WVX'1,25' WG1,25'' )60&B'>@ DL% 156/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&(B )60&B1&(B WY1&([$ WK1&(B$, )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG1&(B1,2:5 WZ1,2:5 )60&B1,2:5 $77[+,=  WK1,2:5' WY1,2:5' )60&B'>@ DLF Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+0.5 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK +0.5 ns 8THCLK–1 8THCLK+1 ns 5THCLK+2.5 - ns 4.5 - ns 3 - ns 8THCLK–0.5 8THCLK+ 3 ns 5THCLK–1 - ns tw(NOE) td(NOE_NCEx) tsu (D-NOE) FSMC_NOE low width FSMC_NOE high to FSMC_NCEx high FSMC_D[15:0] valid data before FSMC_NOE high th(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns FSMC_NWE low to FSMC_D[15:0] valid - 0 ns tv(NWE-D) th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK –1 - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK –1 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. DocID022152 Rev 8 157/202 Electrical characteristics STM32F405xx, STM32F407xx Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK –1 - ns - 5THCLK– 1 ns 8THCLK– 2 - ns - 5THCLK+ 2.5 ns 5THCLK–1.5 - ns - 5THCLK+ 2 ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 1.5 - ns FSMC_NIORD low width 8THCLK–0.5 - ns tw(NIORD) tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. NAND controller waveforms and timings Figure 68 through Figure 71 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 158/202 DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. NAND controller waveforms for read access &3-#?.#%X !,%&3-#?! #,%&3-#?! &3-#?.7% TD!,% ./% TH./% !,% &3-#?./%.2% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 69. NAND controller waveforms for write access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(1:( WK1:($/( )60&B1:( )60&B12(15( WY1:(' WK1:(' )60&B'>@ AIC DocID022152 Rev 8 159/202 Electrical characteristics STM32F405xx, STM32F407xx Figure 70. NAND controller waveforms for common memory read access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(12( WK12($/( )60&B1:( WZ12( )60&B12( WVX'12( WK12(' )60&B'>@ DLF Figure 71. NAND controller waveforms for common memory write access )60&B1&([ $/()60&B$ &/()60&B$ WG$/(12( WZ1:( WK12($/( )60&B1:( )60&B12( WG'1:( WY1:(' WK1:(' )60&B'>@ DLF Table 85. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FSMC_NOE low width Max Unit 4THCLK– 0.5 4THCLK+ 3 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK– 2 - ns 1. CL = 30 pF. 160/202 Min DocID022152 Rev 8 STM32F405xx, STM32F407xx Electrical characteristics Table 86. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FSMC_NWE low width Min Max Unit 4THCLK–1 4THCLK+ 3 ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK –2 - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK–3 - ns - 3THCLK ns 3THCLK–2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 5.3.27 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 13, with the following configuration: • PCK polarity: falling • VSYNC and HSYNC polarity: high • Data format: 14 bits Figure 72. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WVX+6