STM32F411xC STM32F411xE
Arm® Cortex®-M4 32b MCU+FPU, 125 DMIPS, 512KB Flash,
128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces
Datasheet - production data
Features
• Dynamic Efficiency Line with BAM (Batch
Acquisition Mode)
– 1.7 V to 3.6 V power supply
– - 40°C to 85/105/125 °C temperature range
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit,
125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
• Memories
– Up to 512 Kbytes of Flash memory
– 128 Kbytes of SRAM
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Power consumption
– Run: 100 µA/MHz (peripheral off)
– Stop (Flash in Stop mode, fast wakeup
time): 42 µA Typ @ 25C; 65 µA max
@25 °C
– Stop (Flash in Deep power down mode,
slow wakeup time): down to 9 µA @ 25 °C;
28 µA max @25 °C
– Standby: 1.8 µA @25 °C / 1.7 V without
RTC; 11 µA @85 °C @1.7 V
– VBAT supply for RTC: 1 µA @25 °C
• 1×12-bit, 2.4 MSPS A/D converter: up to 16
channels
• General-purpose DMA: 16-stream DMA
controllers with FIFOs and burst support
• Up to 11 timers: up to six 16-bit, two 32-bit
timers up to 100 MHz, each with up to four
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input, two watchdog
timers (independent and window) and a
SysTick timer
December 2017
This is information on a product in full production.
)%*$
WLCSP49
(2.999x3.185 mm)
LQFP100
(14 × 14mm)
LQFP64
(10x10 mm)
UFQFPN48
(7 × 7 mm)
UFBGA100
(7 × 7 mm)
• Debug mode
– Serial wire debug (SWD) & JTAG
interfaces
– Cortex®-M4 Embedded Trace Macrocell™
• Up to 81 I/O ports with interrupt capability
– Up to 78 fast I/Os up to 100 MHz
– Up to 77 5 V-tolerant I/Os
• Up to 13 communication interfaces
– Up to 3 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (2 x 12.5 Mbit/s,
1 x 6.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), SPI2 and SPI3 with
muxed full-duplex I2S to achieve audio
class accuracy via internal audio PLL or
external clock
– SDIO interface (SD/MMC/eMMC)
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with on-chip
PHY
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
• All packages (WLCSP49, LQFP64/100,
®
UFQFPN48, UFBGA100) are ECOPACK 2
Table 1. Device summary
Reference
Part number
STM32F411xC
STM32F411CC, STM32F411RC,
STM32F411VC
STM32F411xE
STM32F411CE, STM32F411RE,
STM32F411VE
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Contents
STM32F411xC STM32F411xE
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
3
Compatibility with STM32F4 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 16
3.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16
3.3
Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 17
3.7
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16
3.15.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16.3
Regulator ON/OFF and internal power supply supervisor availability . . 25
3.17
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.18
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.20
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20.1
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Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Contents
3.20.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20.3
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20.4
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20.5
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.22
Universal synchronous/asynchronous receiver transmitters (USART) . . 29
3.23
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.24
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.25
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.26
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 31
3.27
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 31
3.28
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.29
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.30
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.31
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.32
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.2
VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.3
Operating conditions at power-up/power-down (regulator ON) . . . . . . . 65
6.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 65
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STM32F411xC STM32F411xE
6.3.5
Embedded reset and power control block characteristics . . . . . . . . . . . 66
6.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.11
PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 90
6.3.12
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.13
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.14
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 95
6.3.15
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.16
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.17
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.18
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.19
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.20
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.21
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.22
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.23
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.24
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 121
6.3.25
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.1
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.4
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.5
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.6.1
8
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 142
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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B.1
USB OTG Full Speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . 143
B.2
Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B.3
Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . 146
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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List of tables
STM32F411xC STM32F411xE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F411xC/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 25
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32F411xC/xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F411xC/xE
register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 63
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 65
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 65
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 70
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 71
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 72
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 73
Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 74
Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 74
Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 75
Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 75
Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 75
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 76
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
List of tables
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EMS characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EMI characteristics for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 116
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 116
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V . . . . . . . . . . . . . . . 123
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 126
UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch
quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
LQPF100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data134
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 138
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 142
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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7
List of figures
STM32F411xC STM32F411xE
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
8/149
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F411xC/xE block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 21
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 24
Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F411xC/xE WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F411xC/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32F411xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32F411xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32F411xC/xE UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical VBAT current consumption (LSE in low-drive mode and RTC ON). . . . . . . . . . . . . 76
Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 113
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 118
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 119
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level
DocID026289 Rev 7
STM32F411xC STM32F411xE
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
List of figures
chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch
quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch
quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 130
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
LQPF100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB controller configured as peripheral-only and used in Full-Speed mode . . . . . . . . . . 143
USB controller configured as host-only and used in Full-Speed mode. . . . . . . . . . . . . . . 143
USB controller configured in dual mode and used in Full-Speed mode . . . . . . . . . . . . . . 144
Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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9
Introduction
1
STM32F411xC STM32F411xE
Introduction
This datasheet provides the description of the STM32F411xC/xE microcontrollers.
The STM32F411xC/xE datasheet should be read in conjunction with RM0383 reference
manual which is available from the STMicroelectronics website www.st.com. It includes all
information concerning Flash memory programming.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214) available from www.st.com.
10/149
DocID026289 Rev 7
STM32F411xC STM32F411xE
2
Description
Description
The STM32F411XC/XE devices are based on the high-performance Arm® Cortex® -M4 32bit RISC core operating at a frequency of up to 100 MHz. The Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F411xC/xE belongs to the STM32 Dynamic Efficiency™ product line (with
products combining power efficiency, performance and integration) while adding a new
innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power
consumption during data batching.
The STM32F411xC/xE incorporate high-speed embedded memories (up to 512 Kbytes of
Flash memory, 128 Kbytes of SRAM), and an extensive range of enhanced I/Os and
peripherals connected to two APB buses, two AHB bus and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers
including one PWM timer for motor control, two general-purpose 32-bit timers. They also
feature standard and advanced communication interfaces.
•
Up to three I2Cs
•
Five SPIs
•
Five I2Ss out of which two are full duplex. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
•
Three USARTs
•
SDIO interface
•
USB 2.0 OTG full speed interface
The STM32F411xC/xE operate in the - 40 to + 125 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design
of low-power applications.
These features make the STM32F411xC/xE microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile phone sensor hub
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56
Description
STM32F411xC STM32F411xE
Table 2. STM32F411xC/xE features and peripheral counts
Peripherals
Flash memory in Kbytes
SRAM in Kbytes
Timers
STM32F411xC
STM32F411xE
256
512
System
128
Generalpurpose
7
Advancedcontrol
1
SPI/ I2S
Communication
interfaces
5/5 (2 full duplex)
I2C
3
USART
3
SDIO
1
USB OTG FS
1
GPIOs
12-bit ADC
Number of channels
36
50
81
10
16
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81
10
16
100 MHz
Operating voltage
Package
50
1
Maximum CPU frequency
Operating temperatures
36
1.7 to 3.6 V
Ambient temperatures: - 40 to +85 °C / - 40 to + 105 °C/ - 40 to + 125 °C
Junction temperature: – 40 to + 130 °C
WLCSP49
LQFP64
UFQFPN48
UFBGA100 WLCSP49
LQFP100 UFQFPN48
DocID026289 Rev 7
LQFP64
UFBGA100
LQFP100
STM32F411xC STM32F411xE
Compatibility with STM32F4 Series
The STM32F411xC/xE are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F411xC/xE can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
670)[[
670)[[
670)[[
670)[[
670)[[
670)[[
670)[[
670)670)OLQH
670)670)OLQH
670)670)OLQH
670) 670) OLQH
3% QRW DYDLODEOHDQ\PRUH
5HSODFHG E\ 9 &$3B
3(
3(
3(
3(
3(
3(
3%
9&$3B
966
9''
3'
3'
3'
3'
3%
3%
3%
3%
3(
3(
3(
3(
3(
3(
3%
3%
9&$3B
9''
2.1
Description
966 9''
3'
3'
3'
3'
3%
3%
3%
3%
966 9''
06Y9
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13/149
56
Description
STM32F411xC STM32F411xE
Figure 2. Compatible board design for LQFP64 package
670)[[
670)[[
670)[[
670)[[
670)[[
670)[[
670)[[
9''
9&$3B
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
3%
3%
3%
3%
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DocID026289 Rev 7
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STM32F411xC STM32F411xE
Description
Figure 3. STM32F411xC/xE block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 100 MHz.
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Functional overview
STM32F411xC STM32F411xE
3
Functional overview
3.1
Arm® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices. The processor supports a set of DSP
instructions which allow efficient signal processing and complex algorithm execution. Its
single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F411xC/xE devices are compatible with all Arm tools and software.
Figure 3 shows the general block diagram of the STM32F411xC/xE.
Note:
Cortex®-M4 with FPU is binary compatible with Cortex®-M3.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 105 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the -bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3
Batch Acquisition mode (BAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the I2S
directly to RAM (flash and ART™ stopped) with the DMA using BAM followed by some very
short processing from flash allows to drastically reduce the power consumption of the
application. A dedicated application note (AN4515) describes how to implement the BAM to
allow the best power efficiency.
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3.4
Functional overview
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5
Embedded Flash memory
The devices embed up to 512 Kbytes of Flash memory available for storing programs and
data.
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.18: Low-power modes). Two modes are available: Flash in Stop
mode or in DeepSleep mode (trade off between power saving and startup time, see
Table 34: Low-power mode wakeup timings(1)). Before disabling the Flash memory, the
code must be executed from the internal RAM.
One-time programmable bytes
A one-time programmable area is available with 16 OTP blocks of 32 bytes. Each block can
be individually locked.
(Additional information can be found in the product reference manual.)
3.6
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.7
Embedded SRAM
All devices embed:
•
128 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed
with 0 wait states
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Functional overview
3.8
STM32F411xC STM32F411xE
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 4. Multi-AHB matrix
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3.9
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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STM32F411xC STM32F411xE
Functional overview
The DMA can be used with the main peripherals:
3.10
•
SPI and I2S
•
I2C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
SD/SDIO/MMC/eMMC host interface
•
ADC
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.11
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected
to the 16 external interrupt lines.
3.12
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
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Functional overview
STM32F411xC STM32F411xE
buses is 100 MHz while the maximum frequency of the high-speed APB domains is
100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.13
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The bootloader is located in system memory. It is used to reprogram the Flash memory by
using USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12) through
DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),
SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).
For more detailed information on the bootloader, refer to Application Note: AN2606, STM32
microcontroller system memory boot mode.
3.14
Power supply schemes
•
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 17: Power supply scheme for more details.
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Functional overview
3.15
Power supply supervisor
3.15.1
Internal reset ON
This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
The internal power supply supervisor is enabled by holding PDR_ON high.
The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The devices remain in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The devices also feature an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.15.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should set the device in reset
mode when VDD is below 1.7 V. NRST should be connected to this external power supply
supervisor. Refer to Figure 5: Power supply supervisor interconnection with internal reset
OFF.
Figure 5. Power supply supervisor interconnection with internal reset OFF(1)
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1. The PRD_ON pin is only available on the WLCSP49 and UFBGA100 packages.
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A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
3.16
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•
The brownout reset (BOR) circuitry must be disabled.
•
The embedded programmable voltage detector (PVD) is disabled.
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
Voltage regulator
The regulator has four operating modes:
•
•
3.16.1
Regulator ON
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•
LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
•
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the LQFP100 and
UFBGA100 packages.
All packages have the regulator ON feature.
3.16.2
Regulator OFF
The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG
pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode
allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 µF VCAP ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 17: Power supply scheme.
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Functional overview
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
Figure 6. Regulator OFF
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