STM32F412xE STM32F412xG
Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash,
256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
Datasheet - production data
Features
)%*$
• Dynamic Efficiency Line with BAM (Batch
Acquisition Mode)
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit,
125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
• Memories
– Up to 1 Mbyte of Flash memory
– 256 Kbyte of SRAM
– Flexible external static memory controller
with up to 16-bit data bus: SRAM, PSRAM,
NOR Flash memory
– Dual mode Quad-SPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Power consumption
– Run: 112 µA/MHz (peripheral off)
– Stop (Flash in Stop mode, fast wakeup
time): 50 µA Typ @ 25 °C; 75 µA max
@25 °C
– Stop (Flash in Deep power down mode,
slow wakeup time): down to 18 µA @
25 °C; 40 µA max @25 °C
– Standby: 2.4 µA @25 °C / 1.7 V without
RTC; 12 µA @85 °C @1.7 V
– VBAT supply for RTC: 1 µA @25 °C
• 1×12-bit, 2.4 MSPS ADC: up to 16 channels
LQFP64 (10x10mm)
WLCSP64
UFQFPN48
(3.623x3.651mm) LQFP100 (14x14mm) (7x7 mm)
LQFP144 (20x20mm)
UFBGA100
(7x7mm)
UFBGA144
(10x10mm)
• Up to 17 timers: up to twelve 16-bit timers, two
32-bit timers up to 100 MHz each with up to
four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input, two
watchdog timers (independent and window),
one SysTick timer
• Debug mode
– Serial wire debug (SWD) & JTAG
– Cortex®-M4 Embedded Trace Macrocell™
• Up to 114 I/O ports with interrupt capability
– Up to 109 fast I/Os up to 100 MHz
– Up to 114 five V-tolerant I/Os
• Up to 17 communication interfaces
– Up to 4x I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs (2 x 12.5 Mbit/s,
2 x 6.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
full-duplex I2S interfaces
– SDIO interface (SD/MMC/eMMC)
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with PHY
– 2x CAN (2.0B Active)
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
®
• All packages are ECOPACK 2
Table 1. Device summary
Reference
Part number
• 2x digital filters for sigma delta modulator,
4x PDM interfaces, stereo microphone support
STM32F412xE
STM32F412CE, STM32F412RE, STM32F412VE,
STM32F412ZE
• General-purpose DMA: 16-stream DMA
STM32F412xG
STM32F412CG, STM32F412RG, STM32F412VG,
STM32F412ZG
December 2017
This is information on a product in full production.
DocID028087 Rev 7
1/201
www.st.com
Contents
STM32F412xE/G
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 19
3.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
3.3
Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
3.8
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12
Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.14
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19
2/201
Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.18.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.20
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.21
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.22
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
3.23.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.3
Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.4
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.5
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25
Universal synchronous/asynchronous receiver transmitters (USART) . . 37
3.26
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38
3.30
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.31
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32
Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.33
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.34
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1
WLSCP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2
UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3
LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4
LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5
LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6
UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7
UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.8
Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Contents
STM32F412xE/G
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1
4/201
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.2
VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.3
Operating conditions at power-up/power-down (regulator ON) . . . . . . . 85
6.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 86
6.3.5
Embedded reset and power control block characteristics . . . . . . . . . . . 86
6.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.11
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 115
6.3.12
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.13
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.14
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 121
6.3.15
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.16
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.17
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.18
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.19
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.20
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.21
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.22
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.23
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.24
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Contents
6.3.25
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.26
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 164
6.3.27
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.1
WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.5
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.6
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.7
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.8.1
8
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 192
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
B.1
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 193
B.2
Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
B.3
Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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List of tables
STM32F412xE/G
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
6/201
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F412xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F412xE/G pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STM32F412xE/G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STM32F412xE/G register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 84
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 85
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 86
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 90
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 91
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 92
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 93
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 94
Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 95
Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 96
Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 97
Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 97
Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 97
Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 98
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 98
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DocID028087 Rev 7
STM32F412xE/G
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
List of tables
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 130
FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 153
Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 155
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 157
DocID028087 Rev 7
7/201
8
List of tables
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
8/201
STM32F412xE/G
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 157
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 166
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
WLCSP64 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 169
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 185
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 188
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DocID028087 Rev 7
STM32F412xE/G
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F412xE/G block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 25
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
STM32F412xE/G WLCSP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STM32F412xE/G UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32F412xE/G LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32F412xE/G LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32F412xE/G LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F412xE/G UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F412xE/G UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
DocID028087 Rev 7
9/201
11
List of figures
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
10/201
STM32F412xE/G
USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 140
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 146
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 147
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 151
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 153
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 156
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
WLCSP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 173
LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 177
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 180
LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 193
USB peripheral-only Full speed mode with direct connection
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 194
USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 194
USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 195
Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DocID028087 Rev 7
STM32F412xE/G
Figure 87.
List of figures
Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DocID028087 Rev 7
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11
Introduction
1
STM32F412xE/G
Introduction
This datasheet provides the description of the STM32F412xE/G microcontrollers.
For information on the Cortex®-M4 core, refer to the Cortex®-M4 programming manual
(PM0214) available from www.st.com.
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2
Description
Description
STM32F412XE/G devices are based on the high-performance Arm® Cortex® -M4 32-bit
RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
STM32F412XE/G devices belong to the STM32 Dynamic Efficiency™ product line (with
products combining power efficiency, performance and integration) while adding a new
innovative feature called Batch Acquisition Mode (BAM) allowing even more power
consumption saving during data batching.
STM32F412XE/G devices incorporate high-speed embedded memories (up to 1 Mbyte of
Flash memory, 256 Kbytes of SRAM), and an extensive range of enhanced I/Os and
peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus
matrix.
All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers,
two PWM timers for motor control and two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces:
•
Up to four I2Cs, including one I2C supporting Fast-Mode Plus
•
Five SPIs
•
Five I2Ss of which two are full duplex. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL, or via an external clock
to allow synchronization.
•
Four USARTs
•
An SDIO/MMC interface
•
A USB 2.0 OTG full-speed interface
•
Two CANs.
In addition, STM32F412xE/G devices embed advanced peripherals:
•
A flexible static memory controller interface (FSMC)
•
A Quad-SPI memory interface
•
A digital filter for sigma modulator (DFSDM), two filters, up to four inputs, and support
of microphone MEMs.
STM32F412xE/G devices are offered in 7 packages ranging from 48 to 144 pins. The set of
available peripherals depends on the selected package.
The STM32F412xE/G operates in the -40 to +125 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving modes allows the design
of low-power applications.
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42
Description
STM32F412xE/G
These features make the STM32F412xE/G microcontrollers suitable for a wide range of
applications:
14/201
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile phone sensor hub
•
Wearable devices
•
Connected objects
•
Wifi modules
DocID028087 Rev 7
STM32F412xE/G
Description
Table 2. STM32F412xE/G features and peripheral counts
Peripherals
STM32F412xE
STM32F412xG
512
1024
Flash memory (Kbyte)
SRAM
(Kbyte)
System
256
FSMC memory
controller(1)
-
Quad-SPI memory
interface
1
-
-
1
-
Generalpurpose
10
Advancedcontrol
2
Basic
2
Random number generator
1
Timers
SPI/ I2S
3
2CFMP
USART
Comm.
interfaces
SDIO/MMC
1
4
(2)
4(2)
4
1
Yes
1
No
CAN
LCD parallel interface
Data bus size
GPIOs
12-bit ADC
Number of channels
2
2
2
2
3
4
3
4
-
8
36
50
16
81
114
-
8
36
50
16
81
114
1
10
16
10
16
100 MHz
Operating voltage
Package
1
Yes
1
No
2
Maximum CPU frequency
Operating temperatures
4
1
USB/OTG FS
Dual power rail
Number of digital Filters for
Sigma-delta modulator
Number of channels
1
5/5 (2 full duplex)
I2C
I
1
1.7 to 3.6 V
Ambient temperatures: -40 to +85 °C / -40 to +105 °C/ -40 to +125 °C
Junction temperature: -40 to +130 °C
UFQ
LQFP64
FPN48 WLCSP64
UFBGA
100
LQFP100
UFBGA
LQFP64
UFQ
144
WLCSP
FPN48
LQFP144
64
UFBGA
UFBGA
100
144
LQFP100 LQFP144
1. The FSMC can also be used to interface most graphic LCD controllers.
2. Limited application for the USART3 since RX is not available for the UFQFPN48.
DocID028087 Rev 7
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42
Description
2.1
STM32F412xE/G
Compatibility with STM32F4 series
The STM32F412xE/G are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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DocID028087 Rev 7
STM32F412xE/G
Description
Figure 2. Compatible board design for LQFP64 package
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DocID028087 Rev 7
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42
Description
STM32F412xE/G
Figure 4. STM32F412xE/G block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
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STM32F412xE/G
Functional overview
3
Functional overview
3.1
Arm® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F412xE/G devices are compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F412xE/G.
Note:
Cortex®-M4 with FPU is binary compatible with Cortex®-M3.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3
Batch Acquisition mode (BAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (flash and ART™ stopped) with the DMA using BAM followed by
some very short processing from flash allows to drastically reduce the power consumption
of the application. A dedicated application note (AN4515) describes how to implement the
STM32F412xE/G BAM to allow the best power efficiency.
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Functional overview
3.4
STM32F412xE/G
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5
Embedded Flash memory
The devices embed up to 1 Mbyte of Flash memory available for storing programs and data.
The Flash user area can be protected against reading by an entrusted code (Read
Protection, RDP) with different protection levels.
The flash user sectors can also be individually protected against write operation.
Furthermore the proprietary readout protection (PCROP) can also individually protect the
flash user sectors against D-bus read accesses.
(Additional information can be found in the product reference manual).
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.21: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6
One-time programmable bytes
A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can
be individually locked
(Additional information can be found in the product reference manual)
3.7
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
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3.8
Functional overview
Embedded SRAM
All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states
3.9
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
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3.10
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview
STM32F412xE/G
The DMA can be used with the main peripherals:
3.11
•
SPI and I2S
•
I2C and I2CFMP
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
SD/SDIO/MMC/eMMC host interface
•
Quad-SPI
•
ADC
•
Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter.
Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
•
8-,16-bit data bus width
•
Write FIFO
•
Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.12
Quad-SPI memory interface (QUAD-SPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
22/201
DocID028087 Rev 7
STM32F412xE/G
3.13
Functional overview
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.14
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.15
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
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Functional overview
3.16
STM32F412xE/G
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
Boot from user Flash memory
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
Table 3. Embedded bootloader interfaces
Package
USART1 USART2 USART3 I2C1
PA9/
PD6/
PB11/
PB6/
PA10
PD5
PB10
PB7
SPI3
I2C2
PF0/
PF1
I2C3
PA8/
PB4
I2C
FMP1
PB14/
PB15
SPI1
PA4/
PA5/
PA6/
PA7
PA15/
PC10/
PC11/
PC12
SPI4
PE11/ CAN2 USB
PE12/ PB5/ PA11
PE13/ PB13 /P12
PE14
UFQFPN48
Y
-
-
Y
-
Y
Y
Y
-
-
Y
Y
WLCSP64
Y
-
-
Y
-
Y
Y
Y
Y
-
Y
Y
LQFP64
Y
-
-
Y
-
Y
Y
Y
Y
-
Y
Y
LQFP100
Y
Y
-
Y
-
Y
Y
Y
Y
Y
Y
Y
LQFP144
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
UFBGA100
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
UFBGA144
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.17
Note:
24/201
Power supply schemes
•
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.18.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
DocID028087 Rev 7
STM32F412xE/G
Functional overview
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
The following conditions VDDUSB must be respected:
–
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
VDDUSB rising and falling time rate specifications must be respected.
–
In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB is used, the associated GPIOs powered by VDDUSB are operating
between VDDUSB_MIN and VDDUSB_MAX.
– If USB is not used, the associated GPIOs powered by VDDUSB are operating
between VDD_MIN and VDD_MAX.
Figure 6. VDDUSB connected to an external independent power supply
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Functional overview
STM32F412xE/G
3.18
Power supply supervisor
3.18.1
Internal reset ON
This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.18.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should set the device in reset
mode when VDD is below 1.7 V. NRST should be connected to this external power supply
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
26/201
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Functional overview
Figure 7. Power supply supervisor interconnection with internal reset OFF(1)
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1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
3.19
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•
The brownout reset (BOR) circuitry must be disabled.
•
The embedded programmable voltage detector (PVD) is disabled.
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
Voltage regulator
The regulator has three operating modes:
3.19.1
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. The WLCSP64 is available in two versions, one with the regulator
internally enabled and one with the regulator internally disabled. On all other packages, the
regulator is always enabled.
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Functional overview
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There are three power modes configured by software when the regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•
LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
•
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the 100 pins and 144 pins
packages.
All packages have the regulator ON feature.
3.19.2
Regulator OFF
The regulator is disabled by holding BYPASS_REG pin high.
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The WLCSP64 is available in two versions, one with a fixed enabled
regulator and one with a fixed disabled regulator (see Table 4: Regulator ON/OFF and
internal power supply supervisor availability and Section 8: Part numbering). The regulator
OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
28/201
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
DocID028087 Rev 7
STM32F412xE/G
Functional overview
Figure 8. Regulator OFF
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1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
Min
Max
FSMC_NE low time
3 THCLK - 1
3 THCLK +0.5
FSMC_NEx low to FSMC_NWE low
THCLK + 0.5
THCLK + 0.5
FSMC_NWE low time
THCLK – 1.5
THCLK+ 1
THCLK - 1
-
-
0.5
THCLK - 0.5
-
-
1
THCLK - 1
-
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
th(A_NWE)
Address hold time after FSMC_NWE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NE)
Data to FSMC_NEx low to Data valid
-
THCLK + 2
th(Data_NWE)
Data hold time after FSMC_NWE high
THCLK + 0.5
-
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
1
FSMC_NADV low time
-
THCLK+ 0.5
tw(NADV)
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166
Electrical characteristics
STM32F412xE/G
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2)
Symbol
Parameter
Min
Max
8THCLK - 1
8THCLK + 0.5
6THCLK + 0.5
6THCLK + 1
FSMC_NE low time
tw(NE)
tw(NWE)
FSMC_NWE low time
tsu(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx high 6THCLK + 0.5
-
th(NE_NWAIT)
FSMC_NEx hold time after FSMC_NWAIT
invalid
-
4THCLK + 1
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms
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Electrical characteristics
Table 88. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
tw(NE)
tv(NOE_NE)
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
3THCLK – 1
3THCLK + 0.5
2THCLK
2THCLK + 1
THCLK – 1.5
THCLK
FSMC_NOE high to FSMC_NE high hold
time
0
-
FSMC_NEx low to FSMC_A valid
-
0.5
FSMC_NEx low to FSMC_NADV low
0
1
THCLK – 0.5
THCLK + 0.5
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NADV low time
th(AD_NADV)
FSMC_AD(address) valid hold time after
FSMC_NADV high)
0
-
th(A_NOE)
Address hold time after FSMC_NOE high
THCLK – 0.5
-
th(BL_NOE)
FSMC_BL time after FSMC_NOE high
0
-
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0.5
tsu(Data_NE)
Data to FSMC_NEx high setup time
THCLK - 2
-
tsu(Data_NOE)
Data to FSMC_NOE high setup time
THCLK - 2
-
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 89. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)
Symbol
Min
Max
8THCLK - 1
8THCLK + 0.5
5THCLK
5THCLK + 0.5
tsu(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx
high
5THCLK - 1
-
th(NE_NWAIT)
FSMC_NEx hold time after
FSMC_NWAIT invalid
4THCLK + 1
-
tw(NE)
tw(NOE)
Parameter
FSMC_NE low time
FSMC_NWE low time
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
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STM32F412xE/G
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms
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STM32F412xE/G
Electrical characteristics
Table 90. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
Symbol
Min
Max
4THCLK - 1
4THCLK+0.5
THCLK
THCLK + 1
2THCLK - 1
2THCLK + 0.5
THCLK - 1.5
-
FSMC_NEx low to FSMC_A valid
-
2
FSMC_NEx low to FSMC_NADV low
0
1
THCLK – 0.5
THCLK+ 0.5
THCLK
-
THCLK- 1.5
-
THCLK
-
FSMC_NEx low to FSMC_BL valid
-
1.5
tv(Data_NADV)
FSMC_NADV high to Data valid
-
THCLK + 2
th(Data_NWE)
Data hold time after FSMC_NWE high
THCLK + 0.5
-
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
th(AD_NADV)
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NADV low time
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
th(A_NWE)
Address hold time after FSMC_NWE high
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(BL_NE)
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 91. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
Symbol
Min
Max
FSMC_NE low time
9THCLK - 1
9THCLK + 0.5
FSMC_NWE low time
7THCLK - 1
7THCLK + 0.5
tsu(NWAIT_NE)
FSMC_NWAIT valid before FSMC_NEx high
6THCLK -1
-
th(NE_NWAIT)
FSMC_NEx hold time after FSMC_NWAIT
invalid
4THCLK + 1
-
tw(NE)
tw(NWE)
Parameter
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Synchronous waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms and Table 92 through
Table 95 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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STM32F412xE/G
In all timing tables, the THCLK is the HCLK clock period (with maximum
FSMC_CLK = 90 MHz).
Figure 54. Synchronous multiplexed NOR/PSRAM read timings
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Table 92. Synchronous multiplexed NOR/PSRAM read timings(1)(2)
Symbol
tw(CLK)
Parameter
FSMC_CLK period
Min
Max
2THCLK - 0.5
-
-
1
THCLK + 0.5
-
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKH_NExH)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0
-
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid
(x=16…25)
THCLK
-
-
1.5
THCLK
-
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
td(CLKH-NOEH)
FSMC_CLK high to FSMC_NOE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
1
-
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK
high
2
-
tsu(NWAIT-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
2
-
th(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high
2
-
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
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166
Electrical characteristics
STM32F412xE/G
Figure 55. Synchronous multiplexed PSRAM write timings
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DocID028087 Rev 7
STM32F412xE/G
Electrical characteristics
Table 93. Synchronous multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
tw(CLK)
FSMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK - 0.5
-
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x= 0...2)
-
1
td(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
THCLK + 0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
0
-
-
2
THCLK
-
-
1.5
THCLK + 0.5
-
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
t(CLKH-NWEH)
FSMC_CLK high to FSMC_NWE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FSMC_A/D[15:0] valid data after FSMC_CLK low
-
4
td(CLKL-NBLL)
FSMC_CLK low to FSMC_NBL low
-
3
td(CLKH-NBLH)
FSMC_CLK high to FSMC_NBL high
THCLK
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
2
-
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
-
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
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166
Electrical characteristics
STM32F412xE/G
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings
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Table 94. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Min
Max
2THCLK – 0.5
-
-
1
THCLK +0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
0
-
-
2
THCLK
-
-
1.5
THCLK
-
tw(CLK)
t(CLKL-NExL)
td(CLKH-NExH)
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Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
td(CLKH-NOEH)
FSMC_CLK high to FSMC_NOE high
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK
high
1
-
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
2
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
2
-
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
-
DocID028087 Rev 7
Unit
ns
STM32F412xE/G
Electrical characteristics
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 57. Synchronous non-multiplexed PSRAM write timings
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166
Electrical characteristics
STM32F412xE/G
Table 95. Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol
Min
Max
2THCLK – 0.5
-
-
1
THCLK + 0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
0
-
-
2
THCLK
-
-
1.5
THCLK + 0.5
-
tw(CLK)
td(CLKL-NExL)
Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
-
4
td(CLKL-NBLL)
FSMC_CLK low to FSMC_NBL low
-
3
THCLK
-
2
-
2
-
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
tsu(NWAITCLKH)
FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
Unit
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
6.3.26
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 96 for the SDIO are derived from
tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
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Electrical characteristics
Figure 58. SDIO high-speed mode
Figure 59. SD default mode
Table 96. Dynamic characteristics: SD / MMC characteristics(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fpp =50MHz
9.5
10.5
-
tW(CKH)
Clock high time
fpp =50MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
Input setup time HS
fpp =50MHz
4
-
-
tIH
Input hold time HS
fpp =50MHz
2.5
-
-
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
Output valid time HS
fpp =50MHz
-
13
13.5
tOH
Output hold time HS
fpp =50MHz
11
-
-
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Electrical characteristics
STM32F412xE/G
Table 96. Dynamic characteristics: SD / MMC characteristics(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
fpp =25MHz
2.5
-
-
tIHD
Input hold time SD
fpp =25MHz
2.5
-
-
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
fpp =25 MHz
-
1.5
2
tOHD
Output hold default time SD
fpp =25 MHz
0.5
-
-
ns
1. Guaranteed by characterization results, not tested in production.
2. VDD = 2.7 to 3.6 V.
Table 97. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fpp =50MHz
9.5
10.5
-
tW(CKH)
Clock high time
fpp =50MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
Input setup time HS
fpp =50MHz
3.5
-
-
tIH
Input hold time HS
fpp =50MHz
4
-
-
ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV
Output valid time HS
fpp =50MHz
-
13.5
15
tOH
Output hold time HS
fpp =50MHz
12
-
-
ns
1. Guaranteed by characterization results, not tested in production.
2. CLOAD = 20 pF.
6.3.27
RTC characteristics
Table 98. RTC characteristics
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Symbol
Parameter
-
fPCLK1/RTCCLK frequency ratio
Conditions
Any read/write operation
from/to an RTC register
DocID028087 Rev 7
Min
Max
4
-
STM32F412xE/G
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
WLCSP64 package information
Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package outline
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196
Package information
STM32F412xE/G
Table 99. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.585
0.0207
0.0219
0.0230
A1
-
0.170
-
-
0.0067
-
A2
-
0.380
-
-
0.0150
-
-
0.025
-
-
0.0010
-
b(3)
0.220
0.250
0.280
0.0087
0.0098
0.0110
D
3.588
3.623
3.658
0.1413
0.1426
0.1440
E
3.616
3.651
3.686
0.1424
0.1437
0.1451
e
-
0.400
-
-
0.0157
-
e1
-
2.800
-
-
0.1102
-
e2
-
2.800
-
-
0.1102
-
F
-
0.4115
-
-
0.0162
-
G
-
0.4255
-
-
0.0168
-
aaa
-
-
0.100
-
-
0.0039
bbb
-
-
0.100
-
-
0.0039
ccc
-
-
0.100
-
-
0.0039
ddd
-
-
0.050
-
-
0.0020
eee
-
-
0.050
-
-
0.0020
A3
(2)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
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Package information
Table 100. WLCSP64 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
0.4 mm
Dpad
0.225 mm
Dsm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.250 mm
Stencil thickness
0.100 mm
Device marking for WLCSP64
The following figure gives an example of topside marking and pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 62. WLCSP64 marking example (package top view)
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