STM32F412ZEJ3

STM32F412xE STM32F412xG Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces Datasheet - production data Features UFBGA • Dynamic Efficiency Line with BAM (Batch Acquisition Mode) ® ® • Core: Arm 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – 256 Kbyte of SRAM – Flexible external static memory controller with up to 16-bit data bus: SRAM, PSRAM, NOR Flash memory – Dual mode Quad-SPI interface • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Power consumption – Run: 112 µA/MHz (peripheral off) – Stop (Flash in Stop mode, fast wakeup time): 50 µA Typ @ 25 °C; 75 µA max @25 °C – Stop (Flash in Deep power down mode, slow wakeup time): down to 18 µA @ 25 °C; 40 µA max @25 °C – Standby: 2.4 µA @25 °C / 1.7 V without RTC; 12 µA @85 °C @1.7 V – VBAT supply for RTC: 1 µA @25 °C • 1×12-bit, 2.4 MSPS ADC: up to 16 channels LQFP64 (10x10mm) WLCSP64 UFQFPN48 (3.623x3.651mm) LQFP100 (14x14mm) (7x7 mm) LQFP144 (20x20mm) UFBGA100 (7x7mm) UFBGA144 (10x10mm) • Up to 17 timers: up to twelve 16-bit timers, two 32-bit timers up to 100 MHz each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window), one SysTick timer • Debug mode – Serial wire debug (SWD) & JTAG – Cortex®-M4 Embedded Trace Macrocell™ • Up to 114 I/O ports with interrupt capability – Up to 109 fast I/Os up to 100 MHz – Up to 114 five V-tolerant I/Os • Up to 17 communication interfaces – Up to 4x I2C interfaces (SMBus/PMBus) – Up to 4 USARTs (2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) – Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol), out of which 2 muxed full-duplex I2S interfaces – SDIO interface (SD/MMC/eMMC) – Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY – 2x CAN (2.0B Active) • True random number generator • CRC calculation unit • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar ® • All packages are ECOPACK 2 Table 1. Device summary Reference Part number • 2x digital filters for sigma delta modulator, 4x PDM interfaces, stereo microphone support STM32F412xE STM32F412CE, STM32F412RE, STM32F412VE, STM32F412ZE • General-purpose DMA: 16-stream DMA STM32F412xG STM32F412CG, STM32F412RG, STM32F412VG, STM32F412ZG March 2023 This is information on a product in full production. DS11139 Rev 8 1/205 www.st.com Contents STM32F412xE/G Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 18 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18 3.3 Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 19 3.8 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.19 2/205 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30 3.20 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 30 3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DS11139 Rev 8 STM32F412xE/G Contents 3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 36 3.26 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.27 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 39 3.31 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 39 3.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.35 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1 WLSCP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5 LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.7 UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DS11139 Rev 8 3/205 5 Contents STM32F412xE/G 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 4/205 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 84 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 85 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 85 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 114 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 120 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.24 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DS11139 Rev 8 STM32F412xE/G 7 Contents 6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 163 6.3.27 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.1 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.8 Package term definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.9.1 8 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Appendix A Recommendations when using the internal reset OFF . . . . . . . . 195 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 9 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 196 B.2 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 B.3 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DS11139 Rev 8 5/205 5 List of tables STM32F412xE/G List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/205 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F412xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 30 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F412xE/G pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32F412xE/G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32F412xE/G register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 83 VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 84 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 85 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 89 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 90 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 91 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 92 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 93 Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 94 Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 95 Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 96 Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 96 Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 96 Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 97 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 97 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DS11139 Rev 8 STM32F412xE/G Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. List of tables LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 129 FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 142 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 142 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 152 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 154 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DS11139 Rev 8 7/205 8 List of tables Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. 8/205 STM32F412xE/G Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 156 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 161 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 165 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 WLCSP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 WLCSP64 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 168 UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 187 UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 UFBGA144 - Example of PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . . . 191 Term definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DS11139 Rev 8 STM32F412xE/G List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F412xE/G block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 24 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 26 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F412xE/G WLCSP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F412xE/G UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F412xE/G LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F412xE/G LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F412xE/G LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F412xE/G UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F412xE/G UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator “low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator “high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 DS11139 Rev 8 9/205 10 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. 10/205 STM32F412xE/G USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 139 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 145 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 146 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 150 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 152 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 153 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 155 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 161 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 WLCSP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 WLCSP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 WLCSP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 UFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 UFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 UFBGA144 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 UFBGA144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 196 USB peripheral-only Full speed mode with direct connection for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 197 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 197 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 198 Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DS11139 Rev 8 STM32F412xE/G 1 Introduction Introduction This datasheet provides the description of the STM32F412xE/G microcontrollers. This document should be read in conjunction with the reference manual RM0402 “STM32F412 advanced Arm®-based 32-bit MCUs. The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical reference manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS11139 Rev 8 11/205 41 Description 2 STM32F412xE/G Description STM32F412XE/G devices are based on the high-performance Arm® Cortex® -M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. STM32F412XE/G devices belong to the STM32 Dynamic Efficiency™ product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing even more power consumption saving during data batching. STM32F412XE/G devices incorporate high-speed embedded memories (up to 1 Mbyte of Flash memory, 256 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers, two PWM timers for motor control and two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces: - Up to four I2Cs, including one I2C supporting Fast-Mode Plus - Five SPIs - Five I2Ss of which two are full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL, or via an external clock to allow synchronization. - Four USARTs - An SDIO/MMC interface - A USB 2.0 OTG full-speed interface - Two CANs. In addition, STM32F412xE/G devices embed advanced peripherals: - A flexible static memory controller interface (FSMC) - A Quad-SPI memory interface - A digital filter for sigma modulator (DFSDM), two filters, up to four inputs, and support of microphone MEMs. STM32F412xE/G devices are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals depends on the selected package. The STM32F412xE/G operates in the -40 to +125 °C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. 12/205 DS11139 Rev 8 STM32F412xE/G Description These features make the STM32F412xE/G microcontrollers suitable for a wide range of applications: - Motor drive and application control - Medical equipment - Industrial applications: PLC, inverters, circuit breakers - Printers, and scanners - Alarm systems, video intercom, and HVAC - Home audio appliances - Mobile phone sensor hub - Wearable devices - Connected objects - Wifi modules DS11139 Rev 8 13/205 41 Description STM32F412xE/G Table 2. STM32F412xE/G features and peripheral counts Peripherals STM32F412xE STM32F412xG 512 1024 Flash memory (Kbyte) SRAM (Kbyte) System 256 FSMC memory controller(1) - Quad-SPI memory interface 1 - - 1 - Generalpurpose 10 Advancedcontrol 2 Basic 2 Random number generator 1 Timers SPI/ I2S 3 2CFMP USART Comm. interfaces SDIO/MMC 1 4 (2) 4(2) 4 1 Yes 1 No CAN LCD parallel interface Data bus size GPIOs 12-bit ADC Number of channels 2 2 2 2 3 4 3 4 - 8 36 50 16 81 114 10 16 8 36 50 10 16 81 114 16 100 MHz 1.7 to 3.6 V Ambient temperatures: -40 to +85 °C / -40 to +105 °C/ -40 to +125 °C Junction temperature: -40 to +130 °C UFQ LQFP64 FPN48 WLCSP64 UFBGA 100 LQFP100 UFBGA LQFP64 UFQ 144 WLCSP FPN48 LQFP144 64 1. The FSMC can also be used to interface most graphic LCD controllers. 2. Limited application for the USART3 since RX is not available for the UFQFPN48. 14/205 - 1 Operating voltage Package 1 Yes 1 No 2 Maximum CPU frequency Operating temperatures 4 1 USB/OTG FS Dual power rail Number of digital Filters for Sigma-delta modulator Number of channels 1 5/5 (2 full duplex) I2C I 1 DS11139 Rev 8 UFBGA UFBGA 100 144 LQFP100 LQFP144 STM32F412xE/G Compatibility with STM32F4 series The STM32F412xE/G are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package PB11 not available anymore Replaced by V CAP_1 58 57 56 55 54 53 52 51 41 42 43 44 45 46 47 48 49 50 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP_1 VSS VDD 58 57 56 55 54 53 52 51 41 42 43 44 45 46 47 48 49 50 STM32F405/STM32F415 line STM32F407/STM32F417 line STM32F427/STM32F437 line STM32F429/STM32F439 line STM32F401xx STM32F411xx STM32F412xx STM32F446xx PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 2.1 Description PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS VDD VSS VDD MSv37802V2 DS11139 Rev 8 15/205 41 Description STM32F412xE/G Figure 2. Compatible board design for LQFP64 package STM32F401xx STM32F410xx STM32F411xx STM32F412xx STM32F446xx PC12 PC11 PC10 PA15 PA14 PC12 PC11 PC10 PA15 PA14 670)670)OLQH VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD VSS 53 525150 49 48 47 46 45 44 43 42 41 40 39 38 37 3%QRWDYDLODEOHDQ\PRUH 36 5HSODFHGE\9CAP_1 35 34 33 28 2930 3132 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD VSS PB2 PB10 VCAP_1 VSS VDD PB2 PB10 PB11 VCAP_1 VDD 53 525150 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 28 2930 3132 VCAP_1 increased to 4.7 μf (65ŸRUEHORZ VSS V S S V DD VDD MSv37803V2 Figure 3. Compatible board design for LQFP144 package STM32F405/STM32F415 line STM32F407/STM32F417 line STM32F427/STM32F437 line STM32F429/STM32F439 line PD1 PD0 PC12 PC11 PC10 PA15 PA14 115 114 113 112 111 110 109 115 114 113 112 111 110 109 PD1 PD0 PC12 PC11 PC10 PA15 PA14 STM32F412xx STM32F446xx 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 Separate USB power rail. Connected to VDD if a different power supply for the USB is not required. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_USB VSS PG8 MSv39446V1 16/205 DS11139 Rev 8 STM32F412xE/G Description Figure 4. STM32F412xE/G block diagram ETM FSMC NOR Flash, SRAM, PSRAM AHB3 MPU/FPU I-BUS ARM Cortex-M4 Cortex-M4 100 MHz CLK, NE[3:0], A[25:0], D[16:0], NOEN, NWEN, NBL[1:0], NWAIT CLK, CSA, CSB, D[7:0] Quad-SPI NVIC 256 KB SRAM1 D-BUS S-BUS ACCEL/ CACHE JTAG & SW AHB bus-matrix 6S4M JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO TRACECLK TRACED[3:0] Up to 1MB Flash memory RNG FIFO PA[15:0] GPIO PORT A GPIO PORT B AHB1 100 MHz 8 Streams DMA1 PB[15:0] FIFO 8 Streams DMA2 VDD FIFO @VDDA USB OTG FS Power managmt Voltage regulator 3.3 to 1.2 V POR reset GPIO PORT C Int GPIO PORT D PE[15:0] GPIO PORT E VDDA, VSSA NRST PVD @VDDA @VDD XTAL OSC 4- 16MHz GPIO PORT G PH[1:0] GPIO PORT H Reset & clock M AN AGT control OSC_IN OSC_OUT WDG 32K PWR interface VBAT = 1.8 to 3.6 V @V PCLK HCLK APB2CLK APB1CLK AHB2PCLK AHB1PCLK PG[15:0] VDD= 1.8 to 3.6 V VSS VCAP_1, VCAP_2 Supply supervision POR/PDR BOR PLL1-PLL2 PD[15:0] D+ DSCL, SDA, INT, ID, VBUS @VDD RC HS RC L S PC[15:0] @VDDUSB @VDD PHY AHB2 100MHz BAT LS LS XTAL 32 kHz RTC AWU Backup register OSC32_IN OSC32_OUT ALARM_OUT STAMP1 CRC DMA2 EXT IT. WKUP D[7:0] CMD,CK as AF SDIO/MMC 32b 4 channels as AF TIM3 32b 4 channels as AF DMA1 AHB/ APB2 FIFO 112 AF TIM2 AHB/ APB1 TIM4 32b 4 channels as AF TIM5 32b 4 channels as AF TIM1 / PWM 16b TIM12 16b 2 channels as AF 4 PWM, 3 PWM, ETR, BKIN as AF TIM8 / PWM 16b TIM13 16b 1 channels as AF TIM14 16b 2 channels as AF 16b TIM9 1 channel as AF APB1 50 MHz (max) 4 PWM, 3 PWM, ETR, BKIN as AF TIM10 16b WWDG 1 channel as AF TIM11 RX, TX, SCK, CTS, RTS as AF smcard irDA USART6 16 analog inputs 16b TIMER7 16b irDA SPI2/I2S2 SPI3/I2S3 1 channels as AF RX, TX, SCK, CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF MOSI, MISO, SCK, NSS/WS, MCK as AF MOSI, MISO, SCK, NSS/WS, MCK as AF SPI1/I2S1 I2C1/SMBUS SCL, SDA, SMBA as AF SPI4/I2S4 I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF I2CFMP1/SMBUS SCL, SDA, SMBA as AF SPI5/I2S5 CKIN[3:0], DATIN[3:0], CKOUT VDDREF_ADC TIMER6 irDA smcard DFSDM U S AR T 2 Msensor Bps Temperature ADC1 FIFO MOSI, MISO, SCK, NSS/WS as AF MOSI, MISO, SCK, NSS/WS as AF USART1 irDA USART2 USART3 2 MOSI, MISO, SCK, NSS/WS as AF APB2 100 MHz RX, TX, SCK, CTS, RTS as AF smcard 16b smcard IF CAN1 TX, RX CAN2 TX, RX @VDDA MSv37275V3 1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 50 MHz. DS11139 Rev 8 17/205 41 Functional overview STM32F412xE/G 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F412xE/G devices are compatible with all Arm tools and software. Figure 4 shows the general block diagram of the STM32F412xE/G. Note: Cortex®-M4 with FPU is binary compatible with Cortex®-M3. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 125 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 100 MHz. 3.3 Batch Acquisition mode (BAM) The Batch acquisition mode allows enhanced power efficiency during data batching. It enables data acquisition through any communication peripherals directly to memory using the DMA in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and ART). For example in an audio system, a smart combination of PDM audio sample acquisition and processing from the DFSDM directly to RAM (flash and ART™ stopped) with the DMA using BAM followed by some very short processing from flash allows to drastically reduce the power consumption of the application. A dedicated application note (AN4515) describes how to implement the STM32F412xE/G BAM to allow the best power efficiency. 18/205 DS11139 Rev 8 STM32F412xE/G 3.4 Functional overview Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.5 Embedded Flash memory The devices embed up to 1 Mbyte of Flash memory available for storing programs and data. The Flash user area can be protected against reading by an entrusted code (Read Protection, RDP) with different protection levels. The flash user sectors can also be individually protected against write operation. Furthermore the proprietary readout protection (PCROP) can also individually protect the flash user sectors against D-bus read accesses. (Additional information can be found in the product reference manual). To optimize the power consumption the Flash memory can also be switched off in Run or in Sleep mode (see Section 3.21: Low-power modes). Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between power saving and startup time. Before disabling the Flash, the code must be executed from the internal RAM. 3.6 One-time programmable bytes A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can be individually locked (Additional information can be found in the product reference manual) 3.7 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. DS11139 Rev 8 19/205 41 Functional overview 3.8 STM32F412xE/G Embedded SRAM All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states 3.9 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 5. Multi-AHB matrix S1 S3 S4 DMA_P2 DMA_MEM2 DMA_MEM1 DMA_PI S-bus S2 GP DMA2 GP DMA1 S5 M0 ICODE M1 DCODE Bus matrix-S ACCEL S0 D-bus I-bus ARM Cortex-M4 Flash Up to 1MB M2 SRAM1 256 KB M3 AHB periph. 1 APB1 M4 AHB periph. 2 APB2 M5 FSMC external MemCtrl/ QuadSPI MSv37276V1 3.10 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. 20/205 DS11139 Rev 8 STM32F412xE/G Functional overview The DMA can be used with the main peripherals: 3.11 • SPI and I2S • I2C and I2CFMP • USART • General-purpose, basic and advanced-control timers TIMx • SD/SDIO/MMC/eMMC host interface • Quad-SPI • ADC • Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter. Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR Flash memory. The main functions are: • 8-,16-bit data bus width • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.12 Quad-SPI memory interface (QUAD-SPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode. Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or 32-bit mode. Code execution is also supported. The opcode and the frame format are fully programmable. Communication can be performed either in single data rate or dual data rate. DS11139 Rev 8 21/205 41 Functional overview 3.13 STM32F412xE/G Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.14 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 3.15 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 22/205 DS11139 Rev 8 STM32F412xE/G 3.16 Functional overview Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash memory • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using one of the interface listed in the Table 3 or the USB OTG FS in device mode through DFU (device firmware upgrade). Table 3. Embedded bootloader interfaces Package USART1 USART2 USART3 I2C1 PA9/ PD6/ PB11/ PB6/ PA10 PD5 PB10 PB7 SPI3 I2C2 PF0/ PF1 I2C3 PA8/ PB4 I2C FMP1 PB14/ PB15 SPI1 PA4/ PA5/ PA6/ PA7 PA15/ PC10/ PC11/ PC12 SPI4 PE11/ CAN2 USB PE12/ PB5/ PA11 PE13/ PB13 /P12 PE14 UFQFPN48 Y - - Y - Y Y Y - - Y Y WLCSP64 Y - - Y - Y Y Y Y - Y Y LQFP64 Y - - Y - Y Y Y Y - Y Y LQFP100 Y Y - Y - Y Y Y Y Y Y Y LQFP144 Y Y Y Y Y Y Y Y Y Y Y Y UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y For more detailed information on the bootloader, refer to Application Note: AN2606, STM32™ microcontroller system memory boot mode. 3.17 Note: Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor (POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and NRST pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with decoupling technique. The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF and internal power supply supervisor availability to identify the packages supporting this option. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. • VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6 V) for USB transceivers. For example, when device is powered at 1.8 V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, DS11139 Rev 8 23/205 41 Functional overview STM32F412xE/G it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: – During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – VDDUSB rising and falling time rate specifications must be respected. – In operating mode phase, VDDUSB could be lower or higher than VDD: – If USB is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. – If USB is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 6. VDDUSB connected to an external independent power supply VDDUSB_MAX USB functional area VDDUSB VDDUSB_MIN USB non functional area VDD = VDDA Power-on Operating mode USB non functional area VDD_MIN Power-down time MS37590V1 24/205 DS11139 Rev 8 STM32F412xE/G Functional overview 3.18 Power supply supervisor 3.18.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.18.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low. An external power supply supervisor should monitor VDD and should set the device in reset mode when VDD is below 1.7 V. NRST should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. DS11139 Rev 8 25/205 41 Functional overview STM32F412xE/G Figure 7. Power supply supervisor interconnection with internal reset OFF(1) VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V NRST PDR_ON VDD MSv34975V1 1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.19 • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. • The embedded programmable voltage detector (PVD) is disabled. • VBAT functionality is no more available and VBAT pin should be connected to VDD. Voltage regulator The regulator has three operating modes: 3.19.1 – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. The WLCSP64 is available in two versions, one with the regulator internally enabled and one with the regulator internally disabled. On all other packages, the regulator is always enabled. 26/205 DS11139 Rev 8 STM32F412xE/G Functional overview There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run mode) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. • LPR is used in the Stop mode The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Depending on the package, one or two external ceramic capacitors should be connected on the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the 100 pins and 144 pins packages. All packages have the regulator ON feature. 3.19.2 Regulator OFF The regulator is disabled by holding BYPASS_REG pin high. This feature is available only on UFBGA100 and UFBGA144 packages, which feature the BYPASS_REG pin. The WLCSP64 is available in two versions, one with a fixed enabled regulator and one with a fixed disabled regulator (see Table 4: Regulator ON/OFF and internal power supply supervisor availability and Section 8: Ordering information). The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. DS11139 Rev 8 27/205 41 Functional overview STM32F412xE/G Figure 8. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor Ext. reset controller active signal (optional) when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V3 The following conditions must be respected: Note: 28/205 • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DS11139 Rev 8 STM32F412xE/G Functional overview Figure 9. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V V12 Min V12 VCAP_1/VCAP_2 time NRST PA0 time MSv31179V2 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V VCAP_1/VCAP_2 V12 Min V12 time NRST PA0 asserted externally time MSv31180V1 1. This figure is valid whatever the internal reset mode (ON or OFF). DS11139 Rev 8 29/205 41 Functional overview 3.19.3 STM32F412xE/G Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal power supply supervisor availability Package Regulator ON Regulator OFF Power supply supervisor ON Power supply supervisor OFF UFQFPN48 Yes No Yes No WLCSP64 Yes No Yes PDR_ON set to VDD Yes PDR_ON set to VSS WLCSP64 option P(1) No Yes Yes PDR_ON set to VDD Yes PDR_ON set to VSS LQFP64 Yes No Yes No LQFP100 Yes No Yes No LQFP144 Yes No Yes PDR_ON set to VDD Yes PDR_ON set to VSS UFBGA100 Yes Yes BYPASS_REG set to BYPASS_REG set to VSS VDD UFBGA144 Yes Yes BYPASS_REG set to BYPASS_REG set to VSS VDD 1. Refer to Section 8: Ordering information. 3.20 Real-time clock (RTC) and backup registers The backup domain includes: • The real-time clock (RTC) • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The backup registers are 32-bit registers used to store 80 byte of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, 30/205 DS11139 Rev 8 STM32F412xE/G Functional overview or when the device wakes up from the Standby mode (see Section 3.21: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.21 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. To further reduce the power consumption, the Flash memory can be switched off before entering in Sleep mode. Note that this requires a code execution from the RAM. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/ tamper/ time stamp events). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp event occurs. Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 3.22 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external super-capacitor, or from VDD when no external battery and an external super-capacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC and the backup registers. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal DS11139 Rev 8 31/205 41 Functional overview STM32F412xE/G Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.23 Timers and watchdogs The devices embed two advanced-control timer, ten general-purpose timers, two basic timers, two watchdog timers and one SysTick timer. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control and general-purpose timers. 32/205 DS11139 Rev 8 STM32F412xE/G Functional overview Table 5. Timer feature comparison Timer type Advance d-control Counter Counter Prescaler Timer resolution type factor TIM1, TIM8 TIM2, TIM5 TIM3, TIM4 TIM9 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 100 100 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 50 100 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 50 100 16-bit Up Any integer between 1 and 65536 No 2 No 100 100 Up Any integer between 1 and 65536 No 1 No 100 100 Up Any integer between 1 and 65536 No 2 No 50 100 Up Any integer between 1 and 65536 No 1 No 50 100 Up Any integer between 1 and 65536 Yes 0 No 50 100 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic timers TIM6, TIM7 Max. Max. DMA Capture/ Complemen- interface timer request compare tary output clock clock generation channels (MHz) (MHz) 16-bit 16-bit 16-bit 16-bit DS11139 Rev 8 33/205 41 Functional overview 3.23.1 STM32F412xE/G Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator multiplexed on 4 independent channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete generalpurpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability (0-100%). The advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.23.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F412xE/G (see Table 5 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F412xE/G devices include 4 full-featured general-purpose timers: TIM2. TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in conjunction with the other general-purpose timers and TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM output. TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or onepulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 fullfeatured general-purpose timers or used as simple time bases. 3.23.3 Basic timer (TIM6, TIM7) TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request generation. 34/205 DS11139 Rev 8 STM32F412xE/G 3.23.4 Functional overview Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.23.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.23.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.24 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I2C) The devices feature up to four I2C bus interfaces which can operate in multimaster and slave modes: • One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to 400 kHz) modes and Fast-mode plus (up to 1 MHz). • Three I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode (up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on the complete solution, refer to the nearest STMicroelectronics sales office. All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave) and embed a hardware CRC generation/verification. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 6). Table 6. Comparison of I2C analog and digital filters Pulse width of suppressed spikes Analog filter Digital filter ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks DS11139 Rev 8 35/205 41 Functional overview 3.25 STM32F412xE/G Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6). These four interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s. USART2 and USART3 interfaces communicate at up to 6.25 bit/s. All USART interfaces provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 7. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X X X X X 6.25 12.5 APB2 (max. 100 MHz) USART2 X X X X X X 3.12 6.25 APB1 (max. 50 MHz) (1) X X X X X X 3.12 6.25 APB1 (max. 50 MHz) USART6 X X X X X X 6.25 12.5 APB2 (max. 100 MHz) USART3 1. The RX is not available for the UFQFPN48 package. 3.26 Serial peripheral interface (SPI) The devices feature five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interfaces can be configured to operate in TI mode for communications in master mode and slave mode. 36/205 DS11139 Rev 8 STM32F412xE/G 3.27 Functional overview Inter-integrated sound (I2S) Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in master or slave mode, in simplex communication mode, and full duplex mode for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. 3.28 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Different sources can be selected for the I2S master clock of the APB1 and the I2S master clock of the APB2. This gives the flexibility to work with two different audio sampling frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin (external PLL or Codec output) The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. 3.29 Digital filter for sigma-delta modulators (DFSDM) The device embeds one DFSDM with 2 digital filters modules and 4 external input serial channels (transceivers) or alternately 2 internal parallel inputs support. The amount of filters defines the number of conversions which can be performed simultaneously. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. DS11139 Rev 8 37/205 41 Functional overview STM32F412xE/G The DFSDM peripheral supports: • • 4 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0...20 MHz alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution): – • 2 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1...5), oversampling ratio (up to 1...1024) – integrator: oversampling ratio (1...256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by • • 38/205 internal sources: device memory data streams (DMA) – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM1FLT0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1...3, oversampling ratio = 1...32 – input from digital output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1...256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel • break signal generation on analog watchdog event or on short circuit detector event • extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit input serial channel clock absence • “regulator” or injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority. DS11139 Rev 8 STM32F412xE/G 3.30 Functional overview Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.31 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 byte of SRAM are allocated for each CAN. 3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection (BCD) can detect and identify the type of port, it is connected to (standard USB or charger). The type of charging is also detected: Dedicated Charging Port (DCP), Charging Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a dedicated USB power rail allowing a different supply for the USB and for the rest of the chip. For instance the chip can be powered with the minimum specified supply and the USB running at the level defined by the standard. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected • Link power management (LPM) • Battery charging detection (BCD) supporting DCP, CDP, and SDP (battery charging specification revision 1.2) DS11139 Rev 8 39/205 41 Functional overview 3.33 STM32F412xE/G Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 100 MHz. 3.35 Analog-to-digital converter (ADC) One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer. 3.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.37 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 40/205 DS11139 Rev 8 STM32F412xE/G 3.38 Functional overview Embedded Trace Macrocell™ The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F412xE/G through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DS11139 Rev 8 41/205 41 Pinouts and pin description STM32F412xE/G 4 Pinouts and pin description 4.1 WLSCP64 pinout description Figure 11. STM32F412xE/G WLCSP64 pinout 8 7 6 5 4 3 2 1 A VDD VSS PB7 PB3 PD2 PC12 PA15 VDD B PC13 VBAT PB9 PB6 PB4 PC11 PA14 VSS PDR_ON PB8 PB5 PC10 PA13 PA12 C PC14PC15OSC32_IN OSC32_OUT D PH0 OSC_IN NRST PC3 PC0 BOOT0 PA11 PA10 PA9 E PH1 OSC_OUT PC2 PA0 PA7 PC4 PA8 PC9 PC7 F PC1 VDDA/ VREF+ PA3 PA5 PB1 PC8 PB15 PC6 G VSSA/ VREF- PA1 PA4 PC5 PB2 PB12 PB13 PB14 H PA2 VDD PA6 PB0 PB10 VCAP_1 VSS VDD MSv37280V2 1. The above figure shows the package bump side. 42/205 DS11139 Rev 8 STM32F412xE/G UFQFPN48 pinout description PA15 PA14 PB5 41 PB3 43 42 PB4 44 PB6 PC13 PC14-OSC32_IN 45 PB7 PB9 46 BOOT0 VSS 48 1 47 VBAT PB8 VDD Figure 12. STM32F412xE/G UFQFPN48 pinout 40 39 38 37 36 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH0-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA/VREF- 8 29 PA8 VDDA/VREF+ 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 13 14 15 16 17 18 19 20 21 22 23 25 24 PB12 PB0 PB1 PB2 PB10 VSS VDD PA13 PA7 VSS 34 PA6 35 3 PA5 2 PA4 VDD PA3 UFQFPN48 VCAP_1 4.2 Pinouts and pin description MS31150V3 1. The above figure shows the package top view. DS11139 Rev 8 43/205 72 Pinouts and pin description 4.3 STM32F412xE/G LQFP64 pinout description VBAT PC13 PC14-OSC32_IN VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 VCAP_1 VSS VDD PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA/VREFVDDA/VREF+ PA0 PA1 PA2 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD Figure 13. STM32F412xE/G LQFP64 pinout MS31149V3 1. The above figure shows the package top view. 44/205 DS11139 Rev 8 STM32F412xE/G LQFP100 pinout description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 14. STM32F412xE/G LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VDD VSSA/VREFVREF+ VDDA PA0 PA1 PA2 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP_1 VSS VDD 4.4 Pinouts and pin description MS31151V4 1. The above figure shows the package top view. DS11139 Rev 8 45/205 72 Pinouts and pin description 4.5 STM32F412xE/G LQFP144 pinout description VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Figure 15. STM32F412xE/G LQFP144 pinout PE2 PE3 PE4 PE5 1 2 3 4 108 VDD 107 VSS 106 VCAP_2 105 PA13 PE6 5 104 PA12 VBAT 6 103 PA11 PC13 7 PC14-OSC32_IN 8 102 101 PA10 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 PF2 12 98 97 PC8 PC7 PF3 13 96 PC6 PF4 14 95 VDDUSB PF5 15 94 VSS VSS 16 93 PG8 VDD 17 92 PG7 PF6 18 91 PG6 PF7 19 90 PG5 PF8 20 89 PG4 PF9 21 88 PG3 PF10 22 87 PG2 PH0 - OSC_IN 23 86 PD15 PH1 - OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 29 80 PD11 VDD 30 79 PD10 VSSA/VREF- 31 78 PD9 VREF+ 32 77 PD8 VDDA 33 76 PB15 PA0 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD LQFP144 MSv37281V3 1. The above figure shows the package top view. 46/205 DS11139 Rev 8 STM32F412xE/G 4.6 Pinouts and pin description UFBGA100 pinout description Figure 16. STM32F412xE/G UFBGA100 pinout 1 2 3 A PE3 PE1 PB8 B PE4 PE2 C PC13 7 8 9 10 11 12 PD5 PB4 PB3 PA15 PA14 PA13 PA12 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PD2 PD0 PC11 VCAP _2 PA10 VSS PA9 PA8 PC9 BYPASS _REG PC8 PC7 PC6 VSS VSS VSS PH1OSC_ OUT VDD VDD VDD H PC0 NRST PDR _ON PD15 PD14 PD13 J VSSA PC1 PC2 PD12 PD11 PD10 K VREF- PC3 PA2 PA5 PC4 L VREF+ PA0 PA3 PA6 PC5 PB2 M VDDA PA1 PA4 PA7 PB0 PB1 D E F G 4 5 6 BOOT0 PD7 PB9 PB7 PB6 PE5 PE0 VDD PB5 PC14OSC32 _IN PE6 PC15OSC32 _OUT VBAT PH0OSC_ IN PD9 PB11 PB15 PB14 PB13 PE8 PE10 PE12 PB10 VCAP _1 PB12 PE7 PE9 PE11 PE13 PE14 PE15 MSv37282V1 1. The above figure shows the package top view. DS11139 Rev 8 47/205 72 Pinouts and pin description 4.7 STM32F412xE/G UFBGA144 pinout description Figure 17. STM32F412xE/G UFBGA144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 A PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13 B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 VDDUSB PA11 D PH0 OSC_IN VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E PH1 OSC_OUT PF3 PF4 PF5 PDR_ON VSS VSS PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7 G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP_2 VSS PG8 PC6 H PC0 PC1 PC2 PC3 BYPASS_ REG VSS VCAP_1 PE11 PD11 PG7 PG6 PG5 J VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 MSv37283V2 1. The above figure shows the package top view. 4.8 Pin definition Table 8. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes 48/205 Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input/ output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O B Dedicated BOOT0 pin NRST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 8. Legend/abbreviations used in the pinout table (continued) Name Abbreviation Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 9. STM32F412xE/G pin definition LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions - - - - 1 B2 A3 1 PE2 I/O FT - TRACECLK, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, QUADSPI_BK1_IO2, FSMC_A23, EVENTOUT - - - 2 A1 A2 2 PE3 I/O FT - TRACED0, FSMC_A19, EVENTOUT - - TRACED1, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, DFSDM1_DATIN3, FSMC_A20, EVENTOUT - - TRACED2, TIM9_CH1, SPI4_MISO, SPI5_MISO, DFSDM1_CKIN3, FSMC_A21, EVENTOUT - - TRACED3, TIM9_CH2, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_A22, EVENTOUT - - - - - - - 3 4 B1 C2 B2 B3 3 4 PE4 I/O PE5 I/O FT FT - - - 5 D2 B4 5 PE6 I/O FT 1 1 B7 6 E2 C2 6 VBAT S - - - VBAT EVENTOUT TAMP_1 EVENTOUT OSC32_IN 2 2 B8 7 C1 A1 7 PC13 I/O FT (2)(3) 3 3 C8 8 D1 B1 8 PC14OSC32_IN I/O FT (2)(3)(4) DS11139 Rev 8 49/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) 4 4 C7 9 E1 C1 9 PC15OSC32_ OUT I/O FT (2)(4) EVENTOUT OSC32_ OUT - - - - - C3 10 PF0 I/O FT - I2C2_SDA, FSMC_A0, EVENTOUT - - - - - - C4 11 PF1 I/O FT - I2C2_SCL, FSMC_A1, EVENTOUT - - - - - - D4 12 PF2 I/O FT - I2C2_SMBA, FSMC_A2, EVENTOUT - - - - - - E2 13 PF3 I/O FT - TIM5_CH1, FSMC_A3, EVENTOUT - - - - - - E3 14 PF4 I/O FT - TIM5_CH2, FSMC_A4, EVENTOUT - - - - - - E4 15 PF5 I/O FT - TIM5_CH3, FSMC_A5, EVENTOUT - - - - 10 F2 D2 16 VSS S - - - - - - - 11 G2 D3 17 VDD S - - - - - - - - - F3 18 PF6 I/O FT - TRACED0, TIM10_CH1, QUADSPI_BK1_IO3, EVENTOUT - - - - - - F2 19 PF7 I/O FT - TRACED1, TIM11_CH1, QUADSPI_BK1_IO2, EVENTOUT - - - - - - G3 20 PF8 I/O FT - TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT - - - - - - G2 21 PF9 I/O FT - TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT - - - - - - G1 22 PF10 I/O FT - TIM1_ETR, TIM5_CH4, EVENTOUT - 5 5 D8 12 F1 D1 23 PH0 OSC_IN I/O FT (4) EVENTOUT OSC_IN 6 6 E8 13 G1 E1 24 PH1 OSC_OUT I/O FT (4) EVENTOUT OSC_OUT 7 7 D7 14 H2 F1 25 NRST I/O RST - - NRST 50/205 DS11139 Rev 8 Alternate functions Additional functions STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) - 8 D5 15 H1 H1 26 PC0 I/O FT - EVENTOUT ADC1_10, WKUP2 - 9 F8 16 J2 H2 27 PC1 I/O FT - EVENTOUT ADC1_11, WKUP3 ADC1_12 Alternate functions Additional functions - 10 E7 17 J3 H3 28 PC2 I/O FT - SPI2_MISO, I2S2ext_SD, DFSDM1_CKOUT, FSMC_NWE, EVENTOUT - 11 D6 18 K2 H4 29 PC3 I/O FT - SPI2_MOSI/I2S2_SD, FSMC_A0, EVENTOUT ADC1_13 - - - 19 - - 30 VDD S - - - - 20 - - 31 VSSA/ VREF- S - - - - 8 12 G8 - - - - J1 J1 - VSSA S - - - - - - - - K1 K1 - VREF- S - - - - 9 13 F7 - - - - VDDA/ VREF+ S - - - - - - - 21 L1 L1 32 VREF+ S - - - - - - - 22 M1 M1 33 VDDA S - - - - - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, EVENTOUT ADC1_0, WKUP1 - TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, QUADSPI_BK1_IO3, EVENTOUT ADC1_1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, FSMC_D4/FSMC_DA4, EVENTOUT ADC1_2 10 11 12 14 E6 15 G7 16 H8 23 24 25 L2 M2 K3 J2 K2 L2 34 35 36 PA0 PA1 PA2 I/O I/O I/O FT FT FT DS11139 Rev 8 51/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions ADC1_3 13 17 F6 26 L3 M2 37 PA3 I/O FT - TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, FSMC_D5/FSMC_DA5, EVENTOUT - 18 - 27 - G4 38 VSS S - - - - - - - - E3 H5 - BYPASS_ REG I FT - - - 28 - F4 39 VDD S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1, FSMC_D6/FSMC_DA6, EVENTOUT ADC1_4 - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1, FSMC_D7/FSMC_DA7, EVENTOUT ADC1_5 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, QUADSPI_BK2_IO0, SDIO_CMD, EVENTOUT ADC1_6 - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, QUADSPI_BK2_IO1, EVENTOUT ADC1_7 - I2S1_MCK, QUADSPI_BK2_IO2, FSMC_NE4, EVENTOUT ADC1_14 - 14 15 16 17 - 19 H7 20 G6 21 F5 22 H6 23 E5 24 E4 52/205 29 30 31 32 33 M3 K4 L4 M4 K5 J3 K3 L3 M3 J4 40 41 42 43 44 PA4 PA5 PA6 PA7 PC4 I/O I/O I/O I/O I/O FT FT FT FT FT DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) - 18 25 G5 26 H5 34 35 L5 M5 K4 L4 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 45 46 Pin name I/O (function Pin Notes type structure after (1) reset) PC5 PB0 I/O I/O FT FT Alternate functions Additional functions - I2CFMP1_SMBA, USART3_RX, QUADSPI_BK2_IO3, FSMC_NOE, EVENTOUT ADC1_15 - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI5_SCK/I2S5_CK, EVENTOUT ADC1_8 ADC1_9 19 27 F4 36 M6 M4 47 PB1 I/O FT - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0, QUADSPI_CLK, EVENTOUT 20 28 G4 37 L6 J5 48 PB2 I/O FT - DFSDM1_CKIN0, QUADSPI_CLK, EVENTOUT BOOT1 - - - - - M5 49 PF11 I/O FT - TIM8_ETR, EVENTOUT - - - - - - L5 50 PF12 I/O FT - TIM8_BKIN, FSMC_A6, EVENTOUT - - - - - - - 51 VSS S - - - - - - - - - G5 52 VDD S - - - - - - - - - K5 53 PF13 I/O FT - I2CFMP1_SMBA, FSMC_A7, EVENTOUT - - - - - - M6 54 PF14 I/O FT - I2CFMP1_SCL, FSMC_A8, EVENTOUT - - - - - - L6 55 PF15 I/O FT - I2CFMP1_SDA, FSMC_A9, EVENTOUT - - - - - - K6 56 PG0 I/O FT - CAN1_RX, FSMC_A10, EVENTOUT - - - - - - J6 57 PG1 I/O FT - CAN1_TX, FSMC_A11, EVENTOUT - DS11139 Rev 8 53/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - - - - - - 38 39 M7 L7 M7 L7 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 58 59 Pin name I/O (function Pin Notes type structure after (1) reset) PE7 PE8 I/O I/O FT FT Alternate functions Additional functions - TIM1_ETR, DFSDM1_DATIN2, QUADSPI_BK2_IO0, FSMC_D4/FSMC_DA4, EVENTOUT - - TIM1_CH1N, DFSDM1_CKIN2, QUADSPI_BK2_IO1, FSMC_D5/FSMC_DA5, EVENTOUT - - - - - 40 M8 K7 60 PE9 I/O FT - TIM1_CH1, DFSDM1_CKOUT, QUADSPI_BK2_IO2, FSMC_D6/FSMC_DA6, EVENTOUT - - - - - - 61 VSS S - - - - - - - - - G6 62 VDD S - - - - - TIM1_CH2N, QUADSPI_BK2_IO3, FSMC_D7/FSMC_DA7, EVENTOUT - - TIM1_CH2, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, FSMC_D8/FSMC_DA8, EVENTOUT - - TIM1_CH3N, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, FSMC_D9/FSMC_DA9, EVENTOUT - - TIM1_CH3, SPI4_MISO, SPI5_MISO, FSMC_D10/FSMC_DA1 0, EVENTOUT - - TIM1_CH4, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_D11/FSMC_DA1 1, EVENTOUT - - - - - - - - - - - 54/205 - - - - - 41 42 43 44 45 L8 M9 L9 M10 M11 J7 H8 J8 K8 L8 63 64 65 66 67 PE10 PE11 PE12 PE13 PE14 I/O I/O I/O I/O I/O FT FT FT FT FT DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin Number - - - 46 M12 M8 68 21 - 29 H4 - - 47 L10 M9 69 Pin name I/O (function Pin Notes type structure after (1) reset) PE15 PB10 I/O I/O FT FT Alternate functions Additional functions - TIM1_BKIN, FSMC_D12/FSMC_DA1 2, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL, SDIO_D7, EVENTOUT - - - K9 M10 70 PB11 I/O FT - TIM2_CH4, I2C2_SDA, I2S2_CKIN, USART3_RX, EVENTOUT 22 30 H3 48 L11 H7 71 VCAP_1 S - - - - 23 31 H2 49 F12 H6 - VSS S - - - - 24 32 H1 50 G12 G7 72 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, USART3_CK, CAN2_RX, DFSDM1_DATIN1, FSMC_D13/FSMC_DA1 3, EVENTOUT - - TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX, DFSDM1_CKIN1, EVENTOUT - 25 26 33 G3 34 G2 51 52 L12 K12 M11 M12 73 74 PB12 PB13 I/O I/O FT FT DS11139 Rev 8 55/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) 27 28 35 G1 36 F2 53 54 K11 K10 L11 L12 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 75 76 Pin name I/O (function Pin Notes type structure after (1) reset) PB14 PB15 I/O I/O FT FT Alternate functions Additional functions - TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0/FSMC_DA0, SDIO_D6, EVENTOUT - - RTC_50Hz, TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2, SDIO_CK, EVENTOUT - - - - - 55 - L9 77 PD8 I/O FT - USART3_TX, FSMC_D13/ FSMC_DA13, EVENTOUT - - - 56 K8 K9 78 PD9 I/O FT - USART3_RX, FSMC_D14/FSMC_DA1 4, EVENTOUT - - - - 57 J12 J9 79 PD10 I/O FT - USART3_CK, FSMC_D15/FSMC_DA1 5, EVENTOUT - - I2CFMP1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, FSMC_A16, EVENTOUT - - TIM4_CH1, I2CFMP1_SCL, USART3_RTS, QUADSPI_BK1_IO1, FSMC_A17, EVENTOUT - - - - - 56/205 - - 58 59 J11 J10 H9 L10 80 81 PD11 PD12 I/O I/O FT FT DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions - - - - 60 H12 K10 82 PD13 I/O FT - TIM4_CH2, I2CFMP1_SDA, QUADSPI_BK1_IO3, FSMC_A18, EVENTOUT - - - - - G8 83 VSS S - - - - - - - - - F8 84 VDD S - - - - - TIM4_CH3, I2CFMP1_SCL, FSMC_D0/FSMC_DA0, EVENTOUT - - - - - 61 H11 K11 85 PD14 I/O FT - - - 62 H10 K12 86 PD15 I/O FT - TIM4_CH4, I2CFMP1_SDA, FSMC_D1/FSMC_DA1, EVENTOUT - - - - - J12 87 PG2 I/O FT - FSMC_A12, EVENTOUT - - - - - - J11 88 PG3 I/O FT - FSMC_A13, EVENTOUT - - - - - - J10 89 PG4 I/O FT - FSMC_A14, EVENTOUT - - - - - - H12 90 PG5 I/O FT - FSMC_A15, EVENTOUT - - - - - - H11 91 PG6 I/O FT - QUADSPI_BK1_NCS, EVENTOUT - - - - - - H10 92 PG7 I/O FT - USART6_CK, EVENTOUT - - - - - - G11 93 PG8 I/O FT - USART6_RTS, EVENTOUT - - - - - - - 94 VSS S - - - - - - - - - F10 - VDD S - - - - - - C11 95 VDDUSB S - - - - DS11139 Rev 8 57/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - - - - 29 30 31 37 F1 38 E1 39 F3 40 E2 41 E3 42 D1 43 D2 58/205 63 64 65 66 67 68 69 E12 E11 E10 D12 D11 D10 C12 G12 F12 F11 E11 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 96 97 98 99 E12 100 D12 101 D11 102 Pin name I/O (function Pin Notes type structure after (1) reset) PC6 PC7 PC8 PC9 PA8 PA9 PA10 I/O I/O I/O I/O I/O I/O I/O FT FT FT FT FT FT FT DS11139 Rev 8 Alternate functions Additional functions - TIM3_CH1, TIM8_CH1, I2CFMP1_SCL, I2S2_MCK, DFSDM1_CKIN3, USART6_TX, FSMC_D1/FSMC_DA1, SDIO_D6, EVENTOUT - - TIM3_CH2, TIM8_CH2, I2CFMP1_SDA, SPI2_SCK/I2S2_CK, I2S3_MCK, USART6_RX, DFSDM1_DATIN3, SDIO_D7, EVENTOUT - - TIM3_CH3, TIM8_CH3, USART6_CK, QUADSPI_BK1_IO2, SDIO_D0, EVENTOUT - - MCO_2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S2_CKIN, QUADSPI_BK1_IO0, SDIO_D1, EVENTOUT - - MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1, EVENTOUT - - TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2, EVENTOUT - - TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID, EVENTOUT - STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) 32 44 D3 70 B12 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number C12 103 Pin name I/O (function Pin Notes type structure after (1) reset) PA11 I/O FT Alternate functions Additional functions - TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, USB_FS_DM, EVENTOUT - - 33 45 C1 71 A12 B12 104 PA12 I/O FT - TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX, USB_FS_DP, EVENTOUT 34 46 C2 72 A11 A12 105 PA13 I/O FT - JTMS-SWDIO, EVENTOUT - 73 C11 G9 VCAP_2 S - - - - G10 107 VSS S - - - - - - - 106 35 47 B1 74 F11 36 48 - 75 G11 - - VDD S - - - - - - A1 - - F9 108 VDD S - - - - 76 A10 A11 109 PA14 I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, EVENTOUT - - SPI3_SCK/I2S3_CK, USART3_TX, QUADSPI_BK1_IO1, SDIO_D2, EVENTOUT - - I2S3ext_SD, SPI3_MISO, USART3_RX, QUADSPI_BK2_NCS, FSMC_D2/FSMC_DA2, SDIO_D3, EVENTOUT - 37 38 - - 49 B2 50 A2 51 C3 52 B3 77 78 79 A9 B11 C10 A10 B11 B10 110 111 112 PA15 PC10 PC11 I/O I/O I/O FT FT FT DS11139 Rev 8 59/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - 53 A3 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions - 80 B10 C10 113 PC12 I/O FT - SPI3_MOSI/I2S3_SD, USART3_CK, FSMC_D3/FSMC_DA3, SDIO_CK, EVENTOUT - - - 81 C9 E10 114 PD0 I/O FT - CAN1_RX, FSMC_D2/FSMC_DA2, EVENTOUT - - - - 82 B9 D10 115 PD1 I/O FT - CAN1_TX, FSMC_D3/FSMC_DA3, EVENTOUT - - TIM3_ETR, FSMC_NWE, SDIO_CMD, EVENTOUT - - TRACED1, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS, QUADSPI_CLK, FSMC_CLK, EVENTOUT - - - - 54 A4 - - 83 84 C8 B8 E9 D9 116 117 PD2 PD3 I/O I/O FT FT - - - 85 B7 C9 118 PD4 I/O FT - DFSDM1_CKIN0, USART2_RTS, FSMC_NOE, EVENTOUT - - - 86 A6 B9 119 PD5 I/O FT - USART2_TX, FSMC_NWE, EVENTOUT - - - - - - E7 120 VSS S - - - - - - - - - F7 121 VDD S - - - - - SPI3_MOSI/I2S3_SD, DFSDM1_DATIN1, USART2_RX, FSMC_NWAIT, EVENTOUT - - DFSDM1_CKIN1, USART2_CK, FSMC_NE1, EVENTOUT - - - - - 60/205 - - 87 88 B6 A5 A8 A9 122 123 PD6 PD7 I/O I/O FT FT DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions - - - - - - E8 124 PG9 I/O FT - USART6_RX, QUADSPI_BK2_IO2, FSMC_NE2, EVENTOUT - - - - - D8 125 PG10 I/O FT - FSMC_NE3, EVENTOUT - - - - - - C8 126 PG11 I/O FT - CAN2_RX, EVENTOUT - - - - - - B8 127 PG12 I/O FT - USART6_RTS, CAN2_TX, FSMC_NE4, EVENTOUT - - TRACED2, USART6_CTS, FSMC_A24, EVENTOUT - - - - - - - D7 128 PG13 I/O FT - - - - - C7 129 PG14 I/O FT - TRACED3, USART6_TX, QUADSPI_BK2_IO3, FSMC_A25, EVENTOUT - - - - - - 130 VSS S - - - - - - - - - F6 131 VDD S - - - - - - - - - B7 132 PG15 I/O FT - USART6_CTS, EVENTOUT - - JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, I2C2_SDA, EVENTOUT - - JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0, EVENTOUT - 39 40 55 A5 56 B4 89 90 A8 A7 A7 A6 133 134 PB3 PB4 I/O I/O FT FT DS11139 Rev 8 61/205 72 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) 41 57 C4 91 C5 B6 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 135 Pin name I/O (function Pin Notes type structure after (1) reset) PB5 I/O FT Alternate functions Additional functions - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, SDIO_D3, EVENTOUT - - 42 58 B5 92 B5 C6 136 PB6 I/O FT - TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, SDIO_D0, EVENTOUT 43 59 A6 93 B4 D6 137 PB7 I/O FT - TIM4_CH2, I2C1_SDA, USART1_RX, FSMC_NL, EVENTOUT - 44 60 D4 94 A4 D5 138 BOOT0 I B - - VPP - TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, CAN1_RX, I2C3_SDA, SDIO_D4, EVENTOUT - - 45 46 61 C5 62 B6 95 A3 C5 139 PB8 I/O FT 96 B3 B5 140 PB9 I/O FT - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, I2C2_SDA, SDIO_D5, EVENTOUT - - - 97 C3 A5 141 PE0 I/O FT - TIM4_ETR, FSMC_NBL0, EVENTOUT - - - - 98 A2 A4 142 PE1 I/O FT - FSMC_NBL1, EVENTOUT - 99 D3 E6 - VSS S - - - - - H3 E5 143 PDR_ON I FT - - - C4 F5 144 VDD S - - - - 47 48 63 A7 - C6 64 A8 100 1. Function availability depends on the chosen device. 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 62/205 DS11139 Rev 8 STM32F412xE/G Pinouts and pin description 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F412xE/Greference manual. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). Table 10. FSMC pin definition FSMC Pins 64 pins 100 pins 144 pins A23 - Yes Yes A19 A19 - Yes Yes PE4 A20 A20 - Yes Yes PE5 A21 A21 - Yes Yes PE6 A22 A22 - Yes Yes PF0 A0 - - - Yes PF1 A1 - - - Yes PF2 A2 - - - Yes PF3 A3 - - - Yes PF4 A4 - - - Yes PF5 A5 - - - Yes PC2 NWE NWE Yes Yes Yes PC3 A0 - Yes Yes Yes PA2 D4 DA4 Yes Yes Yes PA3 D5 DA5 Yes Yes Yes PA4 D6 DA6 Yes Yes Yes PA5 D7 DA7 Yes Yes Yes PC4 NE4 NE4 Yes Yes Yes PC5 NOE NOE Yes Yes Yes PF12 A6 - - - Yes PF13 A7 - - - Yes PF14 A8 - - - Yes PF15 A9 - - - Yes PG0 A10 - - - Yes PG1 A11 - - - Yes PE7 D4 DA4 - Yes Yes PE8 D5 DA5 - Yes Yes PE9 D6 DA6 - Yes Yes LCD/NOR/PSR AM/SRAM NOR/PSRAM Mux PE2 A23 PE3 DS11139 Rev 8 63/205 72 Pinouts and pin description STM32F412xE/G Table 10. FSMC pin definition FSMC Pins 64/205 64 pins 100 pins 144 pins DA7 - Yes Yes D8 DA8 - Yes Yes PE12 D9 DA9 - Yes Yes PE13 D10 DA10 - Yes Yes PE14 D11 DA11 - Yes Yes PE15 D12 DA12 - Yes Yes PB12 D13 DA13 Yes Yes Yes PB14 D0 DA0 Yes Yes Yes PD8 D13 DA13 - - Yes PD9 D14 DA14 - Yes Yes PD10 D15 DA15 - Yes Yes PD11 A16 A16 - Yes Yes PD12 A17 A17 - Yes Yes PD13 A18 A18 - Yes Yes PD14 D0 DA0 - Yes Yes PD15 D1 DA1 - Yes Yes PG2 A12 - - - Yes PG3 A13 - - - Yes PG4 A14 - - - Yes PG5 A15 - - - Yes PC6 D1 DA1 Yes Yes Yes PC11 D2 DA2 Yes Yes Yes PC12 D3 DA3 Yes Yes Yes PD0 D2 DA2 - Yes Yes PD1 D3 DA3 - Yes Yes PD2 NWE NWE Yes Yes Yes PD3 CLK CLK - Yes Yes PD4 NOE NOE - Yes Yes PD5 NWE NEW - Yes Yes PD6 NWAIT NWAIT - Yes Yes PD7 NE1 NE1 - Yes Yes PG9 NE2 NE2 - - Yes PG10 NE3 NE3 - - Yes LCD/NOR/PSR AM/SRAM NOR/PSRAM Mux PE10 D7 PE11 DS11139 Rev 8 STM32F412xE/G Pinouts and pin description Table 10. FSMC pin definition FSMC Pins 64 pins 100 pins 144 pins A24 - - Yes A25 A25 - - Yes PB7 NL NL Yes Yes Yes PE0 NBL0 NBL0 - Yes Yes PE1 NBL1 NBL1 - Yes Yes LCD/NOR/PSR AM/SRAM NOR/PSRAM Mux PG12 A24 PG14 DS11139 Rev 8 65/205 72 AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR - - - USART2_CTS - - - - EVENTOUT PA1 - TIM2_CH2 TIM5_CH2 - - SPI4_MOSI/I 2S4_SD - USART2_RTS - QUADSPI_ BK1_IO3 - - EVENTOUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - I2S2_CKIN - USART2_TX - - - FSMC_D4 EVENTOUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - I2S2_MCK - USART2_RX - - - FSMC_D5 EVENTOUT PA4 - - - - - SPI1_NSS/I2 S1_WS SPI3_NSS/ I2S3_WS USART2_CK DFSDM1_ DATIN1 - - FSMC_D6 EVENTOUT PA5 - TIM2_CH1/ TIM2_ETR - TIM8_CH1N - SPI1_SCK/ I2S1_CK - - DFSDM1_ CKIN1 - - FSMC_D7 EVENTOUT PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO I2S2_MCK - - TIM13_ CH1 QUADSPI_ BK2_IO0 SDIO_CMD EVENTOUT PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I 2S1_SD - - - TIM14_ CH1 QUADSPI_ BK2_IO1 - EVENTOUT PA8 MCO_1 TIM1_CH1 - - I2C3_SCL - - USART1_CK - - USB_FS_ SOF SDIO_D1 EVENTOUT PA9 - TIM1_CH2 - - I2C3_ SMBA - - USART1_TX - - USB_FS_ VBUS SDIO_D2 EVENTOUT PA10 - TIM1_CH3 - - - - SPI5_MOSI/ I2S5_SD USART1_RX - - USB_FS_ID - EVENTOUT PA11 - TIM1_CH4 - - - - SPI4_MISO USART1_CTS USART6_ TX CAN1_RX USB_FS_DM - EVENTOUT PA12 - TIM1_ETR - - - - SPI5_MISO USART1_RTS USART6_ RX CAN1_TX USB_FS_DP - EVENTOUT PA13 JTMSSWDIO - - - - - - - - - - - EVENTOUT PA14 JTCKSWCLK - - - - - - - - - - - EVENTOUT PA15 JTDI TIM2_CH1/ TIM2_ETR - - - SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART1_TX - - - - EVENTOUT Port Port A DS11139 Rev 8 STM32F412xE/G AF1 Pinouts and pin description 66/205 Table 11. STM32F412xE/G alternate functions AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - SPI5_SCK/ I2S5_CK - - - - - EVENTOUT PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - SPI5_NSS/ I2S5_WS - DFSDM1_ DATIN0 QUADSPI_ CLK - - EVENTOUT PB2 - - - - - - DFSDM1_ CKIN0 - - QUADSPI_ CLK - - EVENTOUT PB3 JTDOSWO TIM2_CH2 I2CFMP1_ SDA SPI1_SCK/I2 S1_CK SPI3_SCK/ I2S3_CK USART1_RX - I2C2_SDA - - EVENTOUT PB4 JTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO I2S3ext_ SD - I2C3_SDA - SDIO_D0 EVENTOUT PB5 - - TIM3_CH2 - I2C1_SMBA SPI1_MOSI/I 2S1_SD SPI3_MOSI/ I2S3_SD - - CAN2_RX - SDIO_D3 EVENTOUT PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - CAN2_TX QUADSPI_ BK1_NCS SDIO_D0 EVENTOUT PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - FSMC_NL EVENTOUT PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - SPI5_MOSI/I2S 5_SD - CAN1_RX I2C3_SDA - SDIO_D4 EVENTOUT PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/ I2S2_WS - - CAN1_TX I2C2_SDA - SDIO_D5 EVENTOUT PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK/ I2S2_CK I2S3_MCK USART3_TX - I2CFMP1_ SCL - SDIO_D7 EVENTOUT PB11 - TIM2_CH4 - - I2C2_SDA I2S2_CKIN - USART3_RX - - - - EVENTOUT PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/ I2S2_WS SPI4_NSS/ I2S4_WS SPI3_SCK/ I2S3_CK USART3_ CK CAN2_RX DFSDM1_ DATIN1 FSMC_D13/F SMC_DA13 EVENTOUT PB13 - TIM1_CH1N - - I2CFMP1_ SMBA SPI2_SCK/ I2S2_CK SPI4_SCK/ I2S4_CK - USART3_ CTS CAN2_TX DFSDM1_ CKIN1 - EVENTOUT PB14 - TIM1_CH2N - TIM8_CH2N I2CFMP1_ SDA SPI2_MISO I2S2ext_SD USART3_ RTS DFSDM1_ DATIN2 TIM12_CH1 FSMC_D0 SDIO_D6 EVENTOUT PB15 RTC_ 50Hz TIM1_CH3N - TIM8_CH3N I2CFMP1_ SCL SPI2_MOSI/I 2S2_SD - - DFSDM1_ CKIN2 TIM12_CH2 - SDIO_CK EVENTOUT DS11139 Rev 8 Port B Port 67/205 Pinouts and pin description AF1 STM32F412xE/G Table 11. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PC0 - - - - - - - - - - - - EVENTOUT PC1 - - - - - - - - - - - - EVENTOUT PC2 - - - - - SPI2_MISO I2S2ext_SD - DFSDM1_ CKOUT - - FSMC_NWE EVENTOUT PC3 - - - - - SPI2_MOSI/I 2S2_SD - - - - - FSMC_A0 EVENTOUT PC4 - - - - - I2S1_MCK - - - - QUADSPI_ BK2_IO2 FSMC_NE4 EVENTOUT PC5 - - - - I2CFMP1_ SMBA - - USART3_RX - - QUADSPI_ BK2_IO3 FSMC_NOE EVENTOUT PC6 - - TIM3_CH1 TIM8_CH1 I2CFMP1_ SCL I2S2_MCK DFSDM1_ CKIN3 - USART6_ TX - FSMC_D1 SDIO_D6 EVENTOUT PC7 - - TIM3_CH2 TIM8_CH2 I2CFMP1_ SDA SPI2_SCK/ I2S2_CK I2S3_MCK - USART6_ RX - DFSDM1_ DATIN3 SDIO_D7 EVENTOUT PC8 - - TIM3_CH3 TIM8_CH3 - - - - USART6_ CK QUADSPI_ BK1_IO2 - SDIO_D0 EVENTOUT PC9 MCO_2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN - - - QUADSPI_ BK1_IO0 - SDIO_D1 EVENTOUT PC10 - - - - - - SPI3_SCK/ I2S3_CK USART3_TX - QUADSPI_ BK1_IO1 - SDIO_D2 EVENTOUT PC11 - - - - - I2S3ext_SD SPI3_MISO USART3_RX - QUADSPI_ BK2_NCS FSMC_D2 SDIO_D3 EVENTOUT PC12 - - - - - - SPI3_MOSI/ I2S3_SD USART3_CK - - FSMC_D3 SDIO_CK EVENTOUT PC13 - - - - - - - - - - - - EVENTOUT PC14 - - - - - - - - - - - - EVENTOUT PC15 - - - - - - - - - - - - EVENTOUT DS11139 Rev 8 Port C Port STM32F412xE/G AF1 Pinouts and pin description 68/205 Table 11. STM32F412xE/G alternate functions (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PD0 - - - - - - - - - CAN1_RX - FSMC_D2/FS MC_DA2 EVENTOUT PD1 - - - - - - - - - CAN1_TX - FSMC_D3/FS MC_DA3 EVENTOUT PD2 - - TIM3_ETR - - - - - - - FSMC_NWE SDIO_CMD EVENTOUT DFSDM1_ DATIN0 USART2_ CTS - QUADSPI_ CLK - FSMC_CLK EVENTOUT Port Port D DS11139 Rev 8 TRACED1 - - - - PD4 - - - - - - DFSDM1_ CKIN0 USART2_ RTS - - - FSMC_NOE EVENTOUT PD5 - - - - - - - USART2_TX - - - FSMC_NWE EVENTOUT PD6 - - - - - SPI3_MOSI/I 2S3_SD DFSDM1_ DATIN1 USART2_RX - - - FSMC_ NWAIT EVENTOUT PD7 - - - - - - DFSDM1_ CKIN1 USART2_CK - - - FSMC_NE1 EVENTOUT PD8 - - - - - - - USART3_TX - - - FSMC_D13/ FSMC_DA13 EVENTOUT PD9 - - - - - - - USART3_RX - - - FSMC_D14/ FSMC_DA14 EVENTOUT PD10 - - - - - - - USART3_CK - - - FSMC_D15/ FSMC_DA15 EVENTOUT PD11 - - - - I2CFMP1_ SMBA - - USART3_ CTS - QUADSPI_ BK1_IO0 - FSMC_A16 EVENTOUT PD12 - - TIM4_CH1 - I2CFMP1_ SCL USART3_ RTS - QUADSPI_ BK1_IO1 - FSMC_A17 EVENTOUT PD13 - - TIM4_CH2 - I2CFMP1_ SDA - - - - QUADSPI_ BK1_IO3 - FSMC_A18 EVENTOUT PD14 - - TIM4_CH3 - I2CFMP1_ SCL - - - - - - FSMC_D0/ FSMC_DA0 EVENTOUT PD15 - - TIM4_CH4 - I2CFMP1_ SDA - - - - - - FSMC_D1/ FSMC_DA1 EVENTOUT Pinouts and pin description 69/205 PD3 SPI2_SCK/ I2S2_CK STM32F412xE/G Table 11. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PE0 - - TIM4_ETR - - - - - - - - FSMC_NBL0 EVENTOUT PE1 - - - - - - - - - - - FSMC_NBL1 EVENTOUT PE2 TRACECL K - - - - SPI4_SCK/ I2S4_CK SPI5_SCK/ I2S5_CK - - QUADSPI_ BK1_IO2 - FSMC_A23 EVENTOUT PE3 TRACED0 - - - - - - - - - - FSMC_A19 EVENTOUT PE4 TRACED1 - - - - SPI4_NSS/ I2S4_WS SPI5_NSS/ I2S5_WS - DFSDM1_ DATIN3 - - FSMC_A20 EVENTOUT PE5 TRACED2 - - TIM9_CH1 - SPI4_MISO SPI5_MISO - DFSDM1_ CKIN3 - - FSMC_A21 EVENTOUT PE6 TRACED3 - - TIM9_CH2 - SPI4_MOSI/I 2S4_SD SPI5_MOSI/ I2S5_SD - - - - FSMC_A22 EVENTOUT PE7 - TIM1_ETR - - - - DFSDM1_ DATIN2 - - - QUADSPI_ BK2_IO0 FSMC_D4/ FSMC_DA4 EVENTOUT PE8 - TIM1_CH1N - - - - DFSDM1_ CKIN2 - - - QUADSPI_ BK2_IO1 FSMC_D5/ FSMC_DA5 EVENTOUT PE9 - TIM1_CH1 - - - - DFSDM1_ CKOUT - - - QUADSPI_ BK2_IO2 FSMC_D6/ FSMC_DA6 EVENTOUT PE10 - TIM1_CH2N - - - - - - - - QUADSPI_ BK2_IO3 FSMC_D7/ FSMC_DA7 EVENTOUT PE11 - TIM1_CH2 - - - SPI4_NSS/ I2S4_WS SPI5_NSS/ I2S5_WS - - - FSMC_D8/ FSMC_DA8 EVENTOUT PE12 - TIM1_CH3N - - - SPI4_SCK/ I2S4_CK SPI5_SCK/ I2S5_CK - - - - FSMC_D9/ FSMC_DA9 EVENTOUT PE13 - TIM1_CH3 - - - SPI4_MISO SPI5_MISO - - - - FSMC_D10/ FSMC_DA10 EVENTOUT PE14 - TIM1_CH4 - - - SPI4_MOSI/I 2S4_SD SPI5_MOSI/ I2S5_SD - - - - FSMC_D11/ FSMC_DA11 EVENTOUT PE15 - TIM1_BKIN - - - - - - - - - FSMC_D12/ FSMC_DA12 EVENTOUT Port Port E DS11139 Rev 8 STM32F412xE/G AF1 Pinouts and pin description 70/205 Table 11. STM32F412xE/G alternate functions (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PF0 - - - - I2C2_SDA - - - - - - FSMC_A0 EVENTOUT PF1 - - - - I2C2_SCL - - - - - - FSMC_A1 EVENTOUT PF2 - - - - I2C2_SMBA - - - - - - FSMC_A2 EVENTOUT PF3 - - TIM5_CH1 - - - - - - - - FSMC_A3 EVENTOUT PF4 - - TIM5_CH2 - - - - - - - - FSMC_A4 EVENTOUT PF5 - - TIM5_CH3 - - - - - - - - FSMC_A5 EVENTOUT - - EVENTOUT DS11139 Rev 8 Port F Port TRACED0 - - TIM10_CH1 - - - - - PF7 TRACED1 - - TIM11_CH1 - - - - - QUADSPI_ BK1_IO2 - - EVENTOUT PF8 - - - - - - - - - TIM13_CH1 QUADSPI_ BK1_IO0 - EVENTOUT PF9 - - - - - - - - - TIM14_CH1 QUADSPI_ BK1_IO1 - EVENTOUT PF10 - TIM1_ETR TIM5_CH4 - - - - - - - - - EVENTOUT PF11 - - - TIM8_ETR - - - - - - - - EVENTOUT PF12 - - - TIM8_BKIN - - - - - - - FSMC_A6 EVENTOUT PF13 - - - - I2CFMP1_ SMBA - - - - - - FSMC_A7 EVENTOUT PF14 - - - - I2CFMP1_ SCL - - - - - - FSMC_A8 EVENTOUT PF15 - - - - I2CFMP1_ SDA - - - - - - FSMC_A9 EVENTOUT 71/205 Pinouts and pin description PF6 QUADSPI_ BK1_IO3 STM32F412xE/G Table 11. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PG0 - - - - - - - - - CAN1_RX - FSMC_A10 EVENTOUT PG1 - - - - - - - - - CAN1_TX - FSMC_A11 EVENTOUT PG2 - - - - - - - - - - - FSMC_A12 EVENTOUT PG3 - - - - - - - - - - - FSMC_A13 EVENTOUT PG4 - - - - - - - - - - - FSMC_A14 EVENTOUT PG5 - - - - - - - - - - - FSMC_A15 EVENTOUT PG6 - - - - - - - - - - QUADSPI_ BK1_NCS - EVENTOUT PG7 - - - - - - - - USART6_ CK - - - EVENTOUT PG8 - - - - - - - - USART6_ RTS - - - EVENTOUT PG9 - - - - - - - - USART6_ RX QUADSPI_ BK2_IO2 - FSMC_NE2 EVENTOUT PG10 - - - - - - - - - - - FSMC_NE3 EVENTOUT PG11 - - - - - - - - - CAN2_RX - - EVENTOUT PG12 - - - - - - - - USART6_ RTS CAN2_TX - FSMC_NE4 EVENTOUT PG13 TRACED2 - - - - - - - USART6_ CTS - - FSMC_A24 EVENTOUT PG14 TRACED3 - - - - - - - USART6_ TX QUADSPI_ BK2_IO3 - FSMC_A25 EVENTOUT PG15 - - - - - - - - USART6_ CTS - - - EVENTOUT PH0 - - - - - - - - - - - - EVENTOUT PH1 - - - - - - - - - - - - EVENTOUT Port H DS11139 Rev 8 Port G Port STM32F412xE/G AF1 Pinouts and pin description 72/205 Table 11. STM32F412xE/G alternate functions (continued) STM32F412xE/G 5 Memory mapping Memory mapping The memory map is shown in Figure 18. Figure 18. Memory map Reserved Cortex -M4 internal peripherals Reserved 0xE010 0000 - 0xFFFF FFFF 0xE000 0000 - 0xE00F FFFF 0xA000 2000 – 0DFFF FFF 0xA000 1FFF AHB3 0x6000 0000 0x5FFF FFFF AHB2 Reserved 0xFFFF FFFF 512-Mbyte block 7 internal Peripherals 0x5000 0000 0x4002 6800 - 0x4FFF FFFF 0x4002 67FF AHB1 0xE000 0000 0xDFFF FFFF 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF Reserved Reserved 0x4002 0000 0x4001 7400 - 0x4001 FFFF 0x4001 63FF 0xA000 2000 0xA000 1FFF FSMC and QuadSPI 0x6000 0000 0x5FFF FFFF APB2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 Peripherals 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Peripherals 0x0000 0000 Reserved 0x2004 0000 - 0x3FFF FFFF SRAM (256 KB aliased by bit-banding) 0x2000 0000 - 0x2003 FFFF Reserved Option bytes Reserved 0x1FFF C008 - 0x1FFF FFFF 0x4001 0000 0x4000 7400 - 0x4000 FFFF 0x4000 73FF 0x1FFF C000 - 0x1FFF C007 0x1FFF 7A10 - 0x1FFF BFFF Reserved OTP area + lock System memory 0x1FFF 7800 - 0x1FFF 7A0F 0x1FFF 0000 - 0x1FFF 77FF Reserved Flash memory 0x0800 0000 - 0x080F FFFF 0x0808 0000 - 0x1FFE FFFF APB1 0x0010 0000 - 0x07FF FFFF Reserved Aliased to Flash, system, memory or SRAM depending, 0x0000 0000 - 0x000F FFFF on the BOOT pins 0x4000 0000 DS11139 Rev 8 MSv37284V4 73/205 76 Memory mapping STM32F412xE/G Table 12. STM32F412xE/G register boundary addresses Bus ® Cortex -M4 AHB3 AHB2 AHB1 74/205 Boundary address Peripheral 0xE010 0000 - 0xFFFF FFFF Reserved 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 2000 - 0xDFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF QuadSPI control register 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF QUADSPI 0x7000 0000 - 0x08FFF FFFF Reserved 0x6000 0000 - 0x6FFF FFFF FSMC 0x5006 0C00 - 0x5FFF FFFF Reserved 0x5006 0800 0x5006 0BFF RNG 0x5004 000- 0x5006 07FF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4002 6800 - 0x4FFF FFFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2000 - 0x4002 2FFF Reserved 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DS11139 Rev 8 STM32F412xE/G Memory mapping Table 12. STM32F412xE/G register boundary addresses (continued) Bus APB2 Boundary address Peripheral 0x4001 6400- 0x4001 FFFF Reserved 0x4001 6000 - 0x4001 63FF DFSDM1 0x4001 5400 - 0x4001 5FFF Reserved 0x4001 5000 - 0x4001 53FF SPI5/I2S5 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4/I2S4 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7400 - 0x4000 FFFF Reserved DS11139 Rev 8 75/205 76 Memory mapping STM32F412xE/G Table 12. STM32F412xE/G register boundary addresses (continued) Bus APB1 76/205 Boundary address Peripheral 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800- 0x4000 6BFF CAN2 0x4000 6400- 0x4000 67FF CAN1 0x4000 6000- 0x4000 63FF I2CFMP1 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 4C00 - 0x4000 53FF Reserved 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 DS11139 Rev 8 STM32F412xE/G Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Input voltage measurement MCU pin MCU pin C = 50 pF VIN MS19011V2 DS11139 Rev 8 MS19010V2 77/205 165 Electrical characteristics 6.1.6 STM32F412xE/G Power supply scheme Figure 21. Power supply scheme VBAT VBAT = 1.65 to 3.6V GPIOs IN 2 × 2.2 μF VDD 1/2/...11/12 11 × 100 nF + 1 × 4.7 μF VDD_USB VCAP_1 VCAP_2 VSS 1/2/...11/12 IO Logic Kernel logic (CPU, digital & RAM) Voltage regulator BYPASS_REG 100 nF + 1 μF PDR_ON VDD Flash memory OTG FS PHY VDDUSB Reset controller VDDA VREF 100 nF + 1 μF Level shifter OUT VDD Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers) Power switch 100 nF + 1 μF VREF+ VREF- ADC Analog: RCs, PLL,.. VSSA MSv39022V2 1. To connect PDR_ON pin, refer to Section: Power supply supervisor. 2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 3. VCAP_2 pad is only available on 100-pin and 144-pin packages. 4. VDDA=VDD and VSSA=VSS. 5. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and associated DP/DM GPIOs. VDDUSB value does not depend on the VDD and VDDA values, but it must be the last supply to be provided and the first to disappear. Caution: 78/205 Each power supply pair (for example VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DS11139 Rev 8 STM32F412xE/G 6.1.7 Electrical characteristics Current consumption measurement Figure 22. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics, Table 14: Current characteristics, and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 13. Voltage characteristics Symbol VDD–VSS VIN Ratings Min Max –0.3 4.0 Input voltage on FT and TC pins(2) VSS–0.3 VDD+4.0 Input voltage on any other pin VSS–0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 External main supply voltage (including VDDA, VDD, VDDUSB and VBAT)(1) Input voltage for BOOT0 |ΔVDDx| |VSSX −VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current. DS11139 Rev 8 79/205 165 Electrical characteristics STM32F412xE/G Table 14. Current characteristics Symbol Ratings Max. ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 160 Σ IVSS (1) -160 Σ IVDDUSB Total current out of sum of all VSS_x ground lines (sink) Total current into VDDUSB power lines (source) 25 IVDD Maximum current into each VDD_x power line (source)(1) 100 IVSS (1) -100 IIO Maximum current out of each VSS_x ground line (sink) Output current sunk by any I/O and control pin 25 Output current sourced by any I/O and control pin -25 Total output current sunk by sum of all I/O and control pins ΣIIO ΣIINJ(PIN) (2) Injected current on FT and TC pins mA 120 Total output current sunk by sum of all USB I/Os Total output current sourced by sum of all I/Os and control IINJ(PIN) (3) Unit 25 pins(2) -120 (4) –5/+0 Injected current on NRST and B pins (4) Total injected current (sum of all I/O and control pins)(5) ±25 1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 15. Thermal characteristics Symbol TSTG TJ TLEAD Ratings Storage temperature range Maximum junction temperature Maximum lead temperature during soldering (WLCSP64, LQFP64/100/144, UFQFPN48, UFBGA100/144) Value Unit –65 to +150 130 °C see note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011). 80/205 DS11139 Rev 8 STM32F412xE/G Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 16. General operating conditions Symbol fHCLK Parameter Internal AHB clock frequency Conditions Min Typ Max Power Scale3: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x01 0 - 64 Power Scale2: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x10 0 - 84 Power Scale1: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x11 0 - 100 Unit MHz fPCLK1 Internal APB1 clock frequency - 0 - 50 MHz fPCLK2 Internal APB2 clock frequency - 0 - 100 MHz Standard operating voltage - 1.7(1) - 3.6 V 1.7(1) - 2.4 VDD VDDA(2)(3) VDDUSB VBAT Analog operating voltage (ADC limited to 1.2 M samples) Analog operating voltage (ADC limited to 2.4 M samples) Must be the same potential as VDD(4) USB supply voltage USB not used (supply voltage for PA11 and USB used(5) PA12 pins) Backup operating voltage - V 2.4 - 3.6 1.7 3.3 3.6 3.0 - 3.6 1.65 - 3.6 V V VOS[1:0] bits in PWR_CR register = 0x01 1.08(6) 1.14 1.20(6) Max frequency 64 MHz V12 V12 VIN Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins Regulator OFF: 1.2 V external voltage must be supplied on VCAP_1/VCAP_2 pins VOS[1:0] bits in PWR_CR register = 0x10 1.20(6) 1.26 1.32(6) Max frequency 84 MHz VOS[1:0] bits in PWR_CR register = 0x11 Max frequency 100 MHz 1.26 1.32 1.38 Max frequency 64 MHz 1.10 1.14 1.20 Max frequency 84 MHz 1.20 1.26 1.32 Max frequency 100 MHz 1.26 1.32 1.38 -0.3 - 5.5 -0.3 - 5.2 0 - 9 Input voltage on RST, FT and 2 V ≤ VDD ≤ 3.6 V TC pins(7) VDD ≤ 2 V Input voltage on BOOT0 pin - DS11139 Rev 8 V V V 81/205 165 Electrical characteristics STM32F412xE/G Table 16. General operating conditions (continued) Symbol PD PD TA TJ Parameter Power dissipation at TA = 85°C for range 6 or TA = 105°C for range 7(8) Power dissipation at TA = 125 °C for range 3(8) Conditions Min Typ Max UFQFPN48 - - 625 WLCSP64 - - 392 LQFP64 - - 425 LQFP100 - - 465 LQFP144 - - 571 UFBGA100 - - 351 UFBGA144 - - 416 UFQFPN48 - - 156 WLCSP64 - - 98 LQFP64 - - 106 LQFP100 - - 116 LQFP144 - - 142 UFBGA100 - - 88 UFBGA144 - - 104 -40 - 85 -40 - 105 Ambient temperature for range 6 Maximum power dissipation Ambient temperature for range 7 Maximum power dissipation -40 - 105 Low power dissipation(9) -40 - 125 Ambient temperature for range 3 Maximum power dissipation -40 - 110 Low power dissipation -40 - 130 Range 6 -40 - 105 Range 7 -40 - 125 Range 3 -40 - 130 Junction temperature range Low power dissipation(9) (9) 1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 2. When the ADC is used, refer to Table 72: ADC characteristics. 3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 5. Only the DM (PA11) and DP (PA12) pads are supplied through VDDUSB. For application where the VBUS (PA9) is directly connected to the chip, a minimum VDD supply of 2.7V is required. (some application examples are shown in appendix B) 6. Guaranteed by test in production 7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. 82/205 DS11139 Rev 8 Unit mW °C STM32F412xE/G Electrical characteristics Table 17. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.7 to 3.6 V(6) Conversion time up to 2.4 Msps Maximum Flash memory access frequency with no wait states (fFlashmax) Maximum Flash memory access frequency with wait states (1)(2) I/O operation Clock output frequency on I/O pins(3) Possible Flash memory operations 100 MHz with 6 wait states – No I/O up to 30 MHz compensation 8-bit erase and program operations only 18 MHz 100 MHz with 5 wait states – No I/O up to 30 MHz compensation 16-bit erase and program operations 24 MHz 100 MHz with 4 wait states – I/O compensation up to 50 MHz works 16-bit erase and program operations 100 MHz with 3 wait states – up to 100 MHz when VDD = – I/O 3.0 to 3.6 V compensation – up to works 50 MHz when VDD = 2.7 to 3.0 V 32-bit erase and program operations (5) 16 MHz 30 MHz 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. Refer to Table 59: I/O AC characteristics for frequencies vs. external load. 4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 5. Prefetch available over the complete VDD supply range. 6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V. DS11139 Rev 8 83/205 165 Electrical characteristics 6.3.2 STM32F412xE/G VCAP_1/VCAP_2 external capacitors Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors are replaced by a single capacitor. CEXT is specified in Table 18. Figure 23. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. Table 18. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor with the pins VCAP_1 and VCAP_2 available 2.2 µF ESR ESR of external capacitor with the pins VCAP_1 and VCAP_2 available 2.4 V, the compensation cell should be used. Figure 36. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf”7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&LVSHFLILHGLQWKHWDEOH³I/O AC characteristics”. ai14131d 6.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 57). Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 16. Refer to Table 57: I/O static characteristics for the values of VIH and VIL for NRST pin. Table 60. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ VF(NRST)(2) NRST Input filtered pulse - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design, not tested in production. 126/205 DS11139 Rev 8 STM32F412xE/G Electrical characteristics Figure 37. Recommended NRST pin protection VDD External reset circuit (1) RPU NRST (2) Internal Reset Filter 0.1 μF STM32F ai14132c 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 60. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 61 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 61. TIMx characteristics(1)(2) Symbol tres(TIM) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 100 MHz 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 11.9 - ns Parameter Timer resolution time AHB/APBx prescaler>4, fTIMxCLK = 100 MHz fEXT ResTIM tCOUNTER Timer external clock frequency on CH1 to CH4 f TIMxCLK = 100 MHz 0 fTIMxCLK/2 MHz 0 50 MHz Timer resolution - 16/32 bit 0.0119 780 µs - 65536 × 65536 tTIMxCLK - 51.1 S 16-bit counter clock period when internal clock fTIMxCLK = 100 MHz is selected Maximum possible count tMAX_COUNT with 32-bit counter fTIMxCLK = 100 MHz 1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers. 2. Guaranteed by design, not tested in production. 3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK >= 4x PCLKx. DS11139 Rev 8 127/205 165 Electrical characteristics 6.3.19 STM32F412xE/G Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 62. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, contact your local ST sales representative. Table 62. I2C characteristics Symbol Standard mode I2C(1)(2) Parameter Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - 0 900(4) µs th(SDA) SDA data hold time 0 3450(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - µs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - µs tSP Pulse width of the spikes that are suppressed by the analog filter for standard fast mode - - 50 120(5) ns Cb Capacitive load for each bus line - 400 - 400 pF ns µs 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 128/205 DS11139 Rev 8 STM32F412xE/G Electrical characteristics 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 5. The minimum width of the spikes filtered by the analog filter is above tSP (max) Figure 38. I2C bus AC waveforms and measurement circuit VDD_I2C VDD_I2C RP RP STM32Fxx RS SDA I²C bus RS SCL START REPEATED START START tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLH) tw(STO:STA) STOP th(SDA) SCL tr(SCL) tw(SCLL) tf(SCL) tsu(STO) MSv43011V1 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 63. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 2 1. RP = External pull-up resistance, fSCL = I C speed 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external components used to design the application. DS11139 Rev 8 129/205 165 Electrical characteristics STM32F412xE/G FMPI2C characteristics The following table presents FMPI2C characteristics. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output function characteristics (SDA and SCL). Table 64. FMPI2C characteristics(1) Standard mode Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 18 - fFMPI2CC FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 - tsu(SDA) SDA setup time 0.25 - 0.10 - 0.05 - tH(SDA) SDA data hold time 0 - 0 - 0 - - 3.45 - 0.9 - 0.45 tv(SDA,ACK) Data, ACK valid time tr(SDA) tr(SCL) SDA and SCL rise time - 1.0 - 0.30 - 0.12 tf(SDA) tf(SCL) SDA and SCL fall time - 0.30 - 0.30 - 0.12 th(STA) Start condition hold time 4 - 0.6 - 0.26 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - 0.26 - tsu(STO) Stop condition setup time 4 - 0.6 - 0.26 - 4.7 - 1.3 - 0.5 - tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.1 0.05 0.1 Cb Capacitive load for each bus Line - 400 - 400 - 550(2) tw(STO:STA) Stop to Start condition time (bus free) 1. Based on characterization results, not tested in production. 2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas: tr(SDA/SCL) = 0.8473 x Rp x Cload Rp(min) = (VDD -VOL(max)) / IOL(max) 130/205 DS11139 Rev 8 µs pF STM32F412xE/G Electrical characteristics Figure 39. FMPI2C timing diagram and measurement circuit VDD_I2C VDD_I2C RP RP STM32Fxx RS SDA I²C bus RS SCL START REPEATED START START tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLH) STOP th(SDA) tw(STO:STA) SCL tw(SCLL) tr(SCL) tf(SCL) tsu(STO) MSv43012V1 DS11139 Rev 8 131/205 165 Electrical characteristics STM32F412xE/G SPI interface characteristics Unless otherwise specified, the parameters given in Table 65 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 65. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Duty(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master full duplex/receiver mode, 2.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Master transmitter mode 1.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Master mode 1.7 V < VDD < 3.6 V SPI1/2/3/4/5 - - 25 Slave transmitter/full duplex mode 2.7 V < VDD < 3.6 V SPI1//4/5 - - 50 Slave transmitter/full duplex mode 1.7 V < VDD < 3.6 V SPI1/4/5 - - 35(2) Slave receiver mode, 1.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Slave mode, 1.7 V < VDD < 3.6 V SPI2/3 - - 25 30 50 70 % Duty cycle of SPI clock Slave mode frequency Unit MHz tw(SCKH) tw(SCKL) SCK high and low time Master mode, SPI presc = 2 TPCLK−1.5 TPCLK TPCLK +1.5 ns tsu(NSS) NSS setup time Slave mode, SPI presc = 2 3TPCLK - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK - - ns Master mode 4.5 - - ns Slave mode 1.5 - - ns Master mode 5 - - ns Slave mode 0.5 - - ns tsu(MI) tsu(SI) th(MI) th(SI) 132/205 Data input setup time Data input hold time DS11139 Rev 8 STM32F412xE/G Electrical characteristics Table 65. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 7.5 9 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 7.5 14 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.7 V < VDD < 3.6 V 5.5 - - ns tv(MO) Data output valid time Master mode (after enable edge) - 3 8 ns Master mode (after enable edge) 2 - - ns th(MO) Data output hold time 1. Guaranteed by characterization, not tested in production. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50% Figure 40. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) First bit OUT th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 DS11139 Rev 8 133/205 165 Electrical characteristics STM32F412xE/G Figure 41. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) th(SO) First bit OUT tsu(SI) Next bits OUT tdis(SO) Last bit OUT th(SI) First bit IN MOSI input tr(SCK) Next bits IN Last bit IN MSv41659V1 Figure 42. SPI timing diagram - master mode(1) High NSS input SCK Output SCK Output tc(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INPUT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) BIT1 OUT LSB OUT th(MO) ai14136c 134/205 DS11139 Rev 8 STM32F412xE/G Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 66 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 66. I2S dynamic characteristics(1) Symbol Parameter fMCK I2S Main clock output fCK I2S clock frequency DCK Conditions Min Max Unit 256x8K 256xFs(2) MHz Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 - I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 5 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 2 - th(WS) WS hold time Slave mode 0.5 - Master receiver 0 - Slave receiver 2 - Master receiver 0 - Slave receiver 2.5 - Slave transmitter (after enable edge) - 15 Master transmitter (after enable edge) - 2.5 Slave transmitter (after enable edge) 6 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization, not tested in production. 2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency). Note: Refer to the I2S section of RM0402 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DS11139 Rev 8 135/205 165 Electrical characteristics STM32F412xE/G Figure 43. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit SDreceive LSB LSB transmit th(SD_MR) tsu(SD_MR) receive(2) Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 136/205 DS11139 Rev 8 STM32F412xE/G Electrical characteristics QSPI interface characteristics Unless otherwise specified, the parameters given in the following tables for QSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C=20pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics. Table 67. QSPI dynamic characteristics in SDR mode(1) Symbol fSCK 1/tc(SCK) tw(CKH) Parameter QSPI clock frequency Conditions Min Typ Max Write mode 1.71 V≤VDD≤3.6 V Cload = 15 pF - - 80 Read mode 2.7 V