STM32F427IIT6

STM32F427xx STM32F429xx 32b Arm® Cortex®-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 2 MB of Flash memory organized into two banks allowing read-while-write – Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, Compact Flash/NOR/NAND memories • LCD parallel interface, 8080/6800 modes • LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz) • Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input January 2018 This is information on a product in full production. &"'! LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm) LQFP144 (20 × 20 mm) UFBGA169 (7 × 7 mm) LQFP176 (24 × 24 mm) TFBGA216 (13 x 13 mm) LQFP208 (28 x 28 mm) WLCSP143 • Debug mode – SWD & JTAG interfaces – Cortex-M4 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 90 MHz – Up to 166 5 V-tolerant I/Os • Up to 21 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 6 SPIs (45 Mbits/s), 2 with muxed full-duplex I2S for audio class accuracy via internal audio PLL or external clock – 1 x SAI (serial audio interface) – 2 × CAN (2.0B Active) and SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID DocID024030 Rev 10 1/239 www.st.com STM32F427xx STM32F429xx Table 1. Device summary Reference Part number STM32F427xx STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI, STM32F427II, STM32F427AI STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG, STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI, STM32F429xx STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE, STM32F429NE 2/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 LCD-TFT controller (available only on STM32F429xx) . . . . . . . . . . . . . . 24 3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32 3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 32 3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID024030 Rev 10 3/239 6 Contents STM32F427xx STM32F429xx 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37 3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40 3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41 3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41 3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.36 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.37 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.38 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.40 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.41 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.42 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.1 4/239 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DocID024030 Rev 10 STM32F427xx STM32F429xx Contents 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 98 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 98 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 99 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 127 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 133 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 193 6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 194 6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 196 DocID024030 Rev 10 5/239 6 Contents STM32F427xx STM32F429xx 6.3.30 7 8 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.5 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 7.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 227 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9 6/239 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 228 B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 230 B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DocID024030 Rev 10 STM32F427xx STM32F429xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F427xx and STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 29 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32F427xx and STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 53 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STM32F427xx and STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75 STM32F427xx and STM32F429xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 87 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 97 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 98 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 98 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . 102 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 104 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 105 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 106 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 106 Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 109 Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 110 Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 111 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DocID024030 Rev 10 7/239 9 List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/239 STM32F427xx STM32F429xx PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DocID024030 Rev 10 STM32F427xx STM32F429xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. List of tables Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 199 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 204 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 218 UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 221 TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DocID024030 Rev 10 9/239 9 List of figures STM32F427xx STM32F429xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. 10/239 Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F427xx and STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F427xx and STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 31 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 31 STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F42x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F42x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 107 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 107 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ACCHSI accuracy versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DocID024030 Rev 10 STM32F427xx STM32F429xx Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. List of figures SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 163 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 171 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 174 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 182 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 182 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 184 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 185 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 188 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 188 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 198 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 205 LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 209 DocID024030 Rev 10 11/239 12 List of figures Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. 12/239 STM32F427xx STM32F429xx LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 211 LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 213 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 228 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 229 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 DocID024030 Rev 10 STM32F427xx STM32F429xx 1 Introduction Introduction This datasheet provides the description of the STM32F427xx and STM32F429xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the STM32F4xx reference manual. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214), available from www.st.com. DocID024030 Rev 10 13/239 44 Description 2 STM32F427xx STM32F429xx Description The STM32F427xx and STM32F429xx devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F427xx and STM32F429xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces. • Up to three I2Cs • Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus four UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • One SAI serial audio interface • An SDIO/MMC interface • Ethernet and camera interface • LCD-TFT display controller • Chrom-ART Accelerator™. Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to Table 2: STM32F427xx and STM32F429xx features and peripheral counts for the list of peripherals available on each part number. The STM32F427xx and STM32F429xx devices operates in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F427xx and STM32F429xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. 14/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Description These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. DocID024030 Rev 10 15/239 44 STM32F427 Vx Peripherals Flash memory in Kbytes SRAM in Kbytes 1024 2048 STM32F429Vx 512 1024 2048 STM32F427 Zx 1024 2048 STM32F429Zx STM32F427 STM32F429 STM32F427 Ax Ax Ix 512 1024 2048 1024 2048 System 2048 1024 2048 512 1024 2048 STM32F429Bx STM32F429Nx 512 1024 2048 512 1024 2048 256(112+16+64+64) Backup 4 Yes(1) FMC memory controller Ethernet Timers 1024 STM32F429Ix Description 16/239 Table 2. STM32F427xx and STM32F429xx features and peripheral counts Yes Generalpurpose 10 Advanced -control 2 Basic 2 DocID024030 Rev 10 Random number generator 2 SPI / I S Yes 4/2 (full duplex) (2) 6/2 (full duplex)(2) I2C 3 USART/ UART 4/4 USB OTG Communication FS interfaces USB OTG HS Yes Yes 2 SAI 1 SDIO Yes Camera interface LCD-TFT (STM32F429xx only) Yes No Yes No Yes Chrom-ART Accelerator™ GPIOs 12-bit ADC Number of channels No Yes No Yes Yes 82 114 130 140 3 16 24 168 STM32F427xx STM32F429xx CAN Peripherals STM32F427 Vx STM32F429Vx STM32F427 Zx STM32F429Zx 12-bit DAC Number of channels STM32F429Ix STM32F429Bx STM32F429Nx LQFP208 TFBGA216 Yes 2 Maximum CPU frequency 180 MHz 1.8 to 3.6 V(3) Operating voltage Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Packages STM32F427 STM32F429 STM32F427 Ax Ax Ix Junction temperature: –40 to + 125 °C LQFP100 WLCSP143 LQFP144 UFBGA169 UFBGA176 LQFP176 DocID024030 Rev 10 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. For UFBGA169 package, only SDRAM, NAND and multiplexed static memories are supported. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). STM32F427xx STM32F429xx Table 2. STM32F427xx and STM32F429xx features and peripheral counts (continued) Description 17/239 Description 2.1 STM32F427xx STM32F429xx Full compatibility throughout the family The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F427xx and STM32F429xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F427xx and STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as only a few pins are impacted. Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx, STM32F2xx, and STM32F10xx families. Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package    966    966 966 966      ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ  966 966 966IRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 9''IRU670)[[ 9'' 966 966IRUWKH670)[[ 966IRUWKH670)[[ 966RU1&IRUWKH670)[[ DLG 18/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Description Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 966  ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ      966 966 6LJQDOIURP H[WHUQDOSRZHU VXSSO\ VXSHUYLVRU 1RWSRSXODWHGZKHQŸ UHVLVWRURUVROGHULQJ EULGJHSUHVHQW 3'5B21       966 9'' 966 1RWSRSXODWHGIRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 966IRU670)[[ 966IRUWKH670)[[ 9'' 966 9''IRU670)[[ 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ DLG Figure 3. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages     *1'IRU670)[[ %ͺZ΀ϳ͗Ϭ΁͕>ͺ'΀ϳ͗Ϭ΁͕>ͺ΀ϳ͗Ϭ΁͕ >ͺ,^zE͕>ͺs^zE͕>ͺ͕ >ͺ>< Dͬ &/&K DϮ ϴ^ƚƌĞĂŵƐ &/&K Dϭ ϴ^ƚƌĞĂŵƐ &/&K >Ͳd&d ^ZDϭϭϮ^ 'W/KWKZd' /t' W>^ W/΀ϭϱ͗Ϭ΁ W D /͕sh^͕^K& Λ s  Λ s  &/&K W>>ϭ͕Ϯ͕ϯ 'W/KWKZd h^ Kd'&^ WŽǁĞƌŵĂŶĂŐŵƚ s 'W/KWKZd W΀ϭϱ͗Ϭ΁ ,^zE͕s^zE Wh/y>< dZ΀ϯ͗Ϭ΁ >΀ϯ͗Ϭ΁͕^> EZ^͕E^͕Es Et/dͬE/KZ͕EZ'͕ /EdZ džƚĞƌŶĂůŵĞŵŽƌLJĐŽŶƚƌŽůůĞƌ;&DͿ DĚĂƚĂZDϲϰ