STM32F446RCT6

STM32F446xC/E Arm® Cortex®-M4 32-bit MCU+FPU, 225 DMIPS, up to 512 KB Flash/128+4 KB RAM, USB OTG HS/FS, seventeen TIMs, three ADCs and twenty communication interfaces Datasheet - production data Features  Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions  Memories – 512 Kbytes of Flash memory – 128 Kbytes of SRAM – Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories – Dual mode QuadSPI interface  LCD parallel interface, 8080/6800 modes  Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration  Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM  3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode  2× 12-bit D/A converters  General-purpose DMA: 16-stream DMA controller with FIFOs and burst support  Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter  Debug mode – SWD and JTAG interfaces – Cortex®-M4 Trace Macrocell™ January 2021 This is information on a product in full production. LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 x 20 mm) WLCSP 81 UFBGA144 (7 x 7 mm) UFBGA144 (10 x 10 mm)  Up to 114 I/O ports with interrupt capability – Up to 111 fast I/Os up to 90 MHz – Up to 112 5 V-tolerant I/Os  Up to 20 communication interfaces – SPDIF-Rx – Up to 4× I2C interfaces (SMBus/PMBus) – Up to four USARTs and two UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to four SPIs (45 Mbits/s), three with muxed I2S for audio class accuracy via internal audio PLL or external clock – 2x SAI (serial audio interface) – 2× CAN (2.0B Active) – SDIO interface – Consumer electronics control (CEC) I/F  Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range  8- to 14-bit parallel camera interface up to 54 Mbytes/s  CRC calculation unit  RTC: subsecond accuracy, hardware calendar  96-bit unique ID Table 1. Device summary Reference STM32F446xC/E DS10693 Rev 10 Part numbers STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE. 1/198 www.st.com Contents STM32F446xC/E Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 17 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 2/198 Compatibility with STM32F4 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.16.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 27 3.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 28 3.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DS10693 Rev 10 STM32F446xC/E Contents 3.21.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Universal synchronous/asynchronous receiver transmitters (USART) . . 32 3.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.25 HDMI (high-definition multimedia interface) consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.27 SPDIF-RX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.30 Serial audio interface PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.31 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 35 3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 36 3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 36 3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.36 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.37 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.38 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.39 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.40 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.41 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DS10693 Rev 10 3/198 5 Contents 4/198 STM32F446xC/E 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.2 VCAP_1 / VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 77 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 77 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 78 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 108 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 114 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 168 6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 169 6.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DS10693 Rev 10 STM32F446xC/E 7 8 Contents Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.4 UFBGA144 7 x 7 mm package information . . . . . . . . . . . . . . . . . . . . . . 182 7.5 UFBGA144 10 x 10 mm package information . . . . . . . . . . . . . . . . . . . . 185 7.6 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 193 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 195 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS10693 Rev 10 5/198 5 List of tables STM32F446xC/E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. 6/198 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F446xC/E features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 25 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F446xx pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F446xC/E register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 76 VCAP_1 / VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . 77 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 77 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . . 81 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled with prefetch) or RAM . . . . . . . . . 82 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . 92 Typical current consumption in Sleep mode, regulator ON, VDD = 1.7 V . . . . . . . . . . . . . 93 Typical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 94 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DS10693 Rev 10 STM32F446xC/E Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. List of tables Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PLLSAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ADC dynamic accuracy at fADC = 18 MHz - Limited test conditions . . . . . . . . . . . . . . . . . 141 ADC dynamic accuracy at fADC = 36 MHz - Limited test conditions . . . . . . . . . . . . . . . . . 141 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Asynchronous non-multiplexed SRAM/PSRAM/NOR Read timings. . . . . . . . . . . . . . . . . 150 Asynchronous non-multiplexed SRAM/PSRAM/NOR read  NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 151 Asynchronous non-multiplexed SRAM/PSRAM/NOR write  NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Asynchronous multiplexed PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . 153 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DS10693 Rev 10 7/198 8 List of tables Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. 8/198 STM32F446xC/E Asynchronous multiplexed PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . 155 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 160 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V . . . . . . . . . . . . . . . 171 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 183 UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 186 WLCSP81 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 189 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS10693 Rev 10 STM32F446xC/E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Compatible board for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F446xC/E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F446xC/E and Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 23 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1 / VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1 / VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 27 STM32F446xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32F446xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32F446xC LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F446xC/xE WLCSP81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F446xC/xE UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical VBAT current consumption (RTC ON/backup RAM OFF and LSE in low power mode) . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical VBAT current consumption (RTC ON/backup RAM OFF and LSE in high drive mode). . . . . . . . . . . . . . . . . . . . . . . . . 90 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 136 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DS10693 Rev 10 9/198 10 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. 10/198 STM32F446xC/E ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 143 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 144 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 149 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 151 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 152 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 154 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 160 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 164 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 164 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 178 LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 UFBGA144 7 x 7 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . 184 UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 UFBGA144 10 x 10 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . 187 WLCSP81 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 WLCSP81 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 WLCSP81 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 USB controller configured as peripheral-only and used in full speed mode . . . . . . . . . . . 193 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 193 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 194 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DS10693 Rev 10 STM32F446xC/E 1 Introduction Introduction This document provides the description of the STM32F446xC/E products, based on an Arm®(a) core. It must be read in conjunction with the RM0390 reference manual, available on www.st.com. For information on the Cortex®-M4 core refer to the Cortex®-M4 programming manual (PM0214), available on www.st.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS10693 Rev 10 11/198 38 Description 2 STM32F446xC/E Description The STM32F446xC/E devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a floating point unit (FPU) single precision supporting all Arm® single-precision  data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory up to 512 Kbytes, up to 128 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces.  Up to four I2Cs  Four SPIs, three I2Ss full simplex: to achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization  Four USARTs plus two UARTs  An USB OTG full-speed and an USB OTG high-speed with full-speed capability (with the ULPI), both with dedicated power rails allowing to use them throughout the whole power range  Two CANs  Two SAIs serial audio interfaces: to achieve audio class accuracy, the SAIs can be clocked via a dedicated internal audio PLL  SDIO/MMC interface  Camera interface  HDMI-CEC  SPDIF receiver (SPDIFRx)  QuadSPI Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to Table 2 for the list of peripherals available on each part number. The STM32F446xC/E devices operate in the –40 to +105 °C temperature range from a  1.7 to 3.6 V power supply. The supply voltage can drop down to 1.7 V with the use of an external power supply supervisor (refer to Section 3.16.2: Internal reset OFF). A comprehensive set of  power-saving modes enables the design of low-power applications. The STM32F446xC/E devices offer devices in six packages, ranging from 64 to 144 pins. The set of included peripherals changes with the chosen device. These features make the STM32F446xC/E microcontrollers suitable for a wide range of applications, namely motor drive and control, medical equipment, industrial (PLC, inverters, circuit breakers), printers, and scanners, alarm systems, video intercom and HVAC, and home audio appliances. 12/198 DS10693 Rev 10 STM32F446xC/E Description Table 2. STM32F446xC/E features and peripheral counts STM32 STM32 STM32 STM32 STM32 F446MC F446ME F446RC F446RE F446VC Peripherals Flash memory in Kbytes SRAM in Kbytes 256 512 512 128 (112+16) Backup 4 Advancedcontrol 2 Basic 2 2S I2C 512 4/1 FMP + USART/ UART 4/2 USB OTG FS Yes (6-Endpoints) USB Communication OTG HS interfaces CAN Yes (8-Endpoints) 2 SAI 2 SDIO Yes SPDIF-Rx 1 HDMI-CEC 1 Quad SPI(3) 1 Camera interface Yes 63 50 81 114 16 24 3 14 16 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 180 MHz 1.8 to 3.6 V(4) Operating voltage Packages 256 4/3 (simplex)(2) SPI / I Operating temperatures 512 Yes(1) 10 12-bit ADC Number of channels STM32 F446ZE No Generalpurpose GPIOs STM32 F446ZC 256 System FMC memory controller Timers 256 STM32 F446VE Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C WLCSP81 LQFP64 DS10693 Rev 10 LQFP100 LQFP144 UFBGA144 13/198 38 Description STM32F446xC/E 1. For the LQFP100 package only FMC Bank1 is available, it can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. The interrupt line cannot be used as Port G is not available on this package. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode. 3. For the LQFP64 package the Quad SPI is available with limited features. 4. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.16.2: Internal reset OFF). 2.1 Compatibility with STM32F4 family The STM32F446xC/xV is software and feature compatible with the STM32F4 family. The STM32F446xC/xV can be used as drop-in replacement of the other STM32F4 products but some small changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package STM32F446xx 41 42 43 44 45 46 47 48 49 50 PB11 not available anymore Replaced by V CAP1 58 57 56 55 54 53 52 51 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP1 VSS VDD PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 41 42 43 44 45 46 47 48 49 50 58 57 56 55 54 53 52 51 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP1 VDD STM32F405/STM32F415 line STM32F407/STM32F417 line STM32F427/STM32F437 line STM32F429/STM32F439 line VSS VDD PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS VDD MS33846V2 14/198 DS10693 Rev 10 STM32F446xC/E Description Figure 2. Compatible board for LQFP64 package STM32F446xx 53 52 51 50 49 48 47 VDD VCAP2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PB11 not available anymore 36 Replaced by VCAP1 35 34 33 28 29 30 31 32 VDD VSS VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD VSS PB2 PB10 VCAP1 VSS VDD PB11 VCAP1 VDD PB2 PB10 46 45 44 43 42 41 40 39 38 37 36 35 34 33 28 29 30 31 32 PC12 PC11 PC10 PA15 PA14 PC12 PC11 PC10 PA15 PA14 STM32F405/STM32F415 line VCAP increased to 4.7 μF ESR 1 Ω or below VSS VDD VSS VDD MS33845V2 Figure 3 shows the STM32F446xx block diagram. DS10693 Rev 10 15/198 38 Description STM32F446xC/E Figure 3. STM32F446xC/E block diagram MPU FPU USB OTG HS DMA/ FIFO ID, VBUS 8 Streams GP-DMA2 FIFO FLASH 512kB SRAM1 112KB SRAM2 16KB AHB2 180MHz 8 Streams USB OTG FS POR AHB1 180MHz FIFO CAMERA ITF SUPPLY SUPERVISION POR/PDR/ BOR Reset Int @VDDA GPIO PORT USART 2MBpsD PE(15:0) GPIO PORT E USART 2MBps PF(15:0) GPIO PORT F USART 2MBps PG(15:0) GPIO PORT G USART 2MBps RESET& CLOCK MANAGT CTRL PH(1 :0) GPIO PORT H USART 2MBps LS USART TIMER 82MBps / PWM 2 CH as AF 16b WinWATCHDOG smcard USART USART 2MBps 1 irDA 6 MOSI, MISO SCK, NSS as AF SPI1/I2S USART 2MBps MOSI, MISO SCK, NSS as AF USARTSPI 2MBps 4 SD, SCK, FS MCLK as AF USARTSAI 2MBps 1 FIFO smcard USART USART 2MBps irDA 2 USARTSAI 2MBps SD, SCK, FS MCLK as AF VDDREF_ADC 8 AIN common to the 3 ADCs 8 AIN common to the ADC1 & 2 8 AIN to ADC3 4 CH, ETR as AF 4 CH a s AF TIMER12 16b 2 CH as AF 16b 1 CH as AF TIMER6 TIMER7 16b 16b USART2 USART3 smcard irDA ADC1 RX, TX as AF UART5 RX, TX as AF SPDIF SPDIF_RX[3:0] as AF HDMI-CEC HDMI_CEC a s AF SPI2/I2S MOSI, MISO, SCK NSS/WS, MCK as AF SPI3/I2S MOSI, MISO, SCK NSS/WS, MCK as AF ADC 3 DAC1 DAC2 FMPI2C1 SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SM BAL as AF ITF bxCAN1 bxCAN2 DAC1 as AF SCL, SDA, SMBAL as AF I2C1/SMBUS I2C3/SMBUS @VDDA IF RX, TX, SCK, CTS, RTS as AF RX, TX, SCK CTS, RTS as AF UART4 I2C2/SMBUS USART 2MBps TEMP SENSOR 1 CH as AF smcard irDA @VDDA ADC2 4 CH, ETR as AF TIMER5 32b 16b FIFO RX, TX, SCK, CTS, RTS as AF 4 CH, ETR as AF TIMER3 16b TIMER14 16b 16b OSC32_IN OSC32_OUT TIMER2 32b TIMER13 TIMER11 USART 2MBps OSCIN OSCOUT 4KB BKPRAM 16b TIMER10 USART 2MBps 1 CH as AF RX, TX, SCK, CTS, RTS as AF AHB/APB2 AHB/APB1 TIMER USART92MBps 1 CH as AF V DD =1.8 to 3.6V VSS VCAP ALARM_OUT STAMP1 STAMP2 AWU BKP REG TIMER4 16b A PB1 45 MHz 4 PWM, 4 PWM, ETR, BKIN as AF XTAL 32kHz RTC 16b TIMER 12MBps / PWM USART VDDA , VSSA VBAT =1.8 to 3.6V @VBAT APB2 90 MHz 4 PWM, 4 PWM, ETR, BKIN as AF SDIO / MMC VDDUSB = 3.3 TO 3.6 V D+, DID, VBUS WDG32K GPDMA1 APB2 60MHz D(7:0) CMD, CK as AF GPDMA2 EXT IT. WKUP USART 2MBps @VDD Standby interface CRC FIFO 114 AF VOLT. REG. 3.3V TO 1.2V XTAL OSC 4-16MHz LS GPIO PORT C USART 2MBps PD(15:0) @VDDA POWER MNGT PLL1+PLL2+PLL3 GPIO PORT B USART 2MBps PC(15:0) RC HS RC LS PWRCTL PB(15:0) GPIO PORT A USART 2MBps FCLK H CLK APBP2 CLK APBP1 CLK AHB2PCLK AH B1PCLK PA(15:0) HSYNC, VSYNC PIXCK, D(13:0) NRESET PVD Dig. Filter GP-DMA1 CLK, CSa, CSb, D[7:0] QuadSPI FIFO VDDUSB = 3.3 TO 3.6 V D+, DULPI : CLK, D(7:0), DIR, STP, NXT PHY S-BUS PHY I-BUS D-BUS FIFO ARM CORTEX M4 180MHz CLK, NE[3:0], A[23:0], D[31:0] NOEN, NWEN, NBL[1:0] SDCLKE[1:0], SDNE[1:0] NRAS, NCAS, NADV NWAIT, INTN EXT MEM CTL (FMC) SRAM,PSRAM,NOR-FLASH NAND-FLASH, SDRAM FIFO NVIC AHB_EMI ETM FLASH I/F TRACECK TRACED(3:0) JTAG & SW AHB BUS MATRIX 7S8M JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO TX, RX TX, RX DAC2 as AF MS33840V3 16/198 DS10693 Rev 10 STM32F446xC/E Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F446xC/E family is compatible with all Arm tools and software. Figure 3 shows the general block diagram of the STM32F446xC/E family. Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS10693 Rev 10 17/198 38 Functional overview 3.4 STM32F446xC/E Embedded Flash memory The devices embed a Flash memory of 512KB available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All devices embed:  Up to 128 Kbytes of system SRAM RAM is accessed (read/write) at CPU clock speed with 0 wait states.  4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT modes. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves Flash memory, RAM, QuadSPI, FMC, AHB and APB peripherals and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 18/198 DS10693 Rev 10 STM32F446xC/E Functional overview Figure 4. STM32F446xC/E and Multi-AHB matrix S1 S3 S4 S5 USB_HS_M USB OTG HS DMA_P2 DMA_MEM2 GP DMA2 DMA_MEM1 DMA_PI S-bus S2 GP DMA1 S6 ICODE DCODE ACCEL S0 D-bus I-bus ARM Cortex-M4 Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB2 peripherals APB1 AHB1 peripherals APB2 FMC external MemCtl/QuadSPI Bus matrix-S MS33842V1 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. DS10693 Rev 10 19/198 38 Functional overview STM32F446xC/E The DMA can be used with the main peripherals: 3.9  SPI and I2S  I2C  USART  General-purpose, basic and advanced-control timers TIMx  DAC  SDIO  Camera interface (DCMI)  ADC  SAI1/SAI2  SPDIF Receiver (SPDIFRx)  QuadSPI Flexible memory controller (FMC) All devices embed an FMC. It has seven Chip Select outputs supporting the following modes: SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. With the possibility to remap FMC bank 1 (NOR/PSRAM 1 and 2) and FMC SDRAM bank 1/2 in the Cortex-M4 code area. Functionality overview:  8-,16-bit data bus width  Read FIFO for SDRAM controller  Write FIFO  Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 Quad SPI memory interface (QUADSPI) All devices embed a Quad SPI memory interface, which is a specialized communication interface targeting Single, Dual or Quad SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access. Code execution is supported. The opcode and the frame format are fully programmable. Communication can be either in Single Data Rate or Dual Data Rate. 20/198 DS10693 Rev 10 STM32F446xC/E 3.11 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core.  Closely coupled NVIC gives low-latency interrupt processing  Interrupt entry vector table address passed directly to the core  Early processing of interrupts  Processing of late arriving, higher-priority interrupts  Supports tail chaining  Processor state automatically saved  Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.12 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 3.13 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz. The devices embed a dedicated PLL (PLLI2S) and PLLSAI, which makes it possible to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 to 192 kHz. DS10693 Rev 10 21/198 38 Functional overview 3.14 STM32F446xC/E Boot modes At startup, boot pins are used to select one out of three boot options:  Boot from user Flash  Boot from system memory  Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial (UART, I2C, CAN, SPI and USB) communication interface. Refer to application note AN2606 for details. 3.15 Note: Power supply schemes  VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.  VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2). Refer to Table 3 to identify the packages supporting this option.  VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.  VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6 V) for USB transceivers.  For example, when device is powered at 1.8 V, an independent power supply 3.3 V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions must be respected: – During power-on phase (VDD < VDD_MIN), VDDUSB must be always lower than VDD – During power-down phase (VDD < VDD_MIN), VDDUSB must be always lower than VDD – VDDUSB rising and falling time rate specifications must be respected. – In operating mode phase, VDDUSB can be lower or higher than VDD: – If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB supplies both USB transceivers (USB OTG_HS and USB OTG_FS). – If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. – If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. 22/198 DS10693 Rev 10 STM32F446xC/E Functional overview Figure 5. VDDUSB connected to an external independent power supply VDDUSB_MAX USB functional area VDDUSB VDDUSB_MIN USB non functional area VDD = VDDA Power-on Operating mode USB non functional area VDD_MIN Power-down time MS37590V1 3.16 Power supply supervisor 3.16.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.16.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be connected to VSS, to let the device operate down to 1.7 V. Refer to Figure 6. DS10693 Rev 10 23/198 38 Functional overview STM32F446xC/E Figure 6. Power supply supervisor interconnection with internal reset OFF VDD STM32F446x Application reset signal (optional) VBAT PDR_ON PDR not active: 1.7 V < VDD < 3.6 V VSS MS33844V2 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V. A comprehensive set of power-saving mode enables the design low-power applications. When the internal reset is OFF, the following integrated features are no more supported:  The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled  The brownout reset (BOR) circuitry must be disabled  The embedded programmable voltage detector (PVD) is disabled  VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100/LQFP64, allow to disable the internal reset through the PDR_ON signal. 3.17 Voltage regulator The regulator has four operating modes:   3.17.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON:  MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 24/198 DS10693 Rev 10 STM32F446xC/E Functional overview The over-drive mode makes possible operating at a frequency higher than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode).  LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode:  – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.17.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode enables to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. DS10693 Rev 10 25/198 38 Functional overview STM32F446xC/E In regulator OFF mode, the following features are no more supported:  PA0 cannot be used as a GPIO pin since it resets a part of the V12 logic power domain not reset by the NRST pin.  As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.  The over-drive and under-drive modes are not available. Figure 7. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor Ext. reset controller active signal (optional) when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V3 The following conditions must be respected: Note: 26/198  VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.  If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 8).  Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 9).  If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DS10693 Rev 10 STM32F446xC/E Functional overview Figure 8. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1 / VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V V12 Min V12 VCAP_1 / VCAP_2 time NRST time ai18491f 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1 / VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492e 1. This figure is valid whatever the internal reset mode (ON or OFF). 3.17.3 Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON LQFP64 / LQFP100 Yes No LQFP144 Yes No Yes BYPASS_REG set to Vss Yes BYPASS_REG set to VDD UFBGA144 WLCSP81 Regulator OFF Internal reset ON Internal reset OFF DS10693 Rev 10 Yes No Yes PDR_ON set to VDD Yes PDR_ON set to Vss 27/198 38 Functional overview 3.18 STM32F446xC/E Real-time clock (RTC), backup SRAM and backup registers The backup domain includes:  The real-time clock (RTC)  4 Kbytes of backup SRAM  20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and enables automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.19). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.19). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 28/198 DS10693 Rev 10 STM32F446xC/E 3.19 Functional overview Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:  Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.  Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5): – Normal mode (default mode when MR or LPR is enabled) – Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup). Table 5. Voltage regulator modes in stop mode  Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 3.20 VBAT operation The VBAT pin makes it possible to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. DS10693 Rev 10 29/198 38 Functional overview Note: STM32F446xC/E When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin has to be connected to VDD. 3.21 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. Table 6. Timer feature comparison Timer type Advancedcontrol General purpose Basic Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary output Max interface clock (MHz) Max timer clock (MHz)(1) TIM1, TIM8 16-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 Yes 90 180 TIM2, TIM5 32-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 No 45 90/180 TIM3, TIM4 16-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 No 45 90/180 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 90 180 TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 90 180 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 45 90/180 TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 45 90/180 TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 45 90/180 1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 30/198 DS10693 Rev 10 STM32F446xC/E 3.21.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for:  Input capture  Output compare  PWM generation (edge- or center-aligned modes)  One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.21.2 General-purpose timers (TIMx) There are ten synchronized general-purpose timers embedded in the STM32F446xC/E devices (see Table 6 for differences).  TIM2, TIM3, TIM4, TIM5 The STM32F446xC/E include four full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from one to four Hall-effect sensors.  TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.21.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. DS10693 Rev 10 31/198 38 Functional overview 3.21.4 STM32F446xC/E Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.21.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.21.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.22  A 24-bit downcounter  Autoreload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source. Inter-integrated circuit interface (I2C) Four I²C bus interfaces can operate in multimaster and slave modes. Three I²C can support the standard (up to 100 KHz) and fast (up to 400 KHz) modes. One I²C can support the standard (up to 100 KHz), fast (up to 400 KHz) and fast mode plus (up to 1MHz) modes. They (all I²C) support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0 / PMBus. The devices also include programmable analog and digital noise filters (see Table 7). Table 7. Comparison of I2C analog and digital filters - Pulse width of suppressed spikes 3.23 Analog filter  50 ns Digital filter Programmable length from 1 to 15 I2C peripheral clocks Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, and UART5). 32/198 DS10693 Rev 10 STM32F446xC/E Functional overview These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 8. USART feature comparison(1) USART name Max. baud rate in Mbit/s Smartcard SPI Standard Modem irDA LIN (ISO 7816) Oversampling Oversampling master features (RTS/CTS) by 16 by 8 USART1 X X X X X X 5.62 11.25 USART2 X X X X X X 2.81 5.62 USART3 X X X X X X 2.81 5.62 UART4 X X X - X - 2.81 5.62 UART5 X X X - X - 2.81 5.62 USART6 X X X X X X 5.62 11.25 APB mapping APB2 (max. 90 MHz) APB1 (max. 45 MHz) APB2 (max. 90 MHz) 1. X = feature supported. 3.24 Serial peripheral interface (SPI) The devices feature up to four SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, and SPI4 can communicate at up to 45 Mbits/s, SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives eight master mode frequencies and the frame is configurable to 8- or 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 3.25 HDMI (high-definition multimedia interface) consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. DS10693 Rev 10 33/198 38 Functional overview 3.26 STM32F446xC/E Inter-integrated sound (I2S) Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 3.27 SPDIF-RX Receiver Interface (SPDIFRX) The SPDIF-RX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main features of the SPDIF-RX are the following:  Up to 4 inputs available  Automatic symbol rate detection  Maximum symbol rate: 12.288 MHz  Stereo stream from 32 to 192 kHz supported  Supports Audio IEC-60958 and IEC-61937, consumer applications  Parity bit management  Communication using DMA for audio samples  Communication using DMA for control and user channel information  Interrupt capabilities The SPDIF-RX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available the SPDIF-RX re-samples the incoming signal, decodes the Manchester stream, recognizes frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF sub-frame rate used to compute the exact sample rate for clock drift algorithms. 3.28 Serial audio interface (SAI) The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio interfaces based on two independent audio sub blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub blocks can be configured in master or in slave mode. The SAIs use a PLL to achieve audio class accuracy. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. 34/198 DS10693 Rev 10 STM32F446xC/E Functional overview The two sub blocks can be configured in synchronous mode when full-duplex mode is required. SAI1 and SA2 can be served by the DMA controller. 3.29 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications, to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.30 Serial audio interface PLL (PLLSAI) An additional PLL dedicated to audio and USB is used for SAI1 and SAI2 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the 48 MHz clock for USB FS and SDIO in case the system PLL is programmed with factors not multiple of 48 MHz. 3.31 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface enables data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 3.32 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. DS10693 Rev 10 35/198 38 Functional overview 3.33 STM32F446xC/E Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power rails allowing its use throughout the entire power range. The major features are: 3.34  Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing  Supports the session request protocol (SRP) and host negotiation protocol (HNP)  6 bidirectional endpoints  12 host channels with periodic OUT support  HNP/SNP/IP inside (no need for any external resistor)  For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power rails allowing its use throughout the entire power range. The major features are: 36/198  Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing  Supports the session request protocol (SRP) and host negotiation protocol (HNP)  8 bidirectional endpoints  16 host channels with periodic OUT support  Internal FS OTG PHY support  External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.  Internal USB DMA  HNP/SNP/IP inside (no need for any external resistor)  for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DS10693 Rev 10 STM32F446xC/E 3.35 Functional overview Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 94.5 Mbyte/s (in 14-bit mode) at 54 MHz. Its features: 3.36  Programmable polarity for the input pixel clock and synchronization signals  Parallel data communication can be 8-, 10-, 12- or 14-bit  Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)  Supports continuous mode or snapshot (a single frame) mode  Capability to automatically crop the image black and white. General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 90 MHz. 3.37 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:  Simultaneous sample and hold  Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature makes possible a very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 3.38 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. DS10693 Rev 10 37/198 38 Functional overview STM32F446xC/E As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.39 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features:  two DAC converters: one for each output channel  8-bit or 10-bit monotonic output  left or right data alignment in 12-bit mode  synchronized update capability  noise-wave generation  triangular-wave generation  dual DAC channel independent or simultaneous conversions  DMA capability for each channel  external triggers for conversion  input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.40 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.41 Embedded Trace Macrocell™ The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F446xx through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 38/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA/VREFVDDA/VREF+ PA0 PA1 PA2 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VSS VDD Figure 10. STM32F446xC/xE LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 VCAP_1 VSS VDD 4 Pinout and pin description MS31149V3 1. The above figure shows the package top view. DS10693 Rev 10 39/198 64 Pinout and pin description STM32F446xC/E 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 11. STM32F446xC/xE LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP_1 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VDD VSSA/VREFVREF+ VDDA PA0 PA1 PA2 MS31151V4 1. The above figure shows the package top view. 40/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 V DD V SS V CAP_2 PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 V DDUSB V SS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 V DD V SS PD13 PD12 PD11 PD10 PD9 PD8 PB 15 PB 14 PB 13 PB 12 V CAP_1 V DD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 V REF+ V DDA PA 0 PA 1 PA 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PA 3 V SS V DD PA 4 PA 5 PA 6 PA 7 PC4 PC5 PB 0 PB 1 PB 2 PF11 PF12 V SS V DD PF13 PF14 PF15 PG0 PG1 PE 7 PE 8 PE 9 V SS V DD PE 10 PE 11 PE 12 PE 13 PE 14 PE 15 PB 10 PB 11 PE 2 PE 3 PE 4 PE 5 PE 6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 V SS V DD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NR ST PC0 PC1 PC2 PC3 V DD V SSA 109 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 V DD PDR_ON PE 1 PE 0 PB 9 PB 8 BOO T0 PB 7 PB 6 PB 5 PB 4 PB 3 PG15 V DD V SS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 V DD V SS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA 15 PA 14 Figure 12. STM32F446xC LQFP144 pinout ai18496c 1. The above figure shows the package top view. DS10693 Rev 10 41/198 64 Pinout and pin description STM32F446xC/E Figure 13. STM32F446xC/xE WLCSP81 ballout 1 2 3 4 5 6 7 8 9 A VDD PC12 PD4 PD7 PB3 PB5 BOOT0 VDD PE4 B VSS PA15 PD0 PD6 PB4 PB7 VSS PDR_ ON VBAT C PA11 VCAP_2 PA14 PD1 PB6 PB8 PB9 PC13 PC14 D PC9 PA13 PC10 PC11 PD2 PE3 PE2 NRESET PC15 E VDD USB PA8 PA10 PA12 PA7 PA3 PA2 PC2 PH0 F PC6 PC7 PC8 PA9 PB0 PA5 VSSA PC3 PH1 G PD13 PD12 PB15 PB12 PE9 PA6 PA1 VSS PC0 H PD11 PB13 VSS PB10 PE8 PB1 PA4 VDDA VDD J PB14 VDD VCAP_1 PE10 PE7 PB2 PC4 BYPASS_ REG PA0 MSv33518V2 1. The above figure shows the package top view. 42/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description Figure 14. STM32F446xC/xE UFBGA144 ballout 1 2 3 4 5 6 7 8 9 10 11 12 A PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13 B PC14 PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PAI2 C PC15 VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 VDD USB PA11 D PH0 VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E PH1 PF3 PF4 PF5 PDR_ ON VSS VSS PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7 G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP_2 VSS PG8 PC6 H PC0 PC1 PC2 PC3 BYPASS _REG VSS VCAP_1 PE11 PD11 PG7 PG6 PG5 J VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 MSv36519V2 1. The above picture shows the package top view. DS10693 Rev 10 43/198 64 Pinout and pin description STM32F446xC/E Table 9. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5V tolerant IO, I2C FM+ option TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with weak pull-up resistor Pin type I/O structure Notes Definition Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 10. STM32F446xx pin and ball descriptions D7 A3 1 PE2 I/O FT - - 2 D6 A2 2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - - 3 A9 B2 3 PE4 I/O FT - TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT - - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, EVENTOUT - - 4 44/198 - B3 LQFP144 1 WLCSP 81 - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type UFBGA144 Pin number 4 Pin name (function after reset) PE5 I/O FT DS10693 Rev 10 Additional functions - STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) - B4 5 PE6 I/O FT - 1 6 B9 C2 6 VBAT S - - - - 2 7 C8 A1 7 PC13 I/O FT - EVENTOUT TAMP_1/WKUP1 3 8 C9 B1 8 PC14OSC32_IN(PC14) I/O FT - EVENTOUT OSC32_IN 4 9 D9 C1 9 PC15OSC32_OUT(PC15) I/O FT - EVENTOUT OSC32_OUT - - - C3 10 PF0 I/O FT - I2C2_SDA, FMC_A0, EVENTOUT - - - - C4 11 PF1 I/O FT - I2C2_SCL, FMC_A1, EVENTOUT - - - - D4 12 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - E2 13 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - - E3 14 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - - E4 15 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 - 10 - D2 16 VSS S - - - - - 11 - D3 17 VDD S - - - - - - - F3 18 PF6 I/O FT - TIM10_CH1, SAI1_SD_B, QUADSPI_BK1_IO3, EVENTOUT ADC3_IN4 ADC3_IN5 LQFP144 5 WLCSP 81 - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type UFBGA144 Pin number Pin name (function after reset) Additional functions - - - - F2 19 PF7 I/O FT - TIM11_CH1, SAI1_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT - - - G3 20 PF8 I/O FT - SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 - - - G2 21 PF9 I/O FT - SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_IN7 - - - G1 22 PF10 I/O FT - DCMI_D11, EVENTOUT ADC3_IN8 5 12 E9 D1 23 PH0-OSC_IN(PH0) I/O FT - EVENTOUT OSC_IN DS10693 Rev 10 45/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) UFBGA144 LQFP144 13 F9 E1 24 PH1OSC_OUT(PH1) 7 14 D8 F1 25 NRST 8 15 G9 H1 26 PC0 Notes WLCSP 81 6 I/O structure LQFP100 I/O LQFP64 Pin name (function after reset) Pin type Pin number Alternate functions Additional functions FT - EVENTOUT OSC_OUT - - - - SAI1_MCLK_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC123_IN10 ADC123_IN11 I/O RST I/O FT 9 16 - H2 27 PC1 I/O FT - SPI3_MOSI/I2S3_SD, SAI1_SD_A, SPI2_MOSI/I2S2_SD, EVENTOUT 10 17 E8 H3 28 PC2 I/O FT - SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT ADC123_IN12 ADC123_IN13 11 18 F8 H4 29 PC3 I/O FT - SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT - 19 H9 - 30 VDD S - - - - - - G8 - - VSS S - - - - 12 20 F7 J1 31 VSSA S - - - - - - - K1 - VREF- S - - - - - 21 - L1 32 VREF+ S - - - - 13 22 H8 M1 33 VDDA S - - - - - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, EVENTOUT ADC123_IN0, WKUP0/TAMP_2 ADC123_IN1 ADC123_IN2 14 23 J9 J2 34 PA0-WKUP(PA0) I/O FT 15 24 G7 K2 35 PA1 I/O FT - TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, EVENTOUT 16 25 E7 L2 36 PA2 I/O FT - TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, EVENTOUT 46/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) E6 M2 37 PA3 I/O FT - 18 27 - G4 38 VSS S - - - - - - J8 H5 - BYPASS_REG I FT - - - 19 28 - F4 39 VDD S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, EVENTOUT ADC12_IN4, DAC_OUT1 - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT ADC12_IN5, DAC_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, DCMI_PIXCLK, EVENTOUT ADC12_IN6 ADC12_IN7 20 21 22 29 30 31 H7 F6 G6 J3 K3 L3 LQFP144 26 WLCSP 81 17 TIM2_CH4, TIM5_CH4, TIM9_CH2, SAI1_FS_A, USART2_RX, OTG_HS_ULPI_D0, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type UFBGA144 Pin number 40 41 42 Pin name (function after reset) PA4 PA5 PA6 I/O TTa I/O TTa I/O FT Additional functions ADC123_IN3 23 32 E5 M3 43 PA7 I/O FT - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, FMC_SDNWE, EVENTOUT 24 33 J7 J4 44 PC4 I/O FT - I2S1_MCK, SPDIFRX_IN2, FMC_SDNE0, EVENTOUT ADC12_IN14 - USART3_RX, SPDIFRX_IN3, FMC_SDCKE0, EVENTOUT ADC12_IN15 25 34 - K4 45 PC5 I/O FT DS10693 Rev 10 47/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) 27 35 36 H6 L4 M4 46 47 PB0 PB1 I/O I/O I/O structure Pin type LQFP144 UFBGA144 WLCSP 81 F5 Pin name (function after reset) FT FT Notes 26 LQFP100 LQFP64 Pin number Alternate functions Additional functions - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUT ADC12_IN8 - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, SDIO_D2, EVENTOUT ADC12_IN9 - 28 37 J6 J5 48 PB2-BOOT1 (PB2) I/O FT - TIM2_CH4, SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, OTG_HS_ULPI_D4, SDIO_CK, EVENTOUT - - - M5 49 PF11 I/O FT - SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT - - - - L5 50 PF12 I/O FT - FMC_A6, EVENTOUT - - - - - 51 VSS S - - - - - - - G5 52 VDD S - - - - - - - K5 53 PF13 I/O FT - FMPI2C1_SMBA, FMC_A7, EVENTOUT - - - - M6 54 PF14 I/O FTf - FMPI2C1_SCL, FMC_A8, EVENTOUT - - - - L6 55 PF15 I/O FTf - FMPI2C1_SDA, FMC_A9, EVENTOUT - - - - K6 56 PG0 I/O FT - FMC_A10, EVENTOUT - - - - J6 57 PG1 I/O FT - FMC_A11, EVENTOUT - - 38 J5 M7 58 PE7 I/O FT - TIM1_ETR, UART5_RX, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT - - 39 H5 L7 59 PE8 I/O FT - TIM1_CH1N, UART5_TX, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT - - 40 G5 K7 60 PE9 I/O FT - TIM1_CH1, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - 48/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) LQFP64 LQFP100 WLCSP 81 UFBGA144 LQFP144 Pin name (function after reset) Pin type I/O structure Notes Pin number Alternate functions - - - H6 61 VSS S - - - - - - - G6 62 VDD S - - - - - 41 J4 J7 63 PE10 I/O FT - TIM1_CH2N, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT - - 42 - H8 64 PE11 I/O FT - TIM1_CH2, SPI4_NSS, SAI2_SD_B, FMC_D8, EVENTOUT - - 43 - J8 65 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9, EVENTOUT - - 44 - K8 66 PE13 I/O FT - TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10, EVENTOUT - - 45 - L8 67 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11, EVENTOUT - - 46 - M8 68 PE15 I/O FT - TIM1_BKIN, FMC_D12, EVENTOUT - - Additional functions 29 47 H4 M9 69 PB10 I/O FT - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - - - M10 70 PB11 I/O FT - TIM2_CH4, I2C2_SDA, USART3_RX, SAI2_SD_A, EVENTOUT - 30 48 J3 H7 71 VCAP_1 S - - - - 31 49 H3 - - VSS S - - - - 32 50 J2 G7 72 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - 33 51 G4 M11 73 PB12 I/O FT DS10693 Rev 10 49/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) 35 52 53 J1 M12 L11 74 75 PB13 PB14(1) I/O I/O I/O structure Pin type LQFP144 UFBGA144 WLCSP 81 H2 Pin name (function after reset) FT FT Notes 34 LQFP100 LQFP64 Pin number Alternate functions Additional functions - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT OTG_HS_VBUS - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT - - 36 54 G3 L12 76 PB15(1) I/O FT - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT - 55 - L9 77 PD8 I/O FT - USART3_TX, SPDIFRX_IN1, FMC_D13, EVENTOUT - - 56 - K9 78 PD9 I/O FT - USART3_RX, FMC_D14, EVENTOUT - - 57 - J9 79 PD10 I/O FT - USART3_CK, FMC_D15, EVENTOUT - - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT - - TIM4_CH1, FMPI2C1_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT - - - - 58 59 H1 G2 H9 L10 80 81 PD11 PD12 I/O I/O FT FTf - 60 G1 K10 82 PD13 I/O FTf - TIM4_CH2, FMPI2C1_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - - - G8 83 VSS S - - - - - - - F8 84 VDD S - - - - 50/198 DS10693 Rev 10 STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) - K11 85 PD14 I/O FTf - - 62 - K12 86 PD15 I/O FTf - TIM4_CH4, FMPI2C1_SDA, FMC_D1, EVENTOUT - - - - J12 87 PG2 I/O FT - FMC_A12, EVENTOUT - - - - J11 88 PG3 I/O FT - FMC_A13, EVENTOUT - - - - J10 89 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - - H12 90 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - - H11 91 PG6 I/O FT - QUADSPI_BK1_NCS, DCMI_D12, EVENTOUT - - - - H10 92 PG7 I/O FT - USART6_CK, FMC_INT, DCMI_D13, EVENTOUT - - - - G11 93 PG8 I/O FT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT - - - - - 94 VSS S - - - - - - - F10 - VDD S - - - - - - E1 C11 95 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, FMPI2C1_SCL, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, EVENTOUT - - TIM3_CH2, TIM8_CH2, FMPI2C1_SDA, SPI2_SCK/I2S2_CK, I2S3_MCK, SPDIFRX_IN1, USART6_RX, SDIO_D7, DCMI_D1, EVENTOUT - - TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT - 37 38 39 63 64 65 F1 F2 F3 G12 F12 F11 LQFP144 61 WLCSP 81 - TIM4_CH3, FMPI2C1_SCL, SAI2_SCK_A, FMC_D0, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type UFBGA144 Pin number 96 97 98 Pin name (function after reset) PC6 PC7 PC8 I/O I/O I/O FTf FTf FT DS10693 Rev 10 Additional functions - 51/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) 41 66 67 E2 E11 E12 99 100 PC9 PA8 I/O I/O I/O structure Pin type LQFP144 UFBGA144 WLCSP 81 D1 Pin name (function after reset) FT FT Notes 40 LQFP100 LQFP64 Pin number Alternate functions Additional functions - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, EVENTOUT - - MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT - OTG_FS_VBUS 42 68 F4 D12 101 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, SAI1_SD_B, USART1_TX, DCMI_D0, EVENTOUT 43 69 E3 D11 PA10 I/O FT - TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1, EVENTOUT - 44 70 C1 C12 103 PA11(1) I/O FT - TIM1_CH4, USART1_CTS, CAN1_RX, OTG_FS_DM, EVENTOUT - 45 71 E4 B12 104 PA12(1) I/O FT - TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, EVENTOUT - 46 72 D2 A12 105 PA13(JTMS-SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - - 73 C2 G9 106 47 74 B1 G10 107 48 75 A1 F9 108 49 76 C3 A11 109 PA14(JTCK-SWCLK) I/O 50 77 52/198 B2 A10 102 110 VCAP_2 S - - - - VSS S - - - - VDD S - - - - FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT - PA15(JTDI) I/O FT DS10693 Rev 10 STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) 52 53 78 79 80 D4 A2 B11 B10 C10 111 112 113 PC10 PC11 PC12 I/O I/O I/O I/O structure Pin type LQFP144 UFBGA144 WLCSP 81 D3 Pin name (function after reset) FT FT FT Notes 51 LQFP100 LQFP64 Pin number Alternate functions Additional functions - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, EVENTOUT - - SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, EVENTOUT - - I2C2_SDA, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT - - - 81 B3 E10 114 PD0 I/O FT - SPI4_MISO, SPI3_MOSI/I2S3_SD, CAN1_RX, FMC_D2, EVENTOUT - 82 C4 D10 115 PD1 I/O FT - SPI2_NSS/I2S2_WS, CAN1_TX, FMC_D3, EVENTOUT - 54 83 D5 E9 116 PD2 I/O FT - TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT - - - 84 - D9 117 PD3 I/O FT - TRACED1, SPI2_SCK/I2S2_CK, USART2_CTS, QUADSPI_CLK, FMC_CLK, DCMI_D5, EVENTOUT - 85 A3 C9 118 PD4 I/O FT - USART2_RTS, FMC_NOE, EVENTOUT - - 86 - B9 119 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - - E7 120 VSS S - - - - - - - F7 121 VDD S - - - - DS10693 Rev 10 53/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) B4 A8 122 PD6 I/O FT - - 88 A4 A9 123 PD7 I/O FT - USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT - - LQFP144 87 WLCSP 81 - SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type UFBGA144 Pin number Pin name (function after reset) Additional functions - - - - E8 124 PG9 I/O FT - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT - - - D8 125 PG10 I/O FT - SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT - - - - C8 126 PG11 I/O FT - SPI4_SCK, SPDIFRX_IN0, DCMI_D3, EVENTOUT - - - - - B8 127 PG12 I/O FT - SPI4_MISO, SPDIFRX_IN1, USART6_RTS, FMC_NE4, EVENTOUT - - - D7 128 PG13 I/O FT - TRACED2, SPI4_MOSI, USART6_CTS, FMC_A24, EVENTOUT - - - - - C7 129 PG14 I/O FT - TRACED3, SPI4_NSS, USART6_TX, QUADSPI_BK2_IO3, FMC_A25, EVENTOUT - - - - 130 VSS S - - - - - - - F6 131 VDD S - - - - - - - B7 132 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, EVENTOUT - 55 89 54/198 A5 A7 133 PB3(JTDO/TRACES WO) I/O FT DS10693 Rev 10 STM32F446xC/E Pinout and pin description Table 10. STM32F446xx pin and ball descriptions (continued) 57 58 90 91 92 A6 C5 A6 B6 C6 134 135 136 PB4(NJTRST) PB5 PB6 I/O I/O I/O I/O structure Pin type LQFP144 UFBGA144 WLCSP 81 B5 Pin name (function after reset) FT FT FT Notes 56 LQFP100 LQFP64 Pin number Alternate functions Additional functions - NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, EVENTOUT - - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT - - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT - - 59 93 B6 D6 137 PB7 I/O FT - TIM4_CH2, I2C1_SDA, USART1_RX, SPDIFRX_IN0, FMC_NL, DCMI_VSYNC, EVENTOUT 60 94 A7 D5 138 BOOT0 I B - - VPP - TIM2_CH1/TIM2_ETR, TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDIO_D4, DCMI_D6, EVENTOUT - - TIM2_CH2, TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, SAI1_FS_B, CAN1_TX, SDIO_D5, DCMI_D7, EVENTOUT - - - 61 62 95 96 C6 C7 C5 B5 139 140 PB8 PB9 I/O I/O FT FT - 97 - A5 141 PE0 I/O FT - TIM4_ETR, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT - 98 - A4 142 PE1 I/O FT - FMC_NBL1, DCMI_D3, EVENTOUT DS10693 Rev 10 55/198 64 Pinout and pin description STM32F446xC/E Table 10. STM32F446xx pin and ball descriptions (continued) LQFP64 LQFP100 WLCSP 81 UFBGA144 LQFP144 Pin name (function after reset) Pin type I/O structure Notes Pin number Alternate functions 63 99 B7 E6 - VSS S - - - - - - B8 E5 143 PDR_ON S - - - - A8 F5 144 VDD S - - - - 64 100 1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB 56/198 DS10693 Rev 10 Additional functions AF0 AF1 AF2 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR - - - USART2_ CTS UART4_ TX - - - - - - EVENT OUT PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_ RTS UART4_ RX QUADSPI_ BK1_IO3 SAI2_ MCLK_B - - - - EVENT OUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_ TX SAI2_ SCK_B - - - - - - EVENT OUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - SAI1_ FS_A USART2_ RX - - OTG_HS_ ULPI_D0 - - - - EVENT OUT PA4 - - - - - SPI1_NSS/I 2S1_WS SPI3_NSS / I2S3_WS USART2_ CK - - - - OTG_HS_ SOF DCMI_ HSYNC - EVENT OUT PA5 - TIM2_CH1/ TIM2_ETR - TIM8_ CH1N - SPI1_SCK/I 2S1_CK - - - - OTG_HS_ ULPI_CK - - - - EVENT OUT PA6 - TIM1_ BKIN TIM3_CH1 TIM8_ BKIN - SPI1_MISO I2S2_ MCK - - TIM13_CH1 - - - DCMI_ PIXCLK - EVENT OUT PA7 - TIM1_ CH1N TIM3_CH2 TIM8_ CH1N - SPI1_MOSI / I2S1_SD - - - TIM14_CH1 - - FMC_ SDNWE - - EVENT OUT PA8 MCO1 TIM1_CH1 - - I2C3_ SCL - - USART1_ CK - - OTG_FS_ SOF - - - - EVENT OUT PA9 - TIM1_CH2 - - I2C3_ SMBA SPI2_SCK /I2S2_CK SAI1_ SD_B USART1_ TX - - - - - DCMI_D0 - EVENT OUT PA10 - TIM1_CH3 - - - - - USART1_ RX - - OTG_FS_ ID - - DCMI_D1 - EVENT OUT PA11 - TIM1_CH4 - - - - - USART1_ CTS - CAN1_RX OTG_FS_ DM - - - - EVENT OUT PA12 - TIM1_ETR - - - - - USART1_ RTS SAI2_ FS_B CAN1_TX OTG_FS_ DP - - - - EVENT OUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVENT OUT PA14 JTCKSWCLK - - - - - - - - - - - - - - EVENT OUT PA15 JTDI TIM2_CH1/ TIM2_ETR - - HDMI_ CEC SPI1_NSS/ I2S1_WS SPI3_ NSS/ I2S3_WS - UART4_RT S - - - - - - EVENT OUT DS10693 Rev 10 A AF4 AF5 AF6 AF7 AF8 AF9 SPI2/3/ SAI/ CAN1/2 TIM8/9/10/11 I2C1/2/3 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ SPI1/2/3/4 CEC /4/CEC SAI1 /UART5/ UART4/5/ 14/ SPDIFRX SPDIFRX QUADSPI 57/198 Pinout and pin description AF10 Port AF3 STM32F446xC/E Table 11. Alternate function AF0 AF1 AF2 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS PB0 - TIM1_CH2N TIM3_CH3 TIM8_ CH2N - - - SPI3_MOSI/ I2S3_SD UART4_ CTS - OTG_HS_ ULPI_D1 - SDIO_D1 - - EVENT OUT PB1 - TIM1_CH3N TIM3_CH4 TIM8_ CH3N - - - - - - OTG_HS_ ULPI_D2 - SDIO_D2 - - EVENT OUT PB2 - TIM2_CH4 - - - - SAI1_ SD_A SPI3_MOSI/ I2S3_SD - QUADSPI_ CLK OTG_HS_ ULPI_D4 - SDIO_CK - - EVENT OUT PB3 JTDO/ TRACE SWO TIM2_CH2 - - I2C2_ SDA SPI1_SCK /I2S1_CK SPI3_SCK / I2S3_CK - - - - - - - - EVENT OUT PB4 NJTRS T - TIM3_CH1 - I2C3_ SDA SPI1_MISO SPI3_ MISO SPI2_NSS/ I2S2_WS - - - - - - - EVENT OUT PB5 - - TIM3_CH2 - I2C1_ SMBA SPI1_MOSI /I2S1_SD SPI3_ MOSI/ I2S3_SD - - CAN2_RX OTG_HS_ ULPI_D7 - FMC_ SDCKE1 DCMI_ D10 - EVENT OUT PB6 - - TIM4_CH1 HDMI_ CEC I2C1_ SCL - - USART1_ TX - CAN2_TX QUADSPI_ BK1_NCS - FMC_ SDNE1 DCMI_D5 - EVENT OUT PB7 - - TIM4_CH2 - I2C1_ SDA - - USART1_ RX SPDIF_ RX0 - - - FMC_NL DCMI_ VSYNC - EVENT OUT PB8 - TIM2_CH1/ TIM2_ETR TIM4_CH3 TIM10_ CH1 I2C1_ SCL - - - - CAN1_RX - - SDIO_D4 DCMI_D6 - EVENT OUT PB9 - TIM2_CH2 TIM4_CH4 TIM11_ CH1 I2C1_ SDA SPI2_NSS/ I2S2_WS SAI1_ FS_B - - CAN1_TX - - SDIO_D5 DCMI_D7 - EVENT OUT PB10 - TIM2_CH3 - - I2C2_ SCL SPI2_SCK/ I2S2_CK SAI1_ SCK_A USART3_ TX - - OTG_HS_ ULPI_D3 - - - - EVENT OUT PB11 - TIM2_CH4 - - I2C2_ SDA - - USART3_ RX SAI2_ SD_A - - - - - - EVENT OUT PB12 - TIM1_BKIN - - I2C2_ SMBA SPI2_NSS/ I2S2_WS SAI1_ SCK_B USART3_ CK - CAN2_RX OTG_HS_ ULPI_D5 - OTG_ HS_ID - - EVENT OUT PB13 - TIM1_CH1N - - - SPI2_SCK/ I2S2_CK - USART3_ CTS - CAN2_TX OTG_HS_ ULPI_D6 - - - - EVENT OUT PB14 - TIM1_CH2N - TIM8_ CH2N - SPI2_MISO - USART3_ RTS - TIM12_CH1 - - OTG_ HS_DM - - EVENT OUT PB15 RTC_ REFIN TIM1_CH3N - TIM8_ CH3N - SPI2_MOSI /I2S2_SD - - - TIM12_CH2 - - OTG_ HS_DP - - EVENT OUT Port AF3 AF4 AF5 AF6 AF7 AF8 AF9 SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI Pinout and pin description 58/198 Table 11. Alternate function (continued) DS10693 Rev 10 B STM32F446xC/E AF0 AF1 AF2 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS PC0 - - - - - - SAI1_ MCLK_B - - - OTG_HS_ ULPI_STP - FMC_ SDNWE - - EVENT OUT PC1 - - - - - SPI3_MOSI /I2S3_SD SAI1_ SD_A SPI2_MOSI /I2S2_SD - - - - - - - EVENT OUT PC2 - - - - - SPI2_MISO - - - - OTG_HS_ ULPI_DIR - FMC_ SDNE0 - - EVENT OUT PC3 - - - - - SPI2_MOS II2S2_SD - - - - OTG_HS_ ULPI_NXT - FMC_ SDCKE0 - - EVENT OUT PC4 - - - - - I2S1_MCK - - SPDIF_ RX2 - - - FMC_ SDNE0 - - EVENT OUT PC5 - - - - - - - USART3_RX SPDIF_ RX3 - - - FMC_ SDCKE0 - - EVENT OUT PC6 - - TIM3_CH1 TIM8_CH1 FMPI2C1 _SCL I2S2_MCK - - USART6 _TX - - - SDIO_D6 DCMI_D0 - EVENT OUT PC7 - - TIM3_CH2 TIM8_CH2 FMPI2C1 _SDA SPI2_SCK/ I2S2_CK I2S3_MCK SPDIF_RX1 USART6 _RX - - - SDIO_D7 DCMI_D1 - EVENT OUT PC8 TRACE D0 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6 _CK - - - SDIO_D0 DCMI_D2 - EVENT OUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_ SDA I2S_CKIN - UART5_CTS - QUADSPI_ BK1_IO0 - - SDIO_D1 DCMI_D3 - EVENT OUT PC10 - - - - - - SPI3_SCK /I2S3_CK USART3_TX UART4_TX QUADSPI_ BK1_IO1 - - SDIO_D2 DCMI_D8 - EVENT OUT PC11 - - - - - - SPI3_ MISO USART3_RX UART4_RX QUADSPI_ BK2_NCS - - SDIO_D3 DCMI_D4 - EVENT OUT PC12 - - - - I2C2_ SDA - SPI3_ MOSI/ I2S3_SD USART3_CK UART5_TX - - - SDIO_CK DCMI_D9 - EVENT OUT PC13 - - - - - - - - - - - - - - - EVENT OUT PC14 - - - - - - - - - - - - - - - EVENT OUT PC15 - - - - - - - - - - - - - - - EVENT OUT DS10693 Rev 10 C AF4 AF5 AF6 AF7 AF8 AF9 59/198 Pinout and pin description AF10 Port AF3 STM32F446xC/E Table 11. Alternate function (continued) AF0 AF1 AF2 DS10693 Rev 10 D AF4 SYS TIM1/2 TIM3/4/5 PD0 - - - - - PD1 - - - - PD2 - - TIM3_ETR PD3 TRACE D1 - PD4 - PD5 AF5 AF6 AF7 AF8 AF9 AF11 AF12 AF13 AF14 AF15 SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS SPI4_MISO SPI3_ MOSI/ I2S3_SD - - CAN1_RX - - FMC_D2 - - EVENT OUT - - - SPI2_NSS/ I2S2_WS - CAN1_TX - - FMC_D3 - - EVENT OUT - - - - - UART5_RX - - - SDIO_CMD DCMI_ D11 - EVENT OUT - - - SPI2_SCK/ I2S2_CK - USART2_ CTS - QUADSPI_ CLK - - FMC_CLK DCMI_ D5 - EVENT OUT - - - - - - USART2_ RTS - - - - FMC_NOE - - EVENT OUT - - - - - - - USART2_ TX - - - - FMC_NWE - - EVENT OUT PD6 - - - - - SPI3_ MOSI/ I2S3_SD SAI1_ SD_A USART2_ RX - - - - FMC_ NWAIT DCMI_ D10 - EVENT OUT PD7 - - - - - - - USART2_ CK SPDIF_ RX0 - - - FMC_NE1 - - EVENT OUT PD8 - - - - - - - USART3_ TX SPDIF_ RX1 - - - FMC_D13 - - EVENT OUT PD9 - - - - - - - USART3_ RX - - - - FMC_D14 - - EVENT OUT PD10 - - - - - - - USART3_ CK - - - - FMC_D15 - - EVENT OUT PD11 - - - - FMPI2C1 _SMBA - - USART3_ CTS - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16 - - EVENT OUT PD12 - - TIM4_CH1 - FMPI2C1 _SCL - - USART3_ RTS - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17 - - EVENT OUT PD13 - - TIM4_CH2 - FMPI2C1 _SDA - - - - QUADSPI_ BK1_IO3 SAI2_SCK_A - FMC_A18 - - EVENT OUT PD14 - - TIM4_CH3 - FMPI2C1 _SCL - - - SAI2_ SCK_A - - - FMC_D0 - - EVENT OUT PD15 - - TIM4_CH4 - FMPI2C1 _SDA - - - - - - - FMC_D1 - - EVENT OUT STM32F446xC/E AF10 Port AF3 Pinout and pin description 60/198 Table 11. Alternate function (continued) AF0 AF1 AF2 AF4 AF5 AF6 AF7 AF8 SYS TIM1/2 TIM3/4/5 PE0 - - TIM4_ETR - - - - - - PE1 - - - - - - - - PE2 TRACE CLK - - - - SPI4_SCK SAI1_ MCLK_A PE3 TRACE D0 - - - - - PE4 TRACE D1 - - - - PE5 TRACE D2 - - TIM9_CH1 PE6 TRACE D3 - - PE7 - TIM1_ETR PE8 - PE9 AF9 AF11 AF12 AF13 AF14 AF15 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS - SAI2_ MCLK_A - FMC_ NBL0 DCMI_D2 - EVENT OUT - - - - FMC_ NBL1 DCMI_D3 - EVENT OUT - - QUADSPI_ BK1_IO2 - - FMC_A23 - - EVENT OUT SAI1_ SD_B - - - - - FMC_A19 - - EVENT OUT SPI4_NSS SAI1_ FS_A - - - - - FMC_A20 DCMI_D4 - EVENT OUT - SPI4_MISO SAI1_ SCK_A - - - - - FMC_A21 DCMI_D6 - EVENT OUT TIM9_CH2 - SPI4_MOSI SAI1_ SD_A - - - - - FMC_A22 DCMI_D7 - EVENT OUT - - - - - - UART5_RX - QUADSPI_ BK2_IO0 - FMC_D4 - - EVENT OUT TIM1_CH1N - - - - - - UART5_TX - QUADSPI_ BK2_IO1 - FMC_D5 - - EVENT OUT - TIM1_CH1 - - - - - - - - QUADSPI_ BK2_IO2 - FMC_D6 - - EVENT OUT PE10 - TIM1_CH2N - - - - - - - - QUADSPI_ BK2_IO3 - FMC_D7 - - EVENT OUT PE11 - TIM1_CH2 - - - SPI4_NSS - - - - - FMC_D8 - - EVENT OUT PE12 - TIM1_CH3N - - - SPI4_SCK - - - - SAI2_ SCK_B - FMC_D9 - - EVENT OUT PE13 - TIM1_CH3 - - - SPI4_MISO - - - - SAI2_ FS_B - FMC_D10 - - EVENT OUT PE14 - TIM1_CH4 - - - SPI4_MOSI - - - - SAI2_ MCLK_B - FMC_D11 - - EVENT OUT PE15 - TIM1_BKIN - - - - - - - - - - FMC_D12 - - EVENT OUT SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI DS10693 Rev 10 E SAI2_ SD_B 61/198 Pinout and pin description AF10 Port AF3 STM32F446xC/E Table 11. Alternate function (continued) AF0 AF1 AF2 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS PF0 - - - - I2C2_ SDA - - - - - - - FMC_A0 - - EVENT OUT PF1 - - - - I2C2_ SCL - - - - - - - FMC_A1 - - EVENT OUT PF2 - - - - I2C2_ SMBA - - - - - - - FMC_A2 - - EVENT OUT PF3 - - - - - - - - - - - - FMC_A3 - - EVENT OUT PF4 - - - - - - - - - - - - FMC_A4 - - EVENT OUT PF5 - - - - - - - - - - - - FMC_A5 - - EVENT OUT PF6 - - - TIM10_ CH1 - - SAI1_ SD_B - - QUADSPI_ BK1_IO3 - - - - - EVENT OUT PF7 - - - TIM11_ CH1 - - SAI1_ MCLK_B - - QUADSPI_ BK1_IO2 - - - - - EVENT OUT PF8 - - - - - - SAI1_ SCK_B - - TIM13_CH1 QUADSPI_ BK1_IO0 - - - - EVENT OUT PF9 - - - - - - SAI1_ FS_B - - TIM14_CH1 QUADSPI_ BK1_IO1 - - - - EVENT OUT PF10 - - - - - - - - - - - - - DCMI_ D11 - EVENT OUT PF11 - - - - - - - - - - SAI2_SD_B - FMC_ SDNRAS DCMI_ D12 - EVENT OUT PF12 - - - - - - - - - - - - FMC_A6 - - EVENT OUT PF13 - - - - FMPI2C1 _SMBA - - - - - - - FMC_A7 - - EVENT OUT PF14 - - - - FMPI2C1 _SCL - - - - - - - FMC_A8 - - EVENT OUT PF15 - - - - FMPI2C1 _SDA - - - - - - - FMC_A9 - - EVENT OUT Port AF3 AF4 AF5 AF6 AF7 AF8 AF9 SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI Pinout and pin description 62/198 Table 11. Alternate function (continued) DS10693 Rev 10 F STM32F446xC/E AF0 AF1 AF2 DS10693 Rev 10 G AF4 AF5 AF6 AF7 AF8 SYS TIM1/2 TIM3/4/5 PG0 - - - - - - - - - PG1 - - - - - - - - PG2 - - - - - - - PG3 - - - - - - PG4 - - - - - PG5 - - - - PG6 - - - PG7 - - PG8 - PG9 AF9 AF11 AF12 AF13 AF14 AF15 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS - - - FMC_A10 - - EVENT OUT - - - - FMC_A11 - - EVENT OUT - - - - - FMC_A12 - - EVENT OUT - - - - - - FMC_A13 - - EVENT OUT - - - - - - - FMC_A14/ FMC_BA0 - - EVENT OUT - - - - - - - - FMC_A15/ FMC_BA1 - - EVENT OUT - - - - - - - QUADSPI_ BK1_NCS - - DCMI_ D12 - EVENT OUT - - - - - - USART6_C K - - - FMC_INT DCMI_ D13 - EVENT OUT - - - - - - SPDIFRX_ IN2 USART6_R TS - - - FMC_ SDCLK - - EVENT OUT - - - - - - - SPDIFRX_ IN3 USART6_R X QUADSPI_ BK2_IO2 SAI2_FS_B - FMC_NE2/ FMC_NCE3 DCMI_ VSYNC(1) - EVENT OUT PG10 - - - - - - - - - - SAI2_SD_B - FMC_NE3 DCMI_D2 - EVENT OUT PG11 - - - - - - SPI4_ SCK SPDIFRX_ IN0 - - - - - DCMI_D3 - EVENT OUT PG12 - - - - - - SPI4_ MISO SPDIFRX_ IN1 USART6_R TS - - - FMC_NE4 - - EVENT OUT PG13 TRACE D2 - - - - - SPI4_ MOSI - USART6_C TS - - - FMC_A24 - - EVENT OUT PG14 TRACE D3 - - - - - SPI4_ NSS - USART6_T X QUADSPI_ BK2_IO3 - - FMC_A25 - - EVENT OUT PG15 - - - - - - - - USART6_C TS - - - FMC_ SDNCAS DCMI_ D13 - EVENT OUT SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI 63/198 Pinout and pin description AF10 Port AF3 STM32F446xC/E Table 11. Alternate function (continued) AF0 AF1 AF2 SYS TIM1/2 TIM3/4/5 PH0 - - - - - - - - - PH1 - - - - - - - - - Port AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS OTG1_FS FMC/ SDIO/ OTG2_FS DCMI - SYS - - - - - - EVENT OUT - - - - - - EVENT OUT SPI2/3/ SAI/ CAN1/2 SPI2/3/4/ USART1/2/3 USART6/ TIM12/13/ TIM8/9/10/11 I2C1/2/3 SPI1/2/3/4 SAI1 /UART5/ UART4/5/ 14/ CEC /4/CEC SPDIFRX SPDIFRX QUADSPI H 1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. Pinout and pin description 64/198 Table 11. Alternate function (continued) DS10693 Rev 10 STM32F446xC/E STM32F446xC/E 5 Memory mapping Memory mapping The memory map is shown in Figure 15. Figure 15. Memory map Reserved 0xE010 0000 - 0xFFFF FFFF Cortex-M4 internal peripherals 0xE000 0000 - 0xE00F FFFF AHB3 0x6000 0000 - 0xDFFF FFFF Reserved 0x5006 0C00 - 0x5FFF FFFF 0x5006 0BFF AHB2 0xFFFF FFFF 512-Mbyte Block 7 Cortex-M4 Internal peripherals Reserved 0x5000 0000 0x4008 0000 - 0x4FFF FFFF 0x4007 FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte Block 6 FMC 0xD000 0000 0xCFFF FFFF AHB1 512-Mbyte Block 5 FMC/QuadSPI 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF 512-Mbyte Block 4 FMC bank 3 and QuadSPI 0x4002 0000 Reserved 0x4001 6C00 - 0x4001 FFFF 0x4001 6BFF 512-Mbyte Block 3 FMC bank 1 0x6000 0000 0x5FFF FFFF APB2 512-Mbyte Block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte Block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte Block 0 SRAM 0x0000 0000 Reserved 0x2003 0000 - 0x3FFF FFFF Reserved 0x2002 0000 - 0x2002 FFFF SRAM (16 KB aliased By bit-banding SRAM (112 KB aliased By bit-banding 0x2001 C000 - 0x2001 FFFF Reserved 0x1FFF C008 - 0x1FFF FFFF Option Bytes 0x1FFF C000 - 0x1FFF C00F Reserved System memory Reserved Option bytes 0x1FFF 7A10 - 0x1FFF 7FFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFE C008 - 0x1FFE FFFF 0x1FFE C000 - 0x1FFE C00F Reserved 0x4001 0000 0x4000 8000 - 0x4000 FFFF 0x4000 7FFF 0x2000 0000 - 0x2001 BFFF Reserved 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x0820 0000 - 0x0FFF FFFF Flash memory 0x0800 0000 - 0x081F FFFF Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins APB1 0x0020 0000 - 0x07FF FFFF 0x4000 0000 0x0000 0000 - 0x001F FFFF MS33841V1 DS10693 Rev 10 65/198 69 Memory mapping STM32F446xC/E Table 12. STM32F446xC/E register boundary addresses(1) Bus Boundary address - 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xD000 0000 - 0xDFFF FFFF FMC bank 6 0xC000 0000 - 0xCFFF FFFF FMC bank 5 AHB3 0xA000 2000 - 0x0xBFFF FFFF Reserved 0xA000 1000 - 0x0xA000 1FFF QuadSPI control register 0xA000 0000 - 0xA000 0FFF FMC control register 0x9000 0000 - 0x9FFF FFFF QuadSPI 0x8000 0000 - 0x8FFF FFFF FMC bank 3 0x7000 0000 - 0x0x7FFF FFFF - AHB2 66/198 Peripheral Reserved 0x6000 0000 - 0x6FFF FFFF FMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved 0x5006 0800- 0x500F 07FF Reserved 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0X5003 FFFF USB OTG FS DS10693 Rev 10 STM32F446xC/E Memory mapping Table 12. STM32F446xC/E register boundary addresses(1) (continued) Bus Boundary address Peripheral - 0x4008 0000- 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 BC00- 0x4003 FFFF 0x4002 B000 - 0x4002 BBFF 0x4002 9400 - 0x4002 AFFF 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF Reserved 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF AHB1 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0X4002 5000 - 0X4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0X4002 3400 - 0X4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF 0x4002 2800 - 0x4002 2BFF 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DS10693 Rev 10 67/198 69 Memory mapping STM32F446xC/E Table 12. STM32F446xC/E register boundary addresses(1) (continued) Bus Boundary address - 0x4001 6C00- 0x4001 FFFF 0x4001 6800 - 0x4001 6BFF Peripheral Reserved 0x4001 5C00 - 0x4001 5FFF SAI2 0x4001 6000 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF APB2 68/198 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 DS10693 Rev 10 STM32F446xC/E Memory mapping Table 12. STM32F446xC/E register boundary addresses(1) (continued) Bus Boundary address - 0x4000 8000- 0x4000 FFFF 0x4000 7C00 - 0x4000 7FFF Peripheral Reserved 0x4000 7800 - 0x4000 7BFF APB1 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF HDMI-CEC 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF FMPI2C1 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF SPDIFRX 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 1. The grey color is used for reserved boundary addresses. DS10693 Rev 10 69/198 69 Electrical characteristics STM32F446xC/E 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 16. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 16. Pin loading conditions Figure 17. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 70/198 DS10693 Rev 10 MS19010V2 STM32F446xC/E 6.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme VBAT VBAT = 1.65 to 3.6V GPIOs IN 2 × 2.2 μF VCAP_1 VCAP_2 VDD 1/2/...11/12 12 × 100 nF + 1 × 4.7 μF VSS 1/2/...11/12 VDDUSB(2) BYPASS_REG Voltage regulator Flash memory OTG FS PHY 100 nF + 1 μF Reset controller PDR_ON VDDA VREF 100 nF + 1 μF IO Logic Kernel logic (CPU, digital & RAM) VDDUSB(2) VDD Level shifter OUT VDD Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch 100 nF + 1 μF VREF+ ADC VREF- Analog: RCs, PLL,.. VSSA MSv33072V1 1. VDDA and VSSA must be connected to VDDand VSS, respectively. 2. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and associated DP/DM GPIOs. Its value is independent from the VDD and VDDA values, but must be the last supply to be provided and the first to disappear. If VDD is different from VDDUSB and only one on-chip OTG PHY is used, the second OTG PHY GPIOs (DP/DM) are still supplied at VDDUSB (3.3V). 3. VDDUSB is available only on WLCSP81, UFBGA144 and LQFP144 packages. For packages where VDDUSB pin is not available, it is internally connected to VDD. 4. VCAP_2 pad is not available on LQFP64. Caution: Each power supply pair (e.g. VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DS10693 Rev 10 71/198 171 Electrical characteristics 6.1.7 STM32F446xC/E Current consumption measurement Figure 19. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA VDDUSB MSv36557V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13, Table 14, and Table 15 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 13. Voltage characteristics Symbol VDD–VSS VIN Ratings Min Max –0.3 4.0 Input voltage on FT & FTf pins(2) VSS–0.3 VDD+4.0 Input voltage on TTa pins VSS–0.3 4.0 Input voltage on any other pin VSS–0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 External main supply voltage (including VDDA, VDD, VDDUSB and VBAT)(1) Input voltage on BOOT0 pin |VDDx| |VSSX VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.15 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current. 72/198 DS10693 Rev 10 - STM32F446xC/E Electrical characteristics Table 14. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD power lines (source)(1) IVSS (1) IVDDUSB 25 Maximum current into each VDD power pin (source)(1) IVSS (1) IIO IINJ(PIN) 100 - 100 Output current sunk by any I/O and control pin 25 Output current sourced by any I/Os and control pin - 25 Total output current sunk by sum of all I/Os and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 Total output current sourced by sum of all I/Os and control IINJ(PIN) - 240 Total current into VDDUSB power line (source) IVDD IIO 240 Total current out of sum of all VSS ground lines (sink) Maximum current out of each VSS ground pin (sink) Unit pins(2) Injected current on FT, FTf, RST and B pins mA -120 –5/+0(3) Injected current on TTa pins ±5(4) Total injected current (sum of all I/O and control pins)(5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN