STM32F732VET6

STM32F732xx STM32F733xx Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash /256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions. • Memories – Up to 512 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP)) – 528 bytes of OTP memory – SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes) – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • Dual mode Quad-SPI • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – Dedicated USB power – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power – Sleep, Stop and Standby modes November 2020 This is information on a product in full production. LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) UFBGA144 (7 x 7 mm) UFBGA176 (10 x 10 mm) WLCSP100 (0.4 mm pitch) LQFP144 (20 × 20 mm) LQFP176 (24 x 24 mm) – VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes of backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Debug mode – SWD and JTAG interfaces – Cortex®-M7 Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 108 MHz – Up to 138 5 V-tolerant I/Os • Up to 21 communication interfaces – Up to 3× I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock – 2 x SAIs (serial audio interface) DS11854 Rev 5 1/228 www.st.com STM32F732xx STM32F733xx • CRC calculation unit – 1 x CAN (2.0B active) – 2 x SDMMCs • RTC: subsecond accuracy, hardware calendar • Advanced connectivity • 96-bit unique ID – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the part number • AES: 128/256-bit key encryption hardware accelerator • True random number generator Table 1. Device summary Reference Part number STM32F732xx STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE STM32F733xx STM32F733IE, STM32F733ZE, STM32F733VE 2/228 DS11854 Rev 5 STM32F732xx STM32F733xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 STM32F733xx versus STM32F732xx LQFP144/ LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16 3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35 3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DS11854 Rev 5 3/228 6 Contents STM32F732xx STM32F733xx 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 42 3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 43 3.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 44 3.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 45 3.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 45 3.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.32 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 46 3.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.35 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.36 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1 4/228 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DS11854 Rev 5 STM32F732xx STM32F733xx Contents 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 109 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 109 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 109 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 139 6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F733xx devices) 141 6.3.14 USB OTG HS PHY regulator characteristics (on STM32F733xx devices) 141 6.3.15 USB HS PHY external resistor characteristics (on STM32F733xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 145 6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DS11854 Rev 5 5/228 6 Contents 7 8 STM32F732xx STM32F733xx 6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 198 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.1 LQFP64 – 10 x 10 mm, low-profile quad flat package information . . . . . 201 7.2 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 204 7.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 207 7.4 LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . 210 7.5 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 7.6 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.7 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 220 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 226 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 6/228 DS11854 Rev 5 STM32F732xx STM32F733xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F732xx and STM32F733xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F732xx and STM32F733xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 61 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STM32F732xx and STM32F733xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 88 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 107 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 109 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 109 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 114 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 115 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 117 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 117 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 120 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 129 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 DS11854 Rev 5 7/228 9 List of tables Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. 8/228 STM32F732xx STM32F733xx HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 USB HS PHY external resistor characteristics (on STM32F733xx devices). . . . . . . . . . . 142 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 157 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 157 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 178 DS11854 Rev 5 STM32F732xx STM32F733xx Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. List of tables Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 178 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 179 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 180 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 181 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 183 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 199 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 200 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 215 UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 218 WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 222 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 226 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 DS11854 Rev 5 9/228 9 List of figures STM32F732xx STM32F733xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. 10/228 Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F732xx and STM32F733xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F732xx and STM32F733xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . 23 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34 STM32F732xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F732xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F733xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32F732xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32F733xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F733xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32F732xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32F733xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F733xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32F733xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 STM32F732xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 STM32F733xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DS11854 Rev 5 STM32F732xx STM32F733xx Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. List of figures PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 159 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 159 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 173 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 177 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 179 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 180 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 182 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 188 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 191 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 192 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LQFP176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 UFBGA176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 DS11854 Rev 5 11/228 12 List of figures Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. 12/228 STM32F732xx STM32F733xx UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 DS11854 Rev 5 STM32F732xx STM32F733xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F732xx and STM32F733xx microcontrollers. This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx advanced Arm®-based 32-bit MCUs reference manual (RM0431). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 technical reference manual available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS11854 Rev 5 13/228 49 Description 2 STM32F732xx STM32F733xx Description The STM32F732xx and STM32F733xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a single floating point unit (SFPU) precision which supports Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F732xx and STM32F733xx devices incorporate high-speed embedded memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including 64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces. • • • • • • • Up to three I2Cs Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. Four USARTs plus four UARTs An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI or with the integrated HS PHY depending on the part number) One CAN Two SAI serial audio interfaces Two SDMMC host interfaces Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface. The STM32F732xx and STM32F733xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F732xx and STM32F733xx devices offer devices in 7 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. 14/228 DS11854 Rev 5 STM32F732xx STM32F733xx Description These features make the STM32F732xx and STM32F733xx microcontrollers suitable for a wide range of applications: • Motor drive and application control, • Medical equipment, • Industrial applications: PLC, inverters, circuit breakers, • Printers, and scanners, • Alarm systems, video intercom, and HVAC, • Home audio appliances, • Mobile applications, Internet of Things, • Wearable devices: smartwatches. The following table lists the peripherals available on each part number. Table 2. STM32F732xx and STM32F733xx features and peripheral counts Peripherals Flash memory in Kbytes SRAM in Kbytes STM32F73xRx STM32F73xVx STM32F73xZx 256 256 256 512 512 256(176+16+64) Instruction 16 Backup 4 General-purpose 10(2) Advanced-control 2 Basic 2 No 1 Random number generator Yes SPI / I2S 3/3 (simplex)(3) 4/3 (simplex)(3) 2 I C USART/UART 4/2 4/4 USB OTG FS Yes USB OTG HS(4) Yes USB OTG PHY HS controller (USBPHYC) Yes(10) No 1 SAI 2 SDMMC1 SDMMC2 Yes Yes(5)(6) No AES Yes 82 in STM32F732xx 79 in STM32F733xx 50 12-bit ADC Number of channels 5/3 (simplex)(3) 3 CAN GPIOs 512 Yes Low-power Communication interfaces 256 Yes(1) No Quad-SPI Timers 512 System FMC memory controller STM32F73xIx 114 in STM32F732xx 112 in STM32F733xx 140 in STM32F732xx 138 in STM32F733xx 3 16 12-bit DAC Number of channels 24 Yes 2 DS11854 Rev 5 15/228 49 Description STM32F732xx STM32F733xx Table 2. STM32F732xx and STM32F733xx features and peripheral counts (continued) Peripherals STM32F73xRx STM32F73xVx STM32F73xIx 216 MHz(7) Maximum CPU frequency 1.7 to 3.6 V(8) Operating voltage Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F73xZx Junction temperature: –40 to + 125 °C LQFP64(9) LQFP100(9) WLCSP100(10) LQFP144 UFBGA144(10) UFBGA176 LQFP176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. On the STM32F733xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 generalpurpose timers. 3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 4. USB OTG HS with the ULPI in the STM32F732xx devices and with integrated HS PHY in the STM32F733xx devices. 5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 6. The SDMMC2 is not available on the STM32F733Vx devices. 7. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range). 8. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF). 9. Available only on the STM32F732xx devices. 10. Available only on the STM32F733xx devices. 16/228 DS11854 Rev 5 STM32F732xx STM32F733xx Full compatibility throughout the family The STM32F732xx devices are fully pin-to-pin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices. The STM32F732xx devices are partially pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 and Figure 2 give compatible board designs between the STM32F732xx, with LQFP64 and LQFP100 packages, and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package PC3 VDD VSSA VREF+ VDDA PA0-WKUP PA1 PA2 STM32F427xx / STM32F437xx STM32F429xx / STM32F439xx STM32F415xx / STM32F417xx STM32F405xx / STM32F407xx 18 19 20 21 22 23 24 25 VDD PB11 VCAP1 PB10 PE15 PE14 PE12 PE13 PE11 PE9 PE10 PE7 PE8 PB1 PB2 PC5 PB0 PC4 PA7 PA5 PA6 PA4 VDD PA3 18 19 20 21 22 23 24 25 STM32F73xxx Pins 19 to 49 are not compatible VDD VSS VCAP1 PB11 PB10 PE15 PE14 PE12 PE13 PE11 PE10 PE9 PE8 PE7 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA4 PA5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS 2.1 Description MSv41002V2 DS11854 Rev 5 17/228 49 Description STM32F732xx STM32F733xx PC12 PC11 PC10 PA15 PA14 PC12 PC11 PC10 PA15 PA14 Figure 2. Compatible board design for LQFP64 package VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 VSS PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 53 52 51 50 49 48 47 46 45 44 43 42 41 STM32F4x1 40 39 38 37 PB11 not available anymore 36 Replaced by V CAP_1 35 34 33 28 29 30 31 32 VDD VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD VSS PB2 PB10 VCAP_1 VSS VDD PB2 PB10 PB11 VCAP_1 VDD 53 52 51 50 49 48 47 46 45 44 43 42 41 STM32F405/ 40 STM32F415 line 39 38 37 36 35 34 33 28 29 30 31 32 V CAP increased to 4.7 μf ESR 1 ohm or below 1 ohm VDD VSS 57 56 55 54 53 52 51 50 49 48 VDD 47 VSS 46 PA13 45 44 PA12 PA11 PA10 PA9 41 40 PA8 PC9 39 PC8 38 PC7 37 36 PC6 PB15 35 PB14 34 PB13 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB12 VSS VCAP_1 PB11 PB10 PB1 PB2 PB0 PC4 PA7 PA5 PA6 PA4 VSS VDD PA3 PC5 not available anymore Replaced by VCAP_1 VDD VSS VDD 43 42 STM32F732xx VDD PA14 PC 11 PC10 PA15 PC12 PB3 PD2 PB4 PB5 VSS Not compatible STM32F732xx pins with either STM32F4x1 or STM32F405/F415 or both VCAP increased to 4.7 μf ESR between 0.1 ohm and 0.2 ohm VSS VDD MSv42019V1 The STM32F732xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin compatible with the STM32F4xx devices. 18/228 DS11854 Rev 5 STM32F732xx STM32F733xx STM32F733xx versus STM32F732xx LQFP144/ LQFP176 packages Figure 3. Compatible board design for LQFP144 package STM32F732xx 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 STM32F733xx 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 72 VDD VDD 72 PG6, PG7 removed on the STM32F733xx Not compatible pins MSv42021V1 Figure 4. Compatible board design for LQFP176 package STM32F732xx 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 STM32F733xx 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 VDD VSS PH12 88 PH11 88 PH11 2.2 Description PG6, PG7 removed on the STM32F733xx Not compatible pins MSv42074V1 Figure 5 shows the general block diagram of the device family. DS11854 Rev 5 19/228 49 Description STM32F732xx STM32F733xx Figure 5. STM32F732xx and STM32F733xx block diagram FS PHY FIFO RNG AHBP AHBS LDO PLL1 PLL2 BGR USB OTG HS PLL DMA/ FIFO LDO SRAM1 176KB SRAM2 16KB GPIO PORT A PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E CLK, CS,D[7:0] @VDDA POR reset Int RC HS RCC Reset M & control GT GPIO PORT I 2 channels as AF SDMMC2 TIM1 / PWM 16b TIM8 / PWM 16b TIM9 16b TIM10 16b 1 channel as AF TIM11 16b SPI1/I2S1 MOSI, MISO, SCK, NSS as AF SPI4 MOSI, MISO, SCK, NSS as AF SPI5 SD, SCK, FS, MCLK as AF SAI1 SD, SCK, FS, MCLK as AF SAI2 (2) OTG HS PHY CONTROLLER AHB/ APB1 AHB/APB2 WWDG LPTIM1 FIFO FIFO smcard USART1 irDA smcard USART6 irDA MOSI, MISO, SCK, NSS as AF ULPI:CK, D[7:0], DIR, STP, NXT SCL, SDA, INT, ID, VBUS GPDMA1 GPDMA2 1 channel as AF RX, TX, SCK, CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF OSC_IN OSC_OUT VBAT = 1.8 to 3.6 V @VSW 16b TIM6 16b TIM7 16b APB1 0M 3Hz APB1 54 MHz (max) 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF SDMMC1 APB2 108 MHz (max) D[7:0] CMD, CK as AF @VDD33 XTAL 32 kHz OSC32_IN OSC32_OUT RTC AWU Backup register RTC_TS RTC_TAMPx RTC_OUT 4 KB BKPRAM EXT IT. WKUP FIFO FIFO D[7:0] CMD, CK as AF WKUP[4:0] VDDMMC33 = 3.0 to 3.6V VDDUSB33 = 3.0 to 3.6 V VDD = 1.8 to 3.6 V VSS VCAP1 WDG32K CRC 168 AF VOLT. REG 3.3V TO 1.2V Standby interface LS PI[11:0] BBgen + POWER MNGT XTAL OSC 4- 16MHz LS GPIO PORT H VDDA, VSSA NRESET @VDD33 VDD12 FCLK HCLK APBP2CLK APBP1CLK AHB2PCLK AHB1PCLK GPIO PORT G PH[15:0] BOR PVD GPIO PORT F PG[15:0] SUPPLY SUPERVISION POR/PDR @VDDA PLL1+PLL2+PLL3 PF[15:0] DP DM SCL, SDA, INT, ID, VBUS CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0] SDNE[1:0], SDNWE, NL NRAS, NCAS, NADV NWAIT, INTN Quad-SPI AHB1 216 MHz RC LS PA[15:0] OTG FS EXT MEM CTL (FMC) SRAM, SDRAM, NOR-Flash, NAND-Flash, SDRAM 8 Streams FIFO GP-DMA1 USB AHB2 216 MHz 8 Streams FIFO GP-DMA2 AES128 FLASH 512KB TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels TIM12 16b 2 channels as AF TIM13 16b 1 channel as AF TIM14 16b 1 channel as AF smcard USART2 irDA RX, TX, SCK CTS, RTS as AF smcard USART3 irDA UART4 RX, TX, SCK CTS, RTS as AF RX, TX as AF UART5 RX, TX as AF UART7 RX, TX as AF SPI2/I2S2 SPI3/I2S3 I2C1/SMBUS I2C2/SMBUS SYSCFG RX, TX as AF UART8 I2C3/SMBUS Digital filter DP, DM ULPI:CK, D[7:0], DIR, STP, NXT SCL/SDA, INT, ID, VBUS ACCEL/ CACHE PHY D-Cache 8KB (2) USB HS PHY ITCM RAM 16KB AXIM I-Cache 8KB 216MHz DTCM RAM 64KB FIFO ARM CPU Cortex-M7 AHB BUS-MATRIX 11S8M 8S7M AHB bus-matrix TRACECK TRACED[3:0] MPU FPU NVIC DTCM ICTM PWRCTRL JTAG & SW ETM AHB2AXI JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO MOSI, MISO, SCK NSS as AF MOSI, MISO, SCK NSS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF VDDREF_ADC 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 U STemperature AR T 2 M B sensor ps ADC1 ADC2 ADC3 bxCAN1 FIFO @VDDA TX, RX @VDDA IF DAC1 ITF DAC2 DAC1 as AF DAC2 as AF MSv41003V3 1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 20/228 DS11854 Rev 5 STM32F732xx STM32F733xx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring: – Six-stage dual-issue pipeline – Dynamic branch prediction – Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache) – 64-bit AXI4 interface – 64-bit ITCM interface – 2x32-bit DTCM interfaces The processor supports the following memory interfaces: • Tightly Coupled Memory (TCM) interface. • Harvard instruction and data caches and AXI master (AXIM) interface. • Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It supports single precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 5 shows the general block diagram of the STM32F732xx and STM32F733xx family. Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS11854 Rev 5 21/228 49 Functional overview 3.3 STM32F732xx STM32F733xx Embedded Flash memory The STM32F732xx and STM32F733xx devices embed a Flash memory of up to 512 Kbytes available for storing programs and data. The flexible protections can be configured thanks to option bytes: • 3.4 Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader – Level 2: debug/chip read protection disabled. • Write protection (WRP): the protected area is protected against erasing and programming. • Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can be protected against D-bus read accesses by using the proprietary readout protection (PCROP). The protected area is execute-only. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Embedded SRAM All the devices feature: • • System SRAM up to 256 Kbytes: – SRAM1 on AHB bus Matrix: 176 Kbytes – SRAM2 on AHB bus Matrix: 16 Kbytes – DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: – It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 22/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.6 Functional overview AXI-AHB bus matrix The STM32F732xx and STM32F733xx system architecture is based on 2 sub-systems: • • An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: – 3x AXI to 32-bit AHB bridges connected to AHB bus matrix – 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix – The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. AHBS USB_HS_M USB OTG HS DMA_P2 GP DMA2 DMA_MEM2 AHBP 8KB I/D Cache AXIM GP DMA1 DMA_PI Arm Cortex-M7 DMA_MEM1 ITCM DTCM Figure 6. STM32F732xx and STM32F733xx AXI-AHB bus matrix architecture(1) DTCM RAM 64KB ITCM RAM 16KB AXI to multi-AHB ART ITCM 64-bit AHB FLASH 512KB 64-bit BuS Matrix SRAM1 176KB SRAM2 16KB AHB Periph1 AHB periph2 FMC external MemCtl APB1 APB2 Quad-SPI 32-bit Bus Matrix - S MSv41005V1 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. DS11854 Rev 5 23/228 49 Functional overview 3.7 STM32F732xx STM32F733xx DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 24/228 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDMMC • ADC • SAI • Quad-SPI DS11854 Rev 5 STM32F732xx STM32F733xx 3.8 Functional overview Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller • The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories • 8-, 16-, 32-bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • Read FIFO for SDRAM controller • The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: • Direct mode through registers • External Flash status register polling mode • Memory mapped mode. Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit access. The code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. DS11854 Rev 5 25/228 49 Functional overview 3.10 STM32F732xx STM32F733xx Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with a minimum interrupt latency. 3.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the STM32F732xx devices (138 GPIOs in the STM32F733xx devices) can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. The STM32F733xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2. The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate the 480 Mbps in the USB OTG High Speed mode. The PLL1 has as input HSE clock. 26/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.13 Functional overview Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space mapped on ITCM or AXIM interface • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface • The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. 3.14 Note: Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. • • The VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: – During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD – During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD – The VDDSDMMC rising and falling time rate specifications must be respected – In the operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. The VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 7 and Figure 8). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to the VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: – During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD DS11854 Rev 5 27/228 49 Functional overview STM32F732xx STM32F733xx – The VDDUSB rising and falling time rate specifications must be respected – In the operating mode phase, VDDUSB could be lower or higher than VDD: - If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 7. VDDUSB connected to VDD power supply VDD VDD_MAX VDD= VDDA = VDDUSB VDD_MIN Power-on Operating mode Power-down time MS37591V1 Figure 8. VDDUSB connected to external power supply VDDUSB_MAX USB functional area VDDUSB VDDUSB_MIN USB non functional area VDD = VDDA Power-on Operating mode USB non functional area VDD_MIN Power-down time MS37590V1 28/228 DS11854 Rev 5 STM32F732xx STM32F733xx Functional overview On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional power supply pins depending on the package: • The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 µF must be connected on the VDD12OTGHS pin. • On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided for the VDDUSB power pin. 3.15 Power supply supervisor 3.15.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.15.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 9: Power supply supervisor interconnection with internal reset OFF. DS11854 Rev 5 29/228 49 Functional overview STM32F732xx STM32F733xx Figure 9. Power supply supervisor interconnection with internal reset OFF VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V NRST VDD Application reset signal PDR_ON VSS MS31383V4 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 10). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. Figure 10. PDR_ON control with internal reset OFF V DD PDR = 1.7 V time Reset by other source than power supply supervisor NRST PDR_ON PDR_ON time MS19009V7 30/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.16 Functional overview Voltage regulator The regulator has four operating modes: • • 3.16.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: • MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). A different voltage scaling is provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). • LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: • – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. The VCAP_1 and VCAP_2 pins must be connected to 2*2.2 µF, ESR < 2 Ω (or 1*4.7 µF, ESR between 0.1 Ω and 0.2 Ω if only the VCAP_1 pin is provided (on LQFP64 package)). All the packages have the regulator ON feature. DS11854 Rev 5 31/228 49 Functional overview STM32F732xx STM32F733xx Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.16.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. The PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: 32/228 • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. • The over-drive and under-drive modes are not available. • The Standby mode is not available. DS11854 Rev 5 STM32F732xx STM32F733xx Functional overview Figure 11. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor Ext. reset controller active signal (optional) when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V3 The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 12). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 13). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application. Note: On the LQFP64 pin package, the VCAP_2 is not available. DS11854 Rev 5 33/228 49 Functional overview STM32F732xx STM32F733xx Figure 12. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V V12 Min V12 VCAP_1 / VCAP_2 time NRST time ai18491f 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 13. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492e 1. This figure is valid whatever the internal reset mode (ON or OFF). 34/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.16.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package LQFP64, LQFP100 Regulator ON Regulator OFF Internal reset ON Internal reset OFF Yes No No Yes LQFP144 LQFP176, UFBGA144, UFBGA176 3.17 Yes Yes Yes Yes PDR_ON set to VDD PDR_ON set to VSS BYPASS_REG set BYPASS_REG set to VDD to VSS Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator(LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. DS11854 Rev 5 35/228 49 Functional overview STM32F732xx STM32F733xx All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 3.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): – Normal mode (default mode when MR or LPR is enabled) – Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode • Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 36/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.19 Functional overview VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and the VBAT pin should be connected to VDD. 3.20 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. DS11854 Rev 5 37/228 49 Functional overview STM32F732xx STM32F733xx Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 38/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.20.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. The TIM1 and TIM8 support independent DMA request generation. 3.20.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F732xx and STM32F733xx devices (see Table 6 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F732xx and STM32F733xx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.20.3 Basic timers TIM6 and TIM7 These timers are mainly used for the DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. The TIM6 and TIM7 support independent DMA request generation. DS11854 Rev 5 39/228 49 Functional overview 3.20.4 STM32F732xx STM32F733xx Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.20.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous / one-shot mode • Selectable software / hardware input trigger • Selectable clock source: • Internal clock source: LSE, LSI, HSI or APB clock • External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) • Programmable digital glitch filter • Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.20.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 40/228 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source DS11854 Rev 5 STM32F732xx STM32F733xx 3.21 Functional overview Inter-integrated circuit interface (I2C) The devices embed 3 I2Cs. Refer to Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X 1. X: supported. DS11854 Rev 5 41/228 49 Functional overview 3.22 STM32F732xx STM32F733xx Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USARTs. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: • Full-duplex asynchronous communications • Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance • Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming • A common programmable transmit and receive baud rate of up to 27 Mbit/s when USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. • Auto baud rate detection • Programmable data word length (7 or 8 or 9 bits) word length • Programmable data order with MSB-first or LSB-first shifting • Progarmmable parity (odd, even, no parity) • Configurable stop bits (1 or 1.5 or 2 stop bits) • Synchronous mode and clock output for synchronous communications • Single-wire half-duplex communications • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Multiprocessor communications • LIN master synchronous break send capability and LIN slave break detection capability • IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode • Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard) • Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length 42/228 UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DS11854 Rev 5 STM32F732xx STM32F733xx Functional overview Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 3.24 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. DS11854 Rev 5 43/228 49 Functional overview STM32F732xx STM32F733xx SAI1 and SAI2 can be served by the DMA controller 3.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve an error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU and USB interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.26 Audio PLL (PLLSAI) An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. 3.27 SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 3.28 Controller area network (bxCAN) The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated to the CAN. 44/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.29 Functional overview Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Internal FS OTG PHY support • HNP/SNP/IP inside (no need for any external resistor) • BCD support For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 3.30 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s). The STM32F732xx devices feature a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The STM32F733xx devices feature an integrated PHY HS. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has a software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support DS11854 Rev 5 45/228 49 Functional overview STM32F732xx STM32F733xx • Internal FS OTG PHY support • For the STM32F732xx devices: External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • For the STM32F733xx devices: Internal HS OTG PHY support. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F733xx devices. The USB HS PHY controller: 3.31 – Sets the PHYPLL1/2 values for the PHY HS – Sets the other controls on the PHY HS – Controls and monitors the USB PHY’s LDO Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.32 Advanced encryption standard hardware accelerator (AES) The devices embed an AES hardware accelerator which can be used to both encipher and decipher data using AES algorithm. 46/228 DS11854 Rev 5 STM32F732xx STM32F733xx Functional overview The AES peripheral supports: 3.33 • Encryption/Decryption using AES Rijndael Block Cipher algorithm • NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm • 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x 32-bit registers) • Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher Message Authentication Code mode (CMAC) supported. • Key scheduler • Key derivation for decryption • 128-bit data block processing • 128-bit, 256-bit key length • 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer. • Register access supporting 32-bit data width only. • One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC mode. • Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data. • Suspend a message if another message with a higher priority needs to be processed General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. A Fast I/O handling allows a maximum I/O toggling up to 108 MHz. 3.34 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In the scan mode, an automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. DS11854 Rev 5 47/228 49 Functional overview STM32F732xx STM32F733xx To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 3.35 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.36 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • Two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.37 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 48/228 DS11854 Rev 5 STM32F732xx STM32F733xx 3.38 Functional overview Embedded Trace Macrocell™ The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F732xx and STM32F733xx device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using the USB or any other high-speed channel. The real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. The TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DS11854 Rev 5 49/228 49 Pinouts and pin description 4 STM32F732xx STM32F733xx Pinouts and pin description VDD PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PB10 PB11 VCAP_1 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VSS PB9 PB8 Figure 14. STM32F732xx LQFP64 pinout 1. The above figure shows the package top view. 50/228 DS11854 Rev 5 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 MS40455V3 STM32F732xx STM32F733xx Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 15. STM32F732xx LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 MSv40457V1 1. The above figure shows the package top view. DS11854 Rev 5 51/228 98 Pinouts and pin description STM32F732xx STM32F733xx Figure 16. STM32F733xx WLCSP100 ballout (with OTG PHY HS) 1 2 3 4 5 6 PC10 PD1 PD5 PB3 VCAP_2 PA15 PD0 PD4 10 8 9 VSS VDD PE3 PB4 PB7 PE1 PE6 7 A VDD VSS B PA13 PA12 C PA11 PA10 PA9 PA14 PC11 PD3 PB5 PB8 PE2 VBAT D PC9 PC8 PA8 PC7 PC12 PD6 PB6 PB9 PE4 PC13 E PC6 PD15 PD13 PE10 PD2 PD7 PE0 PE5 PC14 PC15 F PD14 PD12 PD11 PE15 PB0 PA5 PC3 PC0 VSS G VDD12 OTGHS OTG_HS _REXT PB10 PE11 PB1 PA6 PA4 PA0 NRST PH0 H PB15 PB13 PB11 PE12 PE8 PC4 PA3 PA2 PC1 PH1 J PB14 PB12 VCAP_1 PE13 PE7 PC5 VDD PA1 VREF+ PC2 K VDD USB VDD VSS PE14 PE9 PB2 PA7 VSS VDDA VSSA BOOT0 VDD MSv42002V2 1. The above figure shows the package top view. 52/228 DS11854 Rev 5 STM32F732xx STM32F733xx Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 17. STM32F732xx LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 MS39132V1 1. The above figure shows the package top view. DS11854 Rev 5 53/228 98 Pinouts and pin description STM32F732xx STM32F733xx 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 18. STM32F733xx LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 with HS PHY 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 MS41014V1 1. The above figure shows the package top view. 54/228 DS11854 Rev 5 STM32F732xx STM32F733xx Pinouts and pin description Figure 19. STM32F733xx UFBGA144 ballout (with OTG PHY HS) 1 2 3 4 5 6 7 8 9 10 11 12 A PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13 B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 VDDUSB PA11 D PH0 OSC_IN VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E PH1 OSC_OUT PF3 PF4 PF5 PDR_ON VSS VSS PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7 G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP_2 VSS PG8 PC6 H PC0 PC1 PC2 PC3 BYPASS_ REG VSS VCAP_1 PE11 PD11 VDD12OTG HS OTG_HS _REXT PG5 J VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 MSv42000V1 1. The above figure shows the package top view. DS11854 Rev 5 55/228 98 Pinouts and pin description STM32F732xx STM32F733xx PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 V DD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 Figure 20. STM32F732xx LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 VCAP_1 VDD PH6 PH7 PH8 PH9 PH10 PH11 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 MS41015V1 1. The above figure shows the package top view. 56/228 DS11854 Rev 5 STM32F732xx STM32F733xx Pinouts and pin description PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 V DD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 Figure 21. STM32F733xx LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 with HS PHY 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 VDD VSS PH12 VCAP_1 VDD PH6 PH7 PH8 PH9 PH10 PH11 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 MS41082V1 1. The above figure shows the package top view. DS11854 Rev 5 57/228 98 Pinouts and pin description STM32F732xx STM32F733xx Figure 22. STM32F733xx UFBGA176 ballout 1 2 A PE3 PE2 B PE4 C 3 4 5 6 7 8 9 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 VBAT PI7 PI6 PI5 VDD 11 12 13 14 15 PB3 PD7 PC12 PA15 PA14 PA13 PG11 PG10 PD6 PD0 PC11 PC10 PA12 VDD SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 PDR_ON VDD BOOT0 VSS VSS 10 VCAP_1 MS39130V1 1. The above figure shows the package top view. 58/228 DS11854 Rev 5 STM32F732xx STM32F733xx Pinouts and pin description Figure 23. STM32F733xx UFBGA176 ballout (with OTG PHY HS) 1 2 A PE3 PE2 B PE4 C 3 4 5 6 7 8 9 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 VBAT PI7 PI6 PI5 VDD 11 12 13 14 15 PB3 PD7 PC12 PA15 PA14 PA13 PG11 PG10 PD6 PD0 PC11 PC10 PA12 VDD SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD VDD12 OTG_HS OTGHS _REXT K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 PDR_ON VDD BOOT0 VSS VSS 10 VCAP_1 MS42001V1 1. The above figure shows the package top view. DS11854 Rev 5 59/228 98 Pinouts and pin description STM32F732xx STM32F733xx Table 9. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5V tolerant I/O, I2C Fm+ option. TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT pin RST Bidirectional reset pin with weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 60/228 DS11854 Rev 5 Pin Number 1 PE2 I/O FT - - 2 2 A1 2 A10 A1 A2 2 2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - - 3 3 B1 3 D9 B1 B2 3 3 PE4 I/O FT - TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, EVENTOUT - - 4 4 B2 4 E8 B2 B3 4 4 PE5 I/O FT - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, EVENTOUT - - - LQFP176 1 LQFP144 A3 UFBGA144 A2 UFBGA176 C9 WLCSP100 1 LQFP176 A2 UFBGA176 1 LQFP144 1 LQFP100 - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT LQFP64 Alternate functions DS11854 Rev 5 - 5 5 B3 5 B10 B3 B4 5 5 PE6 I/O FT - TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCK_B, FMC_A22, EVENTOUT 1 6 6 C1 6 C10 C1 C2 6 6 VBAT S - - - Additional functions - 61/228 Pinouts and pin description Notes Pin name (function after reset)(1) I/O structure STM32F733xx Pin type STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition Pin Number LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 - D2 7 - D2 - - 7 PI8 I/O FT Notes UFBGA176 - I/O structure LQFP144 - Pin name (function after reset)(1) Pin type LQFP100 STM32F733xx LQFP64 STM32F732xx Alternate functions Additional functions EVENTOUT RTC_TAMP2/ RTC_TS, WKUP5 EVENTOUT RTC_TAMP1/ RTC_TS/ RTC_OUT, WKUP4 EVENTOUT OSC32_IN EVENTOUT OSC32_OUT (2) (3) (2) DS11854 Rev 5 2 3 4 7 8 9 7 8 9 D1 E1 F1 8 9 10 D10 E9 E10 D1 E1 F1 A1 B1 C1 7 8 9 8 PC13 9 PC14OSC32_IN(PC1 4) 10 I/O FT (3) Pinouts and pin description 62/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) (2) I/O FT (3) (5) (2) PC15OSC32_OUT(P C15) I/O FT (3) (5) - - D3 11 - D3 - - 11 PI9 I/O FT - UART4_RX, CAN1_RX, FMC_D30, EVENTOUT - - - - E3 12 - E3 - - 12 PI10 I/O FT - FMC_D31, EVENTOUT - - - - E4 13 - E4 - - 13 PI11 I/O FT (4) OTG_HS_ULPI_DIR, EVENTOUT WKUP6 - - - F2 14 - F2 - - 14 VSS S - - - - - - - F3 15 - F3 - - 15 VDD S - - - - STM32F732xx STM32F733xx - Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - - 10 E2 16 - E2 C3 10 16 PF0 I/O FTf - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 H3 17 - H3 C4 11 17 PF1 I/O FTf - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 H2 18 - H2 D4 12 18 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - 13 J2 19 - J2 E2 13 19 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - 14 J3 20 - J3 E3 14 20 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - 15 K3 21 - K3 E4 15 21 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 - 10 16 G2 22 F9 G2 D2 16 22 VSS S - - - - - 11 17 G3 23 F10 G3 D3 17 23 VDD S - - - - - TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, EVENTOUT ADC3_IN4 - TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT ADC3_IN5 - - - - 18 19 K2 K1 24 25 - - K2 K1 F3 F2 18 19 24 25 Pin name (function after reset)(1) PF6 PF7 I/O I/O FT FT Additional functions 63/228 Pinouts and pin description LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number - L3 26 - L3 G3 20 26 PF8 I/O I/O structure Pin type LQFP176 Pin name (function after reset)(1) LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 20 STM32F733xx FT DS11854 Rev 5 Notes - LQFP100 LQFP64 STM32F732xx Alternate functions Additional functions - SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 - SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_IN7 - - 21 L2 27 - L2 G2 21 27 PF9 I/O FT - - 22 L1 28 - L1 G1 22 28 PF10 I/O FT - EVENTOUT ADC3_IN8 FT (5) EVENTOUT OSC_IN EVENTOUT OSC_OUT 5 12 23 G1 29 G10 G1 D1 23 29 PH0-OSC_IN I/O 13 24 H1 30 H10 H1 E1 24 30 PH1-OSC_OUT I/O FT 7 14 25 J1 31 G9 J1 F1 25 31 NRST I/O RS T - - - 8 15 26 M2 32 F8 M2 H1 26 32 PC0 I/O FT (4) SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC1_IN10, ADC2_IN10, ADC3_IN10 - TRACED0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, EVENTOUT ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3, WKUP3 9 16 27 M3 33 H9 M3 H2 27 33 PC1 I/O FT STM32F732xx STM32F733xx 6 (5) Pinouts and pin description 64/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 10 17 28 M4 34 J10 M4 H3 28 34 PC2 I/O FT (4) SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT ADC1_IN12, ADC2_IN12, ADC3_IN12 11 18 29 M5 35 F7 M5 H4 29 35 PC3 I/O FT (4) SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT ADC1_IN13, ADC2_IN13, ADC3_IN13 - - 30 - 36 J7 - F10 30 36 VDD S - - - - 12 19 31 M1 37 K10 M1 J1 31 37 VSSA S - - - - - - - N1 - - N1 K1 - - VREF- S - - - - 13 20 32 P1 38 J9 P1 L1 32 38 VREF+ S - - - - - 21 33 R1 39 K9 R1 M1 33 39 VDDA S - - - - FT (6) TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI2_SD_B, EVENTOUT ADC1_IN0, ADC2_IN0, ADC3_IN0, WKUP1 14 22 34 N3 40 G8 N3 J2 34 40 Pin name (function after reset)(1) PA0-WKUP I/O Additional functions 65/228 Pinouts and pin description LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number DS11854 Rev 5 16 23 24 36 N2 P2 41 42 J8 H8 N2 P2 K2 L2 35 36 41 42 PA1 PA2 I/O I/O I/O structure Pin type LQFP176 Pin name (function after reset)(1) LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 35 STM32F733xx FT FT Notes 15 LQFP100 LQFP64 STM32F732xx Alternate functions Additional functions - TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCK_B, EVENTOUT ADC1_IN1, ADC2_IN1, ADC3_IN1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, EVENTOUT ADC1_IN2, ADC2_IN2, ADC3_IN2, WKUP2 - - - F4 43 - F4 - - 43 PH2 I/O FT - - - - G4 44 - G4 - - 44 PH3 I/O FT - QUADSPI_BK2_IO1, SAI2_MCK_B, FMC_SDNE0, EVENTOUT - - - - H4 45 - H4 - - 45 PH4 I/O FTf (4) I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - - J4 46 - J4 - - 46 PH5 I/O FTf - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - 17 25 37 R2 47 H7 R2 M2 37 47 PA3 I/O FT (4) TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, OTG_HS_ULPI_D0, EVENTOUT ADC1_IN3, ADC2_IN3, ADC3_IN3 18 26 38 - - K8 - G4 38 - VSS S - - - - - - - L4 48 - L4 H5 - 48 BYPASS_REG I FT - - - STM32F732xx STM32F733xx - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, FMC_SDCKE0, EVENTOUT Pinouts and pin description 66/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 39 K4 49 - K4 F4 39 49 20 28 40 N4 50 G7 N4 J3 40 50 VDD S PA4 I/O DS11854 Rev 5 Notes UFBGA176 27 I/O structure LQFP144 19 Pin name (function after reset)(1) Pin type LQFP100 STM32F733xx LQFP64 STM32F732xx Alternate functions Additional functions - - - - TTa - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, EVENTOUT ADC1_IN4, ADC2_IN4, DAC_OUT1 TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT ADC1_IN5, ADC2_IN5, DAC_OUT2 21 29 41 P4 51 F6 P4 K3 41 51 PA5 I/O TTa (4) 22 30 42 P3 52 G6 P3 L3 42 52 PA6 I/O FT - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, EVENTOUT ADC1_IN6, ADC2_IN6 ADC1_IN7, ADC2_IN7 31 43 R3 53 K7 R3 M3 43 53 PA7 I/O FT - 24 32 44 N5 54 H6 N5 J4 44 54 PC4 I/O FT - I2S1_MCK, FMC_SDNE0, EVENTOUT ADC1_IN14, ADC2_IN14 - 33 45 P5 55 J6 P5 K4 45 55 PC5 I/O FT - FMC_SDCKE0, EVENTOUT ADC1_IN15, ADC2_IN15 67/228 Pinouts and pin description 23 TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, FMC_SDNWE, EVENTOUT STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 25 34 46 R5 56 F5 R5 L4 46 56 PB0 I/O FT (4) TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, OTG_HS_ULPI_D1, EVENTOUT ADC1_IN8, ADC2_IN8 26 35 47 R4 57 G5 R4 M4 47 57 PB1 I/O FT (4) TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, EVENTOUT ADC1_IN9, ADC2_IN9 27 36 48 M6 58 K6 M6 J5 48 58 PB2 I/O FT - SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, EVENTOUT - - - 49 R6 59 - R6 M5 49 59 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, EVENTOUT - - - 50 P6 60 - P6 L5 50 60 PF12 I/O FT - FMC_A6, EVENTOUT - - - 51 M8 61 - M8 - 51 61 VSS S - - - - - - 52 N8 62 - N8 G5 52 62 VDD S - - - - - - 53 N6 63 - N6 K5 53 63 PF13 I/O FT - FMC_A7, EVENTOUT - - - 54 R7 64 - R7 M6 54 64 PF14 I/O FT - FMC_A8, EVENTOUT - - - 55 P7 65 - P7 L6 55 65 PF15 I/O FT - FMC_A9, EVENTOUT - - - 56 N7 66 - N7 K6 56 66 PG0 I/O FT - FMC_A10, EVENTOUT - - - 57 M7 67 - M7 J6 57 67 PG1 I/O FT - FMC_A11, EVENTOUT - Pin name (function after reset)(1) Additional functions STM32F732xx STM32F733xx LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx Pinouts and pin description 68/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - 37 58 R8 68 J5 R8 M7 58 68 PE7 I/O FT - TIM1_ETR, UART7_Rx, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT - - 38 59 P8 69 H5 P8 L7 59 69 PE8 I/O FT - TIM1_CH1N, UART7_Tx, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT - - 39 60 P9 70 K5 P9 K7 60 70 PE9 I/O FT - TIM1_CH1, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - - - 61 M9 71 - M9 H6 61 71 VSS S - - - - - - 62 N9 72 - N9 G6 62 72 VDD S - - - - - 40 63 R9 73 E4 R9 J7 63 73 PE10 I/O FT - TIM1_CH2N, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT - - 41 64 P10 74 G4 P10 H8 64 74 PE11 I/O FT - TIM1_CH2, SPI4_NSS, SAI2_SD_B, FMC_D8, EVENTOUT - - 42 65 R10 75 H4 R10 J8 65 75 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9, EVENTOUT - - 43 66 N11 76 J4 N11 K8 66 76 PE13 I/O FT - TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10, EVENTOUT - Pin name (function after reset)(1) Additional functions 69/228 Pinouts and pin description LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx - 44 67 P11 77 K4 P11 L8 67 77 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCK_B, FMC_D11,, EVENTOUT - - 45 68 R11 78 F4 R11 M8 68 78 PE15 I/O FT - TIM1_BKIN, FMC_D12, EVENTOUT - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - Pin name (function after reset)(1) Additional functions 46 69 R12 79 G3 R12 M9 69 79 PB10 I/O FTf 29 47 70 R13 80 H3 R13 M10 70 80 PB11 I/O FTf (4) TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, EVENTOUT - 30 48 71 M10 81 J3 M10 H7 71 81 VCAP_1 S - - - - 31 49 - - - K3 - - - - VSS S - - - - 32 50 72 N10 82 K2 N10 G7 72 82 VDD S - - - - - - - M11 83 - M11 - - 83 PH6 I/O FT - I2C2_SMBA, SPI5_SCK, TIM12_CH1, FMC_SDNE1, EVENTOUT - - - - N12 84 - N12 - - 84 PH7 I/O FTf - I2C3_SCL, SPI5_MISO, FMC_SDCKE1, EVENTOUT - - - - M12 85 - M12 - - 85 PH8 I/O FTf - I2C3_SDA, FMC_D16, EVENTOUT - STM32F732xx STM32F733xx 28 (4) Pinouts and pin description 70/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - - - M13 86 - M13 - - 86 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, EVENTOUT - - - - L13 87 - L13 - - 87 PH10 I/O FT - TIM5_CH1, FMC_D18, EVENTOUT - - - - L12 88 - L12 - - 88 PH11 I/O FT - TIM5_CH2, FMC_D19, EVENTOUT - - - - K12 89 - K12 - - 89 PH12 I/O FT - TIM5_CH3, FMC_D20, EVENTOUT - - - - H12 90 - H12 - - 90 VSS S - - - - - - - J12 91 K2 J12 - - 91 VDD S - - - - FT (4) TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - TIM1_CH1N, SPI2_SCK/I2S2_CK, (4) OTG_HS_VBUS USART3_CTS, OTG_HS_ULPI_D6, EVENTOUT 33 51 73 P12 92 J2 P12 M11 73 92 Pin name (function after reset)(1) PB12 I/O 34 52 74 P13 93 H2 P13 M12 74 93 PB13 I/O FT - - - - - G2 J15 H11 75 94 OTG_HS_REXT - - - - - - - - G1 J14 H10 76 95 VDD12OTGHS - - - Additional functions USB HS OTG PHY calibration resistor - - 71/228 Pinouts and pin description LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number - - PB14 I/O FT - - - - - - J1 R14 L11 77 96 PB14 I/O FT - OTG_HS_DM - - LQFP176 - LQFP144 - UFBGA144 - UFBGA176 94 WLCSP100 R14 LQFP176 75 UFBGA176 53 LQFP144 35 TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, SDMMC2_D0, OTG_HS_DM, EVENTOUT LQFP100 Alternate functions LQFP64 Notes Pin name (function after reset)(1) I/O structure STM32F733xx Pin type STM32F732xx Additional functions - DS11854 Rev 5 54 76 R15 95 - - - - - PB15 I/O FT - - - - - - H1 R15 L12 78 97 PB15 I/O FT - OTG_HS_DP - - 55 77 P15 96 - P15 L9 79 98 PD8 I/O FT - USART3_TX, FMC_D13, EVENTOUT - - 56 78 P14 97 - P14 K9 80 99 PD9 I/O FT - USART3_RX, FMC_D14, EVENTOUT - - 57 79 N15 98 - N15 J9 81 100 PD10 I/O FT - USART3_CK, FMC_D15, EVENTOUT - STM32F732xx STM32F733xx 36 RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, SDMMC2_D1, OTG_HS_DP, EVENTOUT Pinouts and pin description 72/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number DS11854 Rev 5 - 58 59 81 N14 99 N13 100 F3 F2 N14 N13 H9 L10 82 83 101 102 PD11 PD12 I/O I/O I/O structure Pin type LQFP176 Pin name (function after reset)(1) LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 80 STM32F733xx FT FT Notes - LQFP100 LQFP64 STM32F732xx Alternate functions Additional functions - USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - TIM4_CH1, LPTIM1_IN1, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT - - 103 PD13 I/O FT - G8 85 104 VSS S - - - - F8 86 105 VDD S - - - - F1 M14 K11 87 106 PD14 I/O FT - TIM4_CH3, UART8_CTS, FMC_D0, EVENTOUT - 105 E2 L14 K12 88 107 PD15 I/O FT - TIM4_CH4, UART8_RTS, FMC_D1, EVENTOUT - L15 106 - L15 J12 89 108 PG2 I/O FT - FMC_A12, EVENTOUT - K15 107 - K15 J11 90 109 PG3 I/O FT - FMC_A13, EVENTOUT - - 60 82 M15 101 E3 M15 K10 - - 83 - 102 - - - - 84 J13 103 - J13 - 61 85 M14 104 - 62 86 L14 - - 87 - - 88 73/228 Pinouts and pin description 84 TIM4_CH2, LPTIM1_OUT, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - - 89 K14 108 - K14 J10 91 110 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - 90 K13 109 - K13 H12 92 111 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - 91 J15 110 - - - - - PG6 I/O FT - EVENTOUT - - - 92 J14 111 - - - - - PG7 I/O FT - USART6_CK, FMC_INT, EVENTOUT - - - 93 H14 112 - H14 G11 93 112 PG8 I/O FT - USART6_RTS, FMC_SDCLK, EVENTOUT - - - 94 G12 113 - G12 - 94 113 VSS S - - - - - - - - - - - F10 - - VDD - - - - - - - 95 H13 114 K1 95 114 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC2_D6, SDMMC1_D6, EVENTOUT - - TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC2_D7, SDMMC1_D7, EVENTOUT - 37 38 63 64 96 97 H15 115 G15 116 E1 D4 H13 C11 H15 G12 G15 F12 96 97 115 116 Pin name (function after reset)(1) PC6 PC7 I/O I/O FT FT Additional functions STM32F732xx STM32F733xx LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx Pinouts and pin description 74/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number 65 G14 117 D2 G14 F11 98 117 PC8 I/O I/O structure Pin type LQFP176 Pin name (function after reset)(1) LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 98 STM32F733xx FT DS11854 Rev 5 Notes 39 LQFP100 LQFP64 STM32F732xx Alternate functions Additional functions - TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDMMC1_D0, EVENTOUT - - 66 99 F14 118 D1 F14 E11 99 118 PC9 I/O FTf - 41 67 100 F15 119 D3 F15 E12 100 119 PA8 I/O FTf - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT - 42 68 101 E15 120 C3 E15 D12 101 120 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, EVENTOUT OTG_FS_VBUS 43 69 102 D15 121 C2 D15 D11 102 121 PA10 I/O FT - TIM1_CH3, USART1_RX, OTG_FS_ID, EVENTOUT - 44 70 103 C15 122 C1 C15 C12 103 122 PA11 I/O FT - TIM1_CH4, USART1_CTS, CAN1_RX, OTG_FS_DM, EVENTOUT - 45 71 104 B15 123 B2 B15 B12 104 123 PA12 I/O FT - TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, EVENTOUT - 46 72 105 A15 124 B1 A15 A12 105 124 PA13(JTMSSWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - Pinouts and pin description 75/228 40 MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, EVENTOUT STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - 73 106 F13 125 B3 F13 G9 106 125 VCAP_2 S - - - - 47 74 107 F12 126 A2 F12 G10 107 126 VSS S - - - - 48 75 108 G13 127 A1 G13 F9 108 127 VDD S - - - - - - - E12 128 - E12 - - 128 PH13 I/O FT - TIM8_CH1N, UART4_TX, CAN1_TX, FMC_D21, EVENTOUT - - - - E13 129 - E13 - - 129 PH14 I/O FT - TIM8_CH2N, UART4_RX, CAN1_RX, FMC_D22, EVENTOUT - - - - D13 130 - D13 - - 130 PH15 I/O FT - TIM8_CH3N, FMC_D23, EVENTOUT - - - - E14 131 - E14 - - 131 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, EVENTOUT - - - - D14 132 - D14 - - 132 PI1 I/O FT - TIM8_BKIN2, SPI2_SCK/I2S2_CK, FMC_D25, EVENTOUT - - - - C14 133 - C14 - - 133 PI2 I/O FT - TIM8_CH4, SPI2_MISO, FMC_D26, EVENTOUT - - - - C13 134 - C13 - - 134 PI3 I/O FT - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, EVENTOUT - - - - D9 - D9 - - 135 VSS S - - - - 135 Pin name (function after reset)(1) Additional functions STM32F732xx STM32F733xx LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx Pinouts and pin description 76/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number I/O structure Notes - C9 136 - C9 - - 136 VDD S - - - - 109 A14 137 C4 A14 A11 109 137 PA14(JTCKSWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT - - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, EVENTOUT - - SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, EVENTOUT - - 110 111 112 A13 B14 B13 138 139 140 B4 A3 C5 A13 B14 B13 A10 B11 B10 110 111 112 138 139 140 Pin name (function after reset)(1) PA15(JTDI) PC10 PC11 I/O I/O I/O FT FT FT Additional functions 53 80 113 A12 141 D5 A12 C10 113 141 PC12 I/O FT - TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK, EVENTOUT - 81 114 B12 142 B5 B12 E10 114 142 PD0 I/O FT - CAN1_RX, FMC_D2, EVENTOUT - - 82 115 C12 143 A4 C12 D10 115 143 PD1 I/O FT - CAN1_TX, FMC_D3, EVENTOUT - 77/228 Pinouts and pin description Pin type 79 LQFP176 52 78 LQFP144 51 77 UFBGA144 DS11854 Rev 5 50 UFBGA176 76 WLCSP100 49 LQFP176 - Alternate functions UFBGA176 LQFP100 - STM32F733xx LQFP144 LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number WLCSP100 UFBGA176 UFBGA144 LQFP176 Pin type I/O structure Notes LQFP144 83 116 D12 144 E5 D12 E9 116 144 PD2 I/O FT - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, EVENTOUT - - 84 117 145 C6 D11 D9 117 145 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, EVENTOUT - - 85 118 D10 146 B6 D10 C9 118 146 PD4 I/O FT - USART2_RTS, FMC_NOE, EVENTOUT - - 86 119 C11 147 A5 C11 B9 119 147 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - 120 D8 148 - D8 E7 120 148 VSS S - - - - - - 121 C8 149 - C8 F7 121 149 VDDSDMMC S - - - - - D11 LQFP176 54 UFBGA176 LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx Pin name (function after reset)(1) Additional functions 87 122 B11 150 D6 B11 A8 122 150 PD6 I/O FT - - 88 123 A11 151 E6 A11 A9 123 151 PD7 I/O FT - USART2_CK SDMMC2_CMD, FMC_NE1, EVENTOUT - - USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, EVENTOUT - - - 124 C10 152 - C10 E8 124 152 PG9 I/O FT STM32F732xx STM32F733xx - SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, SDMMC2_CK, FMC_NWAIT, EVENTOUT Pinouts and pin description 78/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number WLCSP100 UFBGA176 UFBGA144 LQFP176 Pin type I/O structure Notes LQFP144 125 B10 153 - B10 D8 125 153 PG10 I/O FT - SAI2_SD_B, SDMMC2_D1, FMC_NE3, EVENTOUT - - - 126 B9 154 - B9 C8 126 154 PG11 I/O FT - SDMMC2_D2, FMC_INT, EVENTOUT - - - 127 B8 155 - B8 B8 127 155 PG12 I/O FT - LPTIM1_IN1, USART6_RTS, SDMMC2_D3, FMC_NE4, EVENTOUT - - - 128 A8 156 - A8 D7 128 156 PG13 I/O FT - TRACED0, LPTIM1_OUT, USART6_CTS, FMC_A24, EVENTOUT - - - UFBGA176 - LQFP144 - Pin name (function after reset)(1) - - 129 A7 157 - A7 C7 129 157 PG14 I/O FT - TRACED1, LPTIM1_ETR, USART6_TX, QUADSPI_BK2_IO3, FMC_A25, EVENTOUT - - 130 D7 158 - D7 - 130 158 VSS S - - - Additional functions Pinouts and pin description 79/228 LQFP176 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - - 131 C7 159 - C7 F6 131 159 VDD S - - - - - - 132 B7 160 - B7 B7 132 160 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, EVENTOUT - 161 PB3(JTDO/TRA CESWO) - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SDMMC2_D2, EVENTOUT - - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, SDMMC2_D3, EVENTOUT - (4) TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, OTG_HS_ULPI_D7, FMC_SDCKE1, EVENTOUT - - TIM4_CH1, I2C1_SCL, USART1_TX, QUAD SPI_BK1_NCS, FMC_SDNE1, EVENTOUT - 55 56 57 58 89 90 91 92 133 A10 134 135 136 A9 A6 B6 161 162 163 164 A6 B7 C7 D7 A10 A9 A6 B6 A7 A6 B6 C6 133 134 135 136 162 163 164 Pin name (function after reset)(1) PB4(NJTRST) PB5 PB6 I/O I/O I/O I/O FT FT FT FTf Additional functions STM32F732xx STM32F733xx LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx Pinouts and pin description 80/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx 59 93 137 B5 165 B8 B5 D6 137 165 PB7 I/O FTf - TIM4_CH2, I2C1_SDA, USART1_RX, FMC_NL, EVENTOUT - 60 94 138 D6 166 A7 D6 D5 138 166 BOOT I B - - VPP - TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDMMC2_D4, SDMMC1_D4, EVENTOUT - - 61 95 139 A5 167 C8 A5 C5 139 167 Pin name (function after reset)(1) PB8 I/O FTf Additional functions 96 140 B4 168 D8 B4 B5 140 168 PB9 I/O FTf - - 97 141 A4 169 E7 A4 A5 141 169 PE0 I/O FT - TIM4_ETR, LPTIM1_ETR, UART8_Rx, SAI2_MCK_A, FMC_NBL0, EVENTOUT - - 98 142 A3 170 B9 A3 A4 142 170 PE1 I/O FT - LPTIM1_IN2, UART8_Tx, FMC_NBL1, EVENTOUT - 63 99 - D5 - A8 D5 E6 - - VSS S - - - - Pinouts and pin description 81/228 62 TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDMMC2_D5, SDMMC1_D5, EVENTOUT STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number Notes 172 A9 C5 F5 144 172 VDD S - - - - LQFP176 C5 LQFP144 100 144 UFBGA144 - UFBGA176 - WLCSP100 - LQFP176 - UFBGA176 S LQFP144 PDR_ON LQFP100 Alternate functions LQFP64 I/O structure STM32F733xx Pin type STM32F732xx - - 143 C6 171 - C6 E5 143 171 64 Pin name (function after reset)(1) Additional functions DS11854 Rev 5 - - D4 173 - D4 - - 173 PI4 I/O FT - TIM8_BKIN, SAI2_MCK_A, FMC_NBL2, EVENTOUT - - - - C4 174 - C4 - - 174 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, EVENTOUT - - - - C3 175 - C3 - - 175 PI6 I/O FT - TIM8_CH2, SAI2_SD_A, FMC_D28, EVENTOUT - - - - C2 176 - C2 - - 176 PI7 I/O FT - TIM8_CH3, SAI2_FS_A, FMC_D29, EVENTOUT - - - - F6 - - F6 - - - VSS S - - - - - - - F7 - - F7 - - - VSS S - - - - - - - F8 - - F8 - - - VSS S - - - - - - - F9 - - F9 - - - VSS S - - - - - - - F10 - - F10 - - - VSS S - - - - STM32F732xx STM32F733xx - Pinouts and pin description 82/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes LQFP176 - - - G6 - - G6 - - - VSS S - - - - - - - G7 - - G7 - - - VSS S - - - - - - - G8 - - G8 - - - VSS S - - - - - - - G9 - - G9 - - - VSS S - - - - - - - G10 - - G10 - - - VSS S - - - - - - - H6 - - H6 - - - VSS S - - - - - - - H7 - - H7 - - - VSS S - - - - - - - H8 - - H8 - - - VSS S - - - - - - - H9 - - H9 - - - VSS S - - - - - - - H10 - - H10 - - - VSS S - - - - - - - J6 - - J6 - - - VSS S - - - - - - - J7 - - J7 - - - VSS S - - - - - - - J8 - - J8 - - - VSS S - - - - - - - J9 - - J9 - - - VSS S - - - - - - - J10 - - J10 - - - VSS S - - - - - - - K6 - - K6 - - - VSS S - - - - - - - K7 - - K7 - - - VSS S - - - - - - - K8 - - K8 - - - VSS S - - - - Pin name (function after reset)(1) Additional functions 83/228 Pinouts and pin description LQFP144 DS11854 Rev 5 Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx STM32F732xx STM32F733xx Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 I/O structure Notes LQFP144 Pin type Alternate functions LQFP100 STM32F733xx LQFP64 STM32F732xx - - - K9 - - K9 - - - VSS S - - - - - - - K10 - - K10 - - - VSS S - - - - Pin name (function after reset)(1) Additional functions Pinouts and pin description 84/228 Table 10. STM32F732xx and STM32F733xx pin and ball definition (continued) 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: DS11854 Rev 5 - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). 4. ULPI signals not available on the STM32F733xx devices. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). STM32F732xx STM32F733xx STM32F732xx STM32F733xx Pinouts and pin description Table 11. FMC pin definition Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF0 A0 - - A0 PF1 A1 - - A1 PF2 A2 - - A2 PF3 A3 - - A3 PF4 A4 - - A4 PF5 A5 - - A5 PF12 A6 - - A6 PF13 A7 - - A7 PF14 A8 - - A8 PF15 A9 - - A9 PG0 A10 - - A10 PG1 A11 - - A11 PG2 A12 - - A12 PG3 A13 - - - PG4 A14 - - BA0 PG5 A15 - - BA1 PD11 A16 A16 CLE - PD12 A17 A17 ALE - PD13 A18 A18 - - PE3 A19 A19 - - PE4 A20 A20 - - PE5 A21 A21 - - PE6 A22 A22 - - PE2 A23 A23 - - PG13 A24 A24 - - PG14 A25 A25 - - PD14 D0 DA0 D0 D0 PD15 D1 DA1 D1 D1 PD0 D2 DA2 D2 D2 PD1 D3 DA3 D3 D3 PE7 D4 DA4 D4 D4 PE8 D5 DA5 D5 D5 PE9 D6 DA6 D6 D6 PE10 D7 DA7 D7 D7 DS11854 Rev 5 85/228 98 Pinouts and pin description STM32F732xx STM32F733xx Table 11. FMC pin definition (continued) 86/228 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PE11 D8 DA8 D8 D8 PE12 D9 DA9 D9 D9 PE13 D10 DA10 D10 D10 PE14 D11 DA11 D11 D11 PE15 D12 DA12 D12 D12 PD8 D13 DA13 D13 D13 PD9 D14 DA14 D14 D14 PD10 D15 DA15 D15 D15 PH8 D16 - - D16 PH9 D17 - - D17 PH10 D18 - - D18 PH11 D19 - - D19 PH12 D20 - - D20 PH13 D21 - - D21 PH14 D22 - - D22 PH15 D23 - - D23 PI0 D24 - - D24 PI1 D25 - - D25 PI2 D26 - - D26 PI3 D27 - - D27 PI6 D28 - - D28 PI7 D29 - - D29 PI9 D30 - - D30 PI10 D31 - - D31 PD7 NE1 NE1 - - PG9 NE2 NE2 NCE - PG10 NE3 NE3 - - PG11 - - - - PG12 NE4 NE4 - - PD3 CLK CLK - - PD4 NOE NOE NOE - PD5 NWE NWE NWE - PD6 NWAIT NWAIT NWAIT - PB7 NADV NADV - - DS11854 Rev 5 STM32F732xx STM32F733xx Pinouts and pin description Table 11. FMC pin definition (continued) Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF6 - - - - PF7 - - - - PF8 - - - - PF9 - - - - PF10 - - - - PG6 - - - - PG7 - - INT - PE0 NBL0 NBL0 - NBL0 PE1 NBL1 NBL1 - NBL1 PI4 NBL2 - - NBL2 PI5 NBL3 - - NBL3 PG8 - - - SDCLK PC0 - - - SDNWE PF11 - - - SDNRAS PG15 - - - SDNCAS PH2 - - - SDCKE0 PH3 - - - SDNE0 PH6 - - - SDNE1 PH7 - - - SDCKE1 PH5 - - - SDNWE PC2 - - - SDNE0 PC3 - - - SDCKE0 PB5 - - - SDCKE1 PB6 - - - SDNE1 DS11854 Rev 5 87/228 98 AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 Port SYS DS11854 Rev 5 Port A TIM1/2 AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ 6/UART4/5/7/ ADSPI/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS - TIM2_CH1 /TIM2_ET TIM5_CH1 R TIM8_ETR - - - USART2_CT S UART4_ TX - SAI2_SD_B - - EVEN TOUT PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RT S UART4_RX QUADSPI_ BK1_IO3 SAI2_MCK _B - - EVEN TOUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SAI2_SCK_B - - - - EVEN TOUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - OTG_HS_U LPI_D0 - - EVEN TOUT PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK /I2S1_WS /I2S3_WS - - - - OTG_HS_ SOF EVEN TOUT PA5 - TIM2_CH1 /TIM2_ET R - TIM8_CH1 N - SPI1_SCK /I2S1_CK - - - - OTG_HS_U LPI_CK - - EVEN TOUT PA6 - TIM1_BKI N TIM3_CH1 TIM8_BKIN - SPI1_MIS O - - - TIM13_CH1 - - - EVEN TOUT PA7 - TIM1_CH1 TIM3_CH2 N TIM8_CH1 N - SPI1_MO SI/I2S1_S D - - - TIM14_CH1 - - FMC_SDN WE EVEN TOUT PA8 MCO1 TIM1_CH1 - TIM8_BKIN 2 I2C3_SCL - - USART1_CK - - OTG_FS_S OF - - EVEN TOUT PA9 - TIM1_CH2 - - I2C3_SMB A SPI2_SCK /I2S2_CK - USART1_TX - - - - - EVEN TOUT PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_I D - - EVEN TOUT PA11 - TIM1_CH4 - - - - - USART1_CT S - CAN1_RX OTG_FS_D M - - EVEN TOUT STM32F732xx STM32F733xx PA0 Pinouts and pin description 88/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PA12 - TIM1_ETR - - - - - USART1_RT S SAI2_FS_B CAN1_TX OTG_FS_D P - - EVEN TOUT PA13 JTMSSWDIO - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCLK - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_CH1 /TIM2_ET R - - - - UART4_RTS - - - - EVEN TOUT PB0 - TIM1_CH2 TIM3_CH3 N TIM8_CH2 N - - - - UART4_CTS - OTG_HS_U LPI_D1 - - EVEN TOUT PB1 - TIM1_CH3 TIM3_CH4 N TIM8_CH3 N - - - - - - OTG_HS_U LPI_D2 - - EVEN TOUT PB2 - - - - - - SAI1_SD_ A SPI3_MOSI/I 2S3_SD - QUADSPI_ CLK - - - EVEN TOUT PB3 JTDO/TR ACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK /I2S1_CK /I2S3_CK - - - SDMMC2_ D2 - - EVEN TOUT PB4 NJTRST - TIM3_CH1 - - SPI1_MIS O SPI3_MIS O SPI2_NSS/I2 S2_WS - - SDMMC2_ D3 - - EVEN TOUT PB5 - - TIM3_CH2 - I2C1_SMB A SPI1_MO SI/I2S1_S D SPI3_MO SI/I2S3_S D - - - OTG_HS_U LPI_D7 - FMC_SDC KE1 EVEN TOUT PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - QUADSPI_ BK1_NCS - FMC_SDN E1 EVEN TOUT PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - - FMC_NL EVEN TOUT PB8 - - TIM4_CH3 TIM10_CH 1 I2C1_SCL - - - - CAN1_RX SDMMC2_ D4 - SDMMC1 _D4 EVEN TOUT SPI1_NSS SPI3_NSS /I2S1_WS /I2S3_WS DS11854 Rev 5 89/228 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 Port A Port B AF5 STM32F732xx STM32F733xx Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS /I2S2_WS - - - CAN1_TX Port Port B AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS SDMMC2_ D5 - SDMMC1 _D5 EVEN TOUT DS11854 Rev 5 SYS TIM1/2 PB9 - - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK /I2S2_CK - USART3_TX - - OTG_HS_U LPI_D3 - - EVEN TOUT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - OTG_HS_U LPI_D4 - - EVEN TOUT PB12 - TIM1_BKI N - - I2C2_SMB A SPI2_NSS /I2S2_WS - USART3_CK - - OTG_HS_U LPI_D5 - OTG_HS_ ID EVEN TOUT PB13 - TIM1_CH1 N - - - SPI2_SCK /I2S2_CK - USART3_CT S - - OTG_HS_U LPI_D6 - - EVEN TOUT PB14 - TIM1_CH2 N - TIM8_CH2 N - SPI2_MIS O - USART3_RT S - TIM12_CH1 SDMMC2_ D0 - OTG_HS_ DM EVEN TOUT RTC_REF TIM1_CH3 IN N - TIM8_CH3 N - SPI2_MO SI/I2S2_S D - - - TIM12_CH2 SDMMC2_ D1 - OTG_HS_ DP EVEN TOUT PB15 - - - - - - - - SAI2_FS_B - OTG_HS_U LPI_STP - FMC_SDN WE EVEN TOUT PC1 TRACED0 - - - - SPI2_MO SI/I2S2_S D SAI1_SD_ A - - - - - - EVEN TOUT PC2 - - - - - SPI2_MIS O - - - - OTG_HS_U LPI_DIR - FMC_SDN E0 EVEN TOUT PC3 - - - - - SPI2_MO SI/I2S2_S D - - - - OTG_HS_U LPI_NXT - FMC_SDC KE0 EVEN TOUT Port C STM32F732xx STM32F733xx PC0 Pinouts and pin description 90/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS11854 Rev 5 TIM1/2 TIM3/4/5 PC4 - - - - - I2S1_MCK - - - - - - FMC_SDN E0 EVEN TOUT PC5 - - - - - - - - - - - - FMC_SDC KE0 EVEN TOUT PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - SDMMC2_ D6 - SDMMC1 _D6 EVEN TOUT PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - SDMMC2_ D7 - SDMMC1 _D7 EVEN TOUT PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6_CK - - - SDMMC1 _D0 EVEN TOUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - UART5_CTS - QUADSPI_ BK1_IO0 - - SDMMC1 _D1 EVEN TOUT PC10 - - - - - - SPI3_SCK /I2S3_CK USART3_TX UART4_TX QUADSPI_ BK1_IO1 - - SDMMC1 _D2 EVEN TOUT PC11 - - - - - - SPI3_MIS O USART3_RX UART4_RX QUADSPI_ BK2_NCS - - SDMMC1 _D3 EVEN TOUT PC12 TRACED3 - - - - - SPI3_MO SI/I2S3_S D USART3_CK UART5_TX - - - SDMMC1 _CK EVEN TOUT PC13 - - - - - - - - - - - - - EVEN TOUT PC14 - - - - - - - - - - - - - EVEN TOUT PC15 - - - - - - - - - - - - - EVEN TOUT Port C 91/228 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F732xx STM32F733xx Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS11854 Rev 5 TIM1/2 TIM3/4/5 PD0 - - - - - - - - - CAN1_RX - - FMC_D2 EVEN TOUT PD1 - - - - - - - - - CAN1_TX - - FMC_D3 EVEN TOUT PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1 _CMD EVEN TOUT PD3 - - - - - SPI2_SCK /I2S2_CK - USART2_CT S - - - - FMC_CLK EVEN TOUT PD4 - - - - - - - USART2_RT S - - - - FMC_NO E EVEN TOUT PD5 - - - - - - - USART2_TX - - - - FMC_NW E EVEN TOUT PD6 - - - - - SPI3_MO SI/I2S3_S D SAI1_SD_ A USART2_RX - - - SDMMC2 _CK FMC_NW AIT EVEN TOUT PD7 - - - - - - - USART2_CK - - - SDMMC2 _CMD FMC_NE1 EVEN TOUT PD8 - - - - - - - USART3_TX - - - - FMC_D13 EVEN TOUT PD9 - - - - - - - USART3_RX - - - - FMC_D14 EVEN TOUT PD10 - - - - - - - USART3_CK - - - - FMC_D15 EVEN TOUT PD11 - - - - - - - USART3_CT S - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16/ FMC_CLE EVEN TOUT PD12 - - TIM4_CH1 LPTIM1_IN 1 - - - USART3_RT S - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17/ FMC_ALE EVEN TOUT PD13 - - TIM4_CH2 LPTIM1_O UT - - - - - QUADSPI_ BK1_IO3 SAI2_SCK_ A - FMC_A18 EVEN TOUT PD14 - - TIM4_CH3 - - - - - UART8_CTS - - - FMC_D0 EVEN TOUT PD15 - - TIM4_CH4 - - - - - UART8_RTS - - - FMC_D1 EVEN TOUT Port D Port D STM32F732xx STM32F733xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 92/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS11854 Rev 5 TIM1/2 TIM3/4/5 PE0 - - TIM4_ETR LPTIM1_ET R - - - - UART8_Rx - SAI2_MCK _A - FMC_NBL 0 EVEN TOUT PE1 - - - LPTIM1_IN 2 - - - - UART8_Tx - - - FMC_NBL 1 EVEN TOUT PE2 TRACECL K - - - - SPI4_SCK SAI1_MCL K_A - - QUADSPI_ BK1_IO2 - - FMC_A23 EVEN TOUT PE3 TRACED0 - - - - - SAI1_SD_ B - - - - - FMC_A19 EVEN TOUT PE4 TRACED1 - - - - SPI4_NSS SAI1_FS_ A - - - - - FMC_A20 EVEN TOUT PE5 TRACED2 - - TIM9_CH1 - SPI4_MIS O SAI1_SCK _A - - - - - FMC_A21 EVEN TOUT PE6 TRACED3 TIM1_BKI N2 - TIM9_CH2 - SPI4_MO SI SAI1_SD_ A - - - SAI2_MCK _B - FMC_A22 EVEN TOUT PE7 - TIM1_ETR - - - - - - UART7_Rx - QUADSPI_ BK2_IO0 - FMC_D4 EVEN TOUT PE8 - TIM1_CH1 N - - - - - - UART7_Tx - QUADSPI_ BK2_IO1 - FMC_D5 EVEN TOUT PE9 - TIM1_CH1 - - - - - - UART7_RTS - QUADSPI_ BK2_IO2 - FMC_D6 EVEN TOUT PE10 - TIM1_CH2 N - - - - - - UART7_CTS - QUADSPI_ BK2_IO3 - FMC_D7 EVEN TOUT PE11 - TIM1_CH2 - - - SPI4_NSS - - - - SAI2_SD_B - FMC_D8 EVEN TOUT PE12 - TIM1_CH3 N - - - SPI4_SCK - - - - SAI2_SCK_ B - FMC_D9 EVEN TOUT PE13 - TIM1_CH3 - - - SPI4_MIS O - - - - SAI2_FS_B - FMC_D10 EVEN TOUT PE14 - TIM1_CH4 - - - SPI4_MO SI - - - - SAI2_MCK _B - FMC_D11 EVEN TOUT PE15 - TIM1_BKI N - - - - - - - - - - FMC_D12 EVEN TOUT Port E Port E 93/228 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F732xx STM32F733xx Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DS11854 Rev 5 Port F AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 EVEN TOUT PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 EVEN TOUT PF2 - - - - I2C2_SMB A - - - - - - - FMC_A2 EVEN TOUT PF3 - - - - - - - - - - - - FMC_A3 EVEN TOUT PF4 - - - - - - - - - - - - FMC_A4 EVEN TOUT PF5 - - - - - - - - - - - - FMC_A5 EVEN TOUT PF6 - - - TIM10_CH 1 - SPI5_NSS SAI1_SD_ B - UART7_Rx QUADSPI_ BK1_IO3 - - - EVEN TOUT PF7 - - - TIM11_CH1 - SPI5_SCK SAI1_MCL K_B - UART7_Tx QUADSPI_ BK1_IO2 - - - EVEN TOUT PF8 - - - - - SPI5_MIS O SAI1_SCK _B - UART7_RTS TIM13_CH1 QUADSPI_ BK1_IO0 - - EVEN TOUT PF9 - - - - - SPI5_MO SI SAI1_FS_ B - UART7_CTS TIM14_CH1 QUADSPI_ BK1_IO1 - - EVEN TOUT PF10 - - - - - - - - - - - - - EVEN TOUT PF11 - - - - - SPI5_MO SI - - - - SAI2_SD_B - FMC_SDN RAS EVEN TOUT PF12 - - - - - - - - - - - - FMC_A6 EVEN TOUT PF13 - - - - - - - - - - - - FMC_A7 EVEN TOUT PF14 - - - - - - - - - - - - FMC_A8 EVEN TOUT PF15 - - - - - - - - - - - - FMC_A9 EVEN TOUT STM32F732xx STM32F733xx Port F AF5 Pinouts and pin description 94/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DS11854 Rev 5 Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PG0 - - - - - - - - - - - - FMC_A10 EVEN TOUT PG1 - - - - - - - - - - - - FMC_A11 EVEN TOUT PG2 - - - - - - - - - - - - FMC_A12 EVEN TOUT PG3 - - - - - - - - - - - - FMC_A13 EVEN TOUT PG4 - - - - - - - - - - - - FMC_A14/ FMC_BA0 EVEN TOUT PG5 - - - - - - - - - - - - FMC_A15/ FMC_BA1 EVEN TOUT PG6 - - - - - - - - - - - - - EVEN TOUT PG7 - - - - - - - - USART6_CK - - - FMC_INT EVEN TOUT PG8 - - - - - - - - USART6_RT S - - - FMC_SDC LK EVEN TOUT PG9 - - - - - - - - USART6_RX QUADSPI_ BK2_IO2 SAI2_FS_B SDMMC2 _D0 FMC_NE2 /FMC_NC E EVEN TOUT PG10 - - - - - - - - - - SAI2_SD_B SDMMC2 _D1 FMC_NE3 EVEN TOUT 95/228 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F732xx STM32F733xx Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS11854 Rev 5 TIM1/2 TIM3/4/5 PG11 - - - - - - - - - - SDMMC2_ D2 - - EVEN TOUT PG12 - - - LPTIM1_IN 1 - - - - USART6_RT S - - SDMMC2 _D3 FMC_NE4 EVEN TOUT PG13 TRACED0 - - LPTIM1_O UT - - - - USART6_CT S - - - FMC_A24 EVEN TOUT PG14 TRACED1 - - LPTIM1_ET R - - - - USART6_TX QUADSPI_ BK2_IO3 - - FMC_A25 EVEN TOUT PG15 - - - - - - - - USART6_CT S - - - FMC_SDN CAS EVEN TOUT PH0 - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - EVEN TOUT PH2 - - - LPTIM1_IN 2 - - - - - QUADSPI_ BK2_IO0 SAI2_SCK_ B - FMC_SDC KE0 EVEN TOUT PH3 - - - - - - - - - QUADSPI_ BK2_IO1 SAI2_MCK _B - FMC_SDN E0 EVEN TOUT PH4 - - - - I2C2_SCL - - - - - OTG_HS_U LPI_NXT - - EVEN TOUT PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN WE EVEN TOUT PH6 - - - - I2C2_SMB A SPI5_SCK - - - TIM12_CH1 - - FMC_SDN E1 EVEN TOUT PH7 - - - - I2C3_SCL SPI5_MIS O - - - - - - FMC_SDC KE1 EVEN TOUT Port H STM32F732xx STM32F733xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 96/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 EVEN TOUT PH9 - - - - I2C3_SMB A - - - - TIM12_CH2 - - FMC_D17 EVEN TOUT PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 EVEN TOUT PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 EVEN TOUT PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 EVEN TOUT PH13 - - - TIM8_CH1 N - - - - UART4_TX CAN1_TX - - FMC_D21 EVEN TOUT PH14 - - - TIM8_CH2 N - - - - UART4_RX CAN1_RX - - FMC_D22 EVEN TOUT PH15 - - - TIM8_CH3 N - - - - - - - - FMC_D23 EVEN TOUT PI0 - - TIM5_CH4 - - SPI2_NSS /I2S2_WS - - - - - - FMC_D24 EVEN TOUT PI1 - - - TIM8_BKIN 2 - SPI2_SCK /I2S2_CK - - - - - - FMC_D25 EVEN TOUT PI2 - - - TIM8_CH4 - SPI2_MIS O - - - - - - FMC_D26 EVEN TOUT PI3 - - - TIM8_ETR - SPI2_MO SI/I2S2_S D - - - - - - FMC_D27 EVEN TOUT PI4 - - - TIM8_BKIN - - - - - - SAI2_MCK _A - FMC_NBL 2 EVEN TOUT PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_ A - FMC_NBL 3 EVEN TOUT PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 EVEN TOUT Port H DS11854 Rev 5 Port I 97/228 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F732xx STM32F733xx Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port I AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS11854 Rev 5 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 EVEN TOUT PI8 - - - - - - - - - - - - - EVEN TOUT PI9 - - - - - - - - UART4_RX CAN1_RX - - FMC_D30 EVEN TOUT PI10 - - - - - - - - - - - - FMC_D31 EVEN TOUT PI11 - - - - - - - - - - OTG_HS_U LPI_DIR - - EVEN TOUT PI12 - - - - - - - - - - - - - EVEN TOUT PI13 - - - - - - - - - - - - - EVEN TOUT PI14 - - - - - - - - - - - - - EVEN TOUT PI15 - - - - - - - - - - - - - EVEN TOUT Pinouts and pin description 98/228 Table 12. STM32F732xx and STM32F733xx alternate function mapping (continued) STM32F732xx STM32F733xx STM32F732xx STM32F733xx 5 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. DS11854 Rev 5 99/228 99 Electrical characteristics 6 STM32F732xx STM32F733xx Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 24. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 25. Figure 24. Pin loading conditions Figure 25. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 100/228 DS11854 Rev 5 MS19010V2 STM32F732xx STM32F733xx Power supply scheme Figure 26. STM32F732xx power supply scheme VBAT GP I/Os IN V DDSDMMC V DDSDMMC OUT PG[9..12], PD[6,7] IN 2 × 2.2 μF VDD IO Logic IO Logic VCAP_1 VCAP_2 VDD 1/2/...11/12 12 × 100 nF + 1 × 4.7 μF Level shifter OUT 100 nF + 1 μF Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch VBAT = 1.65 to 3.6V Level shifter 6.1.6 Electrical characteristics Voltage regulator VSS 1/2/...11/12 Flash memory BYPASS_REG VDDUSB VDDUSB 100 nF + 1 μF PDR_ON VDD OTG FS PHY Reset controller VDDA VREF 100 nF + 1 μF Kernel logic (CPU, digital & RAM) 100 nF + 1 μF VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA MSv42076V2 1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 3. VDDA=VDD and VSSA=VSS. DS11854 Rev 5 101/228 200 Electrical characteristics STM32F732xx STM32F733xx Figure 27. STM32F733xx power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) OUT GP I/Os IN V DDSDMMC Level shifter Power switch VBAT = 1.65 to 3.6V IO Logic IN OUT PA[11,12], PB[14,15] VDDUSB IN VDDUSB Level shifter OUT PG[9..12], PD[6,7] Level shifter VDDSDMMC 100 nF + 1 μF IO Logic IO Logic 100 nF + 1 μF OTG FS PHY Kernel logic (CPU, digital & RAM) V CAP_1 2 × 2.2 μF V CAP_2 VDD V DD 1/2/...11/12 12 × 100 nF + 1 × 4.7 μF Voltage regulator VSS 1/2/...11/12 Flash memory BYPASS_REG OTG HS PHY voltage regulator VDD12OTGHS 2.2 μF 3 Kohm +/-1% PDR_ON VDD Reset controller VDDA VREF 100 nF + 1 μF OTG HS PHY OTG_HS_REXT 100 nF + 1 μF VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA MSv42069V1 1. In all the packages (except LQFP100), the VDDUSB allows supplying the PHY FS in PA11/PA12 and the PHY HS on PB14/PB15. In the LQFP100, the PHY HS on PB14/PB15 is supplied by VDDPHYHS. 102/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics 2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 28. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics, Table 14: Current characteristics, and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 13. Voltage characteristics Symbol VDD–VSS VIN Ratings Min Max − 0.3 4.0 Input voltage on FT pins(2) VSS − 0.3 VDD+4.0 Input voltage on TTa pins VSS − 0.3 4.0 Input voltage on any other pin VSS − 0.3 4.0 VSS 9.0 External main supply voltage (including VDDA, VDD, VBAT, VDDUSB, VDDPHYHS and VDDSDMMC) (1) Input voltage on BOOT pin DS11854 Rev 5 Unit V 103/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 13. Voltage characteristics (continued) Symbol |ΔVDDx| |VSSX −VSS| VESD(HBM) Ratings Min Max Variations between different VDD power pins - 50 Variations between all the different ground pins(3) - 50 Electrostatic discharge voltage (human body model) Unit mV see Section 6.3.18: Absolute maximum ratings (electrical sensitivity) - 1. All main power (VDD, VDDA, VDDSDMMC, VDDPHYHS, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current. 3. Include VREF- pin. Table 14. Current characteristics Symbol Ratings Max. ΣIVDD Total current into sum of all VDD_x power lines (source)(1) Σ IVSS (sink)(1) Total current out of sum of all VSS_x ground lines Σ IVDDUSB Σ IVDDSDMMC IVDDSDMMC 300 − 300 Total current into VDDUSB power line (source) 25 Total current into VDDSDMMC power line (source) Maximum current into each VDD_x power line IVDD 60 (source)(1) 100 Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] Maximum current out of each VSS_x ground line (sink)(1) IVSS 25 Total output current sunk by sum of all I/O and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 (2) Total output current sourced by sum of all I/Os and control pins IINJ(PIN) ΣIINJ(PIN) (4) Injected current on FT, FTf, RST and B pins (3) mA − 25 Output current sourced by any I/Os and control pin ΣIIO 100 − 100 Output current sunk by any I/O and control pin IIO Unit − 120 − 5/+0 Injected current on TTa pins(4) ±5 Total injected current (sum of all I/O and control pins)(5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN 2.4 V, the compensation cell should be used. Figure 44. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by CL specified in the table “ I/O AC characteristics”. ai14131d 152/228 DS11854 Rev 5 STM32F732xx STM32F733xx 6.3.21 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 61: I/O static characteristics). Unless otherwise specified, the parameters given in Table 64 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 64. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs VF(NRST) (2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 45. Recommended NRST pin protection VDD External reset circuit (1) NRST (2) RPU Internal Reset Filter 0.1 μF STM32F ai14132c 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 61. Otherwise the reset is not taken into account by the device. DS11854 Rev 5 153/228 200 Electrical characteristics 6.3.22 STM32F732xx STM32F733xx TIM timer characteristics The parameters given in Table 65 are guaranteed by design. Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 65. TIMx characteristics(1)(2) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 216 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 108 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 216 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 × 65536 tTIMxCLK Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. 6.3.23 RTC characteristics Table 66. RTC characteristics 6.3.24 Symbol Parameter Conditions - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register Min Max 4 - 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 16. Table 67. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions VDDA − VREF+ < 1.2 V (1) fADC 154/228 ADC clock frequency VDDA = 1.7 to 2.4 V VDDA = 2.4 to 3.6 V DS11854 Rev 5 Min Typ Max Unit 1.7(1) - 3.6 V 1.7(1) - VDDA V - 0 - V 0.6 15 18 MHz 0.6 30 36 MHz STM32F732xx STM32F733xx Electrical characteristics Table 67. ADC characteristics (continued) Symbol fTRIG(2) VAIN RAIN(2) Parameter External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 κΩ - 1.5 - 6 κΩ - - 4 7 pF - - 0.100 µs 1/fADC tlat(2) Injection trigger conversion latency fADC = 30 MHz - - - 3(5) tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs - - - 2(5) 1/fADC tS(2) Sampling time fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC tSTAB(2) Power-up time - 2 3 µs fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs tCONV(2) Total conversion time (including sampling time) - 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(2) (fADC = 36 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2.4 Msps 12-bit resolution Interleave Dual ADC mode - - 4.5 Msps 12-bit resolution Interleave Triple ADC mode - - 7.2 Msps DS11854 Rev 5 155/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Equation 1: RAIN max formula R AIN ( k – 0.5 ) = ------------------------------------------------------------- – R ADC f ADC × C ADC × ln ( 2 N+2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 68. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V Typ Max(1) ±3 ±4 ±2 ±3 ±1 ±3 ±1 ±2 ±2 ±3 Unit LSB 1. Guaranteed by characterization results. Table 69. ADC static accuracy at fADC = 30 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V 1. Guaranteed by characterization results. 156/228 DS11854 Rev 5 Typ Max(1) ±2 ±5 ±1.5 ±2.5 ±1.5 ±4 ±1 ±2 ±1.5 ±3 Unit LSB STM32F732xx STM32F733xx Electrical characteristics Table 70. ADC static accuracy at fADC = 36 MHz Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(1) ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - − 67 − 72 - dB 1. Guaranteed by characterization results. Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - − 70 − 72 - dB 1. Guaranteed by characterization results. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.20 does not affect the ADC accuracy. DS11854 Rev 5 157/228 200 Electrical characteristics STM32F732xx STM32F733xx Figure 46. ADC accuracy characteristics [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 7 V SSA 4093 4094 4095 4096 VDDA ai14395c 1. See also Table 69. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 47. Typical connection diagram using the ADC STM32F VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL±1 μA 12-bit converter C ADC(1) ai17534 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 158/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 48 or Figure 49, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+ (1) 1 μF // 10 nF VDDA 1 μF // 10 nF VSSA/VREF+ (1) ai17535c 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (1) 1 μF // 10 nF VREF-/VSSA (1) ai17536c 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA. DS11854 Rev 5 159/228 200 Electrical characteristics 6.3.25 STM32F732xx STM32F733xx Temperature sensor characteristics Table 73. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 74. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FF0 7A2C - 0x1FF0 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F 6.3.26 VBAT monitoring characteristics Table 75. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 4 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er(1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.27 Reference voltage The parameters given in Table 76 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 76. internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) 160/228 Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.24 V - 10 - - µs VDD = 3V ± 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Table 76. internal reference voltage (continued) Symbol Parameter Conditions Min Typ Max Unit TCoeff(2) Temperature coefficient - - 30 50 ppm/°C tSTART(2) Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 77. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 6.3.28 Memory address Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FF0 7A2A - 0x1FF0 7A2B DAC electrical characteristics Table 78. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.7(1) - 3.6 V VREF+ Reference supply voltage 1.7(1) - 3.6 V VSSA Ground 0 - 0 V - 5 - - kΩ - 25 - - kΩ - Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage with buffer ON min(2) 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA − 0.2 V DAC_OUT Lower DAC_OUT voltage with buffer OFF min(2) - 0.5 - mV - VREF+ − 1LSB V RLOAD (2) RO(2) CLOAD(2) Connected to Resistive load VSSA with buffer ON Connected to VDDA DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) - DS11854 Rev 5 VREF+ ≤ VDDA It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. 161/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 78. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit µA Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV Given for the DAC in 12-bit configuration Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.5 % Given for the DAC in 12-bit configuration - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ IDDA(4) DNL(4) Gain error(4) DAC DC VDDA current consumption in quiescent mode(3) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the (4) tSETTLING highest input codes when DAC_OUT reaches final value ±4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 162/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Table 78. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 50. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.29 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. • Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below: DS11854 Rev 5 163/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 79. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog Filter ON DNF=0 10 Analog Filter OFF DNF=1 9 Analog Filter ON DNF=0 22.5 Analog Filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: • Tr(SDA/SCL)=0.8473xRpxCload • Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 80. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered 164/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 81 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 81. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode SPI1,4,5 2.7≤VDD≤3.6 - - 54(2) Master mode SPI1,4,5 1.71≤VDD≤3.6 - - 27 Master transmitter mode SPI1,4,5 1.71≤VDD≤3.6 - - 54 Slave receiver mode SPI1,4,5 1.71≤VDD≤3.6 - - 54 Slave mode transmitter/full duplex SPI1,4,5 2.7≤VDD≤3.6 - - 50(3) Slave mode transmitter/full duplex SPI1,4,5 1.71≤VDD≤3.6 - - 37(3) Master & Slave mode SPI2,3 1.71≤VDD≤3.6 - - 27 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4xTpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2xTpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-1 Tpclk Tpclk+1 DS11854 Rev 5 Unit MHz ns 165/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 81. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) th(MI) th(SI) Parameter Data input setup time Data input hold time Conditions Min Typ Max Master mode 4 - - Slave mode 3.5 - - Master mode 3 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 7 9 21 tdis(SO) Data output disable time Slave mode 5 7 12 Slave mode 2.7≤VDD≤3.6V - 6.5 10 Slave mode 1.71≤VDD≤3.6V - 6.5 13.5 Master mode - 2 3 Slave mode 1.71≤VDD≤3.6V 4.5 - - Master mode 0 - - tv(SO) Data output valid time tv(MO) th(SO) Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz. 3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. Figure 51. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) First bit OUT MISO output th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 166/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Figure 52. SPI timing diagram - slave mode and CPHA = 1 NSS input tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41659V1 Figure 53. SPI timing diagram - master mode High NSS input SCK Output tc(SCK) CPHA= 0 CPOL=0 SCK Output SCK input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c DS11854 Rev 5 167/228 200 Electrical characteristics STM32F732xx STM32F733xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 82 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 82. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256 x 8K 256xFs(2) MHz fCK I2S clock frequency Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 DCK I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 5 - th(WS) WS hold time Slave mode 2 - Master receiver 2.5 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) - 12 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency). Note: Refer to RM0431 reference manual I2S section for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. 168/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Figure 54. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(1) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(1) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive MS46528V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 55. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(1) MSB transmit LSB receive(1) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive MS46529V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS11854 Rev 5 169/228 200 Electrical characteristics STM32F732xx STM32F733xx SAI characteristics Unless otherwise specified, the parameters given in Table 83 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 83. SAI characteristics(1) Symbol Parameter Conditions Min Max fMCKL SAI Main clock output - 256x8K 256xFs FCK SAI clock frequency(2) Master data: 32 bits - 128xFs(3) Slave data: 32 bits - 128xFs(3) Master mode 2.7≤VDD≤3.6V - 18 Master mode 1.71≤VDD≤3.6V - 20 Slave mode 1 - Master mode 7 - Slave mode 0.5 - Master receiver 1 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 0.5 - Slave transmitter (after enable edge) 2.7≤VDD≤3.6V - 11 Slave transmitter (after enable edge) 1.71≤VDD≤3.6V - 18 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 2.7≤VDD≤3.6V - 16 Master transmitter (after enable edge) 1.71≤VDD≤3.6V - 18.5 Master transmitter (after enable edge) 7.5 - tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_MT) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 3. With Fs = 192 KHz. 170/228 DS11854 Rev 5 Unit MHz ns STM32F732xx STM32F733xx Electrical characteristics Figure 56. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) Slot n+2 th(SD_MR) Slot n MS32771V1 Figure 57. SAI slave timing waveforms 1/fSCK SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) tsu(FS) th(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 DS11854 Rev 5 171/228 200 Electrical characteristics STM32F732xx STM32F733xx USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 84. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 µs 1. Guaranteed by design. Table 85. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions USB OTG full speed VDDUSB transceiver operating voltage Input levels Min. (1) Typ. - 3.0(2) Max.( 1) Unit - 3.6 V VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold - 1.3 - 2.0 VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3 2.8 - 3.6 14.25 - 24.8 2.4 5.2 8 Output levels VOH Static output level high RL of 15 kΩ to PA11, PA12 (USB_FS_DP/DM) RPD RPU VIN = VDD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) PA12 (USB_FS_DP) PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VSS(4) VIN = VDD V V kΩ VIN = VSS, during idle 0.9 1.25 1.575 VIN = VSS, during reception 0.55 0.95 1.35 1. All the voltages are measured from the local ground potential. 2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG full speed drivers. Note: 172/228 When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state (floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled. DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Figure 58. USB OTG full speed timings: definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 86. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol tr tf trfm Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 111 % - 1.3 2.0 V Driving high or low 28 44 Ω Rise/ fall time matching VCRS Output signal crossover voltage ZDRV Output driver impedance(3) 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. USB high speed (HS) characteristics (through ULPI in STM32F732xx devices) Unless otherwise specified, the parameters given in Table 89 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 88 and VDD supply voltage conditions summarized in Table 87, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified • Capacitive load C = 20 pF, unless otherwise specified • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.20: I/O port characteristics for more details on the input/output characteristics. Table 87. USB HS DC electrical characteristics Symbol Input level Parameter VDD USB OTG HS operating voltage Min.(1) Max.(1) Unit 1.7 3.6 V 1. All the voltages are measured from the local ground potential. DS11854 Rev 5 173/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 88. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit - fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition - - 1.4 ms Peripheral - - 5.6 Host - - - - - - tSTART_DEV tSTART_HOST Clock startup time after the de-assertion of SuspendM 8-bit ±10% 8-bit ±10% PHY preparation time after the first transition of the input clock tPREP ms µs 1. Guaranteed by design. Figure 59. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC Control out (ULPI_STP) tDC tDD data out (8-bit) ai17361c 174/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Table 89. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 1.5 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1 - - tSD Data in setup time - 1.5 - - tHD Data in hold time - 1 - - 2.7 V < VDD < 3.6 V, CL = 20 pF and OSPEEDRy[1:0] = 11 - 6 7.5 - 9.5 11 tDC/tDD Data/control output delay 1.7 V < VDD < 3.6 V, CL = 15 pF and OSPEEDRy[1:0] = 11 - Unit ns 1. Guaranteed by characterization results. USB high speed (HS) characteristics (embedded PHY High speed on STM32F733xx devices) Table 90. USB OTG high speed DC electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Vhssq High speed squelch detection threshold - 100 - 150 mV Vhsdsc High speed disconnect detection threshold - 525 - 625 mV Vhsdif High speed differential detection threshold - 100 - - mV Vhscm High speed data signalling common mode voltage range - -50 - 500 mV Vhsoi High speed idle level - -10 - 10 mV Vhsoh High speed data signaling high - 360 - 440 mV Vhsol High speed data signaling low - -10 - 10 mV Vchirpj Chirp J level - 700 - 1100 mV Vchirpk Chirp K level - -900 - -500 mV Min Typ Max Unit Table 91. USB OTG high speed electrical characteristics Parameter Comments Conditions tlr Rise time - 0.5 - - ns tlf Fall time - 0.5 - - ns tlrfm Setup time from INHSDRIVERENABLE=1 to the transition on INHSDATAP/INHSDATAN - 10 - - ns Zdrv Driver output impedance - 40.5 - 49.5 Ω DS11854 Rev 5 175/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 92. USB FS PHY BCD electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Primary detection mode consumption - - - 300 Secondary detection mode consumption - - - 300 RDAT_LKG Data line leakage resistance - 300 - - kΩ VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V RDCP_DAT Dedicated charging port resistance across D+/D- - - - 200 Ω VLGC_HI Logic high - 2.0 - 3.6 VLGC_LOW Logic low - - - 0.8 Logic threshold - 0.8 - 2.0 VDAT_REF Data detect voltage - 0.25 - 3.6 VDP_SRC D+ source voltage - 0.5 - 3.6 VDM_SRC D- source voltage - 0.5 - 3.6 IDM_SINK D- sink current - 25 - 175 IDP_SINK D+ sink current - 25 - 175 IDP_SRC Data contact detect current source - 7 - 30 IDDUSB VLGC µA V µA CAN (controller area network) interface Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 6.3.30 FMC characteristics Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 60 through Figure 63 represent asynchronous waveforms and Table 93 through Table 100 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 • Capcitive load CL = 30 pF In all timing tables, the THCLK is the HCLK clock period 176/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. DS11854 Rev 5 177/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Thclk -1 2Thclk +1 0 0.5 2Thclk -1 2Thclk +1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 - tsu(Data_NOE) Data to FMC_NOEx high setup time Thclk -1.5 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Thclk -0.5 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Unit ns 1. CL = 30 pF. Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1) Symbol tw(NE) tw(NOE) tw(NWAIT) Parameter Min Max FMC_NE low time 7Thclk +1 7Thclk +1 FMC_NWE low time 5Thclk -1 5Thclk +1 FMC_NWAIT low time Thclk -0.5 - 5Thclk +1.5 - 4Thclk +1 - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. Guaranteed by characterization results. 178/228 DS11854 Rev 5 Unit ns STM32F732xx STM32F733xx Electrical characteristics Figure 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) FMC_NADV (1) tw(NADV) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3Thclk +1 3Thclk +1 FMC_NEx low to FMC_NWE low Thclk - 0.5 Thclk +0.5 FMC_NWE low time Thclk - 1.5 Thclk +0.5 Thclk - - 0 Thclk - 0.5 - - 0.5 Thclk - 0.5 - FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid Unit ns th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - Thclk +1.5 th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Thclk - 0.5 tw(NADV) 1. Guaranteed by characterization results. DS11854 Rev 5 179/228 200 Electrical characteristics STM32F732xx STM32F733xx Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time Min Max 8Thclk -1 8Thclk +1 6Thclk -1.5 6Thclk +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk -1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk + 2 - Unit ns 1. Guaranteed by characterization results. Figure 62. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 180/228 DS11854 Rev 5 STM32F732xx STM32F733xx Electrical characteristics Table 97. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3Thclk -1 3Thclk +1 2Thclk 2Thclk +0.5 Thclk -1 Thclk +1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Thclk -0.5 Thclk +1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) Thclk +0.5 - th(A_NOE) Address hold time after FMC_NOE high Thclk -0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 - tsu(Data_NOE) Data to FMC_NOE high setup time Thclk -1.5 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol Min Max 8Thclk -1 8Thclk +1 FMC_NWE low time 5Thclk -1.5 8Thclk +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk +1 - tw(NE) tw(NOE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. DS11854 Rev 5 181/228 200 Electrical characteristics STM32F732xx STM32F733xx Figure 63. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) FMC_ AD[15:0] t v(Data_NADV) Address th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 Table 99. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Min Max FMC_NE low time 4Thclk -1 4Thclk +1 FMC_NEx low to FMC_NWE low Thclk -0.5 Thclk +0.5 FMC_NWE low time 2Thclk -0.5 2Thclk +0.5 FMC_NWE high to FMC_NE high hold time Thclk -0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 Thclk Thclk +1 FMC_AD(adress) valid hold time after FMC_NADV high) Thclk +0.5 - th(A_NWE) Address hold time after FMC_NWE high Thclk +0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk -0.5 - tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) 182/228 Parameter FMC_NADV low time tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Thclk +1.5 th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 - DS11854 Rev 5 Unit ns STM32F732xx STM32F733xx Electrical characteristics 1. Guaranteed by characterization results. Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Min Max FMC_NE low time 9Thclk - 1 9Thclk + 1 FMC_NWE low time 7Thclk -0.5 7Thclk + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk - 1 - tw(NE) tw(NWE) Parameter Unit ns 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 64 through Figure 67 represent synchronous waveforms and Table 101 through Table 104 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable; • MemoryType = FMC_MemoryType_CRAM; • WriteBurst = FMC_WriteBurst_Enable; • CLKDivision = 1; • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM • CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. – For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at CL=30 pF (on FMC_CLK). – For 1.71 V≤ VDD