STM32F750x8
Arm®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, 64KB Flash/
320+16+ 4KB RAM, USB OTG HS/FS, 25 com IF, cam, LCD
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator™) and L1-cache: 4-Kbyte data
cache and 4-Kbyte instruction cache, allowing
0-wait state execution from embedded Flash
memory and external memories, frequency up
to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions.
• Memories
– 64 Kbytes of Flash memory
– 1024 bytes of OTP memory
– SRAM: 320 Kbytes (including 64 Kbytes of
data TCM RAM for critical real-time data) +
16 Kbytes of instruction TCM RAM (for
critical real-time routines) + 4 Kbytes of
backup SRAM (available in the lowest
power modes)
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• Dual mode Quad-SPI
• LCD parallel interface, 8080/6800 modes
• LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for
enhanced graphic content creation (DMA2D)
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low-power
– Sleep, Stop and Standby modes
June 2018
This is information on a product in full production.
FBGA
LQFP100 (14x14 mm)
TFBGA216 (13x13 mm)
LQFP144 (20x20 mm)
– VBAT supply for RTC, 32×32-bit backup
registers + 4 Kbytes of backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Debug mode
– SWD & JTAG interfaces
– Cortex®-M7 Trace Macrocell™
•
Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
• Up to 25 communication interfaces
– Up to 4× I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (up to 50 Mbit/s), 3 with
muxed simplex I2S for audio class
accuracy via internal audio PLL or external
clock
– 2 x SAIs (serial audio interface)
– 2 × CANs (2.0B active) and SDMMC
interface
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STM32F750x8
– SPDIFRX interface
– HDMI-CEC
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic acceleration: hardware
acceleration for AES 128, 192, 256, triple DES,
HASH (MD5, SHA-1, SHA-2), and HMAC
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
• 8- to 14-bit parallel camera interface up to
54 Mbyte/s
Table 1. Device summary
Reference
STM32F750x8
2/199
Part number
STM32F750V8, STM32F750Z8, STM32F750N8
DS12535 Rev 1
STM32F750x8
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
3
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 19
3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.13
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18
3.17.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.19
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 31
3.20
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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STM32F750x8
3.22
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.4
Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.5
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.6
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24
Universal synchronous/asynchronous receiver transmitters (USART) . . 38
3.25
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 39
3.26
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29
Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.30
SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 41
3.31
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 41
3.32
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.33
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 42
3.34
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 42
3.35
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.36
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37
Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.38
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.39
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.40
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.41
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.42
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.43
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.44
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.2
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.3
Operating conditions at power-up / power-down (regulator ON) . . . . . . 90
6.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 90
6.3.5
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 90
6.3.6
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 120
6.3.13
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.14
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.15
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 126
6.3.16
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.17
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.18
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.19
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.20
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.21
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.24
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.25
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.26
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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8
STM32F750x8
6.3.27
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.28
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.29
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 180
6.3.30
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 181
6.3.31
SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 183
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.1
LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 185
7.2
LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 189
7.3
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 197
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F750x8 features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 28
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage regulator modes in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32F750x8 pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STM32F750x8 alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 89
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 90
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 90
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . 95
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . . 96
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . . 98
Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . . 98
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 100
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 101
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DS12535 Rev 1
7/199
9
List of tables
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
8/199
STM32F750x8
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 137
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 137
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 156
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 156
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 157
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 160
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 160
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 162
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DS12535 Rev 1
STM32F750x8
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 184
Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 184
LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 186
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 193
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 197
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
DS12535 Rev 1
9/199
9
List of figures
STM32F750x8
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
10/199
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F750x8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F750x8 AXI-AHB bus matrix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 26
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 30
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 30
STM32F750V8 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F750Z8 LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F750N8 TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
HSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 139
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 139
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
DS12535 Rev 1
STM32F750x8
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 153
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 159
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 161
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 162
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 173
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 174
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 185
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 189
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
LQFP144, 20 x 20mm, 144-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
DS12535 Rev 1
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11
Introduction
1
STM32F750x8
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F750x8 microcontrollers.
This document should be ready in conjunction with the STM32F75xxx and STM32F74xxx
advanced Arm®-based 32-bit MCUs reference manual (RM0385). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 technical
reference manual available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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2
Description
The STM32F750x8 devices are based on the high-performance Arm® Cortex®-M7 32-bit
RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a single
floating point unit (SFPU) precision which supports all Arm® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances the application security.
The STM32F750x8 devices incorporate high-speed embedded memories with a Flash
memory of 64 Kbytes, 320 Kbytes of SRAM (including 64 Kbytes of Data TCM RAM for
critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines),
4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of
enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multiAHB bus matrix and a multi layer AXI interconnect supporting internal and external
memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control and one low-power timer
available in Stop mode, two general-purpose 32-bit timers, a true random number generator
(RNG), and a cryptographic acceleration cell. They also feature standard and advanced
communication interfaces.
•
•
•
•
•
•
•
•
•
•
•
•
Up to four I2Cs
Six SPIs, three I2Ss in duplex mode. To achieve the audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
Two CANs
Two SAI serial audio interfaces
An SDMMC host interface
Ethernet and camera interfaces
LCD-TFT display controller
Chrom-ART Accelerator™
SPDIFRX interface
HDMI-CEC
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors and a
cryptographic acceleration cell.
The STM32F750x8 devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) is available
on all the packages except LQFP100 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F750x8 devices offer devices in 3 packages ranging from 100 pins to 216 pins.
The set of included peripherals changes with the device chosen.
DS12535 Rev 1
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46
Description
STM32F750x8
These features make the STM32F750x8 microcontrollers suitable for a wide range of
applications.
•
Motor drive and application control,
•
Medical equipment,
•
Industrial applications: PLC, inverters, circuit breakers,
•
Printers, and scanners,
•
Alarm systems, video intercom, and HVAC,
•
Home audio appliances,
•
Mobile applications, Internet of Things,
•
Wearable devices: smartwatches.
Table 2. STM32F750x8 features and peripheral counts
Peripherals
STM32F750V8
Flash memory in Kbytes
System
320(240+16+64)
Instruction
16
Backup
4
Yes(1)
FMC memory controller
Ethernet
Yes
General-purpose
10
Advancedcontrol
2
Basic
2
Low-power
1
Random number generator
SPI /
Yes
I2S
4/3
(simplex)(2)
I2C
Communication
interfaces
6/3 (simplex)(2)
4
USART/UART
4/4
USB OTG FS
Yes
USB OTG HS
Yes
CAN
2
SAI
2
SPDIFRX
4 inputs
SDMMC
Yes
Camera interface
Yes
LCD-TFT
Yes
Chrom-ART Accelerator™ (DMA2D)
Yes
Cryptography
Yes
GPIOs
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STM32F750N8
64
SRAM in Kbytes
Timers
STM32F750Z8
82
DS12535 Rev 1
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168
STM32F750x8
Table 2. STM32F750x8 features and peripheral counts (continued)
Peripherals
STM32F750V8
12-bit ADC
16
12-bit DAC
Number of channels
24
Yes
2
216 MHz(3)
Maximum CPU frequency
1.7 to 3.6 V(4)
Operating voltage
Package
STM32F750N8
3
Number of channels
Operating temperatures
STM32F750Z8
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
LQFP100
LQFP144
TFBGA216
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 Chip Select.
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode
or the I2S audio mode.
3. 216 MHz maximum frequency for -40°C to + 85°C ambient temperature range (200 MHz maximum
frequency for -40°C to + 105°C ambient temperature range).
4. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.17.2:
Internal reset OFF).
DS12535 Rev 1
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46
Description
2.1
STM32F750x8
Full compatibility throughout the family
The STM32F750x8 devices are fully pin-to-pin, compatible with the STM32F4xxxx devices,
allowing the user to try different peripherals, and reaching higher performances (higher
frequency) for a greater degree of freedom during the development cycle.
Figure 1 give compatible board designs between the STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
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The STM32F750x8 LQFP144 and TFBGA216 packages are fully pin to pin compatible with
STM32F4xxxx devices.
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DS12535 Rev 1
STM32F750x8
USB
OTG HS
DMA/
FIFO
DMA2
8 Streams
FIFO
DMA1
8 Streams
FIFO
LCD-TFT
FIFO
CHROM-ART
(DMA2D)
FIFO
ART
GPIO PORT A
PB[15:0]
GPIO PORT B
FLASH 64KB
SRAM1 240 KB
SRAM2 16 KB
Int
PVD
LS
PCLKx
HCLKx
LS
GPIO PORT J
FIFO
D[7:0]
CMD, CK as AF
SDMMC1
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR,
BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR,
BKIN as AF
DMA1
DMA2
AHB/APB2
VDDUSB = 3.0 to 3.6V
VDD = 1.7/1.8 to 3.6 V
VSS
VCAP1, VCAP2
WKUP[4:0]
VDDA, VSSA
NRST
@VDD
Standby
interface
GPIO PORT K
EXT IT. WKUP
DP
DM
ID, VBUS, SOF
CLK, NE [3:0], A[23:0],
D[31:0], NOEN, NWEN,
NBL[3:0], SDCLKE[1:0],
SDNE[1:0], SDNWE, NL
NRAS, NCAS, NADV
NWAIT, INTR
CLK, CS,D[3:0]
OSC_IN
OSC_OUT
IWDG
GPIO PORT I
168 AF
@VDD
Supply
supervision
POR/PDR
BOR
VBAT = 1.65 to 3.6 V
@VBAT
GPIO PORT H
PK[7:0]
AHB/APB1
XTAL 32 kHz
RTC
AWU
Backup register
4 KB BKPSRAM
OSC32_IN
OSC32_OUT
RTC_AF1
RTC_AF1
RTC_50HZ
TIM2
32b
4 channels, ETR as AF
TIM3
16b
4 channels, ETR as AF
TIM4
16b
4 channels, ETR as AF
TIM5
32b
4 channels
TIM12
16b
2 channels as AF
TIM13
16b
1 channel as AF
TIM14
16b
1 channel as AF
smcard
USART2 irDA
RX, TX as AF
CTS, RTS as AF
smcard
irDA
UART4
RX, TX as AF
CTS, RTS as AF
RX, TX as AF
UART5
RX, TX as AF
UART7
RX, TX as AF
TIM1 / PWM 16b
16b
TIM11
16b
RX, TX, CK,
CTS, RTS as AF
smcard USART1
RX, TX, CK,
CTS, RTS as AF
smcard USART6
irDA
irDA
MOSI/SD, SCK/CK
NSS/WS, MCK as AF
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO,
SCK, NSS as AF
APB2 60MHz
SPI1/I2S1
SPI4
SPI5
WWDG
USART3
LPTIM1
16b
TIM6
16b
TIM7
16b
SPI6
FIFO FIFO
SAI2
SD, SCK, FS, MCLK as AF
SPI2/I2S2
SPI3/I2S3
I2C1/SMBUS
I2C2/SMBUS
SAI1
SD, SCK, FS, MCLK as AF
@VDDA
U STemperature
AR T 2 M B ps
sensor
I2C3/SMBUS
@VDDA
Dual DAC
channels
RX, TX as AF
UART8
Digital filter
TIM10
1 channel as AF
bxCAN1
MOSI/SD, SCK/CK
NSS/WS, MCK as AF
MOSI/SD, SCK/CK
NSS/WS, MCK as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C4/SMBUS
ITF
FIFO
1 channel as AF
APB1(max)
0M
3Hz
APB1 54 MHz
16b
TIM9
APB2 108 MHz (max)
TIM8 / PWM 16b
2 channels as AF
8 analog inputs for ADC3
RC LS
Reset &
clock
MAN GT
control
GPIO PORT G
PJ[15:0]
VDDREF_ADC
POR
reset
GPIO PORT F
PI[15:0]
8 analog inputs common
to the 3 ADCs
8 analog inputs common
to the ADC1 & 2
RC HS
XTAL OSC
4- 26MHz
GPIO PORT E
PH[15:0]
Power managmt
Voltage
regulator
1.2 V
VDD
@VDDA
PE[15:0]
PG[15:0]
OTG FS
Quad-SPI
AHB1 216 MHz
GPIO PORT D
PF[15:0]
USB
PUIXCLK, D[13:0]
AHB2 216 MHz
GPIO PORT C
PD[15:0]
HSYNC, VSYNC
Camera
interface
External memory controller (FMC)
SRAM, SDRAM,PSRAM, NOR
Flash, NAND Flash
PLL1,2,3
PC[15:0]
HASH
RNG
@VDDA
PA[15:0]
TDES, AES256
PHY
DMA/
FIFO
LCD_R[7:0], LCD_G[7:0], LCD_B[7:0],
LCD_HSYNC, LCD_VSYNC,
LCD_DE, LCD_CLK
ITCM RAM 16KB
AHB BUS-MATRIX
11S8M
AHB bus-matrix
8S7M
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
ID, VBUS, SOF
Ethernet MAC
10/100
PHY
MII or RMII as AF
MDIO as AF
DTCM RAM 64KB
Arm
Cortex-M7
I-Cache AXIM
4KB
216MHz D-Cache AHBP
4KB
AHBS
FIFO
TRACECK
TRACED[3:0]
MPU
NVIC
DTCM
ICTM
FIFO
JTAG & SW
ETM
AHB2AXI
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
FIFO FIFO
Figure 2. STM32F750x8 block diagram
TX, RX
ADC1
bxCAN2
ADC2
SPDIFRX
SPDIFRX[3:0] as AF
HDMI-CEC
HDMI_CEC as AF
ADC3
IF
DAC_OUT1 DAC_OUT2
as AF
as AF
TX, RX
MSv50782V1
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
DS12535 Rev 1
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46
Functional overview
STM32F750x8
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and a low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
–
Six-stage dual-issue pipeline
–
Dynamic branch prediction
–
Harvard caches (4 Kbytes of I-cache and 4 Kbytes of D-cache)
–
64-bit AXI4 interface
–
64-bit ITCM interface
–
2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
•
Tightly Coupled Memory (TCM) interface.
•
Harvard instruction and data caches and AXI master (AXIM) interface.
•
Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up the software development by using
metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F750x8 devices.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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3.3
Embedded Flash memory
The STM32F750x8 devices embed a Flash memory of 64 Kbytes available for storing
programs and data.
3.4
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify the data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.5
Embedded SRAM
All the devices features:
•
•
System SRAM up to 320 Kbytes:
–
SRAM1 on AHB bus Matrix: 240 Kbytes
–
SRAM2 on AHB bus Matrix: 16 Kbytes
–
DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for
critical real-time data.
Instruction RAM (ITCM-RAM) 16 Kbytes:
–
It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The TCM RAM instruction is reserved only for CPU. It is accessed at
CPU clock speed with 0-wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
3.6
AXI-AHB bus matrix
The STM32F750x8 system architecture is based on 2 sub-systems:
•
•
An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
–
3x AXI to 32-bit AHB bridges connected to AHB bus matrix
–
1x AXI to 64-bit AHB bridge connected to the embedded flash
A multi-AHB Bus-Matrix:
–
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM,
FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and an
efficient operation even when several high-speed peripherals work
simultaneously.
DS12535 Rev 1
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46
Functional overview
STM32F750x8
AHBS
Chrom-ART
Accelerator
(DMA2D)
DMA2D
LCD-TFT_M
USB_HS_M
DMA_P2
ETHERNET_M
AHBP
GP
MAC
USB OTG LCD-TFT
DMA2 Ethernet
HS
DMA_MEM2
4KB
I/D Cache
AXIM
GP
DMA1
DMA_PI
Arm Cortex-M7
DMA_MEM1
ITCM
DTCM
Figure 3. STM32F750x8 AXI-AHB bus matrix architecture
DTCM RAM
64KB
ITCM RAM
16KB
AXI to
multi-AHB
ART
ITCM
64-bit AHB
FLASH
64KB
64-bit BuS Matrix
SRAM1
240KB
SRAM2
16KB
AHB
Periph1
AHB
periph2
FMC external
MemCtl
APB1
APB2
Quad-SPI
32-bit Bus Matrix - S
MSv50784V1
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
3.7
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
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Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
3.8
•
SPI and I2S
•
I2C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
DAC
•
SDMMC
•
Cryptographic acceleration
•
Camera interface (DCMI)
•
ADC
•
SAI
•
SPDIFRX
•
Quad-SPI
•
HDMI-CEC
Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
•
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
DS12535 Rev 1
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46
Functional overview
STM32F750x8
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.9
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•
Direct mode through registers.
•
External flash status register polling mode.
•
Memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
3.10
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
3.11
•
2 displays layers with dedicated FIFO (64x32-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 Input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events.
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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DS12535 Rev 1
STM32F750x8
3.12
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
3.14
Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
DS12535 Rev 1
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46
Functional overview
3.15
STM32F750x8
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space mapped on ITCM or AXIM interface
•
All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•
The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
3.16
Note:
Power supply schemes
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•
VDD = 1.7 to 3.6 Vexternal power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
•
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when
device is powered at 1.8V, an independent power supply 3.3V can be connected to
VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to
disappear. The following conditions VDDUSB must be respected:
–
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
VDDSUB rising and falling time rate specifications must be respected (see Table 19
and Table 20)
–
In operating mode phase, VDDUSB could be lower or higher than VDD:
- If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
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DS12535 Rev 1
STM32F750x8
Figure 4. VDDUSB connected to VDD power supply
VDD
VDD_MAX
VDD= VDDA = VDDUSB
VDD_MIN
Operating mode
Power-on
Power-down
time
MS37591V1
Figure 5. VDDUSB connected to external power supply
VDDUSB_MAX
USB functional area
VDDUSB
VDDUSB_MIN
USB non
functional
area
VDD = VDDA
Power-on
Operating mode
USB non
functional
area
VDD_MIN
Power-down
time
MS37590V1
3.17
Power supply supervisor
3.17.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
DS12535 Rev 1
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46
Functional overview
STM32F750x8
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.17.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
VDD
Application reset
signal (optional)
VBAT
PDR_ON
VSS
PDR not active : 1.7v< VDDVDDA while a negative injection is induced by VIN 2.4 V, the compensation cell should be used.
Figure 33. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON CL
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.
ai14131d
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DS12535 Rev 1
STM32F750x8
6.3.18
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 55: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 58. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
VIN = VSS
30
40
50
kΩ
-
-
-
100
ns
VDD > 2.7 V
300
-
-
ns
Internal Reset source
20
-
-
µs
VF(NRST)
(2)
NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
TNRST_OUT
Generated reset pulse duration
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 34. Recommended NRST pin protection
VDD
External
reset circuit (1)
NRST (2)
RPU
Internal Reset
Filter
0.1 μF
STM32F
ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58. Otherwise the reset is not taken into account by the device.
DS12535 Rev 1
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184
Electrical characteristics
6.3.19
STM32F750x8
TIM timer characteristics
The parameters given in Table 59 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 59. TIMx characteristics(1)(2)
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
216 MHz
1
-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
108 MHz
1
-
tTIMxCLK
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 216 MHz
0
fTIMxCLK/2
MHz
Timer resolution
-
16/32
bit
-
65536 ×
65536
tTIMxCLK
Symbol
tres(TIM)
fEXT
ResTIM
tMAX_COUNT
Parameter
Timer resolution time
Maximum possible count
with 32-bit counter
-
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =
4x PCLKx.
6.3.20
RTC characteristics
Table 60. RTC characteristics
6.3.21
Symbol
Parameter
Conditions
-
fPCLK1/RTCCLK frequency ratio
Any read/write operation
from/to an RTC register
Min
Max
4
-
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 16.
Table 61. ADC characteristics
Symbol
VDDA
Parameter
Power supply
VREF+
Positive reference voltage
VREF-
Negative reference voltage
134/199
Conditions
VDDA −VREF+ < 1.2 V
-
DS12535 Rev 1
Min
Typ
Max
Unit
1.7(1)
-
3.6
V
1.7(1)
-
VDDA
V
-
0
-
V
STM32F750x8
Table 61. ADC characteristics (continued)
Symbol
fADC
fTRIG(2)
VAIN
RAIN(2)
Parameter
ADC clock frequency
External trigger frequency
Conversion voltage range(3)
External input impedance
RADC(2)(4) Sampling switch resistance
CADC(2)
Internal sample and hold
capacitor
Conditions
Min
Typ
Max
Unit
VDDA = 1.7(1) to 2.4 V
0.6
15
18
MHz
VDDA = 2.4 to 3.6 V
0.6
30
36
MHz
fADC = 30 MHz,
12-bit resolution
-
-
1764
kHz
-
-
-
17
1/fADC
-
0
(VSSA or VREFtied to ground)
-
VREF+
V
See Equation 1 for
details
-
-
50
kΩ
-
-
-
6
kΩ
-
-
4
7
pF
-
-
0.100
µs
-
-
3(5)
1/fADC
-
-
0.067
µs
-
-
2(5)
1/fADC
fADC = 30 MHz
0.100
-
16
µs
-
3
-
480
1/fADC
-
2
3
µs
fADC = 30 MHz
12-bit resolution
0.50
-
16.40
µs
fADC = 30 MHz
10-bit resolution
0.43
-
16.34
µs
fADC = 30 MHz
8-bit resolution
0.37
-
16.27
µs
fADC = 30 MHz
6-bit resolution
0.30
-
16.20
µs
tlat(2)
Injection trigger conversion
latency
fADC = 30 MHz
tlatr(2)
Regular trigger conversion
latency
fADC = 30 MHz
tS(2)
Sampling time
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time (including
sampling time)
-
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
Sampling rate
fS(2)
(fADC = 30 MHz, and
tS = 3 ADC cycles)
1/fADC
12-bit resolution
Single ADC
-
-
2
Msps
12-bit resolution
Interleave Dual ADC
mode
-
-
3.75
Msps
12-bit resolution
Interleave Triple ADC
mode
-
-
6
Msps
DS12535 Rev 1
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184
Electrical characteristics
STM32F750x8
Table 61. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IVREF+(2)
ADC VREF DC current
consumption in conversion
mode
-
-
300
500
µA
IVDDA(2)
ADC VDDA DC current
consumption in conversion
mode
-
-
1.6
1.8
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 61.
Equation 1: RAIN max formula
R AIN
( k – 0.5 )
- – R ADC
= --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 62. ADC static accuracy at fADC = 18 MHz
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
Typ
Max(1)
±3
±4
±2
±3
±1
±3
±1
±2
±2
±3
Unit
LSB
1. Guaranteed by characterization results.
Table 63. ADC static accuracy at fADC = 30 MHz
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC = 30 MHz,
RAIN < 10 kΩ,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
1. Guaranteed by characterization results.
136/199
DS12535 Rev 1
Typ
Max(1)
±2
±5
±1.5
±2.5
±1.5
±4
±1
±2
±1.5
±3
Unit
LSB
STM32F750x8
Table 64. ADC static accuracy at fADC = 36 MHz
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max(1)
±4
±7
±2
±3
±3
±6
±2
±3
±3
±6
fADC =36 MHz,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
Unit
LSB
1. Guaranteed by characterization results.
Table 65. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to-noise and distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.3
10.4
-
bits
64
64.2
-
64
65
-
− 67
− 72
-
dB
1. Guaranteed by characterization results.
Table 66. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to noise and distortion ratio
SNR
Signal-to noise ratio
THD
Total harmonic distortion
fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.6
10.8
-
bits
66
67
-
64
68
-
− 70
− 72
-
dB
1. Guaranteed by characterization results.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.17 does not affect the ADC accuracy.
DS12535 Rev 1
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184
Electrical characteristics
STM32F750x8
Figure 35. ADC accuracy characteristics
[1LSB IDEAL =
V REF+
4096
(or
V DDA
4096
depending on package)]
EG
4095
4094
4093
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
1L SBIDEAL
1
0
1
2
3
456
7
V SSA
4093 4094 4095 4096
VDDA
ai14395c
1. See also Table 63.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 36. Typical connection diagram using the ADC
STM32F
VDD
RAIN(1) AINx
VAIN
Cparasitic
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
VT
0.6 V
IL±1 μA
12-bit
converter
C ADC(1)
ai17534
1. Refer to Table 61 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
138/199
DS12535 Rev 1
STM32F750x8
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 37 or Figure 38,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 37. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F
VREF+ (1)
1 μF // 10 nF
VDDA
1 μF // 10 nF
VSSA/VREF-
(1)
ai17535b
1. VREF+ input is available on all the packages whereas the VREF– is available only on TFBGA216. When
VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 38. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA (1)
1 μF // 10 nF
VREF-/VSSA
(1)
ai17536c
1. VREF+ input is available on all the packages whereas the VREF– is available only on TFBGA216. When
VREF- is not available, it is internally connected to VDDA and VSSA.
DS12535 Rev 1
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184
Electrical characteristics
6.3.22
STM32F750x8
Temperature sensor characteristics
Table 67. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VSENSE linearity with temperature
-
±1
±2
°C
Average slope
-
2.5
-
mV/°C
Voltage at 25 °C
-
0.76
-
V
tSTART(2)
Startup time
-
6
10
µs
TS_temp(2)
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
-
µs
TL(1)
Avg_Slope
(1)
V25(1)
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 68. Temperature sensor calibration values
Symbol
Parameter
Memory address
TS_CAL1
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
0x1FF0 F44C - 0x1FF0 F44D
TS_CAL2
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V
0x1FF0 F44E - 0x1FF0 F44F
6.3.23
VBAT monitoring characteristics
Table 69. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
R
Resistor bridge for VBAT
-
50
-
KΩ
Q
Ratio on VBAT measurement
-
4
-
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
5
-
-
µs
Er(1)
TS_vbat(2)(2)
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.24
Reference voltage
The parameters given in Table 70 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 16.
Table 70. internal reference voltage
Symbol
VREFINT
TS_vrefint(1)
VRERINT_s(2)
140/199
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.18
1.21
1.24
V
-
10
-
-
µs
VDD = 3V ± 10mV
-
3
5
mV
ADC sampling time when reading the
internal reference voltage
Internal reference voltage spread over the
temperature range
DS12535 Rev 1
STM32F750x8
Table 70. internal reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TCoeff(2)
Temperature coefficient
-
-
30
50
ppm/°C
tSTART(2)
Startup time
-
-
6
10
µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Table 71. Internal reference voltage calibration values
Symbol
Parameter
VREFIN_CAL
6.3.25
Memory address
Raw data acquired at temperature of 30 °C VDDA = 3.3 V
0x1FF0 F44A - 0x1FF0 F44B
DAC electrical characteristics
Table 72. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
-
VDDA
Analog supply voltage
1.7(1)
-
3.6
V
VREF+
Reference supply voltage
1.7(1)
-
3.6
V
VSSA
Ground
0
-
0
V
-
RLOAD(2)
Resistive load with buffer ON
5
-
-
kΩ
-
RO(2)
Impedance output with buffer
OFF
-
-
15
When the buffer is OFF, the Minimum
kΩ resistive load between DAC_OUT and
VSS to have a 1% accuracy is 1.5 MΩ
Capacitive load
-
-
50
pF
DAC_OUT Lower DAC_OUT voltage
with buffer ON
min(2)
0.2
-
-
V
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
-
-
VDDA −
0.2
V
DAC_OUT Lower DAC_OUT voltage
with buffer OFF
min(2)
-
0.5
-
mV
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
-
-
VREF+ −
1LSB
V
-
170
240
CLOAD(2)
IVREF+(4)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
µA
-
50
75
DS12535 Rev 1
VREF+ ≤VDDA
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
It gives the maximum output excursion of
the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
It gives the maximum output excursion of
the DAC.
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
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184
Electrical characteristics
STM32F750x8
Table 72. DAC characteristics (continued)
Symbol
Min
Typ
Max
Unit
Comments
-
280
380
µA
With no load, middle code (0x800) on the
inputs
-
475
625
µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
±0.5
LSB Given for the DAC in 10-bit configuration.
-
-
±2
LSB Given for the DAC in 12-bit configuration.
-
-
±1
LSB Given for the DAC in 10-bit configuration.
INL(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-
-
±4
LSB Given for the DAC in 12-bit configuration.
-
-
±10
mV Given for the DAC in 12-bit configuration
Offset(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
-
-
±3
LSB
Given for the DAC in 10-bit at VREF+ =
3.6 V
-
-
±12
LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
Gain error
-
-
±0.5
%
Given for the DAC in 12-bit configuration
-
3
6
µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
IDDA(4)
DNL(4)
Gain
error(4)
Parameter
DAC DC VDDA current
consumption in quiescent
mode(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
(4)
tSETTLING
highest input codes when
DAC_OUT reaches final
value ±4LSB
THD(4)
Total Harmonic Distortion
Buffer ON
-
-
-
dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-
-
1
MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Wakeup time from off state
tWAKEUP(4) (Setting the ENx bit in the
DAC Control register)
-
6.5
10
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC
measurement)
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.
142/199
DS12535 Rev 1
STM32F750x8
Figure 39. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R L
DAC_OUTx
12-bit
digital to
analog
converter
C L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.26
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
•
Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0385 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:
Table 73. Minimum I2CCLK frequency in all I2C modes
Symbol
Parameter
Condition
Standard-mode
Fast-mode
f(I2CCLK)
I2CCLK
frequency
Fast-mode Plus
Min
Unit
2
Analog Filtre ON
DNF=0
10
Analog Filtre OFF
DNF=1
9
Analog Filtre ON
DNF=0
22.5
Analog Filtre OFF
DNF=1
16
MHz
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
DS12535 Rev 1
143/199
184
Electrical characteristics
STM32F750x8
The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
•
Tr(SDA/SCL)=0.8473xRpxCload
•
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 74. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
150(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
144/199
DS12535 Rev 1
STM32F750x8
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 75 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 75. SPI dynamic characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Min
Typ
Max
Master mode
SPI1,4,5,6
2.7≤VDD≤3.6
54(2)
Master mode
SPI1,4,5,6
1.71≤VDD≤3.6
27
Master transmitter mode
SPI1,4,5,6
1.71≤VDD≤3.6
54
Slave receiver mode
SPI1,4,5,6
1.71≤VDD≤3.6
-
-
54
Slave mode transmitter/full duplex
SPI1,4,5,6
2.7≤VDD≤3.6
50(3)
Slave mode transmitter/full duplex
SPI1,4,5,6
1.71≤VDD≤3.6
38(3)
Master & Slave mode
SPI2,3
1.71≤VDD≤3.6
27
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
DS12535 Rev 1
Unit
MHz
ns
145/199
184
Electrical characteristics
STM32F750x8
Table 75. SPI dynamic characteristics(1) (continued)
Symbol
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Parameter
Data input setup time
Data input hold time
Conditions
Min
Typ
Max
Master mode
5.5
-
-
Slave mode
4
-
-
Master mode
4
-
-
Slave mode
2
-
-
ta(SO)
Data output access time
Slave mode
7
-
21
tdis(SO)
Data output disable time
Slave mode
5
-
12
Slave mode 2.7≤VDD≤3.6V
-
6.5
10
Slave mode 1.71≤VDD≤3.6V
-
6.5
13
Master mode
-
2
4
Slave mode
1.71≤VDD≤3.6V
5.5
-
-
Master mode
0
-
-
tv(SO)
Data output valid time
tv(MO)
th(SO)
Data output hold time
th(MO)
Unit
ns
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz.
3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
Figure 40. SPI timing diagram - slave mode and CPHA = 0
146/199
DS12535 Rev 1
STM32F750x8
Figure 41. SPI timing diagram - slave mode and CPHA = 1
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
th(NSS)
tc(SCK)
tw(SCKH)
tw(SCKL)
th(SO)
tv(SO)
ta(SO)
MISO
OUTPUT
MSB OUT
tr(SCK)
tf(SCK)
BIT6 OUT
tdis(SO)
LSB OUT
th(SI)
tsu(SI)
MOSI
INPUT
MSB IN
BIT 1 IN
LSB IN
ai14135b
Figure 42. SPI timing diagram - master mode
High
NSS input
SCK Output
tc(SCK)
CPHA= 0
CPOL=0
SCK Output
SCK input
tSU(NSS)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
BIT6 IN
MSB IN
LSB IN
th(MI)
MOSI
OUTPUT
B I T1 OUT
MSB OUT
tv(MO)
LSB OUT
th(MO)
ai14136c
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 76 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
DS12535 Rev 1
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184
Electrical characteristics
STM32F750x8
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 76. I2S dynamic characteristics(1)
Symbol
Parameter
fMCK
I2S Main clock output
fCK
I2S clock frequency
DCK
Conditions
-
Min
256x8K
Max
256xFs
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
30
70
I2S clock frequency duty cycle Slave receiver
tv(WS)
WS valid time
Master mode
-
5
th(WS)
WS hold time
Master mode
0
-
Slave mode
5
-
Slave mode
PCM short pulse mode(3)
3
-
Slave mode
0
-
Slave mode
PCM short pulse mode(3)
2
-
Master receiver
5
-
Slave receiver
1
-
Master receiver
5
-
Slave receiver
1.5
-
Slave transmitter (after enable edge)
-
16
Master transmitter (after enable edge)
-
3.5
Slave transmitter (after enable edge)
5
-
Master transmitter (after enable edge)
0
-
tsu(WS)
WS setup time
th(WS)
WS hold time
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Unit
(2)
MHz
MHz
%
ns
ns
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
Note:
Refer to RM0385 reference manual I2S section for more details on the sampling frequency
(FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. DCK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.
148/199
DS12535 Rev 1
STM32F750x8
Figure 43. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(1)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(1)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
MS46528V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 44. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(1)
MSB transmit
LSB receive(1)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
MS46529V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DS12535 Rev 1
149/199
184
Electrical characteristics
STM32F750x8
SAI characteristics
Unless otherwise specified, the parameters given in Table 77 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C=30 pF
•
Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 77. SAI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCKL
SAI Main clock output
-
256 x 8K
256xFs(2)
MHz
FSCK
SAI clock frequency
Master data: 32 bits
-
128xFs
Slave data: 32 bits
-
128xFs
DSCK
SAI clock frequency duty
cycle
Slave receiver
30
70
tv(FS)
FS valid time
Master mode
8
22
tsu(FS)
FS setup time
Slave mode
2
-
th(FS)
FS hold time
Master mode
8
-
Slave mode
0
-
Master receiver
5
-
Slave receiver
3
-
Master receiver
0
-
Slave receiver
6
-
Slave transmitter (after enable
edge)
-
15
Master transmitter (after enable
edge)
-
20
Master transmitter (after enable
edge)
7
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
Data input setup time
Data input hold time
Data output valid time
tv(SD_MT)
th(SD_MT)
Data output hold time
1. Guaranteed by characterization results.
2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)
150/199
DS12535 Rev 1
MHz
%
ns
STM32F750x8
Figure 45. SAI master timing waveforms
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output)
tv(FS)
th(SD_MT)
tv(SD_MT)
SAI_SD_X
(transmit)
Slot n
tsu(SD_MR)
SAI_SD_X
(receive)
Slot n+2
th(SD_MR)
Slot n
MS32771V1
Figure 46. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X)
SAI_FS_X
(input)
tw(CKL_X)
tsu(FS)
th(FS)
th(SD_ST)
tv(SD_ST)
SAI_SD_X
(transmit)
Slot n
tsu(SD_SR)
SAI_SD_X
(receive)
Slot n+2
th(SD_SR)
Slot n
MS32772V1
DS12535 Rev 1
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184
Electrical characteristics
STM32F750x8
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 78. USB OTG full speed startup time
Symbol
tSTARTUP(1)
Parameter
Max
Unit
USB OTG full speed transceiver startup time
1
µs
1. Guaranteed by design.
Table 79. USB OTG full speed DC electrical characteristics
Symbol
Parameter
Conditions
USB OTG full speed
VDDUSB transceiver operating
voltage
Input
levels
Min.
(1)
Typ.
-
3.0(2)
Max.
(1)
Unit
-
3.6
V
VDI(3)
Differential input sensitivity
I(USB_FS_DP/DM,
USB_HS_DP/DM)
0.2
-
-
VCM(3)
Differential common mode
range
Includes VDI range
0.8
-
2.5
VSE(3)
Single ended receiver
threshold
-
1.3
-
2.0
VOL
Static output level low
RL of 1.5 kΩ to 3.6 V(4)
-
-
0.3
2.8
-
3.6
17
21
24
0.65
1.1
2.0
Output
levels
RPD
RPU
VOH
Static output level high
RL of 15 kΩ to
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VSS(4)
V
V
VIN = VDD
kΩ
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
VIN = VSS
1.5
1.8
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS
0.25
0.37 0.55
2.1
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.
Note:
152/199
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
DS12535 Rev 1
STM32F750x8
Figure 47. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
Table 80. USB OTG full speed electrical characteristics(1)
Driver characteristics
Symbol
tr
tf
trfm
Parameter
Rise time(2)
Fall
time(2)
Conditions
Min
Max
Unit
CL = 50 pF
4
20
ns
CL = 50 pF
4
20
ns
tr/tf
90
110
%
-
1.3
2.0
V
Driving high or
low
28
44
Ω
Rise/ fall time matching
VCRS
Output signal crossover voltage
ZDRV
Output driver impedance(3)
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 83 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 82
and VDD supply voltage conditions summarized in Table 81, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
•
Capacitive load C = 20 pF, unless otherwise specified
•
Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 81. USB HS DC electrical characteristics
Symbol
Input level
Parameter
VDD
USB OTG HS operating voltage
Min.(1)
Max.(1)
Unit
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
DS12535 Rev 1
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184
Electrical characteristics
STM32F750x8
Table 82. USB HS clock timing parameters(1)
Symbol
Parameter
Min
Typ
Max
Unit
-
fHCLK value to guarantee proper operation of
USB HS interface
30
-
-
MHz
FSTART_8BIT
Frequency (first transition)
54
60
66
MHz
FSTEADY
Frequency (steady state) ±500 ppm
59.97
60
60.03
MHz
DSTART_8BIT
Duty cycle (first transition)
40
50
60
%
DSTEADY
Duty cycle (steady state) ±500 ppm
49.975
50
50.025
%
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition
-
-
1.4
ms
Peripheral
-
-
5.6
Host
-
-
-
-
-
-
tSTART_DEV
tSTART_HOST
Clock startup time after the
de-assertion of SuspendM
8-bit ±10%
8-bit ±10%
PHY preparation time after the first transition
of the input clock
tPREP
ms
µs
1. Guaranteed by design.
Figure 48. ULPI timing diagram
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
tSC
tHC
tSD
tHD
data In
(8-bit)
tDC
Control out
(ULPI_STP)
tDC
tDD
data out
(8-bit)
ai17361c
154/199
DS12535 Rev 1
STM32F750x8
Table 83. Dynamic characteristics: USB ULPI(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
tSC
Control in (ULPI_DIR, ULPI_NXT) setup time
-
3
-
-
tHC
Control in (ULPI_DIR, ULPI_NXT) hold time
-
1
-
-
tSD
Data in setup time
-
1.5
-
-
tHD
Data in hold time
-
0.5
-
-
2.7 V < VDD < 3.6 V,
CL = 20 pF and
OSPEEDRy[1:0] = 11
-
5.5
9
-
5.5
11.5
tDC/tDD
Data/control output delay
1.7 V < VDD < 3.6 V,
CL = 15 pF and
OSPEEDRy[1:0] = 11
-
Unit
ns
1. Guaranteed by characterization results.
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 84, Table 85 and Table 86 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 16 and VDD supply voltage conditions summarized in
Table 84, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 20 pF
•
Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 84 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 49 shows the corresponding timing diagram.
Figure 49. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
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Table 84. Dynamics characteristics: Ethernet MAC signals for SMI(1)
Symbol
Min
Typ
Max
MDC cycle time(2.38 MHz)
400
400
403
Td(MDIO)
Write data valid time
10
10.5
12.5
tsu(MDIO)
Read data setup time
12.5
-
-
th(MDIO)
Read data hold time
0
-
-
tMDC
Parameter
Unit
ns
1. Guaranteed by characterization results.
Table 85 gives the list of Ethernet MAC signals for the RMII and Figure 50 shows the
corresponding timing diagram.
Figure 50. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 85. Dynamics characteristics: Ethernet MAC signals for RMII(1)
Symbol
Parameter
Typ
Max
tsu(RXD)
Receive data setup time
1
-
-
tih(RXD)
Receive data hold time
1.5
-
-
tsu(CRS)
Carrier sense setup time
1
-
-
tih(CRS)
Carrier sense hold time
1
-
-
td(TXEN)
Transmit enable valid delay time
5
6
10.5
td(TXD)
Transmit data valid delay time
5
6
12
1. Guaranteed by characterization results.
156/199
Min
DS12535 Rev 1
Unit
ns
STM32F750x8
Table 86 gives the list of Ethernet MAC signals for MII and Figure 50 shows the
corresponding timing diagram.
Figure 51. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
Table 86. Dynamics characteristics: Ethernet MAC signals for MII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
3
-
-
tih(RXD)
Receive data hold time
1.5
-
-
tsu(DV)
Data valid setup time
0
-
-
tih(DV)
Data valid hold time
1.5
-
-
tsu(ER)
Error setup time
1.5
-
-
tih(ER)
Error hold time
0.5
-
-
td(TXEN)
Transmit enable valid delay time
6.5
7
13.5
td(TXD)
Transmit data valid delay time
6.5
7
13.5
Unit
ns
1. Guaranteed by characterization results.
CAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
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Electrical characteristics
6.3.27
STM32F750x8
FMC characteristics
Unless otherwise specified, the parameters given in Table 87 to Table 100 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 52 through Figure 55 represent asynchronous waveforms and Table 87 through
Table 94 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
AddressSetupTime = 0x1
•
AddressHoldTime = 0x1
•
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•
BusTurnAroundDuration = 0x0
•
Capcitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period
158/199
DS12535 Rev 1
STM32F750x8
Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE)
FMC_A[25:0]
t h(A_NOE)
Address
tv(BL_NE)
t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE)
th(Data_NOE)
t su(Data_NE)
Data
FMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FMC_NADV
(1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics
STM32F750x8
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol
Min
Max
2THCLK− 0.5
2 THCLK+1.5
0
1
2THCLK− 1
2THCLK+ 1
FMC_NOE high to FMC_NE high hold time
0
-
FMC_NEx low to FMC_A valid
-
0.5
th(A_NOE)
Address hold time after FMC_NOE high
0
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
th(BL_NOE)
FMC_BL hold time after FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK - 2
-
tsu(Data_NOE)
Data to FMC_NOEx high setup time
THCLK -2
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
FMC_NADV low time
-
THCLK +1
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
tw(NADV)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
Unit
ns
1. CL = 30 pF.
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)
Symbol
Min
Max
FMC_NE low time
7THCLK −1
7THCLK
FMC_NWE low time
5THCLK −1
5THCLK +1
FMC_NWAIT low time
THCLK −0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5THCLK +1.5
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
4THCLK+1
-
tw(NE)
tw(NOE)
tw(NWAIT)
Parameter
1. Guaranteed by characterization results.
160/199
DS12535 Rev 1
Unit
ns
STM32F750x8
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FMC_NWE
tv(A_NE)
FMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FMC_D[15:0]
t v(NADV_NE)
FMC_NADV (1)
tw(NADV)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
Min
Max
FMC_NE low time
3THCLK−0.5
3THCLK+1.5
FMC_NEx low to FMC_NWE low
THCLK−0.5
THCLK+ 1
FMC_NWE low time
THCLK−0.5
THCLK+ 1
FMC_NWE high to FMC_NE high hold time
THCLK −0.5
-
-
0
THCLK−0.5
-
-
0
THCLK−0.5
-
FMC_NEx low to FMC_A valid
th(A_NWE)
Address hold time after FMC_NWE high
tv(BL_NE)
FMC_NEx low to FMC_BL valid
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
tv(Data_NE)
Data to FMC_NEx low to Data valid
-
THCLK+ 3
th(Data_NWE)
Data hold time after FMC_NWE high
THCLK+0.5
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
FMC_NADV low time
-
THCLK+ 0.5
tw(NADV)
Unit
ns
1. Guaranteed by characterization results.
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184
Electrical characteristics
STM32F750x8
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
timings(1)
Symbol
Parameter
tw(NE)
tw(NWE)
Min
Max
FMC_NE low time
8THCLK−0.5
8THCLK+1.5
FMC_NWE low time
6THCLK−0.5
6THCLK+1
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
6THCLK−1
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4THCLK+2
-
Unit
ns
1. Guaranteed by characterization results.
Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FMC_ NE
tv(NOE_NE)
t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
th(A_NOE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NOE)
FMC_ NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
FMC_ AD[15:0]
tsu(Data_NOE)
th(Data_NOE)
Data
Address
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
162/199
DS12535 Rev 1
STM32F750x8
Table 91. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
tw(NE)
tv(NOE_NE)
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
3THCLK−0.5
3THCLK+1.5
FMC_NEx low to FMC_NOE low
2THCLK−1
2THCLK+0.5
FMC_NOE low time
THCLK−0.5
THCLK+0.5
FMC_NOE high to FMC_NE high hold time
0
-
FMC_NEx low to FMC_A valid
-
0.5
FMC_NEx low to FMC_NADV low
0
0.5
THCLK−0.5
THCLK+1.5
FMC_NE low time
FMC_NADV low time
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high)
0
-
th(A_NOE)
Address hold time after FMC_NOE high
THCLK−0.5
-
th(BL_NOE)
FMC_BL time after FMC_NOE high
0
-
FMC_NEx low to FMC_BL valid
-
0.5
tv(BL_NE)
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK−2
-
tsu(Data_NOE)
Data to FMC_NOE high setup time
THCLK−2
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
Unit
ns
1. Guaranteed by characterization results.
Table 92. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol
tw(NE)
tw(NOE)
Parameter
Min
Max
FMC_NE low time
8THCLK−1
8THCLK+2
FMC_NWE low time
5THCLK−1
5THCLK +1
5THCLK +1.5
-
4THCLK+1
-
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
Unit
ns
1. Guaranteed by characterization results.
DS12535 Rev 1
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Electrical characteristics
STM32F750x8
Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FMC_NWE
th(A_NWE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NWE)
FMC_ NBL[1:0]
NBL
t v(A_NE)
FMC_ AD[15:0]
t v(Data_NADV)
Address
th(Data_NWE)
Data
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 93. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
th(AD_NADV)
164/199
Parameter
Min
Max
4THCLK−0.5
4THCLK+1.5
THCLK−1
THCLK+0.5
2THCLK−0.5
2THCLK+0.5
THCLK
-
FMC_NEx low to FMC_A valid
-
0
FMC_NEx low to FMC_NADV low
0
0.5
THCLK−0.5
THCLK+ 1.5
THCLK−2
-
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NADV low time
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(A_NWE)
Address hold time after FMC_NWE high
THCLK
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
THCLK−2
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0
tv(Data_NADV)
FMC_NADV high to Data valid
-
THCLK +2
th(Data_NWE)
Data hold time after FMC_NWE high
THCLK +0.5
-
DS12535 Rev 1
Unit
ns
STM32F750x8
1. Guaranteed by characterization results.
Table 94. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
Symbol
tw(NE)
tw(NWE)
Parameter
FMC_NE low time
FMC_NWE low time
Min
Max
9THCLK
9THCLK+1.5
7THCLK–0.5
7THCLK+0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
6THCLK+2
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4THCLK–1
-
Unit
ns
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 56 through Figure 59 represent synchronous waveforms and Table 95 through
Table 98 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
•
MemoryType = FMC_MemoryType_CRAM;
•
WriteBurst = FMC_WriteBurst_Enable;
•
CLKDivision = 1;
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–
For 2.7 V≤VDD≤3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–
For 1.71 V≤VDD