STM32F765VGH6TR

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Arm® Cortex®-M7 32-bit MCU+FPU, 462 DMIPS, up to 2 MB flash, 512+16+4 KB RAM, USB OTG HS/FS, 28 comm. int., LCD, DSI Datasheet - production data Features • Includes ST state-of-the-art patented technology • Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. • Memories – Up to 2 Mbytes of flash, organized into two banks allowing read-while-write – SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • Dual mode Quad-SPI • Graphics – Chrom-ART Accelerator (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface – Hardware JPEG codec – LCD-TFT controller supporting up to XGA resolution – MIPI® DSI host controller supporting up to 720p 30 Hz resolution • Clock, reset and supply management – 1.7 to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – Dedicated USB power – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) August 2023 This is information on a product in full production. LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm) WLCSP180 LQFP144 (20 × 20 mm) (0.4 mm pitch) LQFP176 (24 × 24 mm) TFBGA216 (13 x 13 mm) TFBGA100 (8 x 8 mm) LQFP208 (28 x 28 mm) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power – Sleep, Stop and Standby modes – VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels • Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer • Debug mode – SWD and JTAG interfaces – Cortex®-M7 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 108 MHz – Up to 166 5 V-tolerant I/Os DS11532 Rev 8 1/256 www.st.com STM32F765xx STM32F767xx STM32F768Ax STM32F769xx • Up to 28 communication interfaces – Up to four I2C interfaces (SMBus/PMBus) – Up to four USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to six SPIs (up to 54 Mbit/s), three with muxed simplex I2S for audio – 2 x SAIs (serial audio interface) – 3 × CANs (2.0B Active) and 2x SDMMCs – SPDIFRX interface – HDMI-CEC – MDIO slave interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit camera interface, up to 54 Mbyte/s • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID Table 1. Device summary Reference 2/256 Part number STM32F765xx STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG STM32F767xx STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI STM32F768Ax STM32F768AI STM32F769xx STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, STM32F769NG, STM32F769NI DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 36 3.20 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 36 3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DS11532 Rev 8 3/256 6 Contents STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.23 4/256 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.23.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 43 3.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 44 3.27 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.28 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.30 Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.31 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 46 3.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 46 3.33 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 47 3.35 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 47 3.36 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 49 3.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.42 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 50 3.43 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.44 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.45 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.46 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.47 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Contents 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 112 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 112 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 112 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 143 6.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 155 6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 DS11532 Rev 8 5/256 6 Contents 7 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 213 6.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 214 6.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 216 6.3.35 DFSDM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 219 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.2 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 7.3 TFBGA100 package information (A08Q) . . . . . . . . . . . . . . . . . . . . . . . . 225 7.4 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 7.5 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.6 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 236 7.7 WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 7.8 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.9 TFBGA216 package information (A0L2) . . . . . . . . . . . . . . . . . . . . . . . . 244 7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 250 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 6/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 33 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 111 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 112 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 112 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode), regulator ON . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 DS11532 Rev 8 7/256 10 List of tables Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. 8/256 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 123 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 124 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 124 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 126 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Flash memory programming (dual bank configuration nDBANK=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 1). . . . . . . . . . . . . . . 154 EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 2). . . . . . . . . . . . . . . 154 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 166 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 167 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. List of tables Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 188 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 189 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 189 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 192 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 192 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 194 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 197 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 202 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 207 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 DFSDM measured timing 1.71-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 220 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 220 LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 TFBGA100 - Example of PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 227 LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DS11532 Rev 8 9/256 10 List of tables STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 131. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 132. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 237 Table 133. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 134. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 135. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 136. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Table 137. TFBGA216 - Example of PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . 247 Table 138. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Table 139. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Table 140. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 250 Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 10/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx block diagram . . . . 20 STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 31 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 35 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 35 STM32F76xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32F76xxx TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32F76xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F76xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32F769xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32F76xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F769Ax/STM32F768Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32F76xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32F769xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32F76xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STM32F769xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 STM32F765xx/STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . 106 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 148 MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 148 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 169 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 169 DS11532 Rev 8 11/256 13 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. 12/256 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 185 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 193 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 194 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 196 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 202 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 206 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 LQFP176 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 WLCSP 180-bump, 5.5 x 6 mm, 1.27 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. List of figures WLCSP180 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 LQFP208 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 LQFP208 - footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 TFBGA216 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 DS11532 Rev 8 13/256 13 Introduction 1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Introduction This document provides information on STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering information. This document must be read in conjunction with the reference manual (RM0410) and the device errata sheet (ES0334), available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical Reference Manual, available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 14/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2 Description Description The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a floating point unit (FPU), which supports Arm® double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU), which enhances the application security. The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices incorporate high-speed embedded memories with a flash up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix, and a multi layer AXI interconnect supporting internal and external memories access. The devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces: - Up to four I2Cs - Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. - Four USARTs plus four UARTs - An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI) - Three CANs - Two SAI serial audio interfaces - Two SDMMC host interfaces - Ethernet and camera interfaces - LCD-TFT display controller - Chrom-ART Accelerator - SPDIFRX interface - HDMI-CEC Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. DS11532 Rev 8 15/256 54 Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. These features make the STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx microcontrollers suitable for a wide range of applications: - Motor drive and application control - Medical equipment - Industrial applications: PLC, inverters, circuit breakers - Printers, and scanners - Alarm systems, video intercom, and HVAC - Home audio appliances - Mobile applications, Internet of Things - Wearable devices: smartwatches The following table lists the peripherals available on each part number. 16/256 DS11532 Rev 8 Peripherals Flash memory in Kbytes SRAM in Kbytes STM32F 765Vx 1024 2048 STM32F767 /769Vx 1024 STM32F 765Zx STM32F767 /769Zx STM32F 769Ax 2048 1024 2048 1024 2048 1024 2048 2048 STM32F 765Ix STM32F767 /769Ix STM32F 765Bx STM32F767 /769Bx 1024 2048 1024 2048 1024 2048 1024 2048 System 512(368+16+128) Instruction 16 Backup 4 STM32F 765Nx 1024 2048 STM32F767 /769Nx 1024 2048 Yes(1) FMC memory controller Quad-SPI Yes Ethernet Yes DS11532 Rev 8 Timers No 10 Advancedcontrol 2 Basic 2 Low-power 1 SPI / I2S Yes 4/3 (simplex)(2) 6/3 (simplex)(2) 5 (simplex)(2) I2C Communication interfaces Yes Generalpurpose Random number generator 6/3 (simplex)(2) 4 USART/UART 4/4 USB OTG FS Yes USB OTG HS Yes CAN 3 SAI 2 SPDIFRX 4 inputs Yes SDMMC2 Yes(3) Yes 17/256 (4) No MIPI-DSI Host No Yes Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes Description SDMMC1 Camera interface LCD-TFT STM32F 768Ax STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 2. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx features and peripheral counts Peripherals STM32F 765Vx STM32F767 /769Vx STM32F 765Zx STM32F767 /769Zx STM32F 769Ax STM32F 768Ax Chrom-ART Accelerator (DMA2D) JPEG codec GPIOs No Yes No 82 Yes 114 128 STM32F 765Bx STM32F767 /769Bx STM32F 765Nx STM32F767 /769Nx No Yes No Yes No Yes 140 132 168 159 168 168 159 Yes (4 filters) 12-bit ADC 3 16 24 Yes 2 12-bit DAC Number of channels 216 MHz(5) Maximum CPU frequency DS11532 Rev 8 Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Junction temperature: –40 to + 125 °C LQFP100 TFBGA100 LQFP144 WLCSP180 UFBGA176(7) LQFP176 LQFP208 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. SPI5 is not available on STM32F769Ax. TFBGA216 3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 4. DSI host interface is only available on STM32F769x sales types. 5. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range). 6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.18.2: Internal reset OFF). 7. UFBGA176 is not available for STM32F769x sales types. STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1.7 to 3.6 V(6) Operating voltage Package STM32F767 /769Ix Yes DFSDM1 Number of channels STM32F 765Ix Description 18/256 Table 2. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx features and peripheral counts (continued) STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description Full compatibility throughout the family The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher frequency for a greater degree of freedom during the development cycle. Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package PC3 VDD VSSA VREF+ VDDA PA0-WKUP PA1 PA2 STM32F427xx / STM32F437xx STM32F429xx / STM32F439xx STM32F415xx / STM32F417xx STM32F405xx / STM32F407xx 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 VDD PB11 VCAP1 PB10 PE15 PE14 PE12 PE13 PE11 PE9 PE10 PE7 PE8 PB1 PB2 PC5 PB0 PC4 PA7 PA5 PA6 PA4 VDD PA3 PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 STM32F76xxx Pins 19 to 49 are not compatible VDD VSS VCAP1 PB11 PB10 PE15 PE14 PE12 PE13 PE11 PE10 PE9 PE8 PE7 PB2 PB1 PB0 PC4 PC5 PA7 PA6 PA4 PA5 VDD VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MSv39136V1 The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are fully pin to pin compatible with STM32F4xx devices. DS11532 Rev 8 19/256 54 Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 2. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx block diagram USB DMA/ OTG HS FIFO GP-DMA2 8 Streams FIFO GP-DMA1 8 Streams FIFO LCD-TFT FIFO SRAM1 368KB SRAM2 16 KB AHB2 216 MHZ (DMA2D) Quad-SPI AHB1 216 MHz PB[15:0] GPIO PORT B Int PVD RC HS PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E PF[15:0] GPIO PORT F PG[15:0] GPIO PORT G PH[15:0] GPIO PORT H @VDD33 VDD12 PLL1+PLL2+PLL3 GPIO PORT J FIFO FIFO 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels TIM12 16b 2 channels as AF 1 channel as AF TIM14 16b 1 channel as AF USART2 smcard irDA RX, TX, SCK CTS, RTS as AF USART3 smcard irDA UART4 RX, TX, SCK CTS, RTS as AF RX, TX as AF UART5 RX, TX as AF UART7 RX, TX as AF UART8 RX, TX as AF MOSI, MISO, SCK NSS as AF MOSI, MISO, SCK NSS as AF SCL, SDA, SMBAL as AF SPI4 LPTIM1 SPI5 16b TIM6 16b TIM7 16b FIFO FIFO SPI6 SD, SCK, FS, MCLK as AF SAI1 SAI2 SPI3/I2S3 I2C1/SMBUS I2C2/SMBUS SYSCFG DFSDM I2C3/SMBUS MDIO Slave @VDDA bxCAN1 DSI HOST ADC1 PLL ADC2 IF IF LDO bxCAN2 @VDDA DAC1 SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF I2C4/SMBUS U STemperature AR T 2 M Bsensor ps ADC3 SPI2/I2S2 Digital filter SPI1/I2S1 WWDG A P B(max) 10 MHz 3 APB1 54 MHz 16b TIM11 smcard USART1 irDA smcard USART6 irDA MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF APB2 108 MHz (max) 16b 16b 8 analog inputs for ADC3 AHB/APB1 TIM2 TIM13 TIM10 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 OSC32_IN OSC32_OUT RTC_TS RTC_TAMPx RTC_OUT 16b 1 channel as AF VDDREF_ADC RTC AWU Backup register TIM8 / PWM 16b SD, SCK, FS, MCLK as AF CKIN[7:0] DATAIN[7:0] CKOUT CKIN[7:0] DATAIN[7:0] CKOUT XTAL 32 kHz TIM1 / PWM TIM9 RX, TX, SCK, CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF GPDMA1 AHB/APB2 VBAT = 1.8 to 3.6 V 16b 2 channels as AF 1 channel as AF LS EXT IT. WKUP SDMMC1 OSC_IN OSC_OUT 4 KB BKPRAM GPIO PORT K SDMMC2 VDDA, VSSA NRESET WKUP[4:0] VDDMMC33 = 1.8 to 3.6V VDDUSB33 = 3.0 to 3.6 V VDD = 1.8 to 3.6 V VSS VCAP1 @VSW CRC GPDMA2 CLK, CS,D[7:0] @VDD33 Standby interface @VDDA 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF VOLT. REG 3.3V TO 1.2V DP DM SCL, SDA, INT, ID, VBUS CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0], SDNE[1:0], SDNWE, NL NRAS, NCAS, NADV NWAIT, INTN WDG32K RCC Reset & control M GT LS GPIO PORT I PJ[15:0] BBgen + POWER MNGT XTAL OSC 4- 16MHz FCLK HCLK APBP2CLK APBP1CLK AHB2PCLK AHB1PCLK PI[15:0] D[7:0] CMD, CK as AF D[7:0] CMD, CK as AF 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF @VDDA SUPPLY SUPERVISION POR/PDR BOR POR reset RC LS GPIO PORT A 168 AF USB EXT MEM CTL (FMC) SRAM, SDRAM, NOR-Flash, NAND-Flash, SDRAM FIFO PA[15:0] HSYNC, VSYNC PUIXCLK, D[13:0] OTG FS @VDDA CHROM-ART PK[7:0] FIFO RNG PHY FIFO Camera ITF TX, RX FIFO LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK DMA/ 10/100 JPEG FLASH 1MB PWRCTRL DP, DM ULPI:CK, D[7:0], DIR, STP, NXT SCL/SDA, INT, ID, VBUS FLASH 1MB ACCEL/ CACHE D-Cache AHBP 16KB AHBS Ethernet MAC PHY MII or RMII as AF MDIO as AF ITCM RAM 16KB AXIM I-Cache 16KB 216MHz DTCM RAM 128KB FIFO Arm CPU Cortex-M7 AHB BUS-MATRIX 11S8M AHB bus-matrix 8S7M TRACECK TRACED[3:0] MPU FPU NVIC DTCM ICTM FIFO JTAG & SW ETM AHB2AXI JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO TX, RX bxCAN3 TX, RX SPDIFRX SPDIFRX[3:0] as AF HDMI-CEC HDMI_CEC as AF ITF DSI PHY DSI_DOP/N, DSI_D1P/N DSI_VCAP, DSI_CKP/N DSI_VDD12, DSI_VSS, DSI_TE as AF DAC2 DAC1 as AF DAC2 as AF MSv41056V2 1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 20/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU Functional overview The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering an outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring: – Six-stage dual-issue pipeline – Dynamic branch prediction – Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) – 64-bit AXI4 interface – 64-bit ITCM interface – 2x32-bit DTCM interfaces The processor supports the following memory interfaces: • Tightly Coupled Memory (TCM) interface. • Harvard instruction and data caches and AXI master (AXIM) interface. • Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow an efficient signal processing and a complex algorithm execution. It supports single and double precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 2 shows the general block diagram of the STM32F76xxx family. Note: The Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS11532 Rev 8 21/256 54 Functional overview 3.3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Embedded Flash memory The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. The Flash interface features: 3.4 • Single /or Dual bank operating modes, • Read-While-Write (RWW) in Dual bank mode. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Embedded SRAM All the devices feature: • • System SRAM up to 512 Kbytes: – SRAM1 on AHB bus Matrix: 368 Kbytes – SRAM2 on AHB bus Matrix: 16 Kbytes – DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: – It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 22/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.6 Functional overview AXI-AHB bus matrix The STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx system architecture is based on 2 sub-systems: • An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: • – 3x AXI to 32-bit AHB bridges connected to AHB bus matrix – 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix – The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. AHBS DMA2D Chrom-ART Accelerator (DMA2D) LCD-TFT_M USB_HS_M ETHERNET_M DMA_P2 GP MAC USB OTG LCD-TFT DMA2 Ethernet HS DMA_MEM2 AHBP 16KB I/D Cache AXIM GP DMA1 DMA_PI Arm Cortex-M7 DMA_MEM1 ITCM DTCM Figure 3. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx AXI-AHB bus matrix architecture(1) DTCM RAM 128KB ITCM RAM 16KB AXI to multi-AHB ART ITCM 64-bit AHB FLASH 2MB 64-bit BuS Matrix SRAM1 368KB SRAM2 16KB AHB periph1 AHB periph2 FMC external MemCtl APB1 APB2 QuadSPI 32-bit Bus Matrix - S MSv39103V2 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. DS11532 Rev 8 23/256 54 Functional overview 3.7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and the transfer sizes between the source and the destination are independent. The DMA can be used with the main peripherals: 24/256 • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDMMC • Camera interface (DCMI) • ADC • SAI • SPDIFRX • Quad-SPI • HDMI-CEC • JPEG codec • DFSDM1 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.8 Functional overview Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller • The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories • 8-,16-,32-bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • Read FIFO for SDRAM controller • The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: • Direct mode through registers • External Flash status register polling mode • Memory mapped mode. Up to 256 Mbytes external Flash are memory mapped, supporting 8, 16 and 32-bit access. Code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. DS11532 Rev 8 25/256 54 Functional overview 3.10 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.11 • 2 display layers with dedicated FIFO (64x32-bit) • Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer • Up to 8 input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to 4 programmable interrupt events Chrom-ART Accelerator (DMA2D) The Chrom-Art Accelerator (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion Various image format codings are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 26/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.13 Functional overview JPEG codec (JPEG) The JPEG codec provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features: 3.14 • 8-bit/channel pixel depths • Single clock per pixel encoding and decoding • Support for JPEG header generation and parsing • Up to four programmable quantization tables • Fully programmable Huffman tables (two AC and two DC) • Fully programmable minimum coded unit (MCU) • Encode/decode support (non simultaneous) • Single clock Huffman coding and decoding • Two-channel interface: Pixel/Compress In, Pixel/Compressed Out • Stallable design • Support for single, greyscale component • Functionality to enable/disable header processing • Internal register interface • Fully synchronous design • Configured for high-speed decode mode External interrupt/event controller (EXTI) The external interrupt/event controller consists of 25 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 3.15 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. DS11532 Rev 8 27/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.16 Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space mapped on ITCM or AXIM interface • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface • The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to STM32 microcontroller system memory boot mode application note (AN2606) for details. 3.17 Note: Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. • • 28/256 VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: – During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD – During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD – The VDDSDMMC rising and falling time rate specifications must be respected – In operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview disappear. The following conditions VDDUSB must be respected: – During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD – The VDDUSB rising and falling time rate specifications must be respected – In operating mode phase, VDDUSB could be lower or higher than VDD: - If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 4. VDDUSB connected to VDD power supply VDD VDD_MAX VDD= VDDA = VDDUSB VDD_MIN Power-on Operating mode Power-down time MS37591V1 DS11532 Rev 8 29/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 5. VDDUSB connected to external power supply VDDUSB_MAX USB functional area VDDUSB VDDUSB_MIN USB non functional area VDD = VDDA Power-on Operating mode USB non functional area VDD_MIN time Power-down MS37590V1 The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins: • VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global VDD. • The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally to VDD12DSI. • The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin. • The VSSDSI pin is an isolated supply ground used for DSI sub-system. • If the DSI functionality is not used at all, then: – The VDDDSI pin must be connected to global VDD. – The VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed. – The VSSDSI pin must be grounded. 3.18 Power supply supervisor 3.18.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through 30/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.18.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V NRST VDD Application reset signal PDR_ON VSS MS31383V4 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All the packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. DS11532 Rev 8 31/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 7. PDR_ON control with internal reset OFF V DD PDR = 1.7 V time Reset by other source than power supply supervisor NRST PDR_ON PDR_ON time MS19009V7 3.19 Voltage regulator The regulator has four operating modes: • • 3.19.1 Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: • MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). 32/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx • Functional overview LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: • – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.19.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In the regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. • The over-drive and under-drive modes are not available. • The Standby mode is not available. DS11532 Rev 8 33/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 8. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor Ext. reset controller active signal (optional) when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V3 The following conditions must be respected: Note: 34/256 • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization VDD PDR = 1.7 or 1.8 V V12 Min V12 VCAP_1, VCAP_2 time NRST PA0 time ai18491g 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492e 1. This figure is valid whatever the internal reset mode (ON or OFF). DS11532 Rev 8 35/256 54 Functional overview 3.19.3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 LQFP144, LQFP208 LQFP176, UFBGA176, TFBGA100, TFBGA216 WLCSP180 Yes Internal reset ON Internal reset OFF Yes No No Yes Yes Yes Yes BYPASS_REG set BYPASS_REG set PDR_ON set to VDD PDR_ON set to VSS to VDD to VSS Yes(1) 1. Available only on dedicated part number. Refer to Section 8: Ordering information. 3.20 Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. 36/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator(LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 3.21 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): – Normal mode (default mode when MR or LPR is enabled) – Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode • Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering DS11532 Rev 8 37/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 3.22 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and the VBAT pin should be connected to VDD. 3.23 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. 38/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DS11532 Rev 8 39/256 54 Functional overview 3.23.1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.23.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F76xxx devices (see Table 6 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F76xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.23.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 40/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.23.4 Functional overview Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.23.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous / one-shot mode • Selectable software / hardware input trigger • Selectable clock source: • Internal clock source: LSE, LSI, HSI or APB clock • External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) • Programmable digital glitch filter • Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.23.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.23.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source DS11532 Rev 8 41/256 54 Functional overview 3.24 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Inter-integrated circuit interface (I2C) The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X 1. X: supported. 42/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.25 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USART. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: • Full-duplex asynchronous communications • Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance • Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming • A common programmable transmit and receive baud rate of up to 27 Mbit/s when the USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. • Auto baud rate detection • Programmable data word length (7 or 8 or 9 bits) word length • Programmable data order with MSB-first or LSB-first shifting • Programmable parity (odd, even, no parity) • Configurable stop bits (1 or 1.5 or 2 stop bits) • Synchronous mode and clock output for synchronous communications • Single-wire half-duplex communications • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Multiprocessor communications • LIN master synchronous break send capability and LIN slave break detection capability • IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode • Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard ) • Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DS11532 Rev 8 43/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 3.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 54 Mbits/s, SPI2 and SPI3 can communicate at up to 27 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 3.27 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. 44/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview SAI1 and SAI2 can be served by the DMA controller 3.28 SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main features of the SPDIFRX are the following: • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.288 MHz • Stereo stream from 32 to 192 kHz supported • Supports Audio IEC-60958 and IEC-61937, consumer applications • Parity bit management • Communication using DMA for audio samples • Communication using DMA for control and user channel information • Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX re-samples the incoming signal, decodes the manchester stream, recognizes frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that is used to compute the exact sample rate for clock drift algorithms. 3.29 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.30 Audio and LCD PLL (PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. DS11532 Rev 8 45/256 54 Functional overview 3.31 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support the MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 3.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: 46/256 • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.33 Functional overview Controller area network (bxCAN) The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM are dedicated for CAN3. 3.34 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support • HNP/SNP/IP inside (no need for any external resistor) For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 3.35 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support DS11532 Rev 8 47/256 54 Functional overview 3.36 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.37 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It features: 48/256 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 3.38 Functional overview Management Data Input/Output (MDIO) slaves The devices embed a MDIO slave interface it includes the following features: • – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers • Configurable slave (port) address • Independently maskable interrupts/events: • 3.39 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: – MDIO Register write – MDIO Register read – MDIO protocol error Able to operate in and wake up from STOP mode Random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.40 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. A fast I/O handling allows a maximum I/O toggling up to 108 MHz. 3.41 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. DS11532 Rev 8 49/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 3.42 Digital filter for Sigma-Delta Modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). The DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – Configurable SPI interface to connect various SD modulator(s) – Configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – Clock output for SD modulator(s): 0..20 MHz Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • – Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • Up to 24-bit output data resolution, signed output data format • Automatic data offset correction (offset stored in register by user) • Continuous or single conversion • Start-of-conversion triggered by: • • 50/256 internal sources: device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: – Software trigger – Internal timers – External events – Start-of-conversion synchronously with first digital filter module (DFSDM0) Analog watchdog feature: – Low value and high value data threshold registers – Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – Input from final output data or from selected input digital serial channels – Continuous monitoring independently from standard conversion Short circuit detector to detect saturated analog input values (bottom and top range): – Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – Monitoring continuously each input serial channel DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview • Break signal generation on analog watchdog event or on short circuit detector event • Extremes detector: – Storage of minimum and maximum values of final conversion data – Refreshed by software • DMA capability to read the final conversion data • Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Table 9. DFSDM implementation DFSDM features DFSDM1 Number of filters: x (DFSDM_FLTx) 4 Number of input transceivers/channels: y (DFSDM_CHy) 8 Internal ADC parallel input support - Number of external triggers (JEXTSEL size) ID register support 32 - DS11532 Rev 8 51/256 54 Functional overview 3.43 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.44 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • Two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.45 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.46 Embedded Trace Macrocell™ The Arm embedded trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F76xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or 52/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 3.47 DSI Host (DSIHOST) The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. These interfaces are as follows: • • • LTDC interface: – Used to transmit information in Video mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI). – Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command mode (DBI). APB slave interface: – Allows the transmission of generic information in Command mode, and follows a proprietary register interface. – Can operate concurrently with either LTDC interface in either Video mode or Adapted Command mode. Video mode pattern generator: – Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli. The DSI Host main features: • Compliant with MIPI® Alliance standards • Interface with MIPI® D-PHY • Supports all commands defined in the MIPI® Alliance specification for DCS: – Transmission of all Command mode packets through the APB interface – Transmission of commands in low-power and high-speed during Video mode • Supports up to two D-PHY data lanes • Bidirectional communication and escape mode support through data lane 0 • Supports non-continuous clock in D-PHY clock lane for additional power saving • Supports Ultra Low-power mode with PLL disabled • ECC and Checksum capabilities • Support for End of Transmission Packet (EoTp) • Fault recovery schemes • 3D transmission support • Configurable selection of system interfaces: • – AMBA APB for control and optional support for Generic and DCS commands – Video Mode interface through LTDC – Adapted Command mode interface through LTDC Independently programmable Virtual Channel ID in DS11532 Rev 8 53/256 54 Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx – Video mode – Adapted Command mode – APB Slave Video Mode interfaces features: • LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2, and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB • Programmable polarity of all LTDC interface signals • Maximum resolution is limited by available DSI physical link bandwidth: – Number of lanes: 2 – Maximum speed per lane: 500 Mbps1Gbps Adapted interface features Support for sending large amounts of data through the memory_write_start(WMS) and memory_write_continue(WMC) DCS commands • LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2, and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB Video mode pattern generator: 54/256 • Vertical and horizontal color bar generation without LTDC stimuli • BER pattern without LTDC stimuli DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 11. STM32F76xxx LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP1 VSS VDD 4 Pinouts and pin description MSv34171V2 1. The above figure shows the package top view. DS11532 Rev 8 55/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 12. STM32F76xxx TFBGA100 pinout 1 2 3 5 6 7 8 A PC14 PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15 VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C PH0 VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 PH1 VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 NRST PC2 PE6 VSS VSS BYPASS -REG VCAP_2 PD1 PC9 PC7 PC0 PC1 PC3 VDD VDD VDDUSB PDR_ON VCAP_1 PC8 PC6 VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15 H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14 J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 D E F G 4 9 10 MSv40497V1 1. The above figure shows the package top view. 56/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 13. STM32F76xxx LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 MS39132V1 1. The above figure shows the package top view. DS11532 Rev 8 57/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 V 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 Figure 14. STM32F76xxx LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 without DSI 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 VCAP_1 VDD PH6 PH7 PH8 PH9 PH10 PH11 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 MS39123V1 1. The above figure shows the package top view. 58/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description DD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI1 V 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 Figure 15. STM32F769xx LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 with DSI 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI0 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 VSSDSI DSI_D1N DSI_D1P VDD12DSI DSI_CKN DSI_CKP VSSDSI DSI_D0N DSI_D0P VCAPDSI VDDDSI PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 VCAP_1 VDD PH6 PH7 PB12 PB13 PB14 PB15 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 PH4 PH5 PA3 BYPASS_REG VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 MS41054V1 1. The above figure shows the package top view. DS11532 Rev 8 59/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 16. STM32F76xxx UFBGA176 ballout 1 2 A PE3 PE2 B PE4 C 3 4 5 6 7 8 9 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 VBAT PI7 PI6 PI5 VDD 11 12 13 14 15 PB3 PD7 PC12 PA15 PA14 PA13 PG11 PG10 PD6 PD0 PC11 PC10 PA12 VDD SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 PDR_ON VDD BOOT0 VSS VSS 10 VCAP_1 MS39130V1 1. The above figure shows the package top view. Note: On the UFBGA176 package, the following balls are connected to Vss for package mechanical stability and for heat dissipation purposes: F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10. 60/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 17. STM32F769Ax/STM32F768Ax WLCSP180 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 A NC(1) NC(1) PA14(JTCK -SWCLK) PD0 PD4 VDDMMC PG10 VSS PB5 BOOT0 VSS NC(1) NC(1) B NC(1) VDD PI1 PC10 PD3 VSS PG11 VDD PB6 PE1 VDD PI7 NC(1) C VCAP_2 VSS PI2 PC11 PD5 PG9 PG13 PB7 PE0 PDR_ON PI6 PE4 VBAT D PA12 PA13(JTMS -SWDIO) PI3 PC12 PD1 PD2 PG12 PB4(NJ TRST) PB9 PI4 PI5 PE5 PC13 E PC9 PA8 PA11 PI0 PH15 PD6 PD7 PB3(JTDO/ TRACESWO) PB8 PE2 PE6 PC15OSC32 _IN PC15OSC32_ OUT F VSS VDDUSB PC7 PA9 PA10 PH13 PH14 PA15(JTDI) PG15 PE3 PI11 VDD VSS G PG4 PG5 PG6 PG7 PG8 PC6 PC8 PG3 PI9 PF0 PF1 PF2 H DSI_D1P DSI_D1N DSI_CKN DSI_CKP VSSDSI VCAPDSI PB12 PG2 PI10 PF3 PF4 PF5 J DSI_D0P DSI_D0N VDD12DSI PD12 PB13 PE10 PB2 PB1 VSS PA2 PA1 VDD VSS K VDDDSI PD15 PD11 PH9 PB10 PE11 PF12 PF14 VDD PH3 PF10 PH0OSC_IN PH1OSC_OUT L PD14 PD13 PD9 PH10 PB11 PE12 PG1 PF13 PA4 PH2 NRST PC0 PC1 M VSS PD10 PD8 PH11 PH8 PE15 PE7 VDD PA7 PA3 VSSA VDDA PA0-WKUP N NC(1) PB15 PB14 VSS VSS PE14 PE8 PG0 PF11 PA6 PH5 PH4 NC(1) P NC(1) NC(1) PH12 VDD VCAP_1 PE13 PE9 PF15 VSS PB0 PA5 NC(1) NC(1) MSv39614V1 1. NC ball must not be connected to GND nor to VDD. 2. The above figure shows the package top view. DS11532 Rev 8 61/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 LQFP208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PI2 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PK2 PK1 PK0 VSS VDD PJ11 PJ10 PJ9 PJ8 PJ7 PJ6 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PA4 PA5 PA6 PA7 PC4 PC5 VDD VSS PB0 PB1 PB2 PI15 PJ0 PJ1 PJ2 PJ3 PJ4 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VSS VDD PJ5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 VDD PB12 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PI12 PI13 PI14 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 PH4 PH5 PA3 VSS VDD 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PI7 PI6 PI5 PI4 VDD PDR_ON VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PK7 PK6 PK5 PK4 PK3 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PJ15 PJ14 PJ13 PJ12 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD PI3 Figure 18. STM32F76xxx LQFP208 pinout 1. The above figure shows the package top view. 62/256 DS11532 Rev 8 MSv39131V1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 LQFP208 with DSI 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PI2 PI1 PI0 PH15 PH14 PH13 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 VSSDSI DSI_D1N DSI_D1P VDD12DSI DSI_CKN DSI_CKP VSSDSI DSI_D0N DSI_D0P VCAPDSI VDDDSI PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PA4 PA5 PA6 PA7 PC4 PC5 VDD VSS PB0 PB1 PB2 PI15 PJ0 PJ1 PJ2 PJ3 PJ4 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VSS VDD PJ5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 VDD PB12 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14 PC15 PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PI12 PI13 PI14 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 PH4 PH5 PA3 VSS VDD 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PI7 PI6 PI5 PI4 VDD PDR_ON VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PK7 PK6 PK5 PK4 PK3 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PJ15 PJ14 PJ13 PJ12 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD PI3 Figure 19. STM32F769xx LQFP208 pinout MSv39124V1 1. The above figure shows the package top view. DS11532 Rev 8 63/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 20. STM32F76xxx TFBGA216 ballout 1 2 3 4 5 6 7 8 9 10 11 A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 E PC14 PF1 PI12 PI9 PDR_ ON BOOT0 VDD VDD F PC15 VSS PI11 VDD VDD VSS VSS VSS G PH0 PF2 PI13 PI15 VDD VSS VSS H PH1 PF3 PI14 PH4 VDD VSS VSS VDD J NRST PF4 PH5 PH3 VDD VSS VSS K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS PF10 PF9 PF8 PC3 BYPASSVSS REG VDD VDD M VSSA PC0 PC1 PC2 PB2 PF12 PG1 N VREF- PA1 PA0 PA4 PC4 PF13 P VREF+ PA2 PA6 PA5 PC5 R VDDA PA3 PA7 PB1 PB0 L 13 14 15 PC12 PA15 PA14 PA13 PD6 PD0 PC11 PC10 PA12 PD5 PD3 PD1 PI3 PI2 PA11 PJ15 PD4 PD2 PH15 PI1 PA10 VCAP2 PH13 PH14 PI0 PA9 VDD PK1 PK2 PC9 PA8 VDDUSB PJ11 PK0 PC8 PC7 PJ8 PJ10 PG8 PC6 VDD PJ7 PJ9 PG7 PG6 VSS VDD PJ6 PD15 PB13 PD10 VDD VDD VCAP1 PD14 PB12 PD9 PD8 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15 VDD VDD SDMMC VSS VSS 12 MS39129V1 1. The above figure shows the package top view. 64/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 21. STM32F769xx TFBGA216 ballout 1 2 3 4 5 6 7 8 9 10 11 A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 E PC14 PF1 PI12 PI9 PDR_ ON BOOT0 VDD VDD 13 14 15 PC12 PA15 PA14 PA13 PD6 PD0 PC11 PC10 PA12 PD5 PD3 PD1 PI3 PI2 PA11 PJ15 PD4 PD2 PH15 PI1 PA10 PH13 PH14 PI0 PA9 F PC15 VSS PI11 VDD VDD VSS VSS VSS DSI_ D1P DSI_ D1N PC9 PA8 G PH0 PF2 PI13 PI15 VDD VSS VSS VDDUSB VSSDSI VDD12 PC8 DSI PC7 H PH1 PF3 PI14 PH4 VDD VSS VSS J NRST PF4 PH5 PH3 VDD VSS VSS VDD K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS PF10 PF9 PF8 PC3 BYPASSVSS REG VDD VDD VDD VDD VCAP1 PD14 M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 L VDD SDMMC VDD VCAP2 VSS VSS VDD 12 VDDDSI DSI_ CKP DSI_ CKN PG8 PC6 DSI_ D0P DSI_ D0N PG7 PG6 VDD VCAPDSI PD15 PB13 PD10 PB12 PD9 PD8 PG3 PG2 PJ5 PH12 PG5 PG4 PH7 PH9 PH11 PE11 PE14 PB10 PH6 PH8 PH10 PE12 PE15 PE13 PB11 PB14 PB15 MS39125V1 1. The above figure shows the package top view. DS11532 Rev 8 65/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 10. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT pin RST Bidirectional reset pin with weak pull-up resistor Pin type I/O structure Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions 1 A3 PE2 I/O FT - B3 2 2 A1 2 2 A2 F10 2 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT 66/256 TFBGA216 1 LQFP208 E10 LQFP176 A3 WLCSP180(1) 1 TFBGA216 1 LQFP208 A2 LQFP176 1 UFBGA176 1 LQFP144 A3 TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, ETH_MII_TXD3, FMC_A23, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure STM32F768Ax STM32F769xx Pin type STM32F765xx STM32F767xx Pin name (function after reset Pin Number DS11532 Rev 8 Additional functions - - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) D3 3 4 4 B1 B2 3 4 3 4 A1 B1 C12 D12 E3 5 5 B3 5 5 B2 E11 - - - - - - G6 - - - - - - - F5 - B2 6 6 C1 6 6 C1 C13 - - - D2 7 7 C2 A2 7 7 D1 8 8 A1 8 8 E1 9 B1 9 9 F1 - - - - - - 3 4 5 3 4 A1 B1 PE4 PE5 PE6 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 3 STM32F768Ax STM32F769xx FT FT Alternate functions Additional functions - TRACED1, SPI4_NSS, SAI1_FS_A, DFSDM1_DATIN3, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, DFSDM1_CKIN3, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT - 5 B2 - - G6 VSS S - - - - - - F5 VDD S - - - - 6 6 C1 VBAT S - - - - NC 7 7 C2 PI8 I/O FT (2) EVENTOUT RTC_TAMP2/ RTC_TS/ WKUP5 D1 D13 8 8 D1 PC13 I/O FT (2) EVENTOUT RTC_TAMP1/ RTC_TS/ RTC_OUT/ WKUP4 9 E1 E12 9 9 E1 PC14OSC32_IN I/O FT (2) (3) EVENTOUT OSC32_IN 10 10 F1 E13 10 10 F1 PC15OSC32_O UT I/O FT (2) (3) EVENTOUT OSC32_OUT - - - G5 - - - G5 VDD S - - - - - D3 11 11 E4 G10 11 11 E4 PI9 I/O FT - UART4_RX, CAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT - - - E3 12 12 D5 H10 12 12 D5 PI10 I/O FT - ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT - - - - E4 13 13 F3 F11 13 13 F3 PI11 I/O FT - LCD_G6, OTG_HS_ULPI_DIR, EVENTOUT WKUP6 - - - F2 14 14 F2 F13 14 14 F2 VSS S - - - - DS11532 Rev 8 FT Notes C3 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number 67/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx - - - F3 15 15 F4 F12 15 15 F4 VDD S - - - - - - 10 E2 16 16 D2 G11 16 16 D2 PF0 I/O FT - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 H3 17 17 E2 G12 17 17 E2 PF1 I/O FT - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 H2 18 18 G2 G13 18 18 G2 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - - - 19 E3 NC - 19 E3 PI12 I/O FT - LCD_HSYNC, EVENTOUT - - - - - - 20 G3 NC - 20 G3 PI13 I/O FT - LCD_VSYNC, EVENTOUT - - - - - - 21 H3 NC - 21 H3 PI14 I/O FT - LCD_CLK, EVENTOUT - - - 13 J2 19 22 H2 H11 19 22 H2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - 14 J3 20 23 J2 H12 20 23 J2 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - 15 K3 21 24 K3 H13 21 24 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 C2 10 16 G2 22 25 H6 J13 22 25 H6 VSS S - - - - D2 11 17 G3 23 26 H5 J12 23 26 H5 VDD S - - - - ADC3_IN4 Additional functions - - 18 K2 24 27 K2 NC 24 27 K2 PF6 I/O FT - TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, EVENTOUT - - 19 K1 25 28 K1 NC 25 28 K1 PF7 I/O FT - TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT ADC3_IN5 - - 20 L3 26 29 L3 NC 26 29 L3 PF8 I/O FT - SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 - - 21 L2 27 30 L2 NC 27 30 L2 PF9 I/O FT - SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_IN7 - - 22 L1 28 31 L1 K11 28 31 L1 PF10 I/O FT - QUADSPI_CLK, DCMI_D11, LCD_DE, EVENTOUT ADC3_IN8 C1 12 23 G1 29 32 G1 K12 29 32 G1 PH0OSC_IN I/O FT (3) EVENTOUT OSC_IN 68/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx D1 13 24 H1 30 33 H1 K13 30 33 H1 PH1OSC_OUT I/O FT (3) EVENTOUT OSC_OUT E1 14 25 J1 31 34 J1 L11 31 34 J1 NRST I/O RS T - - - - DFSDM1_CKIN0, DFSDM1_DATIN4, SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, EVENTOUT ADC1_IN10, ADC2_IN10, ADC3_IN10 - TRACED0, DFSDM1_DATIN0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, DFSDM1_CKIN4, ETH_MDC, MDIOS_MDC, EVENTOUT ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3/ WKUP3 - DFSDM1_CKIN1, SPI2_MISO, DFSDM1_CKOUT, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC1_IN12, ADC2_IN12, ADC3_IN12 ADC1_IN13, ADC2_IN13, ADC3_IN13 - F1 F2 E2 15 16 17 26 27 28 M2 M3 M4 32 33 34 35 36 37 M2 M3 M4 L12 L13 NC 32 33 34 35 36 37 M2 M3 M4 PC0 PC1 PC2 I/O I/O I/O FT FT FT F3 18 29 M5 35 38 L4 NC 35 38 L4 PC3 I/O FT - DFSDM1_DATIN1, SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT - - 30 - 36 39 J5 - 36 39 J5 VDD S - - - Additional functions - - - - - - J6 - - - J6 VSS S - - - - G1 19 31 M1 37 40 M1 M11 37 40 M1 VSSA S - - - - - - - N1 - - N1 - - - N1 VREF- S - - - - - 20 32 P1 38 41 P1 - 38 41 P1 VREF+ S - - - - H1 21 33 R1 39 42 R1 M12 39 42 R1 VDDA S - - - - (4) TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI2_SD_B, ETH_MII_CRS, EVENTOUT ADC1_IN0, ADC2_IN0, ADC3_IN0, WKUP1 G2 22 34 N3 40 43 N3 M13 40 43 N3 PA0WKUP I/O DS11532 Rev 8 FT 69/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) J2 23 24 36 N2 P2 41 42 44 45 N2 P2 J11 J10 41 42 44 45 N2 P2 PA1 PA2 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 35 STM32F768Ax STM32F769xx FT FT Notes H2 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_ REF_CLK, LCD_R2, EVENTOUT ADC1_IN1, ADC2_IN1, ADC3_IN1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC1_IN2, ADC2_IN2, ADC3_IN2, WKUP2 - - - - F4 43 46 K4 L10 43 46 K4 PH2 I/O FT - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - - - G4 44 47 J4 K10 44 47 J4 PH3 I/O FT - QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT - - - - H4 45 48 H4 N12 45 48 H4 PH4 I/O FT - I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, EVENTOUT - - - - J4 46 49 J3 N11 46 49 J3 PH5 I/O FT - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - ADC1_IN3, ADC2_IN3, ADC3_IN3 PA3 I/O FT - TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT K6 VSS S - - - - I FT - - - S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC1_IN4, ADC2_IN4, DAC_OUT1 K2 25 37 R2 47 50 R2 M10 47 50 R2 J1 26 38 - - 51 K6 J9 - 51 E6 - - L4 48 - L5 -(5) 48 - L5 BYPASS_ REG K1 27 39 K4 49 52 K5 K9 49 52 K5 VDD G3 28 70/256 40 N4 50 53 N4 L9 50 53 N4 PA4 I/O DS11532 Rev 8 TTa STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) J3 29 30 42 P4 P3 51 52 54 55 P4 P3 P11 N10 51 52 54 55 P4 P3 PA5 PA6 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 41 STM32F768Ax STM32F769xx TTa FT Notes H3 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, OTG_HS_ULPI_CK, LCD_R4, EVENTOUT ADC1_IN5, ADC2_IN5, DAC_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, SPI6_MISO, TIM13_CH1, MDIOS_MDC, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC1_IN6, ADC2_IN6 ADC1_IN7, ADC2_IN7 K3 31 43 R3 53 56 R3 M9 53 56 R3 PA7 I/O FT - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, SPI6_MOSI, TIM14_CH1, ETH_MII_RX_DV/ETH_RMII_C RS_DV, FMC_SDNWE, EVENTOUT G4 32 44 N5 54 57 N5 NC 54 57 N5 PC4 I/O FT - DFSDM1_CKIN2, I2S1_MCK, SPDIF_RX2, ETH_MII_RXD0/ETH_RMII_RX D0, FMC_SDNE0, EVENTOUT ADC1_IN14, ADC2_IN14 ADC1_IN15, ADC2_IN15 H4 33 45 P5 55 58 P5 NC 55 58 P5 PC5 I/O FT - DFSDM1_DATIN2, SPDIF_RX3, ETH_MII_RXD1/ETH_RMII_RX D1, FMC_SDCKE0, EVENTOUT - - - - - 59 L7 - - 59 L7 VDD S - - - - - - - - - 60 L6 - - 60 L6 VSS S - - - - - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM1_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC1_IN8, ADC2_IN8 - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC1_IN9, ADC2_IN9 J4 K4 34 35 46 47 R5 R4 56 57 61 62 R5 R4 P10 J8 56 57 61 62 R5 R4 PB0 PB1 I/O I/O DS11532 Rev 8 FT FT 71/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx G5 36 48 M6 58 63 M5 J7 58 63 M5 PB2 I/O FT - SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, DFSDM1_CKIN1, EVENTOUT - - - - - - 64 G4 NC - 64 G4 PI15 I/O FT - LCD_G2, LCD_R0, EVENTOUT - - - - - - 65 R6 NC - 65 R6 PJ0 I/O FT - LCD_R7, LCD_R1, EVENTOUT - - - - - - 66 R7 NC - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT - - - - - - 67 P7 NC - 67 P7 PJ2 I/O FT - DSI_TE, LCD_R3, EVENTOUT - - - - - - 68 N8 NC - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT - - - - - - 69 M9 NC - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT - - - 49 R6 59 70 P8 N9 59 70 P8 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT - - - 50 P6 60 71 M6 K7 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT - - - 51 M8 61 72 K7 P9 61 72 K7 VSS S - - - - - - 52 N8 62 73 L8 M8 62 73 L8 VDD S - - - - - - 53 N6 63 74 N6 L8 63 74 N6 PF13 I/O FT - I2C4_SMBA, DFSDM1_DATIN6, FMC_A7, EVENTOUT - - - 54 R7 64 75 P6 K8 64 75 P6 PF14 I/O FT - I2C4_SCL, DFSDM1_CKIN6, FMC_A8, EVENTOUT - - - 55 P7 65 76 M8 P8 65 76 M8 PF15 I/O FT - I2C4_SDA, FMC_A9, EVENTOUT - - - 56 N7 66 77 N7 N8 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT - - - 57 M7 67 78 M7 L7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT - - - H5 37 58 R8 68 79 R8 M7 68 79 R8 PE7 I/O FT - TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT J5 38 59 P8 69 80 N9 N7 69 80 N9 PE8 I/O FT - TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT 72/256 DS11532 Rev 8 Additional functions STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx K5 39 60 P9 70 81 P9 P7 70 81 P9 PE9 I/O FT - TIM1_CH1, DFSDM1_CKOUT, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - - - 61 M9 71 82 K8 - 71 82 K8 VSS S - - - - - - 62 N9 72 83 L9 - 72 83 L9 VDD S - - - - - Additional functions G6 40 63 R9 73 84 R9 J6 73 84 R9 PE10 I/O FT - TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT H6 41 64 P10 74 85 P10 K6 74 85 P10 PE11 I/O FT - TIM1_CH2, SPI4_NSS, DFSDM1_CKIN4, SAI2_SD_B, FMC_D8, LCD_G3, EVENTOUT - J6 42 65 R10 75 86 R10 L6 75 86 R10 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, DFSDM1_DATIN5, SAI2_SCK_B, FMC_D9, LCD_B4, EVENTOUT - K6 43 66 N11 76 87 R12 P6 76 87 R12 PE13 I/O FT - TIM1_CH3, SPI4_MISO, DFSDM1_CKIN5, SAI2_FS_B, FMC_D10, LCD_DE, EVENTOUT - G7 44 67 P11 77 88 P11 N6 77 88 P11 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11, LCD_CLK, EVENTOUT - H7 45 68 R11 78 89 R11 M6 78 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12, LCD_R7, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - J7 46 69 R12 79 90 P12 K5 79 90 P12 PB10 I/O DS11532 Rev 8 FT 73/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) 91 R13 PB11 I/O FT - F8 48 71 M10 81 92 L11 P5 81 92 L11 VCAP_1 S - - - - - 49 - - - 93 K9 N5 - 93 K9 VSS S - - - - - 50 72 N10 82 94 L10 P4 82 94 L10 VDD S - - - - - - - - - 95 M14 NC - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT - - - - M11 83 96 P13 NC 83 96 P13 PH6 I/O FT - I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT - - - - N12 84 97 N13 NC 84 97 N13 PH7 I/O FT - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT - - - - M12 85 98 P14 M5 - 98 P14 PH8 I/O FT - I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT - - - - M13 86 99 N14 K4 - 99 N14 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT - - - - L13 87 100 P15 L4 - 100 P15 PH10 I/O FT - TIM5_CH1, I2C4_SMBA, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT - - - - L12 88 101 N15 M4 - 101 N15 PH11 I/O FT - TIM5_CH2, I2C4_SCL, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT - - - - K12 89 102 M15 P3 - 102 M15 PH12 I/O FT - TIM5_CH3, I2C4_SDA, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT - - - - H12 90 - K10 N4 - - K10 VSS S - - - - - - - J12 91 103 K11 - - 103 K11 VDD S - - - - 74/256 TFBGA216 80 LQFP208 L5 LQFP176 R13 WLCSP180(1) 91 TFBGA216 80 LQFP208 R13 LQFP176 70 UFBGA176 47 LQFP144 K7 TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_T X_EN, DSI_TE, LCD_G5, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure STM32F768Ax STM32F769xx Pin type STM32F765xx STM32F767xx Pin name (function after reset Pin Number DS11532 Rev 8 Additional functions - STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) J8 H10 51 52 53 74 75 P12 P13 R14 92 93 94 104 105 106 L13 K14 R14 H8 J5 N3 85 86 87 104 105 106 L13 K14 R14 PB12 PB13 PB14 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 73 STM32F768Ax STM32F769xx FT FT FT Notes K8 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, UART5_RX, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TX D0, OTG_HS_ID, EVENTOUT - - TIM1_CH1N, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS, UART5_TX, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TX D1, EVENTOUT OTG_HS_VB US - TIM1_CH2N, TIM8_CH2N, USART1_TX, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS, UART4_RTS, TIM12_CH1, SDMMC2_D0, OTG_HS_DM, EVENTOUT - - G10 54 76 R15 95 107 R15 N2 88 107 R15 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, UART4_CTS, TIM12_CH2, SDMMC2_D1, OTG_HS_DP, EVENTOUT K9 55 77 P15 96 108 L15 M3 89 108 L15 PD8 I/O FT - DFSDM1_CKIN3, USART3_TX, SPDIF_RX1, FMC_D13, EVENTOUT - J9 56 78 P14 97 109 L14 L3 90 109 L14 PD9 I/O FT - DFSDM1_DATIN3, USART3_RX, FMC_D14, EVENTOUT - H9 57 79 N15 98 110 K15 M2 91 110 K15 PD10 I/O FT - DFSDM1_CKOUT, USART3_CK, FMC_D15, LCD_B3, EVENTOUT - - I2C4_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - G9 58 80 N14 99 111 N10 K3 92 111 N10 PD11 I/O DS11532 Rev 8 FT 75/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) 59 N13 100 112 M10 J4 93 112 M10 PD12 I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 81 STM32F768Ax STM32F769xx FT Notes K10 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM4_CH1, LPTIM1_IN1, I2C4_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT - - J10 60 82 M15 101 113 M11 L2 94 113 M11 PD13 I/O FT - TIM4_CH2, LPTIM1_OUT, I2C4_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - - 83 - 102 114 J10 M1 95 114 J10 VSS S - - - - - - 84 J13 103 115 J11 - 96 115 J11 VDD S - - - - H8 61 85 M14 104 116 L12 L1 97 116 L12 PD14 I/O FT - TIM4_CH3, UART8_CTS, FMC_D0, EVENTOUT - G8 62 86 L14 105 117 K13 K2 98 117 K13 PD15 I/O FT - TIM4_CH4, UART8_RTS, FMC_D1, EVENTOUT - - - - - - 118 K12 - - - - PJ6 I/O FT - LCD_R7, EVENTOUT - - - - - - 119 J12 - - - - PJ7 I/O FT - LCD_G0, EVENTOUT - - - - - - 120 H12 - - - - PJ8 I/O FT - LCD_G1, EVENTOUT - - - - - - 121 J13 - - - - PJ9 I/O FT - LCD_G2, EVENTOUT - - - - - - 122 H13 - - - - PJ10 I/O FT - LCD_G3, EVENTOUT - - - - - - 123 G12 - - - - PJ11 I/O FT - LCD_G4, EVENTOUT - - - - - - 124 H11 - - - - VDD S - - - - - - - - - - - K1 99 118 H11 VDDDSI S - - - - - - - - - 125 H10 - - - H10 VSS S - - - - - - - - - - - H6 100 119 K12 VCAPDSI S - - - - - - - - - - - J3 - - G13 VDD12DSI S - - - - - - - - - - - J1 101 120 J12 DSI_D0P I/O - - - - - - - - - - - J2 102 121 J13 DSI_D0N I/O - - - - - - - - - - - H5 103 122 G12 VSSDSI S - - - - - - - - - - - H4 104 123 H12 DSI_CKP I/O - - - - 76/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes - - - - - - - H3 105 124 H13 DSI_CKN I/O - - - - - - - - - - - - 106 125 - VDD12DSI S - - - - - - - - - - - H1 107 126 F12 DSI_D1P I/O - - - - - - - - - - - H2 108 127 F13 DSI_D1N I/O - - - - - - - - - - - - 109 128 - VSSDSI S - - - - - - - - - 126 G13 - - - - PK0 I/O FT - LCD_G5, EVENTOUT - - - - - - 127 F12 - - - - PK1 I/O FT - LCD_G6, EVENTOUT - - - - - - 128 F13 - - - - PK2 I/O FT - LCD_G7, EVENTOUT - - - 87 L15 106 129 M13 H9 110 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT - - - 88 K15 107 130 M12 G9 111 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT - - - 89 K14 108 131 N12 G1 112 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - 90 K13 109 132 N11 G2 113 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - 91 J15 110 133 J15 G3 114 133 J15 PG6 I/O FT - FMC_NE3, DCMI_D12, LCD_R7, EVENTOUT - - - 92 J14 111 134 J14 G4 115 134 J14 PG7 I/O FT - SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, EVENTOUT - - - 93 H14 112 135 H14 G5 116 135 H14 PG8 I/O FT - SPI6_NSS, SPDIF_RX2, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT - - - 94 G12 113 136 G10 F1 117 136 G10 VSS S - - - - F6 - 95 H13 114 137 G11 F2 118 137 G11 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, DFSDM1_CKIN3, USART6_TX, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT - F10 63 96 H15 115 138 H15 G6 LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx 119 138 H15 PC6 I/O DS11532 Rev 8 FT Additional functions 77/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) F9 E9 64 65 66 98 99 G15 G14 F14 116 117 118 139 140 141 G15 G14 F14 F3 G8 E1 120 139 121 140 122 141 G15 G14 F14 PC7 PC8 PC9 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 97 STM32F768Ax STM32F769xx FT FT FT Notes E10 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - TIM3_CH2, TIM8_CH2, I2S3_MCK, DFSDM1_DATIN3, USART6_RX, FMC_NE1, SDMMC2_D7, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, FMC_NE2/FMC_NCE, SDMMC1_D0, DCMI_D2, EVENTOUT - - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, LCD_G3, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT -- - D9 67 100 F15 119 142 F15 E2 123 142 F15 PA8 I/O FT - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, CAN3_RX, UART7_RX, LCD_B3, LCD_R6, EVENTOUT C9 68 101 E15 120 143 E15 F4 124 143 E15 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, DCMI_D0, LCD_R5, EVENTOUT OTG_FS_VB US D10 69 102 D15 121 144 D15 F5 125 144 D15 PA10 I/O FT - TIM1_CH3, USART1_RX, LCD_B4, OTG_FS_ID, MDIOS_MDIO, DCMI_D1, LCD_B1, EVENTOUT - - TIM1_CH4, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS, CAN1_RX, OTG_FS_DM, LCD_R4, EVENTOUT - - TIM1_ETR, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, LCD_R5, EVENTOUT - C10 B10 70 71 78/256 103 C15 104 B15 122 123 145 146 C15 B15 E3 D1 126 145 127 146 C15 B15 PA11 PA12 I/O I/O DS11532 Rev 8 FT FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes A10 72 105 A15 124 147 A15 D2 128 147 A15 PA13(JTM S-SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - E7 73 106 F13 125 148 E11 C1 129 148 E11 VCAP_2 S - - - - E5 74 107 F12 126 149 F10 C2 130 149 F10 VSS S - - - - F5 75 108 G13 127 150 F11 B2 131 150 F11 VDD S - - - - LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx Additional functions - - - E12 128 151 E12 F6 - 151 E12 PH13 I/O FT - TIM8_CH1N, UART4_TX, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT - - - E13 129 152 E13 F7 - 152 E13 PH14 I/O FT - TIM8_CH2N, UART4_RX, CAN1_RX, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT - - - - D13 130 153 D13 E5 - 153 D13 PH15 I/O FT - TIM8_CH3N, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT - - - - E14 131 154 E14 E4 132 154 E14 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT - - - - D14 132 155 D14 B3 133 155 D14 PI1 I/O FT - TIM8_BKIN2, SPI2_SCK/I2S2_CK, FMC_D25, DCMI_D8, LCD_G6, EVENTOUT - - - - C14 133 156 C14 C3 156 C14 PI2 I/O FT - TIM8_CH4, SPI2_MISO, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT - - - - C13 134 157 C13 D3 134 157 C13 PI3 I/O FT - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10, EVENTOUT - - - - D9 135 - F9 - 135 F9 VSS S - - - - - - - C9 136 158 E10 - 136 158 E10 VDD S - - - -- A9 76 109 A14 137 159 A14 A3 137 159 A14 PA14(JTC K-SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - - - DS11532 Rev 8 79/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) B9 B8 77 78 79 111 112 A13 B14 B13 138 139 140 160 161 162 A13 B14 B13 F8 B4 C4 138 160 139 161 140 162 A13 B14 B13 PA15(JTDI ) PC10 PC11 I/O I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 110 STM32F768Ax STM32F769xx FT FT FT Notes A8 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS, CAN3_TX, UART7_TX, EVENTOUT - - DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT - - DFSDM1_DATIN5, SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4, EVENTOUT - - C8 80 113 A12 141 163 A12 D4 141 163 A12 PC12 I/O FT - TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9, EVENTOUT D8 81 114 B12 142 164 B12 A4 142 164 B12 PD0 I/O FT - DFSDM1_CKIN6, DFSDM1_DATIN7, UART4_RX, CAN1_RX, FMC_D2, EVENTOUT - E8 82 115 C12 143 165 C12 D5 143 165 C12 PD1 I/O FT - DFSDM1_DATIN6, DFSDM1_CKIN7, UART4_TX, CAN1_TX, FMC_D3, EVENTOUT -- B7 83 116 D12 144 166 D12 D6 144 166 D12 PD2 I/O FT - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT - - - C7 84 117 D11 145 167 C11 B5 145 167 C11 PD3 I/O FT - DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT D7 85 118 D10 146 168 D11 A5 146 168 D11 PD4 I/O FT - DFSDM1_CKIN0, USART2_RTS, FMC_NOE, EVENTOUT 80/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes B6 86 119 C11 147 169 C10 C5 147 169 C10 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - 120 D8 148 170 F8 B6 148 170 F8 VSS S - - - - - - 121 C8 149 171 E9 A6 149 171 E9 VDDSDM MC S - - - - - DFSDM1_CKIN4, SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, DFSDM1_DATIN1, SDMMC2_CK, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT - - C6 87 122 B11 150 172 B11 E6 LQFP176 LQFP144 UFBGA176 Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx 150 172 B11 PD6 I/O FT Additional functions A11 PD7 I/O FT - DFSDM1_DATIN4, SPI1_MOSI/I2S1_SD, DFSDM1_CKIN1, USART2_CK, SPDIF_RX0, SDMMC2_CMD, FMC_NE1, EVENTOUT 174 B10 PJ12 I/O FT - LCD_G3, LCD_B0, EVENTOUT - 175 B9 PJ13 I/O FT - LCD_G4, LCD_B1, EVENTOUT - PJ14 I/O FT - LCD_B2, EVENTOUT - PJ15 I/O FT - LCD_B3, EVENTOUT - - D6 88 123 A11 151 173 A11 E7 151 173 - - - - - 174 B10 NC - - - - - - 175 B9 NC - - - - - - 176 C9 NC - 176 C9 - - - - - 177 D10 - - 177 D10 - - 124 C10 152 178 D9 C6 152 178 D9 PG9 I/O FT - SPI1_MISO, SPDIF_RX3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC, EVENTOUT - - 125 153 179 C8 A7 153 179 C8 PG10 I/O FT - SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT - - SPI1_SCK/I2S1_CK, SPDIF_RX0, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_T X_EN, DCMI_D3, LCD_B3, EVENTOUT - - - 126 B10 B9 154 180 B8 B7 154 180 B8 PG11 I/O DS11532 Rev 8 FT 81/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) - - - 127 128 A8 155 156 B3 B3 PG13 FT - - TRACED0, LPTIM1_OUT, SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_RMII_TX D0, FMC_A24, LCD_R0, EVENTOUT - - TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_RMII_TX D1, FMC_A25, LCD_B0, EVENTOUT - D7 158 184 F7 A8 158 184 F7 VSS S - - - - C7 159 185 E8 B8 159 185 E8 VDD S - - - - - - - - - 186 D8 NC - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT - - - - - - 187 D7 NC - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT - - - - - - 188 C6 NC - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT - - - - - - 189 C5 NC - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT - - - - - - 190 C4 NC - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT - - - 132 B7 160 191 B7 F9 160 191 B7 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, CAN3_RX, UART7_RX, EVENTOUT - - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, CAN3_TX, UART7_TX, EVENTOUT - A6 90 82/256 134 A9 162 193 A9 D8 162 193 A10 A9 PB3 (JTDO/ I/O TRACESW O) PB4(NJTR ST) I/O DS11532 Rev 8 FT - 131 161 192 I/O I/O structure Pin type I/O FT 130 E8 PG14 I/O - A10 A4 PG12 - 192 157 183 TFBGA216 LQFP208 156 182 C7 - 161 NC LQFP176 WLCSP180(1) C7 155 181 - A10 A4 D7 LPTIM1_IN1, SPI6_MISO, SPDIF_RX1, USART6_RTS, LCD_B4, SDMMC2_D3, FMC_NE4, LCD_B1, EVENTOUT 129 133 183 TFBGA216 LQFP208 182 C7 Additional functions - 89 157 181 Alternate functions - A7 A7 LQFP176 UFBGA176 B8 STM32F768Ax STM32F769xx Notes - LQFP144 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number FT FT STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) B5 91 92 136 A6 B6 163 164 194 195 A8 B6 A9 B9 163 194 164 195 A8 B6 PB5 PB6 I/O I/O I/O structure Pin type TFBGA216 LQFP208 LQFP176 WLCSP180(1) TFBGA216 LQFP208 LQFP176 UFBGA176 LQFP144 135 STM32F768Ax STM32F769xx FT FT Notes C5 LQFP100 TFBGA100 STM32F765xx STM32F767xx Pin name (function after reset Pin Number Alternate functions Additional functions - UART5_RX, TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, SPI6_MOSI, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, LCD_G7, EVENTOUT - - UART5_TX, TIM4_CH1, HDMI_CEC, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, I2C4_SCL, FMC_SDNE1, DCMI_D5, EVENTOUT - TIM4_CH2, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, I2C4_SDA, FMC_NL, DCMI_VSYNC, EVENTOUT - A5 93 137 B5 165 196 B5 C8 165 196 B5 PB7 I/O FT - D5 94 138 D6 166 197 E6 A10 166 197 E6 BOOT0 I B - - VPP - I2C4_SCL, TIM4_CH3, TIM10_CH1, I2C1_SCL, DFSDM1_CKIN7, UART5_RX, CAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT - - B4 95 139 A5 167 198 A7 E9 167 198 A7 PB8 I/O FT A4 96 140 B4 168 199 B4 D9 168 199 B4 PB9 I/O FT - I2C4_SDA, TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN7, UART5_TX, CAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT D4 97 141 A4 169 200 A6 C9 169 200 A6 PE0 I/O FT - TIM4_ETR, LPTIM1_ETR, UART8_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT - C4 98 142 A3 170 201 A5 B10 170 201 A5 PE1 I/O FT - LPTIM1_IN2, UART8_TX, FMC_NBL1, DCMI_D3, EVENTOUT - DS11532 Rev 8 83/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number TFBGA216 Pin name (function after reset Pin type I/O structure Notes - - C10 171 203 E5 PDR_ON S - - - - E7 B11 172 204 E7 VDD S - - - - WLCSP180(1) - TFBGA216 - LQFP208 S LQFP176 VSS UFBGA176 F6 LQFP144 202 LQFP100 - TFBGA100 Alternate functions LQFP208 STM32F768Ax STM32F769xx LQFP176 STM32F765xx STM32F767xx E4 99 - D5 - 202 F6 A11 F7 - 143 C6 171 203 E5 100 144 C5 172 204 F4 Additional functions - - - D4 173 205 C3 D10 173 205 C3 PI4 I/O FT - TIM8_BKIN, SAI2_MCLK_A, FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - - - C4 174 206 D3 D11 174 206 D3 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT - - - - C3 175 207 D6 C11 175 207 D6 PI6 I/O FT - TIM8_CH2, SAI2_SD_A, FMC_D28, DCMI_D6, LCD_B6, EVENTOUT - - - - C2 176 208 D4 B12 176 208 D4 PI7 I/O FT - TIM8_CH3, SAI2_FS_A, FMC_D29, DCMI_D7, LCD_B7, EVENTOUT - - - - F6 - - - - - - - VSS S - - - - - - - F7 - - - - - - - VSS S - - - - - - - F8 - - - - - - - VSS S - - - - - - - F9 - - - - - - - VSS S - - - - - - - F10 - - - - - - - VSS S - - - - - - - G6 - - - - - - - VSS S - - - - - - - G7 - - - - - - - VSS S - - - - - - - G8 - - - - - - - VSS S - - - - - - - G9 - - - - - - - VSS S - - - - - - - G10 - - - - - - - VSS S - - - - - - - H6 - - - - - - - VSS S - - - - - - - H7 - - - - - - - VSS S - - - - - - - H8 - - - - - - - VSS S - - - - - - - H9 - - - - - - - VSS S - - - - - - - H10 - - - - - - - VSS S - - - - - - - J6 - - - - - - - VSS S - - - - 84/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx pin and ball definitions (continued) Pin Number LQFP144 UFBGA176 LQFP176 LQFP208 TFBGA216 WLCSP180(1) LQFP176 LQFP208 TFBGA216 Pin name (function after reset Pin type I/O structure Notes Alternate functions LQFP100 STM32F768Ax STM32F769xx TFBGA100 STM32F765xx STM32F767xx - - - J7 - - - - - - - VSS S - - - - - - - J8 - - - - - - - VSS S - - - - - - - J9 - - - - - - - VSS S - - - - - - - J10 - - - - - - - VSS S - - - - - - - K6 - - - - - - - VSS S - - - - - - - K7 - - - - - - - VSS S - - - - - - - K8 - - - - - - - VSS S - - - - - - - K9 - - - - - - - VSS S - - - - - - - K10 - - - - - - - VSS S - - - - Additional functions 1. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid an extra current consumption in low-power modes. list of pins: PI8, PI12, PI13, PI14, PF6, PF7, PF8, PF9, PC2, PC3, PC4, PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14, PK3, PK4, PK5, PK6 and PK7. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 4. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). 5. Internally connected to VDD or VSS depending on part number. DS11532 Rev 8 85/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 12. FMC pin definition 86/256 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF0 A0 - - A0 PF1 A1 - - A1 PF2 A2 - - A2 PF3 A3 - - A3 PF4 A4 - - A4 PF5 A5 - - A5 PF12 A6 - - A6 PF13 A7 - - A7 PF14 A8 - - A8 PF15 A9 - - A9 PG0 A10 - - A10 PG1 A11 - - A11 PG2 A12 - - A12 PG3 A13 - - - PG4 A14 - - BA0 PG5 A15 - - BA1 PD11 A16 A16 CLE - PD12 A17 A17 ALE - PD13 A18 A18 - - PE3 A19 A19 - - PE4 A20 A20 - - PE5 A21 A21 - - PE6 A22 A22 - - PE2 A23 A23 - - PG13 A24 A24 - - PG14 A25 A25 - - PD14 D0 DA0 D0 D0 PD15 D1 DA1 D1 D1 PD0 D2 DA2 D2 D2 PD1 D3 DA3 D3 D3 PE7 D4 DA4 D4 D4 PE8 D5 DA5 D5 D5 PE9 D6 DA6 D6 D6 PE10 D7 DA7 D7 D7 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 12. FMC pin definition (continued) Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PE11 D8 DA8 D8 D8 PE12 D9 DA9 D9 D9 PE13 D10 DA10 D10 D10 PE14 D11 DA11 D11 D11 PE15 D12 DA12 D12 D12 PD8 D13 DA13 D13 D13 PD9 D14 DA14 D14 D14 PD10 D15 DA15 D15 D15 PH8 D16 - - D16 PH9 D17 - - D17 PH10 D18 - - D18 PH11 D19 - - D19 PH12 D20 - - D20 PH13 D21 - - D21 PH14 D22 - - D22 PH15 D23 - - D23 PI0 D24 - - D24 PI1 D25 - - D25 PI2 D26 - - D26 PI3 D27 - - D27 PI6 D28 - - D28 PI7 D29 - - D29 PI9 D30 - - D30 PI10 D31 - - D31 PD7 NE1 NE1 - - PG6 NE3 - - - PG9 NE2 NE2 NCE - PG10 NE3 NE3 - - PG11 - - - - PG12 NE4 NE4 - - PD3 CLK CLK - - PD4 NOE NOE NOE - PD5 NWE NWE NWE - PD6 NWAIT NWAIT NWAIT - DS11532 Rev 8 87/256 102 Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 12. FMC pin definition (continued) 88/256 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PB7 NADV NADV - - PF6 - - - - PF7 - - - - PF8 - - - - PF9 - - - - PF10 - - - - PG6 - - - - PG7 - - INT - PE0 NBL0 NBL0 - NBL0 PE1 NBL1 NBL1 - NBL1 PI4 NBL2 - - NBL2 PI5 NBL3 - - NBL3 PG8 - - - SDCLK PC0 - - - SDNWE PF11 - - - SDNRAS PG15 - - - SDNCAS PH2 - - - SDCKE0 PH3 - - - SDNE0 PH6 - - - SDNE1 PH7 - - - SDCKE1 PH5 - - - SDNWE PC2 - - - SDNE0 PC3 - - - SDCKE0 PC6 NWAIT NWAIT NWAIT - PB5 - - - SDCKE1 PB6 - - - SDNE1 DS11532 Rev 8 AF0 AF1 AF2 AF3 AF4 SYS I2C4/UA RT5/TIM 1/2 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC - TIM2_C H1/TIM2 _ETR TIM5_C H1 PA1 - TIM2_C H2 TIM5_C H2 - - PA2 - TIM2_C H3 TIM5_C H3 TIM9_CH 1 PA3 - TIM2_C H4 TIM5_C H4 PA4 - - PA5 - PA6 Port AF6 AF7 AF8 AF9 AF10 UART4_ TX - - - USART2 _RTS UART4_ RX QUADSP I_BK1_IO 3 - - - USART2 _TX SAI2_SC K_B - TIM9_CH 2 - - - USART2 _RX - LCD_B2 - - - SPI1_NS SPI3_NS S/I2S1_ S/I2S3_ WS WS USART2 _CK SPI6_NS S - - TIM2_C H1/TIM2 _ETR - TIM8_CH 1N - SPI1_SC K/I2S1_ CK - - SPI6_SC K - - TIM1_B KIN TIM3_C H1 TIM8_BKI N - SPI1_MI SO - - SPI6_MI SO PA7 - TIM1_C H1N TIM3_C H2 TIM8_CH 1N - SPI1_M OSI/I2S1 _SD - - PA8 MCO1 TIM1_C H1 - TIM8_BKI N2 I2C3_SC L - - PA9 - TIM1_C H2 - - I2C3_SM BA SPI2_SC K/I2S2_ CK PA10 - TIM1_C H3 - - - - DS11532 Rev 8 Port A AF12 - AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS 89/256 SAI2_SD_ ETH_MII_ B CRS - - - EVEN TOUT SAI2_MC K_B ETH_MII_ RX_CLK/ ETH_RMI I_REF_C LK - - LCD_R2 EVEN TOUT - ETH_MDI O MDIOS_ MDIO - LCD_R1 EVEN TOUT - - LCD_B5 EVEN TOUT - OTG_HS _SOF DCMI_H SYNC LCD_VS YNC EVEN TOUT OTG_HS_ ULPI_CK - - - LCD_R4 EVEN TOUT TIM13_C H1 - - MDIOS_ MDC DCMI_PI XCLK LCD_G2 EVEN TOUT SPI6_MO SI TIM14_C H1 - - - EVEN TOUT USART1 _CK - - OTG_FS_ SOF CAN3_R X UART7_ RX LCD_B3 LCD_R6 EVEN TOUT - USART1 _TX - - - - - DCMI_D 0 LCD_R5 EVEN TOUT - USART1 _RX - LCD_B4 OTG_FS_ ID - MDIOS_ MDIO DCMI_D 1 LCD_B1 EVEN TOUT OTG_HS_ ETH_MII_ ULPI_D0 COL ETH_MII_ RX_DV/E FMC_SD TH_RMII_ NWE CRS_DV Pinouts and pin description USART2 _CTS - AF11 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD - PA0 TIM8_ET R I2C1/2/3/ 4/USART 1/CEC AF5 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping AF0 Port Port A AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PA11 - TIM1_C H4 - - - SPI2_NS S/I2S2_ WS UART4_ RX USART1 _CTS - CAN1_R X OTG_FS_ DM - - - LCD_R4 EVEN TOUT PA12 - TIM1_ET R - - - SPI2_SC K/I2S2_ CK UART4_ TX USART1 _RTS SAI2_FS _B CAN1_T X OTG_FS_ DP - - - LCD_R5 EVEN TOUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCLK - - - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_C H1/TIM2 _ETR - - HDMICEC SPI6_NS S UART4_ RTS - - CAN3_TX UART7_ TX - - EVEN TOUT PB0 - TIM1_C H2N TIM3_C H3 TIM8_CH 2N - - DFSDM1 _CKOUT - UART4_ CTS LCD_R3 OTG_HS_ ETH_MII_ ULPI_D1 RXD2 - - LCD_G1 EVEN TOUT PB1 - TIM1_C H3N TIM3_C H4 TIM8_CH 3N - - DFSDM1 _DATIN1 - - LCD_R6 OTG_HS_ ETH_MII_ ULPI_D2 RXD3 - - LCD_G0 EVEN TOUT PB2 - - - - - - SAI1_SD _A SPI3_MO SI/I2S3_ SD - QUADSP I_CLK DFSDM1_ CKIN1 - - - - EVEN TOUT PB3 JTDO/T RACES WO TIM2_C H2 - - - SPI1_SC SPI3_SC K/I2S1_ K/I2S3_ CK CK - SPI6_SC K - SDMMC2 _D2 CAN3_R X UART7_ RX - - EVEN TOUT PB4 NJTRST - TIM3_C H1 - - SPI1_MI SO SPI2_NS S/I2S2_ WS SPI6_MI SO - SDMMC2 _D3 CAN3_TX UART7_ TX - - EVEN TOUT PB5 - UART5_ RX TIM3_C H2 - I2C1_SM BA - SPI6_MO SI CAN2_R X OTG_HS_ ETH_PPS FMC_SD ULPI_D7 _OUT CKE1 DCMI_D 10 LCD_G7 EVEN TOUT PB6 - UART5_ TX TIM4_C H1 HDMICEC I2C1_SC L USART1 _TX - CAN2_T X QUADSPI _BK1_NC S DCMI_D 5 - EVEN TOUT Port B I2C1/2/3/ 4/USART 1/CEC SPI1_NS SPI3_NS S/I2S1_ S/I2S3_ WS WS SPI3_MI SO SPI1_M SPI3_M OSI/I2S1 OSI/I2S3 _SD _SD - DFSDM1 _DATIN5 I2C4_SC L FMC_SD NE1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 SYS Pinouts and pin description 90/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 AF4 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC I2C1/2/3/ 4/USART 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS DS11532 Rev 8 I2C4/UA RT5/TIM 1/2 PB7 - - TIM4_C H2 - I2C1_SD A - DFSDM1 _CKIN5 USART1 _RX - - - I2S4_SD A FMC_NL DCMI_V SYNC - EVEN TOUT PB8 - I2C4_SC L TIM4_C H3 TIM10_C H1 I2C1_SC L - DFSDM1 _CKIN7 UART5_ RX - CAN1_R X SDMMC2 _D4 ETH_MII_ TXD3 SDMMC _D4 DCMI_D 6 LCD_B6 EVEN TOUT PB9 - I2C4_SD A TIM4_C H4 TIM11_CH 1 I2C1_SD A SPI2_NS DFSDM1 UART5_T S/I2S2_ _DATIN7 X WS - CAN1_T X SDMMC2 _D5 I2C4_SM BA SDMMC _D5 DCMI_D 7 LCD_B7 EVEN TOUT PB10 - TIM2_C H3 - - I2C2_SC L SPI2_SC DFSDM1 K/I2S2_ _DATIN7 CK USART3 _TX - QUADSP I_BK1_N CS OTG_HS_ ETH_MII_ ULPI_D3 RX_ER - - LCD_G4 EVEN TOUT PB11 - TIM2_C H4 - - I2C2_SD A DFSDM1 _CKIN7 USART3 _RX - - ETH_MII_ OTG_HS_ TX_EN/E ULPI_D4 TH_RMII_ TX_EN - DSI_TE LCD_G5 EVEN TOUT PB12 - TIM1_B KIN - - I2C2_SM BA SPI2_NS DFSDM1 S/I2S2_ _DATIN1 WS USART3 _CK UART5_ RX CAN2_R X ETH_MII_ OTG_HS_ TXD0/ET OTG_HS ULPI_D5 H_RMII_T _ID XD0 - - EVEN TOUT PB13 - TIM1_C H1N - - - SPI2_SC DFSDM1 K/I2S2_ _CKIN1 CK USART3 _CTS UART5_T X CAN2_T X ETH_MII_ OTG_HS_ TXD1/ET ULPI_D6 H_RMII_T XD1 - - - EVEN TOUT PB14 - TIM1_C H2N - TIM8_CH 2N USART1_ TX SPI2_MI SO USART3 _RTS UART4_ RTS TIM12_C H1 SDMMC2 _D0 - OTG_HS _DM - - EVEN TOUT PB15 RTC_RE FIN TIM1_C H3N - TIM8_CH 3N SPI2_M USART1_ DFSDM1 OSI/I2S2 RX _CKIN2 _SD - UART4_ CTS TIM12_C H2 SDMMC2 _D1 - OTG_HS _DP - - EVEN TOUT Port B - DFSDM1 _DATIN2 91/256 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 SYS I2C4/UA RT5/TIM 1/2 PC0 - - - DFSDM1_ CKIN0 - PC1 TRACED 0 - - DFSDM1_ DATAIN0 PC2 - - - PC3 - - PC4 - PC5 I2C1/2/3/ 4/USART 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS DFSDM1 _DATIN4 - SAI2_FS _B - OTG_HS_ ULPI_ST P - FMC_SD NWE - LCD_R5 EVEN TOUT - SPI2_M SAI1_SD OSI/I2S2 _A _SD - - - DFSDM1_ CKIN4 ETH_MD C MDIOS_ MDC - - EVEN TOUT DFSDM1_ CKIN1 - SPI2_MI SO DFSDM1 _CKOUT - - - OTG_HS_ ETH_MII_ FMC_SD ULPI_DIR TXD2 NE0 - - EVEN TOUT - DFSDM1_ DATAIN1 - SPI2_M OSI/I2S2 _SD - - - - OTG_HS_ ETH_MII_ FMC_SD ULPI_NX TX_CLK CKE0 T - - EVEN TOUT - - DFSDM1_ CKIN2 - I2S1_M CK - - SPDIF_R X2 - - ETH_MII_ RXD0/ET FMC_SD H_RMII_ NE0 RXD0 - - EVEN TOUT - - - DFSDM1_ DATAIN2 - - - - SPDIF_R X3 - - ETH_MII_ RXD1/ET FMC_SD H_RMII_ CKE0 RXD1 - - EVEN TOUT PC6 - - TIM3_C H1 TIM8_CH 1 - I2S2_M CK - DFSDM1 _CKIN3 USART6 _TX FMC_NW AIT SDMMC2 _D6 - SDMMC _D6 DCMI_D 0 LCD_HS YNC EVEN TOUT PC7 - - TIM3_C H2 TIM8_ CH2 - - I2S3_M CK DFSDM1 _DATAIN 3 USART6 _RX FMC_NE 1 SDMMC2 _D7 - SDMMC _D7 DCMI_D 1 LCD_G6 EVEN TOUT PC8 TRACED 1 - TIM3_C H3 TIM8_ CH3 - - - UART5_ RTS USART6 _CK FMC_NE 2/FMC_N CE - - SDMMC _D0 DCMI_D 2 - EVEN TOUT PC9 MCO2 - TIM3_C H4 TIM8_ CH4 I2C3_SD A I2S_CKI N - UART5_ CTS - QUADSP I_BK1_IO 0 LCD_G3 - SDMMC _D1 DCMI_D 3 LCD_B2 EVEN TOUT PC10 - - - DFSDM1_ CKIN5 - - SPI3_SC K/I2S3_ CK USART3 _TX - - SDMMC _D2 DCMI_D 8 LCD_R2 EVEN TOUT - QUADSP UART4_T I_BK1_IO X 1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 Port C AF1 Pinouts and pin description 92/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PC11 - - - DFSDM1_ DATAIN5 - - SPI3_MI SO USART3 _RX UART4_ RX QUADSP I_BK2_N CS - - SDMMC _D3 DCMI_D 4 - EVEN TOUT PC12 TRACED 3 - - - - - SPI3_M OSI/I2S3 _SD USART3 _CK UART5_T X - - - SDMMC _CK DCMI_D 9 - EVEN TOUT PC13 - - - - - - - - - - - - - - - EVEN TOUT PC14 - - - - - - - - - - - - - - - EVEN TOUT PC15 - - - - - - - - - - - - - - - EVEN TOUT PD0 - - - DFSDM1_ CKIN6 - - DFSDM1 _DATAIN 7 - UART4_ RX CAN1_R X - - FMC_D2 - - EVEN TOUT PD1 - - - DFSDM1_ DATAIN6 - - DFSDM1 _CKIN7 - UART4_T X CAN1_T X - - FMC_D3 - - EVEN TOUT PD2 TRACED 2 - TIM3_ET R - - - - - UART5_ RX - - - SDMMC _CMD DCMI_D 11 - EVEN TOUT PD3 - - - DFSDM1_ CKOUT - SPI2_SC DFSDM1 K/I2S2_ _DATAIN CK 0 USART2 _CTS - - - - FMC_CL K DCMI_D 5 LCD_G7 EVEN TOUT PD4 - - - - - - DFSDM1 _CKIN0 USART2 _RTS - - - - FMC_N OE - - EVEN TOUT PD5 - - - - - - - USART2 _TX - - - - FMC_N WE - - EVEN TOUT PD6 - - - DFSDM1_ CKIN4 - SPI3_M SAI1_SD OSI/I2S3 _A _SD USART2 _RX - - DFSDM1_ DATAIN1 SDMMC2 _CK FMC_N WAIT DCMI_D 10 LCD_B2 EVEN TOUT PD7 - - - DFSDM1_ DATAIN4 - SPI1_M DFSDM1 OSI/I2S1 _CKIN1 _SD USART2 _CK SPDIF_R X0 - - SDMMC2 _CMD FMC_NE 1 - - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port C DS11532 Rev 8 Port D 93/256 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PD8 - - - DFSDM1_ CKIN3 - - - USART3 _TX SPDIF_R X1 - - - FMC_D1 3 - - EVEN TOUT PD9 - - - DFSDM1_ DATAIN3 - - - USART3 _RX - - - - FMC_D1 4 - - EVEN TOUT PD10 - - - DFSDM1_ CKOUT - - - USART3 _CK - - - - FMC_D1 5 - LCD_B3 EVEN TOUT PD11 - - - - I2C4_SM BA - - USART3 _CTS - QUADSP SAI2_SD_ I_BK1_IO A 0 - FMC_A1 6/FMC_ CLE - - EVEN TOUT PD12 - - TIM4_C H1 LPTIM1_I N1 I2C4_SC L - - USART3 _RTS - QUADSP SAI2_FS_ I_BK1_IO A 1 - FMC_A1 7/FMC_ ALE - - EVEN TOUT PD13 - - TIM4_C H2 LPTIM1_ OUT I2C4_SD A - - - - QUADSP I_BK1_IO 3 SAI2_SC K_A - FMC_A1 8 - - EVEN TOUT PD14 - - TIM4_C H3 - - - - - UART8_ CTS - - - FMC_D0 - - EVEN TOUT PD15 - - TIM4_C H4 - - - - - UART8_ RTS - - - FMC_D1 - - EVEN TOUT PE0 - - TIM4_ET LPTIM1_E R TR - - - - UART8_ Rx - SAI2_MC K_A - FMC_NB L0 DCMI_D 2 - EVEN TOUT PE1 - - - LPTIM1_I N2 - - - - UART8_T x - - - FMC_NB L1 DCMI_D 3 - EVEN TOUT PE2 TRACEC LK - - - - SPI4_SC K SAI1_M CLK_A - - QUADSP I_BK1_IO 2 - ETH_MII_ TXD3 FMC_A2 3 - - EVEN TOUT PE3 TRACED 0 - - - - - SAI1_SD _B - - - - - FMC_A1 9 - - EVEN TOUT Port D Port E I2C1/2/3/ 4/USART 1/CEC STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 SYS Pinouts and pin description 94/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD DCMI/L CD/DSI LCD SYS DS11532 Rev 8 I2C4/UA RT5/TIM 1/2 PE4 TRACED 1 - - - - SPI4_NS SAI1_FS S _A - - - DFSDM1_ DATAIN3 - FMC_A2 0 DCMI_D 4 LCD_B0 EVEN TOUT PE5 TRACED 2 - - TIM9_CH 1 - SPI4_MI SO SAI1_SC K_A - - - DFSDM1_ CKIN3 - FMC_A2 1 DCMI_D 6 LCD_G0 EVEN TOUT PE6 TRACED 3 TIM1_B KIN2 - TIM9_CH 2 - SPI4_M OSI SAI1_SD _A - - - SAI2_MC K_B - FMC_A2 2 DCMI_D 7 LCD_G1 EVEN TOUT PE7 - TIM1_ET R - - - - DFSDM1 _DATAIN 2 - UART7_ Rx - QUADSPI _BK2_IO0 - FMC_D4 - - EVEN TOUT PE8 - TIM1_C H1N - - - - DFSDM1 _CKIN2 - UART7_T x - QUADSPI _BK2_IO1 - FMC_D5 - - EVEN TOUT PE9 - TIM1_C H1 - - - - DFSDM1 _CKOUT - UART7_ RTS - QUADSPI _BK2_IO2 - FMC_D6 - - EVEN TOUT PE10 - TIM1_C H2N - - - - DFSDM1 _DATAIN 4 - UART7_ CTS - QUADSPI _BK2_IO3 - FMC_D7 - - EVEN TOUT PE11 - TIM1_C H2 - - - SPI4_NS DFSDM1 S _CKIN4 - - - SAI2_SD_ B - FMC_D8 - LCD_G3 EVEN TOUT PE12 - TIM1_C H3N - - - DFSDM1 SPI4_SC _DATAIN K 5 - - - SAI2_SC K_B - FMC_D9 - LCD_B4 EVEN TOUT PE13 - TIM1_C H3 - - - SPI4_MI SO DFSDM1 _CKIN5 - - - SAI2_FS_ B - FMC_D1 0 - LCD_DE EVEN TOUT PE14 - TIM1_C H4 - - - SPI4_M OSI - - - - SAI2_MC K_B - FMC_D1 1 - LCD_CL K EVEN TOUT PE15 - TIM1_B KIN - - - - - - - - - - FMC_D1 2 - LCD_R7 EVEN TOUT Port E I2C1/2/3/ 4/USART 1/CEC 95/256 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS SYS I2C4/UA RT5/TIM 1/2 PF0 - - - - I2C2_SD A - - - - - - - FMC_A0 - - EVEN TOUT PF1 - - - - I2C2_SC L - - - - - - - FMC_A1 - - EVEN TOUT PF2 - - - - I2C2_SM BA - - - - - - - FMC_A2 - - EVEN TOUT PF3 - - - - - - - - - - - - FMC_A3 - - EVEN TOUT PF4 - - - - - - - - - - - - FMC_A4 - - EVEN TOUT PF5 - - - - - - - - - - - - FMC_A5 - - EVEN TOUT PF6 - - - TIM10_C H1 - SPI5_NS SAI1_SD S _B - UART7_ Rx QUADSP I_BK1_IO 3 - - - - - EVEN TOUT PF7 - - - TIM11_CH 1 - SPI5_SC K SAI1_M CLK_B - QUADSP UART7_T I_BK1_IO x 2 - - - - - EVEN TOUT PF8 - - - - - SPI5_MI SO SAI1_SC K_B - UART7_ RTS TIM13_C H1 QUADSPI _BK1_IO0 - - - - EVEN TOUT PF9 - - - - - SPI5_M OSI SAI1_FS _B - UART7_ CTS TIM14_C H1 QUADSPI _BK1_IO1 - - - - EVEN TOUT PF10 - - - - - - - - - QUADSP I_CLK - - - DCMI_D 11 LCD_DE EVEN TOUT PF11 - - - - - SPI5_M OSI - - - - SAI2_SD_ B - FMC_SD NRAS DCMI_D 12 - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 Port F AF1 Pinouts and pin description 96/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PF12 - - - - - - - - - - - - FMC_A6 - - EVEN TOUT PF13 - - - - I2C4_SM BA - DFSDM1 _DATAIN 6 - - - - - FMC_A7 - - EVEN TOUT PF14 - - - - I2C4_SC L - DFSDM1 _CKIN6 - - - - - FMC_A8 - - EVEN TOUT PF15 - - - - I2C4_SD A - - - - - - - FMC_A9 - - EVEN TOUT PG0 - - - - - - - - - - - - FMC_A1 0 - - EVEN TOUT PG1 - - - - - - - - - - - - FMC_A1 1 - - EVEN TOUT PG2 - - - - - - - - - - - - FMC_A1 2 - - EVEN TOUT PG3 - - - - - - - - - - - - FMC_A1 3 - - EVEN TOUT PG4 - - - - - - - - - - - - FMC_A1 4/FMC_ BA0 - - EVEN TOUT PG5 - - - - - - - - - - - - FMC_A1 5/FMC_ BA1 - - EVEN TOUT PG6 - - - - - - - - - - - - FMC_NE 3 DCMI_D 12 LCD_R7 EVEN TOUT PG7 - - - - - - SAI1_M CLK_A - USART6 _CK - - - FMC_IN T DCMI_D 13 LCD_CL K EVEN TOUT I2C1/2/3/ 4/USART 1/CEC DS11532 Rev 8 97/256 Pinouts and pin description SYS Port F Port G AF4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF11 AF12 PG8 - - - - - SPI6_NS S - SPDIF_R X2 USART6 _RTS PG9 - - - - - SPI1_MI SO - SPDIF_R X3 USART6 _RX PG10 - - - - - SPI1_NS S/I2S1_ WS - - - PG11 - - - - - SPI1_SC K/I2S1_ CK - SPDIF_R X0 PG12 - - - LPTIM1_I N1 - SPI6_MI SO - PG13 TRACED 0 - - LPTIM1_ OUT - SPI6_SC K PG14 TRACED 1 - - LPTIM1_E TR - PG15 - - - - - - - ETH_PPS FMC_SD _OUT CLK AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS - LCD_G7 EVEN TOUT QUADSP SAI2_FS_ I_BK2_IO B 2 SDMMC2 _D0 FMC_NE 2/FMC_ NCE DCMI_V SYNC - EVEN TOUT LCD_G3 SAI2_SD_ B SDMMC2 _D1 FMC_NE 3 DCMI_D 2 LCD_B2 EVEN TOUT - - SDMMC2 _D2 ETH_MII_ TX_EN/E TH_RMII_ TX_EN - DCMI_D 3 LCD_B3 EVEN TOUT SPDIF_R X1 USART6 _RTS LCD_B4 - SDMMC2 _D3 FMC_NE 4 - LCD_B1 EVEN TOUT - - USART6 _CTS - - ETH_MII_ TXD0/ET FMC_A2 H_RMII_T 4 XD0 - LCD_R0 EVEN TOUT SPI6_M OSI - - USART6 _TX QUADSP I_BK2_IO 3 - ETH_MII_ TXD1/ET FMC_A2 H_RMII_T 5 XD1 - LCD_B0 EVEN TOUT - - - USART6 _CTS - - DCMI_D 13 - EVEN TOUT - FMC_SD NCAS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 I2C4/UA RT5/TIM 1/2 Port G AF10 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD SYS I2C1/2/3/ 4/USART 1/CEC AF9 Pinouts and pin description 98/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port DS11532 Rev 8 Port H AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PH0 - - - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - - - EVEN TOUT PH2 - - - LPTIM1_I N2 - - - - - QUADSP I_BK2_IO 0 SAI2_SC K_B ETH_MII_ FMC_SD CRS CKE0 - LCD_R0 EVEN TOUT PH3 - - - - - - - - - QUADSP I_BK2_IO 1 SAI2_MC K_B ETH_MII_ FMC_SD COL NE0 - LCD_R1 EVEN TOUT PH4 - - - - I2C2_SC L - - - - LCD_G5 OTG_HS_ ULPI_NX T - - - LCD_G4 EVEN TOUT PH5 - - - - I2C2_SD A SPI5_NS S - - - - - - FMC_SD NWE - - EVEN TOUT PH6 - - - - I2C2_SM BA SPI5_SC K - - - TIM12_C H1 - ETH_MII_ FMC_SD RXD2 NE1 DCMI_D 8 - EVEN TOUT PH7 - - - - I2C3_SC L SPI5_MI SO - - - - - ETH_MII_ FMC_SD RXD3 CKE1 DCMI_D 9 - EVEN TOUT PH8 - - - - I2C3_SD A - - - - - - - FMC_D1 6 DCMI_H SYNC LCD_R2 EVEN TOUT PH9 - - - - I2C3_SM BA - - - - TIM12_C H2 - - FMC_D1 7 DCMI_D 0 LCD_R3 EVEN TOUT PH10 - - TIM5_C H1 - I2C4_SM BA - - - - - - - FMC_D1 8 DCMI_D 1 LCD_R4 EVEN TOUT PH11 - - TIM5_C H2 - I2C4_SC L - - - - - - - FMC_D1 9 DCMI_D 2 LCD_R5 EVEN TOUT PH12 - - TIM5_C H3 - I2C4_SD A - - - - - - - FMC_D2 0 DCMI_D 3 LCD_R6 EVEN TOUT PH13 - - - TIM8_CH 1N - - - - UART4_T X CAN1_T X - - FMC_D2 1 - LCD_G2 EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Pinouts and pin description 99/256 SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PH14 - - - TIM8_CH 2N - - - - UART4_ RX CAN1_R X - - FMC_D2 2 DCMI_D 4 LCD_G3 EVEN TOUT PH15 - - - TIM8_CH 3N - - - - - - - - FMC_D2 3 DCMI_D 11 LCD_G4 EVEN TOUT PI0 - - TIM5_C H4 - - SPI2_NS S/I2S2_ WS - - - - - - FMC_D2 4 DCMI_D 13 LCD_G5 EVEN TOUT PI1 - - - TIM8_BKI N2 - SPI2_SC K/I2S2_ CK - - - - - - FMC_D2 5 DCMI_D 8 LCD_G6 EVEN TOUT PI2 - - - TIM8_CH 4 - SPI2_MI SO - - - - - - FMC_D2 6 DCMI_D 9 LCD_G7 EVEN TOUT PI3 - - - TIM8_ET R - SPI2_M OSI/I2S2 _SD - - - - - - FMC_D2 7 DCMI_D 10 - EVEN TOUT PI4 - - - TIM8_BKI N - - - - - - SAI2_MC K_A - FMC_NB L2 DCMI_D 5 LCD_B4 EVEN TOUT PI5 - - - TIM8_CH 1 - - - - - - SAI2_SC K_A - FMC_NB L3 DCMI_V SYNC LCD_B5 EVEN TOUT PI6 - - - TIM8_CH 2 - - - - - - SAI2_SD_ A - FMC_D2 8 DCMI_D 6 LCD_B6 EVEN TOUT PI7 - - - TIM8_CH 3 - - - - - - SAI2_FS_ A - FMC_D2 9 DCMI_D 7 LCD_B7 EVEN TOUT PI8 - - - - - - - - - - - - - - - EVEN TOUT PI9 - - - - - - - - UART4_ RX CAN1_R X - - FMC_D3 0 - LCD_VS YNC EVEN TOUT PI10 - - - - - - - - - - - ETH_MII_ RX_ER FMC_D3 1 - LCD_HS YNC EVEN TOUT PI11 - - - - - - - - - LCD_G6 OTG_HS_ ULPI_DIR - - - - EVEN TOUT I2C1/2/3/ 4/USART 1/CEC DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SYS Port H Port I AF3 Pinouts and pin description 100/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PI12 - - - - - - - - - - - - - - LCD_HS YNC EVEN TOUT PI13 - - - - - - - - - - - - - - LCD_VS YNC EVEN TOUT PI14 - - - - - - - - - - - - - - LCD_CL K EVEN TOUT PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0 EVEN TOUT PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVEN TOUT PJ1 - - - - - - - - - - - - - - LCD_R2 EVEN TOUT PJ2 - - - - - - - - - - - - - DSI_TE LCD_R3 EVEN TOUT PJ3 - - - - - - - - - - - - - - LCD_R4 EVEN TOUT PJ4 - - - - - - - - - - - - - - LCD_R5 EVEN TOUT PJ5 - - - - - - - - - - - - - - LCD_R6 EVEN TOUT PJ6 - - - - - - - - - - - - - - LCD_R7 EVEN TOUT PJ7 - - - - - - - - - - - - - - LCD_G0 EVEN TOUT PJ8 - - - - - - - - - - - - - - LCD_G1 EVEN TOUT PJ9 - - - - - - - - - - - - - - LCD_G2 EVEN TOUT PJ10 - - - - - - - - - - - - - - LCD_G3 EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port I DS11532 Rev 8 Port J 101/256 Pinouts and pin description SYS STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) AF0 Port Port J AF1 AF2 AF3 TIM8/9/10/ 11/LPTIM TIM3/4/5 1/DFSDM 1/CEC AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 SPI2/I2S SAI2/QU SPI2/I2S SPI6/SAI SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/ 2/SPI3/I2 2/USART 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD S3/SAI1/ 6/UART4/ S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M I2C4/UA 5/7/8/OT I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT RT4/DF G_FS/SP 4/5/6 5/DFSDM LCD OTG1_FS G2_FS SDM1 DIF 1/SPDIF /LCD AF13 AF14 AF15 DCMI/L CD/DSI LCD SYS I2C4/UA RT5/TIM 1/2 PJ11 - - - - - - - - - - - - - - LCD_G4 EVEN TOUT PJ12 - - - - - - - - - LCD_G3 - - - - LCD_B0 EVEN TOUT PJ13 - - - - - - - - - LCD_G4 - - - - LCD_B1 EVEN TOUT PJ14 - - - - - - - - - - - - - - LCD_B2 EVEN TOUT PJ15 - - - - - - - - - - - - - - LCD_B3 EVEN TOUT PK0 - - - - - - - - - - - - - - LCD_G5 EVEN TOUT PK1 - - - - - - - - - - - - - - LCD_G6 EVEN TOUT PK2 - - - - - - - - - - - - - - LCD_G7 EVEN TOUT PK3 - - - - - - - - - - - - - - LCD_B4 EVEN TOUT PK4 - - - - - - - - - - - - - - LCD_B5 EVEN TOUT PK5 - - - - - - - - - - - - - - LCD_B6 EVEN TOUT PK6 - - - - - - - - - - - - - - LCD_B7 EVEN TOUT PK7 - - - - - - - - - - - - - - LCD_DE EVEN TOUT I2C1/2/3/ 4/USART 1/CEC Port K STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DS11532 Rev 8 SYS Pinouts and pin description 102/256 Table 13. STM32F765xx, STM32F767xx, STM32F768Ax, and STM32F769xx alternate function mapping (continued) STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. DS11532 Rev 8 103/256 103 Electrical characteristics 6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 22. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 23. Figure 22. Pin loading conditions Figure 23. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 104/256 DS11532 Rev 8 MS19010V2 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Power supply scheme Figure 24. STM32F769xx/STM32F779xx power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) OUT GP I/Os IN Level shifter Power switch VBAT = 1.65 to 3.6V IO Logic VDDSDMMC OUT PG[9..12], PD[6,7] IN 2 × 2.2 μF VDD IO Logic Kernel logic (CPU, digital & RAM) VCAP_1 VCAP_2 VDD 1/2/...14/20 20 × 100 nF + 1 × 4.7 μF Level shifter 6.1.6 Electrical characteristics Voltage regulator VSS 1/2/...14/20 Flash memory BYPASS_REG VDDUSB VDDUSB OTG FS PHY 100 nF + 1 μF VDDDSI DSI voltage regulator VCAPDSI VDD12DSI DSI PHY 2.2 μF VSSDSI PDR_ON VDD VDDA VREF 100 nF + 1 μF Reset controller 100 nF + 1 μF VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA MSv39619V1 DS11532 Rev 8 105/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme V BAT V DDSDMMC OUT PG[9..12], PD[6,7] IN OUT PA[11,12], PB[14,15] V DDUSB IN VDDUSB Level shifter IN V DDSDMMC Level shifter GP I/O s Level shifter OUT 100 nF + 1 μF backup circuitry (OSC32K, RTC, Wakeup logic, Backup registers, backup RAM) Power switch VBAT = 1.65 to 3.6V IO Logic IO Logic IO Logic 100 nF + 1 μF OTG FS PHY 2 × 2.2 μF V DD V DD 1/2/...14/20 20 × 100nF + 1 × 4.7 μF Kernel logic (CPU, digital & RAM) V CAP_1 V CAP_2 Voltage regulator V SS 1/2/...14/20 Flash memory BYPASS_REG PDR_ON V DD V DDA V REF 100 nF + 1 μF Reset controller 100 nF + 1 μF V REF+ V REF- ADC Analog: RCs,...PLL, V SSA MSv41016V1 1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.18: Power supply supervisor and Section 3.19: Voltage regulator. 2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. 106/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 26. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 14. Voltage characteristics Symbol VDD–VSS VIN Ratings Min Max − 0.3 4.0 Input voltage on FT pins(3) VSS − 0.3 VDD+4.0 Input voltage on TTa pins VSS − 0.3 4.0 Input voltage on any other pin VSS − 0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins(4) - 50 External main supply voltage (including VDDA, VDD, VBAT, VDDUSB, VDDDSI (1) and VDDSDMMC)(2) Input voltage on BOOT pin |ΔVDDx| |VSSX −VSS| VESD(HBM) Electrostatic discharge voltage (human body model) DS11532 Rev 8 see Section 6.3.18: Absolute maximum ratings (electrical sensitivity) Unit V mV - 107/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Applicable only for STM32F7x9 sales types. 2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 3. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed injected current. 4. Include VREF- pin. Table 15. Current characteristics Symbol Ratings Max. ΣIVDD Total current into sum of all VDD_x power lines (source)(1) Σ IVSS (1) Σ IVDDUSB 420 Total current out of sum of all VSS_x ground lines (sink) −420 Total current into VDDUSB power line (source) 25 Σ IVDDSDMMC Total current into VDDSDMMC power line (source) IVDD IVDDSDMMC IVSS IIO ΣIIO IINJ(PIN) ΣIINJ(PIN)(4) 60 Maximum current into each VDD_x power line (source)(1) 100 Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100 Maximum current out of each VSS_x ground line (sink) (1) −100 Output current sunk by any I/O and control pin 25 Output current sourced by any I/Os and control pin −25 Total output current sunk by sum of all I/O and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 Total output current sunk by sum of all SDMMC I/Os 120 Total output current sourced by sum of all I/Os and control pins except USB I/Os(2) −120 Injected current on FT, FTf, RST and B pins Unit (3) mA −5/+0 Injected current on TTa pins(4) ±5 Total injected current (sum of all I/O and control pins)(5) ±25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN 2.4 V, the compensation cell should be used. Figure 39. I/O AC characteristics definition 90% 10% 50% 50% 10% 90% t f(IO)out t r(IO)out T Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the specified capacitance. 6.3.21 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 66: I/O static characteristics). Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 69. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - µs VF(NRST) (2) VNF(NRST) (2) TNRST_OUT NRST Input filtered pulse NRST Input not filtered pulse Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. 162/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 40. Recommended NRST pin protection VDD External reset circuit (1) RPU NRST (2) Internal Reset Filter 0.1 μF STM32F ai14132c 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 66. Otherwise the reset is not taken into account by the device. 6.3.22 TIM timer characteristics The parameters given in Table 70 are guaranteed by design. Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 70. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 216 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 100 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 216 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 × 65536 tTIMxCLK Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. DS11532 Rev 8 163/256 220 Electrical characteristics 6.3.23 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx RTC characteristics Table 71. RTC characteristics 6.3.24 Symbol Parameter Conditions - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register Min Max 4 - 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 72 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 72. ADC characteristics Symbol VDDA VREF+ fADC fTRIG(2) VAIN RAIN(2) Parameter Power supply Positive reference voltage ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit 1.7(1) - 3.6 V 1.7(1) - VDDA V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 kΩ - 1.5 - 6 kΩ - - 4 7 pF VDDA −VREF+ < 1.2 V VDDA = 1.7(1) to 2.4 V tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 µs - - - 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs 1/fADC tS(2) Sampling time tSTAB(2) Power-up time 164/256 - - - 2(5) fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC - - 2 3 µs DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 72. ADC characteristics (continued) Symbol tCONV(2) Parameter Conditions Min Typ Max Unit fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs Total conversion time (including sampling time) 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(2) (fADC = 36 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2.4 Msps 12-bit resolution Interleave Dual ADC mode - - 4.5 Msps 12-bit resolution Interleave Triple ADC mode - - 7.2 Msps IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 72. Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. DS11532 Rev 8 165/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 73. ADC static accuracy at fADC = 18 MHz Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA −VREF < 1.2 V Typ Max(1) ±3 ±4 ±2 ±3 ±1 ±3 ±1 ±2 ±2 ±3 Unit LSB 1. Guaranteed by characterization results. Table 74. ADC static accuracy at fADC = 30 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA −VREF < 1.2 V Typ Max(1) ±2 ±5 ±1.5 ±2.5 ±1.5 ±4 ±1 ±2 ±1.5 ±3 Unit LSB 1. Guaranteed by characterization results. Table 75. ADC static accuracy at fADC = 36 MHz Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA −VREF < 1.2 V Typ Max(1) ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 Unit LSB 1. Guaranteed by characterization results. Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C 1. Guaranteed by characterization results. 166/256 DS11532 Rev 8 Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - − 67 − 72 - dB STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 °C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - − 70 − 72 - dB 1. Guaranteed by characterization results. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.20 does not affect the ADC accuracy. Figure 41. ADC accuracy characteristics [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 V SSA 7 4093 4094 4095 4096 VDDA ai14395c 1. See also Table 74. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. DS11532 Rev 8 167/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 42. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function VDDA(4) VREF+(4) Sample-and-hold ADC converter I/O analog switch RAIN(1) RADC Converter VAIN Cparasitic(2) Ilkg(3) VSS CADC Sampling switch with multiplexing VSS VSSA MSv67871V3 1. Refer to Table 72 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Section Table 66.: I/O static characteristics for the value of lIkg, 4. Refer to Section 6.1.6: Power supply scheme. 168/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 43 or Figure 44, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F VREF+ (1) 1 μF // 10 nF VDDA 1 μF // 10 nF VSSA/VREF- (1) ai17535b 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (1) 1 μF // 10 nF VREF-/VSSA (1) ai17536c 1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. DS11532 Rev 8 169/256 220 Electrical characteristics 6.3.25 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Temperature sensor characteristics Table 78. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 79. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FF0 F44C - 0x1FF0 F44D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 F44E - 0x1FF0 F44F 6.3.26 VBAT monitoring characteristics Table 80. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 4 - - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er(1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.27 Reference voltage The parameters given in Table 81 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 81. internal reference voltage Symbol VREFINT TS_vrefint(1) VREFINT_s(2) 170/256 Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.24 V - 10 - - µs VDD = 3V ± 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 81. internal reference voltage (continued) Symbol Parameter Conditions Min Typ Max Unit TCoeff(2) Temperature coefficient - - 30 50 ppm/°C tSTART(2) Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 82. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 6.3.28 Memory address Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FF0 F44A - 0x1FF0 F44B DAC electrical characteristics Table 83. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.7(1) - 3.6 V VREF+ Reference supply voltage 1.7(1) - 3.6 V VSSA Ground 0 - 0 V - 5 - kΩ - 25 - - Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum kΩ resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF DAC_OUT Lower DAC_OUT voltage with buffer ON min(2) 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA − 0.2 V DAC_OUT Lower DAC_OUT voltage with buffer OFF min(2) - 0.5 - mV - VREF+ − 1LSB V RLOAD (2) RO(2) CLOAD(2) Connected to Resistive load VSSA with buffer ON Connected to VDDA DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) - DS11532 Rev 8 VREF+ ≤VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. 171/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 83. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit µA Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 µA With no load, middle code (0x800) on the inputs - 475 625 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV Given for the DAC in 12-bit configuration Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.5 % Given for the DAC in 12-bit configuration - 3 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ IDDA(4) DNL(4) Gain error(4) DAC DC VDDA current consumption in quiescent mode(3) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the (4) tSETTLING highest input codes when DAC_OUT reaches final value ±4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 172/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 83. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 45. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.29 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. • Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0410 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below: DS11532 Rev 8 173/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 84. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 16 Analog filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: • The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. • The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: Tr(SDA/SCL)=0.8473xRpxCload Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 85 for the analog filter characteristics: Table 85. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 70(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. 174/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 86 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 86. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode SPI1,4,5,6 2.7≤VDD≤3.6 54(2) Master mode SPI1,4,5,6 1.71≤VDD≤3.6 27 Master transmitter mode SPI1,4,5,6 1.71≤VDD≤3.6 54 Slave receiver mode SPI1,4,5,6 1.71≤VDD≤3.6 54 - - MHz Slave mode transmitter/full duplex SPI1,4,5,6 2.7≤VDD≤3.6 50(3) Slave mode transmitter/full duplex SPI1,4,5,6 1.71≤VDD≤3.6 37(3) Master & Slave mode SPI2,3 1.71≤VDD≤3.6 27 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*TPLCK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*TPLCK - - tw(SCKH) tw(SCKL) SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2 DS11532 Rev 8 Unit ns 175/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 86. SPI dynamic characteristics(1) (continued) Symbol Conditions Min Typ Max Master mode 5 10(4) - - tsu(SI) Slave mode 4.5 - - th(MI) Master mode 2 0(4) - - Slave mode 2 - - tsu(MI) Parameter Data input setup time Data input hold time th(SI) ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 Slave mode 2.7≤VDD≤3.6V - 6.5 10 Slave mode 1.71≤VDD≤3.6V - 6.5 13.5 tv(MO) Master mode - 2 6 th(SO) Slave mode 1.71≤VDD≤3.6V 4.5 - - Master mode 0 - - tv(SO) Data output valid time Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz. 3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. 4. Only for SPI6. Figure 46. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) First bit OUT th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 176/256 DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 47. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) th(SO) First bit OUT tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) First bit IN MOSI input Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 48. SPI timing diagram - master mode(1) High NSS input SCK Output SCK Output tc(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INPUT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) BIT1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. DS11532 Rev 8 177/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 87 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 87. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256xFs(2) MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs 30 70 DCK I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 5 - th(WS) WS hold time Slave mode 2 - Master receiver 2.5 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) - 12 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. The maximum value of 256xFs is 49.152 MHz (APB1 maximum frequency). Note: 178/256 Refer to RM0410 reference manual I2S section for more details about the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DS11532 Rev 8 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 49. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(1) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(1) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive MS46528V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 50. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(1) MSB transmit SDreceive LSB receive LSB transmit th(SD_MR) tsu(SD_MR) (1) Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive MS46529V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS11532 Rev 8 179/256 220 Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx JATG/SWD characteristics Unless otherwise specified, the parameters given in Table 88 for JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 88. Dynamics characteristics: JTAG characteristics Symbol Parameter Fpp 1/tc(TCK) Conditions Min Typ Max 2.7V