STM32F777ZIT6

STM32F777xx STM32F778Ax STM32F779xx Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/ 512+16+4KB RAM, crypto, USB OTG HS/FS, 28 com IF, LCD, DSI Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. • Memories – Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write – SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • Dual mode Quad-SPI • Graphics – Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface – Hardware JPEG codec – LCD-TFT controller supporting up to XGA resolution – MIPI® DSI host controller supporting up to 720p 30 Hz resolution • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – Dedicated USB power – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration September 2017 This is information on a product in full production. )%*$ LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm) WLCSP180 LQFP144 (20 × 20 mm) (0.4 mm pitch) LQFP176 (24 × 24 mm) TFBGA216 (13 x 13 mm) TFBGA100 (8 x 8 mm) LQFP208 (28 x 28 mm) • Low-power – Sleep, Stop and Standby modes – VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels • Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer • Debug mode – SWD & JTAG interfaces – Cortex®-M7 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 108 MHz – Up to 166 5 V-tolerant I/Os DocID028294 Rev 6 1/255 www.st.com STM32F777xx STM32F778Ax STM32F779xx • Up to 28 communication interfaces – Up to 4 I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio – 2 x SAIs (serial audio interface) – 3 × CANs (2.0B Active) and 2x SDMMCs – SPDIFRX interface – HDMI-CEC – MDIO slave interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit camera interface up to 54 Mbyte/s • Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, triple DES, HASH (MD5, SHA-1, SHA-2), and HMAC • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID Table 1. Device summary Reference Part number STM32F777xx STM32F777BI, STM32F777II, STM32F777NI, STM32F777VI, STM32F777ZI STM32F778Ax STM32F778AI STM32F779xx STM32F779AI, STM32F779BI, STM32F779II, STM32F779NI 2/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 2.13 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.19 2.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35 2.20 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 2.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID028294 Rev 6 3/255 6 Contents 3 4/255 STM32F777xx STM32F778Ax STM32F779xx 2.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 42 2.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 43 2.27 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.28 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.30 Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.31 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 45 2.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 45 2.33 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 46 2.35 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 46 2.36 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 48 2.39 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.40 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.41 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.42 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.43 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 49 2.44 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.45 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.46 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.47 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.48 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 115 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 115 5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 115 5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 145 5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 156 5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 DocID028294 Rev 6 5/255 6 Contents 6 7 STM32F777xx STM32F778Ax STM32F779xx 5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 213 5.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 214 5.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 216 5.3.35 DFSDM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 219 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1 LQFP100 14x 14 mm, low-profile quad flat package information . . . . . . 221 6.2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.3 LQFP144 20 x 20 mm, low-profile quad flat package information . . . . . 228 6.4 LQFP176 24 x 24 mm, low-profile quad flat package information . . . . . 232 6.5 LQFP208 28 x 28 mm low-profile quad flat package information . . . . . . 236 6.6 WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.7 UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 6.8 TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 252 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 6/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32F777xx, STM32F778Ax and STM32F779xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STM32F777xx, STM32F778Ax and STM32F779xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 STM32F777xx, STM32F778Ax and STM32F779xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 114 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 115 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 115 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode), regulator ON . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode) on ITCM interface (ART disabled), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Single bank mode, ART ON except prefetch / L1-cache ON) DocID028294 Rev 6 7/255 10 List of tables Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. 8/255 STM32F777xx STM32F778Ax STM32F779xx or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 126 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 127 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 127 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 128 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 129 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Flash memory programming (dual bank configuration nDBANK=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 168 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx List of tables Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 189 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 190 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 193 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 194 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 196 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 198 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 DFSDM measured timing 1.71-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 220 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 220 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 222 TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 227 Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package DocID028294 Rev 6 9/255 10 List of tables STM32F777xx STM32F778Ax STM32F779xx mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 134. UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 245 Table 136. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 137. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 248 Table 138. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Table 139. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 140. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 252 Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 10/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F777xx, STM32F778Ax and STM32F779xx block diagram . . . . . . . . . . . . . . . . . 19 STM32F777xx, STM32F778Ax and STM32F779xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 34 STM32F77xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F77xxx TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32F77xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32F77xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32F779xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32F779Ax/STM32F778Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32F77xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32F779xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32F77xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32F77xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32F779xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 150 MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 150 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 170 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 170 DocID028294 Rev 6 11/255 13 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 12/255 STM32F777xx STM32F778Ax STM32F779xx 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 186 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 192 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 194 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 197 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 203 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 207 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 207 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 221 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 TFBGA100, 8 × 8 × 0.8mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 228 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. List of figures LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 232 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 236 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 DocID028294 Rev 6 13/255 13 Description 1 STM32F777xx STM32F778Ax STM32F779xx Description The STM32F777xx, STM32F778Ax and STM32F779xx devices are based on the highperformance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a floating point unit (FPU) which supports Arm® double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F777xx, STM32F778Ax and STM32F779xx devices incorporate high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces: • Up to four I2Cs • Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus four UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI) • Three CANs • Two SAI serial audio interfaces • Two SDMMC host interfaces • Ethernet and camera interfaces • LCD-TFT display controller • Chrom-ART Accelerator™ • SPDIFRX interface • HDMI-CEC Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors and a cryptographic acceleration cell. The STM32F777xx, STM32F778Ax and STM32F779xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. 14/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Description The STM32F777xx, STM32F778Ax and STM32F779xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. These features make the STM32F777xx, STM32F778Ax and STM32F779xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances • Mobile applications, Internet of Things • Wearable devices: smartwatches The following table lists the peripherals available on each part number. DocID028294 Rev 6 15/255 53 Peripherals Flash memory in Kbytes SRAM in Kbytes STM32F77xVx STM32F77xZx STM32F779Ax 1024 1024 1024 2048 2048 STM32F778Ax 2048 2048 512(368+16+128) Instruction 16 Backup 4 STM32F77xNx 1024 1024 2048 2048 Yes Ethernet Yes No Yes 10 Advanced-control 2 Basic 2 Low-power 1 SPI / Yes I2S 4/3 (simplex)(2) 6/3 (simplex)(2) I2C 4 USART/UART 4/4 USB OTG FS Yes USB OTG HS Yes CAN 3 SAI 2 SPDIFRX 4 inputs SDMMC1 Yes SDMMC2 Yes(3) Camera interface Host(4) Yes No Yes LCD-TFT Yes Chrom-ART Accelerator™ (DMA2D) Yes JPEG codec Yes Cryptography Yes STM32F777xx STM32F778Ax STM32F779xx DocID028294 Rev 6 General-purpose Random number generator MIPI-DSI 2048 STM32F77xBx Yes(1) Quad-SPI Communication interfaces 1024 System FMC memory controller Timers STM32F77xIx Description 16/255 Table 2. STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts Peripherals GPIOs STM32F77xVx STM32F77xZx 82 114 DFSDM1 STM32F779Ax STM32F778Ax 129 STM32F77xNx 159 Yes (4 filters) 3 16 24 Yes 2 12-bit DAC Number of channels 216 MHz(5) Maximum CPU frequency 1.7 to 3.6 V(6) Operating voltage Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Package STM32F77xBx 132 12-bit ADC Number of channels STM32F77xIx Junction temperature: –40 to + 125 °C DocID028294 Rev 6 LQFP100 TFBGA100 LQFP144 WLCSP180 UFBGA176(7) LQFP176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. LQFP208 TFBGA216 STM32F777xx STM32F778Ax STM32F779xx Table 2. STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts (continued) 3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 4. DSI host interface is only available on STM32F779x sales types. 5. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range). 6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). 7. UFBGA176 is not available for STM32F779x sales types. Description 17/255 Description STM32F777xx STM32F778Ax STM32F779xx Full compatibility throughout the family The STM32F777xx, STM32F778Ax and STM32F779xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package 3& 9'' 966$ 95() 9''$ 3$:.83 3$ 3$ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[                 9'' 3% 9&$3 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3& 3% 3& 3$ 3$ 3$ 3$ 9'' 3$ 3& 966$ 95() 9''$ 3$:.83 3$ 3$ 3$ 966  670)[[[ 3LQVWRDUHQRWFRPSDWLEOH 9'' 966 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9'' 966  06Y9 The STM32F77x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are fully pin to pin compatible with STM32F4xx devices. 18/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Description 86% '0$ 27*+6 ),)2 *3'0$ 6WUHDPV ),)2 *3'0$ 6WUHDPV ),)2 /&'7)7 ),)2 3%>@ *3,23257% 3&>@ *3,23257& 3'>@ *3,23257' 3(>@ *3,23257( 3)>@ *3,23257) 3*>@ *3,23257* 3+>@ *3,23257+ *3,23257*3,23257. #9'' 9'' %%JHQ32:(501*7 92/75(* 9729 /6 )&/. +&/. $3%3&/. $3%3&/. $+%3&/. $+%3&/. ),)2 ),)2 6'00& 6'00& /6 *3'0$ $+%$3% $+%$3% &/.&6'>@ 9''$966$ 15(6(7 :.83>@ 9''00& WR9 9''86% WR9 9'' WR9 966 9&$3 #9'' 26&B,1 26&B287 9%$7 WR9 #96: (;7,7:.83 *3'0$ '3 '0 6&/6'$,17,'9%86 &/.1(>@$>@ '>@12(11:(1 1%/>@6'&/.(>@6'1(>@ 6'1:(1/ 15$61&$61$'9 1:$,7,171 :'*. &5& ;7$/N+] 57& $:8 %DFNXSUHJLVWHU 26&B,1 26&B287 57&B76 57&B7$03[ 57&B287 .%%.35$0 7,0 E FKDQQHOV(75DV$) 7,0 E FKDQQHOV(75DV$) 7,0 E FKDQQHOV(75DV$) 7,0 E FKDQQHOV 7,0 E FKDQQHOVDV$) E 7,03:0 E 7,0 E FKDQQHODV$) 7,0 E FKDQQHODV$) 86$57 VPFDUG LU'$ 5;7;6&. &76576DV$) 86$57 VPFDUG LU'$ 8$57 5;7;6&. &76576DV$) 5;7;DV$) 8$57 5;7;DV$) 8$57 5;7;DV$) 8$57 5;7;DV$) 026,0,626&. 166DV$) 026,0,626&. 166DV$) 6&/6'$60%$/DV$) E E 7,0 VPFDUG 86$57 LU'$ VPFDUG 86$57 LU'$ 026,0,62 6&.166DV$) 026,0,62 6&.166DV$) 026,0,62 6&.166DV$) 026,0,62 6&.166DV$) 63,,6 63, ::'* /37,0 63, E 7,0 E 7,0 E 6'6&.)60&/.DV$) ),)2 ),)2 63, 6$, 6$, ,&60%86 ,&60%86 0',26ODYH #9''$ E[&$1 '6,+267 $'& 3// ,) ,) /'2 E[&$1 #9''$ '$& '6,B'231'6,B'31 '6,B9&$3'6,B&.31 '6,B9'''6,B966'6,B7(DV$) '$& '$& DV$) '$& DV$) 6&/6'$60%$/DV$) 7;5; 7;5; E[&$1 7;5; 63',)5; 63',)5;>@DV$) +'0,&(& +'0,B&(&DV$) ,7) '6,3+< 6&/6'$60%$/DV$) 6&/6'$60%$/DV$) ,&60%86 8 67HPSHUDWXUHVHQVRU $5 7  0 % S V $'& 63,,6 ,&60%86 6@ &.287 &.,1>@ '$7$,1>@ &.287 325 UHVHW *3,23257, 3.>@ 5;7;6&. &76576DV$) 5;7;6&. &76576DV$) 86% 27*)6 4XDG63, $+%0+] 3//3//3// 3->@ +6@1 FKDQ7,0B&+>@(75%.,1DV$) 65$0.% $+%0+= 3:5&75/ '0$' '>@ &0'&.DV$) '>@ &0'&.DV$) FRPSOFKDQ7,0B&+>@1 FKDQ7,0B&+>@(75%.,1DV$) -3(* 51* 65$0.% ),)2 3$>@ $) +$6+ #9''$ &+520$57 3,>@ '(6 $(6 3+< ),)2 )/$6+0% $ 3 %  0+]  $3%0+]PD[ /&'B5>@/&'B*>@/&'B%>@ /&'B+6Ͳd&dͺD h^ͺ,^ͺD d,ZEdͺD DͺWϮ 'W D h^Kd' >Ͳd&d DϮ ƚŚĞƌŶĞƚ ,^ DͺDDϮ ,W .% ,'&DFKH y/D 'W Dϭ DͺW/ ƌŵŽƌƚĞdžͲDϳ DͺDDϭ /dD dD Figure 3. STM32F777xx, STM32F778Ax and STM32F779xx AXI-AHB bus matrix architecture(1) dDZD ϭϮϴ@ W Y1$'9B1( )0&B1$'9  WZ1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK − 1 3THCLK + 1 FMC_NEx low to FMC_NWE low THCLK − 1 THCLK + 0.5 THCLK − 1.5 THCLK + 0.5 THCLK - - 0 THCLK − 0.5 - - 0.5 THCLK − 0.5 - FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - THCLK + 1 tw(NADV) 1. Guaranteed by characterization results. 194/255 DocID028294 Rev 6 Unit ns STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) Min Max Unit 8THCLK − 1 8THCLK + 1 6THCLK − 1.5 6THCLK + 0.5 FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK − 1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK + 2 - ns 1. Guaranteed by characterization results. Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms WZ1( )0&B 1( WY12(B1( W K1(B12( )0&B12( W Z12( )0&B1:( WK$B12( WY$B1( )0&B $>@ $GGUHVV WY%/B1( WK%/B12( )0&B 1%/>@ 1%/ WK'DWDB1( WVX'DWDB1( W Y$B1( )0&B $'>@ WVX'DWDB12( WK'DWDB12( 'DWD $GGUHVV WK$'B1$'9 W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 DocID028294 Rev 6 195/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Table 105. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3THCLK − 1 3THCLK + 1 2THCLK 2THCLK + 0.5 THCLK − 1 THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time THCLK − 0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) THCLK + 0.5 - th(A_NOE) Address hold time after FMC_NOE high THCLK − 0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NE) Data to FMC_NEx high setup time THCLK − 1 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK − 1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 106. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol tw(NE) tw(NOE) Parameter FMC_NE low time FMC_NWE low time Max 8THCLK − 1 8THCLK + 1 5THCLK − 1.5 5THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK + 1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid - 1. Guaranteed by characterization results. 196/255 Min DocID028294 Rev 6 4THCLK+ 1 Unit ns STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms WZ1( )0&B 1([ )0&B12( WY1:(B1( WZ1:( W K1(B1:( )0&B1:( WK$B1:( WY$B1( )0&B $>@ $GGUHVV WY%/B1( WK%/B1:( )0&B 1%/>@ 1%/ W Y$B1( )0&B $'>@ W Y'DWDB1$'9 $GGUHVV WK'DWDB1:( 'DWD WK$'B1$'9 W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 Table 107. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) Parameter Min Max Unit FMC_NE low time 4THCLK − 1 4THCLK + 1 FMC_NEx low to FMC_NWE low THCLK − 1 THCLK + 0.5 FMC_NWE low time 2THCLK − 0.5 2THCLK+ 0.5 FMC_NWE high to FMC_NE high hold time THCLK − 0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 THCLK THCLK+ 1 FMC_AD(adress) valid hold time after FMC_NADV high) THCLK − 0.5 - th(A_NWE) Address hold time after FMC_NWE high THCLK + 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 0.5 - tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FMC_NADV low time tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FMC_NWE high THCLK + 0.5 - DocID028294 Rev 6 ns 197/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx 1. Guaranteed by characterization results. Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time Min Max 9THCLK – 1 9THCLK + 1 Unit 7THCLK – 0.5 7THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK – 1 - 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 66 through Figure 69 represent synchronous waveforms and Table 109 through Table 112 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable; • MemoryType = FMC_MemoryType_CRAM; • WriteBurst = FMC_WriteBurst_Enable; • CLKDivision = 1; • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM • CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all the timing tables, the THCLK is the HCLK clock period. – For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at CL=30 pF (on FMC_CLK). – 198/255 For 1.71 V≤ VDD@ WG&/./12(/ WG&/.+12(+ )0&B12( W G&/./$'9 )0&B$'>@ WG&/./$',9 WVX$'9&/.+ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 WK&/.+1:$,79 WK&/.+1:$,79 069 DocID028294 Rev 6 199/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Table 109. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1. td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK − 0.5 - tw(CLK) td(CLKL-NExL) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 200/255 DocID028294 Rev 6 Unit ns STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Figure 67. Synchronous multiplexed PSRAM write timings %867851  WZ&/. WZ&/. )0&B&/. 'DWDODWHQF\  WG&/./1([/ WG&/.+1([+ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/.+1:(+ WG&/./1:(/ )0&B1:( WG&/./$',9 WG&/./$'9 )0&B$'>@ WG&/./'DWD WG&/./'DWD $'>@ ' ' )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 WG&/.+1%/+ )0&B1%/ 069 DocID028294 Rev 6 201/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Table 110. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 .5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 0.5 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. Guaranteed by characterization results. 202/255 DocID028294 Rev 6 Unit ns STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings WZ&/. WZ&/. )0&B&/. WG&/./1([/ WG&/.+1([+ 'DWDODWHQF\  )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/./12(/ WG&/.+12(+ )0&B12( WVX'9&/.+ WK&/.+'9 WVX'9&/.+ )0&B'>@ WK&/.+'9 ' WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E ' WK&/.+1:$,79 WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ W K&/.+1:$,79 WK&/.+1:$,79 069 Table 111. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) t(CLKL-NExL) td(CLKH-NExH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 1.5 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 3.5 - 2 - 3.5 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high DocID028294 Rev 6 Unit ns 203/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx 1. Guaranteed by characterization results. Figure 69. Synchronous non-multiplexed PSRAM write timings WZ&/. WZ&/. )0&B&/. WG&/./1([/ WG&/.+1([+ 'DWDODWHQF\  )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/./1:(/ WG&/.+1:(+ )0&B1:( WG&/./'DWD WG&/./'DWD ' )0&B'>@ ' )0&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WG&/.+1%/+ WK&/.+1:$,79 )0&B1%/ 069 204/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Table 112. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 1 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 1 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. NAND controller waveforms and timings Figure 70 through Figure 73 represent synchronous waveforms, and Table 113 and Table 114 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01; • COM.FMC_WaitSetupTime = 0x03; • COM.FMC_HoldSetupTime = 0x02; • COM.FMC_HiZSetupTime = 0x01; • ATT.FMC_SetupTime = 0x01; • ATT.FMC_WaitSetupTime = 0x03; • ATT.FMC_HoldSetupTime = 0x02; • ATT.FMC_HiZSetupTime = 0x01; • Bank = FMC_Bank_NAND; • MemoryDataWidth = FMC_MemoryDataWidth_16b; • ECC = FMC_ECC_Enable; • ECCPageSize = FMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID028294 Rev 6 205/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Figure 70. NAND controller waveforms for read access )0&B1&([ $/()0&B$ &/()0&B$ )0&B1:( WG$/(12( WK12($/( )0&B12(15( WVX'12( WK12(' )0&B'>@ 069 Figure 71. NAND controller waveforms for write access )0&B1&([ $/()0&B$ &/()0&B$ WK1:($/( WG$/(1:( )0&B1:( )0&B12(15( WY1:(' WK1:(' )0&B'>@ 069 206/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Figure 72. NAND controller waveforms for common memory read access )0&B1&([ $/()0&B$ &/()0&B$ WK12($/( WG$/(12( )0&B1:( WZ12( )0&B12( WVX'12( WK12(' )0&B'>@ 069 Figure 73. NAND controller waveforms for common memory write access )0&B1&([ $/()0&B$ &/()0&B$ WG$/(12( WZ1:( WK12($/( )0&B1:( )0&B1 2( WG'1:( WY1:(' WK1:(' )0&B'>@ 069 Table 113. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max Unit 4THCLK − 0.5 4THCLK + 0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK + 1 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4THCLK − 2 - ns 1. Guaranteed by characterization results. DocID028294 Rev 6 207/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Table 114. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter Min Max Unit 4THCLK − 0.5 4THCLK + 0.5 FMC_NWE low width tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2THCLK − 1 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK − 1 - - 3THCLK + 1 2THCLK − 2 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid ns 1. Guaranteed by characterization results. SDRAM waveforms and timings • CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. – For 3.0 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on FMC_SDCLK). – For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). – For 1.71 V≤ VDD@ 5RZQ &RO &RO &ROL &ROQ WK6'&/./B$GG& WK6'&/./B61'( WG6'&/./B61'( )0&B6'1(>@ WG6'&/./B15$6 WK6'&/./B15$6 )0&B6'15$6 WK6'&/./B1&$6 WG6'&/./B1&$6 )0&B6'1&$6 )0&B6'1:( WVX6'&/.+B'DWD )0&B'>@ WK6'&/.+B'DWD 'DWD 'DWD 'DWDL 'DWDQ 069 208/255 DocID028294 Rev 6 STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Table 115. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 tsu(SDCLKH _Data) Data input setup time 1.5 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Table 116. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 tsu(SDCLKH_Data) Data input setup time 0 - th(SDCLKH_Data) Data input hold time 4.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. DocID028294 Rev 6 209/255 220 Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx Figure 75. SDRAM write access waveforms )0&B6'&/. WG6'&/./B$GG& WK6'&/./B$GG5 WG6'&/./B$GG5 )0&B$>@ 5RZQ &RO &RO &ROL &ROQ WK6'&/./B$GG& WK6'&/./B61'( WG6'&/./B61'( )0&B6'1(>@ WK6'&/./B15$6 WG6'&/./B15$6 )0&B6'15$6 WG6'&/./B1&$6 WK6'&/./B1&$6 WG6'&/./B1:( WK6'&/./B1:( )0&B6'1&$6 )0&B6'1:( WG6'&/./B'DWD 'DWD )0&B'>@ 'DWD 'DWDL 'DWDQ WK6'&/./B'DWD WG6'&/./B1%/ )0&B1%/>@ 069 Table 117. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - 1. Guaranteed by characterization results. 210/255 DocID028294 Rev 6 Unit ns STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics Table 118. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. 5.3.31 Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 119 and Table 120 for Quad-SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 18: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate function characteristics. Table 119. Quad-SPI characteristics in SDR mode(1) Symbol Fck1/t(CK) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 V≤ VDD