STM32G070CB/KB/RB
Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM,
4x USART, timers, ADC, comm. I/Fs, 2.0-3.6V
Datasheet - production data
Features
Core: Arm® 32-bit Cortex®-M0+ CPU,
frequency up to 64 MHz
-40°C to 85°C operating temperature
Memories
– 128 Kbytes of Flash memory with
protection
– 36 Kbytes of SRAM (32 Kbytes with HW
parity check)
CRC calculation unit
Reset and power management
– Voltage range: 2.0 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Low-power modes:
Sleep, Stop, Standby
– VBAT supply for RTC and backup registers
Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator with calibration
– Internal 16 MHz RC with PLL option
– Internal 32 kHz RC oscillator (±5 %)
LQFP32 7 × 7 mm
LQFP48 7 × 7 mm
LQFP64 10 × 10 mm
Communication interfaces
– Two I2C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current
sink, one supporting SMBus/PMBus and
wakeup from Stop mode
– Four USARTs with master/slave
synchronous SPI; two supporting ISO7816
interface, LIN, IrDA capability, auto baud
rate detection and wakeup feature
– Two SPIs (32 Mbit/s) with 4- to 16-bit
programmable bitframe, one multiplexed
with I2S interface
Development support: serial wire debug (SWD)
All packages ECOPACK 2 compliant
Up to 59 fast I/Os
– All mappable on external interrupt vectors
– Multiple 5 V-tolerant I/Os
7-channel DMA controller with flexible mapping
12-bit, 0.4 µs ADC (up to 16 ext. channels)
– Up to 16-bit with hardware oversampling
– Conversion range: 0 to 3.6V
11 timers: 16-bit for advanced motor control,
five 16-bit general-purpose, two basic 16-bit,
two watchdogs, SysTick timer
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
March 2020
This is information on a product in full production.
DS12766 Rev 2
1/93
www.st.com
Contents
STM32G070CB/KB/RB
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.7
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.6
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8
Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14
3.15
2/93
3.7.1
3.13.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
3.13.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 21
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.2
General-purpose timers (TIM3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . . . 23
DS12766 Rev 2
STM32G070CB/KB/RB
Contents
3.15.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15.5
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16
Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 25
3.17
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18
Universal synchronous/asynchronous receiver transmitter (USART) . . . 26
3.19
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20.1
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 29
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 43
5.3.4
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DS12766 Rev 2
3/93
4
Contents
6
STM32G070CB/KB/RB
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.15
NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.16
Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.17
Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.18
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3.19
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3.20
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3.21
Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 73
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4/93
DS12766 Rev 2
STM32G070CB/KB/RB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
STM32G070CB/KB/RB family device features and peripheral counts . . . . . . . . . . . . . . . . 10
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 13
Interconnect of STM32G070CB/KB/RB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Terms and symbols used in Table 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Current consumption in Run and Low-power run modes
at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 47
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DS12766 Rev 2
5/93
6
List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
6/93
STM32G070CB/KB/RB
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DS12766 Rev 2
STM32G070CB/KB/RB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32G070RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32G070CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32G070KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DS12766 Rev 2
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7
Introduction
1
STM32G070CB/KB/RB
Introduction
This document provides information on STM32G070CB/KB/RB microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
Information on memory mapping and control registers is object of reference manual.
Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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STM32G070CB/KB/RB
2
Description
Description
The STM32G070CB/KB/RB mainstream microcontrollers are based on high-performance
Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(128 Kbytes of Flash program memory with read protection, write protection, and 36 Kbytes
of SRAM), DMA and an extensive range of system functions, enhanced I/Os and
peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one
I2S, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, a low-power
RTC, an advanced control PWM timer, five general-purpose 16-bit timers, two basic timers,
two watchdog timers, and a SysTick timer.
The devices operate within ambient temperatures from -40 to 85°C. They can operate with
supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a
comprehensive set of power-saving modes allows the design of low-power applications.
VBAT direct battery input allows keeping RTC and backup registers powered.
The devices come in packages with 32 to 64 pins.
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28
Description
STM32G070CB/KB/RB
Table 1. STM32G070CB/KB/RB family device features and peripheral counts
Comm.
interfaces
Timers
Peripheral
STM32G070KB
STM32G070CB
Flash memory (Kbyte)
128
SRAM (Kbyte)
32 (with parity) or 36 (without parity)
Advanced control
1 (16-bit)
General-purpose
5 (16-bit)
Basic
2 (16-bit)
SysTick
1
Watchdog
2
SPI [I2S](1)
2 [1]
2C
2
USART
4
I
RTC
Yes
(2)
No
AES(2)
No
Tamper pins
2
RNG
GPIOs
29
43
59
Wakeup pins
4
4
5
12-bit ADC channels
11 ext.
+ 2 int.
14 ext.
+ 3 int.
16 ext.
+ 3 int.
Max. CPU frequency
64 MHz
Operating voltage
2.0 - 3.6 V
Operating temperature
Ambient: -40 to 85 °C
Junction: -40 to 105 °C
Number of pins
32
48
2
1. The numbers in brackets denote the count of SPI interfaces configurable as I S interface.
2. RNG: Random number generator, AES: Advanced Encryption Standard
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STM32G070RB
DS12766 Rev 2
64
STM32G070CB/KB/RB
Description
Figure 1. Block diagram
SWCLK
SWDIO
as AF
POWER
DMAMUX
SWD
DMA
VDDIO1
VDDA
Flash memory
VDD
128 KB
NVIC
IOPORT
Bus matrix
CPU
CORTEX-M0+
fmax = 64 MHz
Voltage
regulator
VCORE
I/F
SRAM
36 KB
VDD/VDDA
VSS/VSSA
Parity
HSI16
SUPPLY
SUPERVISION
POR
Reset
Int
POR/PDR
NRST
T sensor
RC 16 MHz
PLLPCLK
PLLRCLK
PA[15:0]
Port A
LSI
PB[15:0]
Port B
PC[15:0]
Port C
PD[9:0]
Port D
PF4,3,1,0
Port F
59 AF
decoder
GPIOs
PLL
XTAL OSC
4-48 MHz
RC 32 kHz
HSE
IWDG
CRC
RCC
I/F
LSE
AHB
Reset & clock control
EXTI
OSC_IN
OSC_OUT
VDD
VBAT
Low-voltage
detector
LSE
System and
peripheral
clocks
XTAL32 kHz
RTC, TAMP
Backup regs
I/F
AHB-to-APB
OSC32_IN
OSC32_OUT
RTC_OUT
RTC_REFIN
RTC_TS
TAMP_IN
VREF+
TIM1
6 channels
BRK, ETR input as AF
TIM3
4 ch., ETR as AF
TIM14
1 channel as AF
TIM15
2 channels as AF
TIM16 &
17
TIMER
16/17
1 channel as AF
I/F
SYSCFG
APB
MOSI/SD
MISO/MCK
SCK/CK
NSS/WS as AF
ADC
SPI1/I2S
TIM6
TIM7
MOSI, MISO,
SCK, NSS,
as AF
SPI2
SCL, SDA, SMBA,
SMBUS as AF
I2C1
SCL, SDA as AF
I2C2
APB
16x IN
PWRCTRL
WWDG
DBGMCU
Power domain of analog blocks :
VBAT
VDD
VDDA
IR_OUT as AF
USART1
&2
USART1/2
RX, TX,CTS, RTS,
CK as AF
USART3
&4
USART3/4
RX, TX,CTS, RTS,
CK as AF
VDDIO1
MSv42183V1
DS12766 Rev 2
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Functional overview
STM32G070CB/KB/RB
3
Functional overview
3.1
Arm® Cortex®-M0+ core with MPU
The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
a simple architecture, easy to learn and program
ultra-low power, energy-efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family
platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32G070CB/KB/RB devices are compatible with Arm
tools and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.
3.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3
Embedded Flash memory
STM32G070CB/KB/RB devices feature 128 Kbytes of embedded Flash memory available
for storing code and data.
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Functional overview
Flexible protections can be configured thanks to option bytes:
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
Level 0: no readout protection
–
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
–
Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.
Table 2. Access status versus readout protection level and execution modes
Area
Protection
level
Debug, boot from RAM or boot
from system memory (loader)
User execution
Read
Write
Erase
Read
Write
Erase
User
memory
1
Yes
Yes
Yes
No
No
No
2
Yes
Yes
Yes
N/A
N/A
N/A
System
memory
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option
bytes
1
Yes
Yes
Yes
Yes
Yes
Yes
2
Yes
No
No
N/A
N/A
N/A
No
No
N/A(1)
N/A
N/A
N/A
Backup
registers
1
Yes
Yes
2
Yes
Yes
(1)
N/A
N/A
1. Erased upon RDP change from Level 1 to Level 0.
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
3.4
single error detection and correction
double error detection
readout of the ECC fail address from the ECC register
Embedded SRAM
STM32G070CB/KB/RB devices have 32 Kbytes of embedded SRAM with parity. Hardware
parity check allows memory data errors to be detected, which contributes to increasing
functional safety of applications.
When the parity protection is not required because the application is not safety-critical, the
parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.
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Functional overview
3.5
STM32G070CB/KB/RB
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
boot from User Flash memory
boot from System memory
boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. The boot loader is located in System memory. It manages the Flash memory
reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I2Cbus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or
PB12/PB13/PB14/PB15.
3.6
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
3.7
Power supply management
3.7.1
Power supply schemes
The STM32G070CB/KB/RB devices require a 2.0 V to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:
VDD = 2.0 to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
VDDA = 2.0 V to 3.6 V
VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to
VDD voltage as it is provided externally through VDD/VDDA pin.
VDDIO1 = VDD
VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage
as it is provided externally through VDD/VDDA pin.
14/93
VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC,
TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not
present. VBAT is provided externally through VBAT pin. When this pin is not available
on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.
VREF+ is the analog peripheral input reference voltage. When VDDA < 2 V, VREF+ must
be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be
grounded when the analog peripherals using VREF+ are not active.
DS12766 Rev 2
STM32G070CB/KB/RB
Functional overview
VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is
internally connected with VDD, and the internal voltage reference buffer must be kept
disabled (refer to datasheets for package pinout description).
VCORE
An embedded linear voltage regulator is used to supply the VCORE internal digital
power. VCORE is the power supply for digital peripherals, SRAM and Flash memory.
The Flash memory is also supplied with VDD.
Figure 2. Power supply overview
VREF+
VREF+
VDDA
VDDA domain
A/D converter
VSSA
VDDIO1 domain
VDDIO1
I/O ring
VDD domain
VSS/VSSA
VDD/VDDA
VSS
Reset block
Temp. sensor
PLL, HSI
Standby circuitry
(Wakeup, IWDG)
VDD
Voltage
regulator
Low-voltage
detector
VCORE domain
Core
SRAM
VCORE
Digital
peripherals
Flash memory
RTC domain
BKP registers
LSE crystal 32.768 kHz osc
RCC BDCR register
RTC and TAMP
VBAT
MSv47920V1
3.7.2
Power supply supervisor
The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes and ensuring proper operation upon power-on and power-down. It maintains the
device in reset when the supply voltage is below VPOR/PDR threshold, without the need for
an external reset circuit.
3.7.3
Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device.
The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power
sleep and Stop modes.
In Standby mode, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.
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Functional overview
3.7.4
STM32G070CB/KB/RB
Low-power modes
By default, the microcontroller is in Run mode after system or power reset. It is up to the
user to select one of the low-power modes described below:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.
Stop 0 and Stop 1 modes
In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are stopped.
The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,
so as to get clock for processing the wakeup event. The main regulator remains active
in Stop 0 mode while it is turned off in Stop 1 mode.
Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The main regulator is switched off to power down VCORE
domain. The low-power regulator is switched off. The PLL, as well as the HSI16 RC
oscillator and the HSE crystal oscillator are also powered down. The RTC can remain
active (Standby mode with RTC, Standby mode without RTC).
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost except for registers in the RTC
domain and standby circuitry.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE
(CSS on LSE).
3.7.5
Reset mode
During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.
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DS12766 Rev 2
STM32G070CB/KB/RB
3.7.6
Functional overview
VBAT operation
The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and
backup registers.
In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for
example, an external battery or an external supercapacitor. Two anti-tamper detection pins
are available.
The RTC domain can also be supplied from VDD/VDDA pin.
By means of a built-in switch, an internal voltage supervisor allows automatic switching of
RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply
voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages
are valid, the RTC domain is supplied from VDD/VDDA pin.
An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is
within a valid range.
Note:
External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT
mode, as in that mode the VDD is not within a valid range.
3.8
Interconnect of peripherals
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Run
Low-power run
Sleep
Low-power sleep
Stop
Table 3. Interconnect of STM32G070CB/KB/RB peripherals
TIMx
Timer synchronization or chaining
Y
Y
-
ADCx
Conversion triggers
Y
Y
-
DMA
Memory-to-memory transfer trigger
Y
Y
-
ADCx
TIM1
Timer triggered by analog watchdog
Y
Y
-
RTC
TIM16
Timer input channel from RTC events
Y
Y
-
All clocks sources (internal
and external)
TIM14,16,17
Clock source used as input channel for
RC measurement and trimming
Y
Y
-
CSS
RAM (parity error)
Flash memory (ECC error)
TIM1,15,16,17
Timer break
Y
Y
-
Interconnect source
TIMx
Interconnect
destination
Interconnect action
DS12766 Rev 2
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28
Functional overview
STM32G070CB/KB/RB
Run
Low-power run
Sleep
Low-power sleep
Stop
Table 3. Interconnect of STM32G070CB/KB/RB peripherals (continued)
Timer break
Y
-
-
TIMx
External trigger
Y
Y
-
ADC
Conversion external trigger
Y
Y
-
Interconnect source
Interconnect
destination
CPU (hard fault)
TIM1,15,16,17
GPIO
3.9
Interconnect action
Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
18/93
System clock source: three different sources can deliver SYSCLK system clock:
–
4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It
can supply clock to system PLL. The HSE can also be configured in bypass mode
for an external clock.
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
–
System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or
HSI16 clocks.
Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–
32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–
32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, ADC) have their
own clock independent of the system clock.
Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
DS12766 Rev 2
STM32G070CB/KB/RB
Functional overview
clock failure can also be detected and generate an interrupt. The CCS feature can be
enabled by software.
Clock output:
–
MCO (microcontroller clock output) provides one of the internal clocks for
external use by the application
–
LSCO (low speed clock output) provides LSI or LSE in all low-power modes
(except in VBAT operation).
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 64 MHz at maximum.
3.10
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.
3.11
Direct memory access controller (DMA)
The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.
With 7 channels, it performs data transfers between memory-mapped peripherals and/or
memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
Single-AHB master
Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers
Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
All DMA channels independently configurable:
–
Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
–
Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
–
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
–
Support of transfers from/to peripherals to/from memory with circular buffer
management
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Functional overview
–
3.12
STM32G070CB/KB/RB
Programmable number of data to be transferred: 0 to 216 - 1
Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.
DMA request multiplexer (DMAMUX)
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.
3.13
Interrupts and events
The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.
3.13.1
Nested vectored interrupt controller (NVIC)
The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
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DS12766 Rev 2
STM32G070CB/KB/RB
Functional overview
Features of the NVIC:
3.13.2
Low-latency interrupt processing
4 priority levels
Handling of a non-maskable interrupt (NMI)
Handling of 32 maskable interrupt lines
Handling of 10 Cortex-M0+ exceptions
Later-arriving higher-priority interrupt processed first
Tail-chaining
Interrupt vector retrieval by hardware
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wakeup from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.
3.14
Analog-to-digital converter (ADC)
A native 12-bit analog-to-digital converter is embedded into STM32G070CB/KB/RB
devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC
has up to 16 external channels and 3 internal channels (temperature sensor, voltage
reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan
mode, automatic conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole VDD supply
range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits (refer to AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
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Functional overview
3.14.1
STM32G070CB/KB/RB
Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.
Table 4. Temperature sensor calibration values
3.14.2
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75A8 - 0x1FFF 75A9
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually
precisely measured for each part by ST during production test and stored in the part’s
engineering bytes. It is accessible in read-only mode.
Table 5. Internal voltage reference calibration values
3.14.3
Calibration value name
Description
Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside
the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a
consequence, the converted digital value is one third the VBAT voltage.
3.15
Timers and watchdogs
The device includes an advanced-control timer, five general-purpose timers, two basic
timers, two low-power timers, two watchdog timers and a SysTick timer. Table 6 compares
features of the advanced-control, general-purpose and basic timers.
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Functional overview
Table 6. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Maximum
operating
frequency
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Advancedcontrol
TIM1
16-bit
Up, down,
up/down
64 MHz
Integer from
1 to 216
Yes
4
3
TIM3
16-bit
Up, down,
up/down
64 MHz
Integer from
1 to 216
Yes
4
-
TIM14
16-bit
Up
64 MHz
Integer from
1 to 216
No
1
-
TIM15
16-bit
Up
64 MHz
Integer from
1 to 216
Yes
2
1
TIM16
TIM17
16-bit
Up
64 MHz
Integer from
1 to 216
Yes
1
1
TIM6
TIM7
16-bit
Up
64 MHz
Integer from
1 to 216
Yes
-
-
Generalpurpose
Basic
3.15.1
Advanced-control timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
input capture
output compare
PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
one-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.15.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
3.15.2
General-purpose timers (TIM3, 14, 15, 16, 17)
There are five synchronizable general-purpose timers embedded in the device (refer to
Table 6 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
TIM3
This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter
and 16-bit prescaler.
It has four independent channels for input capture/output compare, PWM or one-pulse
mode output. It can operate in combination with other general-purpose timers via the
Timer Link feature for synchronization or event chaining. It can generate independent
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Functional overview
STM32G070CB/KB/RB
DMA request and support quadrature encoders. Its counter can be frozen in debug
mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
TIM15, TIM16, TIM17
These are general-purpose timers featuring:
–
16-bit auto-reload upcounter and 16-bit prescaler
–
2 channels and 1 complementary channel for TIM15
–
1 channel and 1 complementary channel for TIM16 and TIM17
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.
3.15.3
Basic timers (TIM6 and TIM7)
These timers can be used as generic 16-bit timebases.
3.15.4
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.
3.15.5
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.
3.15.6
SysTick timer
This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.
Features of SysTick timer:
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24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
DS12766 Rev 2
STM32G070CB/KB/RB
3.16
Functional overview
Real-time clock (RTC), tamper (TAMP) and backup registers
The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of
the silicon die.
The ways of powering the RTC domain are described in Section 3.7.6.
The RTC is an independent BCD timer/counter.
Features of the RTC:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
Programmable alarm
On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with
a master clock
Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be
used to improve the calendar precision
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
Two anti-tamper detection pins with programmable filter
Timestamp feature to save a calendar snapshot, triggered by an event on the
timestamp pin or a tamper event, or by switching to VBAT mode
17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable
resolution and period
Multiple clock sources and references:
–
A 32.768 kHz external crystal (LSE)
–
An external resonator or oscillator (LSE)
–
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
–
The high-speed external clock (HSE) divided by 32
When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When
clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wake the device up from the low-power modes.
The backup registers allow keeping 20 bytes of user application data in the event of VDD
failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by
the system reset, power reset, and upon the device’s wakeup from Standby mode.
3.17
Inter-integrated circuit interface (I2C)
The device embeds two I2C peripherals. Refer to Table 7 for the features.
The I2C-bus interface handles communication between the microcontroller and the serial
I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.
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Functional overview
STM32G070CB/KB/RB
Features of the I2C peripheral:
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Clock stretching
SMBus specification rev 3.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
Command and data acknowledge control
–
Address resolution protocol (ARP) support
–
Host and Device support
–
SMBus alert
–
Timeouts and idle condition detection
PMBus rev 1.3 standard compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent of the PCLK reprogramming
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 7. I2C implementation
I2C features(1)
I2C1
I2C2
Standard mode (up to 100 kbit/s)
X
X
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os
X
X
Programmable analog and digital noise filters
X
X
SMBus/PMBus hardware support
X
-
Independent clock
X
-
Wakeup from Stop mode on address match
X
-
1. X: supported
3.18
Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds universal synchronous/asynchronous receivers/transmitters (USART1,
USART2, USART3, USART4) that communicate at speeds of up to 8 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
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STM32G070CB/KB/RB
Functional overview
half-duplex communication mode. Some can also support SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have
a clock domain independent of the CPU clock, which allows them to wake up the MCU from
Stop mode. The wakeup events from Stop mode are programmable and can be:
start bit detection
any received data frame
a specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 8. USART implementation
USART1
USART2
USART3
USART4
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
X
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
-
LIN mode
X
-
Dual clock domain and wakeup from Stop mode
X
-
Receiver timeout interrupt
X
-
Modbus communication
X
-
Auto baud rate detection
X
-
Driver Enable
X
X
USART modes/features(1)
1. X: supported
3.19
Serial peripheral interface (SPI)
The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
The I2S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.
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Functional overview
STM32G070CB/KB/RB
Table 9. SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
Rx/Tx FIFO
X
X
NSS pulse mode
X
X
I2S mode
X
-
TI mode
X
X
1. X = supported.
3.20
Development support
3.20.1
Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
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DS12766 Rev 2
STM32G070CB/KB/RB
Pinouts, pin description and alternate functions
PD2
PD1
PD0
PC9
51
50
49
PD5
55
52
PD6
56
PD4
PB3
57
PD3
PB4
58
53
PB5
59
54
PB7
PB6
PB8
60
PB9
62
61
PC10
63
Top view
64
Figure 3. STM32G070RxT LQFP64 pinout
PC11
1
48
PC8
PC12
2
47
PA15
PC13
3
46
PA14-BOOT0
PC14-OSC32_IN
4
45
PA13
PC15-OSC32_OUT
5
44
PA12 [PA10]
VBAT
6
43
PA11 [PA9]
VREF+
7
42
PA10
VDD/VDDA
8
41
PD9
LQFP64
28
29
30
31
32
PB2
PB10
PB11
PB12
PB13
PB1
33
27
16
PB0
PB14
PC3
26
34
PC5
15
25
PB15
PC2
PC4
35
24
14
PA7
PA8
PC1
23
36
22
13
PA6
PA9
PC0
PA5
37
21
12
PA4
PC6
NRST
20
38
PA3
11
19
PC7
PF1-OSC_OUT
PA2
PD8
39
18
40
17
9
10
PA1
VSS/VSSA
PF0-OSC_IN
PA0
MSv47927V1
Figure 4. STM32G070CxT LQFP48 pinout
37
38
39
40
41
42
43
44
45
46
1
36
2
35
3
34
4
33
5
32
6
31
LQFP48
7
30
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PC7
PC6
PA9
PA8
PB15
PB14
PB13
24
23
22
21
20
19
25
18
26
12
17
27
11
16
28
10
15
29
9
14
8
13
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VBAT
VREF+
VDD/VDDA
VSS/VSSA
PF0-OSC_IN
PF1-OSC_OUT
NRST
PA0
PA1
47
48
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PD3
PD2
PD1
PD0
PA15
Top view
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
PB12
4
Pinouts, pin description and alternate functions
MSv47928V1
DS12766 Rev 2
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Pinouts, pin description and alternate functions
STM32G070CB/KB/RB
PB5
PB4
PB3
PA15
PA14-BOOT0
27
26
25
PB6
28
PB7
30
29
PB8
31
Top view
32
Figure 5. STM32G070KxT LQFP32 pinout
PB9
1
24
PA13
PC14-OSC32_IN
2
23
PA12 [PA10]
PC15-OSC32_OUT
3
22
PA11 [PA9]
VDD/VDDA
4
21
PA10
VSS/VSSA
5
20
PC6
NRST
6
19
PA9
PA0
7
18
PA8
PA1
8
17
PB2
9
10
11
12
13
14
15
16
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
LQFP32
MSv47929V1
Table 10. Terms and symbols used in Table 11
Column
Pin name
Pin type
I/O structure
Symbol
Definition
Terminal name corresponds to its by-default function at reset, unless otherwise specified in
parenthesis under the pin name.
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
RST
Bidirectional reset pin with embedded weak pull-up resistor
Options for TT or FT I/Os
Note
_f
I/O, Fm+ capable
_a
I/O, with analog switch function
_c
I/O, with specific electrical characteristics
_d
I/O, with specific electrical characteristics
Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions
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Pinouts, pin description and alternate functions
Table 11. Pin assignment and description
LQFP32
LQFP48
LQFP64
(function
upon reset)
Pin type
I/O structure
Note
Pin Number
Alternate
functions
-
-
1
PC11
I/O
FT
-
USART3_RX, USART4_RX,
TIM1_CH4
-
-
-
2
PC12
I/O
FT
-
TIM14_CH1
-
-
1
3
PC13
I/O
FT
(1)(2)
TIM1_BKIN
TAMP_IN1,RTC_TS,
RTC_OUT1,WKUP2
-
2
4
PC14OSC32_IN
(PC14)
I/O
FT
(1)(2)
TIM1_BKIN2
OSC32_IN
2
-
-
PC14OSC32_IN
(PC14)
I/O
FT
(1)(2)
TIM1_BKIN2
OSC32_IN,OSC_IN
3
3
5
PC15OSC32_OUT
(PC15)
I/O
FT
(1)(2)
OSC32_EN, OSC_EN,
TIM15_BKIN
OSC32_OUT
-
4
6
VBAT
S
-
-
-
-
-
5
7
VREF+
S
-
-
-
-
4
6
8
VDD/VDDA
S
-
-
-
-
5
7
9
VSS/VSSA
S
-
-
-
-
-
8
10
PF0-OSC_IN
(PF0)
I/O
FT
-
TIM14_CH1
OSC_IN
-
9
11
PF1OSC_OUT
(PF1)
I/O
FT
-
OSC_EN, TIM15_CH1N
OSC_OUT
6
10 12
NRST
I/O
FT
-
-
NRST
Pin name
Additional
functions
-
-
13
PC0
I/O
FT
-
-
-
-
-
14
PC1
I/O
FT
-
TIM15_CH1-
-
-
-
15
PC2
I/O
FT
-
SPI2_MISO, TIM15_CH2
-
-
-
16
PC3
I/O
FT
-
SPI2_MOSI
-
7
11
17
PA0
I/O
FT_a
-
SPI2_SCK, USART2_CTS,
USART4_TX
ADC_IN0,
TAMP_IN2,WKUP1
DS12766 Rev 2
31/93
35
Pinouts, pin description and alternate functions
STM32G070CB/KB/RB
Table 11. Pin assignment and description (continued)
12 18
PA1
I/O
FT_a
-
9
13 19
PA2
I/O
FT_a
-
SPI1_MOSI/I2S1_SD,
USART2_TX, TIM15_CH1
ADC_IN2,
WKUP4,LSCO
10 14 20
PA3
I/O
FT_a
-
SPI2_MISO, USART2_RX,
TIM15_CH2, EVENTOUT
ADC_IN3
PA4
I/O
TT_a
-
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
EVENTOUT
ADC_IN4, RTC_OUT2
PA4
I/O
TT_a
-
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
EVENTOUT
ADC_IN4, TAMP_IN1,
RTC_TS,
RTC_OUT1,WKUP2
12 16 22
PA5
I/O
TT_a
-
SPI1_SCK/I2S1_CK,
USART3_TX, EVENTOUT
ADC_IN5
13 17 23
PA6
I/O
FT_a
-
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
USART3_CTS, TIM16_CH1
ADC_IN6
14 18 24
PA7
I/O
FT_a
-
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM1_CH1N,
TIM14_CH1, TIM17_CH1
ADC_IN7
-
11
LQFP64
8
SPI1_SCK/I2S1_CK,
USART2_RTS_DE_CK,
USART4_RX, TIM15_CH1N,
I2C1_SMBA, EVENTOUT
LQFP48
Alternate
functions
LQFP32
Note
I/O structure
Pin name
Pin type
Pin Number
15 21
-
-
(function
upon reset)
Additional
functions
ADC_IN1
-
-
25
PC4
I/O
FT_a
-
USART3_TX, USART1_TX
ADC_IN17
-
-
26
PC5
I/O
FT_a
-
USART3_RX, USART1_RX
ADC_IN18, WKUP5
15 19 27
PB0
I/O
FT_a
(3)
SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N,
USART3_RX
ADC_IN8
ADC_IN9
16 20 28
PB1
I/O
FT_a
-
TIM14_CH1, TIM3_CH4,
TIM1_CH3N,
USART3_RTS_DE_CK,
EVENTOUT
17 21 29
PB2
I/O
FT_a
-
SPI2_MISO, USART3_TX,
EVENTOUT
ADC_IN10
PB10
I/O
FT_fa
-
USART3_TX, SPI2_SCK,
I2C2_SCL
ADC_IN11
-
32/93
22 30
DS12766 Rev 2
STM32G070CB/KB/RB
Pinouts, pin description and alternate functions
Table 11. Pin assignment and description (continued)
Pin type
I/O structure
Note
Pin Number
Alternate
functions
-
23 31
PB11
I/O
FT_fa
-
SPI2_MOSI, USART3_RX,
I2C2_SDA
ADC_IN15
-
24 32
PB12
I/O
FT_a
-
SPI2_NSS, TIM1_BKIN,
TIM15_BKIN, EVENTOUT
ADC_IN16
-
25 33
PB13
I/O
FT_f
-
SPI2_SCK, TIM1_CH1N,
USART3_CTS, TIM15_CH1N,
I2C2_SCL, EVENTOUT
-
-
LQFP64
LQFP48
LQFP32
Pin name
(function
upon reset)
Additional
functions
-
26 34
PB14
I/O
FT_f
-
SPI2_MISO, TIM1_CH2N,
USART3_RTS_DE_CK,
TIM15_CH1, I2C2_SDA,
EVENTOUT
-
27 35
PB15
I/O
FT_c
(3)
SPI2_MOSI, TIM1_CH3N,
TIM15_CH1N, TIM15_CH2,
EVENTOUT
RTC_REFIN
18 28 36
PA8
I/O
FT_c
(3)
MCO, SPI2_NSS, TIM1_CH1,
EVENTOUT
-
19 29 37
PA9
I/O
FT_fd
(3)
MCO, USART1_TX, TIM1_CH2,
SPI2_MISO, TIM15_BKIN,
I2C1_SCL, EVENTOUT
-
20 30 38
PC6
I/O
FT
(3)
TIM3_CH1
-
PC7
I/O
FT
-
TIM3_CH2
-
-
31 39
-
-
40
PD8
I/O
FT
-
USART3_TX,
SPI1_SCK/I2S1_CK
-
-
-
41
PD9
I/O
FT
-
USART3_RX,
SPI1_NSS/I2S1_WS,
TIM1_BKIN2
-
21 32 42
PA10
I/O
FT_fd
(3)
SPI2_MOSI, USART1_RX,
TIM1_CH3, TIM17_BKIN,
I2C1_SDA, EVENTOUT
-
22 33 43
PA11
[PA9](4)
I/O
FT_f
(3)
SPI1_MISO/I2S1_MCK,
USART1_CTS, TIM1_CH4,
TIM1_BKIN2, I2C2_SCL
-
23 34 44
PA12
[PA10](4)
FT_f
(3)
SPI1_MOSI/I2S1_SD,
USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN,
I2C2_SDA
-
I/O
DS12766 Rev 2
33/93
35
Pinouts, pin description and alternate functions
STM32G070CB/KB/RB
Table 11. Pin assignment and description (continued)
Note
Alternate
functions
Additional
functions
FT
(5)
SWDIO, IR_OUT, EVENTOUT
-
(5)
SWCLK, USART2_TX,
EVENTOUT
BOOT0
-
I/O
25 36 46
PA14-BOOT0
I/O
FT
LQFP64
PA13
LQFP48
24 35 45
LQFP32
(function
upon reset)
Pin type
Pin name
I/O structure
Pin Number
26 37 47
PA15
I/O
FT
-
SPI1_NSS/I2S1_WS,
USART2_RX,
USART4_RTS_DE_CK,
USART3_RTS_DE_CK,
EVENTOUT
-
-
48
PC8
I/O
FT
-
TIM3_CH3, TIM1_CH1
-
-
-
49
PC9
I/O
FT
-
I2S_CKIN, TIM3_CH4,
TIM1_CH2
-
-
38 50
PD0
I/O
FT_c
(3)
EVENTOUT, SPI2_NSS,
TIM16_CH1
-
-
39 51
PD1
I/O
FT_d
(3)
EVENTOUT, SPI2_SCK,
TIM17_CH1
-
-
40 52
PD2
I/O
FT_c
(3)
USART3_RTS_DE_CK,
TIM3_ETR, TIM1_CH1N
-
-
41 53
PD3
I/O
FT_d
(3)
USART2_CTS, SPI2_MISO,
TIM1_CH2N
-
-
-
54
PD4
I/O
FT
-
USART2_RTS_DE_CK,
SPI2_MOSI, TIM1_CH3N
-
-
-
55
PD5
I/O
FT
-
USART2_TX,
SPI1_MISO/I2S1_MCK,
TIM1_BKIN
-
-
-
56
PD6
I/O
FT
-
USART2_RX,
SPI1_MOSI/I2S1_SD
-
27 42 57
PB3
I/O
FT_a
-
SPI1_SCK/I2S1_CK, TIM1_CH2,
USART1_RTS_DE_CK,
EVENTOUT
-
28 43 58
PB4
I/O
FT_a
-
SPI1_MISO/I2S1_MCK,
TIM3_CH1, USART1_CTS,
TIM17_BKIN, EVENTOUT
-
29 44 59
PB5
I/O
FT
-
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM16_BKIN,
I2C1_SMBA
WKUP6
34/93
DS12766 Rev 2
STM32G070CB/KB/RB
Pinouts, pin description and alternate functions
Table 11. Pin assignment and description (continued)
I/O structure
Note
Pin Number
Alternate
functions
Additional
functions
FT_fa
-
USART1_TX, TIM1_CH3,
TIM16_CH1N, SPI2_MISO,
I2C1_SCL, EVENTOUT
-
FT_fa
-
USART1_RX, SPI2_MOSI,
TIM17_CH1N, USART4_CTS,
I2C1_SDA, EVENTOUT
-
I/O
FT_f
-
SPI2_SCK, TIM16_CH1,
USART3_TX, TIM15_BKIN,
I2C1_SCL, EVENTOUT
-
PB9
I/O
FT_f
-
IR_OUT, TIM17_CH1,
USART3_RX, SPI2_NSS,
I2C1_SDA, EVENTOUT
-
PC10
I/O
FT
-
USART3_TX, USART4_TX,
TIM1_CH3
-
I/O
31 46 61
PB7
I/O
32 47 62
PB8
1
-
LQFP64
PB6
LQFP48
30 45 60
LQFP32
(function
upon reset)
Pin type
Pin name
48 63
-
64
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of
current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers as they are not reset by the system reset. For details on how to manage these GPIOs,
refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
3. Upon reset, a pull-down resistor might be present on PA8, PD0, or PD2, depending on the voltage level on PB0,
PA9, PC6, PA10, PD1, and PD3. In order to disable this resistor, strobe the UCPDx_STROBE bit of the
SYSCFG_CFGR1 register during start-up sequence.
4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the
internal pull-down on PA14 pin are activated.
DS12766 Rev 2
35/93
35
36/93
Table 12. Port A alternate function mapping
DS12766 Rev 2
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
SPI2_SCK
USART2_CTS
-
-
USART4_TX
-
-
-
PA1
SPI1_SCK/
I2S1_CK
USART2_RTS
_DE_CK
-
-
USART4_RX
TIM15_CH1N
I2C1_SMBA
EVENTOUT
PA2
SPI1_MOSI/
I2S1_SD
USART2_TX
-
-
-
TIM15_CH1
-
-
PA3
SPI2_MISO
USART2_RX
-
-
-
TIM15_CH2
-
EVENTOUT
PA4
SPI1_NSS/
I2S1_WS
SPI2_MOSI
-
-
TIM14_CH1
-
-
EVENTOUT
PA5
SPI1_SCK/
I2S1_CK
-
-
-
USART3_TX
-
-
EVENTOUT
PA6
SPI1_MISO/
I2S1_MCK
TIM3_CH1
TIM1_BKIN
-
USART3_CTS
TIM16_CH1
-
-
PA7
SPI1_MOSI/
I2S1_SD
TIM3_CH2
TIM1_CH1N
TIM14_CH1
TIM17_CH1
-
-
PA8
MCO
SPI2_NSS
TIM1_CH1
-
-
-
-
EVENTOUT
PA9
MCO
USART1_TX
TIM1_CH2
-
SPI2_MISO
TIM15_BKIN
I2C1_SCL
EVENTOUT
PA10
SPI2_MOSI
USART1_RX
TIM1_CH3
-
-
TIM17_BKIN
I2C1_SDA
EVENTOUT
PA11
SPI1_MISO/
I2S1_MCK
USART1_CTS
TIM1_CH4
-
-
TIM1_BKIN2
I2C2_SCL
-
PA12
SPI1_MOSI/
I2S1_SD
USART1_RTS
_DE_CK
TIM1_ETR
-
-
I2S_CKIN
I2C2_SDA
-
PA13
SWDIO
IR_OUT
-
-
-
-
-
EVENTOUT
PA14
SWCLK
USART2_TX
-
-
-
-
-
EVENTOUT
PA15
SPI1_NSS/
I2S1_WS
USART2_RX
-
-
USART4_RTS
_DE_CK
USART3_RTS
_DE_CK
-
EVENTOUT
-
STM32G070CB/KB/RB
Port
DS12766 Rev 2
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PB0
SPI1_NSS/
I2S1_WS
TIM3_CH3
TIM1_CH2N
-
USART3_RX
-
-
-
PB1
TIM14_CH1
TIM3_CH4
TIM1_CH3N
-
USART3_RTS
_DE_CK
-
-
EVENTOUT
PB2
-
SPI2_MISO
-
-
USART3_TX
-
-
EVENTOUT
PB3
SPI1_SCK/
I2S1_CK
TIM1_CH2
-
-
USART1_RTS
_DE_CK
-
-
EVENTOUT
PB4
SPI1_MISO/
I2S1_MCK
TIM3_CH1
-
-
USART1_CTS
TIM17_BKIN
-
EVENTOUT
PB5
SPI1_MOSI/
I2S1_SD
TIM3_CH2
TIM16_BKIN
-
-
-
I2C1_SMBA
-
PB6
USART1_TX
TIM1_CH3
TIM16_CH1N
-
SPI2_MISO
-
I2C1_SCL
EVENTOUT
PB7
USART1_RX
SPI2_MOSI
TIM17_CH1N
-
USART4_CTS
-
I2C1_SDA
EVENTOUT
PB8
-
SPI2_SCK
TIM16_CH1
-
USART3_TX
TIM15_BKIN
I2C1_SCL
EVENTOUT
PB9
IR_OUT
-
TIM17_CH1
-
USART3_RX
SPI2_NSS
I2C1_SDA
EVENTOUT
PB10
-
-
-
-
USART3_TX
SPI2_SCK
I2C2_SCL
-
PB11
SPI2_MOSI
-
-
-
USART3_RX
-
I2C2_SDA
-
PB12
SPI2_NSS
-
TIM1_BKIN
-
-
TIM15_BKIN
-
EVENTOUT
PB13
SPI2_SCK
-
TIM1_CH1N
-
USART3_CTS
TIM15_CH1N
I2C2_SCL
EVENTOUT
PB14
SPI2_MISO
-
TIM1_CH2N
-
USART3_RTS
_DE_CK
TIM15_CH1
I2C2_SDA
EVENTOUT
PB15
SPI2_MOSI
-
TIM1_CH3N
-
TIM15_CH1N
TIM15_CH2
-
EVENTOUT
STM32G070CB/KB/RB
Table 13. Port B alternate function mapping
37/93
38/93
Table 14. Port C alternate function mapping
DS12766 Rev 2
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PC0
-
-
-
-
-
-
-
-
PC1
-
-
TIM15_CH1
-
-
-
-
-
PC2
-
SPI2_MISO
TIM15_CH2
-
-
-
-
-
PC3
-
SPI2_MOSI
-
-
-
-
-
-
PC4
USART3_TX
USART1_TX
-
-
-
-
-
-
PC5
USART3_RX
USART1_RX
-
-
-
-
-
-
PC6
-
TIM3_CH1
-
-
-
-
-
-
PC7
-
TIM3_CH2
-
-
-
-
-
-
PC8
-
TIM3_CH3
TIM1_CH1
-
-
-
-
-
PC9
I2S_CKIN
TIM3_CH4
TIM1_CH2
-
-
-
-
-
PC10
USART3_TX
USART4_TX
TIM1_CH3
-
-
-
-
-
PC11
USART3_RX
USART4_RX
TIM1_CH4
-
-
-
-
-
PC12
-
-
TIM14_CH1
-
-
-
-
-
PC13
-
-
TIM1_BKIN
-
-
-
-
-
PC14
-
-
TIM1_BKIN2
-
-
-
-
-
PC15
OSC32_EN
OSC_EN
TIM15_BKIN
-
-
-
-
-
STM32G070CB/KB/RB
Table 15. Port D alternate function mapping
DS12766 Rev 2
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PD0
EVENTOUT
SPI2_NSS
TIM16_CH1
-
-
-
-
-
PD1
EVENTOUT
SPI2_SCK
TIM17_CH1
-
-
-
-
-
PD2
USART3_RTS
_DE_CK
TIM3_ETR
TIM1_CH1N
-
-
-
-
-
PD3
USART2_CTS
SPI2_MISO
TIM1_CH2N
-
-
-
-
-
PD4
USART2_RTS
_DE_CK
SPI2_MOSI
TIM1_CH3N
-
-
-
-
-
PD5
USART2_TX
SPI1_MISO/
I2S1_MCK
TIM1_BKIN
-
-
-
-
-
PD6
USART2_RX
SPI1_MOSI/
I2S1_SD
-
-
-
-
-
-
PD8
USART3_TX
SPI1_SCK/
I2S1_CK
-
-
-
-
-
-
PD9
USART3_RX
SPI1_NSS/
I2S1_WS
TIM1_BKIN2
-
-
-
-
-
Table 16. Port F alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PF0
-
-
TIM14_CH1
-
-
-
-
-
PF1
OSC_EN
-
TIM15_CH1N
-
-
-
-
-
STM32G070CB/KB/RB
*
39/93
Electrical characteristics
STM32G070CB/KB/RB
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
Parameter values defined at temperatures or in temperature ranges out of the ordering
information scope are to be ignored.
Packages used for characterizing certain electrical parameters may differ from the
commercial packages as per the ordering information.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 6. Pin loading conditions
Figure 7. Pin input voltage
MCU pin
MCU pin
C = 50 pF
40/93
VIN
DS12766 Rev 2
STM32G070CB/KB/RB
5.1.6
Electrical characteristics
Power supply scheme
Figure 8. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC and
backup registers)
1.55 V to 3.6 V
Power
switch
VDD
VCORE
VDD/VDDA
VDD
Regulator
OUT
1 x 100 nF
+ 1 x 4.7 μF
GPIOs
IN
Level shifter
VDDIO1
IO
logic
Kernel logic
(CPU, digital and
memories)
VSS
VDDA
VREF
VREF+
VREF+
VREF-
100 nF
ADC
VSSA
VSS/VSSA
MSv47984V1
Caution:
Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
5.1.7
Current consumption measurement
Figure 9. Current consumption measurement scheme
IDDVBAT
VBAT
VDD
(VDDA)
IDD
VBAT
VDD/VDDA
MSv47901V1
DS12766 Rev 2
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80
Electrical characteristics
5.2
STM32G070CB/KB/RB
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 17, Table 18 and Table 19
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
All voltages are defined with respect to VSS.
Table 17. Voltage characteristics
Symbol
Ratings
Min
Max
VDD
External supply voltage
- 0.3
4.0
VBAT
External supply voltage on VBAT pin
- 0.3
4.0
VREF+
External voltage on VREF+ pin
- 0.3
Min(VDD + 0.4, 4.0)
Input voltage on FT_xx pins except FT_c
- 0.3
VDD + 4.0(2)
Input voltage on FT_c pins
- 0.3
5.5
Input voltage on any other pin
- 0.3
4.0
VIN(1)
Unit
V
1. Refer to Table 18 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
Table 18. Current characteristics
Symbol
Ratings
Max
IVDD/VDDA
Current into VDD/VDDA power pin (source)(1)
100
IVSS/VSSA
Current out of VSS/VSSA ground pin (sink)(1)
100
Output current sunk by any I/O and control pin except FT_f
15
Output current sunk by any FT_f pin
20
Output current sourced by any I/O and control pin
15
Total output current sunk by sum of all I/Os and control pins
80
Total output current sourced by sum of all I/Os and control pins
80
IIO(PIN)
∑IIO(PIN)
IINJ(PIN)(2)
∑|IINJ(PIN)|
Injected current on a FT_xx pin
-5 / NA(3)
Injected current on a TT_a pin(4)
-5 / 0
Total injected current (sum of all I/Os and control pins)(5)
Unit
25
1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage values.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. On these I/Os, any current injection disturbs the analog performances of the device.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
42/93
DS12766 Rev 2
mA
STM32G070CB/KB/RB
Electrical characteristics
Table 19. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Value
Unit
–65 to +150
°C
150
°C
Table 20. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
64
fPCLK
Internal APB clock frequency
-
0
64
-
2.0(1)
3.6
-
1.55
3.6
VDD/DDA Supply voltage
VBAT
Backup operating voltage
Unit
MHz
V
V
5.5)(2)
VIN
I/O input voltage
-
-0.3
TA
Ambient temperature(3)
-
-40
85
°C
TJ
Junction temperature
-
-40
105
°C
Min(VDD + 3.6,
V
1. When RESET is released functionality is guaranteed down to VPDR min.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided
that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.4: Thermal characteristics.
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 21 are derived from tests performed under the ambient
temperature condition summarized in Table 20.
Table 21. Operating conditions at power-up / power-down
Symbol
tVDD
5.3.3
Parameter
VDD slew rate
Conditions
Min
Max
VDD rising
-
∞
VDD falling
10
∞
Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under the ambient
temperature conditions summarized in Table 20.
DS12766 Rev 2
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80
Electrical characteristics
STM32G070CB/KB/RB
Table 22. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
tRSTTEMPO(2)
POR temporization when VDD crosses VPOR
VDD rising
-
250
400
μs
VPOR(2)
Power-on reset threshold
-
2.06
2.10
2.14
V
VPDR(2)
Power-down reset threshold
-
1.96
2.00
2.04
V
Hysteresis in
continuous
mode
-
20
-
Hysteresis in
other mode
-
Vhyst_POR_PDR
Hysteresis of VPOR and VPDR
mV
30
-
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed by design.
5.3.4
Embedded voltage reference
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.
Table 23. Embedded internal voltage reference
Symbol
VREFINT
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 105°C
1.182
1.212
1.232
V
tS_vrefint (1)
ADC sampling time when reading
the internal reference voltage
-
4(2)
-
-
µs
tstart_vrefint
Start time of reference voltage
buffer when ADC is enable
-
-
8
12(2)
µs
IDD(VREFINTBUF)
VREFINT buffer consumption from
VDD when converted by ADC
-
-
12.5
20(2)
µA
∆VREFINT
Internal reference voltage spread
over the temperature range
VDD = 3 V
-
5
7.5(2)
mV
-
-
30
50(2)
ppm/°C
300
1000(2)
ppm
-
250
1200(2)
ppm/V
24
25
26
49
50
51
74
75
76
TCoeff_vrefint
ACoeff
VDDCoeff
Temperature coefficient
Long term stability
Voltage coefficient
VREFINT_DIV1
1/4 reference voltage
VREFINT_DIV2
1/2 reference voltage
VREFINT_DIV3
3/4 reference voltage
1000 hours, T = 25 °C
3.0 V < VDD < 3.6 V
-
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
44/93
DS12766 Rev 2
-
%
VREFINT
STM32G070CB/KB/RB
Electrical characteristics
Figure 10. VREFINT vs. temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40
-20
0
20
40
Mean
60
Min
80
100
120
°C
Max
MSv40169V1
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 9: Current consumption
measurement scheme.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0454 reference manual).
When the peripherals are enabled fPCLK = fHCLK
For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
Unless otherwise stated, values given in Table 24 through Table 30 are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions.
DS12766 Rev 2
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80
Electrical characteristics
STM32G070CB/KB/RB
Table 24. Current consumption in Run and Low-power run modes
at different die temperatures
Conditions
Symbol
Parameter
General
25°C
85°C
64 MHz
6.9
7.0
8.0
8.4
56 MHz
6.1
6.3
7.1
7.6
5.5
5.6
6.2
6.8
3.9
4.0
4.8
5.2
24 MHz
3.1
3.2
3.7
4.3
16 MHz
2.0
2.1
2.5
3.0
64 MHz
6.6
6.8
7.6
7.9
56 MHz
5.8
6.1
6.7
7.0
5.2
5.3
6.0
6.2
IDD(Run)
3.6
3.7
4.2
4.6
24 MHz
2.9
3.0
3.4
3.7
16 MHz
1.9
1.9
2.3
2.5
1.5
1.7
2.0
2.4
0.9
1.0
1.4
1.6
2 MHz
0.3
0.3
0.6
1.0
16 MHz
1.5
1.5
1.9
2.2
0.8
0.9
1.3
1.4
0.4
0.6
0.8
1.1
2 MHz
0.3
0.3
0.6
1.0
2 MHz
242
281
636
954
116
171
606
924
74
116
558
840
125 kHz
29
73
540
624
32 kHz
19
62
450
570
2 MHz
219
254
582
840
1 MHz
105
154
516
792
67
105
438
750
125 kHz
26
65
402
528
32 kHz
17
61
390
426
32 MHz
48 MHz
Supply
current in Run
mode
32 MHz
Flash
memory
SRAM
16 MHz
Range 2;
PLL enabled;
fHCLK = fHSI bypass
(≤16 MHz),
fHCLK = fPLLRCLK
(>16 MHz);
(3)
8 MHz
8 MHz
4 MHz
Flash
memory
SRAM
1 MHz
500 kHz
IDD(LPRun)
Supply
current in
Low-power
run mode
PLL disabled;
fHCLK = fHSE bypass
(> 32 kHz),
fHCLK = fLSE bypass
(= 32 kHz);
(3)
Unit
85°C
48 MHz
(3)
Fetch
from(2)
25°C
fHCLK
Range 1;
PLL enabled;
fHCLK = fHSI bypass
(≤16 MHz),
fHCLK = fPLLRCLK
(>16 MHz);
Max(1)
Typ
500 kHz
Flash
memory
SRAM
1. Based on characterization results, not tested in production.
2. Prefetch and cache enabled when fetching from Flash
3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled, cache enabled,
prefetch disabled for code and data fetch from Flash and enabled from SRAM
46/93
DS12766 Rev 2
mA
µA
STM32G070CB/KB/RB
Electrical characteristics
Table 25. Current consumption in Sleep and Low-power sleep modes
Conditions
Symbol
Parameter
IDD(Sleep)
Unit
Voltage
scaling
General
Flash memory enabled;
fHCLK = fHSE bypass
Supply
(≤16 MHz; PLL disabled),
current in
f
=f
Sleep mode HCLK PLLRCLK
(>16 MHz; PLL enabled);
All peripherals disabled
IDD(LPSleep)
25°C 85°C 25°C 85°C
fHCLK
Range 1
Range 2
Supply
current in
Low-power
sleep mode
Max(1)
Typ
Flash memory disabled;
PLL disabled;
fHCLK = fHSE bypass (> 32 kHz),
fHCLK = fLSE bypass (= 32 kHz);
All peripherals disabled
64 MHz
2.0
2.1
2.2
2.5
56 MHz
1.8
1.9
2.0
2.3
48 MHz
1.5
1.7
1.9
2.0
32 MHz
1.1
1.2
1.4
1.6
24 MHz
0.9
1.0
1.2
1.3
16 MHz
0.6
0.7
0.7
0.8
16 MHz
0.4
0.6
0.6
0.7
8 MHz
0.3
0.3
0.4
0.6
2 MHz
0.1
0.2
0.2
0.5
2 MHz
65
108
180
432
1 MHz
36
83
156
396
500 kHz
27
70
150
300
125 kHz
17
61
132
282
32 kHz
15
58
132
270
mA
µA
1. Based on characterization results, not tested in production.
Table 26. Current consumption in Stop 0 mode
Conditions
Symbol
IDD(Stop 0)
Max(1)
Typ
Parameter
Supply current
in Stop 0
mode
Unit
VDD
25 °C
85 °C
25 °C
85 °C
2.4 V
110
160
150
264
3V
110
160
150
288
3.6 V
116
165
156
300
µA
1. Based on characterization results, not tested in production.
Table 27. Current consumption in Stop 1 mode
Conditions(1)
Symbol
Parameter
Unit
RTC
Disabled
IDD(Stop 1)
Max(2)
Typ
Supply current
in Stop 1 mode
Enabled
(clocked by
LSE bypass)
VDD
25 °C
85 °C
25 °C
85 °C
2.4 V
3.6
35
12
144
3V
3.7
36
18
162
3.6 V
4.2
36
22
168
2.4 V
4.1
35
13
144
3V
4.4
36
19
168
3.6 V
4.8
37
24
174
DS12766 Rev 2
µA
47/93
80
Electrical characteristics
STM32G070CB/KB/RB
1. Flash memory not powered.
2. Based on characterization results, not tested in production.
Table 28. Current consumption in Standby mode
Symbol
Conditions
Parameter
General
RTC disabled
IDD(Standby)
Supply current in
Standby mode
RTC enabled,
clocked by LSI
Max(1)
Typ
VDD
25 °C
85 °C
25 °C
85 °C
2.4 V
1.0
2.2
2.7
14
3.0 V
1.2
2.6
3.5
17
3.6 V
1.4
3.2
4.1
19
2.4 V
1.5
2.8
3.5
17
3.0 V
1.8
3.3
4.6
21
3.6 V
2.2
4.1
6.4
25
Unit
µA
1. Based on characterization results, not tested in production.
Table 29. Current consumption in VBAT mode
Symbol
IDD_VBAT
Conditions
Parameter
Supply current in
VBAT mode
Typ
RTC
VBAT
25 °C
85 °C
Enabled, clocked by
LSE bypass at
32.768 kHz
2.4 V
286
391
3.0 V
402
523
3.6 V
556
721
Enabled, clocked by
LSE crystal at
32.768 kHz
2.4 V
407
528
3.0 V
517
660
3.6 V
660
897
Unit
nA
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 47: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
48/93
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 30: Current consumption of peripherals, the I/Os used by an application also
contribute to the current consumption. When an I/O pin switches, it uses the current from
the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive
load (internal or external) connected to the pin:
I SW = V DDIO1 f SW C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIO1 is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
when the peripheral is clocked on
–
when the peripheral is clocked off
Ambient operating temperature and supply voltage conditions summarized in Table 17:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in the
following table. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 30. Current consumption of peripherals
Consumption in µA/MHz
Peripheral
Bus
Range 1
Range 2
Low-power run
and sleep
IOPORT Bus
IOPORT
1.0
0.7
0.5
GPIOA
IOPORT
3.4
2.8
3.0
GPIOB
IOPORT
3.1
2.6
2.5
GPIOC
IOPORT
2.9
2.5
3.0
GPIOD
IOPORT
1.8
1.5
1.5
GPIOF
IOPORT
0.7
0.6
1.0
Bus matrix
AHB
3.2
2.2
2.8
All AHB Peripherals
AHB
15.0
12.5
14.0
DS12766 Rev 2
49/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 30. Current consumption of peripherals (continued)
Consumption in µA/MHz
Peripheral
Bus
Range 1
Range 2
Low-power run
and sleep
DMA1/DMAMUX
AHB
4.7
3.8
4.5
CRC
AHB
0.5
0.4
0.5
FLASH
AHB
4.1
3.5
4.0
All APB peripherals
APB
46.5
47.5
48.0
APB
0.2
0.2
0.1
PWR
APB
0.4
0.3
0.5
SYSCFG
APB
0.4
0.4
0.3
WWDG
APB
0.4
0.3
0.5
TIM1
APB
7.3
6.1
6.5
TIM3
APB
3.6
3.0
2.5
TIM6
APB
0.7
0.6
0.5
TIM7
APB
0.7
0.7
1.0
TIM14
APB
1.5
1.2
1.5
TIM15
APB
4.0
3.3
3.0
TIM16
APB
2.3
2.0
2.0
TIM17
APB
0.7
0.7
0.5
I2C1
APB
3.8
3.1
3.5
I2C2
APB
0.7
0.6
1.0
AHB to APB
bridge(1)
SPI2
APB
1.5
1.2
1.0
USART1
APB
7.2
6.0
6.5
USART2
APB
7.2
6.0
6.0
USART3
APB
2.0
1.7
2.0
USART4
APB
2.0
1.7
2.0
ADC
APB
2.0
1.7
2.0
1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 31 are the latency between the event and the execution of
the first user instruction.
50/93
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Table 31. Low-power mode wakeup times(1)
Symbol
Parameter
Conditions
Typ
Max
tWUSLEEP
Wakeup time from
Sleep to Run
mode
-
11
11
Wakeup time from Transiting to Low-power-run-mode execution in Flash
tWULPSLEEP Low-power sleep memory not powered in Low-power sleep mode;
mode
HCLK = HSI16 / 8 = 2 MHz
tWUSTOP0
Transiting to Run-mode execution in Flash memory not
powered in Stop 0 mode;
HCLK = HSI16 = 16 MHz;
Wakeup time from Regulator in Range 1 or Range 2
Stop 0
Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 0 mode;
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
Transiting to Run-mode execution in Flash memory not
powered in Stop 1 mode;
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
tWUSTOP1
Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 1 mode;
HCLK = HSI16 = 16 MHz;
Wakeup time from Regulator in Range 1 or Range 2
Stop 1
Transiting to Low-power-run-mode execution in Flash
memory not powered in Stop 1 mode;
HCLK = HSI16/8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
Transiting to Low-power-run-mode execution in SRAM or
in Flash memory powered in Stop 1 mode;
HCLK = HSI16 / 8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
tWUSTBY
tWULPRUN
Transiting to Run mode;
Wakeup time from
HCLK = HSI16 = 16 MHz;
Standby mode
Regulator in Range 1
Wakeup time from Transiting to Run mode;
Low-power run
HSISYS = HSI16/8 = 2 MHz
mode(2)
Unit
CPU
cycles
11
14
5.6
6
µs
2
2.4
9.0
11.2
5
7.5
µs
22
25.3
18
23.5
14.5
30
µs
5
7
µs
1. Based on characterization results, not tested in production.
2. Time until REGLPF flag is cleared in PWR_SR2.
DS12766 Rev 2
51/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 32. Regulator mode transition times(1)
Symbol
tVOST
Parameter
Conditions
Transition times between regulator
Range 1 and Range 2(2)
HSISYS = HSI16
Typ
Max
Unit
20
40
µs
1. Based on characterization results, not tested in production.
2. Time until VOSF flag is cleared in PWR_SR2.
5.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 11 for recommended clock input waveform.
Table 33. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source frequency
Conditions
Min
Typ
Max
Voltage scaling
Range 1
-
8
48
Voltage scaling
Range 2
-
8
26
Unit
MHz
VHSEH
OSC_IN input pin high level voltage
-
0.7 VDDIO1
-
VDDIO1
VHSEL
OSC_IN input pin low level voltage
-
VSS
-
0.3 VDDIO1
Voltage scaling
Range 1
7
-
-
Voltage scaling
Range 2
18
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
V
ns
1. Guaranteed by design.
Figure 11. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tw(HSEL)
t
THSE
MS19214V2
52/93
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 12 for recommended clock input waveform.
Table 34. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User external clock source frequency
-
-
32.768
1000
VLSEH
OSC32_IN input pin high level voltage
-
0.7 VDDIO1
-
VDDIO1
VLSEL
OSC32_IN input pin low level voltage
-
VSS
-
0.3 VDDIO1
-
250
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
V
ns
1. Guaranteed by design.
Figure 12. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
VLSEL
10%
tr(LSE)
t
tf(LSE)
tw(LSEL)
TLSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 35. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 35. HSE oscillator characteristics(1)
Symbol
fOSC_IN
RF
Conditions(2)
Min
Typ
Max
Unit
Oscillator frequency
-
4
8
48
MHz
Feedback resistor
-
-
200
-
kΩ
Parameter
DS12766 Rev 2
53/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 35. HSE oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions(2)
Min
Typ
Max
-
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
0.44
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
-
0.45
-
VDD = 3 V,
Rm = 30 Ω,
CL = 5 pF@48 MHz
-
0.68
-
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
-
0.94
-
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
-
1.77
-
Maximum critical crystal
transconductance
Startup
-
-
1.5
mA/V
Startup time
VDD is stabilized
-
2
-
ms
During startup
IDD(HSE)
Gm
tSU(HSE)(4)
HSE current consumption
(3)
Unit
mA
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
54/93
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Figure 13. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
8 MHz
resonator
CL2
REXT (1)
fHSE
RF
Bias
controlled
gain
OSC_OUT
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 36. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 36. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
IDD(LSE)
Parameter
LSE current consumption
Maximum critical crystal
Gmcritmax
gm
tSU(LSE)(3) Startup time
Conditions(2)
Min
Typ
Max
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
315
-
LSEDRV[1:0] = 10
Medium high drive capability
-
500
-
LSEDRV[1:0] = 11
High drive capability
-
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
-
-
0.75
LSEDRV[1:0] = 10
Medium high drive capability
-
-
1.7
LSEDRV[1:0] = 11
High drive capability
-
-
2.7
VDD is stabilized
-
2
-
Unit
nA
µA/V
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
DS12766 Rev 2
55/93
80
Electrical characteristics
3.
STM32G070CB/KB/RB
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 14. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
programmable
amplifier
32.768 kHz
resonator
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
5.3.8
Internal clock source characteristics
The parameters given in Table 37 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 37. HSI16 oscillator characteristics(1)
Symbol
fHSI16
Parameter
Conditions
Min
Typ
Max
Unit
15.88
-
16.08
MHz
HSI16 Frequency
VDD=3.0 V, TA=30 °C
∆Temp(HSI16)
HSI16 oscillator frequency drift over
temperature
TA= 0 to 85 °C
-1
-
1
%
TA= -40 to 85 °C
-2
-
1.5
%
∆VDD(HSI16)
HSI16 oscillator frequency drift over
VDD
VDD=VDD(min) to 3.6 V
-0.1
-
0.05
%
From code 127 to 128
-8
-6
-4
-5.8
-3.8
-1.8
0.2
0.3
0.4
TRIM
From code 63 to 64
HSI16 frequency user trimming step From code 191 to 192
For all other code
increments
DHSI16(2)
tsu(HSI16)(2)
56/93
%
Duty Cycle
-
45
-
55
%
HSI16 oscillator start-up time
-
-
0.8
1.2
μs
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Table 37. HSI16 oscillator characteristics(1) (continued)
Symbol
tstab(HSI16)
Parameter
(2)
IDD(HSI16)(2)
Conditions
Min
Typ
Max
Unit
HSI16 oscillator stabilization time
-
-
3
5
μs
HSI16 oscillator power consumption
-
-
155
190
μA
1. Based on characterization results, not tested in production.
2. Guaranteed by design.
Low-speed internal (LSI) RC oscillator
Table 38. LSI oscillator characteristics(1)
Symbol
Parameter
Conditions
LSI frequency
fLSI
tSU(LSI)(2)
(2)
tSTAB(LSI)
IDD(LSI)(2)
Min
Typ
Max
VDD = 3.0 V, TA = 30 °C
31.04
-
32.96
VDD = VDD(min) to 3.6 V, TA = -40 to
85 °C
29.5
-
34
-
80
130
μs
-
125
180
μs
-
110
180
nA
LSI oscillator start-up time
LSI oscillator stabilization time
5% of final frequency
LSI oscillator power
consumption
-
Unit
kHz
1. Based on characterization results, not tested in production.
2. Guaranteed by design.
5.3.9
PLL characteristics
The parameters given in Table 39 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20: General operating conditions.
Table 39. PLL characteristics(1)
Symbol
Parameter
fPLL_IN
PLL input clock
DPLL_IN
PLL input clock duty cycle
fPLL_P_OUT PLL multiplier output clock P
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT
tLOCK
Jitter
Conditions
Min
Typ
Max
Unit
-
2.66
-
16
MHz
-
45
-
55
%
Voltage scaling Range 1
3.09
-
122
Voltage scaling Range 2
3.09
-
40
Voltage scaling Range 1
12
-
64
Voltage scaling Range 2
12
-
16
Voltage scaling Range 1
96
-
344
Voltage scaling Range 2
96
-
128
-
15
40
-
50
-
-
40
-
frequency(2)
PLL VCO output
PLL lock time
RMS cycle-to-cycle jitter
RMS period jitter
System clock 56 MHz
DS12766 Rev 2
MHz
MHz
MHz
μs
±ps
57/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 39. PLL characteristics(1) (continued)
Symbol
IDD(PLL)
Parameter
Conditions
PLL power consumption
on VDD(1)
Min
Typ
Max
VCO freq = 96 MHz
-
200
260
VCO freq = 192 MHz
-
300
380
VCO freq = 344 MHz
-
520
650
Unit
μA
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.
5.3.10
Flash memory characteristics
Table 40. Flash memory characteristics(1)
Symbol
tprog
Parameter
Row (32 double word) programming time
tprog_page
Page (2 Kbyte) programming time
tprog_bank
tME
IDD(FlashA)
IDD(FlashP)
Typ
Max
Unit
-
85
125
µs
Normal programming
2.7
4.6
Fast programming
1.7
2.8
Normal programming
21.8
36.6
Fast programming
13.7
22.4
22.0
40.0
Normal programming
1.4
2.4
Fast programming
0.9
1.4
22.1
40.1
Programming
3
-
Page erase
3
-
Mass erase
3
-
Programming, 2 µs peak
duration
7
-
Erase, 41 µs peak duration
7
-
64-bit programming time
tprog_row
tERASE
Conditions
Page (2 Kbyte) erase time
-
Bank (128 Kbyte(2)) programming time
Mass erase time
-
Average consumption from VDD
Maximum current (peak)
ms
s
ms
mA
mA
1. Guaranteed by design.
2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank
Table 41. Flash memory endurance and data retention
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = -40 to +85 °C
1
kcycle(2)
at TA = 85 °C
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
58/93
DS12766 Rev 2
Min(1)
Unit
1
kcycles
15
Years
STM32G070CB/KB/RB
5.3.11
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 42. They are based on the EMS levels and classes
defined in application note AN1709.
Table 42. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 64 MHz, LQFP64,
conforming to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be applied
VDD = 3.3 V, TA = +25 °C,
through 100 pF on VDD and VSS pins to induce a fHCLK = 64 MHz, LQFP64,
functional disturbance
conforming to IEC 61000-4-4
5A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
corrupted program counter
unexpected reset
critical data corruption (for example control registers)
DS12766 Rev 2
59/93
80
Electrical characteristics
STM32G070CB/KB/RB
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 43. EMI characteristics
Symbol
Parameter
Conditions
Max vs.
[fHSE/fHCLK]
Monitored
frequency band
Unit
8 MHz / 64 MHz
SEMI
Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP64 package
compliant with IEC 61967-2
0.1 MHz to 30 MHz
7
30 MHz to 130 MHz
-1
130 MHz to 1 GHz
8
1 GHz to 2 GHz
7
EMI level
5.3.12
2.5
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 44. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
value(1)
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming to
ANSI/ESDA/JEDEC JS-001
2
2000
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming to
ANSI/ESDA/JEDEC JS-002
C2a
500
1. Based on characterization results, not tested in production.
60/93
DS12766 Rev 2
Unit
V
STM32G070CB/KB/RB
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current is injected to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 45. Electrical sensitivity
Symbol
LU
5.3.13
Parameter
Static latch-up class
Conditions
Class
TA = +85 °C conforming to JESD78
II Level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional
limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 46. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
IINJ
Description
Injected current on
pin
Unit
Negative
injection
Positive
injection
All except PA4, PA5, PA6, PB0,
PB3, and PC0
-5
N/A
mA
PA4, PA5
-5
0
mA
PA6, PB0, PB3, and PC0
0
N/A
mA
1. Based on characterization results, not tested in production.
DS12766 Rev 2
61/93
80
Electrical characteristics
5.3.14
STM32G070CB/KB/RB
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under the conditions summarized in Table 20: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 47. I/O static characteristics
Symbol
VIL(1)
Parameter
I/O input low level
voltage
Conditions
All
except VDD(min) < VDDIO1 < 3.6 V
FT_c
FT_c
Min
Typ
I/O input high level
voltage
(2)
-
VDDIO1 < 2.7 V
-
VDD(min) < VDDIO1 < 2.7 V
-
-
Vhys(3)
I/O input hysteresis
Ilkg
Input leakage
current(3)
FT_c
FT_d
TT_a
-
0.25 x VDDIO1
-
-
-
-
0.7 x VDDIO1
-
5
-
200
-
0 < VIN ≤ VDDIO1
-
-
±70
VDDIO1 ≤ VIN ≤ VDDIO1+1 V
-
-
600(4)
VDDIO1 +1 V < VIN ≤
5.5 V(3)
-
-
150(4)
0 < VIN ≤ VDDIO1
-
-
2000
VDDIO1 < VIN ≤ 5 V
-
-
3000(4)
0 < VIN ≤ VDDIO1
-
-
4500
VDDIO1 < VIN ≤ 5.5 V
-
-
9000(4)
0 < VIN ≤ VDDIO1
-
-
±150
VDDIO1 < VIN ≤
VDDIO1 + 0.3 V
-
-
2000(4)
25
40
55
kΩ
25
40
55
kΩ
-
5
-
pF
VDD(min) < VDDIO1 < 3.6 V
RPU
Weak pull-up
equivalent resistor
RPD
Weak pull-down
V = VDDIO1
equivalent resistor(5) IN
CIO
I/O pin capacitance
(5)
VIN = VSS
-
1. Refer to Figure 15: I/O input characteristics.
2. Tested in production.
3. Guaranteed by design.
62/93
V
0.3 x VDDIO1
TT_xx,
FT_xx, VDD(min) < VDDIO1 < 3.6 V
NRST
FT_xx
except
FT_c
and
FT_d
0.39 x VDDIO1
- 0.06 (3)
-
0.7 x VDDIO1
2)
All
except VDD(min) < VDDIO1 < 3.6 V
0.49 x VDDIO1
FT_c
+ 0.26(3)
FT_c
Unit
0.3 x VDDIO1
(
VIH(1)
Max
DS12766 Rev 2
V
mV
nA
STM32G070CB/KB/RB
Electrical characteristics
4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 15.
Figure 15. I/O input characteristics
3
Minimum required
logic level 1 zone
2.5
ent)
uirem
2
S
(CMO
VIN (V)
V IHmin
= 0.7
0.49 VDDIO
1
VILmax = 0.39
VILmax = 0.3
0.5
TTL standard requirement
stan
V DDIO
1.5
VIHmin =
req
dard
+ 0.26
Undefined input range
VDDIO - 0.06
VDDIO
ment)
dard require
(CMOS stan
TTL standard requirement
Minimum required
logic level 0 zone
0
2.0
2.2
2.4
Device characteristics
2.6
2.8
3.0
3.2
3.4
3.6
VDDIO (V)
Test thresholds
MSv47926V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to
±15 mA with relaxed VOL/VOH.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 17: Voltage characteristics).
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 17:
Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
DS12766 Rev 2
63/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Table 48. Output voltage characteristics(1)
Symbol
Parameter
Conditions
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
Min
Max
-
0.4
VDDIO1 - 0.4
-
-
0.4
2.4
-
-
1.3
VDDIO1 - 1.3
-
-
0.4
VDDIO1 - 0.45
-
-
0.4
-
0.4
(2)
CMOS port
|IIO| = 2 mA for FT_c I/Os
= 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
TTL port(2)
|IIO| = 2 mA for FT_c I/Os
= 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
All I/Os except FT_c
|IIO| = 15 mA
VDDIO1 ≥ 2.7 V
|IIO| = 1 mA for FT_c I/Os
= 3 mA for other I/Os
|IIO| = 20 mA
VOLFM+ Output low level voltage for an FT I/O
VDDIO1 ≥ 2.7 V
(3)
pin in FM+ mode (FT I/O with _f option)
|IIO| = 9 mA
Unit
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 16 and
Table 49, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.
Table 49. I/O AC characteristics(1)(2)
Speed Symbol
Fmax
Parameter
Maximum frequency
00
Tr/Tf
64/93
Output rise and fall time
Min
Max
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
Conditions
-
2
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V
-
0.35
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
3
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V
-
0.45
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
100
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V
-
225
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
75
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V
-
150
DS12766 Rev 2
Unit
MHz
ns
STM32G070CB/KB/RB
Electrical characteristics
Table 49. I/O AC characteristics(1)(2) (continued)
Speed Symbol
Fmax
Parameter
Maximum frequency
01
Tr/Tf
Fmax
Output rise and fall time
Maximum frequency
10
Tr/Tf
Fmax
Output rise and fall time
Maximum frequency
11
Tr/Tf
Fm+
Fmax
Tf
Output rise and fall time
Maximum frequency
Output fall time(4)
Min
Max
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
Conditions
-
10
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
2
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
15
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
2.5
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
30
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
60
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
15
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
30
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
30
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
15
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
60
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
30
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
11
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
22
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
4
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
8
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
60
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
30
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
80(3)
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
40
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
5.5
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
11
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
2.5
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
5
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 3.6 V
Unit
MHz
ns
MHz
ns
MHz
ns
-
1
MHz
-
5
ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0454 reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.
DS12766 Rev 2
65/93
80
Electrical characteristics
STM32G070CB/KB/RB
Figure 16. I/O AC characteristics definition(1)
90%
10%
50%
50%
10%
90%
t f(IO)out
t r(IO)out
T
Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 49: I/O AC characteristics.
5.3.15
NRST input characteristics
The NRST input driver uses CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 20: General operating conditions.
Table 50. NRST pin characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
-
-
0.3 x VDDIO1
Unit
VIL(NRST)
NRST input low level
voltage
-
VIH(NRST)
NRST input high level
voltage
-
0.7 x VDDIO1
-
-
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
-
-
200
-
mV
RPU
Weak pull-up
equivalent resistor(2)
VIN = VSS
25
40
55
kΩ
-
-
-
70
ns
2.0 V ≤ VDD ≤ 3.6 V
350
-
-
ns
VF(NRST)
NRST input filtered
pulse
VNF(NRST)
NRST input not filtered
pulse
1.
V
Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
66/93
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Figure 17. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 50: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16
Analog switch booster
Table 51. Analog switch booster characteristics(1)
Symbol
VDD
Parameter
Min
Typ
Max
Unit
VDD(min)
-
3.6
V
Booster startup time
-
-
240
µs
Booster consumption for
VDD ≤ 2.7 V
-
-
500
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
-
-
900
Supply voltage
tSU(BOOST)
1. Guaranteed by design.
5.3.17
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 52 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 20: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 52. ADC characteristics(1)
Symbol
Parameter
Conditions(2)
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
2.0
-
3.6
V
VREF+
Positive reference
voltage
-
2
-
VDDA
V
Range 1
0.14
-
35
Range 2
0.14
-
16
fADC
ADC clock frequency
DS12766 Rev 2
MHz
67/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 52. ADC characteristics(1) (continued)
Conditions(2)
Min
Typ
Max
12 bits
-
-
2.50
10 bits
-
-
2.92
8 bits
-
-
3.50
6 bits
-
-
4.38
fADC = 35 MHz; 12 bits
-
-
2.33
12 bits
-
-
fADC/15
Conversion voltage
range
-
VSSA
-
VREF+
V
RAIN
External input
impedance
-
-
-
50
kΩ
CADC
Internal sample and
hold capacitor
-
-
5
-
pF
tSTAB
ADC power-up time
-
2
Conversion
cycle
tCAL
Calibration time
fADC = 35 MHz
2.35
µs
-
82
1/fADC
Symbol
fs
fTRIG
VAIN (3)
Parameter
Sampling rate
External trigger
frequency
CKMODE = 00
tLATR
ts
Trigger conversion
latency
Sampling time
ADC voltage regulator
tADCVREG_STUP start-up time
tCONV
tIDLE
IDDA(ADC)
68/93
Total conversion time
(including sampling
time)
Laps of time allowed
between two
conversions without
rearm
ADC consumption
from VDDA
2
-
CKMODE = 01
6.5
CKMODE = 10
12.5
CKMODE = 11
3.5
3
Unit
MSps
MHz
1/fADC
1/fPCLK
0.043
-
4.59
µs
1.5
-
160.5
1/fADC
-
-
-
20
µs
fADC = 35 MHz
Resolution = 12 bits
0.40
-
4.95
µs
fADC = 35 MHz
Resolution = 12 bits
ts + 12.5 cycles for successive
approximation
= 14 to 173
-
-
-
100
fs = 2.5 MSps
-
410
-
fs = 1 MSps
-
164
-
fs = 10 kSps
-
17
-
DS12766 Rev 2
1/fADC
µs
µA
STM32G070CB/KB/RB
Electrical characteristics
Table 52. ADC characteristics(1) (continued)
Symbol
IDDV(ADC)
Parameter
ADC consumption
from VREF+
Conditions(2)
Min
Typ
Max
fs = 2.5 MSps
-
65
-
fs = 1 MSps
-
26
-
fs = 10 kSps
-
0.26
-
Unit
µA
1. Guaranteed by design
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate
functions for further details.
Table 53. Maximum ADC RAIN .
Resolution
12 bits
10 bits
8 bits
Sampling cycle at 35 MHz
Sampling time at 35 MHz
[ns]
Max. RAIN(1)(2)
(Ω)
1.5
43
50
3.5
100
680
7.5
214
2200
12.5
357
4700
19.5
557
8200
39.5
1129
15000
79.5
2271
33000
160.5
4586
50000
1.5
43
68
3.5
100
820
7.5
214
3300
12.5
357
5600
19.5
557
10000
39.5
1129
22000
79.5
2271
39000
160.5
4586
50000
1.5
43
82
3.5
100
1500
7.5
214
3900
12.5
357
6800
19.5
557
12000
39.5
1129
27000
79.5
2271
50000
160.5
4586
50000
DS12766 Rev 2
69/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 53. Maximum ADC RAIN . (continued)
Resolution
Sampling cycle at 35 MHz
Sampling time at 35 MHz
[ns]
Max. RAIN(1)(2)
(Ω)
1.5
43
390
3.5
100
2200
7.5
214
5600
12.5
357
10000
19.5
557
15000
39.5
1129
33000
79.5
2271
50000
160.5
4586
50000
6 bits
1. Guaranteed by design.
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
Table 54. ADC accuracy(1)(2)(3)
Symbol
Parameter
ET
Total
unadjusted
error
EO
Min
Typ
Max
Unit
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
-
3
6.5
LSB
Offset error
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
-
1.5
4.5
LSB
EG
Gain error
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
-
3
5
LSB
ED
Differential
linearity error
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
-
1.2
1.5
LSB
VDDA=VREF+ < 3.6 V;
Integral linearity
fADC = 35 MHz; fs ≤ 2.5 MSps;
error
TA = entire range
-
2.5
3
LSB
EL
70/93
Conditions(4)
ENOB
Effective
number of bits
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
9.6
10.2
-
bit
SINAD
Signal-to-noise VDDA=VREF+ < 3.6 V;
and distortion fADC = 35 MHz; fs ≤ 2.5 MSps;
ratio
TA = entire range
59.5
63
-
dB
SNR
VDDA=VREF+ < 3.6 V;
Signal-to-noise
fADC = 35 MHz; fs ≤ 2.5 MSps;
ratio
TA = entire range
60
64
-
dB
THD
Total harmonic
distortion
-
-74
-70
dB
VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
1. Based on characterization results, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion
of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins
susceptible to receive negative current.
4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V
and disabled when VDDA ≥ 2.4 V.
Figure 18. ADC accuracy characteristics
EG
Code
(1) Example of an actual transfer curve
4095
(2) Ideal transfer curve
4094
(3) End point correlation line
4093
ET total unadjusted error: maximum deviation
between the actual and ideal transfer curves.
(2)
ET
EO offset error: maximum deviation between the
first actual transition and the first ideal one.
(3)
7
(1)
6
EG gain error: deviation between the last ideal
transition and the last actual one.
5
EL
EO
ED differential linearity error: maximum deviation
between actual steps and the ideal ones.
4
3
ED
EL integral linearity error: maximum deviation between
any actual transition and the end point correlation line.
2
1 LSB ideal
1
0
1
2
3
4
5
6
7
4093 4094 4095
(VAIN / VREF+)*4095
MSv19880V3
Figure 19. Typical connection diagram using the ADC
VDDA
VT
RAIN(1)
VAIN
Sample and hold ADC converter
RADC
AINx
Cparasitic(2)
VT
Ilkg (3)
12-bit
converter
CADC
MS33900V5
1. Refer to Table 52: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 47: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 47: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 8: Power supply scheme.
The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as
possible to the chip.
DS12766 Rev 2
71/93
80
Electrical characteristics
5.3.18
STM32G070CB/KB/RB
Temperature sensor characteristics
Table 55. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
-
±1
±2
°C
2.3
2.5
2.7
mV/°C
0.742
0.76
0.785
V
tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4)
-
8
15
µs
tSTART(1)
Start-up time when entering in continuous mode(4)
-
70
120
µs
tS_temp(1)
ADC sampling time when reading the temperature
5
-
-
µs
IDD(TS)(1)
Temperature sensor consumption from VDD, when
selected by ADC
-
4.7
7
µA
TL(1)
VTS linearity with temperature
(2)
Avg_Slope
Average slope
Voltage at 30°C (±5 °C)(3)
V30
1. Guaranteed by design.
2. Based on characterization results, not tested in production.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
4.
Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
5.3.19
VBAT monitoring characteristics
Table 56. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
R
Resistor bridge for VBAT
-
39
-
kΩ
Q
Ratio on VBAT measurement
-
3
-
-
Error on Q
-10
-
10
%
ADC sampling time when reading the VBAT
12
-
-
µs
Er
(1)
tS_vbat(1)
1. Guaranteed by design.
Table 57. VBAT charging characteristics
Symbol
RBC
5.3.20
Parameter
Battery
charging
resistor
Conditions
Min
Typ
Max
VBRS = 0
-
5
-
VBRS = 1
-
1.5
-
Unit
kΩ
Timer characteristics
The parameters given in the following tables are guaranteed by design. Refer to
Section 5.3.14: I/O port characteristics for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).
72/93
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Table 58. TIMx(1) characteristics
Symbol
Parameter
tres(TIM)
Timer resolution time
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
15.625
-
ns
0
fTIMxCLK/2
0
40
-
16
bit
1
65536
tTIMxCLK
0.015625
1024
µs
-
65536 × 65536
tTIMxCLK
-
67.10
s
fTIMxCLK = 64 MHz
Timer external clock frequency
on CH1 to CH4
fTIMxCLK = 64 MHz
fEXT
ResTIM
TIMx
Timer resolution
tCOUNTER
16-bit counter clock period
Maximum possible count with
32-bit counter
tMAX_COUNT
fTIMxCLK = 64 MHz
fTIMxCLK = 64 MHz
MHz
1. TIMx, is used as a general term in which x stands for 1,, 3, 4, 5, 6, 7, 8, 15, 16 or 17.
Table 59. IWDG min/max timeout period at 32 kHz LSI clock(1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]= 0x000
Max timeout RL[11:0]= 0xFFF
/4
0
0.125
512
/8
1
0.250
1024
/16
2
0.500
2048
/32
3
1.0
4096
/64
4
2.0
8192
/128
5
4.0
16384
/256
6 or 7
8.0
32768
Unit
ms
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.
5.3.21
Characteristics of communication interfaces
I2C-bus interface characteristics
The I2C-bus interface meets timing requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The timings are guaranteed by design as long as the I2C peripheral is properly configured
(refer to the reference manual RM0454) and when the I2CCLK frequency is greater than the
minimum shown in the following table.
DS12766 Rev 2
73/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 60. Minimum I2CCLK frequency
Symbol
Parameter
Condition
Typ
Standard-mode
2
Analog filter enabled
fI2CCLK(min)
Minimum I2CCLK
frequency for correct
operation of I2C
peripheral
Fast-mode
DNF = 0
Analog filter disabled
DNF = 1
Analog filter enabled
Fast-mode Plus
DNF = 0
Analog filter disabled
DNF = 1
Unit
9
9
MHz
18
16
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its
characteristics:
Table 61. I2C analog filter characteristics(1)
Symbol
Parameter
Limiting duration of spikes suppressed
by the filter(2)
tAF
Min
Max
Unit
50
260
ns
1. Based on characterization results, not tested in production.
2. Spikes shorter than the limiting duration are suppressed.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 62 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 20: General operating conditions. The additional general conditions
are:
OSPEEDRy[1:0] set to 11 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
74/93
DS12766 Rev 2
STM32G070CB/KB/RB
Electrical characteristics
Table 62. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
tsu(NSS) NSS setup time
th(NSS)
NSS hold time
Conditions
Min
Typ
Max
Master mode
VDD(min) < VDD < 3.6 V
Range 1
32
Master transmitter
VDD(min) < VDD < 3.6 V
Range 1
32
Slave receiver
VDD(min) < VDD < 3.6 V
Range 1
32
-
-
Unit
MHz
Slave transmitter/full duplex
2.7 < VDD < 3.6 V
Range 1
32
Slave transmitter/full duplex
VDD(min) < VDD < 3.6 V
Range 1
23
VDD(min) < VDD < 3.6 V
Range 2
8
Slave mode, SPI prescaler = 2
4 ₓ TPCLK
-
-
ns
Slave mode, SPI prescaler = 2
2 ₓ TPCLK
-
-
ns
tw(SCKH) SCK high time
Master mode
TPCLK
- 1.5
TPCLK
TPCLK
+ 1.5
ns
tw(SCKL) SCK low time
Master mode
TPCLK
- 1.5
TPCLK
TPCLK
+ 1.5
ns
tsu(MI)
Master data input setup
time
-
1
-
-
ns
tsu(SI)
Slave data input setup
time
-
1
-
-
ns
th(MI)
Master data input hold
time
-
5
-
-
ns
th(SI)
Slave data input hold
time
-
1
-
-
ns
ta(SO)
Data output access time Slave mode
9
-
34
ns
tdis(SO)
Data output disable time Slave mode
9
-
16
ns
2.7 < VDD < 3.6 V
Range 1
-
9
14
VDD(min) < VDD < 3.6 V
Range 1
-
9
21
VDD(min) < VDD < 3.6 V
Voltage Range 2
-
11
24
-
3
5
tv(SO)
tv(MO)
Slave data output valid
time
Master data output valid
time
-
DS12766 Rev 2
ns
ns
75/93
80
Electrical characteristics
STM32G070CB/KB/RB
Table 62. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
th(SO)
Slave data output hold
time
-
5
-
-
ns
th(MO)
Master data output hold
time
-
1
-
-
ns
1. Based on characterization results, not tested in production.
Figure 20. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
SCK input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
MISO output
tv(SO)
th(SO)
First bit OUT
tf(SCK)
Next bits OUT
tdis(SO)
Last bit OUT
th(SI)
tsu(SI)
MOSI input
First bit IN
Next bits IN
Last bit IN
MSv41658V1
Figure 21. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
ta(SO)
tw(SCKL)
tf(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
tv(SO)
First bit OUT
tsu(SI)
MOSI input
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
Last bit OUT
th(SI)
First bit IN
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
Figure 22. SPI timing diagram - master mode
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO
INP UT
tr(SCK)
tf(SCK)
BIT6 IN
MSB IN
LSB IN
th(MI)
MOSI
OUTPUT
B I T1 OUT
MSB OUT
tv(MO)
LSB OUT
th(MO)
ai14136c
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 63. I2S characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S main clock output
fMCK= 256 x Fs; (Fs = audio sampling
frequency)
Fsmin = 8 kHz; Fsmax = 192 kHz;
2.048
49.152
MHz
fCK
I2S clock frequency
Master data
-
64xFs
Slave data
-
64xFs
DCK
I2S clock frequency duty
cycle
30
70
Slave receiver
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MHz
%
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Table 63. I2S characteristics(1) (continued)
Symbol
Parameter
tv(WS)
WS valid time
th(WS)
Min
Max
Master mode
-
8
WS hold time
Master mode
2
-
tsu(WS)
WS setup time
Slave mode
4
-
th(WS)
WS hold time
Slave mode
2
-
Master receiver
4
-
Slave receiver
5
-
Master receiver
4.5
-
Slave receiver
2
-
tsu(SD_MR)
Conditions
Data input setup time
tsu(SD_SR)
th(SD_MR)
Data input hold time
th(SD_SR)
after enable edge; 2.7 < VDD < 3.6V
Unit
ns
16
tv(SD_ST)
Data output valid time slave transmitter
tv(SD_MT)
Data output valid time master transmitter
after enable edge
-
5.5
th(SD_ST)
Data output hold time slave transmitter
after enable edge
8
-
th(SD_MT)
Data output hold time master transmitter
after enable edge
1
-
-
after enable edge;
VDD(min) < VDD < 3.6V
23
1. Based on characterization results, not tested in production.
Figure 23. I2S slave timing diagram (Philips protocol)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
th(SD_ST)
Bitn transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
MSv39721V1
1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
Figure 24. I2S master timing diagram (Philips protocol)
90%
10%
tr(CK)
tf(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
Bitn transmit
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
th(SD_MT)
MSB receive
Bitn receive
LSB receive
MSv39720V1
1. Based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USART characteristics
Unless otherwise specified, the parameters given in Table 64 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 20: General operating conditions. The additional general
conditions are:
OSPEEDRy[1:0] set to 10 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).
Table 64. USART characteristics
Symbol
fCK
Parameter
USART clock frequency
Conditions
Min
Typ
Max
Master mode
-
-
8
Slave mode
-
-
21
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Unit
MHz
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Table 64. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
tsu(NSS)
NSS setup time
Slave mode
tker + 2
-
-
th(NSS)
NSS hold time
Slave mode
2
-
-
tw(CKH)
CK high time
tw(CKL)
CK low time
Master mode
1 / fCK / 2
-1
1 / fCK / 2
1 / fCK / 2
+1
tsu(RX)
Data input setup time
Master mode
tker + 2
-
-
Slave mode
4
-
-
Master mode
1
-
-
Slave mode
0.5
-
-
Master mode
-
0.5
1
Slave mode
-
10
19
Master mode
0
-
-
Slave mode
7
-
-
th(RX)
Data input hold time
tv(TX)
Data output valid time
th(TX)
Data output hold time
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Unit
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STM32G070CB/KB/RB
6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 25. LQFP64 package outline
0.25 mm
GAUGE PLANE
c
A1
A
SEATING PLANE
C
A2
A1
ccc C
D
D1
D3
K
L
L1
33
48
32
49
64
E
E1
b
E3
6.1
17
PIN 1
IDENTIFICATION
16
1
e
5W_ME_V3
1. Drawing is not to scale.
Table 65. LQFP64 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
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Package information
STM32G070CB/KB/RB
Table 65. LQFP64 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 26. Recommended footprint for LQFP64 package
48
33
0.3
0.5
49
32
12.7
10.3
10.3
17
64
1.2
16
1
7.8
12.7
ai14909c
1. Dimensions are expressed in millimeters.
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Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 27. LQFP64 package marking example
Revision code
R
STM32G070
RBT6
Product identification (1)
Date code
Y WW
Pin 1 identifier
MSv42184V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
6.2
STM32G070CB/KB/RB
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 28. LQFP48 package outline
c
A1
A
A2
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc C
K
A1
D
L
D1
L1
D3
36
25
37
24
48
E
E3
E1
b
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
Table 66. LQFP48 mechanical data
inches(1)
millimeters
Symbol
84/93
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
DS12766 Rev 2
STM32G070CB/KB/RB
Package information
Table 66. LQFP48 mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 29. Recommended footprint for LQFP48 package
0.50
1.20
9.70
0.30
25
36
37
24
0.20
7.30
5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS12766 Rev 2
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Package information
STM32G070CB/KB/RB
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 30. LQFP48 package marking example
Product identification (1)
STM32G070
CBT6
Date code
Y WW
Pin 1 identifier
R
Revision code
MSv42185V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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LQFP32 package information
LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 31. LQFP32 package outline
c
A2
A1
A
SEATING
PLANE
C
0.25 mm
ccc
GAUGE PLANE
C
K
D
L
A1
D1
L1
D3
24
17
25
16
32
9
PIN 1
IDENTIFICATION
1
E
E1
E3
b
6.3
Package information
8
e
5V_ME_V2
1. Drawing is not to scale.
Table 67. LQFP32 mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
DS12766 Rev 2
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Package information
STM32G070CB/KB/RB
Table 67. LQFP32 mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 32. Recommended footprint for LQFP32 package
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
1. Dimensions are expressed in millimeters.
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STM32G070CB/KB/RB
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 33. LQFP32 package marking example
Product identification (1)
STM32
G070KBT6
Date code
Pin 1 identifier
Y WW
R
Revision code
MSv42186V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12766 Rev 2
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6.4
Thermal characteristics
The operating junction temperature TJ must never exceed the maximum given in
Table 20: General operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the
operating conditions, is:
TJ(max) = TA(max) + PD(max) x ΘJA
where:
TA(max) is the maximum operating ambient temperature in °C,
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
PD = PINT + PI/O,
–
PINT is power dissipation contribution from product of IDD and VDD
–
PI/O is power dissipation contribution from output ports where:
PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high
level in the application.
Table 68. Package thermal characteristics
Symbol
ΘJA
6.4.1
Parameter
Thermal resistance
junction-ambient
Package
Value
LQFP64 10 × 10 mm
65
LQFP48 7 × 7 mm
75
LQFP32 7 × 7 mm
76
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (still air). Available from www.jedec.org.
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7
Ordering information
Ordering information
Example
STM32
G
070
K
B
T
6
xyy
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
G = general-purpose
Device subfamily
070 = STM32G070
Pin count
K = 32
C = 48
R = 64
Flash memory size
B = 128 Kbytes
Package type
T = LQFP
Temperature range
6 = -40 to 85°C (105°C junction)
Options
˽TR = tape and reel packing
˽˽˽ = tray packing
other = 3-character ID incl. custom Flash code and packing information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
DS12766 Rev 2
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Revision history
8
STM32G070CB/KB/RB
Revision history
Table 69. Document revision history
Date
Revision
28-Nov-2018
1
Initial release.
2
Cover page updated;
Section 2: Description updated;
Section 3.7.1: Power supply schemes: corrected
minimum VDD and VDDA values;
Section 3.14.1: Temperature sensor: “engineering
bytes” replaced “System memory”;
Section 3.17: Inter-integrated circuit interface (I2C):
SMBus and PMBus feature points;
Section 3.18: Universal synchronous/asynchronous
receiver transmitter (USART): max. speed corrected;
Table 11: Note 3 inserted and note 4 modified;
Table 17 updated;
Table 18: Note 2 removed;
Table 20: Redefined VIN;
Table 27 Typical current consumption in Run and Lowpower run modes removed;
depending on code executed
Table 45: LU class modified from “II” to “II Level A”;
Table 48: I/O current condition for relaxed VOL/VOH
corrected from 18 mA to 15 mA; section Output driving
current corrected accordingly;
Table 52: major update;
Section 3.12: DMA request multiplexer (DMAMUX)
added;
Figures with package marking examples corrected.
11-Mar-2020
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STM32G070CB/KB/RB
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
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product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS12766 Rev 2
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