STM32G071GBU3

STM32G071x8/xB Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM, 4x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz • -40°C to 85°C/105°C/125°C operating temperature • Memories – Up to 128 Kbytes of Flash memory with protection and securable area – 36 Kbytes of SRAM (32 Kbytes with HW parity check) • CRC calculation unit • Reset and power management – Voltage range: 1.7 V to 3.6 V – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Programmable voltage detector (PVD) – Low-power modes: Sleep, Stop, Standby, Shutdown – VBAT supply for RTC and backup registers • Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 16 MHz RC with PLL option (±1 %) – Internal 32 kHz RC oscillator (±5 %) • Up to 60 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os • 7-channel DMA controller with flexible mapping • 12-bit, 0.4 µs ADC (up to 16 ext. channels) – Up to 16-bit with hardware oversampling – Conversion range: 0 to 3.6V • Two 12-bit DACs, low-power sample-and-hold • Two fast low-power analog comparators, with programmable input and output, rail-to-rail • 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer • Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown September 2021 This is information on a product in full production. LQFP32 7 × 7 mm LQFP48 7 × 7 mm LQFP64 10 × 10 mm UFQFPN28 4 × 4 mm UFQFPN32 5 × 5 mm UFQFPN48 7 × 7 mm UFBGA64 5 × 5 mm WLCSP25 2.3 × 2.5 mm • Communication interfaces – Two I2C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode – Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature – One low-power UART – Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface – HDMI CEC interface, wakeup on header • USB Type-C™ Power Delivery controller • Development support: serial wire debug (SWD) • 96-bit unique ID • All packages ECOPACK 2 compliant Table 1. Device summary Reference Part number STM32G071x8 STM32G071C8, STM32G071G8, STM32G071K8, STM32G071R8 STM32G071xB STM32G071CB, STM32G071EB, STM32G071GB, STM32G071KB, STM32G071RB DS12232 Rev 4 1/135 www.st.com Contents STM32G071x8/xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16 3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14 2/135 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24 3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS12232 Rev 4 STM32G071x8/xB Contents 3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 29 3.18.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32 3.22 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.25 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 56 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 56 5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DS12232 Rev 4 3/135 5 Contents 6 7 4/135 STM32G071x8/xB 5.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 100 5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.1 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 6.5 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 6.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.7 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.8 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 130 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 DS12232 Rev 4 STM32G071x8/xB 8 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 DS12232 Rev 4 5/135 5 List of tables STM32G071x8/xB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. 6/135 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32G071x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Terms and symbols used in Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Current consumption in Run and Low-power run modes at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical current consumption in Run and Low-power run modes, depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 62 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DS12232 Rev 4 STM32G071x8/xB Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. List of tables EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 WLCSP25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Recommended PCB pad design rules for WLCSP25 package . . . . . . . . . . . . . . . . . . . . 110 UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 125 LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 DS12232 Rev 4 7/135 7 List of figures STM32G071x8/xB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 8/135 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32G071RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32G071RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32G071CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32G071CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32G071KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32G071KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32G071GxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32G071Ex WLCSP25 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 WLCSP25 chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Recommended PCB pad design for WLCSP25 package . . . . . . . . . . . . . . . . . . . . . . . . . 109 WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 DS12232 Rev 4 STM32G071x8/xB Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. List of figures LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DS12232 Rev 4 9/135 9 Introduction 1 STM32G071x8/xB Introduction This document provides information on STM32G071x8/xB microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes. Information on memory mapping and control registers is object of reference manual. Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 10/135 DS12232 Rev 4 STM32G071x8/xB 2 Description Description The STM32G071x8/xB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions. The devices incorporate a memory protection unit (MPU), high-speed embedded memories (36 Kbytes of SRAM and up to 128 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area), DMA, an extensive range of system functions, enhanced I/Os, and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, one HDMI CEC, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, five general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB Type-C Power Delivery controller. The devices operate within ambient temperatures from -40 to 125°C and with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered. The devices come in packages with 28 to 64 pins. Table 2. STM32G071x8/xB family device features and peripheral counts STM32G071_ Peripheral Flash memory (Kbyte) _EB _G8 _GB _G8 xxN _GB xxN _K8 _KB _K8 xxN _KB xxN _C8 _CB _R8 _RB 128 64 128 64 128 64 128 64 128 64 128 64 128 Comm. interfaces Timers SRAM (Kbyte) 32 (with parity) or 36 (without parity) Advanced control 1 (16-bit) high frequency General-purpose 4 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit) Basic 2 (16-bit) Low-power 2 (16-bit) SysTick 1 Watchdog 2 SPI [I2S](1) 2 [1] I2C 2 USART 4 LPUART UCPD 1 (2) 2 CEC (2) 2 1 RTC Yes DS12232 Rev 4 11/135 35 Description STM32G071x8/xB Table 2. STM32G071x8/xB family device features and peripheral counts (continued) STM32G071_ Peripheral _EB _G8 _GB _G8 xxN _GB xxN _K8 _KB Tamper pins 2 Random number generator No AES No GPIOs 23 26 _K8 xxN _KB xxN 30 _C8 _CB _R8 _RB 44 60 Wakeup pins 4 3 4 3 4 5 12-bit ADC channels 10 ext. + 2 int. 9 ext. + 2 int. 11 ext. + 2 int. 10 ext. + 2 int. 14 ext. + 3 int. 16 ext. + 3 int. 12-bit DAC channels 2 Internal voltage reference buffer No Yes Analog comparators 2 Max. CPU frequency 64 MHz Operating voltage 1.7 to 3.6 V Operating temperature(3) Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C Number of pins 25 28 32 2 1. The numbers in brackets denote the count of SPI interfaces configurable as I S interface. 2. One port with only one CC line available (supporting limited number of use cases). 3. Depends on order code. Refer to Section 7: Ordering information for details. 12/135 DS12232 Rev 4 48 64 STM32G071x8/xB Description Figure 1. Block diagram SWCLK SWDIO NVIC IOPORT Bus matrix CORTEX-M0+ fmax = 64 MHz VDDIO1 VDDA Flash memory VDD up to 128 KB I/F SRAM 36 KB Port B PCx Port C PDx Port D PFx Port F SUPPLY SUPERVISION POR Reset Int POR/BOR NRST T sensor RC 16 MHz PVD PLL XTAL OSC 4-48 MHz RC 32 kHz HSE RCC I/F LSE Reset & clock control EXTI from peripherals VDD LSE System and peripheral clocks XTAL32 kHz RTC, TAMP Backup regs I/F AHB-to-APB OSC32_IN OSC32_OUT RTC_OUT RTC_REFIN RTC_TS TAMP_IN VREFBUF COMP1 4 channels ETR TIM3 4 channels ETR TIM6 TIM14 1 channel TIM7 TIM15 2 channels BKIN TIM16 & 17 TIMER 16/17 1 channel BKIN LPTIM1 &1/2 2 LPTIMER ETR, IN, OUT DAC_OUT1 I/F DAC_OUT2 ADC MOSI/SD MISO/MCK SCK/CK NSS/WS SPI1/I2S MOSI, MISO SCK, NSS SPI2 I/F PWRCTRL APB DAC UCPD UCPD1 &2 CEC HDMI-CEC Power domain of analog blocks : APB WWDG CC, DBCC FRSTX 4 channels BKIN, BKIN2, ETR TIM2 (32-bit) COMP2 SYSCFG 16x IN VBAT Low-voltage detector TIM1 IN+, IN-, OUT OSC_IN OSC_OUT IWDG CRC AHB PBx decoder Port A VDD/VDDA VSS/VSSA Parity HSI16 PLLPCLK PLLQCLK PLLRCLK LSI GPIOs PAx Voltage regulator VCORE DMA CPU VREF+ POWER DMAMUX SWD DBGMCU IRTIM USART1 &2 USART1/2 RX, TX CTS, RTS, CK USART3 &4 USART3/4 RX, TX CTS, RTS, CK LPUART VBAT VDD DS12232 Rev 4 VDDA IR_OUT VDDIO1 RX, TX, CTS, RTS I2C1 SCL, SDA SMBA, SMBUS I2C2 SCL, SDA MSv42182V2 13/135 35 Functional overview STM32G071x8/xB 3 Functional overview 3.1 Arm® Cortex®-M0+ core with MPU The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: • a simple architecture, easy to learn and program • ultra-low power, energy-efficient operation • excellent code density • deterministic, high-performance interrupt handling • upward compatibility with Cortex-M processor family • platform security robustness, with integrated Memory Protection Unit (MPU). The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Owing to embedded Arm core, the STM32G071x8/xB devices are compatible with Arm tools and software. The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.13.1. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3 Embedded Flash memory STM32G071x8/xB devices feature up to 128 Kbytes of embedded Flash memory available for storing code and data. 14/135 DS12232 Rev 4 STM32G071x8/xB Functional overview Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Protection level Debug, boot from RAM or boot from system memory (loader) User execution Read Write Erase Read Write Erase User memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) N/A N/A N/A Backup registers 1 Yes Yes 2 Yes Yes (1) N/A N/A 1. Erased upon RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.3.1 • single error detection and correction • double error detection • readout of the ECC fail address from the ECC register Securable area A part of the Flash memory can be hidden from the application once the code it contains is executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be accessed until the system resets. The securable area generally contains the secure boot code to execute only once at boot. This helps to isolate secret code from untrusted application code. DS12232 Rev 4 15/135 35 Functional overview 3.4 STM32G071x8/xB Embedded SRAM STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications. When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes. The memory can be read/write-accessed at CPU clock speed, with 0 wait states. 3.5 Boot modes At startup, the boot pin and boot selector option bit are used to select one of the three boot options: • boot from User Flash memory • boot from System memory • boot from embedded SRAM The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through one of the following interfaces: 3.6 • USART on pins PA9/PA10, PC10/PC11, or PA2/PA3 • I2C-bus on pins PB6/PB7 or PB10/PB11 • SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 16/135 DS12232 Rev 4 STM32G071x8/xB Functional overview 3.7 Power supply management 3.7.1 Power supply schemes The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals: • VDD = 1.7 (1.6) to 3.6 V VDD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin. The minimum voltage of 1.7 V corresponds to power-on reset release threshold VPOR(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold VPDR(min). • VDDA = 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V VDDA is the analog power supply for the A/D converter, D/A converter, voltage reference buffer and comparators. VDDA voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin. • VDDIO1 = VDD VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin. • VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not present. VBAT is provided externally through VBAT pin. When this pin is not available on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin. • VREF+ is the analog peripheral input reference voltage, or the output of the internal voltage reference buffer (when enabled). When VDDA < 2 V, VREF+ must be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be grounded when the analog peripherals using VREF+ are not active. The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register: – VREF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V) – VREF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V) VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is internally connected with VDD, and the internal voltage reference buffer must be kept disabled (refer to datasheets for package pinout description). • VCORE An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the power supply for digital peripherals, SRAM and Flash memory. The Flash memory is also supplied with VDD. DS12232 Rev 4 17/135 35 Functional overview STM32G071x8/xB Figure 2. Power supply overview VREF+ VREF+ VDDA VSSA VDDA domain A/D converter Comparators D/A converter Voltage reference buffer VDDIO1 domain VDDIO1 I/O ring VDD domain VSS/VSSA VDD/VDDA VSS Reset block Temp. sensor PLL, HSI Standby circuitry (Wakeup, IWDG) VDD Voltage regulator Low-voltage detector VCORE domain Core SRAM VCORE Digital peripherals Flash memory RTC domain BKP registers LSE crystal 32.768 kHz osc RCC BDCR register RTC and TAMP VBAT MSv39736V3 3.7.2 Power supply supervisor The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising VDD and other four for falling VDD. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to VPVD threshold. It allows generating an interrupt when VDD level crosses the VPVD threshold, selectively while falling, while rising, or while falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However, SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM. 18/135 DS12232 Rev 4 STM32G071x8/xB 3.7.4 Functional overview Low-power modes By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode. • Stop 0 and Stop 1 modes In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode. • Standby mode The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down VCORE domain. The low-power regulator is either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE). • Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the DS12232 Rev 4 19/135 35 Functional overview STM32G071x8/xB HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper). 3.7.5 Reset mode During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated. 3.7.6 VBAT operation The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers. In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available. The RTC domain can also be supplied from VDD/VDDA pin. By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin. An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is within a valid range. Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT mode, as in that mode the VDD is not within a valid range. 3.8 Interconnect of peripherals Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes. 20/135 DS12232 Rev 4 STM32G071x8/xB Functional overview Stop TIMx Sleep Low-power sleep Interconnect source Run Low-power run Table 4. Interconnect of peripherals TIMx Timer synchronization or chaining Y Y - ADCx DACx Conversion triggers Y Y - DMA Memory-to-memory transfer trigger Y Y - COMPx Comparator output blanking Y Y - TIM1,2,3 Timer input channel, trigger, break from analog signals comparison Y Y - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y TIM1 Timer triggered by analog watchdog Y Y - TIM16 Timer input channel from RTC events Y Y - Low-power timer triggered by RTC alarms or tampers Y Y Y Clock source used as input channel for RC measurement and trimming Y Y - Interconnect destination COMPx ADCx RTC LPTIMERx Interconnect action All clock sources (internal and external) TIM14,16,17 CSS RAM (parity error) Flash memory (ECC error) COMPx PVD TIM1,15,16,17 Timer break Y Y - CPU (hard fault) TIM1,15,16,17 Timer break Y - - TIMx External trigger Y Y - LPTIMERx External trigger Y Y Y Conversion external trigger Y Y - GPIO ADC DACx DS12232 Rev 4 21/135 35 Functional overview 3.9 STM32G071x8/xB Clocks and startup The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: three different sources can deliver SYSCLK system clock: • – 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL. – System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or HSI16 clocks. Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog. • Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC) have their own clock independent of the system clock. • Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software. • Clock output: – MCO (microcontroller clock output) provides one of the internal clocks for external use by the application – LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT operation). Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum. 3.10 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions. 22/135 DS12232 Rev 4 STM32G071x8/xB Functional overview Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers. 3.11 Direct memory access controller (DMA) The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture. With 7 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU. Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests. Main features of the DMA controller: • Single-AHB master • Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers • Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals • All DMA channels independently configurable: • 3.12 – Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software. – Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2). – Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size. – Support of transfers from/to peripherals to/from memory with circular buffer management – Programmable number of data to be transferred: 0 to 216 - 1 Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error. DMA request multiplexer (DMAMUX) The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals. 3.13 Interrupts and events The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) DS12232 Rev 4 23/135 35 Functional overview STM32G071x8/xB and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow. The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions. 3.13.1 Nested vectored interrupt controller (NVIC) The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management. The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset. If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency. Features of the NVIC: 3.13.2 • Low-latency interrupt processing • 4 priority levels • Handling of a non-maskable interrupt (NMI) • Handling of 32 maskable interrupt lines • Handling of 10 Cortex-M0+ exceptions • Later-arriving higher-priority interrupt processed first • Tail-chaining • Interrupt vector retrieval by hardware Extended interrupt/event controller (EXTI) The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode. The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels. The channels can be independently masked. The EXTI controller can capture pulses shorter than the internal clock period. 24/135 DS12232 Rev 4 STM32G071x8/xB Functional overview A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt. 3.14 Analog-to-digital converter (ADC) A native 12-bit analog-to-digital converter is embedded into STM32G071x8/xB devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase. The ADC can be served by the DMA controller. It can operate in the whole VDD supply range. The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to AN2668). An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers. 3.14.1 Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements. To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode. Table 5. Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB DS12232 Rev 4 25/135 35 Functional overview 3.14.2 STM32G071x8/xB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and comparators. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually precisely measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in read-only mode. Table 6. Internal voltage reference calibration values 3.14.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the VBAT voltage. 3.15 Digital-to-analog converter (DAC) The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels. Features of the DAC: 26/135 • Two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Independent or simultaneous conversion for DAC channels • DMA capability for either DAC channel • Triggering with timer events, synchronized with DMA • Triggering with external events • Sample-and-hold low-power mode, with internal or external capacitor DS12232 Rev 4 STM32G071x8/xB 3.16 Functional overview Voltage reference buffer (VREFBUF) When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC) and to VREF+ pin for external components. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled. On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used. 3.17 Comparators (COMP) Two embedded rail-to-rail analog comparators have programmable reference voltage (internal or external), hysteresis, speed (low for low-power) and output polarity. The reference voltage can be one of the following: • external, from an I/O • internal, from DAC • internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4) The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator. 3.18 Timers and watchdogs The device includes an advanced-control timer, six general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced-control, general-purpose and basic timers. Table 7. Timer feature comparison Timer type Timer Counter resolution Counter type Maximum operating frequency Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advancedcontrol TIM1 16-bit Up, down, up/down 128 MHz Integer from 1 to 216 Yes 4 3 DS12232 Rev 4 27/135 35 Functional overview STM32G071x8/xB Table 7. Timer feature comparison (continued) Timer Counter resolution Counter type Maximum operating frequency Prescaler factor DMA request generation Capture/ compare channels Complementary outputs TIM2 32-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM3 16-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM14 16-bit Up 64 MHz Integer from 1 to 216 No 1 - TIM15 16-bit Up 128 MHz Integer from 1 to 216 Yes 2 1 TIM16 TIM17 16-bit Up 64 MHz Integer from 1 to 216 Yes 1 1 Basic TIM6 TIM7 16-bit Up 64 MHz Integer from 1 to 216 Yes - - Low-power LPTIM1 LPTIM2 16-bit Up 64 MHz 2n where n=0 to 7 No N/A - Timer type Generalpurpose 3.18.1 Advanced-control timer (TIM1) The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for: • input capture • output compare • PWM output (edge or center-aligned modes) with full modulation capability (0-100%) • one-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.18.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 28/135 DS12232 Rev 4 STM32G071x8/xB 3.18.2 Functional overview General-purpose timers (TIM2, 3, 14, 15, 16, 17) There are six synchronizable general-purpose timers embedded in the device (refer to Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs or act as a simple timebase. • TIM2, TIM3 These are full-featured general-purpose timers: – TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler – TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate together or in combination with other generalpurpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counters can be frozen in debug mode. • TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode. • TIM15, TIM16, TIM17 These are general-purpose timers featuring: – 16-bit auto-reload upcounter and 16-bit prescaler – 2 channels and 1 complementary channel for TIM15 – 1 channel and 1 complementary channel for TIM16 and TIM17 All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode. 3.18.3 Basic timers (TIM6 and TIM7) These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases. 3.18.4 Low-power timers (LPTIM1 and LPTIM2) These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it. DS12232 Rev 4 29/135 35 Functional overview STM32G071x8/xB Features of LPTIM1 and LPTIM2: 3.18.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output (pulse, PWM) • Continuous/one-shot mode • Selectable software/hardware input trigger • Selectable clock source: – Internal: LSE, LSI, HSI16 or APB clocks – External: over LPTIM input (working even with no internal clock source running, used by pulse counter application) • Programmable digital glitch filter • Encoder mode Independent watchdog (IWDG) The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode. 3.18.6 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode. 3.18.7 SysTick timer This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter. Features of SysTick timer: 3.19 • 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source Real-time clock (RTC), tamper (TAMP) and backup registers The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die. The ways of powering the RTC domain are described in Section 3.7.6. The RTC is an independent BCD timer/counter. 30/135 DS12232 Rev 4 STM32G071x8/xB Functional overview Features of the RTC: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month • Programmable alarm • On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock • Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy • Two anti-tamper detection pins with programmable filter • Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin or a tamper event, or by switching to VBAT mode • 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable resolution and period • Multiple clock sources and references: – A 32.768 kHz external crystal (LSE) – An external resonator or oscillator (LSE) – The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) – The high-speed external clock (HSE) divided by 32 When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes. The backup registers allow keeping 20 bytes of user application data in the event of VDD failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes. 3.20 Inter-integrated circuit interface (I2C) The device embeds two I2C peripherals. Refer to Table 8 for the features. The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing. DS12232 Rev 4 31/135 35 Functional overview STM32G071x8/xB Features of the I2C peripheral: • I2C-bus specification and user manual rev. 5 compatibility: – • Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Clock stretching SMBus specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection • PMBus rev 1.3 standard compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent of the PCLK reprogramming • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 8. I2C implementation I2C features(1) I2C1 I2C2 Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X Programmable analog and digital noise filters X X SMBus/PMBus hardware support X - Independent clock X - Wakeup from Stop mode on address match X - 1. X: supported 3.21 Universal synchronous/asynchronous receiver transmitter (USART) The device embeds universal synchronous/asynchronous receivers/transmitters that communicate at speeds of up to 8 Mbit/s. They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire 32/135 DS12232 Rev 4 STM32G071x8/xB Functional overview half-duplex communication mode. Some can also support SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from Stop mode. The wakeup events from Stop mode are programmable and can be: • start bit detection • any received data frame • a specific programmed data frame All USART interfaces can be served by the DMA controller. Table 9. USART implementation USART1 USART2 USART3 USART4 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X - LIN mode X - Dual clock domain and wakeup from Stop mode X - Receiver timeout interrupt X - Modbus communication X - Auto baud rate detection X - Driver Enable X X USART modes/features(1) 1. X: supported 3.22 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one LPUART. The peripheral supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent of the CPU clock, and can wakeup the system from Stop mode. The Stop mode wakeup events are programmable and can be: • start bit detection • any received data frame • a specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while DS12232 Rev 4 33/135 35 Functional overview STM32G071x8/xB having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interface can be served by the DMA controller. 3.23 Serial peripheral interface (SPI) The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC calculation. The SPI peripherals can be served by the DMA controller. The I2S interface mode of the SPI peripheral (if supported, see the following table) supports four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. Table 10. SPI/I2S implementation SPI features(1) SPI1 SPI2 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X I2S X - X X mode TI mode 1. X = supported. 3.24 USB Type-C™ Power Delivery controller The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications. The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring: 34/135 • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB Power Delivery message transmission and reception • FRS (fast role swap) support DS12232 Rev 4 STM32G071x8/xB Functional overview The digital controller handles notably: • USB Type-C level detection with de-bounce, generating interrupts • FRS detection, generating an interrupt • byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible) • USB Power Delivery timing dividers (including a clock pre-scaler) • CRC generation/checking • 4b5b encode/decode • ordered sets (with a programmable ordered set mask at receive) • frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling. 3.25 Development support 3.25.1 Serial wire debug port (SW-DP) An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. DS12232 Rev 4 35/135 35 Pinouts, pin description and alternate functions 4 STM32G071x8/xB Pinouts, pin description and alternate functions The devices housed in 28-pin and 32-pin packages come in two variants - “GP” and “N” (the latter with ordering code having N behind the temperature range digit). Refer to Table 2: Features and peripheral counts for differences. PD2 PD1 PD0 PC9 51 50 49 PD5 55 52 PD6 56 PD4 PB3 57 PD3 PB4 58 53 PB5 59 54 PB7 PB6 PB8 60 PB9 62 61 PC10 63 Top view 64 Figure 3. STM32G071RxT LQFP64 pinout PC11 1 48 PC8 PC12 2 47 PA15 PC13 3 46 PA14-BOOT0 PC14-OSC32_IN 4 45 PA13 PC15-OSC32_OUT 5 44 PA12 [PA10] VBAT 6 43 PA11 [PA9] VREF+ 7 42 PA10 VDD/VDDA 8 41 PD9 LQFP64 28 29 30 31 32 PB1 PB2 PB10 PB11 PB12 PB13 27 33 PB0 16 26 PB14 PC3 PC5 34 25 15 PC4 PB15 PC2 24 35 PA7 14 23 PA8 PC1 22 36 PA6 13 PA5 PA9 PC0 21 37 PA4 12 20 PC6 PF2-NRST PA3 38 19 11 PA2 PC7 PF1-OSC_OUT 18 PD8 39 17 40 PA1 9 10 PA0 VSS/VSSA PF0-OSC_IN MSv39710V3 36/135 DS12232 Rev 4 STM32G071x8/xB Pinouts, pin description and alternate functions Figure 4. STM32G071RxI UFBGA64 pinout 1 2 3 4 5 6 7 8 A PC11 PC10 PB7 PB6 PD6 PD2 PD0 PC8 B PC15OSC32 _OUT PC12 PB8 PB3 PD5 PD1 PC9 PA12 [PA10] C PC14OSC32 _IN PC13 PB9 PB4 PD4 PA15 PA14BOOT0 PA11 [PA9] D VDD/ VDDA VREF+ VBAT PB5 PD3 PA10 PA13 PD9 E VSS/ VSSA PF2NRST PC0 PA7 PC7 PA9 PC6 PD8 F PF0OSC_I N PC1 PA3 PA6 PB0 PB14 PB15 PA8 G PF1OSC_ OUT PC2 PA2 PA5 PB1 PB10 PB12 PB13 H PC3 PA0 PA1 PA4 PC4 PC5 PB2 PB11 MSv47971V1 Figure 5. STM32G071CxT LQFP48 pinout 37 38 39 40 41 42 43 44 45 46 1 36 2 35 3 34 4 33 5 32 6 31 LQFP48 7 30 24 23 22 21 20 19 18 25 17 26 12 16 27 11 15 28 10 14 29 9 13 8 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view MSv39711V3 DS12232 Rev 4 37/135 47 Pinouts, pin description and alternate functions STM32G071x8/xB Figure 6. STM32G071CxU UFQFPN48 pinout 37 38 39 40 41 42 43 44 45 46 1 36 2 35 3 34 4 33 5 32 6 31 UFQFPN48 7 30 8 29 9 28 10 27 11 Exposed pad 23 22 21 20 19 18 17 16 15 14 13 12 26 25 24 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 VSS MSv39714V3 PB8 PB7 PB6 PB5 PB4 PB3 PA15 PA14-BOOT0 31 30 29 28 27 26 25 Top view 32 Figure 7. STM32G071KxT LQFP32 pinout PB9 1 24 PA13 PC14-OSC32_IN 2 23 PA12 [PA10] PC15-OSC32_OUT 3 22 PA11 [PA9] VDD/VDDA 4 21 PA10 VSS/VSSA 5 20 PC6 PF2-NRST 6 19 PA9 PA0 7 18 PA8 GP version PA1 8 17 PB2 (_KxT) 9 10 11 12 13 14 15 16 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 LQFP32 PB8 PB7 PB6 PD3 PD2 PD1 PD0 PA14-BOOT0 31 30 29 28 27 26 25 Top view 32 MSv39712V3 PB9 1 24 PA13 PC14-OSC32_IN 2 23 PA12 [PA10] PC15-OSC32_OUT 3 22 PA11 [PA9] VDD/VDDA 4 21 PA10 VSS/VSSA 5 20 PC6 PF2-NRST 6 19 PA9 PA0 7 18 PA8 PA1 8 17 PB15 9 10 11 12 13 14 15 16 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 LQFP32 N version (_KxTxN) MSv42120V1 38/135 DS12232 Rev 4 STM32G071x8/xB Pinouts, pin description and alternate functions 25 26 27 28 29 1 24 2 23 3 22 4 5 UFQFPN32 21 20 PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB2 GP version (_KxU) 16 15 14 13 17 12 18 8 11 19 7 9 6 10 PB9 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 30 32 Top view 31 PB8 PB7 PB6 PB5 PB4 PB3 PA15 PA14-BOOT0 Figure 8. STM32G071KxU UFQFPN32 pinout PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS 25 26 27 28 29 1 24 2 23 3 22 4 5 UFQFPN32 21 20 PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB15 N version (_KxUxN) 16 15 14 13 17 12 18 8 11 19 7 9 6 10 PB9 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 30 32 Top view 31 PB8 PB7 PB6 PD3 PD2 PD1 PD0 PA14-BOOT0 MSv39715V3 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS MSv42121V1 DS12232 Rev 4 39/135 47 Pinouts, pin description and alternate functions STM32G071x8/xB Figure 9. STM32G071GxU UFQFPN28 pinout 22 23 24 25 26 1 21 2 20 15 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PC6 PA8 PB1 GP version (_GxU) PA2 PA3 PA4 PA5 PA6 PA7 PB0 14 16 7 13 17 6 12 5 11 UFQFPN28 18 10 19 4 9 3 8 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 27 28 PB8 PB7 PB6 PB5 PB4 PB3 PA15 Top view MSv39713V4 22 23 24 25 26 1 21 2 20 15 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PC6 PA8 PB15 N version (_GxUxN) PA2 PA3 PA4 PA5 PA6 PA7 PB0 14 16 7 13 17 6 12 5 11 UFQFPN28 18 10 19 4 9 3 8 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 27 28 PB8 PB7 PB6 PD3 PD2 PD1 PD0 Top view MSv42122V2 Figure 10. STM32G071Ex WLCSP25 pinout Top view 1 2 3 4 5 A PA15 PA14BOOT0 PB5 PB7 PC14OSC32 _IN B PA12 [PA10] PA13 PB6 PB8 PC15OSC32 _OUT C PA11 [PA9] PA6 PA3 PA0 VDD/ VDDA D PA8 PA7 PA4 PA1 VSS/ VSSA E PB1 PB0 PA5 PA2 PF2 NRST MSv47938V2 40/135 DS12232 Rev 4 STM32G071x8/xB Pinouts, pin description and alternate functions Table 11. Terms and symbols used in Table 12 Column Symbol Definition Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. Pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor Options for TT or FT I/Os Note _f I/O, Fm+ capable _a I/O, with analog switch function _c I/O, USB Type-C PD capable _d I/O, USB Type-C PD Dead Battery function Upon reset, all I/Os are set as analog inputs, unless otherwise specified. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions Table 12. Pin assignment and description WLCSP25 UFQFPN28 - GP UFQFPN28 - N LQFP32 / UFQFPN32 - GP LQFP32 / UFQFPN32 - N LQFP48 / UFQFPN48 UFBGA64 LQFP64 (function upon reset) Pin type I/O structure Note Pin number Alternate functions - - - - - - A1 1 PC11 I/O FT - USART3_RX, USART4_RX, TIM1_CH4 - - - - - - - B2 2 PC12 I/O FT - LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1 - - - - - - 1 C2 3 PC13 I/O FT (1)(2) TIM1_BKIN TAMP_IN1,RTC_TS, RTC_OUT1,WKUP2 Pin name DS12232 Rev 4 Additional functions 41/135 47 Pinouts, pin description and alternate functions STM32G071x8/xB Table 12. Pin assignment and description (continued) WLCSP25 UFQFPN28 - GP UFQFPN28 - N LQFP32 / UFQFPN32 - GP LQFP32 / UFQFPN32 - N LQFP48 / UFQFPN48 UFBGA64 LQFP64 (function upon reset) Pin type I/O structure Note Pin number Alternate functions - - - - - 2 C1 4 PC14OSC32_IN (PC14) I/O FT (1)(2) TIM1_BKIN2 OSC32_IN A5 1 1 2 2 - - - PC14OSC32_IN (PC14) I/O FT (1)(2) TIM1_BKIN2 OSC32_IN,OSC_IN B5 2 2 3 3 3 B1 5 PC15OSC32_OUT (PC15) I/O FT (1)(2) OSC32_EN, OSC_EN, TIM15_BKIN OSC32_OUT - - - - - 4 D3 6 VBAT S - - - - - - - - - 5 D2 7 VREF+ S - - - VREF_OUT C5 3 3 4 4 6 D1 8 VDD/VDDA S - - - - D5 4 4 5 5 7 E1 9 VSS/VSSA S - - - - - - - - - 8 F1 10 PF0-OSC_IN (PF0) I/O FT - TIM14_CH1 OSC_IN - - - - - 9 G1 11 PF1OSC_OUT (PF1) I/O FT - OSC_EN, TIM15_CH1N OSC_OUT E5 5 5 6 6 10 E2 12 PF2 - NRST I/O FT - MCO NRST - - - - - - E3 13 PC0 I/O FT - LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1 - - - - - - - F2 14 PC1 I/O FT - LPTIM1_OUT, LPUART1_TX, TIM15_CH1 - - - - - - - G2 15 PC2 I/O FT - LPTIM1_IN2, SPI2_MISO, TIM15_CH2 - - - - - - - H1 16 PC3 I/O FT - LPTIM1_ETR, SPI2_MOSI, LPTIM2_ETR - - SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, COMP1_INM, ADC_IN0, USART4_TX, LPTIM1_OUT, TAMP_IN2,WKUP1 UCPD2_FRSTX, COMP1_OUT C4 6 42/135 6 7 7 Pin name 11 H2 17 PA0 I/O FT_a DS12232 Rev 4 Additional functions STM32G071x8/xB Pinouts, pin description and alternate functions Table 12. Pin assignment and description (continued) E4 C3 - 7 8 9 - 8 9 - 8 9 10 - D3 10 10 11 E3 11 11 12 C2 12 12 13 D2 13 13 14 - - - - 8 9 12 H3 18 13 G3 19 10 14 F3 20 - 11 15 H4 21 - - - 12 16 G4 22 13 17 F4 23 14 18 E4 24 - - H5 25 PA1 PA2 PA3 PA4 PA4 PA5 PA6 I/O I/O I/O I/O I/O I/O I/O I/O structure (function upon reset) Pin type LQFP64 UFBGA64 LQFP48 / UFQFPN48 LQFP32 / UFQFPN32 - N LQFP32 / UFQFPN32 - GP UFQFPN28 - N 7 Pin name FT_a FT_a FT_a TT_a TT_a TT_a FT_a Note D4 UFQFPN28 - GP WLCSP25 Pin number Alternate functions Additional functions - SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT COMP1_INP, ADC_IN1 - SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, COMP2_INM, ADC_IN2, UCPD1_FRSTX, WKUP4,LSCO TIM15_CH1, LPUART1_TX, COMP2_OUT - SPI2_MISO, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT COMP2_INP, ADC_IN3 - SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT ADC_IN4, DAC_OUT1, RTC_OUT2 - SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT ADC_IN4, DAC_OUT1, TAMP_IN1,RTC_TS, RTC_OUT1,WKUP2 - SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT ADC_IN5, DAC_OUT2 - SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT ADC_IN6 ADC_IN7 COMP1_INM, ADC_IN17 PA7 I/O FT_a - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT PC4 I/O FT_a - USART3_TX, USART1_TX, TIM2_CH1_ETR DS12232 Rev 4 43/135 47 Pinouts, pin description and alternate functions STM32G071x8/xB Table 12. Pin assignment and description (continued) - E1 15 - - LQFP48 / UFQFPN48 UFBGA64 - - - H6 26 - 14 15 - - 16 - 17 - - - - 16 20 G5 28 - 21 H7 29 Pin type LQFP64 15 19 F5 27 (function upon reset) PC5 I/O PB0 PB0 I/O I/O Note - - Pin name I/O structure E2 14 LQFP32 / UFQFPN32 - N - UFQFPN28 - N UFQFPN28 - GP - LQFP32 / UFQFPN32 - GP WLCSP25 Pin number Alternate functions Additional functions FT_a - USART3_RX, USART1_RX, TIM2_CH2 COMP1_INP, ADC_IN18, WKUP5 - SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT ADC_IN8 (3) SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT UCPD1_DBCC2, ADC_IN8 COMP1_INM, ADC_IN9 FT_a FT_da PB1 I/O FT_a - TIM14_CH1, TIM3_CH4, TIM1_CH3N, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, EVENTOUT PB2 I/O FT_a - SPI2_MISO, USART3_TX, LPTIM1_OUT, EVENTOUT COMP1_INP, ADC_IN10 ADC_IN11 - - - - - 22 G6 30 PB10 I/O FT_fa - CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK, I2C2_SCL, COMP1_OUT - - - - - 23 H8 31 PB11 I/O FT_fa - SPI2_MOSI, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT ADC_IN15 - SPI2_NSS, LPUART1_RTS_DE, TIM1_BKIN, TIM15_BKIN, UCPD2_FRSTX, EVENTOUT ADC_IN16 - SPI2_SCK, LPUART1_CTS, TIM1_CH1N, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT - - - - - 44/135 - - - - - - 24 G7 32 25 G8 33 PB12 PB13 I/O I/O FT_a FT_f DS12232 Rev 4 STM32G071x8/xB Pinouts, pin description and alternate functions Table 12. Pin assignment and description (continued) - - - - - 15 - D1 16 16 18 I/O structure Pin type LQFP48 / UFQFPN48 Pin name 26 F6 34 PB14 I/O FT_f - SPI2_MISO, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT 17 27 F7 35 PB15 I/O FT_c (3) SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT UCPD1_CC2, RTC_REFIN, 18 28 F8 36 PA8 I/O FT_c (3) MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT, EVENTOUT UCPD1_CC1 MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, EVENTOUT UCPD1_DBCC1 - LQFP64 Alternate functions UFBGA64 Note - LQFP32 / UFQFPN32 - N UFQFPN28 - N LQFP32 / UFQFPN32 - GP UFQFPN28 - GP WLCSP25 Pin number (function upon reset) Additional functions - - - - 19 19 29 E6 37 PA9 I/O FT_fd (3) - 17 - 20 20 30 E7 38 PC6 I/O FT - UCPD1_FRSTX, TIM3_CH1, TIM2_CH3 - - - 17 - - PC6 I/O FT_d (3) UCPD1_FRSTX, TIM3_CH1, TIM2_CH3 UCPD1_DBCC1 - - - - - PC7 I/O FT - UCPD2_FRSTX, TIM3_CH2, TIM2_CH4 - - - - - - - E8 40 PD8 I/O FT - USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT - - - - - - - D8 41 PD9 I/O FT - USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2 - - - - 21 21 32 D6 42 PA10 I/O FT_fd (3) SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, EVENTOUT UCPD1_DBCC2 22 33 C8 43 PA11 [PA9](4) - SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL, COMP1_OUT - 23 34 B8 44 PA12 [PA10](4) - SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA, COMP2_OUT - C1 18 18 22 B1 19 19 23 - - - 31 E5 39 I/O I/O FT_f FT_f DS12232 Rev 4 45/135 47 Pinouts, pin description and alternate functions STM32G071x8/xB Table 12. Pin assignment and description (continued) I/O structure Note 37 C6 47 SWDIO, IR_OUT, EVENTOUT - (5) SWCLK, USART2_TX, EVENTOUT BOOT0 - FT 25 36 C7 46 PA14-BOOT0 - (5) I/O A2 21 21 25 26 FT I/O 24 35 D7 45 - Additional functions PA13 B2 20 20 24 A1 22 Alternate functions (function upon reset) Pin type LQFP64 Pin name UFBGA64 LQFP48 / UFQFPN48 LQFP32 / UFQFPN32 - N UFQFPN28 - N LQFP32 / UFQFPN32 - GP UFQFPN28 - GP WLCSP25 Pin number PA15 I/O FT - SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK, EVENTOUT - - - - - - A8 48 PC8 I/O FT - UCPD2_FRSTX, TIM3_CH3, TIM1_CH1 - - - - - - - B7 49 PC9 I/O FT - I2S_CKIN, TIM3_CH4, TIM1_CH2 - - - 22 - 26 38 A7 50 PD0 I/O FT_c (3) EVENTOUT, SPI2_NSS, TIM16_CH1 UCPD2_CC1 - - 23 - 27 39 B6 51 PD1 I/O FT_d (3) EVENTOUT, SPI2_SCK, TIM17_CH1 UCPD2_DBCC1 - - 24 - 28 40 A6 52 PD2 I/O FT_c (3) USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N UCPD2_CC2 - - 25 - 29 41 D5 53 PD3 I/O FT_d (3) USART2_CTS, SPI2_MISO, TIM1_CH2N UCPD2_DBCC2 - - - - - - C5 54 PD4 I/O FT - USART2_RTS_DE_CK, SPI2_MOSI, TIM1_CH3N - - - - - - - B5 55 PD5 I/O FT - USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN - - - - - - - A5 56 PD6 I/O FT - USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT - COMP2_INM COMP2_INP - 23 - 27 - 42 B4 57 PB3 I/O FT_a - SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, EVENTOUT - 24 - 28 - 43 C4 58 PB4 I/O FT_a - SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN, EVENTOUT 46/135 DS12232 Rev 4 STM32G071x8/xB Pinouts, pin description and alternate functions Table 12. Pin assignment and description (continued) 29 B3 26 26 30 A4 27 27 31 B4 28 28 32 - 44 D4 59 30 45 A4 60 31 46 A3 61 32 47 B3 62 - - - 1 1 - - - - - 48 C3 63 - A2 64 PB5 PB6 PB7 PB8 I/O I/O I/O I/O I/O structure (function upon reset) Pin type LQFP64 UFBGA64 LQFP48 / UFQFPN48 LQFP32 / UFQFPN32 - N UFQFPN28 - N - Pin name FT FT_fa FT_fa FT_f Note A3 25 LQFP32 / UFQFPN32 - GP UFQFPN28 - GP WLCSP25 Pin number Alternate functions Additional functions - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT WKUP6 - USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT COMP2_INP - USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT COMP2_INM, PVD_IN - CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT - - - PB9 I/O FT_f - IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA, EVENTOUT PC10 I/O FT - USART3_TX, USART4_TX, TIM1_CH3 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (for example to drive a LED). 2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual. 3. Upon reset, a pull-down resistor might be present on PB15, PA8, PD0, or PD2, depending on the voltage level on PB0, PA9, PC6, PA10, PD1, and PD3. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1 register during start-up sequence. 4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register. 5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated. DS12232 Rev 4 47/135 47 48/135 Table 13. Port A alternate function mapping DS12232 Rev 4 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PA0 SPI2_SCK USART2_CTS TIM2_CH1_ETR - USART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUT PA1 SPI1_SCK/ I2S1_CK USART2_RTS _DE_CK TIM2_CH2 - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT PA2 SPI1_MOSI/ I2S1_SD USART2_TX TIM2_CH3 - UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUT PA3 SPI2_MISO USART2_RX TIM2_CH4 - UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT PA4 SPI1_NSS/ I2S1_WS SPI2_MOSI - - TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT PA5 SPI1_SCK/ I2S1_CK CEC TIM2_CH1_ETR - USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT PA6 SPI1_MISO/ I2S1_MCK TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUT PA7 SPI1_MOSI/ I2S1_SD TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUT PA8 MCO SPI2_NSS TIM1_CH1 - - LPTIM2_OUT - EVENTOUT PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT PA10 SPI2_MOSI USART1_RX TIM1_CH3 - - TIM17_BKIN I2C1_SDA EVENTOUT PA11 SPI1_MISO/ I2S1_MCK USART1_CTS TIM1_CH4 - - TIM1_BKIN2 I2C2_SCL COMP1_OUT PA12 SPI1_MOSI/ I2S1_SD USART1_RTS _DE_CK TIM1_ETR - - I2S_CKIN I2C2_SDA COMP2_OUT PA13 SWDIO IR_OUT - - - - - EVENTOUT PA14 SWCLK USART2_TX - - - - - EVENTOUT PA15 SPI1_NSS/ I2S1_WS USART2_RX TIM2_CH1_ETR - USART4_RTS _DE_CK USART3_RTS _DE_CK - EVENTOUT - STM32G071x8/xB Port DS12232 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PB0 SPI1_NSS/ I2S1_WS TIM3_CH3 TIM1_CH2N - USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUT PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - USART3_RTS _DE_CK LPTIM2_IN1 LPUART1_RTS _DE EVENTOUT PB2 - SPI2_MISO - - USART3_TX LPTIM1_OUT - EVENTOUT PB3 SPI1_SCK/ I2S1_CK TIM1_CH2 TIM2_CH2 - USART1_RTS _DE_CK - - EVENTOUT PB4 SPI1_MISO/ I2S1_MCK TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT PB5 SPI1_MOSI/ I2S1_SD TIM3_CH2 TIM16_BKIN - - LPTIM1_IN1 I2C1_SMBA COMP2_OUT PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO LPTIM1_ETR I2C1_SCL EVENTOUT PB7 USART1_RX SPI2_MOSI TIM17_CH1N - USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT PB8 CEC SPI2_SCK TIM16_CH1 - USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT PB9 IR_OUT UCPD2_FRSTX TIM17_CH1 - USART3_RX SPI2_NSS I2C1_SDA EVENTOUT PB10 CEC LPUART1_RX TIM2_CH3 - USART3_TX SPI2_SCK I2C2_SCL COMP1_OUT PB11 SPI2_MOSI LPUART1_TX TIM2_CH4 - USART3_RX - I2C2_SDA COMP2_OUT PB12 SPI2_NSS LPUART1_RTS _DE TIM1_BKIN - - TIM15_BKIN UCPD2_FRSTX EVENTOUT PB13 SPI2_SCK LPUART1_CTS TIM1_CH1N - USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT PB14 SPI2_MISO UCPD1_FRSTX TIM1_CH2N - USART3_RTS _DE_CK TIM15_CH1 I2C2_SDA EVENTOUT PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT STM32G071x8/xB Table 14. Port B alternate function mapping 49/135 50/135 Table 15. Port C alternate function mapping DS12232 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PC0 LPTIM1_IN1 LPUART1_RX LPTIM2_IN1 - - - - - PC1 LPTIM1_OUT LPUART1_TX TIM15_CH1 - - - - - PC2 LPTIM1_IN2 SPI2_MISO TIM15_CH2 - - - - - PC3 LPTIM1_ETR SPI2_MOSI LPTIM2_ETR - - - - - PC4 USART3_TX USART1_TX TIM2_CH1_ETR - - - - - PC5 USART3_RX USART1_RX TIM2_CH2 - - - - - PC6 UCPD1_FRSTX TIM3_CH1 TIM2_CH3 - - - - - PC7 UCPD2_FRSTX TIM3_CH2 TIM2_CH4 - - - - - PC8 UCPD2_FRSTX TIM3_CH3 TIM1_CH1 - - - - - PC9 I2S_CKIN TIM3_CH4 TIM1_CH2 - - - - - PC10 USART3_TX USART4_TX TIM1_CH3 - - - - - PC11 USART3_RX USART4_RX TIM1_CH4 - - - - - PC12 LPTIM1_IN1 UCPD1_FRSTX TIM14_CH1 - - - - - PC13 - - TIM1_BKIN - - - - - PC14 - - TIM1_BKIN2 - - - - - PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - - STM32G071x8/xB Table 16. Port D alternate function mapping DS12232 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PD0 EVENTOUT SPI2_NSS TIM16_CH1 - - - - - PD1 EVENTOUT SPI2_SCK TIM17_CH1 - - - - - PD2 USART3_RTS _DE_CK TIM3_ETR TIM1_CH1N - - - - - PD3 USART2_CTS SPI2_MISO TIM1_CH2N - - - - - PD4 USART2_RTS _DE_CK SPI2_MOSI TIM1_CH3N - - - - - PD5 USART2_TX SPI1_MISO/ I2S1_MCK TIM1_BKIN - - - - - PD6 USART2_RX SPI1_MOSI/ I2S1_SD LPTIM2_OUT - - - - - PD8 USART3_TX SPI1_SCK/ I2S1_CK LPTIM1_OUT - - - - - PD9 USART3_RX SPI1_NSS/ I2S1_WS TIM1_BKIN2 - - - - - Table 17. Port F alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PF0 - - TIM14_CH1 - - - - - PF1 OSC_EN - TIM15_CH1N - - - - - PF2 MCO - - - - - - - STM32G071x8/xB * 51/135 Electrical characteristics STM32G071x8/xB 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored. Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 11. Pin loading conditions Figure 12. Pin input voltage MCU pin MCU pin C = 50 pF 52/135 VIN DS12232 Rev 4 STM32G071x8/xB 5.1.6 Electrical characteristics Power supply scheme Figure 13. Power supply scheme VBAT Backup circuitry (LSE, RTC and backup registers) 1.55 V to 3.6 V Power switch VDD VCORE VDD/VDDA VDD Regulator OUT 1 x 100 nF + 1 x 4.7 μF GPIOs IN Level shifter VDDIO1 IO logic Kernel logic (CPU, digital and memories) VSS VDDA VREF VREF+ VREF+ 100 nF 1 μF VREF- ADC DAC COMPs VREFBUF VSSA VSS/VSSA MSv47900V1 Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS12232 Rev 4 53/135 107 Electrical characteristics 5.1.7 STM32G071x8/xB Current consumption measurement Figure 14. Current consumption measurement scheme IDDVBAT VBAT VDD (VDDA) IDD VBAT VDD/VDDA MSv47901V1 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are defined with respect to VSS. Table 18. Voltage characteristics Symbol Ratings Min Max VDD External supply voltage - 0.3 4.0 VBAT External supply voltage on VBAT pin - 0.3 4.0 VREF+ External voltage on VREF+ pin - 0.3 Min(VDD + 0.4, 4.0) Input voltage on FT_xx pins except FT_c - 0.3 VDD + 4.0(2) Input voltage on FT_c pins - 0.3 5.5 Input voltage on any other pin - 0.3 4.0 VIN(1) 1. Refer to Table 19 for the maximum allowed injected current values. 2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 54/135 DS12232 Rev 4 Unit V STM32G071x8/xB Electrical characteristics Table 19. Current characteristics Symbol Ratings Max IVDD/VDDA Current into VDD/VDDA power pin (source)(1) 100 IVSS/VSSA (1) 100 Current out of VSS/VSSA ground pin (sink) IIO(PIN) ∑IIO(PIN) Output current sunk by any I/O and control pin except FT_f 15 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 15 Total output current sunk by sum of all I/Os and control pins 80 Total output current sourced by sum of all I/Os and control pins 80 Injected current on a TT_a pin(4) ∑|IINJ(PIN)| mA -5 / NA(3) Injected current on a FT_xx pin IINJ(PIN)(2) Unit -5 / 0 Total injected current (sum of all I/Os and control pins)(5) 25 1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. On these I/Os, any current injection disturbs the analog performances of the device. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 20. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 64 fPCLK Internal APB clock frequency - 0 64 VDD Standard operating voltage - 1.7(1) 3.6 For ADC and COMP operation 1.62 3.6 For DAC operation 1.8 3.6 For VREFBUF operation 2.4 3.6 VDDA Analog supply voltage DS12232 Rev 4 Unit MHz V V 55/135 107 Electrical characteristics STM32G071x8/xB Table 21. General operating conditions (continued) Symbol VBAT Parameter Conditions Min Max Unit - 1.55 3.6 V All except TT_xx and FT_c -0.3 Min(VDD + 3.6, 5.5)(2) TT_xx -0.3 VDD + 0.3 Backup operating voltage VIN I/O input voltage FT_c Ambient temperature(3) TA -0.3 (4) Suffix 6 -40 85 Suffix 7(4) -40 105 (4) -40 125 6(4) -40 105 (4) Suffix 7 -40 125 Suffix 3(4) -40 130 Suffix 3 Suffix TJ Junction temperature 5.0 V (2) °C °C 1. When RESET is released functionality is guaranteed down to VPDR min. 2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled. 3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.9: Thermal characteristics. 4. Temperature range digit in the order code. See Section 7: Ordering information. 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22. Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.3 VDD slew rate Conditions Min Max VDD rising - ∞ VDD falling; ULPEN = 0 10 ∞ VDD falling; ULPEN = 1 100 ∞ Unit µs/V ms/V Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions. Table 23. Embedded reset and power control block characteristics Symbol Parameter Conditions(1) Min Typ Max Unit tRSTTEMPO(2) POR temporization when VDD crosses VPOR VDD rising - 250 400 μs 56/135 VPOR(2) Power-on reset threshold - 1.62 1.66 1.70 V VPDR(2) Power-down reset threshold - 1.60 1.64 1.69 V VBOR1 Brownout reset threshold 1 VDD rising 2.05 2.10 2.18 VDD falling 1.95 2.00 2.08 DS12232 Rev 4 V STM32G071x8/xB Electrical characteristics Table 23. Embedded reset and power control block characteristics (continued) Symbol Parameter VBOR2 Brownout reset threshold 2 VBOR3 Brownout reset threshold 3 VBOR4 Brownout reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_POR_PDR Hysteresis of VPOR and VPDR Conditions(1) Min Typ Max VDD rising 2.20 2.31 2.38 VDD falling 2.10 2.21 2.28 VDD rising 2.50 2.62 2.68 VDD falling 2.40 2.52 2.58 VDD rising 2.80 2.91 3.00 VDD falling 2.70 2.81 2.90 VDD rising 2.05 2.15 2.22 VDD falling 1.95 2.05 2.12 VDD rising 2.20 2.30 2.37 VDD falling 2.10 2.20 2.27 VDD rising 2.35 2.46 2.54 VDD falling 2.25 2.36 2.44 VDD rising 2.50 2.62 2.70 VDD falling 2.40 2.52 2.60 VDD rising 2.65 2.74 2.87 VDD falling 2.55 2.64 2.77 VDD rising 2.80 2.91 3.03 VDD falling 2.70 2.81 2.93 VDD rising 2.90 3.01 3.14 VDD falling 2.80 2.91 3.04 Hysteresis in continuous mode - 20 - Hysteresis in other mode - 30 - Unit V V V V V V V V V V mV Vhyst_BOR_PVD Hysteresis of VBORx and VPVDx - - 100 - mV IDD(BOR_PVD)(2) BOR and PVD consumption - - 1.1 1.6 µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. DS12232 Rev 4 57/135 107 Electrical characteristics 5.3.4 STM32G071x8/xB Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max Unit -40°C < TJ < 130°C 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs IDD(VREFINTBUF) VREFINT buffer consumption from VDD when converted by ADC - - 12.5 20(2) µA ∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV - - 30 50(2) ppm/°C 300 1000(2) ppm - 250 1200(2) ppm/V 24 25 26 49 50 51 74 75 76 TCoeff_vrefint ACoeff VDDCoeff Temperature coefficient Long term stability 1000 hours, T = 25 °C Voltage coefficient VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage 3.0 V < VDD < 3.6 V - - % VREFINT 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Figure 15. VREFINT vs. temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 58/135 DS12232 Rev 4 STM32G071x8/xB 5.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0444 reference manual). • When the peripherals are enabled fPCLK = fHCLK • For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS Unless otherwise stated, values given in Table 25 through Table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. DS12232 Rev 4 59/135 107 Electrical characteristics STM32G071x8/xB Table 25. Current consumption in Run and Low-power run modes at different die temperatures Conditions Symbol Parameter General 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 64 MHz 6.3 6.4 6.8 6.7 7.0 7.7 56 MHz 5.5 5.7 5.9 5.9 6.3 6.8 5.0 5.1 5.4 5.2 5.7 6.3 3.5 3.6 3.8 4.0 4.3 4.7 24 MHz 2.8 2.9 3.1 3.1 3.6 4.0 16 MHz 1.8 1.9 2.1 2.1 2.5 3.0 64 MHz 6.0 6.2 6.4 6.3 6.6 7.0 56 MHz 5.3 5.5 5.7 5.6 5.8 6.2 4.7 4.8 5.0 5.0 5.2 5.6 3.3 3.4 3.5 3.5 3.8 4.1 24 MHz 2.6 2.7 2.9 2.8 3.1 3.4 16 MHz 1.7 1.7 1.9 1.9 2.1 2.7 1.4 1.5 1.7 1.7 2.0 2.6 0.8 0.9 1.0 1.2 1.3 1.8 2 MHz 0.3 0.3 0.5 0.5 0.8 1.4 16 MHz 1.4 1.4 1.6 1.6 1.8 2.2 0.7 0.8 1.0 1.1 1.2 1.6 0.4 0.5 0.6 0.7 0.9 1.5 2 MHz 0.3 0.3 0.5 0.5 0.8 1.2 2 MHz 220 255 420 530 795 1255 105 155 320 505 770 1200 67 105 265 465 700 1110 26 66 230 450 520 1045 17 56 220 375 475 1035 199 231 380 485 700 1220 95 140 290 430 660 1140 61 95 240 365 625 1100 125 kHz 24 59 225 335 440 970 32 kHz 15 55 220 325 355 940 fHCLK 48 MHz Range 1; PLL enabled; fHCLK = fHSE_bypass (≤16 MHz), fHCLK = fPLLRCLK (>16 MHz); (3) IDD(Run) 32 MHz 48 MHz Supply current in Run mode 32 MHz Fetch from(2) Flash memory SRAM 16 MHz Range 2; PLL enabled; fHCLK = fHSE_bypass (≤16 MHz), fHCLK = fPLLRCLK (>16 MHz); (3) 8 MHz 8 MHz 4 MHz Flash memory SRAM 1 MHz 500 kHz IDD(LPRun) Supply current in Low-power run mode Max(1) Typ PLL disabled; 125 kHz fHCLK = fHSE bypass (> 32 kHz), 32 kHz fHCLK = fLSE 2 MHz bypass (= 32 kHz); (3) 1 MHz 500 kHz Flash memory SRAM Unit mA µA 1. Based on characterization results, not tested in production. 2. Prefetch and cache enabled when fetching from Flash memory. Code compiled with high optimization for space in SRAM. 3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled. 60/135 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 26. Typical current consumption in Run and Low-power run modes, depending on code executed Conditions Symbol Typ Parameter General Fetch from(1) 6.4 100 6.2 97 5.9 92 4.6 71 4.6 71 6.2 96 6.2 97 6.0 93 Fibonacci 6.2 96 While(1) loop 4.8 Dhrystone 2.1 Flash memory Fibonacci While(1) loop Reduced code (3) Coremark Dhrystone 2.1 IDD(Run) Supply current in Run mode Reduced SRAM code(3) 1.5 Coremark (2) 91 Fibonacci 1.1 69 While(1) loop 1.1 69 Reduced code(3) 1.5 91 Coremark 1.4 88 1.4 84 Fibonacci 1.5 91 While(1) loop 1.1 69 380 190 395 198 405 203 Fibonacci 385 193 While(1) loop 400 Flash memory SRAM code(3) Coremark Dhrystone 2.1 IDD(LPRun) (2) 94 1.5 Reduced fHCLK = fHSI16/8 = 2 MHz; PLL disabled, 75 94 Dhrystone 2.1 Supply current in Low-power run mode mA 1.5 Dhrystone 2.1 Range 2; fHCLK = fHSI16 = 16 MHz, PLL disabled, Unit 25 °C Coremark (2) Unit 25 °C Code Reduced code(3) Range 1; fHCLK = fPLLRCLK = 64 MHz; Typ Reduced Flash memory code(3) 250 Coremark uA 200 125 245 123 240 120 Fibonacci 250 125 While(1) loop 230 115 Dhrystone 2.1 SRAM μA/MHz uA/MHz 1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM. 2. VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM 3. Reduced code used for characterization results provided in Table 25. DS12232 Rev 4 61/135 107 Electrical characteristics STM32G071x8/xB Table 27. Current consumption in Sleep and Low-power sleep modes Conditions Symbol Parameter Voltage scaling General IDD(Sleep) Supply current in Sleep mode Max(1) Typ fHCLK 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 64 MHz 1.8 1.9 2.1 1.8 2.1 2.9 56 MHz 1.6 1.7 1.9 1.7 1.9 2.8 48 MHz 1.4 1.5 1.7 1.6 1.7 2.7 32 MHz 1.0 1.1 1.3 1.2 1.3 2.3 24 MHz 0.8 0.9 1.1 1.0 1.1 1.9 16 MHz 0.5 0.6 0.8 0.6 0.7 1.7 16 MHz 0.4 0.5 0.7 0.5 0.6 1.4 8 MHz 0.3 0.3 0.5 0.3 0.5 1.2 2 MHz 0.1 0.2 0.4 0.2 0.4 1.1 2 MHz 60 99 265 150 360 1110 1 MHz 33 75 240 130 330 1010 500 kHz 25 64 230 125 250 870 125 kHz 16 55 220 110 235 715 32 kHz 14 53 215 110 225 645 Flash memory enabled; fHCLK = fHSE bypass Range 1 (≤16 MHz; PLL disabled), fHCLK = fPLLRCLK (>16 MHz; PLL enabled); All peripherals disabled Range 2 Flash memory disabled; Supply PLL disabled; current in =f bypass (> 32 kHz), IDD(LPSleep) f Low-power HCLK HSE fHCLK = fLSE bypass (= 32 kHz); sleep mode All peripherals disabled Unit mA µA 1. Based on characterization results, not tested in production. Table 28. Current consumption in Stop 0 mode Conditions Symbol Unit HSI kernel Enabled IDD(Stop 0) Supply current in Stop 0 mode Disabled VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 275 305 430 330 425 750 2.4 V 280 310 435 330 450 850 3V 280 315 435 350 490 950 3.6 V 285 315 440 375 500 1020 1.8 V 95 140 270 120 180 490 2.4 V 100 145 275 125 220 610 3V 100 145 280 125 240 720 3.6 V 105 150 285 130 250 840 1. Based on characterization results, not tested in production. 62/135 Max(1) Typ Parameter DS12232 Rev 4 µA STM32G071x8/xB Electrical characteristics Table 29. Current consumption in Stop 1 mode Conditions Symbol Parameter Flash memory Unit RTC(2) Disabled Not powered IDD(Stop 1) Supply current in Stop 1 mode Enabled Powered Max(1) Typ Disabled VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 3.2 32 150 8 100 480 2.4 V 3.3 32 150 10 120 535 3V 3.4 33 155 15 135 620 3.6 V 3.8 33 155 18 140 705 1.8 V 3.4 32 150 9 100 480 2.4 V 3.7 32 155 11 120 540 3V 4.0 33 155 16 140 630 3.6 V 4.4 34 160 20 145 720 1.8 V 6.9 36 155 12 100 575 2.4 V 7.3 36 160 14 110 600 3V 7.3 37 160 18 120 645 3.6 V 7.8 38 160 23 135 665 µA 1. Based on characterization results, not tested in production. 2. Clocked by LSI Table 30. Current consumption in Standby mode Symbol Parameter Conditions General RTC disabled RTC enabled, clocked by LSI; IDD(Standby) Supply current in Standby mode(2) IWDG enabled, clocked by LSI ULPEN = 0 Max(1) Typ VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 0.07 1.7 6.7 0.7 9 34 2.4 V 0.13 2.1 8.1 0.8 12 38 3.0 V 0.20 2.5 10.0 0.9 14 46 3.6 V 0.34 3.0 12.0 1.0 16 55 1.8 V 0.35 2.0 7.0 0.8 10 35 2.4 V 0.49 2.4 8.4 1.0 12 40 3.0 V 0.66 2.9 10.5 1.3 15 47 3.6 V 0.90 3.5 12.5 2.2 18 56 1.8 V 0.26 1.9 6.8 0.8 10 34 2.4 V 0.37 2.3 8.3 1.0 12 39 3.0 V 0.49 2.7 10.3 1.4 15 45 3.6 V 0.69 3.3 12.3 2.1 18 52 1.8 V 0.70 1.6 6.6 - - - 2.4 V 0.89 2.0 8.0 - - - 3.0 V 1.10 2.4 9.8 - - - 3.6 V 1.30 2.9 11.8 - - - DS12232 Rev 4 Unit µA 63/135 107 Electrical characteristics STM32G071x8/xB Table 30. Current consumption in Standby mode (continued) Symbol ∆IDD(SRAM) Conditions Parameter General Extra supply current to retain SRAM content(3) SRAM retention enabled Max(1) Typ VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 0.49 3.0 14.8 0.6 16 58 2.4 V 0.57 3.1 14.9 1.1 17 63 3.0 V 0.67 3.2 15.0 1.5 17 67 3.6 V 0.77 3.3 15.0 1.9 18 71 Unit µA 1. Based on characterization results, not tested in production. 2. Without SRAM retention and with ULPEN bit set 3. To be added to IDD(Standby) as appropriate Table 31. Current consumption in Shutdown mode Symbol Conditions Parameter RTC VDD Disabled IDD(Shutdown) Supply current in Shutdown mode Enabled, clocked by LSE bypass at 32.768 kHz Max(1) Typ 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 1.8 V 17 515 4500 250 3000 32600 2.4 V 23 600 5150 450 3500 33600 3.0 V 33 730 6450 1075 4250 37400 3.6 V 53 940 7700 1250 5300 43600 1.8 V 205 710 4700 900 4500 27300 2.4 V 300 890 5500 1550 5500 34800 3.0 V 420 1150 6800 2475 6000 40900 3.6 V 565 1450 8100 3250 7000 48500 Unit nA 1. Based on characterization results, not tested in production. Table 32. Current consumption in VBAT mode Symbol Parameter Conditions RTC Enabled, clocked by LSE bypass at 32.768 kHz IDD(VBAT) Supply current in VBAT mode Enabled, clocked by LSE crystal at 32.768 kHz Disabled 64/135 DS12232 Rev 4 Typ VDD 25°C 85°C 125°C 1.8 V 165 170 620 2.4 V 260 355 970 3.0 V 365 475 1200 3.6 V 505 655 2070 1.8 V 290 390 960 2.4 V 370 480 1150 3.0 V 470 600 1650 3.6 V 600 815 2250 1.8 V 1 80 660 2.4 V 2 90 750 3.0 V 2 105 1200 3.6 V 6 200 1700 Unit nA STM32G071x8/xB Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 51: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 33: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIO1 × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIO1 is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DS12232 Rev 4 65/135 107 Electrical characteristics STM32G071x8/xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 18: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 33. Current consumption of peripherals Consumption in µA/MHz Peripheral Range 1 Range 2 Low-power run and sleep IOPORT Bus IOPORT 1.0 0.7 0.5 GPIOA IOPORT 3.4 2.8 3.0 GPIOB IOPORT 3.1 2.6 2.5 GPIOC IOPORT 2.9 2.5 3.0 GPIOD IOPORT 1.8 1.5 1.5 GPIOF IOPORT 0.7 0.6 1.0 Bus matrix AHB 3.2 2.2 2.8 All AHB Peripherals AHB 15.0 12.5 14.0 DMA1/DMAMUX AHB 4.7 3.8 4.5 CRC AHB 0.5 0.4 0.5 FLASH AHB 4.1 3.5 4.0 All APB peripherals APB 46.5 47.5 48.0 APB 0.2 0.2 0.1 PWR APB 0.4 0.3 0.5 SYSCFG/VREFBUF/COMP APB 0.4 0.4 0.3 AHB to APB 66/135 Bus bridge(1) WWDG APB 0.4 0.3 0.5 TIM1 APB 7.3 6.1 6.5 TIM2 APB 4.7 3.8 5.0 TIM3 APB 3.6 3.0 2.5 TIM6 APB 0.7 0.6 0.5 TIM7 APB 0.7 0.7 1.0 TIM14 APB 1.5 1.2 1.5 TIM15 APB 4.0 3.3 3.0 TIM16 APB 2.3 2.0 2.0 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 33. Current consumption of peripherals (continued) Consumption in µA/MHz Peripheral Bus Range 1 Range 2 Low-power run and sleep TIM17 APB 0.7 0.7 0.5 LPTIM1 APB 3.2 2.7 3.0 LPTIM2 APB 3.1 2.5 3.0 I2C1 APB 3.8 3.1 3.5 I2C2 APB 0.7 0.6 1.0 SPI2 APB 1.5 1.2 1.0 USART1 APB 7.2 6.0 6.5 USART2 APB 7.2 6.0 6.0 USART3 APB 2.0 1.7 2.0 USART4 APB 2.0 1.7 2.0 LPUART1 APB 4.3 3.5 4.0 CEC APB 0.4 0.3 0.5 UCPD1 APB 4.0 7.7 NA(2) UCPD2 APB 4.0 7.7 NA(2) ADC APB 2.0 1.7 2.0 DAC APB 2.2 1.8 2.0 1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB. 2. UCPDx are always clocked by HSI16. 5.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 34 are the latency between the event and the execution of the first user instruction. Table 34. Low-power mode wakeup times(1) Symbol Parameter Conditions Typ Max tWUSLEEP Wakeup time from Sleep to Run mode - 11 11 Wakeup time from Transiting to Low-power-run-mode execution in Flash tWULPSLEEP Low-power sleep memory not powered in Low-power sleep mode; mode HCLK = HSI16 / 8 = 2 MHz DS12232 Rev 4 Unit CPU cycles 11 14 67/135 107 Electrical characteristics STM32G071x8/xB Table 34. Low-power mode wakeup times(1) (continued) Symbol tWUSTOP0 Parameter Conditions Typ Max 5.6 6 Transiting to Run-mode execution in Flash memory not powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Wakeup time from Regulator in Range 1 or Range 2 Stop 0 Transiting to Run-mode execution in SRAM or in Flash µs memory powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2 Transiting to Run-mode execution in Flash memory not powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2 tWUSTOP1 Unit 2 2.4 9.0 11.2 5 7.5 Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Wakeup time from Regulator in Range 1 or Range 2 Stop 1 Transiting to Low-power-run-mode execution in Flash µs memory not powered in Stop 1 mode; HCLK = HSI16/8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1) 22 25.3 18 23.5 tWUSTBY Transiting to Run mode; Wakeup time from HCLK = HSI16 = 16 MHz; Standby mode Regulator in Range 1 14.5 30 µs tWUSHDN Transiting to Run mode; Wakeup time from HCLK = HSI16 = 16 MHz; Shutdown mode Regulator in Range 1 258 340 µs tWULPRUN Wakeup time from Transiting to Run mode; Low-power run HSISYS = HSI16/8 = 2 MHz mode(2) 5 7 µs Transiting to Low-power-run-mode execution in SRAM or in Flash memory powered in Stop 1 mode; HCLK = HSI16 / 8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1) 1. Based on characterization results, not tested in production. 2. Time until REGLPF flag is cleared in PWR_SR2. Table 35. Regulator mode transition times(1) Symbol tVOST Parameter Conditions Transition times between regulator Range 1 and Range 2(2) HSISYS = HSI16 1. Based on characterization results, not tested in production. 2. Time until VOSF flag is cleared in PWR_SR2. 68/135 DS12232 Rev 4 Typ Max Unit 20 40 µs STM32G071x8/xB Electrical characteristics Table 36. Wakeup time using LPUART(1) Symbol Parameter tWULPUART Conditions Stop mode 0 Wakeup time needed to calculate the maximum LPUART baud rate allowing to wakeup up from Stop mode when LPUART clock source is HSI16 Stop mode 1 Typ Max - 1.7 - 8.5 Unit µs 1. Guaranteed by design. 5.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 16 for recommended clock input waveform. Table 37. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 Unit MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1 VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIO1 Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 tw(HSEH) OSC_IN high or low time tw(HSEL) V ns - - 1. Guaranteed by design. Figure 16. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tw(HSEL) t THSE MS19214V2 DS12232 Rev 4 69/135 107 Electrical characteristics STM32G071x8/xB Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 17 for recommended clock input waveform. Table 38. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1 VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIO1 - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 17. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) t tf(LSE) tw(LSEL) TLSE MS19215V2 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 39. HSE oscillator characteristics(1) Symbol fOSC_IN RF 70/135 Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ Parameter DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 39. HSE oscillator characteristics(1) (continued) Symbol Parameter Conditions(2) Min Typ Max - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Maximum critical crystal transconductance Startup - - 1.5 mA/V Startup time VDD is stabilized - 2 - ms During startup IDD(HSE) Gm tSU(HSE)(4) HSE current consumption (3) Unit mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. DS12232 Rev 4 71/135 107 Electrical characteristics STM32G071x8/xB Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - Unit nA µA/V 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 72/135 DS12232 Rev 4 s STM32G071x8/xB 3. Electrical characteristics tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 5.3.8 Internal clock source characteristics The parameters given in Table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 41. HSI16 oscillator characteristics(1) Symbol fHSI16 Parameter Conditions Min Typ Max Unit 15.88 - 16.08 MHz HSI16 Frequency VDD=3.0 V, TA=30 °C ∆Temp(HSI16) HSI16 oscillator frequency drift over temperature TA= 0 to 85 °C -1 - 1 % TA= -40 to 125 °C -2 - 1.5 % ∆VDD(HSI16) HSI16 oscillator frequency drift over VDD -0.1 - 0.05 % -8 -6 -4 -5.8 -3.8 -1.8 0.2 0.3 0.4 VDD=1.62 V to 3.6 V From code 127 to 128 TRIM From code 63 to 64 HSI16 frequency user trimming step From code 191 to 192 For all other code increments DHSI16(2) tsu(HSI16)(2) % Duty Cycle - 45 - 55 % HSI16 oscillator start-up time - - 0.8 1.2 μs DS12232 Rev 4 73/135 107 Electrical characteristics STM32G071x8/xB Table 41. HSI16 oscillator characteristics(1) (continued) Symbol tstab(HSI16) Parameter (2) IDD(HSI16)(2) Conditions Min Typ Max Unit HSI16 oscillator stabilization time - - 3 5 μs HSI16 oscillator power consumption - - 155 190 μA 1. Based on characterization results, not tested in production. 2. Guaranteed by design. Figure 20. HSI16 frequency vs. temperature MHz 16.4 +2% 16.3 +1.5% 16.2 +1% 16.1 16 15.9 -1% 15.8 -1.5% 15.7 -2% 15.6 -40 -20 0 20 40 min 60 mean 80 100 120 °C max MSv39299V1 Low-speed internal (LSI) RC oscillator Table 42. LSI oscillator characteristics(1) Symbol Parameter LSI frequency fLSI tSU(LSI)(2) (2) tSTAB(LSI) IDD(LSI)(2) Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - 80 130 μs - 125 180 μs - 110 180 nA LSI oscillator start-up time LSI oscillator stabilization time 5% of final frequency LSI oscillator power consumption - 1. Based on characterization results, not tested in production. 2. Guaranteed by design. 74/135 DS12232 Rev 4 Unit kHz STM32G071x8/xB 5.3.9 Electrical characteristics PLL characteristics The parameters given in Table 43 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions. Table 43. PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock frequency(2) - 2.66 - 16 MHz DPLL_IN PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.09 - 122 Voltage scaling Range 2 3.09 - 40 Voltage scaling Range 1 12 - 128 Voltage scaling Range 2 12 - 33 Voltage scaling Range 1 12 - 64 Voltage scaling Range 2 12 - 16 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 96 - 128 - 15 40 - 50 - - 40 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time - RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 56 MHz MHz MHz MHz MHz μs ±ps μA 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. 5.3.10 Flash memory characteristics Table 44. Flash memory characteristics(1) Symbol tprog Parameter Row (32 double word) programming time tprog_page Page (2 Kbyte) programming time tprog_bank tME Typ Max Unit - 85 125 µs Normal programming 2.7 4.6 Fast programming 1.7 2.8 Normal programming 21.8 36.6 Fast programming 13.7 22.4 22.0 40.0 Normal programming 1.4 2.4 Fast programming 0.9 1.4 22.1 40.1 64-bit programming time tprog_row tERASE Conditions Page (2 Kbyte) erase time - Bank (128 Kbyte(2)) programming time Mass erase time - DS12232 Rev 4 ms s ms 75/135 107 Electrical characteristics STM32G071x8/xB Table 44. Flash memory characteristics(1) (continued) Symbol IDD(FlashA) IDD(FlashP) Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Programming 3 - Page erase 3 - Mass erase 3 - Programming, 2 µs peak duration 7 - Erase, 41 µs peak duration 7 - Unit mA mA 1. Guaranteed by design. 2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank Table 45. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = -40 to +105 °C 1 kcycle(2) 10 kcycles 30 at TA = 105 °C 15 1 kcycle(2) at TA = 125 °C 7 10 kcycles(2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 1 kcycle Data retention Unit at TA = 85 °C (2) tRET Min(1) (2) 10 kcycles at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 46. They are based on the EMS levels and classes defined in application note AN1709. 76/135 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 46. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 64 MHz, LQFP64, conforming to IEC 61000-4-2 2B VEFTB VDD = 3.3 V, TA = +25 °C, Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a fHCLK = 64 MHz, LQFP64, functional disturbance conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • corrupted program counter • unexpected reset • critical data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. DS12232 Rev 4 77/135 107 Electrical characteristics STM32G071x8/xB Table 47. EMI characteristics Symbol Parameter Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8 MHz / 64 MHz SEMI Peak level VDD = 3.6 V, TA = 25 °C, LQFP64 package compliant with IEC 61967-2 0.1 MHz to 30 MHz 7 30 MHz to 130 MHz -1 130 MHz to 1 GHz 8 1 GHz to 2 GHz 7 EMI level 5.3.12 dBµV 2.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 48. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001 2 2000 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002 C2a 500 Unit V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current is injected to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 49. Electrical sensitivity Symbol LU 78/135 Parameter Static latch-up class Conditions TA = +125 °C conforming to JESD78 DS12232 Rev 4 Class II Level A STM32G071x8/xB 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 50. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Injected current on pin Unit Negative injection Positive injection All except PA4, PA5, PA6, PB0, PB3, and PC0 -5 N/A mA PA4, PA5 -5 0 mA PA6, PB0, PB3, and PC0 0 N/A mA 1. Based on characterization results, not tested in production. DS12232 Rev 4 79/135 107 Electrical characteristics 5.3.14 STM32G071x8/xB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 51. I/O static characteristics Symbol VIL(1) Parameter I/O input low level voltage Conditions All except 1.62 V < VDDIO1 < 3.6 V FT_c FT_c VIH(1) I/O input high level voltage Vhys(3) I/O input hysteresis Ilkg Input leakage current(3) FT_c FT_d TT_a 1.62 V < VDDIO1 < 2.7 V - - 0.39 x VDDIO1 - 0.06 (3) V 0.3 x VDDIO1 - 0.25 x VDDIO1 2) - - 0.49 x VDDIO1 + 0.26(3) - - 0.7 x VDDIO1 - 5 - 200 - 0 < VIN ≤ VDDIO1 - - ±70 VDDIO1 ≤ VIN ≤ VDDIO1+1 V - - 600(4) VDDIO1 +1 V < VIN ≤ 5.5 V(3) - - 150(4) 0 < VIN ≤ VDDIO1 - - 2000 VDDIO1 < VIN ≤ 5 V - - 3000(4) 0 < VIN ≤ VDDIO1 - - 4500 VDDIO1 < VIN ≤ 5.5 V - - 9000(4) 0 < VIN ≤ VDDIO1 - - ±150 VDDIO1 < VIN ≤ VDDIO1 + 0.3 V - - 2000(4) 25 40 55 kΩ 25 40 55 kΩ - 5 - pF 1.62 V < VDDIO1 < 3.6 V Weak pull-up equivalent resistor RPD Weak pull-down V = VDDIO1 equivalent resistor(5) IN CIO I/O pin capacitance VIN = VSS - 1. Refer to Figure 21: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 80/135 Unit - RPU (5) Max (2) - - TT_xx, FT_xx, 1.62 V < VDDIO1 < 3.6 V NRST FT_xx except FT_c and FT_d Typ 0.3 x VDDIO1 2.7 V < VDDIO1 < 3.6 V All except 1.62 V < VDDIO1 < 3.6 V FT_c FT_c Min DS12232 Rev 4 0.7 x VDDIO1 ( V mV nA STM32G071x8/xB Electrical characteristics 4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max). 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 21. Figure 21. I/O input characteristics 3 2.5 Minimum required logic level 1 zone TTL standard requirement nt) 2 rd r tanda Ss (CMO VIN (V) 1.5 V IHmin = 0.7 eme equir V DDIO 0.49 VD VIHmin = DIO Undefined input range + 0.26 1 VILmax = 0.39 0.5 VILmax = 0.3 VDDIO - 0.06 dard (CMOS stan VDDIO TTL standard requirement t) requiremen Minimum required logic level 0 zone 0 1.6 1.8 2.0 2.2 Device characteristics 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDDIO (V) Test thresholds MSv47925V1 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to ±15 mA with relaxed VOL/VOH. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: • The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 18: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 18: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in DS12232 Rev 4 81/135 107 Electrical characteristics STM32G071x8/xB Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 52. Output voltage characteristics(1) Symbol Parameter Conditions VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Min Max - 0.4 VDDIO1 - 0.4 - - 0.4 2.4 - - 1.3 VDDIO1 - 1.3 - - 0.4 VDDIO1 - 0.45 - - 0.4 - 0.4 (2) CMOS port |IIO| = 2 mA for FT_c I/Os = 6 mA for other I/Os VDDIO1 ≥ 2.7 V TTL port(2) |IIO| = 2 mA for FT_c I/Os = 6 mA for other I/Os VDDIO1 ≥ 2.7 V All I/Os except FT_c |IIO| = 15 mA VDDIO1 ≥ 2.7 V |IIO| = 1 mA for FT_c I/Os = 3 mA for other I/Os VDDIO1 ≥ 1.62 V |IIO| = 20 mA VDDIO1 ≥ 2.7 V VOLFM+ Output low level voltage for an FT I/O (3) pin in FM+ mode (FT I/O with _f option) |I | = 9 mA IO VDDIO1 ≥ 1.62 V Unit V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 53, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 53. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf 82/135 Output rise and fall time Min Max C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V Conditions - 2 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 0.35 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 3 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 0.45 C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 100 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 225 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 75 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 150 DS12232 Rev 4 Unit MHz ns STM32G071x8/xB Electrical characteristics Table 53. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 01 Tr/Tf Fmax Output rise and fall time Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency Output fall time(4) Min Max C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V Conditions - 10 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2.5 C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 60 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30 C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 15 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30 C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 11 C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 22 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 4 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 8 C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60 C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 80(3) C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 40 C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 5.5 C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 11 C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2.5 C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 5 - 1 MHz - 5 ns C=50 pF, 1.6 V ≤ VDDIO1 ≤ 3.6 V Unit MHz ns MHz ns MHz ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0444 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz. 4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification. DS12232 Rev 4 83/135 107 Electrical characteristics STM32G071x8/xB Figure 22. I/O AC characteristics definition(1) 90% 10% 50% 50% 10% 90% t f(IO)out t r(IO)out T Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%) when loaded by the specified capacitance. MS32132V2 1. Refer to Table 53: I/O AC characteristics. 5.3.15 NRST input characteristics The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU. Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 54. NRST pin characteristics(1) Symbol Parameter Conditions Min Typ Max - - 0.3 x VDDIO1 Unit VIL(NRST) NRST input low level voltage - VIH(NRST) NRST input high level voltage - 0.7 x VDDIO1 - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ - - - 70 ns 1.7 V ≤ VDD ≤ 3.6 V 350 - - ns VF(NRST) NRST input filtered pulse VNF(NRST) NRST input not filtered pulse 1. V Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 84/135 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Figure 23. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF MS19878V3 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 54: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 5.3.16 Analog switch booster Table 55. Analog switch booster characteristics(1) Symbol VDD Parameter Min Typ Max Unit 1.62 V - 3.6 V Booster startup time - - 240 µs Booster consumption for 1.62 V ≤ VDD ≤ 2.0 V - - 250 Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V - - 500 Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V - - 900 Supply voltage tSU(BOOST) IDD(BOOST) µA 1. Guaranteed by design. 5.3.17 Analog-to-digital converter characteristics Unless otherwise specified, the parameters given in Table 56 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 56. ADC characteristics(1) Symbol Parameter Conditions(2) Min Typ Max Unit VDDA Analog supply voltage - 1.62 - 3.6 V VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA VDDA < 2 V DS12232 Rev 4 VDDA V 85/135 107 Electrical characteristics STM32G071x8/xB Table 56. ADC characteristics(1) (continued) Conditions(2) Min Typ Max Range 1 0.14 - 35 Range 2 0.14 - 16 12 bits - - 2.50 10 bits - - 2.92 8 bits - - 3.50 6 bits - - 4.38 fADC = 35 MHz; 12 bits - - 2.33 12 bits - - fADC/15 Conversion voltage range - VSSA - VREF+ V RAIN External input impedance - - - 50 kΩ CADC Internal sample and hold capacitor - - 5 - pF tSTAB ADC power-up time - 2 Conversion cycle tCAL Calibration time fADC = 35 MHz 2.35 µs - 82 1/fADC Symbol fADC fs fTRIG VAIN (3) Parameter ADC clock frequency Sampling rate External trigger frequency CKMODE = 00 tLATR ts Trigger conversion latency Sampling time ADC voltage regulator tADCVREG_STUP start-up time tCONV tIDLE 86/135 Total conversion time (including sampling time) Laps of time allowed between two conversions without rearm 2 - CKMODE = 01 6.5 CKMODE = 10 12.5 CKMODE = 11 3.5 3 Unit MHz MSps MHz 1/fADC 1/fPCLK fADC = 35 MHz; VDDA > 2V 0.043 - 4.59 µs 1.5 - 160.5 1/fADC fADC = 35 MHz; VDDA < 2V 0.1 - 4.59 µs 160.5 1/fADC - - - 20 µs fADC = 35 MHz Resolution = 12 bits 0.40 - 4.95 µs Resolution = 12 bits - DS12232 Rev 4 3.5 ts + 12.5 cycles for successive approximation = 14 to 173 - - 100 1/fADC µs STM32G071x8/xB Electrical characteristics Table 56. ADC characteristics(1) (continued) Symbol IDDA(ADC) IDDV(ADC) Parameter ADC consumption from VDDA ADC consumption from VREF+ Conditions(2) Min Typ Max fs = 2.5 MSps - 410 - fs = 1 MSps - 164 - fs = 10 kSps - 17 - fs = 2.5 MSps - 65 - fs = 1 MSps - 26 - fs = 10 kSps - 0.26 - Unit µA µA 1. Guaranteed by design 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details. Table 57. Maximum ADC RAIN . Resolution 12 bits Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) 1.5(3) 43 50 3.5 100 680 7.5 214 2200 12.5 357 4700 19.5 557 8200 39.5 1129 15000 79.5 2271 33000 160.5 4586 50000 43 68 3.5 100 820 7.5 214 3300 12.5 357 5600 19.5 557 10000 39.5 1129 22000 79.5 2271 39000 160.5 4586 50000 (3) 1.5 10 bits DS12232 Rev 4 87/135 107 Electrical characteristics STM32G071x8/xB Table 57. Maximum ADC RAIN . (continued) Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) 1.5(3) 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 8 bits (3) 1.5 6 bits 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. Only allowed with VDDA > 2 V Table 58. ADC accuracy(1)(2)(3) Symbol ET 88/135 Parameter Total unadjusted error Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 3 4 2 V < VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 3 6.5 1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 3 7.5 DS12232 Rev 4 Unit LSB STM32G071x8/xB Electrical characteristics Table 58. ADC accuracy(1)(2)(3) (continued) Symbol EO EG ED EL Parameter Offset error Gain error Differential linearity error Integral linearity error Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 1.5 2 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 1.5 4.5 1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 1.5 5.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 3 3.5 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 3 5 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 3 6.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 1.2 1.5 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 1.2 1.5 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 1.2 1.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 2.5 3 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 2.5 3 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 2.5 3.5 DS12232 Rev 4 Unit LSB LSB LSB LSB 89/135 107 Electrical characteristics STM32G071x8/xB Table 58. ADC accuracy(1)(2)(3) (continued) Symbol ENOB SINAD SNR Parameter Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 10.1 10.2 - 2 V < VDDA = VREF+ < 3.6 V; Effective fADC = 35 MHz; fs ≤ 2.5 MSps; number of bits TA = entire range 9.6 10.2 - 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; 9.5 10.2 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 62.5 63 - 59.5 63 - 59 63 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 63 64 - 2 V < VDDA = VREF+ < 3.6 V; Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range ratio 60 64 - 60 64 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - -74 -73 2 V < VDDA = VREF+ < 3.6 V; Total harmonic fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range distortion - -74 -70 - -74 -70 2 V < VDDA = VREF+ < 3.6 V; Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps; and distortion TA = entire range ratio 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; THD 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; 1. Based on characterization results, not tested in production. 2. ADC DC accuracy values are measured after internal calibration. 3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current. 4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 90/135 DS12232 Rev 4 Unit bit dB dB dB STM32G071x8/xB Electrical characteristics Figure 24. ADC accuracy characteristics EG Code (1) Example of an actual transfer curve 4095 (2) Ideal transfer curve 4094 (3) End point correlation line 4093 ET total unadjusted error: maximum deviation between the actual and ideal transfer curves. (2) ET EO offset error: maximum deviation between the first actual transition and the first ideal one. (3) 7 (1) 6 EG gain error: deviation between the last ideal transition and the last actual one. 5 EL EO ED differential linearity error: maximum deviation between actual steps and the ideal ones. 4 3 ED EL integral linearity error: maximum deviation between any actual transition and the end point correlation line. 2 1 LSB ideal 1 0 1 2 3 4 5 6 7 4093 4094 4095 (VAIN / VREF+)*4095 MSv19880V3 Figure 25. Typical connection diagram using the ADC VDDA VT RAIN(1) VAIN Sample and hold ADC converter RADC AINx Cparasitic(2) VT Ilkg (3) 12-bit converter CADC MS33900V5 1. Refer to Table 56: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 51: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 51: I/O static characteristics for the values of Ilkg. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DS12232 Rev 4 91/135 107 Electrical characteristics 5.3.18 STM32G071x8/xB Digital-to-analog converter characteristics Table 59. DAC characteristics(1) Symbol VDDA VREF+ Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ Max Unit DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 3.6 V Other modes 1.80 - DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 VDDA V Other modes 1.80 - connected to VSSA 5 - - connected to VDDA 25 - - 9.6 11.7 13.8 RL Resistive load DAC output buffer ON RO Output Impedance DAC output buffer OFF Output impedance sample and hold mode, output buffer ON VDD = 2.7 V - - 2 RBON VDD = 2.0 V - - 3.5 Output impedance sample and hold mode, output buffer OFF VDD = 2.7 V - - 16.5 RBOFF VDD = 2.0 V - - 18.0 DAC output buffer ON - - 50 pF Sample and hold mode - 0.1 1 µF DAC output buffer ON 0.2 - VREF+ – 0.2 V DAC output buffer OFF 0 - VREF+ ±0.5 LSB - 1.7 3 ±1 LSB - 1.6 2.9 ±2 LSB - 1.55 2.85 ±4 LSB - 1.48 2.8 ±8 LSB - 1.4 2.75 CL CSH VDAC_OUT tSETTLING tWAKEUP(2) PSRR 92/135 Capacitive load Voltage on DAC_OUT output Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF - 2 2.5 Wakeup time from off state (setting the ENx bit in the DAC Control register) until final value ±1 LSB Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - 4.2 7.5 Normal mode DAC output buffer OFF, CL ≤ 10 pF - 2 5 Normal mode DAC output buffer ON CL ≤ 50 pF, RL = 5 kΩ, DC - -80 -28 VDDA supply rejection ratio DS12232 Rev 4 kΩ kΩ kΩ kΩ µs µs dB STM32G071x8/xB Electrical characteristics Table 59. DAC characteristics(1) (continued) Symbol Parameter TW_to_W Minimum time between two consecutive writes into the DAC_DORx register to guarantee a correct DAC_OUT for a small variation of the input code (1 LSB) tSAMP Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when DACOUT reaches final value ±1LSB) Conditions DAC_MCR:MODEx[2:0] = 000 or 001 CL ≤ 50 pF; RL ≥ 5 kΩ DAC_MCR:MODEx[2:0] = 010 or 011 CL ≤ 10 pF µs 0.7 3.5 - 10.5 18 - 2 3.5 µs - - -(3) nA 5.2 7 8.8 pF 50 - - µs - 1500 - - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.2 DAC output buffer OFF Sample and hold mode, DAC_OUT pin connected CIint Internal sample and hold capacitor tTRIM Middle code offset trim time DAC output buffer ON Voffset Middle code offset for 1 trim VREF+ = 3.6 V code step VREF+ = 1.8 V - DAC output buffer OFF - - Output leakage current DAC consumption from VDDA 1 Unit - Ileak IDDA(DAC) Max - DAC_OUT pin connected DAC output buffer OFF, CSH = 100 nF DAC output buffer ON Typ 1.4 DAC output buffer ON, CSH = 100 nF DAC_OUT pin not connected (internal connection only) Min Sample and hold mode, CSH = 100 nF DS12232 Rev 4 ms - µV µA 315 ₓ 670 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) 93/135 107 Electrical characteristics STM32G071x8/xB Table 59. DAC characteristics(1) (continued) Symbol Parameter Conditions DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ DAC output buffer OFF Min Typ Max No load, middle code (0x800) - 185 240 No load, worst code (0xF1C) - 340 400 No load, middle code (0x800) - 155 205 Unit µA Sample and hold mode, buffer ON, CSH = 100 nF, worst case - 185 ₓ 400 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) Sample and hold mode, buffer OFF, CSH = 100 nF, worst case - 155 ₓ 205 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) 1. Guaranteed by design. 2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). 3. Refer to Table 51: I/O static characteristics. 4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details. Figure 26. 12-bit buffered / non-buffered DAC Buffered / non-buffered DAC Buffer(1) RLOAD 12-bit digital-to-analog converter DAC_OUTx CLOAD MSv47959V1 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 94/135 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 60. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain TUE TUECal SNR THD Offset error at code 0x800(3) Offset error at code 0x001(4) Conditions Min Typ Max DAC output buffer ON - - ±2 DAC output buffer OFF - - ±2 guaranteed DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±4 VREF+ = 3.6 V - - ±12 VREF+ = 1.8 V - - ±25 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±8 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±5 VREF+ = 3.6 V - - ±5 VREF+ = 1.8 V - - ±7 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±0.5 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±30 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±12 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±23 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ 1 kHz, BW 500 kHz - 71.2 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz BW 500 kHz - 71.6 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -78 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - -79 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ Offset Error at DAC output buffer ON code 0x800 CL ≤ 50 pF, RL ≥ 5 kΩ after calibration (5) Gain error Total unadjusted error Total unadjusted error after calibration Signal-to-noise ratio Total harmonic distortion Unit LSB DS12232 Rev 4 % LSB LSB dB dB 95/135 107 Electrical characteristics STM32G071x8/xB Table 60. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2. Difference between two consecutive codes - 1 LSB. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON. 5.3.19 Voltage reference buffer characteristics Table 61. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Degraded mode(2) iload = 100 µA Voltage reference output T = 30 °C Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 VRS = 0 2.038 2.042 2.046 VRS = 1 2.497 2.5 2.503 VRS = 0 VDDA-150 mV - VDDA VRS = 1 VDDA-150 mV - VDDA Unit V Trim step resolution - - - ±0.05 ±0.1 % CL Load capacitor - - 0.5 1 1.5 µF esr Equivalent Serial Resistor of Cload - - - - 2 Ω Iload Static load current - - - - 4 mA Iload = 500 µA - 200 1000 Iload = 4 mA - 100 500 - 50 500 TRIM Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode 96/135 DS12232 Rev 4 ppm/V ppm/mA STM32G071x8/xB Electrical characteristics Table 61. VREFBUF characteristics(1) (continued) Symbol Parameter Temperature TCoeff_vrefbuf coefficient of VREFBUF(3) PSRR tSTART Power supply rejection Start-up time Conditions Min Typ Max Unit - - 50 ppm/ °C DC 40 60 - 100 kHz 25 40 - CL = 0.5 µF(4) - 300 350 (4) - 500 650 µF(4) - 650 800 - 8 - Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 -40 °C < TJ < +125 °C CL = 1.1 µF CL = 1.5 IINRUSH IDDA(VREFB UF) Control of maximum DC current drive on VREFBUF_OUT during start-up phase (5) VREFBUF consumption from VDDA - dB µs mA µA 1. Guaranteed by design. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf. 4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise. 5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1. 5.3.20 Comparator characteristics Table 62. COMP characteristics(1) Symbol Conditions Min Typ Max Unit Analog supply voltage - 1.62 - 3.6 V VIN Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA IDDA(SCALER) Parameter Scaler static consumption from VDDA tSTART_SCALER Scaler startup time VREFINT V - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs - DS12232 Rev 4 97/135 107 Electrical characteristics STM32G071x8/xB Table 62. COMP characteristics(1) (continued) Symbol Parameter Comparator startup time to reach propagation delay specification tSTART tD Propagation delay Comparator offset error Voffset Comparator hysteresis Vhys IDDA(COMP) Comparator consumption from VDDA Conditions Min Typ Max - - 5 High-speed mode Unit µs Medium-speed mode - - 15 200 mV step; 100 mV overdrive High-speed mode - 30 50 ns Medium-speed mode - 0.3 0.6 µs >200 mV step; 100 mV overdrive High-speed mode - - 70 ns Medium-speed mode - - 1.2 µs Full common mode range - ±5 ±20 mV No hysteresis - 0 - Low hysteresis - 10 - Medium hysteresis - 20 - High hysteresis - 30 - Medium-speed mode; No deglitcher Static - 5 7.5 With 50 kHz and ±100 mV overdrive square signal - 6 - Medium-speed mode; With deglitcher Static - 7 10 With 50 kHz and ±100 mV overdrive square signal - 8 - Static - 250 400 With 50 kHz and ±100 mV overdrive square signal - 250 - High-speed mode mV µA 1. Guaranteed by design. 2. Refer to Table 24: Embedded internal voltage reference. 5.3.21 Temperature sensor characteristics Table 63. TS characteristics Symbol Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.785 V tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs Start-up time when entering in continuous mode(4) - 70 120 µs TL(1) Avg_Slope(2) V30 tSTART(1) 98/135 Parameter VTS linearity with temperature Average slope Voltage at 30°C (±5 °C)(3) DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 63. TS characteristics (continued) Symbol Parameter Min Typ Max Unit tS_temp(1) ADC sampling time when reading the temperature 5 - - µs IDD(TS)(1) Temperature sensor consumption from VDD, when selected by ADC - 4.7 7 µA 1. Guaranteed by design. 2. Based on characterization results, not tested in production. 3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. 4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 5.3.22 VBAT monitoring characteristics Table 64. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading the VBAT 12 - - µs Er(1) (1) tS_vbat 1. Guaranteed by design. Table 65. VBAT charging characteristics Symbol RBC 5.3.23 Parameter Battery charging resistor Conditions Min Typ Max VBRS = 0 - 5 - VBRS = 1 - 1.5 - Unit kΩ Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 66. TIMx(1) characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT ResTIM Conditions Min Max Unit - 1 - tTIMxCLK 15.625 - ns 0 fTIMxCLK/2 0 40 TIMx (except TIM2) - 16 TIM2 - 32 fTIMxCLK = 64 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 64 MHz Timer resolution DS12232 Rev 4 MHz bit 99/135 107 Electrical characteristics STM32G071x8/xB Table 66. TIMx(1) characteristics (continued) Symbol Parameter tCOUNTER 16-bit counter clock period Maximum possible count with 32-bit counter tMAX_COUNT Conditions Min Max Unit - 1 65536 tTIMxCLK 0.015625 1024 µs - 65536 × 65536 tTIMxCLK - 67.10 s fTIMxCLK = 64 MHz fTIMxCLK = 64 MHz 1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17. Table 67. IWDG min/max timeout period at 32 kHz LSI clock(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms 1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period. 5.3.24 Characteristics of communication interfaces I2C-bus interface characteristics The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table. 100/135 DS12232 Rev 4 STM32G071x8/xB Electrical characteristics Table 68. Minimum I2CCLK frequency Symbol Parameter Condition Typ Standard-mode 2 Analog filter enabled fI2CCLK(min) Fast-mode Minimum I2CCLK frequency for correct operation of I2C peripheral DNF = 0 Analog filter disabled DNF = 1 Analog filter enabled Fast-mode Plus DNF = 0 Analog filter disabled DNF = 1 Unit 9 9 MHz 18 16 The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics: Table 69. I2C analog filter characteristics(1) Symbol Parameter Limiting duration of spikes suppressed by the filter(2) tAF Min Max Unit 50 260 ns 1. Based on characterization results, not tested in production. 2. Spikes shorter than the limiting duration are suppressed. SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 70 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. The additional general conditions are: • OSPEEDRy[1:0] set to 11 (output speed) • capacitive load C = 30 pF • measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). DS12232 Rev 4 101/135 107 Electrical characteristics STM32G071x8/xB Table 70. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency tsu(NSS) NSS setup time th(NSS) NSS hold time Conditions Min Typ Max Master mode 1.65 < VDD < 3.6 V Range 1 32 Master transmitter 1.65 < VDD < 3.6 V Range 1 32 Slave receiver 1.65 < VDD < 3.6 V Range 1 32 - - Unit MHz Slave transmitter/full duplex 2.7 < VDD < 3.6 V Range 1 32 Slave transmitter/full duplex 1.65 < VDD < 3.6 V Range 1 23 1.65 < VDD < 3.6 V Range 2 8 Slave mode, SPI prescaler = 2 4 ₓ TPCLK - - ns Slave mode, SPI prescaler = 2 2 ₓ TPCLK - - ns tw(SCKH) SCK high time Master mode TPCLK - 1.5 TPCLK TPCLK + 1.5 ns tw(SCKL) SCK low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1.5 ns tsu(MI) Master data input setup time - 1 - - ns tsu(SI) Slave data input setup time - 1 - - ns th(MI) Master data input hold time - 5 - - ns th(SI) Slave data input hold time - 1 - - ns ta(SO) Data output access time Slave mode 9 - 34 ns tdis(SO) Data output disable time Slave mode 9 - 16 ns 2.7 < VDD < 3.6 V Range 1 - 9 14 1.65 < VDD < 3.6 V Range 1 - 9 21 1.65 < VDD < 3.6 V Voltage Range 2 - 11 24 - 3 5 tv(SO) tv(MO) 102/135 Slave data output valid time Master data output valid time - DS12232 Rev 4 ns ns STM32G071x8/xB Electrical characteristics Table 70. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit th(SO) Slave data output hold time - 5 - - ns th(MO) Master data output hold time - 1 - - ns 1. Based on characterization results, not tested in production. Figure 27. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) th(SO) First bit OUT tf(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 Figure 28. SPI timing diagram - slave mode and CPHA = 1 NSS input SCK input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) First bit OUT tsu(SI) MOSI input th(SO) Next bits OUT tr(SCK) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DS12232 Rev 4 103/135 107 Electrical characteristics STM32G071x8/xB Figure 29. SPI timing diagram - master mode High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. Table 71. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output fMCK= 256 x Fs; (Fs = audio sampling frequency) Fsmin = 8 kHz; Fsmax = 192 kHz; 2.048 49.152 MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs DCK I2S clock frequency duty cycle 30 70 104/135 Slave receiver DS12232 Rev 4 MHz % STM32G071x8/xB Electrical characteristics Table 71. I2S characteristics(1) (continued) Symbol Parameter tv(WS) WS valid time th(WS) Min Max Master mode - 8 WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 4 - th(WS) WS hold time Slave mode 2 - Master receiver 4 - Slave receiver 5 - Master receiver 4.5 - Slave receiver 2 - tsu(SD_MR) Conditions Data input setup time tsu(SD_SR) th(SD_MR) Data input hold time th(SD_SR) after enable edge; 2.7 < VDD < 3.6V Unit ns 16 tv(SD_ST) Data output valid time slave transmitter tv(SD_MT) Data output valid time master transmitter after enable edge - 5.5 th(SD_ST) Data output hold time slave transmitter after enable edge 8 - th(SD_MT) Data output hold time master transmitter after enable edge 1 - - after enable edge; 1.65 < VDD < 3.6V 23 1. Based on characterization results, not tested in production. Figure 30. I2S slave timing diagram (Philips protocol) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit tsu(SD_SR) SDreceive LSB receive(2) th(SD_ST) Bitn transmit th(SD_SR) MSB receive Bitn receive LSB receive MSv39721V1 1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS12232 Rev 4 105/135 107 Electrical characteristics STM32G071x8/xB Figure 31. I2S master timing diagram (Philips protocol) 90% 10% tr(CK) tf(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) Bitn transmit LSB transmit th(SD_MR) tsu(SD_MR) SDreceive th(SD_MT) MSB receive Bitn receive LSB receive MSv39720V1 1. Based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USART characteristics Unless otherwise specified, the parameters given in Table 72 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. The additional general conditions are: • OSPEEDRy[1:0] set to 10 (output speed) • capacitive load C = 30 pF • measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART). Table 72. USART characteristics Symbol fCK 106/135 Parameter USART clock frequency Conditions Min Typ Max Master mode - - 8 Slave mode - - 21 DS12232 Rev 4 Unit MHz STM32G071x8/xB Electrical characteristics Table 72. USART characteristics Symbol Parameter Conditions Min Typ Max tsu(NSS) NSS setup time Slave mode tker + 2 - - th(NSS) NSS hold time Slave mode 2 - - tw(CKH) CK high time tw(CKL) CK low time Master mode 1 / fCK / 2 -1 1 / fCK / 2 1 / fCK / 2 +1 tsu(RX) Data input setup time Master mode tker + 2 - - Slave mode 4 - - Master mode 1 - - Slave mode 0.5 - - Master mode - 0.5 1 Slave mode - 10 19 Master mode 0 - - Slave mode 7 - - th(RX) Data input hold time tv(TX) Data output valid time th(TX) Data output hold time 5.3.25 Unit ns UCPD characteristics UCPD1 and UCPD2 controllers comply with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.0 specifications. Table 73. UCPD operating conditions Symbol VDD Parameter UCPD operating supply voltage Conditions Sink mode only Sink and source mode DS12232 Rev 4 Min Typ Max Unit 3.0 3.3 3.6 V 3.135 3.3 3.465 V 107/135 107 Package information 6 STM32G071x8/xB Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 WLCSP25 package information WLCSP25 is a 25-ball, 2.30 x 2.48 mm wafer-level chip-scale package with 0.4 mm pitch. Figure 32. WLCSP25 chip-scale package outline F bbb Z e1 5 G 4 3 A1 A1 ball location 2 1 A B e DETAIL A e2 C E D E e aaa D BOTTOM VIEW TOP VIEW A3 A A2 (4X) SIDE VIEW A2 BUMP A1 b eee Z FRONT VIEW Z b (25x) ccc M Z X Y ddd M Z DETAIL A ROTATED 90 A06J_WLCSP25_ME_V1 1. Drawing is not to scale. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. 108/135 DS12232 Rev 4 STM32G071x8/xB Package information Table 74. WLCSP25 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A(2) - - 0.59 - - 0.023 A1 - 0.18 - - 0.007 - A2 - 0.38 - - 0.015 - - - 0.001 - 0.025 (3) A3 - b 0.22 0.25 0.28 0.009 0.010 0.011 D 2.28 2.30 2.32 0.090 0.091 0.091 E 2.46 2.48 2.50 0.097 0.098 0.098 e - 0.40 - - 0.016 - e1 - 1.60 - - 0.063 - e2 - 1.60 - - 0.063 - F(4) - 0.350 - - 0.014 - G(4) - 0.440 - - 0.017 - aaa - - 0.10 - - 0.004 bbb - - 0.10 - - 0.004 ccc - - 0.10 - - 0.004 ddd - - 0.05 - - 0.002 eee - - 0.05 - - 0.002 1. Values in inches are converted from mm and rounded to 3 decimal digits. 2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal values and tolerances of A1 and A2. 3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability. 4. Calculated dimensions are rounded to the 3rd decimal place Figure 33. Recommended PCB pad design for WLCSP25 package Dpad Dsm DS12232 Rev 4 MS18965V2 109/135 129 Package information STM32G071x8/xB Table 75. Recommended PCB pad design rules for WLCSP25 package Dimension Recommended value (mm) Pitch 0.4 Dpad 225 Dsm 0.290 typ.(1) Stencil opening 0.250 Stencil thickness 0.100 1. Depends on the solder mask registration tolerance Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below. Figure 34. WLCSP25 package marking example Ball A1 identifier Product identification (1) G0786 Date code Y WW R Revision code MSv47937V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 110/135 DS12232 Rev 4 STM32G071x8/xB 6.2 Package information UFQFPN28 package information UFQFPN is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 35. UFQFPN28 package outline Detail Y D E D D1 E1 Detail Z A0B0_ME_V5 1. Drawing is not to scale. Table 76. UFQFPN28 package mechanical data(1) millimeters inches Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - 0.000 0.050 - 0.0000 0.0020 D 3.900 4.000 4.100 0.1535 0.1575 0.1614 D1 2.900 3.000 3.100 0.1142 0.1181 0.1220 E 3.900 4.000 4.100 0.1535 0.1575 0.1614 E1 2.900 3.000 3.100 0.1142 0.1181 0.1220 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 L1 0.250 0.350 0.450 0.0098 0.0138 0.0177 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS12232 Rev 4 111/135 129 Package information STM32G071x8/xB Figure 36. Recommended footprint for UFQFPN28 package           !"?&0?6 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 37. UFQFPN28 package marking example Product identification (1) G071GB R Revision code Date code Y WW Pin 1 identifier MSv47912V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 112/135 DS12232 Rev 4 STM32G071x8/xB 6.3 Package information UFQFPN32 package information UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package. Figure 38. UFQFPN32 package outline D A A1 A3 e ddd C C SEATINGPLANE D1 b e E2 b E1 E 1 L 32 D2 L PIN 1 Identifier A0B8_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. Table 77. UFQFPN32 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.000 0.0007 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 (2) D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008 E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm. DS12232 Rev 4 113/135 129 Package information STM32G071x8/xB Figure 39. Recommended footprint for UFQFPN32 package 5.30 3.80 25 32 1 0.60 24 3.45 3.80 5.30 3.45 0.50 0.30 8 17 16 9 0.75 3.80 A0B8_FP_V2 1. Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 40. UFQFPN32 package marking example Product identification (1) G071KB6 Date code Y WW R Revision code Pin 1 identifier MSv47910V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 114/135 DS12232 Rev 4 STM32G071x8/xB LQFP32 package information LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 41. LQFP32 package outline c A2 A1 A SEATING PLANE C 0.25 mm ccc GAUGE PLANE C K D L A1 D1 L1 D3 24 17 25 16 32 9 PIN 1 IDENTIFICATION 1 E E1 E3 b 6.4 Package information 8 e 5V_ME_V2 1. Drawing is not to scale. Table 78. LQFP32 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 DS12232 Rev 4 115/135 129 Package information STM32G071x8/xB Table 78. LQFP32 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42. Recommended footprint for LQFP32 package 0.80 1.20 24 17 25 16 0.50 0.30 7.30 6.10 9.70 7.30 32 9 8 1 1.20 6.10 9.70 1. Dimensions are expressed in millimeters. 116/135 DS12232 Rev 4 5V_FP_V2 STM32G071x8/xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 43. LQFP32 package marking example Product identification (1) STM32G 071KBT6 Date code Pin 1 identifier Y WW R Revision code MSv47908V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12232 Rev 4 117/135 129 Package information 6.5 STM32G071x8/xB UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package Figure 44. UFQFPN48 package outline Pin 1 identifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner R 0.125 typ. Detail Z E2 1 48 Z A0B9_ME_V3 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. Table 79. UFQFPN48 package mechanical data inches(1) millimeters Symbol 118/135 Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 DS12232 Rev 4 STM32G071x8/xB Package information Table 79. UFQFPN48 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45. Recommended footprint for UFQFPN48 package 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 24 0.50 0.55 5.80 0.75 A0B9_FP_V2 1. Dimensions are expressed in millimeters. DS12232 Rev 4 119/135 129 Package information STM32G071x8/xB Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. UFQFPN48 package marking example Product identification (1) STM32G 071CBU6 Date code Y WW Pin 1 identifier R Revision code MSv47906V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 120/135 DS12232 Rev 4 STM32G071x8/xB LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 47. LQFP48 package outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K D A1 L D1 L1 D3 36 25 37 24 48 E E1 b E3 6.6 Package information 13 PIN 1 IDENTIFICATION 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 80. LQFP48 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - DS12232 Rev 4 121/135 129 Package information STM32G071x8/xB Table 80. LQFP48 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 48. Recommended footprint for LQFP48 package 0.50 1.20 9.70 0.30 25 36 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. 122/135 DS12232 Rev 4 STM32G071x8/xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 49. LQFP48 package marking example Product identification (1) STM32G071 CBT6 Date code Y WW Pin 1 identifier R Revision code MSv47904V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12232 Rev 4 123/135 129 Package information 6.7 STM32G071x8/xB UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-low-profile fine-pitch ball grid array package. Figure 50. UFBGA64 package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e X A1 ball A1 ball identifier index area F E A F D1 D e Y H 8 1 Øb (64 balls) Ø eee M Z Y X Ø fff M Z BOTTOM VIEW TOP VIEW A019_ME_V1 1. Drawing is not to scale. Table 81. UFBGA64 package mechanical data inches(1) millimeters Symbol 124/135 Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DS12232 Rev 4 STM32G071x8/xB Package information Table 81. UFBGA64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 51. Recommended footprint for UFBGA64 package Dpad Dsm BGA_WLCSP_FT_V1 Table 82. Recommended PCB design rules for UFBGA64 package Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS12232 Rev 4 125/135 129 Package information STM32G071x8/xB Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 52. UFBGA64 package marking example (1) Product identification G071R8I6 Standard ST logo Date code Y WW Revision code R Ball A1 identifier MSv47972V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 126/135 DS12232 Rev 4 STM32G071x8/xB LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 53. LQFP64 package outline 0.25 mm GAUGE PLANE c A1 A SEATING PLANE C A2 A1 ccc C D D1 D3 K L L1 33 48 32 49 64 E E1 b E3 6.8 Package information 17 PIN 1 IDENTIFICATION 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 83. LQFP64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS12232 Rev 4 127/135 129 Package information STM32G071x8/xB Table 83. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 54. Recommended footprint for LQFP64 package 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are expressed in millimeters. 128/135 DS12232 Rev 4 STM32G071x8/xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 55. LQFP64 package marking example Revision code R STM32G071 RBT6 Product identification (1) Date code Y WW Pin 1 identifier MSv47902V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12232 Rev 4 129/135 129 STM32G071x8/xB 6.9 Thermal characteristics The operating junction temperature TJ must never exceed the maximum given in Table 21: General operating conditions. The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is: TJ(max) = TA(max) + PD(max) x ΘJA where: • TA(max) is the maximum operating ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD = PINT + PI/O, – PINT is power dissipation contribution from product of IDD and VDD – PI/O is power dissipation contribution from output ports where: PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 84. Package thermal characteristics Symbol ΘJA 6.9.1 Parameter Thermal resistance junction-ambient Package Value LQFP64 10 × 10 mm 65 UFBGA64 5 × 5 mm 74 LQFP48 7 × 7 mm 75 UFQFPN48 7 × 7 mm 30 LQFP32 7 × 7 mm 76 UFQFPN32 5 × 5 mm 34 UFQFPN28 4 × 4 mm 44 WLCSP25 2.3 × 2.5 mm 70 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (still air). Available from www.jedec.org. 6.9.2 Selecting the product temperature range The temperature range is specified in the ordering information scheme shown in Section 7: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature. As applications do not commonly use microcontrollers at their maximum power consumption, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range best suits the application. 130/135 DS12232 Rev 4 STM32G071x8/xB The following example shows how to calculate the temperature range needed for a given application. Example: Assuming the following worst application conditions: • ambient temperature TA = 50 °C (measured according to JESD51-2) • IDD = 50 mA; VDD = 3.6 V • 20 I/Os simultaneously used as output at low level with IOL = 8 mA (VOL= 0.4 V), and • 8 I/Os simultaneously used as output at low level with IOL = 20 mA (VOL= 1.3 V), the power consumption from power supply PINT is: PINT = 50 mA × 3.6 V= 118 mW, the power loss through I/Os PIO is PIO = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW, and the total power PD to dissipate is: PD = 180 mW + 272 mW = 452 mW For a package with ΘJA= 65 °C/W, the junction temperature stabilizes at: TJ = 50°C + (65 °C/W × 452 mW) = 50 °C + 29.4 °C = 79.4 °C As a conclusion, product version with suffix 6 (maximum allowed TJ = 105° C) is sufficient for this application. If the same application was used in a hot environment with maximum TA greater than 75.5 °C, the junction temperature would exceed 105°C and the product version allowing higher maximum TJ would have to be ordered. DS12232 Rev 4 131/135 131 Ordering information 7 STM32G071x8/xB Ordering information Example STM32 G 071 K 8 T 6 xyy Device family STM32 = Arm® based 32-bit microcontroller Product type G = general-purpose Device subfamily 071 = STM32G071 Pin count E = 25 G = 28 K = 32 C = 48 R = 64 Flash memory size 8 = 64 Kbytes B = 128 Kbytes Package type I = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = -40 to 85°C (105°C junction) 7 = -40 to 105°C (125°C junction) 3 = -40 to 125°C (130°C junction) Options xTR = tape and reel packing; x = N (“N” product version), otherwise blank x˽˽ = tray packing; x = N (“N” product version) or blank other = 3-character ID incl. custom Flash code and packing information; x = N for “N” product version For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. 132/135 DS12232 Rev 4 STM32G071x8/xB 8 Revision history Revision history Table 85. Document revision history Date Revision 8-Nov-2018 1 Initial release. 2 Table 19: IINJ(PIN) parameter definition modified; Table 21: VIN parameter definition modified; Table 51: FT_d type added to Ilkg parameter specification, note attached to Ilkg values, and TT_xx modified to TT_a; Table 56: “single ended mode” removed from IDDV(ADC) parameter definition; Table 84: UFBGA64 5x5 mm package ΘJA corrected 3 Cover page updated; Section 2: Description updated; Section 3.3.1: Securable area added; Section 3.7.1: Power supply schemes: corrected minimum VDD and VDDA values; Section 3.14.1: Temperature sensor: “engineering bytes” replaced “System memory”; Section 3.20: Inter-integrated circuit interface (I2C): SMBus and PMBus feature points; Section 3.21: Universal synchronous/asynchronous receiver transmitter (USART): max. speed corrected; Table 12: Note 3 inserted and note 4 modified; Table 18 updated; Table 19: Note 2 removed; Table 21: Redefined VIN for I/Os of other than TT_xx and FT_c type; Table 49: LU class modified from “II” to “II Level A”; Table 52: I/O current condition for relaxed VOL/VOH corrected from 18 mA to 15 mA; section Output driving current corrected accordingly; Table 56: major update; Section 3.12: DMA request multiplexer (DMAMUX) added; Figures with package marking examples corrected. 28-Nov-2018 06-Mar-2020 Changes DS12232 Rev 4 133/135 134 Revision history STM32G071x8/xB Table 85. Document revision history (continued) Date 23-Sep-2021 134/135 Revision Changes 4 Updated: – Section 2: Description – Section 4: Pinouts, pin description and alternate functions – Replaced “PD version” reference for “N version” reference on Figure 8: STM32G071KxU UFQFPN32 pinout, Figure 9: STM32G071GxU UFQFPN28 pinout, Table 12: Pin assignment and description and Section 7: Ordering information – Section 6: Package information: all subsections were rearranged – Example in Section 6.9.2: Selecting the product temperature range – Footnote 3 on Table 25: Current consumption in Run and Low-power run modes at different die temperatures – Footnote 2 on Table 43: PLL characteristics – VIL line on Table 51: I/O static characteristics – VREFBUF_OUT line on Table 61: VREFBUF characteristics DS12232 Rev 4 STM32G071x8/xB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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