STM32G0B1RET6N

STM32G0B1xB/xC/xE Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM, 6x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz • -40°C to 85°C/105°C/125°C operating temperature • Memories – Up to 512 Kbytes of Flash memory with protection and securable area, two banks, read-while-write support – 144 Kbytes of SRAM (128 Kbytes with HW parity check) • CRC calculation unit • Reset and power management – Voltage range: 1.7 V to 3.6 V – Separate I/O supply pin (1.6 V to 3.6 V) – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Programmable voltage detector (PVD) – Low-power modes: Sleep, Stop, Standby, Shutdown – VBAT supply for RTC and backup registers • Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 16 MHz RC with PLL option (±1 %) – Internal 48 MHz RC oscillator – Internal 32 kHz RC oscillator (±5 %) • Up to 94 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os • 12-channel DMA controller with flexible mapping • 12-bit, 0.4 µs ADC (up to 16 ext. channels) – Up to 16-bit with hardware oversampling – Conversion range: 0 to 3.6V • Two 12-bit DACs, low-power sample-and-hold • Three fast low-power analog comparators, with programmable input and output, rail-to-rail • 15 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and six 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer • Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown December 2022 This is information on a product in full production. UFQFPN32 5 × 5 mm UFQFPN48 7 × 7 mm LQFP32 7 × 7 mm LQFP48 7 × 7 mm LQFP64 10 × 10 mm LQFP80 12 × 12 mm LQFP100 14 × 14 mm UFBGA64 5 × 5 mm UFBGA100 7 × 7 mm WLCSP52 3.09 × 3.15 mm • Communication interfaces – Three I2C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, two supporting SMBus/PMBus and wakeup from Stop mode – Six USARTs with master/slave synchronous SPI; three supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature – Two low-power UARTs – Three SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, two multiplexed with I2S interface – HDMI CEC interface, wakeup on header • USB 2.0 FS device (crystal-less) and host controller • USB Type-C™ Power Delivery controller • Two FDCAN controllers • Development support: serial wire debug (SWD) • 96-bit unique ID • All packages ECOPACK 2 compliant Table 1. Device summary Reference Part number STM32G0B1xB STM32G0B1CB, STM32G0B1KB, STM32G0B1MB, STM32G0B1RB, STM32G0B1VB STM32G0B1xC STM32G0B1CC, STM32G0B1KC, STM32G0B1MC, STM32G0B1RC, STM32G0B1VC STM32G0B1xE STM32G0B1CE, STM32G0B1KE, STM32G0B1ME, STM32G0B1NE, STM32G0B1RE, STM32G0B1VE DS13560 Rev 4 1/158 www.st.com Contents STM32G0B1xB/xC/xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16 3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14 2/158 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24 3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS13560 Rev 4 STM32G0B1xB/xC/xE Contents 3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17) . . . . . . . . . . . . . . . 29 3.18.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32 3.22 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24 Universal serial bus device (USB) and host (USBH) . . . . . . . . . . . . . . . . 34 3.25 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.26 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.27.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 68 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 68 DS13560 Rev 4 3/158 5 Contents 6 STM32G0B1xB/xC/xE 5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 100 5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 107 5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 115 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.5 WLCSP52 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.6 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.8 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.9 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.10 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.11 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.11.1 4/158 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 DS13560 Rev 4 STM32G0B1xB/xC/xE 6.11.2 Contents Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 154 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 DS13560 Rev 4 5/158 5 List of tables STM32G0B1xB/xC/xE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. 6/158 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Terms and symbols used in Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Port E alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current consumption in Run and Low-power run modes at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical current consumption in Run and Low-power run modes, depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 74 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DS13560 Rev 4 STM32G0B1xB/xC/xE Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. List of tables PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Input characteristics of FT_e I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 USB FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 WLCSP52 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 WLCSP52 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 140 LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 LQFP80 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 DS13560 Rev 4 7/158 7 List of figures STM32G0B1xB/xC/xE List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 8/158 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32G0B1VxT LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32G0B1VxI UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32G0B1MxT LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32G0B1RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32G0B1RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32G0B1NxY WLCSP52 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32G0B1CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32G0B1CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32G0B1KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32G0B1KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Current injection into FT_e input with diode active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 USB timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . 123 UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DS13560 Rev 4 STM32G0B1xB/xC/xE Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. List of figures WLCSP52 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 WLCSP52 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 WLCSP52 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 LQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 LQFP80 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 LQFP80 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 DS13560 Rev 4 9/158 9 Introduction 1 STM32G0B1xB/xC/xE Introduction This document provides information on STM32G0B1xB/xC/xE microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes. Information on memory mapping and control registers is object of reference manual. Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 10/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 2 Description Description The STM32G0B1xB/xC/xE mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions. The devices incorporate a memory protection unit (MPU), high-speed embedded memories (144 Kbytes of SRAM and up to 512 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area), DMA, an extensive range of system functions, enhanced I/Os, and peripherals. The devices offer standard communication interfaces (three I2Cs, three SPIs / two I2S, one HDMI CEC, one full-speed USB, two FD CANs, and six USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, three fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, six general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB TypeC Power Delivery controller. The devices operate within ambient temperatures from -40 to 125°C and with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered. The devices come in packages with 32 to 100 pins. Some packages with low pin count are available in two pinouts (standard and alternative indicated by “N” suffix). Products marked by N suffix are offering VDDIO2 supply and additional UCPD port versus the standard pinout, therefore those are better choice for UCPD/USB applications. DS13560 Rev 4 11/158 35 Description STM32G0B1xB/xC/xE Table 2. Features and peripheral counts STM32G0B1_ Peripheral Flash memory (Kbyte) _CBxxN/ _CCxxN/ _CExxN _NE 128/256/ 128/256 128/256 128/256 512 /512 /512 /512 512 _KBxxN/ _KCxxN/ _KExxN _KB/ _KC/ _KE Timers SRAM (Kbyte) _RBxxN/ _RCxxN/ _RExxN _RB/ _RC/ _RE General-purpose 6 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit) Basic 2 (16-bit) Low-power 2 (16-bit) SysTick 1 Watchdog 2 [I2S](1) 3 [2] 2 I C 3 USART 6 LPUART 2 USB 1 1(2) 2 FDCAN 2 CEC 1 RTC Yes Tamper pins 3 VDDIO2 pin / VSS pin No/No Yes/No No/No Yes/Yes Yes/Yes Random number generator No AES No GPIOs 30 29 Wakeup pins 4 3 ADC channels (ext. + int.) 11 + 2 10 + 2 44 42 46 No/No Yes/Yes Yes/Yes Yes/Yes 60 58 74 94 7 8 80 100 4 5 14 + 3 16 + 3 DAC channels Internal voltage reference buffer 2 No Yes Analog comparators 3 Max. CPU frequency 64 MHz Operating voltage 1.7 to 3.6 V Operating temperature(3) Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C Number of pins 32 48 52 1. The numbers in brackets denote the count of SPI interfaces configurable as I2S 64 interface. 2. One port with only one CC line available (supporting limited number of use cases). 3. Depends on order code. Refer to Section 7: Ordering information for details. 12/158 _VB/ _VC/ _VE 128 (parity-protected) or 144 (not parity-protected) 1 (16-bit) high frequency UCPD _MB/ _MC/ _ME 128/256 128/256 128/256 128/256 /512 /512 /512 /512 Advanced control SPI Comm. interfaces _CB/ _CC/ _CE DS13560 Rev 4 STM32G0B1xB/xC/xE Description Figure 1. Block diagram POWER DMAMUX SWCLK SWDIO SWD DMA CORTEX-M0+ fmax = 64 MHz NVIC I/F Bus matrix CPU IOPORT Port B PCx Port C PDx Port D PEx Port E PFx Port F VDD/VDDA VSS/VSSA VDDIO2 POR Reset Int RC 48 MHz POR/BOR NRST T sensor RC 16 MHz PVD PLL XTAL OSC 4-48 MHz RC 32 kHz RCC from peripherals LSE VDD LSE System and peripheral clocks XTAL32 kHz RTC, TAMP Backup regs I/F AHB-to-APB TIM1 COMP2 RTC_OUT RTC_REFIN RTC_TS TAMP_IN DAC I/F DAC_OUT2 4 channels ETR TIM3 & 4 4 channels ETR TIM14 1 channel TIM15 2 channels BKIN TIM16 & 17 TIMER 16/17 1 channel BKIN LPTIM1 &1/2 2 LPTIMER ETR, IN, OUT TIM6 I/F MOSI/SD MISO/MCK SCK/CK NSS/WS SPI/I2S 1&2 SPI1/I2S MOSI, MISO SCK, NSS SPI3 TIM7 PWRCTRL APB ADC CC, DBCC FRSTX UCPD1 &2 UCPD CEC HDMI-CEC APB WWDG IRTIM IR_OUT USART1 to 6 USART3/4 RX, TX CTS, RTS LPUART1 LPUART& && 22 RX, TX, CTS, RTS DBGMCU USB FS I2C1 &2 I2C2 FDCAN1 FDCAN1&&22 I2C3 Power domain of analog blocks : 4 channels BKIN, BKIN2, ETR TIM2 (32-bit) SYSCFG DAC_OUT1 RX, TX OSC32_IN OSC32_OUT VREFBUF COMP3 NOE, DM, DP VBAT Low-voltage detector COMP1 16x IN OSC_IN OSC_OUT IWDG I/F Reset & clock control CRC EXTI IN+, IN-, OUT SUPPLY SUPERVISION HSE AHB Port A Parity HSI48 HSI16 PLLPCLK PLLQCLK PLLRCLK LSI decoder PAx PBx VDDIO1 VDDA Flash memory VDD up to 512 KB VDDIO2 SRAM 144 KB GPIOs VREF+ Voltage regulator VCORE VBAT VDD DS13560 Rev 4 VDDA VDDIO1/VDDIO2 SCL, SDA SMBA, SMBUS SCL, SDA MSv63193V2 13/158 35 Functional overview STM32G0B1xB/xC/xE 3 Functional overview 3.1 Arm® Cortex®-M0+ core with MPU The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: • a simple architecture, easy to learn and program • ultra-low power, energy-efficient operation • excellent code density • deterministic, high-performance interrupt handling • upward compatibility with Cortex-M processor family • platform security robustness, with integrated Memory Protection Unit (MPU). The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Owing to embedded Arm core, the STM32G0B1xB/xC/xE devices are compatible with Arm tools and software. The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.13.1. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3 Embedded Flash memory STM32G0B1xB/xC/xE devices feature up to 512 Kbytes of embedded Flash memory available for storing code and data. 14/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Protection level Debug, boot from RAM or boot from system memory (loader) User execution Read Write Erase Read Write Erase User memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) N/A N/A N/A Backup registers 1 Yes Yes 2 Yes Yes (1) N/A N/A 1. Erased upon RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.3.1 • single error detection and correction • double error detection • readout of the ECC fail address from the ECC register Securable area A part of the Flash memory can be hidden from the application once the code it contains is executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be accessed until the system resets. The securable area generally contains the secure boot code to execute only once at boot. This helps to isolate secret code from untrusted application code. DS13560 Rev 4 15/158 35 Functional overview 3.4 STM32G0B1xB/xC/xE Embedded SRAM STM32G0B1xB/xC/xE devices have 128 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications. When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 144 Kbytes. The memory can be read/write-accessed at CPU clock speed, with 0 wait states. 3.5 Boot modes At startup, the boot pin and boot selector option bit are used to select one of the three boot options: • boot from User Flash memory • boot from System memory • boot from embedded SRAM The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through one of the following interfaces: 3.6 • USART on pins PA9/PA10, PC10/PC11, or PA2/PA3 • I2C-bus on pins PB6/PB7 or PB10/PB11 • SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15 • • USB on pins PA11/PA12 FDCAN on pins PD0/PD1 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 16/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview 3.7 Power supply management 3.7.1 Power supply schemes The STM32G0B1xB/xC/xE devices require a 1.7 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals: • VDD = 1.7 (1.6) to 3.6 V VDD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin. The minimum voltage of 1.7 V corresponds to power-on reset release threshold VPOR(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold VPDR(min). • VDDA = 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V VDDA is the analog power supply for the A/D converter, D/A converter, voltage reference buffer and comparators. VDDA voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin. • VDDIO1 = VDD VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin. • VDDIO2 = 1.6 to 3.6 V VDDIO2 is the power supply from VDDIO2 pin for selected I/Os and VDDUSB. On packages without VDDIO2 pin, VDDUSB and VDDIO2 are internally connected with VDD. Although VDDIO2 is independent of VDD or VDDA, it must not be applied without valid VDD. • VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not present. VBAT is provided externally through VBAT pin. When this pin is not available on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin. • VREF+ is the analog peripheral input reference voltage, or the output of the internal voltage reference buffer (when enabled). When VDDA < 2 V, VREF+ must be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be grounded when the analog peripherals using VREF+ are not active. The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register: – VREF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V) – VREF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V) VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is internally connected with VDD, and the internal voltage reference buffer must be kept disabled (refer to datasheets for package pinout description). • VCORE An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the power supply for digital peripherals, SRAM and Flash memory. The Flash memory is also supplied with VDD. DS13560 Rev 4 17/158 35 Functional overview STM32G0B1xB/xC/xE Figure 2. Power supply overview VREF+ VREF+ VDDA VSSA VDDIO1 VDDIO2 VDDIO2 VDDA domain A/D converter Comparators D/A converter Voltage reference buffer I/O ring VDDIO1 domain I/O ring USB VDDIO2 domain VDD domain VSS/VSSA VDD/VDDA VSS Reset block Temp. sensor PLL, HSI Standby circuitry (Wakeup, IWDG) VDD Voltage regulator Low-voltage detector VCORE domain Core SRAM VCORE Digital peripherals Flash memory RTC domain BKP registers LSE crystal 32.768 kHz osc RCC BDCR register RTC and TAMP VBAT MSv63104V2 3.7.2 Power supply supervisor The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising VDD and other four for falling VDD. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to VPVD threshold. It allows generating an interrupt when VDD level crosses the VPVD threshold, selectively while falling, while rising, or while falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However, SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM. 18/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 3.7.4 Functional overview Low-power modes By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode. • Stop 0 and Stop 1 modes In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode. • Standby mode The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down VCORE domain. The low-power regulator is either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE). • Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the DS13560 Rev 4 19/158 35 Functional overview STM32G0B1xB/xC/xE HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper). 3.7.5 Reset mode During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated. 3.7.6 VBAT operation The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers. In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available. The RTC domain can also be supplied from VDD/VDDA pin. By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin. An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is within a valid range. Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT mode, as in that mode the VDD is not within a valid range. 3.8 Interconnect of peripherals Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes. 20/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview Stop TIMx Sleep Low-power sleep Interconnect source Run Low-power run Table 4. Interconnect of peripherals TIMx Timer synchronization or chaining Y Y - ADCx DACx Conversion triggers Y Y - DMA Memory-to-memory transfer trigger Y Y - Comparator output blanking Y Y - TIM1,2,3,4 Timer input channel, trigger, break from analog signals comparison Y Y - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y TIM1 Timer triggered by analog watchdog Y Y - TIM16 Timer input channel from RTC events Y Y - Low-power timer triggered by RTC alarms or tampers Y Y Y Clock source used as input channel for RC measurement and trimming Y Y - Interconnect destination COMPx COMPx ADCx RTC LPTIMERx Interconnect action All clock sources (internal and external) TIM14,16,17 CSS RAM (parity error) Flash memory (ECC error) COMPx PVD TIM1,15,16,17 Timer break Y Y - CPU (hard fault) TIM1,15,16,17 Timer break Y - - TIMx External trigger Y Y - LPTIMERx External trigger Y Y Y Conversion external trigger Y Y - GPIO ADC DACx DS13560 Rev 4 21/158 35 Functional overview 3.9 STM32G0B1xB/xC/xE Clocks and startup The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: three different sources can deliver SYSCLK system clock: • • – 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL. – System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or HSI16 clocks. Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog. USB clock source: – HSI 48 MHz in association with CRS can provide a dedicated clock to USB FS allowing the peripheral to operate as device without requiring an external resonator • Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC, USB FS) have their own clock independent of the system clock. • Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software. • Clock output: – MCO (microcontroller clock output) provides one of the internal clocks for external use by the application – LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT operation). Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum. 22/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 3.10 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions. Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers. 3.11 Direct memory access controller (DMA) The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture. With 12 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU. Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests. Main features of the DMA controller: • Single-AHB master • Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers • Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals • All DMA channels independently configurable: • 3.12 – Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software. – Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2). – Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size. – Support of transfers from/to peripherals to/from memory with circular buffer management – Programmable number of data to be transferred: 0 to 216 - 1 Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error. DMA request multiplexer (DMAMUX) The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals. DS13560 Rev 4 23/158 35 Functional overview 3.13 STM32G0B1xB/xC/xE Interrupts and events The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow. The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions. 3.13.1 Nested vectored interrupt controller (NVIC) The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management. The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset. If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency. Features of the NVIC: 3.13.2 • Low-latency interrupt processing • 4 priority levels • Handling of a non-maskable interrupt (NMI) • Handling of 32 maskable interrupt lines • Handling of 10 Cortex-M0+ exceptions • Later-arriving higher-priority interrupt processed first • Tail-chaining • Interrupt vector retrieval by hardware Extended interrupt/event controller (EXTI) The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode. The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels. 24/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview The channels can be independently masked. The EXTI controller can capture pulses shorter than the internal clock period. A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt. 3.14 Analog-to-digital converter (ADC) A native 12-bit analog-to-digital converter is embedded into STM32G0B1xB/xC/xE devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase. The ADC can be served by the DMA controller. It can operate in the whole VDD supply range. The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to AN2668). An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers. 3.14.1 Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements. To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode. DS13560 Rev 4 25/158 35 Functional overview STM32G0B1xB/xC/xE Table 5. Temperature sensor calibration values 3.14.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and comparators. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually precisely measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in read-only mode. Table 6. Internal voltage reference calibration values 3.14.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the VBAT voltage. 3.15 Digital-to-analog converter (DAC) The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels. 26/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview Features of the DAC: 3.16 • Two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Independent or simultaneous conversion for DAC channels • DMA capability for either DAC channel • Triggering with timer events, synchronized with DMA • Triggering with external events • Sample-and-hold low-power mode, with internal or external capacitor Voltage reference buffer (VREFBUF) When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC) and to VREF+ pin for external components. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled. On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used. 3.17 Comparators (COMP) Three embedded rail-to-rail analog comparators have programmable reference voltage (internal or external), hysteresis, speed (low for low-power) and output polarity. The reference voltage can be one of the following: • external, from an I/O • internal, from DAC • internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4) The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator. 3.18 Timers and watchdogs The device includes an advanced-control timer, seven general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced-control, general-purpose and basic timers. DS13560 Rev 4 27/158 35 Functional overview STM32G0B1xB/xC/xE Table 7. Timer feature comparison Timer type Timer Counter resolution Counter type Maximum operating frequency Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advancedcontrol TIM1 16-bit Up, down, up/down 128 MHz Integer from 1 to 216 Yes 4 3 TIM2 32-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM3 16-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM4 16-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM14 16-bit Up 64 MHz Integer from 1 to 216 No 1 - TIM15 16-bit Up 128 MHz Integer from 1 to 216 Yes 2 1 TIM16 TIM17 16-bit Up 64 MHz Integer from 1 to 216 Yes 1 1 Basic TIM6 TIM7 16-bit Up 64 MHz Integer from 1 to 216 Yes - - Low-power LPTIM1 LPTIM2 16-bit Up 64 MHz 2n where n=0 to 7 No N/A - Generalpurpose 3.18.1 Advanced-control timer (TIM1) The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for: • input capture • output compare • PWM output (edge or center-aligned modes) with full modulation capability (0-100%) • one-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.18.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 28/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 3.18.2 Functional overview General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17) There are seven synchronizable general-purpose timers embedded in the device (refer to Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs or act as a simple timebase. • TIM2, TIM3, and TIM4 These are full-featured general-purpose timers: – TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler – TIM3 and TIM4 with 16-bit auto-reload up/downcounter and 16-bit prescaler They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate in combination with other general-purpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counter can be frozen in debug mode. • TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode. • TIM15, TIM16, TIM17 These are general-purpose timers featuring: – 16-bit auto-reload upcounter and 16-bit prescaler – 2 channels and 1 complementary channel for TIM15 – 1 channel and 1 complementary channel for TIM16 and TIM17 All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode. 3.18.3 Basic timers (TIM6 and TIM7) These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases. 3.18.4 Low-power timers (LPTIM1 and LPTIM2) These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it. DS13560 Rev 4 29/158 35 Functional overview STM32G0B1xB/xC/xE Features of LPTIM1 and LPTIM2: 3.18.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output (pulse, PWM) • Continuous/one-shot mode • Selectable software/hardware input trigger • Selectable clock source: – Internal: LSE, LSI, HSI16 or APB clocks – External: over LPTIM input (working even with no internal clock source running, used by pulse counter application) • Programmable digital glitch filter • Encoder mode Independent watchdog (IWDG) The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode. 3.18.6 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode. 3.18.7 SysTick timer This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter. Features of SysTick timer: 3.19 • 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source Real-time clock (RTC), tamper (TAMP) and backup registers The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die. The ways of powering the RTC domain are described in Section 3.7.6. The RTC is an independent BCD timer/counter. 30/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview Features of the RTC: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month • Programmable alarm • On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock • Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy • Two anti-tamper detection pins with programmable filter • Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin or a tamper event, or by switching to VBAT mode • 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable resolution and period • Multiple clock sources and references: – A 32.768 kHz external crystal (LSE) – An external resonator or oscillator (LSE) – The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) – The high-speed external clock (HSE) divided by 32 When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes. The backup registers allow keeping 20 bytes of user application data in the event of VDD failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes. 3.20 Inter-integrated circuit interface (I2C) The device embeds three I2C peripherals. Refer to Table 8 for the features. The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing. DS13560 Rev 4 31/158 35 Functional overview STM32G0B1xB/xC/xE Features of the I2C peripheral: • I2C-bus specification and user manual rev. 5 compatibility: – • Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Clock stretching SMBus specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection • PMBus rev 1.3 standard compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent of the PCLK reprogramming • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 8. I2C implementation I2C1 I2C2 I2C3 Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X Programmable analog and digital noise filters X X SMBus/PMBus hardware support X - Independent clock X - Wakeup from Stop mode on address match X - I2C features(1) 1. X: supported 3.21 Universal synchronous/asynchronous receiver transmitter (USART) The device embeds universal synchronous/asynchronous receivers/transmitters that communicate at speeds of up to 8 Mbit/s. 32/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Functional overview They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. Some can also support SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from Stop mode. The wakeup events from Stop mode are programmable and can be: • start bit detection • any received data frame • a specific programmed data frame All USART interfaces can be served by the DMA controller. Table 9. USART implementation USART1 USART2 USART3 USART4 USART5 USART6 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X - LIN mode X - Dual clock domain and wakeup from Stop mode X - Receiver timeout interrupt X - Modbus communication X - Auto baud rate detection X - Driver Enable X X USART modes/features(1) 1. X: supported 3.22 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds two LPUARTs. The peripheral supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent of the CPU clock, and can wakeup the system from Stop mode. The Stop mode wakeup events are programmable and can be: • start bit detection • any received data frame • a specific programmed data frame DS13560 Rev 4 33/158 35 Functional overview STM32G0B1xB/xC/xE Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interface can be served by the DMA controller. 3.23 Serial peripheral interface (SPI) The device contains three SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC calculation. The SPI peripherals can be served by the DMA controller. The I2S interface mode of the SPI peripheral (if supported, see the following table) supports four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. Table 10. SPI/I2S implementation SPI1 SPI2 SPI3 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X X - X X SPI features(1) I 2S mode TI mode 1. X = supported. 3.24 Universal serial bus device (USB) and host (USBH) The devices embed a USB controller with full-speed USB device and host functionality compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up to 1 KB and suspend/resume support. It requires a precise 48 MHz clock that is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 34/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 3.25 Functional overview USB Type-C™ Power Delivery controller The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications. The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring: • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB Power Delivery message transmission and reception • FRS (fast role swap) support The digital controller handles notably: • USB Type-C level detection with de-bounce, generating interrupts • FRS detection, generating an interrupt • byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible) • USB Power Delivery timing dividers (including a clock pre-scaler) • CRC generation/checking • 4b5b encode/decode • ordered sets (with a programmable ordered set mask at receive) • frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling. 3.26 Controller area network (FDCAN) The controller area network (CAN) subsystem consists of two CAN modules and a message RAM. The CAN modules are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. The 1-Kbyte message RAM per CAN module implements filters, receive FIFOs, receive buffers, transmit event FIFOs, and transmit buffers. 3.27 Development support 3.27.1 Serial wire debug port (SW-DP) An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. DS13560 Rev 4 35/158 35 Pinouts, pin description and alternate functions 4 STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions The devices housed in 32-pin, 48-pin, and 64-pin packages come in two variants - “GP” and “N” (the latter with ordering code having N behind the temperature range digit). Refer to Table 2: Features and peripheral counts for differences. Figure 3. STM32G0B1VxT LQFP100 pinout 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 LQFP100 13 63 50 49 48 47 46 45 44 43 42 41 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF6 PF7 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 40 51 39 52 25 38 53 24 37 54 23 36 55 22 35 56 21 34 57 20 33 58 19 32 59 18 31 60 17 30 61 16 29 15 28 62 27 14 26 PB9 PC10 PC11 PE4 PE5 PE6 PC12 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PF3 PF4 PF5 PC0 PC1 PC2 PC3 PA0 99 100 PB8 PB7 PB6 PE3 PE2 PE1 PE0 PB5 PB4 PB3 PF13 PF12 PF11 PF10 PF9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC9 PC8 Top view 1. The I/O pins supplied by VDDIO2 are shown in gray. 36/158 DS13560 Rev 4 PA15 PA14-BOOT0 PA13 PF8 PA12 [PA10] PA11 [PA9] PA10 PD15 PD14 PD13 PD12 VDDIO2 VSS PD11 PD10 PD9 PD8 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PB12 STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions Figure 4. STM32G0B1VxI UFBGA100 pinout Top view 1 2 3 4 5 6 7 8 9 10 11 12 A PB8 PE3 PE2 PE0 PB3 PF13 PF11 PF9 PD6 PD5 PD2 PC9 B PC11 PC10 PB7 PE1 PB4 PF12 PF10 PD7 PD4 PD0 PA15 PA14BOOT0 C PE6 PE4 PB9 PB6 PB5 PD3 PD1 PC8 PA13 PA12 [PA10] D PC14OSC32 _IN PC12 PE5 PF8 PD15 PA11 [PA9] E PC15OSC32 _OUT VBAT PC13 PA10 PD14 PD13 F VDD VREF+ PD12 VDDIO 2 G VSS PF2NRST PD11 VSS H PF0OSC_I N PF4 PF3 PA9 PD9 PD10 J PF1OSC_ OUT PF5 PC1 PB15 PC6 PD8 K PC0 PC2 PA0 PA3 PA7 L PC3 PA1 PA4 PC4 PB0 PB2 M PA2 PA5 PA6 PC5 PB1 PF6 PE9 PE14 PB12 PB14 PC7 PF7 PE10 PE12 PE15 PB11 PA8 PE7 PE8 PE11 PE13 PB10 PB13 1. The I/O pads supplied by VDDIO2 are shown in gray. DS13560 Rev 4 37/158 55 Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE PD5 PD4 PD3 PD2 PD1 PD0 PC9 PC8 PA15 68 67 66 65 64 63 62 61 PB4 PD6 PB5 73 69 PE0 74 70 PE1 75 PB3 PE3 76 PD7 PB6 77 71 PB7 78 72 PB8 79 Top view 80 Figure 5. STM32G0B1MxT LQFP80 pinout PB9 1 60 PA14-BOOT0 PC10 2 59 PA13 PC11 3 58 PA12 [PA10] PC12 4 57 PA11 [PA9] PC13 5 56 PA10 PD15 PC14-OSC32_IN 6 55 PC15-OSC32_OUT 7 54 PD14 VBAT 8 53 PD13 VREF+ 9 52 PD12 VDD 10 51 VDDIO2 VSS 11 PF0-OSC_IN PF1-OSC_OUT LQFP80 50 VSS 12 49 PD11 31 32 33 34 35 36 37 38 39 40 PB2 PE8 PE9 PE10 PB10 PB11 PB12 PB13 PB14 PB15 PE7 41 30 20 PB1 PA1 29 PA8 PB0 42 28 19 PC5 PA9 PA0 27 43 PC4 18 26 PC6 PC3 PA7 44 25 17 PA6 PC7 PC2 24 PD8 45 PA5 46 16 23 15 PC1 PA4 PC0 22 PD9 21 PD10 47 PA3 48 14 PA2 13 PF2-NRST 1. The I/O pins supplied by VDDIO2 are shown in gray. 38/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions PD1 PD0 PC9 49 PD4 54 50 PD5 55 51 PD6 56 PD3 PB3 57 PD2 PB4 58 52 PB5 59 53 PB7 PB6 PB8 60 PB9 62 61 PC10 63 Top view 64 Figure 6. STM32G0B1RxT LQFP64 pinout PC11 1 48 PC8 PC12 2 47 PA15 PC13 3 46 PA14-BOOT0 PC14-OSC32_IN 4 45 PA13 PC15-OSC32_OUT 5 44 PA12 [PA10] VBAT 6 43 PA11 [PA9] VREF+ 7 42 PA10 VDD/VDDA 8 41 PD9 VSS/VSSA 9 40 PD8 PF0-OSC_IN 10 39 PC7 PF1-OSC_OUT 11 38 PC6 PF2-NRST 12 37 PA9 PC0 13 36 PA8 PC1 14 35 PB15 PC2 15 34 PB14 PC3 16 33 PB13 32 PB12 PC9 31 49 30 PB11 PD0 50 PB10 PD1 51 29 PB2 PD2 52 28 PB1 PD3 53 27 PB0 PD4 54 26 PD5 PC5 PD6 55 25 PC4 56 24 PA7 PB3 23 57 22 PA6 PB4 58 PA5 PB5 59 21 PA4 PB6 60 20 PB7 PA3 PB8 19 PA2 61 18 62 17 PB9 63 PA1 PC10 64 Top view PA0 LQFP64 GP version (_RxT) PC11 1 48 PC8 PC12 2 47 PA15 PC13 3 46 PA14-BOOT0 PC14-OSC32_IN 4 45 PA13 PC15-OSC32_OUT 5 44 PA12 [PA10] VBAT 6 43 PA11 [PA9] VREF+ 7 42 PA10 VDD/VDDA 8 41 VDDIO2 VSS/VSSA 9 40 VSS PF0-OSC_IN 10 39 PC7 PF1-OSC_OUT 11 38 PC6 PF2-NRST 12 37 PA9 PC0 13 36 PA8 PC1 14 35 PB15 PC2 15 34 PB14 PC3 16 33 PB13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA2 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 PB12 17 PA0 PA1 LQFP64 N version (_RxTxN) 1. The I/O pins supplied by VDDIO2 are shown in gray. DS13560 Rev 4 39/158 55 Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE Figure 7. STM32G0B1RxI UFBGA64 pinout 1 2 3 4 5 6 7 8 A PC11 PC10 PB7 PB6 PD6 PD2 PD0 PC8 B PC15OSC32 _OUT PC12 PB8 PB3 PD5 PD1 PC9 PA12 [PA10] C PC14OSC32 _IN PC13 PB9 PB4 PD4 PA15 PA14BOOT0 PA11 [PA9] D VDD/ VDDA VREF+ VBAT PB5 PD3 PA10 PA13 VDDIO 2 E VSS/ VSSA PF2NRST PC0 PA7 PC7 PA9 PC6 VSS F PF0OSC_I N PC1 PA3 PA6 PB0 PB14 PB15 PA8 G PF1OSC_ OUT PC2 PA2 PA5 PB1 PB10 PB12 PB13 H PC3 PA0 PA1 PA4 PC4 PC5 PB2 PB11 Top view N version 1. The I/O pads supplied by VDDIO2 are shown in gray. 40/158 DS13560 Rev 4 (_RxIxN) STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions Figure 8. STM32G0B1NxY WLCSP52 pinout Top view 1 A B PA12 [PA10] H PC7 PA8 PC6 PB15 8 PD2 VREF+ PF2NRST PA5 PF0OSC_IN PF1OSC_ OUT PA4 PA7 VDD/ VDDA VSS/ VSSA PA1 PC4 PC14OSC32 _IN PC15OSC32 _OUT VBAT PA2 PB0 PB8 PC13 PB9 PA6 PB1 PB5 PB6 PC5 10 11 12 13 PB4 PB7 PB11 9 PB3 PB12 PB2 PB10 7 PD1 PA9 PB14 6 PD3 PA10 VSS PB13 5 PA14BOOT0 PA13 VDDIO 2 G 4 PD0 PA11 [PA9] E F 3 PA15 C D 2 PA3 PA0 1. The I/O pads supplied by VDDIO2 are shown in gray. DS13560 Rev 4 41/158 55 Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE Figure 9. STM32G0B1CxT LQFP48 pinout 37 38 39 40 41 42 43 44 45 46 1 36 2 35 3 34 4 33 5 32 6 31 LQFP48 7 30 GP version (_RxT) 24 23 22 21 20 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 19 25 18 26 12 17 27 11 16 28 10 15 29 9 14 8 13 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view 37 38 39 40 41 42 43 44 45 46 1 36 2 35 3 34 4 33 5 32 6 31 LQFP48 7 30 24 23 22 21 20 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 19 25 18 26 12 17 27 11 16 28 10 15 29 9 14 8 13 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view 1. The I/O pins supplied by VDDIO2 are shown in gray. 42/158 DS13560 Rev 4 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 VDDIO2 N version VSS (_RxTxN) PA9 PA8 PB15 PB14 PB13 STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions Figure 10. STM32G0B1CxU UFQFPN48 pinout 37 38 39 40 41 42 43 44 45 46 1 36 2 35 3 34 4 33 5 32 6 31 UFQFPN48 7 30 8 29 9 28 10 27 Exposed pad 23 22 21 20 19 18 17 16 15 14 12 26 25 24 11 13 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 GP version (_CxT) PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 VSS 37 7 38 8 39 9 40 0 41 1 42 2 43 3 44 4 45 5 46 6 1 36 6 2 35 5 3 34 4 4 33 3 5 32 2 6 31 1 UFQFPN48 7 30 0 8 29 9 9 28 8 10 1 0 27 7 Exposed pad 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 12 1 2 26 6 25 5 24 24 11 1 1 13 13 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA PF0-OSC_IN PF1-OSC_OUT PF2-NRST PA0 PA1 47 7 48 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 VDDIO2 VSS PA9 PA8 PB15 PB14 PB13 N version (_CxTxN) PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 VSS 1. The I/O leads supplied by VDDIO2 are shown in dark gray. DS13560 Rev 4 43/158 55 Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE PB5 PB4 PB3 PA15 PA14-BOOT0 27 26 25 PB6 28 PB7 30 29 PB8 31 Top view 32 Figure 11. STM32G0B1KxT LQFP32 pinout PB9 1 24 PA13 PC14-OSC32_IN 2 23 PA12 [PA10] PC15-OSC32_OUT 3 22 PA11 [PA9] VDD/VDDA 4 21 PA10 VSS/VSSA 5 20 PC6 PF2-NRST 6 19 PA9 PA0 7 18 PA8 GP version PA1 8 17 PB2 (_KxT) 9 10 11 12 13 14 15 16 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 LQFP32 PB8 PB7 PB6 PD3 PD2 PD1 PD0 PA14-BOOT0 31 30 29 28 27 26 25 Top view 32 MSv39712V3 PB9 1 24 PA13 PC14-OSC32_IN 2 23 PA12 [PA10] PC15-OSC32_OUT 3 22 PA11 [PA9] VDD/VDDA 4 21 PA10 VSS/VSSA 5 20 VDDIO2 PF2-NRST 6 19 PA9 PA0 7 18 PA8 PA1 8 17 PB15 9 10 11 12 13 14 15 16 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 LQFP32 1. The I/O pins supplied by VDDIO2 are shown in dark gray. 44/158 DS13560 Rev 4 N version (_KxTxN) STM32G0B1xB/xC/xE Pinouts, pin description and alternate functions 25 26 27 28 29 1 24 2 23 3 22 4 21 UFQFPN32 5 20 6 19 Exposed pad 7 18 8 PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB2 GP version (_KxU) 16 15 14 13 12 11 9 17 10 PB9 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 30 32 Top view 31 PB8 PB7 PB6 PB5 PB4 PB3 PA15 PA14-BOOT0 Figure 12. STM32G0B1KxU UFQFPN32 pinout PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS 25 26 27 28 29 1 24 2 23 3 22 4 5 UFQFPN32 6 21 20 19 Exposed pad 7 18 8 PA13 PA12 [PA10] PA11 [PA9] PA10 VDDIO2 PA9 PA8 PB15 N version (_KxUxN) 16 15 14 13 12 11 10 17 9 PB9 PC14-OSC32_IN PC15-OSC32_OUT VDD/VDDA VSS/VSSA PF2-NRST PA0 PA1 30 32 Top view 31 PB8 PB7 PB6 PD3 PD2 PD1 PD0 PA14-BOOT0 MSv39715V3 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS 1. The I/O leads supplied by VDDIO2 are shown in dark gray. DS13560 Rev 4 45/158 55 Pinouts, pin description and alternate functions STM32G0B1xB/xC/xE Table 11. Terms and symbols used in Table 12 Column Pin name Pin type Symbol Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor Options for TT or FT I/Os I/O structure Note Definition _f I/O, Fm+ capable _a I/O, with analog switch function _c I/O, USB Type-C PD capable _e I/O, with switchable diode to VDDIOx _d I/O, USB Type-C PD Dead Battery function _s I/O, supplied from VDDIO2 only Upon reset, all I/Os are set as analog inputs, unless otherwise specified. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 46/158 DS13560 Rev 4 WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 - - - 64 64 A2 2 2 B2 PC10 - - - - - 1 1 A1 3 3 B1 PC11 I/O FT - USART3_RX, USART4_RX, TIM1_CH4, SPI3_MISO - - - - - - - - - - 4 C2 PE4 I/O FT - TIM3_CH2 - - - - - - - - - - 5 D3 PE5 I/O FT - TIM3_CH3 - - - - - - - - - - 6 C1 PE6 I/O FT - TIM3_CH4 TAMP_IN3, WKUP3 - - - - - 2 2 B2 4 7 D2 PC12 I/O FT - LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1, USART5_TX, SPI3_MOSI - - - 1 1 B11 3 3 C2 5 8 E3 PC13 I/O FT (1)(2) TIM1_BKIN TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2 - - 2 2 B13 4 4 C1 6 9 D1 PC14OSC32_IN I/O FT (1)(2) TIM1_BKIN2 OSC32_IN 2 2 - - - - - - - - - PC14OSC32_IN I/O FT (1)(2) TIM1_BKIN2 OSC32_IN, OSC_IN 3 3 3 3 C12 5 5 B1 7 10 E1 PC15OSC32_OUT I/O FT (1)(2) OSC32_EN, OSC_EN, TIM15_BKIN OSC32_OUT - - 4 4 C10 6 6 D3 8 11 E2 VBAT S - - - - - - 5 5 D11 7 7 D2 9 12 F2 VREF+ S - - - VREFBUF_OUT 4 4 6 6 D13 8 8 D1 10 13 F1 VDD/VDDA S - - - - 5 5 7 7 E12 9 9 E1 11 14 G1 VSS/VSSA S - - - - - - 8 8 F13 10 10 F1 12 15 H1 PF0-OSC_IN I/O FT - CRS1_SYNC, EVENTOUT, TIM14_CH1 OSC_IN I/O Note LQFP48 / UFQFPN48 - N - I/O structure LQFP48 / UFQFPN48 - GP - Pin type LQFP32 / UFQFPN32 - N 47/158 Pin name Alternate functions Additional functions FT - USART3_TX, USART4_TX, TIM1_CH3, SPI3_SCK - Pinouts, pin description and alternate functions DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number STM32G0B1xB/xC/xE Table 12. Pin assignment and description LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin type I/O structure Note Alternate functions - - 9 9 G12 11 11 G1 13 16 J1 PF1OSC_OUT I/O FT - OSC_EN, EVENTOUT, TIM15_CH1N OSC_OUT 6 6 10 10 F11 12 12 E2 14 17 G2 PF2-NRST I/O - - MCO, LPUART2_TX, LPUART2_RTS_DE NRST - - - - - - - - - 18 H3 PF3 I/O FT - LPUART2_RX, USART6_RTS_DE_CK - - - - - - - - - - 19 H2 PF4 I/O FT - LPUART1_TX - - - - - - - - - - 20 J2 PF5 I/O FT - LPUART1_RX - - - - - - 13 13 E3 15 21 K1 PC0 I/O FT_a - LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1, LPUART2_TX, USART6_TX, I2C3_SCL, COMP3_OUT COMP3_INM7 - - - - - 14 14 F2 16 22 J3 PC1 I/O FT_a - LPTIM1_OUT, LPUART1_TX, TIM15_CH1, LPUART2_RX, USART6_RX, I2C3_SDA COMP3_INP1 - - - - - 15 15 G2 17 23 K2 PC2 I/O FT - LPTIM1_IN2, SPI2_MISO/I2S2_MCK, TIM15_CH2, FDCAN2_RX, COMP3_OUT - - - - - - 16 16 H1 18 24 L1 PC3 I/O FT - LPTIM1_ETR, SPI2_MOSI/I2S2_SD, LPTIM2_ETR, FDCAN2_TX - 7 7 11 11 H13 17 17 H2 19 25 K3 PA0 I/O FT_a - SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1 8 8 12 12 E10 18 18 H3 20 26 L2 PA1 I/O FT_ea - SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT COMP1_INP2, ADC_IN1 9 9 13 13 E8 19 19 G3 21 27 M1 PA2 I/O FT_a - SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT COMP2_INM8, ADC_IN2, WKUP4, LSCO Pin name Additional functions STM32G0B1xB/xC/xE LQFP32 / UFQFPN32 - N DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number Pinouts, pin description and alternate functions 48/158 Table 12. Pin assignment and description (continued) LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 10 14 14 H11 20 20 F3 22 28 K4 PA3 I/O Alternate functions Additional functions FT_ea - SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT COMP2_INP2, ADC_IN3 ADC_IN4, DAC1_OUT1, RTC_OUT2 21 H4 23 29 L3 PA4 I/O TT_a - SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS - - - - - - PA4 I/O TT_a - SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2 F9 22 22 G4 24 30 M2 PA5 I/O TT_ea - SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT ADC_IN5, DAC1_OUT2 F7 23 23 F4 25 31 M3 PA6 I/O FT_ea - SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA ADC_IN6 ADC_IN7 - - 15 15 G10 21 11 11 - - - 12 12 16 16 13 13 17 17 49/158 14 14 18 18 H9 24 24 E4 26 32 K5 PA7 I/O FT_a - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL - - - - G8 25 25 H5 27 33 L4 PC4 I/O FT_a - USART3_TX, USART1_TX, TIM2_CH1_ETR, FDCAN1_RX COMP1_INM7, ADC_IN17 - - - - G6 26 26 H6 28 34 M4 PC5 I/O FT_a - USART3_RX, USART1_RX, TIM2_CH2, FDCAN1_TX COMP1_INP0, ADC_IN18, WKUP5 Pinouts, pin description and alternate functions DS13560 Rev 4 Note LQFP48 / UFQFPN48 - GP 10 I/O structure LQFP32 / UFQFPN32 - N Pin name Pin type LQFP32 / UFQFPN32 - GP Pin number STM32G0B1xB/xC/xE Table 12. Pin assignment and description (continued) LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin name Pin type I/O structure Note Alternate functions 15 15 19 19 H7 27 27 F5 29 35 L5 PB0 I/O FT_ea - SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS COMP3_INP0, ADC_IN8 16 16 20 20 H5 28 28 G5 30 36 M5 PB1 I/O FT_ea - TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE COMP1_INM6, ADC_IN9 17 - 21 21 G4 29 29 H7 31 37 L6 PB2 I/O FT_ea - SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT COMP1_INP1, COMP3_INM6, ADC_IN10 - - - - - - - - - 38 M6 PF6 I/O FT - LPUART1_RTS_DE - - - - - - - - - - 39 L7 PF7 I/O FT - LPUART1_CTS, USART5_CTS - - - - - - - - - 32 40 M7 PE7 I/O FT_a - TIM1_ETR, USART5_RTS_DE_CK COMP3_INP2 - - - - - - - - 33 41 M8 PE8 I/O FT_a - USART4_TX, TIM1_CH1N COMP3_INM8 - - - - - - - - 34 42 K8 PE9 I/O FT - USART4_RX, TIM1_CH1 - - - - - - - - - 35 43 L8 PE10 I/O FT - TIM1_CH2N, USART5_TX - - - - - - - - - - 44 M9 PE11 I/O FT - TIM1_CH2, USART5_RX - - - - - - - - - - 45 L9 PE12 I/O FT - SPI1_NSS/I2S1_WS, TIM1_CH3N - - - - - - - - - - 46 M10 PE13 I/O FT - SPI1_SCK/I2S1_CK, TIM1_CH3 - - - - - - - - - - 47 K9 PE14 I/O FT - SPI1_MISO/I2S1_MCK, TIM1_CH4, TIM1_BKIN2 - - - - - - - - - - 48 L10 PE15 I/O FT - SPI1_MOSI/I2S1_SD, TIM1_BKIN - Additional functions STM32G0B1xB/xC/xE LQFP32 / UFQFPN32 - N DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number Pinouts, pin description and alternate functions 50/158 Table 12. Pin assignment and description (continued) LQFP32 / UFQFPN32 - N LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin type I/O structure Note 51/158 Pin name Alternate functions - - 22 22 H3 30 30 G6 36 49 M11 PB10 I/O FT_fa - CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT ADC_IN11 - - 23 23 F5 31 31 H8 37 50 L11 PB11 I/O FT_fa - SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT ADC_IN15 - - 24 24 E6 32 32 G7 38 51 K10 PB12 I/O FT_fa - SPI2_NSS/I2S2_WS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, EVENTOUT, I2C2_SMBA ADC_IN16 - - 25 25 H1 33 33 G8 39 52 M12 PB13 I/O FT_fs - SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT - - - 26 26 G2 34 34 F6 40 53 K11 PB14 I/O FT_fs - SPI2_MISO/I2S2_MCK, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK - - 17 27 27 F3 35 35 F7 41 54 J10 PB15 I/O FT_fcs (3) SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT, USART6_CTS UCPD1_CC2, RTC_REFIN 18 18 28 28 F1 36 36 F8 42 55 L12 PA8 I/O FT_fcs (3) MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA UCPD1_CC1 19 19 29 29 E4 37 37 E6 43 56 H10 PA9 I/O FT_fds (3) MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL UCPD1_DBCC1 20 - 30 - D5 38 38 E7 44 57 J11 PC6 I/O FT_s - UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX - - - 31 - D3 39 39 E5 45 58 K12 PC7 I/O FT_s - UCPD2_FRSTX, TIM3_CH2, TIM2_CH4, LPUART2_RX - Additional functions Pinouts, pin description and alternate functions DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number STM32G0B1xB/xC/xE Table 12. Pin assignment and description (continued) LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin name Pin type I/O structure Note Alternate functions - - - - - 40 - - 46 59 J12 PD8 I/O FT_s - USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT - - - - - - 41 - - 47 60 H11 PD9 I/O FT_s - USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2 - - - - - - - - - 48 61 H12 PD10 I/O FT_s - MCO - - - - - - - - - 49 62 G11 PD11 I/O FT_s - USART3_CTS, LPTIM2_ETR - - - - 30 E2 - 40 E8 50 63 G12 VSS S - - - - - 20 - 31 D1 - 41 D8 51 64 F12 VDDIO2 S - - - - - - - - - - - - 52 65 F11 PD12 I/O FT_s - USART3_RTS_DE_CK, LPTIM2_IN1, TIM4_CH1, FDCAN1_RX - - - - - - - - - 53 66 E12 PD13 I/O FT_s - LPTIM2_OUT, TIM4_CH2, FDCAN1_TX - - - - - - - - - 54 67 E11 PD14 I/O FT_s - LPUART2_CTS, TIM4_CH3, FDCAN2_RX - - - - - - - - - 55 68 D11 PD15 I/O FT_s - CRS1_SYNC, LPUART2_RTS_DE, TIM4_CH4, FDCAN2_TX - 21 21 32 32 C4 42 42 D6 56 69 E10 PA10 I/O FT_fds (3) SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA UCPD1_DBCC2 22 22 33 33 C2 43 43 C8 57 70 D12 PA11 [PA9] I/O FT_fs (4) SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT USB_DM 23 23 34 34 B1 44 44 B8 58 71 C12 PA12 [PA10] I/O FT_fs (4) SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT USB_DP - - - - - - - - - 72 D10 PF8 I/O FT_s - - - Additional functions STM32G0B1xB/xC/xE LQFP32 / UFQFPN32 - N DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number Pinouts, pin description and alternate functions 52/158 Table 12. Pin assignment and description (continued) WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 35 35 B3 45 45 D7 59 73 C11 PA13 25 25 36 36 B5 46 46 C7 60 74 B12 PA14-BOOT0 I/O FT_s (5) SWCLK, USART2_TX, EVENTOUT, LPUART2_TX BOOT0 26 - 37 37 A2 47 47 C6 61 75 B11 PA15 I/O FT_s - SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS - - - - - - 48 48 A8 62 76 C10 PC8 I/O FT_s - UCPD2_FRSTX, TIM3_CH3, TIM1_CH1, LPUART2_CTS - - - - - - 49 49 B7 63 77 A12 PC9 I/O FT_s - I2S_CKIN, TIM3_CH4, TIM1_CH2, LPUART2_RTS_DE, USB_NOE - - 26 38 38 A4 50 50 A7 64 78 B10 PD0 I/O FT_cs (3) EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1, FDCAN1_RX UCPD2_CC1 - 27 39 39 C6 51 51 B6 65 79 C9 PD1 I/O FT_ds (3) EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1, FDCAN1_TX UCPD2_DBCC1 - 28 40 40 B7 52 52 A6 66 80 A11 PD2 I/O FT_cs (3) USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX UCPD2_CC2 - 29 41 41 A6 53 53 D5 67 81 C8 PD3 I/O FT_ds (3) USART2_CTS, SPI2_MISO/I2S2_MCK, TIM1_CH2N, USART5_TX UCPD2_DBCC2 - - - - - 54 54 C5 68 82 B9 PD4 I/O FT_s - USART2_RTS_DE_CK, SPI2_MOSI/I2S2_SD, TIM1_CH3N, USART5_RTS_DE_CK - - - - - - 55 55 B5 69 83 A10 PD5 I/O FT - USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN, USART5_CTS - - - - - - 56 56 A5 70 84 A9 PD6 I/O FT - USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT - I/O Note LQFP48 / UFQFPN48 - N 24 I/O structure LQFP48 / UFQFPN48 - GP 24 Pin type LQFP32 / UFQFPN32 - N 53/158 Pin name Alternate functions Additional functions FT_es (5) SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX - Pinouts, pin description and alternate functions DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number STM32G0B1xB/xC/xE Table 12. Pin assignment and description (continued) LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin name Pin type I/O structure Note Alternate functions - - - - - - - - 71 85 B8 PD7 I/O FT - MCO2 - - - - - - - - - - 86 A8 PF9 I/O FT - USART6_TX - - - - - - - - - - 87 B7 PF10 I/O FT - USART6_RX - - - - - - - - - - 88 A7 PF11 I/O FT - USART6_RTS_DE_CK - - - - - - - - - - 89 B6 PF12 I/O FT - TIM15_CH1, USART6_CTS - - - - - - - - - - 90 A6 PF13 I/O FT - TIM15_CH2 - 27 - 42 42 A8 57 57 B4 72 91 A5 PB3 I/O FT_a - SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK COMP2_INM6 28 - 43 43 B9 58 58 C4 73 92 B5 PB4 I/O FT_a - SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO COMP2_INP0 29 - 44 44 A10 59 59 D4 74 93 C5 PB5 I/O FT - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI WKUP6 - - - - - - - - 75 94 A4 PE0 I/O FT - TIM16_CH1, EVENTOUT, TIM4_ETR - - - - - - - - - 76 95 B4 PE1 I/O FT - TIM17_CH1, EVENTOUT - - - - - - - - - - 96 A3 PE2 I/O FT - TIM3_ETR - - - - - - - - - 77 97 A2 PE3 I/O FT - TIM3_CH1 - Additional functions STM32G0B1xB/xC/xE LQFP32 / UFQFPN32 - N DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number Pinouts, pin description and alternate functions 54/158 Table 12. Pin assignment and description (continued) LQFP32 / UFQFPN32 - N LQFP48 / UFQFPN48 - GP LQFP48 / UFQFPN48 - N WLCSP52 LQFP64 - GP LQFP64 - N UFBGA64 - N LQFP80 LQFP100 UFBGA100 Pin name Pin type I/O structure Note Alternate functions 30 30 45 45 C8 60 60 A4 78 98 C4 PB6 I/O FT_fa - USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX COMP2_INP1 31 31 46 46 D7 61 61 A3 79 99 B3 PB7 I/O FT_fa - USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX COMP2_INM7, PVD_IN 32 32 47 47 A12 62 62 B3 80 100 A1 PB8 I/O FT_f - CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3 - 1 1 48 48 D9 63 63 C3 1 1 C3 PB9 I/O FT_f - IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4 - Additional functions 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (for example to drive a LED). 2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual. 3. Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2 depending on voltage level on PA9, PA10, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bit in SYSCFG_CFGR1 register during start-up sequence. 4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register. 5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated. 55/158 Pinouts, pin description and alternate functions DS13560 Rev 4 LQFP32 / UFQFPN32 - GP Pin number STM32G0B1xB/xC/xE Table 12. Pin assignment and description (continued) 56/158 Table 13. Port A alternate function mapping (AF0 to AF7) DS13560 Rev 4 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PA0 SPI2_SCK/ I2S2_CK USART2_CTS TIM2_CH1_ETR - USART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUT PA1 SPI1_SCK/ I2S1_CK USART2_RTS _DE_CK TIM2_CH2 - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT PA2 SPI1_MOSI/ I2S1_SD USART2_TX TIM2_CH3 - UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUT PA3 SPI2_MISO/ I2S2_MCK USART2_RX TIM2_CH4 - UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT PA4 SPI1_NSS/ I2S1_WS SPI2_MOSI/ I2S2_SD USB_NOE USART6_TX TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT PA5 SPI1_SCK/ I2S1_CK CEC TIM2_CH1_ETR USART6_RX USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT PA6 SPI1_MISO/ I2S1_MCK TIM3_CH1 TIM1_BKIN USART6_CTS USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUT PA7 SPI1_MOSI/ I2S1_SD TIM3_CH2 TIM1_CH1N USART6_RTS _DE_CK TIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUT PA8 MCO SPI2_NSS/ I2S2_WS TIM1_CH1 - CRS1_SYNC LPTIM2_OUT - EVENTOUT PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO/ I2S2_MCK TIM15_BKIN I2C1_SCL EVENTOUT PA10 SPI2_MOSI/ I2S2_SD USART1_RX TIM1_CH3 MCO2 - TIM17_BKIN I2C1_SDA EVENTOUT PA11 SPI1_MISO/ I2S1_MCK USART1_CTS TIM1_CH4 FDCAN1_RX - TIM1_BKIN2 I2C2_SCL COMP1_OUT PA12 SPI1_MOSI/ I2S1_SD USART1_RTS _DE_CK TIM1_ETR FDCAN1_TX - I2S_CKIN I2C2_SDA COMP2_OUT PA13 SWDIO IR_OUT USB_NOE - - - - EVENTOUT PA14 SWCLK USART2_TX - - - - - EVENTOUT PA15 SPI1_NSS/ I2S1_WS USART2_RX TIM2_CH1_ETR MCO2 USART4_RTS _DE_CK USART3_RTS _DE_CK USB_NOE EVENTOUT STM32G0B1xB/xC/xE Port DS13560 Rev 4 Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 PA0 - - - - - - - - PA1 - - - - - - - - PA2 - - - - - - - - PA3 - - - - - - - - PA4 - SPI3_NSS - - - - - - PA5 - - - - - - - - PA6 I2C2_SDA I2C3_SDA - - - - - - PA7 I2C2_SCL I2C3_SCL - - - - - - PA8 I2C2_SMBA - - - - - - - PA9 I2C2_SCL - - - - - - - PA10 I2C2_SDA - - - - - - - PA11 - - - - - - - - PA12 - - - - - - - - PA13 - - LPUART2_RX - - - - - PA14 - - LPUART2_TX - - - - - PA15 I2C2_SMBA SPI3_NSS - - - - - - STM32G0B1xB/xC/xE Table 14. Port A alternate function mapping (AF8 to AF15) 57/158 58/158 Table 15. Port B alternate function mapping (AF0 to AF7) DS13560 Rev 4 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PB0 SPI1_NSS/ I2S1_WS TIM3_CH3 TIM1_CH2N FDCAN2_RX USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUT PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N FDCAN2_TX USART3_RTS _DE_CK LPTIM2_IN1 LPUART1_RTS _DE COMP3_OUT PB2 - SPI2_MISO/ I2S2_MCK - MCO2 USART3_TX LPTIM1_OUT - EVENTOUT PB3 SPI1_SCK/ I2S1_CK TIM1_CH2 TIM2_CH2 USART5_TX USART1_RTS _DE_CK - I2C3_SCL EVENTOUT PB4 SPI1_MISO/ I2S1_MCK TIM3_CH1 - USART5_RX USART1_CTS TIM17_BKIN I2C3_SDA EVENTOUT PB5 SPI1_MOSI/ I2S1_SD TIM3_CH2 TIM16_BKIN FDCAN2_RX - LPTIM1_IN1 I2C1_SMBA COMP2_OUT PB6 USART1_TX TIM1_CH3 TIM16_CH1N FDCAN2_TX SPI2_MISO/ I2S2_MCK LPTIM1_ETR I2C1_SCL EVENTOUT PB7 USART1_RX SPI2_MOSI/ I2S2_SD TIM17_CH1N - USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT PB8 CEC SPI2_SCK/ I2S2_CK TIM16_CH1 FDCAN1_RX USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT PB9 IR_OUT UCPD2_FRSTX TIM17_CH1 FDCAN1_TX USART3_RX SPI2_NSS/ I2S2_WS I2C1_SDA EVENTOUT PB10 CEC LPUART1_RX TIM2_CH3 - USART3_TX SPI2_SCK/ I2S2_CK I2C2_SCL COMP1_OUT PB11 SPI2_MOSI/ I2S2_SD LPUART1_TX TIM2_CH4 - USART3_RX - I2C2_SDA COMP2_OUT PB12 SPI2_NSS/ I2S2_WS LPUART1_RTS _DE TIM1_BKIN FDCAN2_RX - TIM15_BKIN UCPD2_FRSTX EVENTOUT PB13 SPI2_SCK/ I2S2_CK LPUART1_CTS TIM1_CH1N FDCAN2_TX USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT STM32G0B1xB/xC/xE Port Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PB14 SPI2_MISO/ I2S2_MCK UCPD1_FRSTX TIM1_CH2N - USART3_RTS _DE_CK TIM15_CH1 I2C2_SDA EVENTOUT PB15 SPI2_MOSI/ I2S2_SD - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT Table 16. Port B alternate function mapping (AF8 to AF15) DS13560 Rev 4 Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 PB0 USART5_TX - LPUART2_CTS - - - - - PB1 USART5_RX - LPUART2_RTS _DE - - - - - PB2 - - - - - - - - PB3 I2C2_SCL SPI3_SCK - - - - - - PB4 I2C2_SDA SPI3_MISO - - - - - - PB5 USART5_RTS _DE_CK SPI3_MOSI - - - - - - PB6 USART5_CTS TIM4_CH1 LPUART2_TX - - - - - PB7 - TIM4_CH2 LPUART2_RX - - - - - PB8 USART6_TX TIM4_CH3 - - - - - - PB9 USART6_RX TIM4_CH4 - - - - - - PB10 - - - - - - - - PB11 - - - - - - - - PB12 I2C2_SMBA - - - - - - - PB13 - - - - - - - - PB14 USART6_RTS _DE_CK - - - - - - - PB15 USART6_CTS - - - - - - - STM32G0B1xB/xC/xE Table 15. Port B alternate function mapping (AF0 to AF7) (continued) 59/158 60/158 Table 17. Port C alternate function mapping DS13560 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PC0 LPTIM1_IN1 LPUART1_RX LPTIM2_IN1 LPUART2_TX USART6_TX - I2C3_SCL COMP3_OUT PC1 LPTIM1_OUT LPUART1_TX TIM15_CH1 LPUART2_RX USART6_RX - I2C3_SDA - PC2 LPTIM1_IN2 SPI2_MISO/ I2S2_MCK TIM15_CH2 FDCAN2_RX - - - COMP3_OUT PC3 LPTIM1_ETR SPI2_MOSI/ I2S2_SD LPTIM2_ETR FDCAN2_TX - - - - PC4 USART3_TX USART1_TX TIM2_CH1_ETR FDCAN1_RX - - - - PC5 USART3_RX USART1_RX TIM2_CH2 FDCAN1_TX - - - - PC6 UCPD1_FRSTX TIM3_CH1 TIM2_CH3 LPUART2_TX - - - - PC7 UCPD2_FRSTX TIM3_CH2 TIM2_CH4 LPUART2_RX - - - - PC8 UCPD2_FRSTX TIM3_CH3 TIM1_CH1 LPUART2_CTS - - - - PC9 I2S_CKIN TIM3_CH4 TIM1_CH2 LPUART2_RTS_ DE - - USB_NOE - PC10 USART3_TX USART4_TX TIM1_CH3 - SPI3_SCK - - - PC11 USART3_RX USART4_RX TIM1_CH4 - SPI3_MISO - - - PC12 LPTIM1_IN1 UCPD1_FRSTX TIM14_CH1 USART5_TX SPI3_MOSI - - - PC13 - - TIM1_BKIN - - - - - PC14 - - TIM1_BKIN2 - - - - - PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - - STM32G0B1xB/xC/xE Table 18. Port D alternate function mapping DS13560 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PD0 EVENTOUT SPI2_NSS/ I2S2_WS TIM16_CH1 FDCAN1_RX - - - - PD1 EVENTOUT SPI2_SCK/ I2S2_CK TIM17_CH1 FDCAN1_TX - - - - PD2 USART3_RTS _DE_CK TIM3_ETR TIM1_CH1N USART5_RX - - - - PD3 USART2_CTS SPI2_MISO/ I2S2_MCK TIM1_CH2N USART5_TX - - - - PD4 USART2_RTS _DE_CK SPI2_MOSI/ I2S2_SD TIM1_CH3N USART5_RTS _DE_CK - - - - PD5 USART2_TX SPI1_MISO/ I2S1_MCK TIM1_BKIN USART5_CTS - - - - PD6 USART2_RX SPI1_MOSI/ I2S1_SD LPTIM2_OUT - - - - - PD7 - - - MCO2 - - - - PD8 USART3_TX SPI1_SCK/ I2S1_CK LPTIM1_OUT - - - - - PD9 USART3_RX SPI1_NSS/ I2S1_WS TIM1_BKIN2 - - - - - PD10 MCO - - - - - - - PD11 USART3_CTS LPTIM2_ETR - - - - - - PD12 USART3_RTS _DE_CK LPTIM2_IN1 TIM4_CH1 FDCAN1_RX - - - - PD13 - LPTIM2_OUT TIM4_CH2 FDCAN1_TX - - - - PD14 - LPUART2_CTS TIM4_CH3 FDCAN2_RX - - - - PD15 CRS1_SYNC LPUART2_RTS _DE TIM4_CH4 FDCAN2_TX - - - - STM32G0B1xB/xC/xE * 61/158 62/158 Table 19. Port E alternate function mapping DS13560 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PE0 TIM16_CH1 EVENTOUT TIM4_ETR - - - - - PE1 TIM17_CH1 EVENTOUT - - - - - - PE2 - TIM3_ETR - - - - - - PE3 - TIM3_CH1 - - - - - - PE4 - TIM3_CH2 - - - - - - PE5 - TIM3_CH3 - - - - - - PE6 - TIM3_CH4 - - - - - - PE7 - TIM1_ETR - USART5_RTS_D E_CK - - - - PE8 USART4_TX TIM1_CH1N - - - - - - PE9 USART4_RX TIM1_CH1 - - - - - - PE10 - TIM1_CH2N - USART5_TX - - - - PE11 - TIM1_CH2 - USART5_RX - - - - PE12 SPI1_NSS/ I2S1_WS TIM1_CH3N - - - - - - PE13 SPI1_SCK/ I2S1_CK TIM1_CH3 - - - - - - PE14 SPI1_MISO/I2S1 _MCK TIM1_CH4 TIM1_BK2 - - - - - PE15 SPI1_MOSI/I2S1 _SD TIM1_BK - - - - - - STM32G0B1xB/xC/xE DS13560 Rev 4 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PF0 CRS1_SYNC EVENTOUT TIM14_CH1 - - - - - PF1 OSC_EN EVENTOUT TIM15_CH1N - - - - - PF2 MCO LPUART2_TX - LPUART2_RTS _DE - - - - PF3 - LPUART2_RX - USART6_RTS _DE_CK - - - - PF4 - LPUART1_TX - - - - - - PF5 - LPUART1_RX - - - - - - PF6 - LPUART1_RTS _DE - - - - - - PF7 - LPUART1_CTS - USART5_CTS - - - - PF8 - - - - - - - - PF9 - - - USART6_TX - - - - PF10 - - - USART6_RX - - - - PF11 - - - USART6_RTS _DE_CK - - - - PF12 TIM15_CH1 - - USART6_CTS - - - - PF13 TIM15_CH2 - - - - - - - STM32G0B1xB/xC/xE Table 20. Port F alternate function mapping 63/158 Electrical characteristics STM32G0B1xB/xC/xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored. Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = VDDIO2 = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 13. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 14. Figure 13. Pin loading conditions Figure 14. Pin input voltage MCU pin MCU pin C = 50 pF 64/158 VIN DS13560 Rev 4 STM32G0B1xB/xC/xE 5.1.6 Electrical characteristics Power supply scheme Figure 15. Power supply scheme VBAT Backup circuitry (LSE, RTC and backup registers) 1.55 V to 3.6 V Power switch VDD VCORE VDD/VDDA VDD Regulator 1 x 100 nF + 1 x 4.7 μF GPIOs IN Level shifter OUT IO logic Level shifter VDDIO1 IO logic Kernel logic (CPU, digital and memories) VSS VDDIO2 VDDIO2 VDDIO2 OUT GPIOs IN 100 nF +4.7 μF VREF VDDA VREF+ VREF+ 100 nF 1 μF VREF- ADC DAC COMPs VREFBUF VSSA VSS/VSSA MSv66839V2 Caution: Power supply pin pair (VDD/VDDA/VDDIO2 and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS13560 Rev 4 65/158 123 Electrical characteristics 5.1.7 STM32G0B1xB/xC/xE Current consumption measurement Figure 16. Current consumption measurement scheme IDDVBAT VBAT VDD (VDDA) IDD VBAT VDD/VDDA VDDIO2 MSv66840V1 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 21, Table 22 and Table 23 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are defined with respect to VSS. Table 21. Voltage characteristics Symbol Min Max External supply voltage -0.3 4.0 External supply voltage for selected I/Os -0.3 4.0 VBAT External supply voltage on VBAT pin -0.3 4.0 VREF+ External voltage on VREF+ pin -0.3 Min(VDD + 0.4, 4.0) VDD VDDIO2 VIN(1) Ratings -0.3 Input voltage on FT_c pins -0.3 5.5 Input voltage on any other pin -0.3 4.0 2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 66/158 (2) Input voltage on FT_xx pins except FT_c 1. Refer to Table 22 for the maximum allowed injected current values. DS13560 Rev 4 Unit VDD + 4.0 V STM32G0B1xB/xC/xE Electrical characteristics Table 22. Current characteristics Symbol Ratings IVDD/VDDA /VDDIO2 IVSS/VSSA IIO(PIN) ∑IIO(PIN) Max Current into VDD/VDDA/VDDIO2 power pin (source)(1) 100 Current out of VSS/VSSA ground pin (sink)(1) 100 Output current sunk by any I/O and control pin except FT_f 15 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 15 Total output current sunk by sum of all I/Os and control pins 80 Total output current sourced by sum of all I/Os and control pins 80 Injected current on a TT_a pin(4) ∑|IINJ(PIN)| mA -5 / NA(3) Injected current on a FT_xx pin IINJ(PIN)(2) Unit -5 / 0 Total injected current (sum of all I/Os and control pins) (5) 25 1. All main power (VDD/VDDA/VDDIO2, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. On these I/Os, any current injection disturbs the analog performances of the device. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 23. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Value Unit -65 to +150 °C 150 °C Table 24. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 64 fPCLK Internal APB clock frequency - 0 64 VDD Standard operating voltage - 1.7(1) 3.6 V VDDIO2 External supply voltage for selected I/Os - 1.7 3.6 V DS13560 Rev 4 MHz 67/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 24. General operating conditions (continued) Symbol VDDA VBAT VIN Parameter Conditions Min Max For ADC and COMP operation 1.62 3.6 For DAC operation 1.8 3.6 For VREFBUF operation 2.4 3.6 - 1.55 3.6 Analog supply voltage Backup operating voltage All except TT_xx and FT_c -0.3 TT_xx -0.3 VDD + 0.3 FT_c -0.3 5.0(2) Suffix 6(4) -40 85 (4) -40 105 3(4) -40 125 Suffix 6(4) -40 105 7(4) -40 125 (4) -40 130 I/O input voltage TA Ambient temperature(3) Suffix 7 Suffix TJ Suffix Junction temperature Suffix 3 Unit V V Min(VDD + 3.6, 5.5) (2) V °C °C 1. When RESET is released functionality is guaranteed down to VPDR min. 2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled. 3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.11: Thermal characteristics. 4. Temperature range digit in the order code. See Section 7: Ordering information. 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 25 are derived from tests performed under the ambient temperature condition summarized in Table 24. Table 25. Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.3 VDD slew rate Conditions Min Max VDD rising - ∞ VDD falling; ULPEN = 0 10 ∞ VDD falling; ULPEN = 1 100 ∞ Unit µs/V ms/V Embedded reset and power control block characteristics The parameters given in Table 26 are derived from tests performed under the ambient temperature conditions summarized in Table 24: General operating conditions. Table 26. Embedded reset and power control block characteristics Symbol tRSTTEMPO VPOR(2) 68/158 (2) Parameter Conditions(1) Min Typ Max Unit POR temporization when VDD crosses VPOR VDD rising - 250 400 μs - 1.62 1.66 1.70 V Power-on reset threshold DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 26. Embedded reset and power control block characteristics (continued) Symbol Parameter VPDR(2) Power-down reset threshold VBOR1 Brownout reset threshold 1 VBOR2 Brownout reset threshold 2 VBOR3 Brownout reset threshold 3 VBOR4 Brownout reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_POR_PDR Hysteresis of VPOR and VPDR Conditions(1) Min Typ Max Unit - 1.60 1.64 1.69 V VDD rising 2.05 2.10 2.18 VDD falling 1.95 2.00 2.08 VDD rising 2.20 2.31 2.38 VDD falling 2.10 2.21 2.28 VDD rising 2.50 2.62 2.68 VDD falling 2.40 2.52 2.58 VDD rising 2.80 2.91 3.00 VDD falling 2.70 2.81 2.90 VDD rising 2.05 2.15 2.22 VDD falling 1.95 2.05 2.12 VDD rising 2.20 2.30 2.37 VDD falling 2.10 2.20 2.27 VDD rising 2.35 2.46 2.54 VDD falling 2.25 2.36 2.44 VDD rising 2.50 2.62 2.70 VDD falling 2.40 2.52 2.60 VDD rising 2.65 2.74 2.87 VDD falling 2.55 2.64 2.77 VDD rising 2.80 2.91 3.03 VDD falling 2.70 2.81 2.93 VDD rising 2.90 3.01 3.14 VDD falling 2.80 2.91 3.04 Hysteresis in continuous mode - 20 - Hysteresis in other mode - 30 - V V V V V V V V V V V mV Vhyst_BOR_PVD Hysteresis of VBORx and VPVDx - - 100 - mV IDD(BOR_PVD)(2) BOR and PVD consumption - - 1.1 1.6 µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. DS13560 Rev 4 69/158 123 Electrical characteristics 5.3.4 STM32G0B1xB/xC/xE Embedded voltage reference The parameters given in Table 27 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 27. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max Unit -40°C < TJ < 130°C 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs IDD(VREFINTBUF) VREFINT buffer consumption from VDD when converted by ADC - - 12.5 20(2) µA ∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV - - 30 50(2) ppm/°C 300 1000(2) ppm - 250 1200(2) ppm/V 24 25 26 49 50 51 74 75 76 TCoeff_vrefint ACoeff VDDCoeff Temperature coefficient Long term stability 1000 hours, T = 25 °C Voltage coefficient VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage 3.0 V < VDD < 3.6 V - - % VREFINT 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Figure 17. VREFINT vs. temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 70/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 5.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 16: Current consumption measurement scheme. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0444 reference manual). • When the peripherals are enabled fPCLK = fHCLK • For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS Unless otherwise stated, values given in Table 28 through Table 36 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. DS13560 Rev 4 71/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 28. Current consumption in Run and Low-power run modes at different die temperatures Conditions Symbol Parameter General 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 64 MHz 8.6 8.8 9.4 9.0 9.1 9.7 56 MHz 7.5 7.8 8.3 7.9 8.0 8.6 6.7 7.0 7.6 7.1 7.2 7.8 4.6 4.8 5.4 4.8 5.0 5.5 24 MHz 3.6 3.8 4.3 3.8 4.1 4.6 16 MHz 2.3 2.5 3.0 2.4 2.6 3.2 64 MHz 8.8 8.9 9.4 9.3 9.4 9.9 56 MHz 7.7 7.8 8.3 8.2 8.3 8.8 6.9 7.0 7.5 7.3 7.4 7.9 4.7 4.8 5.3 5.0 5.1 5.6 24 MHz 3.6 3.8 4.3 4.1 4.2 4.7 16 MHz 2.3 2.4 2.9 2.5 2.6 3.2 1.8 2.0 2.4 2.2 2.3 2.9 1.0 1.1 1.6 1.3 1.4 2.1 2 MHz 0.3 0.4 0.9 0.6 0.9 1.4 16 MHz 1.9 2.0 2.5 2.3 2.4 3.0 1.0 1.1 1.6 1.3 1.5 2.1 2 MHz 0.3 0.4 0.9 0.6 0.9 1.4 2 MHz 280 415 950 585 845 1515 155 285 820 530 835 1315 90 220 750 475 795 1220 45 170 700 445 745 1190 30 155 695 430 720 1185 250 360 855 575 835 1495 140 260 730 530 825 1300 80 205 650 475 780 1230 125 kHz 40 155 635 440 745 1200 32 kHz 30 135 625 415 715 1180 fHCLK 48 MHz Range 1; PLL enabled; fHCLK = fHSE_bypass (≤16 MHz), fHCLK = fPLLRCLK (>16 MHz); IDD(Run) Supply (3) current in Run mode (from Flash memory) Range 2; PLL enabled; fHCLK = fHSE_bypass (≤16 MHz), fHCLK = fPLLRCLK (>16 MHz); (3) 32 MHz 48 MHz 32 MHz Fetch from(2) Flash memory SRAM 16 MHz 8 MHz 8 MHz Flash memory SRAM 1 MHz 500 kHz IDD(LPRun) Supply current in Low-power run mode Max(1) Typ PLL disabled; 125 kHz fHCLK = fHSE bypass (> 32 kHz), 32 kHz fHCLK = fLSE 2 MHz bypass (= 32 kHz); (3) 1 MHz 500 kHz Flash memory SRAM Unit mA µA 1. Based on characterization results, not tested in production. 2. Prefetch and cache enabled when fetching from Flash memory. Code compiled with high optimization for space in SRAM. 3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled. 72/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 29. Typical current consumption in Run and Low-power run modes, depending on code executed Conditions Symbol Typ Parameter General Fetch from(1) 8.70 136 8.15 127 8.00 125 Fibonacci 7.30 114 While(1) loop 5.90 92 8.85 138 9.10 142 8.95 140 Fibonacci 9.85 154 While(1) loop 8.85 Dhrystone 2.1 Reduced Flash memory code(3) Coremark Dhrystone 2.1 IDD(Run) Supply current in Run mode Reduced SRAM code(3) 2.45 Coremark (2) 119 Fibonacci 1.70 106 While(1) loop 1.35 84 Reduced code(3) 2.10 131 Coremark 2.10 131 2.05 128 Fibonacci 2.25 141 While(1) loop 2.05 128 485 243 475 238 480 240 500 250 Flash memory SRAM code(3) Coremark Dhrystone 2.1 IDD(LPRun) (2) 153 1.90 Reduced fHCLK = fHSI16/8 = 2 MHz; PLL disabled, 138 119 Dhrystone 2.1 Supply current in Low-power run mode mA 1.90 Dhrystone 2.1 Range 2; fHCLK = fHSI16 = 16 MHz, PLL disabled, Unit 25 °C Coremark (2) Unit 25 °C Code Reduced code(3) Range 1; fHCLK = fPLLRCLK = 64 MHz; Typ Flash memory Fibonacci While(1) loop Reduced code 515 (3) 490 Coremark μA 258 245 485 243 480 240 Fibonacci 510 255 While(1) loop 480 240 Dhrystone 2.1 SRAM μA/MHz μA/MHz 1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM. 2. VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM DS13560 Rev 4 73/158 123 Electrical characteristics STM32G0B1xB/xC/xE 3. Reduced code used for characterization results provided in Table 28. Table 30. Current consumption in Sleep and Low-power sleep modes Conditions Symbol Parameter Voltage scaling General IDD(Sleep) Supply current in Sleep mode Max(1) Typ fHCLK 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 64 MHz 1.9 2.0 2.6 2.5 2.6 3.3 56 MHz 1.7 1.8 2.4 2.2 2.4 3.2 48 MHz 1.5 1.6 2.2 1.9 2.1 2.8 32 MHz 1.1 1.2 1.8 1.4 1.6 2.3 24 MHz 0.9 1.0 1.6 1.2 1.3 2.1 16 MHz 0.5 0.6 1.2 0.7 0.9 1.6 16 MHz 0.4 0.6 1.0 0.6 0.7 1.4 8 MHz 0.3 0.4 0.9 0.4 0.5 1.2 2 MHz 0.2 0.3 0.7 0.2 0.4 1.0 2 MHz 70 200 705 175 500 1325 1 MHz 48 175 685 145 438 1285 500 kHz 37 165 670 130 413 1255 125 kHz 28 155 665 105 388 1250 32 kHz 26 150 660 90 Flash memory enabled; fHCLK = fHSE bypass Range 1 (≤16 MHz; PLL disabled), fHCLK = fPLLRCLK (>16 MHz; PLL enabled); All peripherals disabled Range 2 Flash memory disabled; Supply PLL disabled; current in =f bypass (> 32 kHz), f IDD(LPSleep) Low-power HCLK HSE fHCLK = fLSE bypass (= 32 kHz); sleep mode All peripherals disabled Unit mA µA 375 1210 1. Based on characterization results, not tested in production. Table 31. Current consumption in Stop 0 mode Conditions Symbol Parameter Unit HSI kernel Enabled IDD(Stop 0) Supply current in Stop 0 mode Disabled VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 290 370 675 370 470 850 2.4 V 295 370 680 370 470 870 3V 295 375 695 375 475 930 3.6 V 300 380 695 375 475 1050 1.8 V 100 190 505 180 290 680 2.4 V 100 195 510 180 290 685 3V 105 195 525 180 295 695 3.6 V 105 200 530 185 305 830 1. Based on characterization results, not tested in production. 74/158 Max(1) Typ DS13560 Rev 4 µA STM32G0B1xB/xC/xE Electrical characteristics Table 32. Current consumption in Stop 1 mode Conditions Symbol Parameter Flash memory Unit RTC(2) Disabled Not powered IDD(Stop 1) Supply current in Stop 1 mode Enabled Powered Max(1) Typ Disabled VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 2.9 25 105 - - - 2.4 V 3.1 26 110 - - - 3V 3.3 26 110 - - - 3.6 V 3.6 26 110 - - - 1.8 V 3.3 25 105 - - - 2.4 V 3.6 26 110 - - - 3V 3.7 26 110 - - - 3.6 V 4.2 27 110 - - - 1.8 V 7.0 30 110 - - - 2.4 V 7.3 30 115 - - - 3V 7.5 30 115 - - - 3.6 V 7.8 31 115 - - - µA 1. Based on characterization results, not tested in production. 2. Clocked by LSI Table 33. Current consumption in Standby mode Symbol Parameter Conditions General RTC disabled RTC enabled, clocked by LSI; IDD(Standby) Supply current in Standby mode(2) IWDG enabled, clocked by LSI ULPEN = 0 Max(1) Typ VDD 25°C 85°C 1.8 V 0.1 2.4 V 0.1 3.0 V 125°C 25°C 85°C 130°C 2.1 9.4 0.8 14 45 2.5 11.5 1.2 17 54 0.2 3.0 13.5 1.4 18 64 3.6 V 0.3 3.5 16.0 1.8 21 74 1.8 V 0.4 2.3 9.7 2.0 15 45 2.4 V 0.5 2.8 11.5 2.5 18 55 3.0 V 0.7 3.4 14.0 3.0 20 64 3.6 V 0.9 4.0 16.0 3.3 23 75 1.8 V 0.3 2.3 9.6 2.1 14 45 2.4 V 0.4 2.7 11.5 2.3 17 54 3.0 V 0.5 3.3 13.5 2.6 19 64 3.6 V 0.7 3.8 16.0 3.0 22 74 1.8 V 0.7 2.0 9.4 - - - 2.4 V 0.9 2.4 11.0 - - - 3.0 V 1.1 2.9 13.5 - - - 3.6 V 1.3 3.4 15.5 - - - DS13560 Rev 4 Unit µA 75/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 33. Current consumption in Standby mode (continued) Symbol ∆IDD(SRAM) Conditions Parameter General Extra supply current to retain SRAM content(3) SRAM retention enabled Max(1) Typ VDD 25°C 85°C 125°C 25°C 85°C 130°C 1.8 V 1.0 11.5 57 4.3 41 265 2.4 V 1.0 11.5 57 4.3 41 265 3.0 V 1.1 11.6 58 4.4 41 270 3.6 V 1.2 11.6 59 4.4 42 270 Unit µA 1. Based on characterization results, not tested in production. 2. Without SRAM retention and with ULPEN bit set 3. To be added to IDD(Standby) as appropriate Table 34. Current consumption in Shutdown mode Symbol Conditions Parameter RTC VDD Disabled IDD(Shutdown) Supply current in Shutdown mode Enabled, clocked by LSE bypass at 32.768 kHz Max(1) Typ 25 °C 85 °C 125 °C 25 °C 85 °C 130 °C 1.8 V 23 840 7050 240 3210 39200 2.4 V 38 965 8050 370 3910 44600 3.0 V 38 1100 9550 370 4700 51500 3.6 V 57 1350 11000 500 5700 59400 1.8 V 235 1050 7400 290 3850 47000 2.4 V 320 1250 8400 440 4690 53500 3.0 V 425 1500 9950 450 5640 61800 3.6 V 550 1850 11500 590 6840 71200 Unit nA 1. Based on characterization results, not tested in production. Table 35. Current consumption in VBAT mode Symbol Parameter Conditions RTC Enabled, clocked by LSE bypass at 32.768 kHz IDD(VBAT) Supply current in VBAT mode Enabled, clocked by LSE crystal at 32.768 kHz Disabled 76/158 DS13560 Rev 4 Typ VDD 25°C 85°C 125°C 1.8 V 195 416 2015 2.4 V 320 530 2366 3.0 V 492 635 2838 3.6 V 627 908 3339 1.8 V 130 325 1550 2.4 V 160 400 1800 3.0 V 210 500 2050 3.6 V 285 605 2400 1.8 V 4 160 1450 2.4 V 4 190 1700 3.0 V 4 220 1950 3.6 V 7 270 2250 Unit nA STM32G0B1xB/xC/xE Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 55: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (seeTable 36: Current consumption of peripherals ), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DS13560 Rev 4 77/158 123 Electrical characteristics STM32G0B1xB/xC/xE On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 21: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 36. Current consumption of peripherals Consumption in µA/MHz Peripheral Range 1 Range 2 Low-power run and sleep IOPORT Bus IOPORT 0.5 0.4 0.3 GPIOA IOPORT 3.1 2.4 3.0 GPIOB IOPORT 2.9 2.3 3.0 GPIOC IOPORT 3.0 2.4 2.8 GPIOD IOPORT 2.7 2.2 2.5 GPIOE IOPORT 1.6 1.4 1.6 GPIOF IOPORT 2.8 2.3 2.6 Bus matrix AHB 0.5 0.5 0.5 All AHB Peripherals AHB 31 26 30 DMA1/DMAMUX AHB 5.1 4.3 4.9 CRC AHB 0.4 0.4 0.5 FLASH AHB 22 18 21 All APB peripherals APB 120 110 220 APB 0.2 0.2 0.1 APB 0.4 0.3 0.4 WWDG APB 0.4 0.4 0.4 DMA2 APB 1.5 1.3 1.5 TIM1 APB 7.6 6.3 7.2 TIM2 APB 5.2 4.3 4.9 TIM3 APB 4.7 3.9 4.3 TIM4 APB 4.4 3.7 4.2 TIM6 APB 1.2 1.0 1.1 TIM7 APB 0.8 0.7 0.8 TIM14 APB 1.4 1.2 1.3 AHB to APB bridge(1) PWR 78/158 Bus DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 36. Current consumption of peripherals (continued) Consumption in µA/MHz Peripheral Bus Range 1 Range 2 Low-power run and sleep TIM15 APB 4.2 3.5 3.9 TIM16 APB 2.7 2.3 2.5 TIM17 APB 0.8 0.7 0.7 LPTIM1 APB 3.3 2.7 3.1 LPTIM2 APB 3.2 2.7 3.1 I2C1 APB 3.6 3.0 3.3 I2C2 APB 3.4 2.8 3.2 I2C3 APB 0.9 0.7 0.8 SPI1 APB 2.2 1.9 2.1 SPI2 APB 2.1 1.7 2.0 SPI3 APB 1.4 1.2 1.3 USART1 APB 7.4 6.2 6.9 USART2 APB 7.4 6.2 7.0 USART3 APB 7.4 6.2 6.9 USART4 APB 2.1 1.8 2.0 USART5 APB 2.3 1.9 2.1 USART6 APB 2.2 1.8 2.1 LPUART1 APB 4.5 3.7 4.2 LPUART2 APB 4.9 4.1 4.6 ADC APB 2.4 2.0 2.3 DAC1 APB 1.9 1.6 1.8 SYSCFG/VREFBUF/COMP APB 0.5 0.4 0.5 CEC APB 0.4 0.3 0.3 CRS APB 0.2 0.2 0.3 USB APB 3.3 2.7 3.0 FDCAN APB 16 13 15 UCPD1 APB 4.0 7.9 59.0(2) UCPD2 APB 4.0 7.9 59.5(2) 1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB. 2. UCPDx are always clocked by HSI16. DS13560 Rev 4 79/158 123 Electrical characteristics 5.3.6 STM32G0B1xB/xC/xE Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 37 are the latency between the event and the execution of the first user instruction. Table 37. Low-power mode wakeup times(1) Symbol Parameter Conditions Typ Max tWUSLEEP Wakeup time from Sleep to Run mode - 11 11 Wakeup time from Transiting to Low-power-run-mode execution in Flash tWULPSLEEP Low-power sleep memory not powered in Low-power sleep mode; mode HCLK = HSI16 / 8 = 2 MHz tWUSTOP0 Transiting to Run-mode execution in Flash memory not powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Wakeup time from Regulator in Range 1 or Range 2 Stop 0 Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2 Transiting to Run-mode execution in Flash memory not powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2 tWUSTOP1 Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Wakeup time from Regulator in Range 1 or Range 2 Stop 1 Transiting to Low-power-run-mode execution in Flash memory not powered in Stop 1 mode; HCLK = HSI16/8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1) Transiting to Low-power-run-mode execution in SRAM or in Flash memory powered in Stop 1 mode; HCLK = HSI16 / 8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1) tWUSTBY 80/158 Transiting to Run mode; Wakeup time from HCLK = HSI16 = 16 MHz; Standby mode Regulator in Range 1 DS13560 Rev 4 Unit CPU cycles 11 14 5.6 6 µs 2 2.4 9.0 11.2 5 7.5 µs 22 25.3 18 23.5 14.5 30 µs STM32G0B1xB/xC/xE Electrical characteristics Table 37. Low-power mode wakeup times(1) (continued) Symbol Parameter Conditions tWUSHDN Transiting to Run mode; Wakeup time from HCLK = HSI16 = 16 MHz; Shutdown mode Regulator in Range 1 tWULPRUN Wakeup time from Transiting to Run mode; Low-power run HSISYS = HSI16/8 = 2 MHz mode(2) Typ Max Unit 258 340 µs 5 7 µs 1. Based on characterization results, not tested in production. 2. Time until REGLPF flag is cleared in PWR_SR2. Table 38. Regulator mode transition times(1) Symbol Parameter Conditions Transition times between regulator Range 1 and Range 2(2) tVOST HSISYS = HSI16 Typ Max Unit 20 40 µs Typ Max Unit - 1.7 - 8.5 1. Based on characterization results, not tested in production. 2. Time until VOSF flag is cleared in PWR_SR2. Table 39. Wakeup time using LPUART(1) Symbol Parameter tWULPUART Conditions Stop mode 0 Wakeup time needed to calculate the maximum LPUART baud rate allowing to wakeup up from Stop mode when LPUART clock source is HSI16 Stop mode 1 µs 1. Guaranteed by design. 5.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 18 for recommended clock input waveform. Table 40. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1 VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIO1 DS13560 Rev 4 Unit V 81/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 40. High-speed external user clock characteristics(1) (continued) Symbol Parameter tw(HSEH) OSC_IN high or low time tw(HSEL) Conditions Min Typ Max Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 Unit ns - - 1. Guaranteed by design. Figure 18. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. See Figure 19 for recommended clock input waveform. Table 41. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIO1 - VDDIO1 VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIO1 - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) 1. Guaranteed by design. 82/158 DS13560 Rev 4 V ns STM32G0B1xB/xC/xE Electrical characteristics Figure 19. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% 10% VLSEL tr(LSE) t tf(LSE) tw(LSEL) TLSE MS19215V2 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 42. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 42. HSE oscillator characteristics(1) Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Maximum critical crystal transconductance Startup - - 1.5 mA/V Startup time VDD is stabilized - 2 - ms Symbol fOSC_IN RF Parameter During startup IDD(HSE) Gm tSU(HSE)(4) HSE current consumption (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. DS13560 Rev 4 83/158 123 Electrical characteristics STM32G0B1xB/xC/xE 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 20. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 43. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 84/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 43. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Conditions(2) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - Unit nA µA/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS13560 Rev 4 85/158 123 Electrical characteristics 5.3.8 STM32G0B1xB/xC/xE Internal clock source characteristics The parameters given in Table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 44. HSI16 oscillator characteristics(1) Symbol fHSI16 Parameter Conditions Min Typ Max Unit 15.88 - 16.08 MHz HSI16 Frequency VDD=3.0 V, TA=30 °C ∆Temp(HSI16) HSI16 oscillator frequency drift over temperature TA= 0 to 85 °C -1 - 1 % TA= -40 to 125 °C -2 - 1.5 % ∆VDD(HSI16) HSI16 oscillator frequency drift over VDD -0.1 - 0.05 % -8 -6 -4 -5.8 -3.8 -1.8 0.2 0.3 0.4 VDD=1.62 V to 3.6 V From code 127 to 128 From code 63 to 64 HSI16 frequency user trimming step From code 191 to 192 TRIM For all other code increments DHSI16(2) tsu(HSI16)(2) tstab(HSI16) (2) IDD(HSI16)(2) Duty Cycle - 45 - 55 % HSI16 oscillator start-up time - - 0.8 1.2 μs HSI16 oscillator stabilization time - - 3 5 μs HSI16 oscillator power consumption - - 155 190 μA 1. Based on characterization results, not tested in production. 2. Guaranteed by design. 86/158 % DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Figure 22. HSI16 frequency vs. temperature MHz 16.4 +2% 16.3 +1.5% 16.2 +1% 16.1 16 15.9 -1% 15.8 -1.5% 15.7 -2% 15.6 -40 -20 0 20 40 min 60 80 mean 100 120 °C max MSv39299V1 High-speed internal 48 MHz (HSI48) RC oscillator Table 45. HSI48 oscillator characteristics(1) Symbol Parameter fHSI48 HSI48 Frequency TRIM HSI48 user trimming step USER TRIM COVERAGE Conditions Typ Max Unit - 48 - MHz - 0.11(2) 0.18(2) % ±6(3) ±7(3) - % 45(2) - 55(2) % VDD = 3.0 V to 3.6 V, TA = –15 to 85 °C - - ±3(3) VDD = 1.65 V to 3.6 V, TA = –40 to 125 °C - - ±4.5(3) VDD = 3 V to 3.6 V - 0.025(3) 0.05(3) VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3) VDD=3.0V, TA=30°C - HSI48 user trimming coverage ±64 steps DuCy(HSI48) Duty Cycle - Accuracy of the HSI48 oscillator ACCHSI48_REL over temperature (factory calibrated) DVDD(HSI48) Min HSI48 oscillator frequency drift with VDD % % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns DS13560 Rev 4 87/158 123 Electrical characteristics STM32G0B1xB/xC/xE 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. Figure 23. HSI48 frequency versus temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 10 30 Avg 50 70 90 min 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 46. LSI oscillator characteristics(1) Symbol Parameter LSI frequency fLSI tSU(LSI)(2) (2) tSTAB(LSI) IDD(LSI)(2) Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - 80 130 μs - 125 180 μs - 110 180 nA LSI oscillator start-up time LSI oscillator stabilization time 5% of final frequency LSI oscillator power consumption - 1. Based on characterization results, not tested in production. 2. Guaranteed by design. 88/158 DS13560 Rev 4 Unit kHz STM32G0B1xB/xC/xE 5.3.9 Electrical characteristics PLL characteristics The parameters given in Table 47 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions. Table 47. PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock frequency(2) - 2.66 - 16 MHz DPLL_IN PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.09 - 122 Voltage scaling Range 2 3.09 - 40 Voltage scaling Range 1 12 - 128 Voltage scaling Range 2 12 - 33 Voltage scaling Range 1 12 - 64 Voltage scaling Range 2 12 - 16 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 96 - 128 - 15 40 - 50 - - 40 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time - RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 56 MHz MHz MHz MHz MHz μs ±ps μA 1. Guaranteed by design. 2. Make sure to use the appropriate division factor M to obtain the specified PLL input clock values. 5.3.10 Flash memory characteristics Table 48. Flash memory characteristics(1) Symbol tprog Parameter Row (32 double word) programming time tprog_page Page (2 Kbyte) programming time tprog_bank tME Typ Max Unit - 85 125 µs Normal programming 2.7 4.6 Fast programming 1.7 2.8 Normal programming 21.8 36.6 Fast programming 13.7 22.4 22.0 40.0 Normal programming 2.8 4.7 Fast programming 1.8 2.9 22.1 40.1 64-bit programming time tprog_row tERASE Conditions Page (2 Kbyte) erase time - Bank (512 Kbyte(2)) programming time Mass erase time - DS13560 Rev 4 ms s ms 89/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 48. Flash memory characteristics(1) (continued) Symbol IDD(FlashA) IDD(FlashP) Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Programming 3 - Page erase 3 - Mass erase 5 - Programming, 2 µs peak duration 7 - Erase, 41 µs peak duration 7 - Unit mA mA 1. Guaranteed by design. 2. Values provided also apply to devices with less Flash memory than one 512 Kbyte bank Table 49. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = -40 to +105 °C 1 kcycle(2) 10 kcycles 30 at TA = 105 °C 15 1 kcycle(2) at TA = 125 °C 7 10 kcycles(2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 1 kcycle Data retention Unit at TA = 85 °C (2) tRET Min(1) (2) 10 kcycles at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 50. They are based on the EMS levels and classes defined in application note AN1709. 90/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 50. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 64 MHz, LQFP100, conforming to IEC 61000-4-2 2B VEFTB VDD = 3.3 V, TA = +25 °C, Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a fHCLK = 64 MHz, LQFP100, functional disturbance conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • corrupted program counter • unexpected reset • critical data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. DS13560 Rev 4 91/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 51. EMI characteristics Symbol Parameter Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8 MHz / 64 MHz SEMI Peak level VDD = 3.6 V, TA = 25 °C, LQFP100 package compliant with IEC 61967-2 0.1 MHz to 30 MHz 9 30 MHz to 130 MHz 16 130 MHz to 1 GHz 4 1 GHz to 2 GHz 8 EMI level 5.3.12 dBµV 2.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 52. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001 2 2000 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002 C2a 250 Unit V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current is injected to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 53. Electrical sensitivity Symbol LU 92/158 Parameter Static latch-up class Conditions TA = +125 °C conforming to JESD78 DS13560 Rev 4 Class II Level A STM32G0B1xB/xC/xE 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 54. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Injected current on pin Unit Negative injection Positive injection All except PA4, PA5, PA6, PB0, PB3, and PC0 -5 N/A mA PA4, PA5 -5 0 mA PA6, PB0, PB3, and PC0 0 N/A mA 1. Based on characterization results, not tested in production. DS13560 Rev 4 93/158 123 Electrical characteristics 5.3.14 STM32G0B1xB/xC/xE I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 55. I/O static characteristics Symbol VIL(1) Parameter I/O input low level voltage Conditions All except 1.62 V < VDDIOx < 3.6 V FT_c I/O input high level voltage I/O input hysteresis Ilkg (2) - 2.7 V < VDDIOx < 3.6 V - 1.62 V < VDDIOx < 2.7 V - - 0.39 x VDDIOx - 0.06 (3) V 2) - - 0.49 x VDDIOx + 0.26(3) - - 0.7 x VDDIOx - 5 TT_xx, FT_xx, 1.62 V < VDDIOx < 3.6 V NRST - 200 - 0 < VIN ≤ VDDIOx - - ±70 VDDIOx ≤ VIN ≤ VDDIOx+1 V - - 600(4) VDDIOx +1 V < VIN ≤ 5.5 V(3) - - 150(4) 0 < VIN ≤ VDDIOx - - 2000 VDDIOx < VIN ≤ 5 V - - 3000(4) 0 < VIN ≤ VDDIOx - - 4500 VDDIOx < VIN ≤ 5.5 V - - 9000(4) 0 < VIN ≤ VDDIOx - - ±150 VDDIOx < VIN ≤ VDDIOx + 0.3 V - - 2000(4) 25 40 55 kΩ 25 40 55 kΩ - 5 - pF All except 1.62 V < VDDIOx < 3.6 V FT_c FT_c TT_a 1.62 V < VDDIOx < 3.6 V RPU Weak pull-up equivalent resistor RPD Weak pull-down V = VDDIOx equivalent resistor(5) IN CIO I/O pin capacitance VIN = VSS - 1. Refer to Figure 24: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 94/158 0.3 x VDDIOx 0.25 x VDDIOx FT_d (5) Unit - FT_xx except FT_c and FT_d Input leakage current(3) Max 0.3 x VDDIOx FT_c Vhys(3) Typ - FT_c VIH(1) Min DS13560 Rev 4 0.7 x VDDIOx ( V mV nA STM32G0B1xB/xC/xE Electrical characteristics 4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max). 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 24. Figure 24. I/O input characteristics 3 2.5 Minimum required logic level 1 zone TTL standard requirement nt) 2 rd r tanda Ss (CMO VIN (V) 1.5 V IHmin = 0.7 VIHmin = eme equir V DDIO 0.49 VDDIO Undefined input range + 0.26 1 VILmax = 0.39 0.5 VILmax = 0.3 VDDIO - 0.06 VDDIO TTL standard requirement ment) dard require (CMOS stan Minimum required logic level 0 zone 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDDIO (V) Device characteristics Test thresholds MSv47925V1 Characteristics of FT_e I/Os The following table and figure specify input characteristics of FT_e I/Os. Table 56. Input characteristics of FT_e I/Os Symbol IINJ VDDIO1-VIN Rd Parameter Conditions Min Typ Max Unit - - - 5 mA Voltage over VDDIO1 IINJ = 5 mA - - 2 V Diode dynamic serial resistor IINJ = 5 mA - - 300 Ω Injected current on pin DS13560 Rev 4 95/158 123 Electrical characteristics STM32G0B1xB/xC/xE Figure 25. Current injection into FT_e input with diode active 5 -40°C 25°C 125°C 4 3 IINJ (mA) 2 1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VIN – VDDIO1 (V) 1.4 1.6 1.8 2 MSv63112V1 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and up to ±15 mA with relaxed VOL/VOH. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: • The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 21: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 21: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). 96/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 57. Output voltage characteristics(1) Symbol Parameter Conditions VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin CMOS port(2) |IIO| = 2 mA for FT_c I/Os = 8 mA for other I/Os VDDIOx ≥ 2.7 V TTL port(2) |IIO| = 2 mA for FT_c I/Os = 8 mA for other I/Os VDDIOx ≥ 2.7 V All I/Os except FT_c |IIO| = 15 mA VDDIOx ≥ 2.7 V |IIO| = 1 mA for FT_c I/Os = 3 mA for other I/Os VDDIOx ≥ 1.62 V Min Max - 0.4 VDDIOx - 0.4 - - 0.4 2.4 - - 1.3 VDDIOx - 1.3 - - 0.4 VDDIOx - 0.45 - - 0.4 - 0.4 |IIO| = 20 mA VDDIOx ≥ 2.7 V VOLFM+ Output low level voltage for an FT I/O (3) pin in FM+ mode (FT I/O with _f option) |I | = 9 mA IO VDDIOx ≥ 1.62 V Unit V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 26 and Table 58, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 58. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Output rise and fall time Conditions Min Max C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 0.35 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 0.45 C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 225 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 75 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 150 DS13560 Rev 4 Unit MHz ns 97/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 58. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 01 Tr/Tf Fmax Output rise and fall time Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency Output fall time(4) Min Max C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V Conditions - 10 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 2 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 15 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 2.5 C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 30 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 60 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 15 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 30 C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 30 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 15 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 60 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 30 C=50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 11 C=50 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 22 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 4 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 8 C=30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 60 C=30 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 30 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 80(3) C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 40 C=30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 5.5 C=30 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 11 C=10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2.5 C=10 pF, 1.6 V ≤ VDDIOx ≤ 2.7 V - 5 C=50 pF, 1.6 V ≤ VDDIOx ≤ 3.6 V Unit MHz ns MHz ns MHz ns - 1 MHz - 5 ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0444 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz. 4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification. 98/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Figure 26. I/O AC characteristics definition(1) 90% 10% 50% 50% 10% 90% t I,2RXW t U,2RXW T 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWW”7DQGLIWKHGXW\F\FOHLV r f ZKHQORDGHGE\WKHVSHFLILHGFDSDFLWDQFH MS32132V2 1. Refer to Table 58: I/O AC characteristics. 5.3.15 NRST input characteristics The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU. Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 59. NRST pin characteristics(1) Symbol Parameter Conditions Min Typ Max - - 0.3 x VDDIO1 Unit VIL(NRST) NRST input low level voltage - VIH(NRST) NRST input high level voltage - 0.7 x VDDIO1 - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ - - - 70 ns 1.7 V ≤ VDD ≤ 3.6 V 350 - - ns VF(NRST) NRST input filtered pulse VNF(NRST) NRST input not filtered pulse 1. V Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). DS13560 Rev 4 99/158 123 Electrical characteristics STM32G0B1xB/xC/xE Figure 27. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF MS19878V3 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 59: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3. The external capacitor on NRST must be placed as close as possible to the device. 5.3.16 Analog switch booster Table 60. Analog switch booster characteristics(1) Symbol VDD Parameter Min Typ Max Unit 1.62 V - 3.6 V Booster startup time - - 240 µs Booster consumption for 1.62 V ≤ VDD ≤ 2.0 V - - 250 Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V - - 500 Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V - - 900 Supply voltage tSU(BOOST) IDD(BOOST) µA 1. Guaranteed by design. 5.3.17 Analog-to-digital converter characteristics Unless otherwise specified, the parameters given in Table 61 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 24: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 61. ADC characteristics(1) Symbol Parameter Conditions(2) Min Typ Max Unit VDDA Analog supply voltage - 1.62 - 3.6 V VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA 100/158 VDDA < 2 V DS13560 Rev 4 VDDA V STM32G0B1xB/xC/xE Electrical characteristics Table 61. ADC characteristics(1) (continued) Conditions(2) Min Typ Max Range 1 0.14 - 35 Range 2 0.14 - 16 12 bits - - 2.50 10 bits - - 2.92 8 bits - - 3.50 6 bits - - 4.38 fADC = 35 MHz; 12 bits - - 2.33 12 bits - - fADC/15 Conversion voltage range - VSSA - VREF+ V RAIN External input impedance - - - 50 kΩ CADC Internal sample and hold capacitor - - 5 - pF tSTAB ADC power-up time - 2 Conversion cycle tCAL Calibration time fADC = 35 MHz 2.35 µs - 82 1/fADC Symbol fADC fs fTRIG VAIN (3) Parameter ADC clock frequency Sampling rate External trigger frequency CKMODE = 00 tLATR ts Trigger conversion latency Sampling time tADCVREG_STUP ADC voltage regulator start-up time tCONV Total conversion time (including sampling time) tIDLE Laps of time allowed between two conversions without rearm 2 - CKMODE = 01 6.5 CKMODE = 10 12.5 CKMODE = 11 3.5 3 Unit MHz MSps MHz 1/fADC 1/fPCLK fADC = 35 MHz; VDDA > 2V 0.043 - 4.59 µs 1.5 - 160.5 1/fADC fADC = 35 MHz; VDDA < 2V 0.1 - 4.59 µs 160.5 1/fADC - - - 20 µs fADC = 35 MHz Resolution = 12 bits 0.40 - 4.95 µs Resolution = 12 bits - DS13560 Rev 4 3.5 ts + 12.5 cycles for successive approximation = 14 to 173 - - 100 1/fADC µs 101/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 61. ADC characteristics(1) (continued) Symbol IDDA(ADC) IDDV(ADC) Parameter ADC consumption from VDDA ADC consumption from VREF+ Conditions(2) Min Typ Max fs = 2.5 MSps - 410 - fs = 1 MSps - 164 - fs = 10 kSps - 17 - fs = 2.5 MSps - 65 - fs = 1 MSps - 26 - fs = 10 kSps - 0.26 - Unit µA µA 1. Guaranteed by design 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details. Table 62. Maximum ADC RAIN . Resolution 12 bits Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) 1.5(3) 43 50 3.5 100 680 7.5 214 2200 12.5 357 4700 19.5 557 8200 39.5 1129 15000 79.5 2271 33000 160.5 4586 50000 43 68 3.5 100 820 7.5 214 3300 12.5 357 5600 19.5 557 10000 39.5 1129 22000 79.5 2271 39000 160.5 4586 50000 (3) 1.5 10 bits 102/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 62. Maximum ADC RAIN . (continued) Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) 1.5(3) 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 8 bits (3) 1.5 6 bits 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 3. Only allowed with VDDA > 2 V Table 63. ADC accuracy(1)(2)(3) Symbol ET Parameter Total unadjusted error Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 3 4 2 V < VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 3 6.5 1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 3 7.5 DS13560 Rev 4 Unit LSB 103/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 63. ADC accuracy(1)(2)(3) (continued) Symbol EO EG ED EL 104/158 Parameter Offset error Gain error Differential linearity error Integral linearity error Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 1.5 2 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 1.5 4.5 1.65 V < VDDA=VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 1.5 5.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 3 3.5 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 3 5 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 3 6.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 1.2 1.5 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 1.2 1.5 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 1.2 1.5 VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - 2.5 3 2 V < VDDA = VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range - 2.5 3 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; - 2.5 3.5 DS13560 Rev 4 Unit LSB LSB LSB LSB STM32G0B1xB/xC/xE Electrical characteristics Table 63. ADC accuracy(1)(2)(3) (continued) Symbol ENOB SINAD SNR Parameter Conditions(4) Min Typ Max VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 10.1 10.2 - 2 V < VDDA = VREF+ < 3.6 V; Effective fADC = 35 MHz; fs ≤ 2.5 MSps; number of bits TA = entire range 9.6 10.2 - 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; 9.5 10.2 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 62.5 63 - 59.5 63 - 59 63 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C 63 64 - 2 V < VDDA = VREF+ < 3.6 V; Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range ratio 60 64 - 60 64 - VDDA = VREF+ = 3 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = 25 °C - -74 -73 2 V < VDDA = VREF+ < 3.6 V; Total harmonic fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range distortion - -74 -70 - -74 -70 2 V < VDDA = VREF+ < 3.6 V; Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps; and distortion TA = entire range ratio 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; THD 1.65 V < VDDA = VREF+ < 3.6 V; TA = entire range Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps; Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps; Unit bit dB dB dB 1. Based on characterization results, not tested in production. 2. ADC DC accuracy values are measured after internal calibration. 3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current. 4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. DS13560 Rev 4 105/158 123 Electrical characteristics STM32G0B1xB/xC/xE Figure 28. ADC accuracy characteristics EG Code (1) Example of an actual transfer curve 4095 (2) Ideal transfer curve 4094 (3) End point correlation line 4093 ET total unadjusted error: maximum deviation between the actual and ideal transfer curves. (2) ET EO offset error: maximum deviation between the first actual transition and the first ideal one. (3) 7 (1) 6 EG gain error: deviation between the last ideal transition and the last actual one. 5 EL EO ED differential linearity error: maximum deviation between actual steps and the ideal ones. 4 3 ED EL integral linearity error: maximum deviation between any actual transition and the end point correlation line. 2 1 LSB ideal 1 0 1 2 3 4 5 6 7 4093 4094 4095 (VAIN / VREF+)*4095 MSv19880V3 Figure 29. Typical connection diagram using the ADC VDDA VT RAIN(1) VAIN Sample and hold ADC converter RADC AINx Cparasitic(2) VT Ilkg (3) 12-bit converter CADC MS33900V5 1. Refer to Table 61: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 55: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 55: I/O static characteristics for the values of Ilkg. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 15: Power supply scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 106/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 5.3.18 Electrical characteristics Digital-to-analog converter characteristics Table 64. DAC characteristics(1) Symbol VDDA VREF+ Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ Max Unit DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 3.6 V Other modes 1.80 - DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 VDDA V Other modes 1.80 - connected to VSSA 5 - - connected to VDDA 25 - - 9.6 11.7 13.8 RL Resistive load DAC output buffer ON RO Output Impedance DAC output buffer OFF Output impedance sample and hold mode, output buffer ON VDD = 2.7 V - - 2 RBON VDD = 2.0 V - - 3.5 Output impedance sample and hold mode, output buffer OFF VDD = 2.7 V - - 16.5 RBOFF VDD = 2.0 V - - 18.0 DAC output buffer ON - - 50 pF Sample and hold mode - 0.1 1 µF DAC output buffer ON 0.2 - VREF+ – 0.2 V DAC output buffer OFF 0 - VREF+ ±0.5 LSB - 1.7 3 ±1 LSB - 1.6 2.9 ±2 LSB - 1.55 2.85 ±4 LSB - 1.48 2.8 ±8 LSB - 1.4 2.75 CL CSH VDAC_OUT tSETTLING tWAKEUP(2) PSRR Capacitive load Voltage on DAC_OUT output Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF - 2 2.5 Wakeup time from off state (setting the ENx bit in the DAC Control register) until final value ±1 LSB Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - 4.2 7.5 Normal mode DAC output buffer OFF, CL ≤ 10 pF - 2 5 Normal mode DAC output buffer ON CL ≤ 50 pF, RL = 5 kΩ, DC - -80 -28 VDDA supply rejection ratio DS13560 Rev 4 kΩ kΩ kΩ kΩ µs µs dB 107/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 64. DAC characteristics(1) (continued) Symbol Parameter TW_to_W Minimum time between two consecutive writes into the DAC_DORx register to guarantee a correct DAC_OUT for a small variation of the input code (1 LSB) tSAMP Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when DACOUT reaches final value ±1LSB) Conditions DAC_MCR:MODEx[2:0] = 000 or 001 CL ≤ 50 pF; RL ≥ 5 kΩ DAC_MCR:MODEx[2:0] = 010 or 011 CL ≤ 10 pF µs 3.5 - 10.5 18 - 2 3.5 µs - - -(3) nA 5.2 7 8.8 pF 50 - - µs - 1500 - - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.2 DAC output buffer OFF CIint Internal sample and hold capacitor tTRIM Middle code offset trim time DAC output buffer ON Voffset Middle code offset for 1 trim VREF+ = 3.6 V code step VREF+ = 1.8 V - Sample and hold mode, CSH = 100 nF 108/158 - 0.7 Sample and hold mode, DAC_OUT pin connected DAC output buffer OFF - - Output leakage current DAC consumption from VDDA 1 Unit - Ileak IDDA(DAC) Max - DAC_OUT pin connected DAC output buffer OFF, CSH = 100 nF DAC output buffer ON Typ 1.4 DAC output buffer ON, CSH = 100 nF DAC_OUT pin not connected (internal connection only) Min DS13560 Rev 4 ms - 315 ₓ 670 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) µV µA STM32G0B1xB/xC/xE Electrical characteristics Table 64. DAC characteristics(1) (continued) Symbol Parameter Conditions DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ DAC output buffer OFF Min Typ Max No load, middle code (0x800) - 185 240 No load, worst code (0xF1C) - 340 400 No load, middle code (0x800) - 155 205 Unit µA Sample and hold mode, buffer ON, CSH = 100 nF, worst case - 185 ₓ 400 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) Sample and hold mode, buffer OFF, CSH = 100 nF, worst case - 155 ₓ 205 ₓ Ton/(Ton+ Ton/(Ton+ Toff)(4) Toff)(4) 1. Guaranteed by design. 2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). 3. Refer to Table 55: I/O static characteristics. 4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details. Figure 30. 12-bit buffered / non-buffered DAC Buffered / non-buffered DAC Buffer(1) RLOAD 12-bit digital-to-analog converter DAC_OUTx CLOAD MSv47959V1 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DS13560 Rev 4 109/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 65. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain TUE TUECal SNR THD 110/158 Offset error at code 0x800(3) Offset error at code 0x001(4) Conditions Min Typ Max DAC output buffer ON - - ±2 DAC output buffer OFF - - ±2 guaranteed DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±4 VREF+ = 3.6 V - - ±12 VREF+ = 1.8 V - - ±25 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±8 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±5 VREF+ = 3.6 V - - ±5 VREF+ = 1.8 V - - ±7 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±0.5 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±30 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±12 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±23 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ 1 kHz, BW 500 kHz - 71.2 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz BW 500 kHz - 71.6 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -78 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - -79 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ Offset Error at DAC output buffer ON code 0x800 CL ≤ 50 pF, RL ≥ 5 kΩ after calibration (5) Gain error Total unadjusted error Total unadjusted error after calibration Signal-to-noise ratio Total harmonic distortion Unit LSB DS13560 Rev 4 % LSB LSB dB dB STM32G0B1xB/xC/xE Electrical characteristics Table 65. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2. Difference between two consecutive codes - 1 LSB. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON. 5.3.19 Voltage reference buffer characteristics Table 66. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Degraded mode(2) Iload = 100 µA Voltage reference output T = 30 °C Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 VRS = 0 2.038 2.042 2.046 VRS = 1 2.497 2.5 2.503 VRS = 0 VDDA-150 mV - VDDA VRS = 1 VDDA-150 mV - VDDA Unit V Trim step resolution - - - ±0.05 ±0.1 % CL Load capacitor - - 0.5 1 1.5 µF esr Equivalent Serial Resistor of Cload - - - - 2 Ω Iload Static load current - - - - 4 mA Iload = 500 µA - 200 1000 Iload = 4 mA - 100 500 - 50 500 TRIM Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode DS13560 Rev 4 ppm/V ppm/mA 111/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 66. VREFBUF characteristics(1) (continued) Symbol Parameter Temperature TCoeff_vrefbuf coefficient of VREFBUF(3) PSRR tSTART Power supply rejection Start-up time Conditions Min Typ Max Unit - - 50 ppm/ °C DC 40 60 - 100 kHz 25 40 - CL = 0.5 µF(4) - 300 350 (4) - 500 650 µF(4) - 650 800 - 8 - Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 -40 °C < TJ < +125 °C CL = 1.1 µF CL = 1.5 IINRUSH IDDA(VREFB UF) Control of maximum DC current drive on VREFBUF_OUT during start-up phase (5) VREFBUF consumption from VDDA - dB µs mA µA 1. Guaranteed by design. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf. 4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise. 5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1. 5.3.20 Comparator characteristics Table 67. COMP characteristics(1) Symbol Conditions Min Typ Max Unit Analog supply voltage - 1.62 - 3.6 V VIN Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA IDDA(SCALER) Parameter Scaler static consumption from VDDA tSTART_SCALER Scaler startup time 112/158 VREFINT V - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs - DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 67. COMP characteristics(1) (continued) Symbol Parameter Comparator startup time to reach propagation delay specification tSTART tD Propagation delay Comparator offset error Voffset Comparator hysteresis Vhys IDDA(COMP) Comparator consumption from VDDA Conditions Min Typ Max - - 5 High-speed mode Unit µs Medium-speed mode - - 15 200 mV step; 100 mV overdrive High-speed mode - 30 50 ns Medium-speed mode - 0.3 0.6 µs >200 mV step; 100 mV overdrive High-speed mode - - 70 ns Medium-speed mode - - 1.2 µs Full common mode range - ±5 ±20 mV No hysteresis - 0 - Low hysteresis - 10 - Medium hysteresis - 20 - High hysteresis - 30 - Medium-speed mode; No deglitcher Static - 5 7.5 With 50 kHz and ±100 mV overdrive square signal - 6 - Medium-speed mode; With deglitcher Static - 7 10 With 50 kHz and ±100 mV overdrive square signal - 8 - Static - 250 400 With 50 kHz and ±100 mV overdrive square signal - 250 - High-speed mode mV µA 1. Guaranteed by design. 2. Refer to Table 27: Embedded internal voltage reference. 5.3.21 Temperature sensor characteristics Table 68. TS characteristics Symbol Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.785 V tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs Start-up time when entering in continuous mode(4) - 70 120 µs TL(1) Avg_Slope(2) V30 tSTART(1) Parameter VTS linearity with temperature Average slope Voltage at 30°C (±5 °C)(3) DS13560 Rev 4 113/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 68. TS characteristics (continued) Symbol Parameter Min Typ Max Unit tS_temp(1) ADC sampling time when reading the temperature 5 - - µs IDD(TS)(1) Temperature sensor consumption from VDD, when selected by ADC - 4.7 7 µA 1. Guaranteed by design. 2. Based on characterization results, not tested in production. 3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. 4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 5.3.22 VBAT monitoring characteristics Table 69. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading the VBAT 12 - - µs Er(1) (1) tS_vbat 1. Guaranteed by design. Table 70. VBAT charging characteristics Symbol RBC 5.3.23 Parameter Battery charging resistor Conditions Min Typ Max VBRS = 0 - 5 - VBRS = 1 - 1.5 - Unit kΩ Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 71. TIMx(1) characteristics Symbol Parameter tres(TIM) Timer resolution time fEXT ResTIM 114/158 Conditions Min Max Unit - 1 - tTIMxCLK 15.625 - ns 0 fTIMxCLK/2 0 40 TIMx (except TIM2) - 16 TIM2 - 32 fTIMxCLK = 64 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 64 MHz Timer resolution DS13560 Rev 4 MHz bit STM32G0B1xB/xC/xE Electrical characteristics Table 71. TIMx(1) characteristics (continued) Symbol Parameter tCOUNTER 16-bit counter clock period Maximum possible count with 32-bit counter tMAX_COUNT Conditions Min Max Unit - 1 65536 tTIMxCLK 0.015625 1024 µs - 65536 × 65536 tTIMxCLK - 67.10 s fTIMxCLK = 64 MHz fTIMxCLK = 64 MHz 1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17. Table 72. IWDG min/max timeout period at 32 kHz LSI clock(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms 1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an uncertainty of one RC period. 5.3.24 Characteristics of communication interfaces I2C-bus interface characteristics The I2C-bus interface meets timing requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table. DS13560 Rev 4 115/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 73. Minimum I2CCLK frequency Symbol Parameter Condition Typ Standard-mode 2 Analog filter enabled fI2CCLK(min) Fast-mode Minimum I2CCLK frequency for correct operation of I2C peripheral DNF = 0 Analog filter disabled DNF = 1 Analog filter enabled Fast-mode Plus DNF = 0 Analog filter disabled DNF = 1 Unit 9 9 MHz 18 16 The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its characteristics: Table 74. I2C analog filter characteristics(1) Symbol Parameter Limiting duration of spikes suppressed by the filter(2) tAF Min Max Unit 50 260 ns 1. Based on characterization results, not tested in production. 2. Spikes shorter than the limiting duration are suppressed. SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 75 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 24: General operating conditions. The additional general conditions are: • OSPEEDRy[1:0] set to 11 (output speed) • capacitive load C = 30 pF • measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). 116/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Table 75. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency tsu(NSS) NSS setup time th(NSS) NSS hold time Conditions Min Typ Max Master mode 1.65 < VDD < 3.6 V Range 1 32 Master transmitter 1.65 < VDD < 3.6 V Range 1 32 Slave receiver 1.65 < VDD < 3.6 V Range 1 32 - - Unit MHz Slave transmitter/full duplex 2.7 < VDD < 3.6 V Range 1 32 Slave transmitter/full duplex 1.65 < VDD < 3.6 V Range 1 23 1.65 < VDD < 3.6 V Range 2 8 Slave mode, SPI prescaler = 2 4 ₓ TPCLK - - ns Slave mode, SPI prescaler = 2 2 ₓ TPCLK - - ns tw(SCKH) SCK high time Master mode TPCLK - 1.5 TPCLK TPCLK + 1.5 ns tw(SCKL) SCK low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1.5 ns tsu(MI) Master data input setup time - 1 - - ns tsu(SI) Slave data input setup time - 1 - - ns th(MI) Master data input hold time - 5 - - ns th(SI) Slave data input hold time - 1 - - ns ta(SO) Data output access time Slave mode 9 - 34 ns tdis(SO) Data output disable time Slave mode 9 - 16 ns 2.7 < VDD < 3.6 V Range 1 - 9 14 1.65 < VDD < 3.6 V Range 1 - 9 21 1.65 < VDD < 3.6 V Voltage Range 2 - 11 24 - 3 5 tv(SO) tv(MO) Slave data output valid time Master data output valid time - DS13560 Rev 4 ns ns 117/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 75. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit th(SO) Slave data output hold time - 5 - - ns th(MO) Master data output hold time - 1 - - ns 1. Based on characterization results, not tested in production. Figure 31. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) th(SO) First bit OUT tf(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 Figure 32. SPI timing diagram - slave mode and CPHA = 1 NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) First bit OUT tsu(SI) MOSI input th(SO) Next bits OUT tr(SCK) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 118/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Figure 33. SPI timing diagram - master mode High NSS input SCK Output SCK Output tc(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT BIT1 OUT MSB OUT LSB OUT th(MO) tv(MO) ai14136c 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. Table 76. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output fMCK= 256 x Fs; (Fs = audio sampling frequency) Fsmin = 8 kHz; Fsmax = 192 kHz; 2.048 49.152 MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs DCK I2S clock frequency duty cycle 30 70 Slave receiver DS13560 Rev 4 MHz % 119/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 76. I2S characteristics(1) (continued) Symbol Parameter tv(WS) WS valid time th(WS) Min Max Master mode - 8 WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 4 - th(WS) WS hold time Slave mode 2 - Master receiver 4 - Slave receiver 5 - Master receiver 4.5 - Slave receiver 2 - tsu(SD_MR) Conditions Data input setup time tsu(SD_SR) th(SD_MR) Data input hold time th(SD_SR) after enable edge; 2.7 < VDD < 3.6V Unit ns 16 tv(SD_ST) Data output valid time slave transmitter tv(SD_MT) Data output valid time master transmitter after enable edge - 5.5 th(SD_ST) Data output hold time slave transmitter after enable edge 8 - th(SD_MT) Data output hold time master transmitter after enable edge 1 - - after enable edge; 1.65 < VDD < 3.6V 23 1. Based on characterization results, not tested in production. Figure 34. I2S slave timing diagram (Philips protocol) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit tsu(SD_SR) SDreceive LSB receive(2) th(SD_ST) Bitn transmit th(SD_SR) MSB receive Bitn receive LSB receive MSv39721V1 1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 120/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Figure 35. I2S master timing diagram (Philips protocol) 90% 10% tr(CK) tf(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) Bitn transmit LSB transmit th(SD_MR) tsu(SD_MR) SDreceive th(SD_MT) MSB receive Bitn receive LSB receive MSv39720V1 1. Based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USART characteristics Unless otherwise specified, the parameters given in Table 77 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 24: General operating conditions. The additional general conditions are: • OSPEEDRy[1:0] set to 10 (output speed) • capacitive load C = 30 pF • measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART). Table 77. USART characteristics Symbol fCK Parameter USART clock frequency Conditions Min Typ Max Master mode - - 8 Slave mode - - 21 DS13560 Rev 4 Unit MHz 121/158 123 Electrical characteristics STM32G0B1xB/xC/xE Table 77. USART characteristics Symbol Parameter Conditions Min Typ Max Unit tsu(NSS) NSS setup time Slave mode tker + 2 - - th(NSS) NSS hold time Slave mode 2 - - tw(CKH) CK high time tw(CKL) CK low time Master mode 1 / fCK / 2 -1 1 / fCK / 2 1 / fCK / 2 +1 tsu(RX) Data input setup time Master mode tker + 2 - - Slave mode 4 - - Master mode 1 - - Slave mode 0.5 - - Master mode - 0.5 1 Slave mode - 10 19 Master mode 0 - - Slave mode 7 - - th(RX) Data input hold time tv(TX) Data output valid time th(TX) Data output hold time ns USB full speed (FS) characteristics The STM32G0B1xB/xC/xE USB interface is fully compliant with the USB specification version 2.0 and Battery charging rev 1.2 (primary and secondary detection). Table 78. USB FS electrical characteristics(1) Symbol Parameter Conditions Min(2) Typ Max(2) Unit - 3.0(3) - 3.6 V 14.25 - 24.8 kΩ 0.9 1.25 1.575 kΩ 1.425 2.25 3.09 kΩ 1.3 - 2.0 V 28 36 44 Ω VDDIO2 USB full speed transceiver operating voltage RPD Pull down resistor on PA11, PA12 (USB_FS_DP/DM) VIN = VDD Pull Up Resistor on PA12 (USB_FS_DP) VIN = VSS, during idle Pull Up Resistor on PA12 (USB_FS_DP) VIN = VSS during reception RPU VCRS Output signal crossover voltage ZDRV Output driver impedance(4) Driving high or low 1. Guaranteed by design. 2. All the voltages are measured from the local ground potential. 3. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. No external termination series resistors are required on DP (D+) and DM (D-) pins as the matching impedance is included in the embedded driver.. 122/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Electrical characteristics Figure 36. USB timings – definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b UCPD characteristics UCPD1 and UCPD2 controllers comply with USB Type-C Rev.2 and USB Power Delivery Rev. 3.0 specifications. Table 79. UCPD operating conditions Symbol VDD Parameter UCPD operating supply voltage Vswing Output voltage swing ZDRV Output driver impedance Conditions Sink mode only Sink and source mode Driving high or low Min Typ Max 3.0 3.3 3.6 3.135 3.3 3.465 1.05 - 1.2 33 - 75 Unit V Ω CAN (controller area network) interface Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX). DS13560 Rev 4 123/158 123 Package information 6 STM32G0B1xB/xC/xE Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 UFQFPN32 package information UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package. Figure 37. UFQFPN32 package outline D A A1 A3 e ddd C C SEATINGPLANE D1 b e E2 b E1 E 1 L 32 D2 L PIN 1 Identifier A0B8_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. Table 80. UFQFPN32 package mechanical data inches(1) millimeters Symbol 124/158 Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.000 0.0007 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 (2) D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Table 80. UFQFPN32 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 3.400 3.500 3.600 0.1339 0.1378 0.1417 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm. Figure 38. Recommended footprint for UFQFPN32 package 5.30 3.80 25 32 1 0.60 24 3.45 3.80 5.30 3.45 0.50 0.30 8 17 16 9 3.80 0.75 A0B8_FP_V2 1. Dimensions are expressed in millimeters DS13560 Rev 4 125/158 153 Package information STM32G0B1xB/xC/xE Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 39. UFQFPN32 package marking example Product identification (1) 32G0B1KCU6 Date code Y WW R Revision code Pin 1 identifier 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 126/158 DS13560 Rev 4 STM32G0B1xB/xC/xE LQFP32 package information LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 40. LQFP32 package outline c A2 A1 A SEATING PLANE C 0.25 mm ccc GAUGE PLANE C K D A1 L D1 L1 D3 24 17 25 16 32 9 PIN 1 IDENTIFICATION 1 E E1 E3 b 6.2 Package information 8 e 5V_ME_V2 1. Drawing is not to scale. Table 81. LQFP32 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 DS13560 Rev 4 127/158 153 Package information STM32G0B1xB/xC/xE Table 81. LQFP32 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41. Recommended footprint for LQFP32 package 0.80 1.20 24 17 25 16 0.50 0.30 7.30 6.10 9.70 7.30 32 9 8 1 1.20 6.10 9.70 1. Dimensions are expressed in millimeters. 128/158 DS13560 Rev 4 5V_FP_V2 STM32G0B1xB/xC/xE Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. LQFP32 package marking example STM32G Product identification (1) 0B1KET6 Date code Y WW Revision code Pin 1 identifier R 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13560 Rev 4 129/158 153 Package information 6.3 STM32G0B1xB/xC/xE UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package Figure 43. UFQFPN48 package outline Pin 1 identifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner R 0.125 typ. Detail Z E2 1 48 Z A0B9_ME_V3 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. Table 82. UFQFPN48 package mechanical data inches(1) millimeters Symbol 130/158 Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Table 82. UFQFPN48 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. Recommended footprint for UFQFPN48 package 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 24 0.50 0.55 5.80 0.75 A0B9_FP_V2 1. Dimensions are expressed in millimeters. DS13560 Rev 4 131/158 153 Package information STM32G0B1xB/xC/xE Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 45. UFQFPN48 package marking example STM32G0B1 Product identification (1) CEU6 Date code Y WW Will be provided later Revision code Pin 1 identifier R 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 132/158 DS13560 Rev 4 STM32G0B1xB/xC/xE LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 46. LQFP48 package outline SEATING PLANE C c A1 A A2 0.25 mm GAUGE PLANE ccc C K D A1 L D1 L1 D3 36 25 37 24 48 E E1 b E3 6.4 Package information 13 PIN 1 IDENTIFICATION 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 83. LQFP48 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - DS13560 Rev 4 133/158 153 Package information STM32G0B1xB/xC/xE Table 83. LQFP48 mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 47. Recommended footprint for LQFP48 package 0.50 1.20 9.70 0.30 25 36 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are expressed in millimeters. 134/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 48. LQFP48 package marking example STM32G0B1 Product identification (1) CET6 Date code Y WW Will be provided later Revision code Pin 1 identifier R 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13560 Rev 4 135/158 153 Package information 6.5 STM32G0B1xB/xC/xE WLCSP52 package information WLCSP52 is a 52-ball, 3.09 x 3.15 mm, 0.4 mm pitch, wafer-level chip-scale package. Figure 49. WLCSP52 - Outline bbb Z A1 BALL ORIENTATION A1 G 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C E e2 D E F G H DETAIL B e1 F A A2 D aaa (4x) TOP VIEW BOTTOM VIEW SIDE VIEW BUMP DETAIL A A2 eee Z Z b(52x) ccc ddd ZXY Z SEATING PLANE FRONT VIEW DETAIL B DETAIL A B0BG_WLCSP52_ME_V1 1. Drawing is not to scale. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. Table 84. WLCSP52 - Mechanical data inches(1) millimeters Symbol 136/158 Min Typ Max Min Typ Max A(2) - - 0.58 - - 0.023 A1 - 0.17 - - 0.007 - A2 - 0.38 - - 0.015 - A3(3) - 0.025 - - 0.001 - DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Table 84. WLCSP52 - Mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.23 0.26 0.28 0.009 0.010 0.011 D 3.06 3.09 3.12 0.120 0.122 0.123 E 3.12 3.15 3.18 0.123 0.124 0.125 e - 0.40 - - 0.016 - e1 - 2.40 - - 0.094 - e2 - 2.42 - - 0.095 - (4) - 0.35 - - 0.014 - G(4) - 0.36 - - 0.014 - N - - 0.10 - - 0.004 aaa - - 0.10 - - 0.004 bbb - - 0.10 - - 0.004 ccc - - 0.05 - - 0.002 ddd - - 0.05 - - 0.002 eee - - 0.58 - - 0.023 F 1. Values in inches are converted from mm and rounded to 3 decimal digits. 2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2. 3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability. 4. Calculated dimensions are rounded to the 3rd decimal place Figure 50. WLCSP52 - Recommended footprint Dpad Dsm BGA_WLCSP_FT_V1 DS13560 Rev 4 137/158 153 Package information STM32G0B1xB/xC/xE Table 85. WLCSP52 - Recommended PCB design rules Dimension Recommended values Pitch 0.4 mm Dpad 0,225 mm Dsm 0.290 mm typ. (depends on soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks that identify the parts throughout supply chain operations, are not indicated below. Figure 51. WLCSP52 package marking example Pin 1 identifier Product identification (1) G0B1E6 Date code Y WW R Revision code 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 138/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 6.6 Package information UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-low-profile fine-pitch ball grid array package. Figure 52. UFBGA64 package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e X A1 ball A1 ball identifier index area F E A F D1 D e Y H 8 1 Øb (64 balls) Ø eee M Z Y X Ø fff M Z BOTTOM VIEW TOP VIEW A019_ME_V1 1. Drawing is not to scale. Table 86. UFBGA64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DS13560 Rev 4 139/158 153 Package information STM32G0B1xB/xC/xE Table 86. UFBGA64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 53. Recommended footprint for UFBGA64 package Dpad Dsm BGA_WLCSP_FT_V1 Table 87. Recommended PCB design rules for UFBGA64 package Dimension 140/158 Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 54. UFBGA64 package marking example Product identification (1) G0B1RE6N Date code Revision code Will be provided later Y WW R Pin 1 identifier 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13560 Rev 4 141/158 153 Package information 6.7 STM32G0B1xB/xC/xE LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 55. LQFP64 package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 E E1 E3 b 17 PIN 1 IDENTIFICATION 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 88. LQFP64 package mechanical data inches(1) millimeters Symbol 142/158 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Table 88. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 56. Recommended footprint for LQFP64 package 33 48 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are expressed in millimeters. DS13560 Rev 4 143/158 153 Package information STM32G0B1xB/xC/xE Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 57. LQFP64 package marking example STM32G0B1 Product identification (1) RET6 Date code Will be provided later Y WW Revision code Pin 1 identifier R 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 144/158 DS13560 Rev 4 STM32G0B1xB/xC/xE LQFP80 package information This LQFP is an 80 pin, 12 x 12 mm low-profile quad flat package. Figure 58. LQFP80 package outline 2 1 (2) R1 TI O N BB R2 H D 1/4 S (6) B L 3 (L1) (1) (11) E 1/4 SECTION A-A 4x N/4 TIPS aaa C A-B D bbb H A-B D 4x (N – 4)x e (13) C A 0.05 GAUGE PLANE 0.25 B SE C 6.8 Package information A2 A1(12) b C A-B D (10) (9) (11) ccc C D (3) (11) N (11) c (4) 1 2 3 c1 E 1/4 b1 (3) B (6) D 1/4 WITH PLATING b (4) D D1 (2) (5) (3) A ddd BASE METAL SECTION B-B E1 (2) (5) A (11) E A (Section A-A) 1. Drawing is not to scale. Table 89. LQFP80 package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 14.000 - - 0.5512 - D1 - 12.000 - - 0.4724 - DS13560 Rev 4 145/158 153 Package information STM32G0B1xB/xC/xE Table 89. LQFP80 package mechanical data (continued) inches(1) mm Dim. Min Typ Max Min Typ Max D2 - 9.500 - - 0.3740 - E - 14.000 - - 0.5512 - E1 - 12.000 - - 0.4724 - E3 - 9.500 - - 0.3740 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 θ 0.0° - 7.0° 0.0° - 7.0° 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 59. LQFP80 - Recommended footprint 1.25 0.3 12.30 14.70 0.5 1.2 9.80 14.70 1. Dimensions are expressed in millimeters. 146/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 60. LQFP80 package marking example STM32G0B1 MET6 Will be provided later R Y WW Product identification (1) Revision code Date code Pin 1 identifier 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13560 Rev 4 147/158 153 Package information 6.9 STM32G0B1xB/xC/xE UFBGA100 package information UFBGA100 is a 100-ball, 7 x 7 mm, 0.5 mm pitch ultra-fine-profile ball grid array package. Figure 61. UFBGA100 package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 A1 ball identifier Z e A1 ball index area X E A Z D1 D e Y M 12 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW A0C2_ME_V5 1. Drawing is not to scale. Table 90. UFBGA100 package mechanical data inches(1) millimeters Symbol 148/158 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.450 - - 0.0177 - A3 - 0.130 - - 0.0051 0.0094 A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 6.850 7.000 7.150 0.2697 0.2756 0.2815 D1 - 5.500 - - 0.2165 - E 6.850 7.000 7.150 0.2697 0.2756 0.2815 E1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Table 90. UFBGA100 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 62. Recommended footprint for UFBGA100 package Dpad Dsm A0C2_FP_V1 Table 91. UFBGA100 recommended PCB design rules Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DS13560 Rev 4 149/158 153 Package information STM32G0B1xB/xC/xE Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 63. UFBGA100 package marking example STM32G Product identification (1) 0B1VEI6 Date code Revision code Will be provided later Y WW R Pin 1 identifier 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 150/158 DS13560 Rev 4 STM32G0B1xB/xC/xE LQFP100 package information LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package. Figure 64. LQFP100 package outline 0.25 mm c A1 A SEATING PLANE C A2 GAUGE PLANE D A1 K ccc C L D1 L1 D3 51 75 76 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 6.10 Package information 25 e 1L_ME_V5 1. Drawing is not to scale. Table 92. LQFP100 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DS13560 Rev 4 151/158 153 Package information STM32G0B1xB/xC/xE Table 92. LQFP100 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 65. Recommended footprint for LQFP100 package 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 1. Dimensions are expressed in millimeters. 152/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 66. LQFP100 package marking example STM32G0B1 VET6 Will be provided later R Y WW Product identification (1) Revision code Date code Pin 1 identifier 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13560 Rev 4 153/158 153 STM32G0B1xB/xC/xE 6.11 Thermal characteristics The operating junction temperature TJ must never exceed the maximum given in Table 24: General operating conditions. The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is: TJ(max) = TA(max) + PD(max) x ΘJA where: • TA(max) is the maximum operating ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD = PINT + PI/O, – PINT is power dissipation contribution from product of IDD and VDD – PI/O is power dissipation contribution from output ports where: PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 93. Package thermal characteristics Value Symbol Θ 6.11.1 Parameter Thermal resistance Package Junctionto-ambient Junctionto-board Junctionto-case LQFP100 14 × 14 mm 47 23 9 UFBGA100 7 × 7 mm 48 30 12 LQFP80 12 x 12 mm 51 24 10 LQFP64 10 × 10 mm 53 25 11 UFBGA64 5 × 5 mm 51 32 32 WLCSP52 3.09 × 3.15 mm 55 23 3 LQFP48 7 × 7 mm 59 27 13 UFQFPN48 7 × 7 mm 28 12 9 LQFP32 7 × 7 mm 59 27 13 UFQFPN32 5 × 5 mm 35 20 14 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (still air). Available from www.jedec.org. 6.11.2 Selecting the product temperature range The temperature range is specified in the ordering information scheme shown in Section 7: Ordering information. 154/158 DS13560 Rev 4 STM32G0B1xB/xC/xE Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature. As applications do not commonly use microcontrollers at their maximum power consumption, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range best suits the application. The following example shows how to calculate the temperature range needed for a given application. Example: Assuming the following worst application conditions: • ambient temperature TA = 50 °C (measured according to JESD51-2) • IDD = 50 mA; VDD = 3.6 V • 20 I/Os simultaneously used as output at low level with IOL = 8 mA (VOL= 0.4 V), and • 8 I/Os simultaneously used as output at low level with IOL = 20 mA (VOL= 1.3 V), the power consumption from power supply PINT is: PINT = 50 mA × 3.6 V= 118 mW, the power loss through I/Os PIO is PIO = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW, and the total power PD to dissipate is: PD = 180 mW + 272 mW = 452 mW For a package with ΘJA= 65 °C/W, the junction temperature stabilizes at: TJ = 50°C + (65 °C/W × 452 mW) = 50 °C + 29.4 °C = 79.4 °C As a conclusion, product version with suffix 6 (maximum allowed TJ = 105° C) is sufficient for this application. If the same application was used in a hot environment with maximum TA greater than 75.5 °C, the junction temperature would exceed 105°C and the product version allowing higher maximum TJ would have to be ordered. DS13560 Rev 4 155/158 155 Ordering information 7 STM32G0B1xB/xC/xE Ordering information Example STM32 G 0B1 R E T 6 xyy Device family STM32 = Arm® based 32-bit microcontroller Product type G = general-purpose Device subfamily 0B1 = STM32G0B1 Pin count K = 32 C = 48 N = 52 M = 80 R = 64 V = 100 Flash memory size B = 128 Kbytes C = 256 Kbytes E = 512 Kbytes Package type I = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = -40 to 85°C (105°C junction) 7 = -40 to 105°C (125°C junction) 3 = -40 to 125°C (130°C junction) Options xTR = tape and reel packing; x = N (“N” product version), otherwise blank x˽˽ = tray packing; x = N (“N” product version) or blank other = 3-character ID incl. custom Flash code and packing information; x = N for “N” product version For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. 156/158 DS13560 Rev 4 STM32G0B1xB/xC/xE 8 Revision history Revision history Table 94. Document revision history Date Revision 13-Nov-2020 1 Initial release. 2 Table 1: Device summary table reordered; Updated last paragraph in Section 2: Description; Updated Table 12: Pin assignment and description; Updated Table 66: VREFBUF characteristics; Missing package marking examples added in Section 6: Package information and Figure 42: LQFP32 package marking example corrected; Section 6.5: WLCSP52 package information updated; Updated example in Section 6.11.2: Selecting the product temperature range; Section 6.11: Thermal characteristics - improved UFBGA100, UFBGA64, and LQFP80 ΘJAvalues as a result of characterization; Updated Section 6.8: LQFP80 package information. 3 Updated Figure 3 to Figure 6 and Figure 9 to Figure 12: marking of VDDIO2-only supplied pins corrected. I/O type “_s” added to Table 11: Terms and symbols used in Table 12 and Table 12: Pin assignment and description. 4 Added HSI48 in features on the cover page and in Figure 1: Block diagram; Updated Table 2: Features and peripheral counts; Updated Table 12: Pin assignment and description (UFBGA80 corrected to LQFP80) in the header; Updated Section : USB full speed (FS) characteristics; Section UCPD characteristics made a sub-section of Section 5.3.24: Characteristics of communication interfaces; Updated Figure 58: LQFP80 package outline. 30-Nov-2021 18-Jan-2022 12-Dec-2022 Changes DS13560 Rev 4 157/158 157 STM32G0B1xB/xC/xE IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved 158/158 DS13560 Rev 4