STM32G483xE
Arm® Cortex®-M4 32-bit MCU+FPU, up to 512 KB Flash, 170 MHz /
213 DMIPS, 128 KB SRAM, rich analog, math accelerator, AES
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 170 MHz
with 213 DMIPS, MPU, DSP instructions
• Operating conditions:
– VDD, VDDA voltage range:
1.71 V to 3.6 V
• Memories
– 512 Kbytes of Flash memory with ECC
support, two banks read-while-write,
proprietary code readout protection
(PCROP), securable memory area, 1 Kbyte
OTP
– 96 Kbytes of SRAM, with hardware parity
check implemented on the first 32 Kbytes
– Routine booster: 32 Kbytes of SRAM on
instruction and data bus, with hardware
parity check (CCM SRAM)
– External memory interface for static
memories FSMC supporting SRAM,
PSRAM, NOR and NAND memories
– Quad-SPI memory interface
• Reset and supply management
– Power-on/power-down reset
(POR/PDR/BOR)
– Programmable voltage detector (PVD)
– Low-power modes: sleep, stop, standby
and shutdown
– VBAT supply for RTC and backup registers
This is information on a product in full production.
UFQFPN48
(7 x 7 mm)
WLCSP81
(4.02 x 4.27 mm)
LQFP80 (12 x 12 mm)
LQFP100 (14 x 14 mm)
LQFP128 (14 x 14 mm)
UFBGA121
(6 x 6 mm)
TFBGA100
(8 x 8 mm)
• Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz oscillator with calibration
– Internal 16 MHz RC with PLL option (± 1%)
– Internal 32 kHz RC oscillator (± 5%)
• Mathematical hardware accelerators
– CORDIC for trigonometric functions
acceleration
– FMAC: filter mathematical accelerator
November 2021
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
• Up to 107 fast I/Os
– All mappable on external interrupt vectors
– Several I/Os with 5 V tolerant capability
• Interconnect matrix
• 16-channel DMA controller
• 5 x 12-bit ADCs 0.25 µs, up to 42 channels.
Resolution up to 16-bit with hardware
oversampling, 0 to 3.6 V conversion range
• 7 x 12-bit DAC channels
– 3 x buffered external channels 1 MSPS
– 4 x unbuffered internal channels 15 MSPS
• 7 x ultra-fast rail-to-rail analog comparators
• 6 x operational amplifiers that can be used in
PGA mode, all terminals accessible
• Internal voltage reference buffer (VREFBUF)
supporting three output voltages (2.048 V,
2.5 V, 2.9 V)
• 17 timers:
– 2 x 32-bit timer and 2 x 16-bit timers with
up to four IC/OC/PWM or pulse counter
and quadrature (incremental) encoder input
– 3 x 16-bit 8-channel advanced motor
control timers, with up to 8 x PWM
DS12997 Rev 4
1/230
www.st.com
STM32G483xE
–
–
–
–
–
–
channels, dead time generation and
emergency stop
1 x 16-bit timer with 2 x IC/OCs, one
OCN/PWM, dead time generation and
emergency stop
2 x 16-bit timers with IC/OC/OCN/PWM,
dead time generation and emergency stop
2 x watchdog timers (independent, window)
1 x SysTick timer: 24-bit downcounter
2 x 16-bit basic timers
1 x low-power timer
• Calendar RTC with alarm, periodic wakeup
from stop/standby
• Communication interfaces
– 3 x FDCAN controller supporting flexible
data rate
– 4 x I2C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from stop
– 5 x USART/UARTs (ISO 7816 interface,
LIN, IrDA, modem control)
– 1 x LPUART
– 4 x SPIs, 4 to 16 programmable bit frames,
2 x with multiplexed half duplex I2S
interface
– 1 x SAI (serial audio interface)
– USB 2.0 full-speed interface with LPM and
BCD support
– IRTIM (infrared interface)
– USB Type-C™ /USB power delivery
controller (UCPD)
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
• AES: 128/256-bit key encryption hardware
accelerator
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
Table 1. Device summary
Reference
Part number
STM32G483xE
STM32G483CE, STM32G483RE, STM32G483ME,
STM32G483PE, STM32G483VE, STM32G483QE
2/230
DS12997 Rev 4
STM32G483xE
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17
3.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.11
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.6
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16
DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18
3.17.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 29
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DS12997 Rev 4
3/230
6
Contents
4/230
STM32G483xE
3.18.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18.4
Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 31
3.19
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.20
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.24
Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 33
3.25
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.25.1
Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 35
3.25.2
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25.4
Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25.5
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25.6
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.26
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 38
3.27
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.29
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.30
Universal synchronous/asynchronous receiver transmitter (USART) . . . 41
3.31
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 42
3.32
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.33
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.34
Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 44
3.35
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.36
USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 44
3.37
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.38
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 45
3.39
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.40
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.40.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.40.2
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DS12997 Rev 4
STM32G483xE
4
5
Contents
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1
UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2
LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4
LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5
LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6
LQFP128 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.7
WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.8
TFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.9
UFBGA121 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.10
Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.11
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 83
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 83
5.3.4
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DS12997 Rev 4
5/230
6
Contents
6
STM32G483xE
5.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3.16
Extended interrupt and event controller input (EXTI) characteristics . . 132
5.3.17
Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.18
Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 133
5.3.19
Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 148
5.3.20
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 155
5.3.21
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.22
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.3.23
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.24
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.25
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.26
Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 165
5.3.27
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.3.28
QUADSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.3.29
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.1
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.2
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.4
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.5
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.6
TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
6.7
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.8
LQFP128 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.9
UFBGA121 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.10
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.10.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.10.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 225
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6/230
DS12997 Rev 4
STM32G483xE
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32G483xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32G483xE peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SAI features implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM32G483xE pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 87
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . . 89
Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 93
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical current consumption in Run and Low-power run modes, with different codes
running from CCMSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 98
Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 99
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DS12997 Rev 4
7/230
9
List of tables
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
8/230
STM32G483xE
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 144
ADC accuracy (Multiple ADCs operation) - limited test conditions 2 . . . . . . . . . . . . . . . . 145
ADC accuracy (Multiple ADCs operation) - limited test conditions 3 . . . . . . . . . . . . . . . . 146
DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 177
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 177
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 178
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 179
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 180
DS12997 Rev 4
STM32G483xE
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
List of tables
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 180
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
WLCSP81 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
WLCSP81 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LQFP80 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
TFBGA100 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LQPF100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
LQFP128 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
UFBGA121 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
UFBGA121 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DS12997 Rev 4
9/230
9
List of figures
STM32G483xE
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
10/230
STM32G483xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32G483xE UFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32G483xE LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32G483xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32G483xE LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32G483xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32G483xE LQFP128 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32G483xE WLCSP81 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32G483xE TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32G483xE UFBGA121 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 176
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 178
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 179
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 181
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
DS12997 Rev 4
STM32G483xE
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
List of figures
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 190
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 191
Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
WLCSP81 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
WLCSP81 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
WLCSP81 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
UFQFPN48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
LQFP48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LQFP48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LQFP80 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
LQFP80 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
TFBGA100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
TFBGA100 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
LQFP128 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LQFP128 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
LQFP128 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
UFBGA121 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
UFBGA121 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DS12997 Rev 4
11/230
11
Introduction
1
STM32G483xE
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32G483xE microcontrollers.
This document should be read in conjunction with the reference manual RM0440
“STM32G4 Series advanced Arm® 32-bit MCUs”. The reference manual is available from
the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical
reference manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12/230
DS12997 Rev 4
STM32G483xE
2
Description
Description
The STM32G483xE devices are based on the high-performance Arm® Cortex®-M4 32-bit
RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm single-precision data-processing instructions and all the data types. It also
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (up to 512 Kbytes of Flash memory, and
128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for
devices with packages of 100 pins and more), a Quad-SPI Flash memory interface, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
The devices also embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, securable memory area and proprietary code
readout protection.
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC for trigonometric functions and FMAC unit for filter functions).
They offer five fast 12-bit ADCs (4 Msps), seven comparators, six operational amplifiers,
seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a lowpower RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor
control, seven general-purpose 16-bit timers, and one 16-bit low-power timer.
They also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Four SPIs multiplexed with two half duplex I2Ss
- Three USARTs, two UARTs and one low-power UART.
- Three FDCANs
- One SAI
- USB device
- UCPD
The STM32G483xE devices embed an AES.
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported including an analog independent supply
input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC and
the registers.
The STM32G483xE family offers 8 packages from 48-pin to 128-pin.
DS12997 Rev 4
13/230
47
Description
STM32G483xE
STM32G483RE
STM32G483ME
STM32G483VE
STM32G483PE
STM32G483QE
Flash memory
STM32G483CE
Peripheral
Table 2. STM32G483xE features and peripheral counts
512
Kbytes
512
Kbytes
512
Kbytes
512
Kbytes
512
Kbytes
512
Kbytes
SRAM
128 (80 + 16+ 32) Kbytes
External memory controller
for static memories (FSMC)
No
QUADSPI
Timers
Advanced
motor control
3 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic
2 (16-bit)
Low power
1 (16-bit)
SysTick timer
1
Watchdog
timers
(independent,
window)
2
3 (2)
Yes
4 (2)
2
I C
4
USART
3
UART
0 in LQFP48
1 in UFQFPN48
2
LPUART
1
FDCANs
3
USB device
Yes
UCPD
Yes
SAI
Yes
RTC
Tamper pins
Yes
2
3
Random number generator
Yes
AES
Yes
14/230
Yes
1
SPI(I2S)(2)
Comm.
interfaces
Yes(1)
Yes
DS12997 Rev 4
STM32G483xE
Description
FMAC
Yes
GPIOs
Wakeup pins
12-bit ADCs
Number of channels
38 in LQFP48
42 in UFQFPN48
3
52
4
67 in WLCSP81
66 in LQFP80
4
20 in LQFP48
21 in UFQFPN48
26
42 in WLCSP81
41 in LQFP80
107
107
5
5
5
42
42
42
4
7 (3 external + 4 internal)
Internal voltage reference
buffer
Yes
Analog comparator
7
Operational amplifiers
6
Max. CPU frequency
170 MHz
Operating voltage
Packages
86
5
12-bit DAC
Number of channels
Operating temperature
STM32G483QE
Yes
STM32G483PE
CORDIC
STM32G483VE
STM32G483ME
STM32G483RE
STM32G483CE
Peripheral
Table 2. STM32G483xE features and peripheral counts (continued)
1.71 V to 3.6 V
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
LQFP48/
UFQFPN48
LQFP64
WLCSP81/
LQFP80
LQFP100/
LQFP128 LQFP128
TFBGA100
1. For the LQFP100 package, only FMC bank1 and NAND bank are available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 chip select.
2. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
DS12997 Rev 4
15/230
47
Description
STM32G483xE
Figure 1. STM32G483xE block diagram
Arm®
Cortex-M4
170MHz
QUADSPI
D-BUS
I-BUS
S-BUS
GP-DMA2
8 Chan
GP-DMA1
8 Chan
@VDDA
CCM SRAM 32 KB
CH1
DAC2
OUT1
SRAM1 80 KB
CH1
DAC3
RNG
CH2
CH1
DAC4
CH2
RNB1
analog
SAR ADC1
IF
POWER MNGT
CORDIC
SAR ADC3
VOLT. REG.
3.3V TO 1.2V
VDD12
FMAC
IF
AHB1
SAR ADC5
OUT1/OUT2
CH2
SRAM2 16 KB
@VDDA
SAR ADC4
CH1
DAC1
AHB2
SAR ADC2
CLK, NCS, BK1_IO[3:0]
TinyAES
FLASH 2 x 256 KB
DMAMUX
Ain ADC
CLK, E(3:0), A(23:0)
D(31:0), OEN, WEN,
BL(3:0), L, WAIT/IORDY,
IORD, IOWD,IS16 as AF
FSMC
MPU
NVIC
FPU
ACCEL/
CACHE
TRACECK
TRACED(3:0)
JTAG & SW
ETM
AHB BUS-MATRIX 5M / 9S
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
@VDD
SUPPLY
SUPERVISION
@VDD
PA(15:0)
USART
GPIO2MBps
PORT A
LSI
POR
PB(15:0)
USART
GPIO2MBps
PORT B
PLL
PC(15:0)
USART
GPIO2MBps
PORT C
Reset
Int
HSI
VDD = 1.71 to 3.6V
VSS
POR / BOR
VDD, VSS,
VDDA, VSSA,
RESET
PVD, PWM
HSI48
PD(15:0)
USART
GPIO2MBps
PORT D
PE(15:0)
USART
GPIO2MBps
PORT E
PF(15:0)
USART
GPIO2MBps
PORT F
PG(10:0)
USART
GPIO2MBps
PORT G
XTAL OSC
4-48MHz
IWDG
RESET&
CLOCKCTRL
OSC_IN
OSC_OUT
Standby Interface
VBAT = 1.55 to 3.6V
@VBAT
peripheralclocks
and system
EXT IT. WKUP
TIMER8
16b PWM
AHB/APB2 AHB/APB1
4 CH, ETR as AF
16b
TIMER3&4
4 CH, ETR as AF
CH as AF
TIMER16
USART
2MBps
TIMER17
USART
2MBps
4 PWM,4PWM,
ETR,BKIN as F
RX, TX, SCK,CTS,
RTS as AF
USART
USART
2MBps1
MOSI, MISO
SCK, NSS as AF
1
USART SPI
2MBps
PWRCTRL
16b
16b
TIMER20 16b PWM
SPI 4
LP_UART1
TIMER6
16b trigg
TIMER7
16b trigg
USART2&3
UART4&5
SPI2&3
CRS
CAN1 & 2 & 3
PHY
Smcard
irDA
irDA
I2S half
duplex
RX, TX, SCK,
CTS, RTS as AF
RX, TX, CTS,
RTS as AF
MOSI, MISO, SCK
NSS, as AF
RX,TX as AF
UCPD
OPAMP
1,2,3,4,5,6
FIFO
COMP
1,2,3,4,5,6,7
SCL, SDA, SMBAL as AF
I2C1&2&3&4
LP timer1
@VDDA
RX, TX as AF
WinWATCHDOG
SysCfg
Vref_Buf
RTC_OUT
RTC_TS
RTC_TAMPx
TIMER2&5
TIMER15
USART
2MBps
MOSI, MISO
SCK, NSS as AF
OSC32_IN
OSC_OUT
16b PWM
CH as AF
CH as AF16b
RTC Interface
FIFO
TIMER1
CRC
APB2
4 PWM,4PWM,
ETR,BKIN as F
4 PWM,4PWM,
ETR,BKIN as F
RTC AWU
BKPREG
SAI1
APB2 60MHzAPB1
107 AF
XTAL 32kHz
USB
Device
PHY
FS, SCK, SD,
MCLK as AF
D+
D-
CC1
CC2
MSv60856V1
1. AF: alternate function on I/O pins.
16/230
DS12997 Rev 4
STM32G483xE
Functional overview
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional codeefficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm core, the STM32G483xE family is compatible with all Arm tools and
software.
Figure 1 shows the general block diagram of the STM32G483xE devices.
3.2
Adaptive real-time memory accelerator (ART accelerator)
The ART accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 protected areas, which can be
divided in up into 8 subareas each. The protection area sizes range between 32 bytes and
the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS12997 Rev 4
17/230
47
Functional overview
3.4
STM32G483xE
Embedded Flash memory
The STM32G483xE devices feature up to 512 Kbytes of embedded Flash memory which is
available for storing programs and data.
The Flash interface features:
–
Single or dual bank operating modes
–
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank. The dual bank boot is also supported.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•
Write protection (WRP): the protected area is protected against erasing and
programming.
•
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
•
Securable memory area: a part of Flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main Flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error.
Purpose of the Securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The Flash memory embeds the error correction code (ECC) feature supporting:
18/230
•
Single error detection and correction
•
Double error detection
•
The address of the ECC fail can be read in the ECC register
•
1 Kbyte (128 double word) OTP (one-time programmable) for user data. The OTP area
is available in Bank 1 only. The OTP data cannot be erased and can be written only
once.
DS12997 Rev 4
STM32G483xE
3.5
Functional overview
Embedded SRAM
STM32G483xE devices feature 128 Kbytes of embedded SRAM. This SRAM is split into
three blocks:
80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus or through the I-Code/D-Code buses. The first
32 Kbytes of SRAM1 support hardware parity check.
•
16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System bus. SRAM2 can be retained in standby modes.
•
32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports
hardware parity check and can be write-protected with 1-Kbyte granularity.
•
The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, FSMC, QUADSPI, AHB and APB peripherals). It also ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 2. Multi-AHB bus matrix
DMA1
DMA2
S-bus
D-bus
Cortex®-M4
with FPU
I-bus
3.6
•
DCode
ACCEL
ICode
FLASH
512 KB
SRAM1
CCM
SRAM
SRAM2
AHB1
peripherals
AHB2
peripherals
FSMC
QUADSPI
BusMatrix-S
MSv42663V1
DS12997 Rev 4
19/230
47
Functional overview
3.7
STM32G483xE
Boot modes
At startup, a BOOT0 pin (or nBOOT0 option bit) and an nBOOT1 option bit are used to
select one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
3.8
CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
Cordic features
3.9
•
24-bit CORDIC rotation engine
•
Circular and Hyperbolic modes
•
Rotation and Vectoring modes
•
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
Programmable precision up to 20-bit
•
Fast convergence: 4 bits per clock cycle
•
Supports 16-bit and 32-bit fixed point input and output formats
•
Low latency AHB slave interface
•
Results can be read as soon as ready without polling or interrupt
•
DMA read and write channels
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
20/230
DS12997 Rev 4
STM32G483xE
Functional overview
FMAC features
3.10
•
16 x 16-bit multiplier
•
24+2-bit accumulator with addition and subtraction
•
16-bit input and output data
•
256 x 16-bit local memory
•
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
Input and output sample buffers can be circular
•
Buffer “watermark” feature reduces overhead in interrupt mode
•
Filter functions: FIR, IIR (direct form 1)
•
AHB slave interface
•
DMA read and write data channels
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.11
Power supply management
3.11.1
Power supply schemes
The STM32G483xE devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several
independent supplies, can be provided for specific peripherals:
•
VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
•
VDDA = 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage and should preferably be connected to VDD when
these peripherals are not used.
VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
DS12997 Rev 4
21/230
47
Functional overview
•
STM32G483xE
VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V VREF+ must be equal to VDDA.
When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
–
VREF+ = 2.048 V
–
VREF+ = 2.5 V
–
VREF+ = 2.9 V
VREF- is double bonded with VSSA.
3.11.2
Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a peripheral voltage monitor which compares the
independent supply voltages VDDA, with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
3.11.3
Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
22/230
•
Range 1 boost mode with the CPU running at up to 170 MHz.
•
Range 1 normal mode with CPU running at up to 150 MHz.
•
Range 2 with a maximum CPU frequency of 26 MHz.
DS12997 Rev 4
STM32G483xE
3.11.4
Functional overview
Low-power modes
By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
3.11.5
•
Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
•
Low-power run mode: This mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16.
•
Low-power sleep mode: This mode is entered from the low-power run mode. Only the
CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the
system reverts to the Low power run mode.
•
Stop mode: In Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
•
Standby mode: The Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
•
Shutdown mode: The Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
DS12997 Rev 4
23/230
47
Functional overview
3.11.6
STM32G483xE
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when there is no external battery and when an external
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note:
24/230
When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
DS12997 Rev 4
STM32G483xE
3.12
Functional overview
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Run
Sleep
Low-power run
Low-power sleep
Stop
Table 3. STM32G483xE peripherals interconnect matrix
TIMx
Timers synchronization or chaining
Y
Y
Y
Y
-
ADCx
DACx
Conversion triggers
Y
Y
Y
Y
-
DMA
Memory to memory transfer trigger
Y
Y
Y
Y
-
COMPx
Comparator output blanking
Y
Y
Y
Y
-
IRTIM
Infrared interface output generation
Y
Y
Y
Y
-
TIM1, 8, 20
TIM2, 3, 4, 5
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
-
LPTIMER1
Low-power timer triggered by analog
signals comparison
Y
Y
Y
Y
Y
TIM1, 8, 20
Timer triggered by analog watchdog
Y
Y
Y
Y
-
TIM16
Timer input channel from RTC events
Y
Y
Y
Y
-
LPTIMER1
Low-power timer triggered by RTC
alarms or tampers
Y
Y
Y
Y
Y
All clocks sources (internal and
external)
TIM5,
TIM15, 16, 17
Clock source used as input channel for
RC measurement and trimming
Y
Y
Y
Y
-
USB
TIM2
Timer triggered by USB SOF
Y
Y
-
-
-
CSS
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
TIM1,8, 20
TIM15,16,17
Timer break
Y
Y
Y
Y
-
CPU (hard fault)
TIM1,8,20
TIM15/16/17
Timer break
Y
Y
Y
Y
-
Interconnect source
TIMx
TIM16/TIM17
COMPx
ADCx
RTC
Interconnect
destination
Interconnect action
DS12997 Rev 4
25/230
47
Functional overview
STM32G483xE
26/230
Low-power run
Low-power sleep
Stop
GPIO
Sleep
Interconnect source
Run
Table 3. STM32G483xE peripherals interconnect matrix (continued)
TIMx
External trigger
Y
Y
Y
Y
-
LPTIMER1
External trigger
Y
Y
Y
Y
Y
ADCx
DACx
Conversion external trigger
Y
Y
Y
Y
-
Interconnect
destination
Interconnect action
DS12997 Rev 4
STM32G483xE
3.13
Functional overview
Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: three different sources can deliver SYSCLK system clock:
•
–
4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to system PLL. The HSE can also be configured in bypass
mode for an external clock.
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
–
System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–
32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–
32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
•
Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,
RNG) have their own clock independent of the system clock.
•
Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
•
Clock-out capability:
–
MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
–
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
DS12997 Rev 4
27/230
47
Functional overview
3.14
STM32G483xE
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
•
16 independently configurable channels (requests)
–
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
•
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
Support for circular buffer management
•
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•
Memory-to-memory transfer
•
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
•
Access to Flash, SRAM, APB and AHB peripherals as source and destination
•
Programmable number of data to be transferred: up to 65536.
Table 4. DMA implementation
28/230
DMA features
DMA1
DMA2
Number of regular channels
8
8
DS12997 Rev 4
STM32G483xE
3.16
Functional overview
DMA request router (DMAMUX)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.17
Interrupts and events
3.17.1
Nested vectored interrupt controller (NVIC)
The STM32G483xE devices embed a nested vectored interrupt controller which is able to
manage 16 priority levels, and to handle up to 102 maskable interrupt channels plus the 16
interrupt lines of the Cortex®-M4.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 44 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 107 GPIOs can
be connected to the 16 external interrupt lines.
DS12997 Rev 4
29/230
47
Functional overview
3.18
STM32G483xE
Analog-to-digital converter (ADC)
The device embeds five successive approximation analog-to-digital converters with the
following features:
•
12-bit native resolution, with built-in calibration
•
4 Msps maximum conversion rate with full resolution
Down to 41.67 ns sampling time
–
Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
•
One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
•
Single-ended and differential mode inputs
•
Low-power design
•
3.18.1
–
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
Results stored into a data register or in RAM with DMA controller support
–
Data pre-processing: left/right alignment and per channel offset compensation
–
Built-in oversampling unit for enhanced SNR
–
Channel-wise programmable sampling time
–
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
–
Flexible sample time control
–
Hardware gain and offset compensation
Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADCs input channels which is used to
convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
30/230
DS12997 Rev 4
STM32G483xE
Functional overview
Table 5. Temperature sensor calibration values
3.18.2
Calibration value name
Description
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
TS_CAL2
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
Memory address
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADCx_IN18,
x = 1,3,4,5 input channel. The precise voltage of VREFINT is individually measured for each
part by ST during production test and stored in the system memory area. It is accessible in
read-only mode.
Table 6. Internal voltage reference calibration values
3.18.3
Calibration value name
Description
Memory address
VREFINT
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the VBAT battery voltage using
the internal ADC1_IN17 channel. As the VBAT voltage may be higher than the VDDA, and
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one third of the VBAT voltage.
3.18.4
Operational amplifier internal output (OPAMPxINT):
The OPAMPx (x = 1...6) output OPAMPxINT can be sampled using an ADCx (x = 1...5)
internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be
used as GPIO.
3.19
Digital to analog converter (DAC)
Seven 12 bit DAC channels (3 external buffered and 4 internal unbuffered) can be used to
convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in inverting configuration.
DS12997 Rev 4
31/230
47
Functional overview
STM32G483xE
This digital interface supports the following features:
•
Up to two DAC output channels
•
8-bit or 12-bit output mode
•
Buffer offset calibration (factory and user trimming)
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Saw tooth wave generation
•
Dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
External triggers for conversion
•
Sample and hold low-power mode, with internal or external capacitor
•
Up to 1 Msps for external output and 15 Msps for internal output
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.20
Voltage reference buffer (VREFBUF)
The STM32G483xE devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports three voltages:
•
2.048 V
•
2.5 V
•
2.9 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 3. Voltage reference buffer
VREFBUF
VDDA
Bandgap
+
DAC, ADC
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
32/230
DS12997 Rev 4
STM32G483xE
3.21
Functional overview
Comparators (COMP)
The STM32G483xE devices embed seven rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis.
The reference voltage can be one of the following:
•
External I/O
•
DAC output channels
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.
3.22
Operational amplifier (OPAMP)
The STM32G483xE devices embed six operational amplifiers with external or internal
follower routing and PGA capability.
The operational amplifier features:
3.23
•
13 MHz bandwidth
•
Rail-to-rail input/output
•
PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging
of -1, -3, -7, -15, -31 or -63
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.24
Advanced encryption standard hardware accelerator (AES)
The STM32G483xE devices embed an AES hardware accelerator that can be used both to
encipher and to decipher data using an AES algorithm.
DS12997 Rev 4
33/230
47
Functional overview
STM32G483xE
The AES peripheral supports:
3.25
•
Encryption/decryption using AES Rijndael block cipher algorithm
•
NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
•
128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
•
Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported
•
Key scheduler
•
Key derivation for decryption
•
128-bit data block processing
•
128-bit, 256-bit key length
•
1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer
•
Register access supporting 32-bit data width only
•
One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode
•
Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data
•
Suspend a message if another message with a higher priority needs to be processed.
Timers and watchdogs
The STM32G483xE devices include three advanced motor control timers, up to nine
general-purpose timers, two basic timers, one low-power timer, two watchdog timers and a
SysTick timer. The table below compares the features of the advanced motor control,
general purpose and basic timers.
Table 7. Timer feature comparison
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Up,
Any integer
down, between 1 and
Up/down
65536
Yes
4
4
32-bit
Up,
Any integer
down, between 1 and
Up/down
65536
Yes
4
No
TIM3, TIM4
16-bit
Up,
Any integer
down, between 1 and
Up/down
65536
Yes
4
No
TIM15
16-bit
Any integer
between 1 and
65536
Yes
2
1
Timer type
Timer
Counter
resolution
Advanced
motor
control
TIM1, TIM8,
TIM20
16-bit
Generalpurpose
TIM2, TIM5
Generalpurpose
Generalpurpose
34/230
Counter
type
Up
Prescaler
factor
DS12997 Rev 4
STM32G483xE
Functional overview
Table 7. Timer feature comparison (continued)
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
outputs
Generalpurpose
TIM16, TIM17
16-bit
Up
Any integer
between 1 and
65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1 and
65536
Yes
0
No
3.25.1
Advanced motor control timer (TIM1, TIM8, TIM20)
The advanced motor control timers can each be seen as a four-phase
PWM multiplexed on 8 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as complete general-purpose
timers.
The 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced motor control timer counter can be frozen and the PWM
outputs disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.25.2) using the same architecture, so the advanced motor control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
DS12997 Rev 4
35/230
47
Functional overview
3.25.2
STM32G483xE
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32G483xE devices (see Table 7 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
–
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has 2 channels and 1 complementary channel
–
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.25.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
36/230
DS12997 Rev 4
STM32G483xE
3.25.4
Functional overview
Low-power timer (LPTIM1)
The devices embed a low-power timer. This timer has an independent clock and are running
in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system
from Stop mode.
LPTIM1 is active in Stop mode.
This low-power timer supports the following features:
3.25.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous/ one shot mode
•
Selectable software/hardware input trigger
•
Selectable clock source
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
–
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.25.6
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.25.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
DS12997 Rev 4
37/230
47
Functional overview
3.26
STM32G483xE
Real-time clock (RTC) and backup registers
The RTC supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.27
38/230
Tamper and backup registers (TAMP)
•
32 32-bit backup registers, retained in all low-power modes and also in VBAT mode.
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. They are not reset by a system or power reset, or when the device
wakes up from Standby or Shutdown mode.
•
Up to three tamper pins for external tamper detection events. The external tamper pins
can be configured for edge detection, edge and level, level detection with filtering.
•
Five internal tampers events.
•
Any tamper detection can generate a RTC timestamp event.
•
Any tamper detection erases the backup registers.
•
Any tamper detection can generate an interrupt and wake-up the device from all lowpower modes.
DS12997 Rev 4
STM32G483xE
3.28
Functional overview
Infrared transmitter
The STM32G483xE devices provide an infrared transmitter solution. The solution is based
on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 4. Infrared transmitter
TIM17_CH1
IRTIM
IR_OUT
TIM16_CH1
MS30474V2
DS12997 Rev 4
39/230
47
Functional overview
3.29
STM32G483xE
Inter-integrated circuit interface (I2C)
The device embeds four I2Cs. Refer to Table 8: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 8. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
Fast-mode (up to 400 kbit/s)
X
X
X
X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
Wakeup from Stop mode on address match
X
X
X
X
1. X: supported
40/230
DS12997 Rev 4
STM32G483xE
3.30
Functional overview
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32G483xE devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, USART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the U(S)ARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode. The wakeup from Stop mode can be
done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
All USART interfaces can be served by the DMA controller.
Table 9. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3
UART4
UART5
LPUART1
Hardware flow control for modem
X
X
X
X
X
X
Continuous communication using DMA
X
X
X
X
X
X
Multiprocessor communication
X
X
X
X
X
X
Synchronous mode
X
X
X
-
-
-
Smartcard mode
X
X
X
-
-
-
Single-wire half-duplex communication
X
X
X
X
X
X
IrDA SIR ENDEC block
X
X
X
X
X
-
LIN mode
X
X
X
X
X
-
Dual clock domain
X
X
X
X
X
X
Wakeup from Stop mode
X
X
X
X
X
X
Receiver timeout interrupt
X
X
X
X
X
-
Modbus communication
X
X
X
X
X
-
Auto baud rate detection
Driver Enable
X (4 modes)
X
X
LPUART/USART data length
X
X
X
X
7, 8 and 9 bits
DS12997 Rev 4
41/230
47
Functional overview
STM32G483xE
Table 9. USART/UART/LPUART features (continued)
USART modes/features(1)
USART1 USART2 USART3
UART4
Tx/Rx FIFO
X
Tx/Rx FIFO size
8
UART5
LPUART1
1. X = supported.
3.31
Low-power universal asynchronous receiver transmitter
(LPUART)
The STM32G483xE devices embed one Low-Power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default. It has a clock domain independent
from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop
mode can be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.32
Serial peripheral interface (SPI)
Four SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in
slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and hardware CRC calculation.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex communication modes. They can
be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and
synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can
be set by 8-bit programmable linear prescaler. When operating in master mode it can output
a clock for an external audio component at 256 times the sampling frequency.
All SPI interfaces can be served by the DMA controller.
42/230
DS12997 Rev 4
STM32G483xE
3.33
Functional overview
Serial audio interfaces (SAI)
The device embeds 1 SAI. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
SAI peripheral supports:
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
8-word integrated FIFOs for each audio sub-block.
•
Synchronous or asynchronous mode between the audio sub-blocks.
•
Master or slave configuration independent for both audio sub-blocks.
•
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
•
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
Number of bits by frame may be configurable.
•
Frame synchronization active level configurable (offset, bit length, level).
•
First active bit position in the slot is configurable.
•
LSB first or MSB first for data transfer.
•
Mute mode.
•
Stereo/Mono audio frame capability.
•
Communication clock strobing edge configurable (SCK).
•
Error flags with associated interrupts if enabled respectively.
•
•
–
Overrun and underrun detection.
–
Anticipated frame synchronization signal detection in slave mode.
–
Late frame synchronization signal detection in slave mode.
–
Codec not ready for the AC’97 mode in reception.
Interruption sources when enabled:
–
Errors.
–
FIFO requests.
DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Table 10. SAI features implementation
SAI features
Support(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
Mute mode
X
Stereo/Mono audio frame capability
X
16 slots
X
DS12997 Rev 4
43/230
47
Functional overview
STM32G483xE
Table 10. SAI features implementation (continued)
SAI features
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
FIFO size
Support(1)
X
X (8 word)
SPDIF
X
1. X: supported.
3.34
Controller area network (FDCAN1, FDCAN2, FDCAN3)
The controller area network (CAN) subsystem consists of three CAN modules and a shared
message RAM memory.
The three CAN modules (FDCAN1, FDCAN2 and FDCAN3) are compliant with ISO 11898-1
(CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification
version 1.0.
A 3-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers. This message RAM is shared between the three
FDCAN modules.
3.35
Universal serial bus (USB)
The STM32G483xE devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume
support. It requires a precise 48 MHz clock which can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
in automatic trimming mode. The synchronization for this oscillator can be taken from the
USB data stream itself (SOF signalization) which allows crystal less operation.
3.36
USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
44/230
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
•
“Dead battery” support
•
USB Power Delivery message transmission and reception
•
FRS (fast role swap) support
DS12997 Rev 4
STM32G483xE
Functional overview
The digital controller handles notably:
•
USB Type-C level detection with de-bounce, generating interrupts
•
FRS detection, generating an interrupt
•
Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
USB Power Delivery timing dividers (including a clock pre-scaler)
•
CRC generation/checking
•
4b5b encode/decode
•
Ordered sets (with a programmable ordered set mask at receive)
•
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.37
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.38
Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes two memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
This memory controller is also named Flexible memory controller (FMC).
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
–
Ferroelectric RAM (FRAM)
•
8-,16- bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
DS12997 Rev 4
45/230
47
Functional overview
STM32G483xE
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.39
Quad-SPI memory interface (QUADSPI)
The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the QUADSPI registers
•
Status polling mode: the external Flash status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
quad SPI Flash memories are accessed simultaneously.
The Quad-SPI interface supports:
46/230
•
Indirect mode: all the operations are performed using the QUADSPI registers
•
Status polling mode: the external Flash status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
•
Three functional modes: indirect, status-polling, and memory-mapped
•
SDR and DDR support
•
Fully programmable opcode for both indirect and memory mapped mode
•
Fully programmable frame format for both indirect and memory mapped mode
–
Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
–
Instruction phase
–
Address phase
–
Alternate bytes phase
–
Dummy cycles phase
–
Data phase
•
Integrated FIFO for reception and transmission
•
8, 16, and 32-bit data accesses are allowed
•
DMA channel for indirect mode operations
•
Programmable masking for external Flash flag management
•
Timeout management
•
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
DS12997 Rev 4
STM32G483xE
Functional overview
3.40
Development support
3.40.1
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.40.2
Embedded trace macrocell™
The Arm embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32G483xE devices through a small number of ETM pins to an external hardware trace
port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third party debugger software tools.
DS12997 Rev 4
47/230
47
Pinouts and pin description
STM32G483xE
4
Pinouts and pin description
4.1
UFQFPN48 pinout description
VDD
PB9
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PC11
PC10
PA15
PA14
48
47
46
45
44
43
42
41
40
39
38
37
Figure 5. STM32G483xE UFQFPN48 pinout
VBAT
1
36
PA13
PC13
2
35
VDD
PC14-OSC32_IN
3
34
PA12
PC15-OSC32_OUT
4
33
PA11
PF0-OSC_IN
5
32
PA10
PF1-OSC_OUT
6
31
PA9
PG10-NRST
7
30
PA8
PA0
8
29
PC6
PA1
9
28
PB15
PA2
10
27
PB14
PA3
11
26
PB13
PA4
12
25
PB12
UFQFPN48
1. The above figure shows the package top view.
2. VSS pads are connected to the exposed pad.
48/230
DS12997 Rev 4
24
PB11
23
VDD
22
PB10
21
VDDA
20
VREF+
19
PB2
18
PB1
17
PB0
16
PC4
15
PA7
14
PA6
PA5
13
Exposed pad
VSS
MS60210V1
STM32G483xE
4.2
Pinouts and pin description
LQFP48 pinout description
VDD
VSS
PB9
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
PA13
48
47
46
45
44
43
42
41
40
39
38
37
Figure 6. STM32G483xE LQFP48 pinout
VBAT
1
36
VDD
PC13
2
35
VSS
PC14 - OSC32_IN
3
34
PA12
PC15 - OSC32_OUT
4
33
PA11
PF0 - OSC_IN
5
32
PA10
PF1 - OSC_OUT
6
31
PA9
PG10 - NRST
7
30
PA8
PA0
8
29
PB15
PA1
9
28
PB14
PA2
10
27
PB13
PA3
11
26
PB12
PA4
12
25
PB11
13
14
15
16
17
18
19
20
21
22
23
24
PA5
PA6
PA7
PB0
PB1
PB2
VSSA
VREF+
VDDA
PB10
VSS
VDD
LQFP48
MSv42659V2
1. The above figure shows the package top view.
LQFP64 pinout description
VDD
VSS
PB9
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
PA13
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 7. STM32G483xE LQFP64 pinout
VBAT
1
48
VDD
PC13
2
47
VSS
PC14-OSC32_IN
3
46
PA12
PC15-OSC32_OUT
4
45
PA11
PF0-OSC_IN
5
44
PA10
PF1-OSC_OUT
6
43
PA9
PG10-NRST
7
42
PA8
PC0
8
41
PC9
PC1
9
40
PC8
PC2
10
39
PC7
PC3
11
38
PC6
PA0
12
37
PB15
PA1
13
36
PB14
PA2
14
35
PB13
VSS
15
34
PB12
VDD
16
33
PB11
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VDDA
PB10
VSS
VDD
LQFP64
PA3
4.3
MSv42658V2
1. The above figure shows the package top view.
DS12997 Rev 4
49/230
77
Pinouts and pin description
4.4
STM32G483xE
LQFP80 pinout description
VDD
VSS
PB9
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
PA13
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Figure 8. STM32G483xE LQFP80 pinout
VBAT
1
60
PA12
PC13
2
59
PA11
PC14-OSC32_IN
3
58
PA10
PC15-OSC32_OUT
4
57
PA9
PF0-OSC_IN
5
56
PA8
PF1-OSC_OUT
6
55
PC9
PG10-NRST
7
54
PC8
PC0
8
53
PC7
PC1
9
52
PC6
PC2
10
51
VDD
PC3
11
50
VSS
PA0
12
49
PD10
PA1
13
48
PD9
PA2
14
47
PD8
VSS
15
46
PB15
VDD
16
45
PB14
PA3
17
44
PB13
PA4
18
43
PB12
PA5
19
42
PB11
PA6
20
41
VDD
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PA7
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VDDA
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VSS
LQFP80
MSv60826V1
1. The above figure shows the package top view.
50/230
DS12997 Rev 4
STM32G483xE
LQFP100 pinout description
VDD
VSS
PE1
PE0
PB9
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
PA13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 9. STM32G483xE LQFP100 pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
PA12
PE5
4
72
PA11
PE6
5
71
PA10
VBAT
6
70
PA9
PC13
7
69
PA8
PC14-OSC32_IN
8
68
PC9
PC15-OSC32_OUT
9
67
PC8
PF9
10
66
PC7
PF10
11
65
PC6
PF0-OSC_IN
12
64
VDD
PF1-OSC_OUT
13
63
VSS
PG10-NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
PF2
19
57
PD10
PA0
20
56
PD9
PA1
21
55
PD8
PA2
22
54
PB15
VSS
23
53
PB14
VDD
24
52
PB13
PA3
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
VSSA
VREF+
VDDA
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VSS
VDD
PB11
LQFP100
PA4
4.5
Pinouts and pin description
MSv42661V3
1. The above figure shows the package top view.
DS12997 Rev 4
51/230
77
Pinouts and pin description
4.6
STM32G483xE
LQFP128 pinout description
VDD
VSS
PD1
PD0
PG9
PG8
PG7
PG6
PG5
PC12
PC11
PC10
PA15
PA14
PF6
110
109
108
107
106
105
104
103
102
101
100
99
98
97
PD4
111
PD5
114
PD3
PD6
115
PD2
PD7
116
112
PB3
117
113
PB4
PB7
122
118
PB8-BOOT0
123
119
PB9
124
PB6
PE0
125
PB5
PE1
126
120
VSS
127
121
VDD
128
Figure 10. STM32G483xE LQFP128 pinout
PE2
1
96
PA13
PE3
2
95
VDD
PE4
3
94
VSS
PE5
4
93
PA12
PE6
5
92
PA11
VBAT
6
91
PA10
PC13
7
90
PA9
PC14-OSC32_IN
8
89
PA8
PC15-OSC32_OUT
9
88
PC9
PF3
10
87
PC8
PF4
11
86
PG4
VSS
12
85
PG3
VDD
13
84
PG2
PF5
14
83
PG1
PF7
15
82
PG0
PF8
16
81
PC7
PF9
17
80
PC6
PF10
18
79
VDD
PF0-OSC_IN
19
78
VSS
PF1-OSC_OUT
20
77
PD15
PG10-NRST
21
76
PD14
PC0
22
75
PD13
PC1
23
74
PD12
PC2
24
73
PD11
PC3
25
72
PD10
PF2
26
71
PD9
PA0
27
70
PD8
PA1
28
69
PB15
PA2
29
68
PB14
VSS
30
67
PB13
VDD
31
66
PB12
PA3
32
65
PB11
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VSS
VDD
PF11
PF12
PF13
PF14
PF15
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
VSS
VDD
41
PB2
45
40
PB1
VDDA
39
PB0
44
38
PC5
VREF+
37
PC4
43
36
PA7
42
35
PA6
VSSA
34
PA5
VREF+
33
PA4
LQFP128
MSv42664V3
1. The above figure shows the package top view.
52/230
DS12997 Rev 4
STM32G483xE
4.7
Pinouts and pin description
WLCSP81 pinout description
Figure 11. STM32G483xE WLCSP81 pinout
1
2
3
4
5
6
7
8
9
A
VDD
PA15
PC12
PD1
PB3
PB5
PB9
VSS
VDD
B
VSS
PA13
PC10
PD0
PD2
PB6
PB8-BOOT0
PC13
VBAT
C
PA12
PA11
PA14
PC11
PC8
PB4
PB7
PC1
PC14OSC32_IN
D
PA8
PC9
PA10
PA9
PC7
PA4
PA0
PG10-NRST
PC15OSC32_OUT
E
VDD
PD11
PC6
PB15
PE12
PC4
PA1
PC0
PF0-OSC_IN
F
VSS
PD10
PD9
PE15
PE9
PB0
PA5
PC2
PF1OSC_OUT
G
PD8
PB14
PB12
PE13
PE8
PB1
PA6
PA2
PC3
H
PB13
PB11
PB10
PE11
PE7
VSSA
PC5
PA3
VSS
J
VDD
VSS
PE14
PE10
VDDA
VREF+
PB2
PA7
VDD
MSv48046V1
1. The above figure shows the package top view.
4.8
TFBGA100 pinout description
Figure 12. STM32G483xE TFBGA100 pinout
1
2
3
4
5
6
7
8
9
10
A
PE4
PB9
PB8-BOOT0
PB6
PB3
PD6
PD5
PD4
PD1
PC12
B
PE5
PE3
PE1
PB7
PB5
PD7
PD2
PD0
PA15
PA14
C
PC14OSC32_IN
PE6
PE2
PE0
PB4
PD3
PC11
PC10
PA12
PA11
D
PC15OSC32_OUT
VSS
VBAT
PC13
VDD
VSS
VDD
PA13
PA10
PA9
E
PF0-OSC_IN
PF1OSC_OUT
PF9
PF10
VSS
VSS
VSS
PC8
PC9
PA8
F
PC2
PC0
PG10-NRST
PC1
VDD
VSS
VDD
PD14
PC6
PC7
G
PC3
PA1
PF2
PA0
PE7
PE12
PD10
PD9
PD13
PD15
H
PA2
PA4
PA3
PB0
PE8
PE9
PE15
PB11
PB14
PD11
J
PA5
PA6
PC5
PB2
VDDA
PE11
PE14
PB10
PB13
PD12
K
PA7
PC4
PB1
VSSA
VREF+
PE10
PE13
PB12
PB15
PD8
MS48951V1
1. The above figure shows the package top view.
DS12997 Rev 4
53/230
77
Pinouts and pin description
4.9
STM32G483xE
UFBGA121 pinout description
Figure 13. STM32G483xE UFBGA121 pinout
1
2
3
4
5
6
7
8
9
10
11
A
PE4
PE2
VDD
PB9
PB6
PB3
PD4
VDD
PD1
PA15
PF6
B
PE5
PE3
VSS
PE0
PB5
PD7
PD3
VSS
PD0
PA14
PA13
C
PC13
VBAT
PE6
PE1
PB7
PB4
PD2
PC11
PC10
VSS
VDD
D
PC14OSC32_IN
PC15OSC32_OUT
PF3
PF4
PB8-BOOT0
PD6
PC12
PA9
PA10
PA12
PA11
E
VDD
VSS
PF5
PF7
PF8
PD5
PA8
PC9
PC8
PG4
PG3
F
PF0-OSC_IN
PF1OSC_OUT
PF9
PF10
PG10-NRST
PD15
PG2
PG1
PG0
PC6
PC7
G
PC1
PC0
PC2
PA0
PB1
PF15
PD11
PD12
PD13
PD14
VDD
H
PC3
PF2
PA1
PC5
PF12
PF14
PE10
PB15
PD8
PD9
PD10
J
VDD
VSS
PA2
PB0
PF11
PF13
PE9
PE13
PB12
PB14
PB13
K
PA3
PA5
PA7
PB2
VSSA
VSS
PE8
PE12
PE14
VSS
VDD
L
PA4
PA6
PC4
VREF+
VDDA
VDD
PE7
PE11
PE15
PB10
PB11
MS52876V1
1. The above figure shows the package top view.
54/230
DS12997 Rev 4
STM32G483xE
4.10
Pinouts and pin description
Pin definition
Table 11. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TT
3.6 V tolerant I/O
B
Dedicated BOOT0 pin
NRST
I/O structure
_a
I/O, with Analog switch function supplied by VDDA
_c
I/O, USB Type-C PD capable
_d
I/O, USB Type-C PD Dead Battery function
_u
Pin functions
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
(1)
_f(2)
Notes
Definition
(3)
I/O, Fm+ capable
I/O, with USB function
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 12 are: FT_a, FT_fa, TT_a.
2. The related I/O structures in Table 12 are: FT_f, FT_fa.
3. The related I/O structures in Table 12 are FT_u.
DS12997 Rev 4
55/230
77
Pinouts and pin description
STM32G483xE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C3
B2
A1
B1
1
2
3
4
A2
B2
A1
B1
1
2
3
4
PE2
PE3
PE4
PE5
I/O
I/O
I/O
I/O
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
FT
FT
FT
FT
Notes
-
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition
Alternate functions
Additional
functions
-
TRACECK,
TIM3_CH1,
SAI1_CK1, SPI4_SCK,
TIM20_CH1,
FMC_A23,
SAI1_MCLK_A,
EVENTOUT
-
-
TRACED0,
TIM3_CH2,
SPI4_NSS,
TIM20_CH2,
FMC_A19,
SAI1_SD_B,
EVENTOUT
-
-
TRACED1,
TIM3_CH3, SAI1_D2,
SPI4_NSS,
TIM20_CH1N,
FMC_A20,
SAI1_FS_A,
EVENTOUT
-
-
TRACED2,
TIM3_CH4,
SAI1_CK2,
SPI4_MISO,
TIM20_CH2N,
FMC_A21,
SAI1_SCK_A,
EVENTOUT
-
WKUP3,
RTC_TAMP3
-
-
-
-
-
C2
5
C3
5
PE6
I/O
FT
-
TRACED3, SAI1_D1,
SPI4_MOSI,
TIM20_CH3N,
FMC_A22,
SAI1_SD_A,
EVENTOUT
B9
1
1
1
1
D3
6
C2
6
VBAT
S
-
-
-
-
TIM1_BKIN,
TIM1_CH1N,
TIM8_CH4N,
EVENTOUT
WKUP2,
RTC_TAMP1,
RTC_TS,
RTC_OUT1
EVENTOUT
OSC32_IN
(3)
EVENTOUT
OSC32_OUT
-
TIM20_CH4,
I2C3_SCL,
FMC_A3, EVENTOUT
-
B8
2
2
2
2
D4
7
C1
7
PC13
I/O
FT
C9
3
3
3
3
C1
8
D1
8
PC14OSC32_IN
I/O
FT
D9
4
4
4
4
D1
9
D2
9
PC15I/O
OSC32_OUT
FT
-
-
-
-
-
-
-
D3
10
56/230
PF3
I/O
DS12997 Rev 4
FT_f
(2)
(3)
(2)
(3)
(2)
STM32G483xE
Pinouts and pin description
-
-
D4
11
PF4
I/O
FT_f
-
F1
-
-
-
-
D2
-
E2
12
VSS
S
-
-
-
-
A9
-
-
-
-
D5
-
E1
13
VDD
S
-
-
-
-
-
-
-
-
-
-
-
E3
14
PF5
I/O
FT
-
TIM20_CH2N,
FMC_A5, EVENTOUT
-
-
TIM20_BKIN,
TIM5_CH2,
QUADSPI1_BK1_IO2,
FMC_A1,
SAI1_MCLK_B,
EVENTOUT
-
-
TIM20_BKIN2,
TIM5_CH3,
QUADSPI1_BK1_IO0,
FMC_A24,
SAI1_SCK_B,
EVENTOUT
-
-
TIM20_BKIN,
TIM15_CH1,
SPI2_SCK,
TIM5_CH4,
QUADSPI1_BK1_IO1,
FMC_A25,
SAI1_FS_B,
EVENTOUT
-
-
TIM20_BKIN2,
TIM15_CH2,
SPI2_SCK,
QUADSPI1_CLK,
FMC_A0, SAI1_D3,
EVENTOUT
-
FT_fa
-
I2C2_SDA,
SPI2_NSS/I2S2_WS,
TIM1_CH3N,
EVENTOUT
ADC1_IN10,
OSC_IN
FT_a
-
SPI2_SCK/I2S2_CK,
EVENTOUT
ADC2_IN10,
COMP3_INM,
OSC_OUT
-
MCO, EVENTOUT
NRST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E3
E4
-
-
10
11
E4
E5
F3
F4
LPQF128
-
LPQF100
-
TFBGA100
-
LQFP80
-
LQFP64
-
COMP1_OUT,
TIM20_CH1N,
I2C3_SDA, FMC_A4,
EVENTOUT
LQFP48
Alternate functions
WLCSP81
Notes
I/O structure
Pin type
UFBGA121
UFQFPN48
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
15
16
17
18
PF7
PF8
PF9
PF10
I/O
I/O
I/O
I/O
E9
5
5
5
5
E1
12
F1
19
PF0-OSC_IN I/O
F9
6
6
6
6
E2
13
F2
20
PF1OSC_OUT
I/O
D8
7
7
7
7
F3
14
F5
21
PG10-NRST
I/O
DS12997 Rev 4
FT
FT
FT
FT
NRST
(4)
Additional
functions
-
57/230
77
Pinouts and pin description
STM32G483xE
C8
F8
-
-
-
-
-
8
9
10
8
9
10
F2
F4
F1
15
16
17
G2
G1
G3
22
23
24
PC0
PC1
PC2
I/O
I/O
I/O
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
FT_a
TT_a
FT_a
Notes
E8
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
LPTIM1_IN1,
TIM1_CH1,
LPUART1_RX,
EVENTOUT
ADC12_IN6,
COMP3_INM
-
LPTIM1_OUT,
TIM1_CH2,
LPUART1_TX,
QUADSPI1_BK2_IO0,
SAI1_SD_A,
EVENTOUT
ADC12_IN7,
COMP3_INP
-
LPTIM1_IN2,
TIM1_CH3,
COMP3_OUT,
TIM20_CH2,
QUADSPI1_BK2_IO1,
EVENTOUT
ADC12_IN8
ADC12_IN9,
OPAMP5_VINP
G9
-
-
11
11
G1
18
H1
25
PC3
I/O
TT_a
-
LPTIM1_ETR,
TIM1_CH4, SAI1_D1,
TIM1_BKIN2,
QUADSPI1_BK2_IO2,
SAI1_SD_A,
EVENTOUT
-
-
-
-
-
G3
19
H2
26
PF2
I/O
FT
-
TIM20_CH3,
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
TIM2_CH1,
TIM5_CH1,
USART2_CTS,
COMP1_OUT,
TIM8_BKIN,
TIM8_ETR,
TIM2_ETR,
EVENTOUT
ADC12_IN1,
COMP1_INM,
COMP3_INP,
RTC_TAMP2,WK
UP1
-
RTC_REFIN,
TIM2_CH2,
TIM5_CH2,
USART2_RTS_DE,
TIM15_CH1N,
EVENTOUT
ADC12_IN2,
COMP1_INP,
OPAMP1_VINP,
OPAMP3_VINP,
OPAMP6_VINM
-
TIM2_CH3,
TIM5_CH3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
QUADSPI1_BK1_NCS
, LPUART1_TX,
UCPD1_FRSTX,
EVENTOUT
ADC1_IN3,
COMP2_INM,
OPAMP1_VOUT,
WKUP4/LSCO
D7
E7
G8
8
9
10
58/230
8
9
10
12
13
14
12
13
14
G4
G2
H1
20
21
22
G4
H3
J3
27
28
29
PA0
PA1
PA2
I/O
I/O
I/O
DS12997 Rev 4
TT_a
TT_a
FT_a
STM32G483xE
Pinouts and pin description
Table 12. STM32G483xE pin definition (continued)
WLCSP81
UFQFPN48
LQFP48
LQFP64
LQFP80
TFBGA100
LPQF100
UFBGA121
LPQF128
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
H9
-
-
15
15
D6
23
J2
30
VSS
S
-
-
-
-
J9
-
-
16
16
D7
24
J1
31
VDD
S
-
-
-
-
-
TIM2_CH4,
TIM5_CH4,
SAI1_CK1,
USART2_RX,
TIM15_CH2,
QUADSPI1_CLK,
LPUART1_RX,
SAI1_MCLK_A,
EVENTOUT
ADC1_IN4,
COMP2_INP,
OPAMP1_VINM/
OPAMP
1_VINP,
OPAMP5_VINM
-
TIM3_CH2,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
SAI1_FS_B,
EVENTOUT
ADC2_IN17,
DAC1_OUT1,
COMP1_INM
-
TIM2_CH1,
TIM2_ETR,
SPI1_SCK,
UCPD1_FRSTX,
EVENTOUT
ADC2_IN13,
DAC1_OUT2,
COMP2_INM,
OPAMP2_VINM
-
TIM16_CH1,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
TIM1_BKIN,
COMP1_OUT,
QUADSPI1_BK1_IO3,
LPUART1_CTS,
EVENTOUT
ADC2_IN3,
DAC2_OUT1,
OPAMP2_VOUT
-
TIM17_CH1,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI,
TIM1_CH1N,
COMP2_OUT,
QUADSPI1_BK1_IO2,
UCPD1_FRSTX,
EVENTOUT
ADC2_IN4,
COMP2_INP,
OPAMP1_VINP,
OPAMP2_VINP
-
TIM1_ETR, I2C2_SCL,
USART1_TX,
QUADSPI1_BK2_IO3,
EVENTOUT
ADC2_IN5
H8
D6
F7
G7
J8
E6
11
12
13
14
15
16
11
12
13
14
15
-
17
18
19
20
21
22
17
18
19
20
21
22
H3
H2
J1
J2
K1
K2
25
26
27
28
29
30
K1
L1
K2
L2
K3
L3
32
33
34
35
36
37
PA3
PA4
PA5
PA6
PA7
PC4
I/O
I/O
I/O
I/O
I/O
I/O
DS12997 Rev 4
TT_a
TT_a
TT_a
TT_a
TT_a
FT_fa
Additional
functions
59/230
77
Pinouts and pin description
STM32G483xE
F6
G6
-
17
18
16
17
23
24
25
23
24
25
J3
H4
K3
31
32
33
H4
J4
G5
38
39
40
PC5
PB0
PB1
I/O
I/O
I/O
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
TT_a
TT_a
TT_a
Notes
H7
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
TIM15_BKIN,
SAI1_D3,
TIM1_CH4N,
USART1_RX,
EVENTOUT
ADC2_IN11,
OPAMP1_VINM,
OPAMP2_VINM,
WKUP5
-
TIM3_CH3,
TIM8_CH2N,
TIM1_CH2N,
QUADSPI1_BK1_IO1,
UCPD1_FRSTX,
EVENTOUT
ADC3_IN12/
ADC1_IN15,
COMP4_INP,
OPAMP2_VINP,
OPAMP3_VINP
-
TIM3_CH4,
TIM8_CH3N,
TIM1_CH3N,
COMP4_OUT,
QUADSPI1_BK1_IO0,
EVENTOUT
ADC3_IN1/
ADC1_IN12,
COMP1_INP,
OPAMP3_VOUT,
OPAMP6_VINM
ADC2_IN12,
COMP4_INM,
OPAMP3_VINM
J7
19
18
26
26
J4
34
K4
41
PB2
I/O
TT_a
-
RTC_OUT2,
LPTIM1_OUT,
TIM5_CH1,
TIM20_CH1,
I2C3_SMBA,
QUADSPI1_BK2_IO1,
EVENTOUT
H6
-
19
27
27
K4
35
K5
42
VSSA
S
-
-
-
-
J6
20
20
28
28
K5
36
L4
43
VREF+
S
-
-
-
VREFBUF_OUT
-
-
-
-
-
-
-
-
44
VREF+
S
-
-
-
VREFBUF_OUT
J5
21
21
29
29
J5
37
L5
45
VDDA
S
-
-
-
-
H9
-
-
-
-
E5
-
K6
46
VSS
S
-
-
-
-
J1
-
-
-
-
F5
-
L6
47
VDD
S
-
-
-
-
-
-
-
-
-
-
-
J5
48
PF11
I/O
FT
-
TIM20_ETR,
FMC_NE4,
EVENTOUT
-
-
-
-
-
-
-
-
H5
49
PF12
I/O
FT
-
TIM20_CH1, FMC_A6,
EVENTOUT
-
-
-
-
-
-
-
-
J6
50
PF13
I/O
FT
-
TIM20_CH2,
I2C4_SMBA, FMC_A7,
EVENTOUT
-
-
-
-
-
-
-
-
H6
51
PF14
I/O
FT_f
-
TIM20_CH3,
I2C4_SCL, FMC_A8,
EVENTOUT
-
-
-
-
-
-
-
-
G6
52
PF15
I/O
FT_f
-
TIM20_CH4,
I2C4_SDA, FMC_A9,
EVENTOUT
-
60/230
DS12997 Rev 4
STM32G483xE
Pinouts and pin description
Table 12. STM32G483xE pin definition (continued)
WLCSP81
UFQFPN48
LQFP48
LQFP64
LQFP80
TFBGA100
LPQF100
UFBGA121
LPQF128
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
H5
-
-
-
30
G5
38
L7
53
PE7
I/O
TT_a
-
TIM1_ETR, FMC_D4,
SAI1_SD_B,
EVENTOUT
G5
F5
J4
H4
E5
G4
J3
F4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
31
32
33
34
35
36
37
38
H5
H6
K6
J6
G6
K7
J7
H7
39
40
41
42
43
44
45
46
K7
J7
H7
L8
K8
J8
K9
L9
54
55
56
57
58
59
60
61
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS12997 Rev 4
FT_a
FT_a
FT_a
FT_a
FT_a
FT_a
FT_a
FT_a
Additional
functions
ADC3_IN4,
COMP4_INP
-
TIM5_CH3,
TIM1_CH1N,
FMC_D5,
SAI1_SCK_B,
EVENTOUT
ADC345_IN6,
COMP4_INM
-
TIM5_CH4,
TIM1_CH1, FMC_D6,
SAI1_FS_B,
EVENTOUT
ADC3_IN2
-
TIM1_CH2N,
QUADSPI1_CLK,
FMC_D7,
SAI1_MCLK_B,
EVENTOUT
ADC345_IN14
-
TIM1_CH2,
SPI4_NSS,
QUADSPI1_BK1_NCS
, FMC_D8,
EVENTOUT
ADC345_IN15
-
TIM1_CH3N,
SPI4_SCK,
QUADSPI1_BK1_IO0,
FMC_D9, EVENTOUT
ADC345_IN16
-
TIM1_CH3,
SPI4_MISO,
QUADSPI1_BK1_IO1,
FMC_D10,
EVENTOUT
ADC3_IN3
-
TIM1_CH4,
SPI4_MOSI,
TIM1_BKIN2,
QUADSPI1_BK1_IO2,
FMC_D11,
EVENTOUT
ADC4_IN1
-
TIM1_BKIN,
TIM1_CH4N,
USART3_RX,
QUADSPI1_BK1_IO3,
FMC_D12,
EVENTOUT
ADC4_IN2
61/230
77
Pinouts and pin description
STM32G483xE
J8
47
L10
62
PB10
I/O
TT_a
-
J2
-
23
31
40
E6
48
K10
63
VSS
S
-
-
-
-
J1
23
24
32
41
F7
49
K11
64
VDD
S
-
-
-
-
-
TIM2_CH4,
USART3_RX,
LPUART1_TX,
QUADSPI1_BK1_NCS
, EVENTOUT
ADC12_IN14,
COMP6_INP,
OPAMP4_VINP,
OPAMP6_VOUT
-
TIM5_ETR,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
TIM1_BKIN,
USART3_CK,
LPUART1_RTS_DE,
FDCAN2_RX,
EVENTOUT
ADC4_IN3/
ADC1_IN11,
COMP7_INM,
OPAMP4_VOUT,
OPAMP6_VINP
-
SPI2_SCK/I2S2_CK,
TIM1_CH1N,
USART3_CTS,
LPUART1_CTS,
FDCAN2_TX,
EVENTOUT
ADC3_IN5,
COMP5_INP,
OPAMP3_VINP,
OPAMP4_VINP,
OPAMP6_VINP
-
TIM15_CH1,
SPI2_MISO,
TIM1_CH2N,
USART3_RTS_DE,
COMP4_OUT,
EVENTOUT
ADC4_IN4/
ADC1_IN5,
COMP7_INP,
OPAMP2_VINP,
OPAMP5_VINP
ADC4_IN5/
ADC2_IN15,
COMP6_INM,
OPAMP5_VINM
H2
G3
H1
G2
24
25
26
27
25
26
27
28
33
34
35
36
42
43
44
45
H8
K8
J9
H9
50
51
52
53
L11
J9
J11
J10
LPQF128
39
LPQF100
30
TFBGA100
22
LQFP80
22
LQFP64
H3
TIM2_CH3,
USART3_TX,
LPUART1_RX,
QUADSPI1_CLK,
TIM1_BKIN,
SAI1_SCK_A,
EVENTOUT
LQFP48
Alternate functions
WLCSP81
Notes
I/O structure
Pin type
UFBGA121
UFQFPN48
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
65
66
67
68
PB11
PB12
PB13
PB14
I/O
I/O
I/O
I/O
TT_a
TT_a
TT_a
TT_a
Additional
functions
COMP5_INM,
OPAMP3_VINM,
OPAMP4_VINM
E4
28
29
37
46
K9
54
H8
69
PB15
I/O
TT_a
-
RTC_REFIN,
TIM15_CH2,
TIM15_CH1N,
COMP3_OUT,
TIM1_CH3N,
SPI2_MOSI/I2S2_SD,
EVENTOUT
G1
-
-
-
47
K10
55
H9
70
PD8
I/O
TT_a
-
USART3_TX,
FMC_D13,
EVENTOUT
ADC4_IN12/
ADC5_IN12,
OPAMP4_VINM
F3
-
-
-
48
G8
56
H10
71
PD9
I/O
TT_a
-
USART3_RX,
FMC_D14,
EVENTOUT
ADC4_IN13/
ADC5_IN13,
OPAMP6_VINP
62/230
DS12997 Rev 4
STM32G483xE
Pinouts and pin description
Table 12. STM32G483xE pin definition (continued)
WLCSP81
UFQFPN48
LQFP48
LQFP64
LQFP80
TFBGA100
LPQF100
UFBGA121
LPQF128
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
F2
-
-
-
49
G7
57
H11
72
PD10
I/O
FT_a
-
USART3_CK,
FMC_D15,
EVENTOUT
E2
-
-
-
-
H10
58
G7
73
PD11
I/O
TT_a
Additional
functions
ADC345_IN7,
COMP6_INM
-
TIM5_ETR,
I2C4_SMBA,
USART3_CTS,
FMC_A16,
EVENTOUT
ADC345_IN8,
COMP6_INP,
OPAMP4_VINP
ADC345_IN9,
COMP5_INP,
OPAMP5_VINP
-
-
-
-
-
J10
59
G8
74
PD12
I/O
TT_a
-
TIM4_CH1,
USART3_RTS_DE,
FMC_A17,
EVENTOUT
-
-
-
-
-
G9
60
G9
75
PD13
I/O
FT_a
-
TIM4_CH2, FMC_A18,
EVENTOUT
ADC345_IN10,
COMP5_INM
-
-
-
-
-
F8
61
G10
76
PD14
I/O
TT_a
-
TIM4_CH3,
FMC_D0, EVENTOUT
ADC345_IN11,
COMP7_INP,
OPAMP2_VINP
-
-
-
-
-
G10
62
F6
77
PD15
I/O
FT_a
-
TIM4_CH4,
SPI2_NSS,
FMC_D1, EVENTOUT
COMP7_INM
B1
-
-
-
50
E7
63
-
78
VSS
S
-
-
-
-
E1
-
-
-
51
-
64
G11
79
VDD
S
-
-
-
-
-
TIM3_CH1,
TIM8_CH1,
I2S2_MCK,
COMP6_OUT,
I2C4_SCL,
EVENTOUT
-
-
E3
29
-
38
52
F9
65
F10
80
PC6
I/O
FT_f
D5
-
-
39
53
F10
66
F11
81
PC7
I/O
FT_f
-
TIM3_CH2,
TIM8_CH2,
I2S3_MCK,
COMP5_OUT,
I2C4_SDA,
EVENTOUT
-
-
-
-
-
-
-
F9
82
PG0
I/O
FT
-
TIM20_CH1N,
FMC_A10,
EVENTOUT
-
-
-
-
-
-
-
-
F8
83
PG1
I/O
FT
-
TIM20_CH2N,
FMC_A11,
EVENTOUT
-
-
-
-
-
-
-
-
F7
84
PG2
I/O
FT
-
TIM20_CH3N,
SPI1_SCK, FMC_A12,
EVENTOUT
-
DS12997 Rev 4
63/230
77
Pinouts and pin description
STM32G483xE
-
C5
D2
D1
D4
-
-
-
-
30
31
64/230
-
-
-
30
31
-
-
40
41
42
43
-
-
54
55
56
57
-
-
E8
E9
E10
D10
-
-
67
68
69
70
E11
E10
E9
E8
E7
D8
85
86
87
88
89
90
PG3
PG4
PC8
PC9
PA8
PA9
I/O
I/O
I/O
I/O
I/O
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
FT_f
FT_f
FT_f
FT_f
FT_a
I/O FT_fda
DS12997 Rev 4
Notes
-
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
TIM20_BKIN,
I2C4_SCL,
SPI1_MISO,
TIM20_CH4N,
FMC_A13,
EVENTOUT
-
-
TIM20_BKIN2,
I2C4_SDA,
SPI1_MOSI,
FMC_A14,
EVENTOUT
-
-
TIM3_CH3,
TIM8_CH3,
TIM20_CH3,
COMP7_OUT,
I2C3_SCL,
EVENTOUT
-
-
TIM3_CH4,
TIM8_CH4, I2SCKIN,
TIM8_BKIN2,
I2C3_SDA,
EVENTOUT
-
-
MCO, I2C3_SCL,
I2C2_SDA,
I2S2_MCK,
TIM1_CH1,
USART1_CK,
COMP7_OUT,
TIM4_ETR,
FDCAN3_RX,
SAI1_CK2,
SAI1_SCK_A,
EVENTOUT
ADC5_IN1,
OPAMP5_VOUT
-
I2C3_SMBA,
I2C2_SCL, I2S3_MCK,
TIM1_CH2,
USART1_TX,
OMP5_OUT,
TIM15_BKIN,
TIM2_CH3,
SAI1_FS_A,
EVENTOUT
ADC5_IN2,
UCPD1_DBCC1
STM32G483xE
Pinouts and pin description
C2
32
33
33
44
45
58
59
D9
C10
71
72
D9
D11
91
92
PA10
PA11
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
32
I/O FT_fda
I/O
FT_u
Notes
D3
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
TIM17_BKIN,
USB_CRS_SYNC,
I2C2_SMBA,
SPI2_MISO,
TIM1_CH3,
USART1_RX,
COMP6_OUT,
TIM2_CH4,
TIM8_BKIN, SAI1_D1,
SAI1_SD_A,
EVENTOUT
UCPD1_DBCC2,
PVD_IN
-
SPI2_MOSI/I2S2_SD,
TIM1_CH1N,
USART1_CTS,
COMP1_OUT,
FDCAN1_RX,
TIM4_CH1,
TIM1_CH4,
TIM1_BKIN2,
EVENTOUT
USB_DM
USB_DP
C1
34
34
46
60
C9
73
D10
93
PA12
I/O
FT_u
-
TIM16_CH1, I2SCKIN,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT,
FDCAN1_TX,
TIM4_CH2,
TIM1_ETR,
EVENTOUT
A8
-
35
47
61
F6
74
C10
94
VSS
S
-
-
-
-
A1
35
36
48
62
-
75
C11
95
VDD
S
-
-
-
-
(5)
SWDIO-JTMS,
TIM16_CH1N,
I2C4_SCL, I2C1_SCL,
IR_OUT,
USART3_CTS,
TIM4_CH3,
SAI1_SD_B,
EVENTOUT
-
-
TIM5_ETR,
TIM4_CH4,
SAI1_SD_B,
I2C2_SCL, TIM5_CH1,
USART3_RTS,
QUADSPI1_BK1_IO3,
EVENTOUT
-
B2
-
36
-
37
-
49
-
63
-
D8
-
76
-
B11
A11
96
97
PA13
PF6
I/O
I/O
DS12997 Rev 4
FT_f
FT_f
65/230
77
Pinouts and pin description
STM32G483xE
C3
A2
B3
C4
A3
-
-
37
38
39
40
-
-
-
66/230
38
39
-
-
-
-
-
50
51
52
53
54
-
-
64
65
66
67
68
-
-
B10
B9
C8
C7
A10
-
-
77
78
79
80
81
-
-
B10
A10
C9
C8
D7
-
-
98
99
100
101
102
103
104
PA14
PA15
PC10
PC11
PC12
PG5
PG6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS12997 Rev 4
FT_f
FT_f
FT
FT_f
FT
FT
FT
Notes
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
(5)
SWCLK-JTCK,
LPTIM1_OUT,
I2C4_SMBA,
I2C1_SDA,
TIM8_CH2,
TIM1_BKIN,
USART2_TX,
SAI1_FS_B,
EVENTOUT
-
(5)
JTDI, TIM2_CH1,
TIM8_CH1, I2C1_SCL,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_RX,
UART4_RTS_DE,
TIM1_BKIN,
FDCAN3_TX,
TIM2_ETR,
EVENTOUT
-
-
TIM8_CH1N,
UART4_TX,
SPI3_SCK/I2S3_CK,
USART3_TX,
EVENTOUT
-
-
TIM8_CH2N,
UART4_RX,
SPI3_MISO,
USART3_RX,
I2C3_SDA,
EVENTOUT
-
-
TIM5_CH2,
TIM8_CH3N,
UART5_TX,
SPI3_MOSI/I2S3_SD,
USART3_CK,
UCPD1_FRSTX,
EVENTOUT
-
-
TIM20_ETR,
SPI1_NSS,
LPUART1_CTS,
FMC_A15,
EVENTOUT
-
-
TIM20_BKIN,
I2C3_SMBA,
LPUART1_RTS_DE,
FMC_INT, EVENTOUT
-
STM32G483xE
Pinouts and pin description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
105
106
PG7
PG8
I/O
I/O
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
FT_f
FT_f
Notes
-
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
SAI1_CK1, I2C3_SCL,
LPUART1_TX,
FMC_INT,
SAI1_MCLK_A,
EVENTOUT
-
-
I2C3_SDA,
LPUART1_RX,
FMC_NE3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
107
PG9
I/O
FT
-
SPI3_SCK,
USART1_TX,
FMC_NCE/FMC_NE2,
TIM15_CH1N,
EVENTOUT
B4
-
-
-
69
B8
82
B9
108
PD0
I/O
FT
-
TIM8_CH4N,
FDCAN1_RX,
FMC_D2, EVENTOUT
-
-
A4
-
-
-
70
A9
83
A9
109
PD1
I/O
FT
-
TIM8_CH4,
TIM8_BKIN2,
FDCAN1_TX,
FMC_D3, EVENTOUT
-
-
-
-
-
-
-
B8
110
VSS
S
-
-
-
-
A1
-
-
-
-
-
-
A8
111
VDD
S
-
-
-
-
-
TIM3_ETR,
TIM8_BKIN,
UART5_RX,
EVENTOUT
-
-
TIM2_CH1/
TIM2_ETR,
USART2_CTS,
QUADSPI1_BK2_NCS
, FMC_CLK,
EVENTOUT
-
-
TIM2_CH2,
USART2_RTS_DE,
QUADSPI1_BK2_IO0,
FMC_NOE,
EVENTOUT
-
-
USART2_TX,
QUADSPI1_BK2_IO1,
FMC_NWE,
EVENTOUT
-
B5
-
-
-
-
-
-
-
-
-
-
-
55
-
-
-
71
-
-
-
B7
C6
A8
A7
84
85
86
87
C7
B7
A7
E6
112
113
114
115
PD2
PD3
PD4
PD5
I/O
I/O
I/O
I/O
DS12997 Rev 4
FT
FT
FT
FT
67/230
77
Pinouts and pin description
STM32G483xE
-
A5
C6
A6
-
-
41
42
43
68/230
-
40
41
42
-
-
56
57
58
-
-
72
73
74
A6
B6
A5
C5
B5
88
89
90
91
92
D6
B6
A6
C6
B5
116
117
118
119
120
PD6
PD7
PB3
PB4
PB5
I/O
I/O
I/O
I/O
I/O
DS12997 Rev 4
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
-
FT
FT
FT
FT_c
FT_f
Notes
-
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
-
TIM2_CH4, SAI1_D1,
USART2_RX,
QUADSPI1_BK2_IO2,
FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
-
-
TIM2_CH3,
USART2_CK,
QUADSPI1_BK2_IO3,
FMC_NCE/FMC_NE1,
EVENTOUT
-
(5)
JTDO-TRACESWO,
TIM2_CH2,
TIM4_ETR,
UCPD1_CRS_SYNC,
TIM8_CH1N,
SPI1_SCK,
SPI3_SCK/I2S3_CK,
USART2_TX,
TIM3_ETR,
FDCAN3_RX,
SAI1_SCK_B,
EVENTOUT
-
(6)
JTRST, TIM16_CH1,
TIM3_CH1,
TIM8_CH2N,
SPI1_MISO,
SPI3_MISO,
USART2_RX,
UART5_RTS_DE,
TIM17_BKIN,
FDCAN3_TX,
SAI1_MCLK_B,
EVENTOUT
UCPD1_CC2
-
TIM16_BKIN,
TIM3_CH2,
TIM8_CH3N,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
USART2_CK,
I2C3_SDA,
FDCAN2_RX,
TIM17_CH1,
LPTIM1_IN1,
SAI1_SD_B,
UART5_CTS,
EVENTOUT
-
(5)
STM32G483xE
Pinouts and pin description
B6
C7
B7
A7
-
44
45
46
47
-
43
44
45
46
-
59
60
61
62
-
75
76
77
78
-
A4
B4
A3
A2
C4
93
94
95
96
97
A5
C5
D5
A4
B4
121
122
PB6
PB7
123 PB8-BOOT0
124
125
PB9
PE0
I/O
I/O
I/O
I/O
I/O
DS12997 Rev 4
FT_c
FT_f
FT_f
FT_f
FT
Notes
I/O structure
Pin type
LPQF128
UFBGA121
LPQF100
TFBGA100
LQFP80
LQFP64
LQFP48
UFQFPN48
WLCSP81
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Alternate functions
Additional
functions
(6)
TIM16_CH1N,
TIM4_CH1,
TIM8_CH1,
TIM8_ETR,
USART1_TX,
COMP4_OUT,
FDCAN2_TX,
TIM8_BKIN2,
LPTIM1_ETR,
SAI1_FS_B,
EVENTOUT
UCPD1_CC1
-
TIM17_CH1N,
TIM4_CH2,
I2C4_SDA, I2C1_SDA,
TIM8_BKIN,
USART1_RX,
COMP3_OUT,
TIM3_CH4,
LPTIM1_IN2,
FMC_NL,
UART4_CTS,
EVENTOUT
-
(7)
TIM16_CH1,
TIM4_CH3,
SAI1_CK1,
I2C1_SCL,
USART3_RX,
COMP1_OUT,
FDCAN1_RX,
TIM8_CH2,
TIM1_BKIN,
SAI1_MCLK_A,
EVENTOUT
-
-
TIM17_CH1,
TIM4_CH4,
SAI1_D2,
I2C1_SDA,
IR_OUT, USART3_TX,
COMP2_OUT,
FDCAN1_TX,
TIM8_CH3,
TIM1_CH3N,
SAI1_FS_A,
EVENTOUT
-
-
TIM4_ETR,
TIM20_CH4N,
TIM16_CH1,
TIM20_ETR,
USART1_TX,
FMC_NBL0,
EVENTOUT
-
69/230
77
Pinouts and pin description
STM32G483xE
B3
98
C4
126
PE1
I/O
FT
-
-
-
47
63
79
-
99
B3
127
VSS
S
-
-
-
-
A9
48
48
64
80
-
100
A3
128
VDD
S
-
-
-
-
LPQF128
-
LPQF100
-
TFBGA100
-
LQFP80
-
LQFP64
-
TIM17_CH1,
TIM20_CH4,
USART1_RX,
FMC_NBL1,
EVENTOUT
LQFP48
Alternate functions
WLCSP81
Notes
I/O structure
Pin type
UFBGA121
UFQFPN48
Pin Number
Pin name
(function after
reset)(1)
Table 12. STM32G483xE pin definition (continued)
Additional
functions
-
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA),
the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
3.
After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit
MCUs”.
4. PG10-NRST pin is FT tolerant if it is configured as PG10 GPIO by option bytes except for the startup time until option bytes
are loaded.
5. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
6. After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down on
PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support on
UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have UCPD_CC
functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the UCPD_DBCC
pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The pull-down effect on
the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead battery disable) in
the PWR_CR3 register.
7.
It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left
unconnected.
70/230
DS12997 Rev 4
Alternate functions
Table 13. Alternate function
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PA0
-
TIM2_CH1
TIM5_CH1
-
-
-
-
USART2_
CTS
COMP1
_OUT
TIM8_
BKIN
TIM8_ETR
-
-
-
TIM2_
ETR
EVENT
OUT
PA1
RTC_
REFIN
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_
RTS_DE
-
TIM15_C
H1N
-
-
-
-
-
EVENT
OUT
PA2
-
TIM2_CH3
TIM5_CH3
-
-
-
-
USART2_
TX
COMP2
_OUT
TIM15_C
H1
QUADSPI_B
K1_NCS
-
LPUART1_TX
-
UCPD_
FRSTX
EVENT
OUT
PA3
-
TIM2_CH4
TIM5_CH4
SAI_CK1
-
-
-
USART2_
RX
-
TIM15_C
H2
QUADSPI_C
LK
-
LPUART1_RX
SAI_MCLK_A
-
EVENT
OUT
PA4
-
-
TIM3_CH2
-
-
SPI1_NSS
SPI3_NSS/I
2S3_WS
USART2_
CK
-
-
-
-
-
SAI_FS_B
-
EVENT
OUT
PA5
-
TIM2_CH1
TIM2_ETR
-
-
SPI1_SCK
-
-
-
-
-
-
-
-
UCPD_
FRSTX
EVENT
OUT
PA6
-
TIM16_CH1
TIM3_CH1
-
TIM8_
BKIN
SPI1_MISO
TIM1_BKIN
-
COMP1
_OUT
-
QUADSPI_B
K1_IO3
-
LPUART1_
CTS
-
-
EVENT
OUT
PA7
-
TIM17_CH1
TIM3_CH2
-
TIM8_
CH1N
SPI1_MOSI
TIM1_CH1
N
-
COMP2_
OUT
-
QUADSPI_B
K1_IO2
-
-
-
UCPD_
FRSTX
EVENT
OUT
PA8
MCO
-
-
-
I2C2_
SMBA
I2S2_MCK
TIM1_CH1
USART1_
CK
COMP7
_OUT
-
TIM4_ETR
CAN3_
RX
SAI_CK2
-
SAI_SCK
_A
EVENT
OUT
PA9
-
-
I2C3_SMBA
-
I2C2_
SCL
I2S3_MCK
TIM1_CH2
USART1_
TX
COMP5
_OUT
TIM15_B
KIN
TIM2_CH3
CAN1_
RXFD
-
-
SAI_FS_
A
EVENT
OUT
PA10
-
TIM17_BKIN
I2C3_SCL
USB_CRS_
SYNC
I2C2_
SDA
SPI2_MISO
TIM1_CH3
USART1_
RX
COMP6
_OUT
CAN1_T
XFD
TIM2_CH4
TIM8_
BKIN
SAI_D1
-
SAI_SD_
A
EVENT
OUT
PA11
-
-
-
-
-
SPI2_MOSI/I
2S2_SD
TIM1_CH1
N
USART1_
CTS
COMP1
_OUT
CAN1_
RX
TIM4_CH1
TIM1_CH
4
TIM1_BKIN2
-
-
EVENT
OUT
PA12
-
TIM16_CH1
-
-
-
I2SCKIN
TIM1_CH2
N
USART1_
RTS_DE
COMP2
_OUT
CAN1_
TX
TIM4_CH2
TIM1_
ETR
-
-
-
EVENT
OUT
PA13
SWDIOJTMS
TIM16_CH1N
-
-
-
IR_OUT
-
USART3_
CTS
-
-
TIM4_CH3
-
-
SAI_SD_B
-
EVENT
OUT
PA14
SWCLKJTCK
LPTIM1_OUT
-
I2C4_SMBA
I2C1_
SDA
TIM8_CH2
TIM1_
BKIN
USART2_
TX
-
-
-
CAN3_
TXFD
-
SAI_FS_B
-
EVENT
OUT
PA15
JTDI
TIM2_CH1
TIM8_CH1
-
I2C1_
SCL
SPI1_NSS
SPI3_NSS/I
2S3_WS
USART2_
RX
UART4
_RTS_DE
TIM1_
BKIN
-
CAN3_
TX
-
-
TIM2_ET
R
EVENT
OUT
Port
Port A
DS12997 Rev 4
71/230
Pinouts and pin description
AF0
STM32G483xE
4.11
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PB0
-
-
TIM3_CH3
-
TIM8_
CH2N
-
TIM1_CH2
N
-
-
-
QUADSPI_B
K1_IO1
-
-
-
UCPD_
FRSTX
EVENT
OUT
PB1
-
-
TIM3_CH4
-
TIM8_
CH3N
-
TIM1_CH3
N
-
COMP4_O
UT
-
QUADSPI_B
K1_IO0
-
LPUART1_RTS
_DE
-
-
EVENT
OUT
PB2
-
LPTIM1_OUT
TIM5_CH1
TIM20_CH1
I2C3_
SMBA
-
-
-
-
-
QUADSPI_B
K2_IO1
-
-
-
-
EVENT
OUT
PB3
JTDOTRACESWO
TIM2_CH2
TIM4_ETR
USB_CRS_SYN
C
TIM8_
CH1N
SPI1_SCK
SPI3_SCK/I
2S3_CK
USART2_TX
-
-
TIM3_ETR
CAN3_R
X
-
-
SAI_SCK
_B
EVENT
OUT
PB4
JTRST
TIM16_CH1
TIM3_CH1
-
TIM8_
CH2N
SPI1_MISO
SPI3_MISO
USART2_R
X
UART5_RT
S_DE
-
TIM17_BKIN
CAN3_T
X
-
-
SAI_MCL
K_B
EVENT
OUT
PB5
-
TIM16_BKIN
TIM3_CH2
TIM8_CH3N
I2C1_
SMBA
SPI1_MOSI
SPI3_MOSI
/I2S3_SD
USART2_C
K
I2C3_SDA
CAN2_R
X
TIM17_CH1
LPTIM1_I
N1
SAI_SD_B
-
UART5_
CTS
EVENT
OUT
PB6
-
TIM16_CH1N
TIM4_CH1
-
-
TIM8_CH1
TIM8_ETR
USART1_TX
COMP4_O
UT
CAN2_T
X
TIM8_BKIN2
LPTIM1_
ETR
-
-
SAI_FS_
B
EVENT
OUT
PB7
-
TIM17_CH1N
TIM4_CH2
I2C4_SDA
I2C1_
SDA
TIM8_BKIN
-
USART1_R
X
COMP3_O
UT
CAN2_T
XFD
TIM3_CH4
LPTIM1_I
N2
FMC_NL
-
UART4_
CTS
EVENT
OUT
PB8
-
TIM16_CH1
TIM4_CH3
SAI_CK1
I2C1_
SCL
-
-
USART3_R
X
COMP1_O
UT
CAN1_R
X
TIM8_CH2
-
TIM1_BKIN
-
SAI_MCL
K_A
EVENT
OUT
PB9
-
TIM17_CH1
TIM4_CH4
SAI_D2
I2C1_
SDA
-
IR_OUT
USART3_TX
COMP2_O
UT
CAN1_T
X
TIM8_CH3
-
TIM1_CH3N
-
SAI_FS_
A
EVENT
OUT
PB10
-
TIM2_CH3
-
-
-
-
-
USART3_TX
LPUART1_
RX
-
QUADSPI_C
LK
CAN3_T
XFD
TIM1_BKIN
-
SAI_SCK
_A
EVENT
OUT
PB11
-
TIM2_CH4
-
-
-
-
-
USART3_R
X
LPUART1_
TX
-
QUADSPI_B
K1_NCS
CAN3_R
XFD
-
-
-
EVENT
OUT
PB12
-
-
TIM5_ETR
-
I2C2_
SMBA
SPI2_NSS/I2
S2_WS
TIM1_BKIN
USART3_C
K
LPUART1_
RTS_DE
CAN2_R
X
-
-
-
-
-
EVENT
OUT
PB13
-
-
-
-
-
SPI2_SCK/I2
S2_CK
TIM1_CH1
N
USART3_CT
S
LPUART1_
CTS
CAN2_T
X
-
-
-
-
-
EVENT
OUT
PB14
-
TIM15_CH1
-
-
-
SPI2_MISO
TIM1_CH2
N
USART3_RT
S_DE
COMP4_O
UT
-
-
-
-
-
-
EVENT
OUT
PB15
RTC_REFIN
TIM15_CH2
TIM15_CH1N
COMP3_OUT
TIM1_
CH3N
SPI2_MOSI/I
2S2_SD
-
-
-
-
-
-
-
-
-
EVENT
OUT
DS12997 Rev 4
Port B
Port
STM32G483xE
AF0
Pinouts and pin description
72/230
Table 13. Alternate function (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PC0
-
LPTIM1_IN1
TIM1_CH1
-
-
-
-
-
LPUART1_
RX
-
-
-
-
-
-
EVENT
OUT
PC1
-
LPTIM1_OUT
TIM1_CH2
-
-
-
-
-
LPUART1_
TX
-
QUADSPI_
BK2_IO0
-
-
SAI_SD_A
-
EVENT
OUT
PC2
-
LPTIM1_IN2
TIM1_CH3
COMP3_OUT
-
-
TIM20_CH2
-
-
-
QUADSPI_
BK2_IO1
-
-
-
-
EVENT
OUT
PC3
-
LPTIM1_ETR
TIM1_CH4
SAI_D1
-
-
TIM1_BKIN
2
-
-
-
QUADSPI_
BK2_IO2
-
-
SAI_SD_A
-
EVENT
OUT
PC4
-
-
TIM1_ETR
-
I2C2_SC
L
-
-
USART1_TX
-
-
QUADSPI_
BK2_IO3
-
-
-
-
EVENT
OUT
PC5
-
-
TIM15_BKIN
SAI_D3
-
-
TIM1_CH4
N
USART1_R
X
-
-
-
-
-
-
-
EVENT
OUT
PC6
-
-
TIM3_CH1
-
TIM8_
CH1
-
I2S2_MCK
COMP6_OU
T
I2C4_SCL
-
-
-
-
-
-
EVENT
OUT
PC7
-
-
TIM3_CH2
-
TIM8_
CH2
-
I2S3_MCK
COMP5_OU
T
I2C4_SDA
-
-
-
-
-
-
EVENT
OUT
PC8
-
-
TIM3_CH3
-
TIM8_
CH3
-
TIM20_CH3
COMP7_OU
T
I2C3_SCL
-
-
-
-
-
-
EVENT
OUT
PC9
-
-
TIM3_CH4
-
TIM8_
CH4
I2SCKIN
TIM8_
BKIN2
-
I2C3_SDA
-
-
-
-
-
-
EVENT
OUT
PC10
-
-
-
-
TIM8_
CH1N
UART4_TX
SPI3_SCK/I
2S3_CK
USART3_TX
-
-
-
-
-
-
-
EVENT
OUT
PC11
-
-
-
-
TIM8_
CH2N
UART4_RX
SPI3_MISO
USART3_R
X
I2C3_SDA
-
-
-
-
-
-
EVENT
OUT
PC12
-
TIM5_CH2
-
-
TIM8_C
H3N
UART5_TX
SPI3_MOSI
/I2S3_SD
USART3_C
K
-
-
-
-
-
-
UCPD_
FRSTX
EVENT
OUT
PC13
-
-
TIM1_BKIN
-
TIM1_
CH1N
-
TIM8_CH4
N
-
-
-
-
-
-
-
-
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
DS12997 Rev 4
Port C
Port
73/230
Pinouts and pin description
AF0
STM32G483xE
Table 13. Alternate function (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PD0
-
-
-
-
-
-
TIM8_CH4
N
-
-
CAN1_R
X
-
-
FMC_D2
-
-
EVENT
OUT
PD1
-
-
-
-
TIM8_
CH4
-
TIM8_BKIN
2
-
-
CAN1_T
X
-
-
FMC_D3
-
-
EVENT
OUT
PD2
-
-
TIM3_ETR
-
TIM8_
BKIN
UART5_RX
-
-
-
-
-
-
-
-
-
EVENT
OUT
PD3
-
-
TIM2_CH1/TIM2
_ETR
-
-
-
-
USART2_CT
S
-
-
QUADSPI_B
K2_NCS
-
FMC_CLK
-
-
EVENT
OUT
PD4
-
-
TIM2_CH2
-
-
-
-
USART2_RT
S_DE
-
CAN1_R
XFD
QUADSPI_B
K2_IO0
-
FMC_NOE
-
-
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2_TX
-
CAN1_T
XFD
QUADSPI_B
K2_IO1
-
FMC_NWE
-
-
EVENT
OUT
PD6
-
-
TIM2_CH4
SAI_D1
-
-
-
USART2_
RX
-
CAN2_R
XFD
QUADSPI_B
K2_IO2
-
FMC_NWAIT
SAI_SD_A
-
EVENT
OUT
PD7
-
-
TIM2_CH3
-
-
-
-
USART2_
CK
-
-
QUADSPI_B
K2_IO3
-
FMC_NCE/FM
C_NE1
-
-
EVENT
OUT
PD8
-
-
-
-
-
-
-
USART3_TX
-
-
-
-
FMC_D13
-
-
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_
RX
-
CAN2_R
XFD
-
-
FMC_D14
-
-
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_
CK
-
CAN2_T
XFD
-
-
FMC_D15
-
-
EVENT
OUT
PD11
-
TIM5_ETR
-
-
I2C4_
SMBA
-
-
USART3_
CTS
-
-
-
-
FMC_A16
-
-
EVENT
OUT
PD12
-
-
TIM4_CH1
-
-
-
-
USART3_
RTS_DE
-
-
-
-
FMC_A17
-
-
EVENT
OUT
PD13
-
-
TIM4_CH2
-
-
-
-
-
-
-
-
-
FMC_A18
-
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
-
-
-
-
FMC_D0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
SPI2_NSS
-
-
-
-
-
FMC_D1
-
-
EVENT
OUT
DS12997 Rev 4
Port D
Port
STM32G483xE
AF0
Pinouts and pin description
74/230
Table 13. Alternate function (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PE0
-
-
TIM4_ETR
TIM20_CH4N
TIM16_
CH1
-
TIM20_ETR
USART1_
TX
-
CAN1_R
XFD
-
-
FMC_NBL0
-
-
EVENT
OUT
PE1
-
-
-
-
TIM17_
CH1
-
TIM20_CH4
USART1_
RX
-
CAN1_T
XFD
-
-
FMC_NBL1
-
-
EVENT
OUT
PE2
TRACECK
-
TIM3_CH1
SAI_CK1
-
SPI4_SCK
TIM20_CH1
-
-
-
-
-
FMC_A23
SAI_MCLK_A
-
EVENT
OUT
PE3
TRACED0
-
TIM3_CH2
-
-
SPI4_NSS
TIM20_CH2
-
-
-
-
-
FMC_A19
SAI_SD_B
-
EVENT
OUT
PE4
TRACED1
-
TIM3_CH3
SAI_D2
-
SPI4_NSS
TIM20_CH1
N
-
-
-
-
-
FMC_A20
SAI_FS_A
-
EVENT
OUT
PE5
TRACED2
-
TIM3_CH4
SAI_CK2
-
SPI4_MISO
TIM20_CH2
N
-
-
-
-
-
FMC_A21
SAI_SCK_A
-
EVENT
OUT
PE6
TRACED3
-
-
SAI_D1
-
SPI4_MOSI
TIM20_CH3
N
-
-
-
-
-
FMC_A22
SAI_SD_A
-
EVENT
OUT
PE7
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
FMC_D4
SAI_SD_B
-
EVENT
OUT
PE8
-
TIM5_CH3
TIM1_CH1N
-
-
-
-
-
-
-
-
-
FMC_D5
SAI_SCK_B
-
EVENT
OUT
PE9
-
TIM5_CH4
TIM1_CH1
-
-
-
-
-
-
-
-
-
FMC_D6
SAI_FS_B
-
EVENT
OUT
PE10
-
-
TIM1_CH2N
-
-
-
-
-
-
-
QUADSPI_
CLK
-
FMC_D7
SAI_MCLK_B
-
EVENT
OUT
PE11
-
-
TIM1_CH2
-
-
SPI4_NSS
-
-
-
-
QUADSPI_
BK1_NCS
-
FMC_D8
-
-
EVENT
OUT
PE12
-
-
TIM1_CH3N
-
-
SPI4_SCK
-
-
-
-
QUADSPI_
BK1_IO0
-
FMC_D9
-
-
EVENT
OUT
PE13
-
-
TIM1_CH3
-
-
SPI4_MISO
-
-
-
-
QUADSPI_
BK1_IO1
-
FMC_D10
-
-
EVENT
OUT
PE14
-
-
TIM1_CH4
-
-
SPI4_MOSI
TIM1_
BKIN2
-
-
-
QUADSPI_
BK1_IO2
-
FMC_D11
-
-
EVENT
OUT
PE15
-
-
TIM1_BKIN
-
-
-
TIM1_
CH4N
USART3_
RX
-
-
QUADSPI_
BK1_IO3
-
FMC_D12
-
-
EVENT
OUT
DS12997 Rev 4
Port E
Port
75/230
Pinouts and pin description
AF0
STM32G483xE
Table 13. Alternate function (continued)
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PF0
-
-
-
-
I2C2_
SDA
SPI2_NSS/I2
S2_WS
TIM1_CH3
N
-
-
-
-
-
-
-
-
EVENT
OUT
PF1
-
-
-
-
-
SPI2_SCK/I2
S2_CK
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF2
-
-
TIM20_CH3
-
I2C2_
SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
PF3
-
-
TIM20_CH4
-
I2C3_
SCL
-
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
PF4
-
-
COMP1_OUT
TIM20_CH1N
I2C3_
SDA
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
TIM20_CH2N
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
TIM5_ETR
TIM4_CH4
SAI_SD_B
I2C2_
SCL
-
TIM5_CH1
USART3_
RTS
-
-
QUADSPI_
BK1_IO3
-
-
-
-
EVENT
OUT
PF7
-
-
TIM20_BKIN
-
-
-
TIM5_CH2
-
-
-
QUADSPI_
BK1_IO2
-
FMC_A1
SAI_MCLK_B
-
EVENT
OUT
PF8
-
-
TIM20_BKIN2
-
-
-
TIM5_CH3
-
-
-
QUADSPI_
BK1_IO0
-
FMC_A24
SAI_SCK_B
-
EVENT
OUT
PF9
-
-
TIM20_BKIN
TIM15_CH1
-
SPI2_SCK
TIM5_CH4
-
-
-
QUADSPI_
BK1_IO1
-
FMC_A25
SAI_FS_B
-
EVENT
OUT
PF10
-
-
TIM20_BKIN2
TIM15_CH2
-
SPI2_SCK
-
-
-
-
QUADSPI_
CLK
-
FMC_A0
SAI_D3
-
EVENT
OUT
PF11
-
-
TIM20_ETR
-
-
-
-
-
-
-
-
-
FMC_NE4
-
-
EVENT
OUT
PF12
-
-
TIM20_CH1
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
PF13
-
-
TIM20_CH2
-
I2C4_
SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
PF14
-
-
TIM20_CH3
-
I2C4_
SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
PF15
-
-
TIM20_CH4
-
I2C4_
SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
DS12997 Rev 4
Port F
Port
STM32G483xE
AF0
Pinouts and pin description
76/230
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS_AF
LPTIM1/
TIM2/5/
15/16/17
I2C3/
TIM1/2/3/4/5/8/1
5/20/
GPCOMP1
QUADSPI/
I2C3/4/SAI/
USB/
TIM8/15/20/GPC
OMP3/
TSC
I2C1/2/3/
4/
TIM1/8/1
6/17
QUADSPI/SP
I1/2/3/4/I2S2/
3/
I2C4/
UART4/5/TIM
8/
Infrared
QUADSPI/S
PI2/3/
I2S2/3/
TIM1/5/8/20
/
Infrared
USART1/2/3
/CAN/
GPCOMP5/6
/7
I2C3/4/
UART4/5/L
PUART1/G
PCOMP1/2/
3/4/5/6/7
CAN/
TIM1/8/1
5/CAN1/2
QUADSPI/TI
M2/3/4/8/17
LPTIM1/
TIM1/8/C
AN1/3
SDIO/FMC/
LPUART1/
SAI
TIM1
SAI/OPAMP2
UART4/5/
SAI/
TIM2/15/
UCPD
EVENT
PG0
-
-
TIM20_CH1N
-
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
PG1
-
-
TIM20_CH2N
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
PG2
-
-
TIM20_CH3N
-
-
SPI1_SCK
-
-
-
-
-
-
FMC_A12
-
-
EVENT
OUT
PG3
-
-
TIM20_BKIN
-
I2C4_
SCL
SPI1_MISO
TIM20_CH4
N
-
-
-
-
-
FMC_A13
-
-
EVENT
OUT
PG4
-
-
TIM20_BKIN2
-
I2C4_
SDA
SPI1_MOSI
-
-
-
-
-
-
FMC_A14
-
-
EVENT
OUT
PG5
-
-
TIM20_ETR
-
-
SPI1_NSS
-
-
LPUART1_
CTS
-
-
-
FMC_A15
-
-
EVENT
OUT
PG6
-
-
TIM20_BKIN
-
I2C3_
SMBA
-
-
-
LPUART1_
RTS_DE
-
-
-
FMC_INT
-
-
EVENT
OUT
PG7
-
-
-
SAI_CK1
I2C3_
SCL
-
-
-
LPUART1_
TX
-
-
-
FMC_INT
SAI_MCLK_A
-
EVENT
OUT
PG8
-
-
-
-
I2C3_
SDA
-
-
-
LPUART1_
RX
-
-
-
FMC_NE3
-
-
EVENT
OUT
PG9
-
-
-
-
-
-
SPI3_SCK
USART1_TX
-
-
-
-
FMC_NCE/FM
C_NE2
-
TIM15_C
H1N
EVENT
OUT
PG10
MCO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS12997 Rev 4
Port G
Port
STM32G483xE
Table 13. Alternate function (continued)
Pinouts and pin description
77/230
Electrical characteristics
STM32G483xE
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 14.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 15.
Figure 14. Pin loading conditions
Figure 15. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
78/230
DS12997 Rev 4
MS19211V1
STM32G483xE
5.1.6
Electrical characteristics
Power supply scheme
Figure 16. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
OUT
n x 100 nF
GPIOs
IN
+1 x 4.7 μF
Level shifter
VDDIO
IO
logic
Kernel logic
(CPU, Digital
& Memories)
n x VSS
VDDA
VREF+
VREF
VREF+
10 nF
+1 μF
Reset block
Temp. sensor
PLL, HSI16, HSI48
VDDA
100 nF +1 μF
VREF-
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
Standby circuitry
(Wakeup logic,
IWDG)
VSSA
MS60206V1
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DS12997 Rev 4
79/230
194
Electrical characteristics
5.1.7
STM32G483xE
Current consumption measurement
Figure 17. Current consumption measurement
IDD_VBAT
IDD
IDDA
VBAT
VDD
VDDA
MS60200V1
The IDD_ALL parameters given in Table 21 to Table 25 represent the total MCU consumption
including the current supplying VDD, VDDA and VBAT.
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 14. Voltage characteristics(1)
Symbol
VDD - VSS
VIN(2)
|∆VDDx|
|VSSx-VSS|
Ratings
Min
Max
-0.3
4.0
Input voltage on FT_xxx pins except FT_c pins
VSS-0.3
min (VDD, VDDA)
+ 4.0(3)(4)
Input voltage on FT_c pins
VSS-0.3
5.5
Input voltage on TT_xx pins
VSS-0.3
4.0
Input voltage on any other pins
VSS-0.3
4.0
-
50
-
50
-
0.4
External main supply voltage (including VDD,
VDDA, VBAT and VREF+)
Variations between different VDDX power pins of
the same domain
Variations between all the different ground pins
VREF+-VDDA Allowed voltage difference for VREF+ > VDDA
(5)
Unit
V
mV
V
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
80/230
DS12997 Rev 4
STM32G483xE
Electrical characteristics
2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 15. Current characteristics
Symbol
Ratings
Max
∑IVDD
Total current into sum of all VDD power lines (source)(1)
150
∑IVSS
(sink)(1)
150
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
Total current out of sum of all VSS ground lines
(1)
100
(sink)(1)
100
Maximum current into each VDD power pin (source)
Maximum current out of each VSS ground pin
Output current sunk by any I/O and control pin except FT_f
20
Output current sunk by any FT_f pin
20
Output current sourced by any I/O and control pin
∑IIO(PIN)
Total output current sunk by sum of all I/Os and control
Unit
mA
20
pins(2)
100
Total output current sourced by sum of all I/Os and control pins(2)
IINJ(PIN)(3)
Injected current on FT_xxx, TT_xx, NRST pins
∑|IINJ(PIN)|
Total injected current (sum of all I/Os and control pins)(5)
100
-5/0(4)
±25
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DS12997 Rev 4
Value
Unit
–65 to +150
°C
150
°C
81/230
194
Electrical characteristics
STM32G483xE
5.3
Operating conditions
5.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
170
fPCLK1
Internal APB1 clock frequency
-
0
170
fPCLK2
Internal APB2 clock frequency
-
0
170
Standard operating voltage
-
1.71(1)
3.6
VDD
VDDA
Analog supply voltage
ADC or COMP used
1.62
DAC 1 MSPS or DAC 15 MSPS
1.71
OPAMP used
2.0
VREFBUF used
2.4
ADC, DAC, OPAMP, COMP,
VREFBUF not used
VBAT
VIN
Backup operating voltage
-
TA
TJ
Power dissipation
V
3.6
TT_xx
-0.3
VDD+0.3
FT_c
-0.3
5
-0.3
MIN(MIN(VDD,
VDDA)+3.6 V,
5.5 V)(2)(3)
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package.
Power dissipation is then calculated according ambient
temperature (TA) and maximum junction temperature (TJ) and
selected thermal resistance.
Ambient temperature for the
suffix 6 version
Maximum power dissipation
-40
85
Low-power dissipation(4)
-40
105
Ambient temperature for the
suffix 3 version
Maximum power dissipation
-40
125
Low-power dissipation(4)
-40
130
Suffix 6 version
-40
105
Suffix 3 version
-40
130
Junction temperature range
V
3.6
3.6
I/O input voltage
MHz
3.6
1.55
All I/O except TT_xx and FT_c
PD
0
Unit
V
V
mW
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10:
Thermal characteristics).
82/230
DS12997 Rev 4
°C
°C
STM32G483xE
5.3.2
Electrical characteristics
Operating conditions at power-up / power-down
The parameters given in Table 18 are derived from tests performed under the ambient
temperature condition summarized in Table 17.
Table 18. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
tVDD
Min
Max
0
∞
10
∞
0
∞
10
∞
-
VDD fall time rate
VDDA rise time rate
tVDDA
5.3.3
Conditions
-
VDDA fall time rate
Unit
µs/V
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under the ambient
temperature conditions summarized in Table 17: General operating conditions.
Table 19. Embedded reset and power control block characteristics
Symbol
tRSTTEMPO(2)
Parameter
Reset temporization after
BOR0 is detected
VBOR0(2)
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage
detector threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
Conditions(1)
Min
Typ
Max
Unit
-
250
400
μs
Rising edge
1.62
1.66
1.7
Falling edge
1.6
1.64
1.69
Rising edge
2.06
2.1
2.14
Falling edge
1.96
2
2.04
Rising edge
2.26
2.31
2.35
Falling edge
2.16
2.20
2.24
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
Rising edge
2.85
2.90
2.95
Falling edge
2.76
2.81
2.86
Rising edge
2.1
2.15
2.19
Falling edge
2
2.05
2.1
Rising edge
2.26
2.31
2.36
Falling edge
2.15
2.20
2.25
Rising edge
2.41
2.46
2.51
Falling edge
2.31
2.36
2.41
Rising edge
2.56
2.61
2.66
Falling edge
2.47
2.52
2.57
VDD rising
DS12997 Rev 4
V
V
V
V
V
V
V
V
V
83/230
194
Electrical characteristics
STM32G483xE
Table 19. Embedded reset and power control block characteristics (continued)
Conditions(1)
Min
Typ
Max
Rising edge
2.69
2.74
2.79
Falling edge
2.59
2.64
2.69
Rising edge
2.85
2.91
2.96
Falling edge
2.75
2.81
2.86
Rising edge
2.92
2.98
3.04
Falling edge
2.84
2.90
2.96
Hysteresis in
continuous
Hysteresis voltage of BORH0 mode
-
20
-
Hysteresis in
other mode
-
30
-
Symbol
Parameter
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst_BORH0
Unit
V
V
V
mV
Hysteresis voltage of BORH
(except BORH0) and PVD
-
-
100
-
mV
BOR(3) (except BOR0) and
IDD
(BOR_PVD)(2) PVD consumption from VDD
-
-
1.1
1.6
µA
Vhyst_BOR_PVD
VPVM1
VDDA peripheral voltage
monitoring (COMP/ADC)
Rising edge
1.61
1.65
1.69
Falling edge
1.6
1.64
1.68
VPVM2
VDDA peripheral voltage
monitoring (OPAMP/DAC)
Rising edge
1.78
1.82
1.86
Falling edge
1.77
1.81
1.85
V
V
Vhyst_PVM1
PVM1 hysteresis
-
-
10
-
mV
Vhyst_PVM2
PVM2 hysteresis
-
-
10
-
mV
-
-
2
-
µA
IDD
PVM1 and PVM2
(PVM1/PVM2)
consumption from VDD
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
84/230
DS12997 Rev 4
STM32G483xE
5.3.4
Electrical characteristics
Embedded voltage reference
The parameters given in Table 20 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions.
Table 20. Embedded internal voltage reference
Symbol
Parameter
VREFINT
Internal reference
voltage
Conditions
Min
Typ
–40 °C < TA < +130 °C 1.182 1.212
Max
Unit
1.232
V
ADC sampling time
when reading the
internal reference
voltage
-
4(2)
-
-
µs
Start time of reference
voltage buffer when
ADC is enable
-
-
8
12(2)
µs
VREFINT buffer
consumption from VDD
IDD(VREFINTBUF) when converted by
ADC
-
-
12.5
20(2)
µA
tS_vrefint
(1)
tstart_vrefint
∆VREFINT
Internal reference
voltage spread over
the temperature range
VDD = 3 V
-
5
7.5(2)
mV
TCoeff
Average temperature
coefficient
–40°C < TA < +130°C
-
30
50(2)
ppm/°C
ACoeff
Long term stability
1000 hours, T = 25°C
-
300
1000(2)
ppm
Average voltage
coefficient
3.0 V < VDD < 3.6 V
-
250
1200(2)
ppm/V
24
25
26
49
50
51
74
75
76
VDDCoeff
VREFINT_DIV1
1/4 reference voltage
VREFINT_DIV2
1/2 reference voltage
VREFINT_DIV3
3/4 reference voltage
-
%
VREFINT
1. The shortest sampling time is determined in the application by multiple iterations.
2. Guaranteed by design.
DS12997 Rev 4
85/230
194
Electrical characteristics
STM32G483xE
Figure 18. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40
-20
0
20
40
Mean
60
Min
80
100
120
°C
Max
MSv40169V2
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Figure 17: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “number of wait states according
to CPU clock (HCLK) frequency” available in the reference manual RM0440
"STM32G4 Series advanced Arm®-based 32-bit MCUs").
•
When the peripherals are enabled fPCLK = fHCLK
•
The voltage scaling Range 1 is adjusted to fHCLK frequency as follows:
–
Voltage Range 1 Boost mode for 150 MHz < fHCLK ≤ 170 MHz
–
Voltage Range 1 Normal mode for 26 MHz < fHCLK ≤ 150 MHz
The parameters given in Table 21 to Table 25 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
86/230
DS12997 Rev 4
STM32G483xE
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Condition
Symbol
Parameter
-
Typ
Voltage
scaling
Range 2
DS12997 Rev 4
IDD (Run)
Supply current
in Run mode
fHCLK = fHSE up to
Range 1
48 MHz included,
Boost
bypass mode PLL
mode
ON above 48
MHz all
peripherals
disable
Unit
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
26 MHz
3.65
3.85
4.45
5.1
6.45
4.40
6.60
11.0
16.0
22.0
16 MHz
2.30
2.55
3.1
3.8
5.15
3.00
5.00
9.00
14.9
21.0
8 MHz
1.25
1.50
2.05
2.8
4.1
2.00
3.6
7.70
13.0
19.0
4 MHz
0.75
0.955
1.5
2.3
3.6
1.40
3.00
7.00
12.0
19.0
2 MHz
0.47
0.69
1.25
2
3.35
0.990
2.60
6.70
12.0
19.0
1 MHz
0.34
0.55
1.1
1.9
3.2
0.830
2.50
6.50
12.0
18.0
100 KHz
0.22
0.43
0.98
1.75
3.1
0.690
2.30
6.30
11.0
18.0
170 MHz
29.50
29.5
31
32
34.5
31.0
35.0
42.0
48.0
56.0
150 MHz
24.50
26
27
28
30
26.0
28.0
34.0
44.0
47.0
120 MHz
19.50
20
20.5
21.5
23.5
21.0
23.0
32.0
38.0
43.0
80 MHz
13.00
13.5
14
15.5
17
15.0
17.0
25.0
30.0
37.0
72 MHz
12.00
12
13
14
15.5
13.0
16.0
23.0
29.0
36.0
64 MHz
10.50
11
11.5
12.5
14.5
12.0
14.0
21.0
27.0
34.0
48 MHz
7.90
8.2
9
9.7
11.5
9.10
13.0
19.0
25.0
32.0
32 MHz
5.40
5.65
6.4
7.2
8.85
6.50
9.60
15.0
21.0
29.0
24 MHz
4.10
4.35
5.1
5.95
7.6
5.20
8.00
14.0
20.0
28.0
16 MHz
2.80
3.1
3.8
4.7
6.3
4.30
6.40
12.0
18.0
26.0
mA
87/230
Electrical characteristics
Range 1
fHCLK
Max
Condition
Symbol
Parameter
-
Typ
Voltage
scaling
SYSCLK source is HSE
in bypass mode
all peripherals disable
Supply current
IDD (LPRun) in Low-power
run mode
SYSCLK source is HSI16
all peripherals disable
fHCLK
Max
Unit
DS12997 Rev 4
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
2 MHz
455
725
1350
2250
3800
1200
3200
8100 14000 22000
1 MHz
280
545
1200
2100
3600
1100
3000
7900 14000 22000
250 KHz
160
435
1100
2000
3500
840
2800
7700 14000 22000
62.5 KHz
130
405
1050
1950
3500
810
2700
7600 14000 22000
2 MHz
920
1200
1850
2750
4250
1900
3800
8700 15000 22000
1 MHz
780
1100
1700
2650
4150
1700
3700
8600 14000 22000
250 KHz
725
980
1600
2500
4050
1600
3600
8400 14000 22000
62.5 KHz
720
955
1600
2500
4000
1500
3500
8400 14000 22000
Electrical characteristics
88/230
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued)
µA
STM32G483xE
Conditions
Symbol
Parameter
-
Voltage
DS12997 Rev 4
IDD
(Run)
Supply
current in
Run mode
fHCLK
fHCLK = fHSE
up to 48MHz
Range 1
included,
bypass mode Boost mode
PLL ON
above 48
MHz all
peripherals
disable
Range 1
Unit
25°C
55°C
85°C
105°C 125°C
55°C
85°C
26 MHz
3.70
3.9
4.45
5.15
16 MHz
2.35
2.55
3.1
8 MHz
1.25
1.5
4 MHz
0.75
2 MHz
105°C 125°C
6.45
4.40
6.60
11.0
16.0
22.0
3.85
5.15
3.00
5.00
9.00
14.0
21.0
2.05
2.8
4.15
2.00
3.60
7.70
13.0
19.0
0.97
1.5
2.3
3.6
1.40
3.00
7.00
12.0
19.0
0.47
0.7
1.25
2.05
3.35
0.990
2.60
6.70
12.0
19.0
1 MHz
0.34
0.56
1.1
1.9
3.2
0.830
2.50
6.50
12.0
18.0
100 KHz
0.22
0.44
0.975
1.8
3.1
0.690
2.30
6.30
11.0
18.0
170 MHz
29.50
30
31
32
34.5
31.0
35.0
42.0
48.0
56.0
150 MHz
24.50
24.5
25.5
26.5
28.5
26.0
28.0
34.0
44.0
47.0
120 MHz
19.50
20
20.5
22
23.5
21.0
23.0
32.0
38.0
43.0
80 MHz
13.00
13.5
14.5
15.5
17
15.0
17.0
25.0
30.0
37.0
72 MHz
12.00
12.5
13
14
15.5
13.0
16.0
23.0
29.0
36.0
64 MHz
10.50
11
11.5
13
14.5
12.0
14.0
21.0
27.0
34.0
48 MHz
7.95
8.3
9
10
11.5
9.10
13.0
19.0
25.0
32.0
32 MHz
5.40
5.7
6.45
7.25
8.9
6.50
9.60
15.0
21.0
29.0
24 MHz
4.10
4.4
5.1
6
7.65
5.20
8.00
14.0
20.0
28.0
16 MHz
2.85
3.15
3.8
4.75
6.35
4.30
6.40
12.0
18.0
26.0
mA
89/230
Electrical characteristics
25°C
scaling
Range 2
Max(1)
Typ
STM32G483xE
Table 22. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
Conditions
Symbol
Parameter
-
IDD
(LPRun)
Supply
current in
Low-power
run mode
Voltage
fHCLK
SYSCLK source is HSI16
all peripherals disable
Unit
DS12997 Rev 4
25°C
55°C
85°C
105°C 125°C
25°C
55°C
85°C
105°C 125°C
2 MHz
450
725
1350
2250
3800
1200
3200
8100
14000 22000
1 MHz
270
575
1200
2150
3650
1100
3000
7900
14000 22000
250 KHz
185
460
1050
2000
3550
840
2800
7700
14000 22000
62.5 KHz
130
430
1050
2000
3500
810
2700
7600
14000 22000
2 MHz
970
1200
1850
2750
4300
1900
3800
8700
15000 22000
1 MHz
800
1100
1700
2650
4150
1700
3700
8600
14000 22000
250 KHz
680
990
1600
2550
4050
1600
3600
8400
14000 22000
62.5 KHz
695
965
1600
2500
4050
1500
3500
8400
14000 22000
scaling
SYSCLK source is HSE
in bypass mode
all peripherals disable
Max(1)
Typ
Electrical characteristics
90/230
Table 22. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) (continued)
µA
1. Guaranteed by characterization results, unless otherwise specified.
STM32G483xE
Symbol
Parameter
-
Voltage
DS12997 Rev 4
IDD(Run)
Supply
current in
Run mode
fHCLK = fHSE
up to 48MHz
included,
bypass mode
PLL ON
above 48
MHz all
peripherals
disable
fHCLK
Range 1
Boost
mode
Unit
25°C
55°C
85°C
25°C
55°C
85°C
26 MHz
3.35
3.55
4.1
4.95
6.45
4.00
6.20
11.0
15.0
22.0
16 MHz
2.15
2.35
2.9
3.7
5.25
3.10
4.70
8.70
14.0
20.0
8 MHz
1.15
1.35
1.9
2.7
4.2
1.90
3.50
7.50
13.0
19.0
4 MHz
0.69
0.855
1.4
2.2
3.7
1.30
2.90
6.90
12.0
19.0
2 MHz
0.43
0.595
1.15
1.95
3.45
0.960
2.60
6.60
12.0
18.0
1 MHz
0.30
0.47
1
1.8
3.3
0.810
2.40
6.40
12.0
18.0
100 KHz
0.19
0.355
0.89
1.7
3.2
0.680
2.30
6.30
11.0
18.0
170 MHz
26.00
26.5
27.5
28.5
30.5
28.0
32.0
39.0
45.0
53.0(2)
150 MHz
21.50
22
22.5
23.5
25.5
23.0
25.0
31.0
41.0
46.0(2)
120 MHz
17.50
17.5
18.5
19.5
21.5
19.0
21.0
30.0
36.0
41.0
80 MHz
11.50
12
12.5
13.5
15.5
13.0
15.0
23.0
29.0
35.0
72 MHz
10.50
11
11.5
12.5
14.5
12.0
14.0
21.0
27.0
34.0
64 MHz
9.45
9.7
10.5
11.5
13.5
11.0
13.0
20.0
26.0
33.0
48 MHz
7.25
7.5
8.2
9.25
11
8.10
12.0
17.0
23.0
31.0
32 MHz
4.90
5.15
5.85
6.9
8.7
6.00
8.90
15.0
21.0
29.0
24 MHz
3.75
4
4.7
5.7
7.5
4.80
7.50
13.0
19.0
27.0
16 MHz
2.60
2.85
3.5
4.5
6.3
4.00
6.10
12.0
18.0
26.0
scaling
Range 2
Max(1)
Typ
Conditions
105°C 125°C
105°C 125°C
STM32G483xE
Table 23. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1
mA
Range 1
Electrical characteristics
91/230
Conditions
Symbol
Parameter
-
IDD
(LPRun)
Supply
current in
Low-power
run mode
Voltage
fHCLK
SYSCLK source is HSI16
all peripherals disable
Unit
DS12997 Rev 4
25°C
55°C
85°C
105°C 125°C
25°C
55°C
85°C
105°C 125°C
2 MHz
365
570
1200
2150
3850
1200
3100
7900
14000 22000
1 MHz
240
425
1050
2000
3650
960
2900
7700
14000 22000
250 KHz
135
315
945
1850
3550
840
2800
7600
13000 22000
62.5 KHz
105
285
915
1850
3550
780
2700
7600
13000 22000
2 MHz
835
1050
1650
2600
4300
1800
3700
8600
14000 22000
1 MHz
775
940
1550
2500
4150
1700
3600
8500
14000 22000
250 KHz
640
860
1450
2400
4100
1500
3500
8400
14000 22000
62.5 KHz
640
830
1450
2350
4050
1600
3500
8400
14000 22000
scaling
SYSCLK source is HSE
in bypass mode
all peripherals disable
Max(1)
Typ
Electrical characteristics
92/230
Table 23. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 (continued)
µA
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
STM32G483xE
Typ
Typ
Typ
Typ
Single Bank
Mode
Dual Bank
Mode
Single Bank
Mode
Dual Bank
Mode
25°C
25°C
25°C
25°C
Reduced
code(1)
3.65
3.7
140
142
Coremark
3.65
3.7
140
142
140
142
Conditions
Symbol
Parameter
Code
-
Voltage scaling
Range2
fHCLK=26MHz
DS12997 Rev 4
IDD
(Run)
Supply
current in
Run mode
fHCLK=fHSE
up to 48 MHZ
included, bypass
mode PLL ON
above 48 MHz all
peripherals
disable
Unit
mA
Dhrystone2.1
3.65
3.7
Fibonacci
4.55
4.2
175
162
While(1)
2.90
3
112
115
Reduced
code(1)
24.5
24.5
163
163
24
24
160
160
163
163
Coremark
Range 1
fHCLK= 150 MHz Dhrystone2.1
mA
24.5
Fibonacci
22.5
28
150
187
While(1)
19.5
20
130
133
Reduced
code(1)
29.5
29.5
174
174
29
29
171
171
174
174
Coremark
Range 1
Boost mode
Dhrystone2.1
fHCLK= 170 MHz
Fibonacci
While(1)
mA
29.5
29.5
38
35
224
206
23.5
24
138
141
µA/MHz
µA/MHz
µA/MHz
93/230
Electrical characteristics
24.5
Unit
STM32G483xE
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
Typ
Typ
Single Bank
Mode
Dual Bank
Mode
25°C
Reduced
code(1)
Coremark
Conditions
Symbol
Parameter
Code
-
IDD
(LPRun)
Supply
current in
Low-power
run
Voltage scaling
SYSCLK source is HSI16
fHCLK = 2 MHz
all peripherals disable
Typ
Typ
Single Bank
Mode
Dual Bank
Mode
25°C
25°C
25°C
920
970
460
485
905
985
453
493
458
458
Unit
µA
Dhrystone2.1
915
915
Fibonacci
1,050
950
525
475
While(1)
930
875
465
438
Unit
Electrical characteristics
94/230
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) (continued)
µA/MHz
DS12997 Rev 4
1. Reduced code used for characterization results provided in Table 21, Table 23.
STM32G483xE
Conditions
Symbol
Parameter
-
Typ
Voltage
scaling
Range2
fHCLK=26 M
Hz
Code
DS12997 Rev 4
IDD (Run)
3.25
125
Coremark
3.35
129
Dhrystone2.1
3.30
Fibonacci
3.30
127
While(1)
3.40
131
21.50
143
Coremark
22.50
150
Dhrystone2.1
21.50
Fibonacci
22.50
150
While(1)
20.00
133
26.00
153
Coremark
27.00
159
Dhrystone2.1
26.00
Fibonacci
27.50
162
While(1)
24.50
144
955
478
Supply current in fHCLK = fHSE = 2 MHz
all peripherals disable
Low-power run
Coremark
890
445
Dhrystone2.1
915
Fibonacci
880
440
While(1)
905
453
95/230
1. Reduced code used for characterization results provided in Table 21, Table 23.
code(1)
code(1)
code(1)
mA
mA
mA
µA
127
143
153
458
µA/MHz
µA/MHz
µA/MHz
µA/MHz
Electrical characteristics
Reduced code(1)
Reduced
IDD
(LPRun)
Unit
25°C
Reduced
Range 1
Boost mode
fHCLK=
170 MHz
Unit
25°C
Reduced
fHCLK = fHSE up to 48 MHZ
Range 1
Supply current in included, bypass mode
f
= 150
PLL ON above 48 MHz all HCLK
Run mode
MHz
peripherals disable
Typ
STM32G483xE
Table 25. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Conditions
Symbol
Parameter
-
Typ
Voltage
scaling
Range2
fHCLK=26 M
Hz
Reduced code(1)
2.65
102
Coremark
2.80
108
Dhrystone2.1
2.65
Fibonacci
2.60
100
While(1)
2.45
94
17.50
117
Coremark
18.00
120
DS12997 Rev 4
IDD (Run)
Dhrystone2.1
17.50
Fibonacci
17.00
113
16
107
21.00
124
Coremark
22.00
129
Dhrystone2.1
21.00
Fibonacci
20.50
121
While(1)
19.50
115
890
445
Coremark
830
415
Dhrystone2.1
825
Fibonacci
830
415
While(1)
815
408
While(1)
(1)
Reduced code
Range 1
Boost mode
fHCLK=
170 MHz
Reduced
IDD
(LPRun)
SYSCLK source is HSI16
Supply current in
FHCLK = 2MHz
Low-power run
all peripherals disable
1. Reduced code used for characterization results provided in Table 21, Table 23.
code(1)
mA
mA
mA
µA
102
117
124
413
Unit
µA/MHz
µA/MHz
µA/MHz
µA/MHz
STM32G483xE
Single bank
mode
code(1)
Unit
Single
bank
mode
fHCLK
Reduced
fHCLK = fHSE up to 48 MHZ
Range 1
Supply current in included, bypass mode
= 150
f
PLL ON above 48 MHz all HCLK
Run mode
MHz
peripherals disable
Typ
Electrical characteristics
96/230
Table 26. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2
Conditions
Symbol
Parameter
-
Typ
Voltage
scaling
Range2
fHCLK=26 M
Hz
fHCLK
Single bank
mode
Coremark
2.85
110
Dhrystone2.1
2.75
Fibonacci
2.95
113
2.60
100
18.00
120
Coremark
18.50
123
Dhrystone2.1
18.00
Fibonacci
19.00
127
While(1)
17.00
113
Reduced code(1)
22.00
129
Coremark
22.50
132
Dhrystone2.1
22.00
Fibonacci
23.50
138
20.50
121
900
450
Coremark
850
425
Dhrystone2.1
870
Fibonacci
850
425
While(1)
810
405
DS12997 Rev 4
While(1)
(1)
Reduced code
IDD
(LPRun)
SYSCLK source is HSI16
Supply current in
FHCLK = 2MHz
Low-power run
all peripherals disable
mA
mA
mA
µA
106
120
129
435
Unit
µA/MHz
µA/MHz
µA/MHz
µA/MHz
97/230
Electrical characteristics
106
Reduced code
Range 1
Boost mode
fHCLK=
170 MHz
Single
bank
mode
2.75
(1)
IDD (Run)
Unit
Reduced code(1)
While(1)
fHCLK = fHSE up to 48 MHZ
Range 1
Supply current in included, bypass mode
= 150
f
PLL ON above 48 MHz all HCLK
Run mode
MHz
peripherals disable
Typ
STM32G483xE
Table 27. Typical current consumption in Run and Low-power run modes, with different codes
running from CCMSRAM
Table 28. Current consumption in Sleep and Low-power sleep mode Flash ON
Typ
Condition
Symbol
Parameter
-
Voltage
scaling
Range 2
DS12997 Rev 4
IDD (Sleep)
Supply current
in sleep mode
fHCLK
Unit
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
26 MHz
0.98
1.1
1.75
2.4
3.75
1.90
3.50
7.60
13.0
19.0
16 MHz
0.67
0.835
1.45
2.15
3.5
1.50
3.00
7.10
12.0
19.0
8 MHz
0.44
0.605
1.25
2
3.35
1.10
2.70
6.70
12.0
19.0
4 MHz
0.33
0.5
1.1
1.9
3.25
0.860
2.50
6.50
12.0
18.0
2 MHz
0.27
0.445
1.05
1.85
3.2
0.760
2.40
6.40
11.0
18.0
1 MHz
0.24
0.415
1.05
1.8
3.15
0.720
2.30
6.40
11.0
18.0
100 KHz
0.21
0.385 0.995
1.8
3.1
0.670
2.30
6.30
11.0
18.0
6.60
6.95
7.8
8.9
10.5
8.00
12.0
18.0
24.0
33.0
5.50
5.8
6.55
7.55
9.25
6.40
9.50
15.0
21.0
29.0
4.50
4.75
5.5
6.55
8.2
5.40
8.20
14.0
20.0
28.0
80 MHz
3.15
3.45
4.2
5.15
6.8
4.50
6.60
12.0
18.0
26.0
72 MHz
2.85
3.15
3.9
4.9
6.55
4.20
6.30
12.0
18.0
26.0
64 MHz
2.60
2.9
3.65
4.6
6.3
3.50
6.00
12.0
18.0
26.0
48 MHz
1.90
2.2
3
3.65
5.3
3.20
5.30
11.0
17.0
25.0
32 MHz
1.40
1.65
2.4
3.2
4.85
2.70
4.80
11.0
17.0
25.0
24 MHz
1.10
1.35
2.1
3
4.65
2.30
4.50
9.80
16.0
25.0
16 MHz
0.83
1.1
1.85
2.75
4.35
1.90
4.10
9.40
16.0
24.0
Range 1
fHCLK = fHSE
Boost
170 MHz
up to 48 MHz
mode
included, bypass
mode PLL ON
150 MHz
above 48 MHz all
peripherals disable
120 MHz
Range 1
Max
Electrical characteristics
98/230
1. Reduced code used for characterization results provided in Table 21, Table 23.
mA
STM32G483xE
Condition
Symbol
Parameter
Typ
Voltage
scaling
-
SYSCLK source is HSE
in bypass mode
all peripherals disable
IDD
(LPSleep)
Supply current
in Low-power
sleep mode
SYSCLK source is HSI16
all peripherals disable
fHCLK
Max
Unit
DS12997 Rev 4
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
2 MHz
205
430
1150
2050
3600
1600
2900
7800 14000 22000
1 MHz
165
400
1100
2000
3550
1100
2900
7700 14000 22000
250 KHz
145
370
1100
2000
3550
820
2800
7700 13000 22000
62.5 KHz
140
365
1050
2000
3550
810
2800
7700 13000 22000
2 MHz
700
925
1650
2550
4100
1600
3600
8400 14000 22000
1 MHz
710
925
1600
2550
4100
1600
3600
8400 14000 22000
250 KHz
670
910
1600
2500
4050
1600
3600
8400 14000 22000
62.5 KHz
685
910
1600
2500
4050
1600
3600
8400 14000 22000
STM32G483xE
Table 28. Current consumption in Sleep and Low-power sleep mode Flash ON (continued)
μA
μA
Table 29. Current consumption in low-power sleep modes, Flash in power-down
Condition
Symbol
Parameter
-
Voltage
scaling
IDD
(LPSleep)
Supply current
in low-power
sleep mode
SYSCLK source is HSI16
all peripherals disable
fHCLK
Max
Unit
99/230
25°C
55°C
85°C 105°C 125°C 25°C
55°C
85°C 105°C 125°C
2 MHz
210
385
1150
2050
3550
910
2900
7800 14000 22000
1 MHz
150
360
1100
2000
3550
860
2900
7700 14000 22000
250 KHz
120
330
1050
2000
3500
820
2700
7600 13000 21000
62.5 KHz
110
330
1050
1950
3500
810
2700
7600 13000 21000
2 MHz
675
900
1600
2500
4050
1600
3600
8500 14000 22000
1 MHz
695
890
1600
2500
4050
1600
3600
8400 14000 22000
250 KHz
640
885
1600
2500
4050
1600
3600
8500 14000 22000
62.5 KHz
690
880
1600
2500
4050
1400
3000
7000 12000 19000
μA
Electrical characteristics
SYSCLK source is HSE
in bypass mode
all peripherals disable
Typ
Symbol
Parameter
Conditions
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
1.8 V
80
250
830
1550
2850
630
2100
5900
11000
18000
2.4 V
80
250
835
1600
2850
640
2100
5900
11000
18000
3.0 V
80.5
255
840
1600
2900
640
2200
6000
11000
18000
3.6 V
81.5
255
845
1600
2900
640
2200
6000
11000
18000
1.8 V
80.5
255
830
1550
2850
640
2100
5900
11000
18000
2.4 V
81
255
835
1600
2850
640
2200
5900
11000
18000
3.0 V
81.5
255
835
1600
2850
640
2200
6000
11000
18000
3.6 V
82
255
845
1600
2900
650
2200
6000
11000
18000
1.8 V
80
255
830
1550
2850
-
-
-
-
-
2.4 V
80.5
255
830
1600
2850
-
-
-
-
-
3.0 V
81.5
255
835
1600
2900
-
-
-
-
-
3.6 V
83
260
845
1600
2900
-
-
-
-
-
1.8 V
83.5
220
655
1300
-
-
-
-
-
-
2.4 V
84
220
660
1300
-
-
-
-
-
-
3.0 V
84.5
220
660
1300
-
-
-
-
-
-
3.6 V
87
220
660
1300
-
-
-
-
-
-
Wakeup clock is HSI6,
voltage Range 1
3.0 V
1.73
-
-
-
-
-
-
-
-
-
Wakeup clock is
HSI6 = 4 MHz,
(HPRE = 4),
voltage Range 2
3.0 V
-
Supply current
IDD
in Stop 1
RTC disabled
(Stop 1) mode, RTC
disabled
RTC clocked by LSI
DS12997 Rev 4
IDD
(Stop 1
with
RTC)
Supply current
RTC clocked by LSE
in Stop 1
mode, RTC bypassed at 32768 Hz
enabled
RTC clocked by LSE
quartz in low drive mode
at 32768 Hz
IDD
(wakeu
p from
Stop 1
Supply current
during wakeup
from
Stop 1 mode
Max(1)
Typ
Unit
Electrical characteristics
100/230
Table 30. Current consumption in Stop 1 mode
µA
mA
1.29
-
-
-
-
-
-
-
-
STM32G483xE
1. Guaranteed by characterization results, unless otherwise specified.
-
Conditions
Symbol
Parameter
-
IDD(Stop 0)
Supply current
in Stop 0 mode, RTC disabled
Max(1)
Typ
Unit
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
1.8 V
190
380
980
1750
3100
790
2400
6500
11000
19000
2.4 V
190
380
985
1750
3100
790
2400
6400
11000
19000
3V
190
380
985
1750
3100
800
2400
6500
12000
19000
3.6 V
190
380
985
1750
3100
800
2500
6500
12000
12000
STM32G483xE
Table 31. Current consumption in Stop 0 mode
µA
1. Guaranteed by characterization results, unless otherwise specified.
Table 32. Current consumption in Standby mode
Conditions
DS12997 Rev 4
Symbol
Parameter
-
IDD
(Standby)
Supply current in Standby
mode (backup registers
retained),
RTC disabled
No
independent
watchdog
With
independent
watchdog
Max(1)
Typ
Unit
25°C
55°C
85°C
105°C 125°C 25°C 55°C 85°C 105°C
125°C
1.8 V
100
275
1350
3450
8450
200
1100 4100
9700
27000
2.4 V
110
325
1600
4100
10000
220
1200 4800 12000
31000
3V
130
385
1900
4850
12000
240
1400 5500 13000
35000
3.6 V
180
530
2400
6050
14500
360
1700 6300 15000
40000
1.8 V
300
-
-
-
-
-
-
-
-
-
2.4 V
365
-
-
-
-
-
-
-
-
-
3V
435
-
-
-
-
-
-
-
-
-
3.6 V
545
-
-
-
-
-
-
-
-
-
nA
101/230
Electrical characteristics
VDD
Conditions
Symbol
Parameter
RTC clocked
by LSI, no
independent
watchdog
Supply current in Standby
mode (backup registers
(Standby with retained),
RTC)
RTC enabled
IDD
RTC clocked
by LSI, with
independent
watchdog
DS12997 Rev 4
RTC clocked
by LSE
bypassed at
32768 Hz
RTC clocked
by LSE
quartz(2) in
low drive
mode
IDD
(SRAM2)(3)
Unit
VDD
25°C
55°C
85°C
105°C 125°C 25°C 55°C 85°C 105°C
125°C
1.8 V
540
725
1800
3850
8850
660
1500 4600 11000
27000
2.4 V
700
920
2150
4650
10500
860
1900 5300 12000
31000
3V
885
1150
2650
5550
12500 1100 2200 6300 14000
36000
3.6 V
1100
1450
3350
7000
15500 1400 2700 7400 16000
41000
1.8 V
580
-
-
-
-
-
-
-
-
-
2.4 V
760
-
-
-
-
-
-
-
-
-
3V
960
-
-
-
-
-
-
-
-
-
3.6 V
1200
-
-
-
-
-
-
-
-
-
1.8 V
410
580
1600
3650
8600
-
-
-
-
-
2.4 V
545
750
1950
4450
10500
-
-
-
-
-
3V
830
1150
2750
5800
13000
-
-
-
-
-
3.6 V
2200
3050
5550
9550
18000
-
-
-
-
-
1.8 V
370
570
1350
3150
7100
-
-
-
-
-
2.4 V
495
715
1650
3800
8350
-
-
-
-
-
3V
655
915
2100
4550
9850
-
-
-
-
-
3.6 V
875
1350
2800
5750
12000
-
-
-
-
-
1.8 V
300
825
2950
6300
12550
-
-
-
-
-
2.4 V
305
875
2900
6400
12500
-
-
-
-
-
3V
305
865
2950
6150
12500
-
-
-
-
-
3.6 V
310
870
3000
6450
13000
-
-
-
-
-
nA
nA
nA
STM32G483xE
Supply current to be added in
Standby mode when SRAM2 is retained
Max(1)
Typ
Electrical characteristics
102/230
Table 32. Current consumption in Standby mode (continued)
Conditions
Symbol
Parameter
-
Unit
VDD
25°C
55°C
85°C
3V
2.46
-
-
Wakeup
Supply current during wakeup clock is
from Standby) from Standby mode
HSI16 =
16 MHz(4)
IDD (wakeup
Max(1)
Typ
105°C 125°C 25°C 55°C 85°C 105°C
-
-
-
-
-
-
125°C
-
STM32G483xE
Table 32. Current consumption in Standby mode (continued)
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is:
IIDD_ALL(Standby + RTC) + IDD_ALL(SRAM2).
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 36: Low-power mode wakeup timings.
Table 33. Current consumption in Shutdown mode
DS12997 Rev 4
Conditions
Symbol
Parameter
-
IDD
(Shutdown)
Supply current
in Shutdown
mode (backup
registers
retained) RTC
disabled
-
Max(1)
Typ
Unit
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
1.8 V
19
140
885
2500
6600
78.0
490
3100
8100
24000
2.4 V
28
180
1050
2950
7800
94.0
570
3600
9300
27000
3V
43
230
1300
3600
9300
130
680
4100
11000
31000
3.6 V
87
360
1750
4700
12000
190
870
4900
13000
35000
nA
Electrical characteristics
103/230
Conditions
Symbol
Parameter
Supply current
in Shutdown
IDD
mode (backup
(Shutdown with registers
RTC)
retained) RTC
enabled
DS12997 Rev 4
IDD(wakeup
from
Shutdown)
Supply current
during wakeup
from Shutdown
mode
Max(1)
Typ
Unit
-
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
RTC
clocked by
LSE
bypassed
at 32768
Hz
1.8 V
330
445
1150
2700
6800
-
-
-
-
-
2.4 V
460
605
1450
3350
8150
-
-
-
-
-
3V
745
1000
2200
4550
10500
-
-
-
-
-
3.6 V
2100
2850
4900
8150
15500
-
-
-
-
-
RTC
clocked by
LSE
quartz(2) in
low drive
mode
1.8 V
285
450
1050
2500
-
-
-
-
-
-
2.4 V
410
585
1300
3050
-
-
-
-
-
-
3V
565
770
1750
3750
-
-
-
-
-
-
3.6 V
780
1200
2400
4850
-
-
-
-
-
-
3V
1.6
-
-
-
-
-
-
-
-
-
Wakeup
clock is
HSI16 =
16 MHz(3)
Electrical characteristics
104/230
Table 33. Current consumption in Shutdown mode (continued)
nA
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 36: Low-power mode wakeup timings.
STM32G483xE
Conditions
Symbol
Parameter
-
RTC
disabled
IDD(VBAT)
Backup domain
supply current
RTC
enabled and
clocked by
LSE
bypassed at
32768 Hz
DS12997 Rev 4
RTC
enabled and
clocked by
LSE
quartz(2)
Max(1)
Typ
Unit
VBAT
25°C
55°C
85°C
105°C
125°C
25°C
55°C
85°C
105°C
125°C
1.8 V
4
17
92
245
600
-
-
-
-
-
2.4 V
5
20
105
280
690
-
-
-
-
-
3V
6
24
125
330
805
-
-
-
-
-
3.6 V
16
54
260
675
1650
-
-
-
-
-
1.8 V
310
315
350
470
-
-
-
-
-
-
2.4 V
435
440
500
665
-
-
-
-
-
-
3V
720
815
1050
1350
-
-
-
-
-
-
3.6 V
2150
2600
3400
4050
-
-
-
-
-
-
1.8 V
270
345
455
715
835
-
-
-
-
-
2.4 V
385
455
650
910
910
-
-
-
-
-
3V
525
600
910
1150
1000
-
-
-
-
-
3.6 V
710
995
1250
1700
1900
-
-
-
-
-
STM32G483xE
Table 34. Current consumption in VBAT mode
nA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics
105/230
Electrical characteristics
STM32G483xE
IO system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins
which should be configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This is done either by using pull-up/down resistors or by configuring the pins in
output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 36: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
106/230
DS12997 Rev 4
STM32G483xE
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 35. The MCU is placed
under the following conditions:
•
All I/O pins are in Analog mode
•
The given value is calculated by measuring the difference of the current consumptions:
–
when the peripheral is clocked on
–
when the peripheral is clocked off
•
Ambient operating temperature and supply voltage conditions summarized in Table 14:
Voltage characteristics
•
The power consumption of the digital part of the on-chip peripherals is given in
Table 35. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 35. Peripheral current consumption
Bus
-
AHB1
Peripheral
Range 1
Boost
mode
Range 1
Low-power
Normal Range 2
run and
mode
sleep
Bus Matrix
6.12
5.69
4.70
6.11
AHB1 to APB1 bridge
0.26
0.25
0.22
0.03
AHB1 to APB2 bridge
0.39
0.37
0.32
0.03
FSMC
10.21
9.52
7.87
10.28
QUADSPI
3.51
3.27
2.69
3.51
CORDIC
1.28
1.19
0.98
0.78
CRC
0.74
0.68
0.57
0.63
DMA 1
2.83
2.64
2.17
2.75
DMA 2
3.11
2.90
2.39
2.43
DMAMUX
6.71
6.26
5.17
6.68
SRAM1
0.58
0.54
0.44
0.54
FLASH
6.46
6.01
4.95
6.15
FMAC
4.59
4.29
3.57
3.83
DS12997 Rev 4
Unit
µA/MHz
µA/MHz
107/230
194
Electrical characteristics
STM32G483xE
Table 35. Peripheral current consumption (continued)
Bus
AHB2
108/230
Peripheral
Range 1
Boost
mode
Range 1
Low-power
Normal Range 2
run and
mode
sleep
ADC1/ADC2
6.24
5.80
4.77
5.88
ADC3/ADC4/ADC5
8.21
7.64
6.29
8.14
DAC1
4.70
4.38
3.63
4.40
DAC2
2.51
2.34
1.93
2.14
DAC3
4.62
4.31
3.57
4.15
DAC4
4.31
4.01
3.32
3.90
GPIOA
0.09
0.08
0.07
0.14
GPIOB
0.10
0.09
0.07
0.03
GPIOC
0.10
0.09
0.08
0.03
GPIOD
0.06
0.06
0.03
0.05
GPIOE
0.23
0.22
0.18
0.10
GPIOF
0.07
0.07
0.05
0.02
GPIOG
0.25
0.24
0.20
0.24
SRAM2
0.39
0.37
0.29
0.28
CCM SRAM
0.29
0.27
0.23
0.22
RNG
2.09
1.95
NA
NA
AES
2.84
2.64
2.19
2.43
DS12997 Rev 4
Unit
µA/MHz
STM32G483xE
Electrical characteristics
Table 35. Peripheral current consumption (continued)
Bus
APB1
Peripheral
Range 1
Boost
mode
Range 1
Low-power
Normal Range 2
run and
mode
sleep
CRS
0.74
0.68
0.57
0.51
FDCAN1/FDCAN2/FDCAN3
22.20
20.68
17.10
21.15
I2C1
1.29
1.20
0.99
1.28
I2C2
1.29
1.20
0.99
1.28
I2C3
1.25
1.17
0.96
1.56
I2C4
1.25
1.16
0.96
1.97
LPTIM1
1.11
1.03
0.85
1.42
LPUART1
1.91
1.78
1.47
2.03
PWR
0.71
0.65
0.53
0.53
RTC
2.64
2.46
2.07
3.26
SPI2/I2S2
4.05
3.77
3.11
4.16
SPI3/I2S3
4.08
3.81
3.13
4.49
TIM2
7.97
7.42
6.16
8.29
TIM3
6.37
5.93
4.92
6.81
TIM4
6.43
5.98
4.97
6.50
TIM5
8.28
7.71
6.38
8.11
TIM6
1.22
1.13
0.94
1.45
TIM7
1.28
1.18
0.98
1.56
UART4
2.51
2.33
1.92
3.14
UART5
2.79
2.60
2.14
3.34
USART2
2.75
2.56
2.12
3.11
USART3
2.71
2.52
2.08
2.47
USB
0.46
0.43
NA
NA
UCPD
2.46
2.28
1.89
NA
WWDG
0.42
0.39
0.31
0.42
DS12997 Rev 4
Unit
µA/MHz
109/230
194
Electrical characteristics
STM32G483xE
Table 35. Peripheral current consumption (continued)
Bus
APB2
110/230
Range 1
Boost
mode
Peripheral
Range 1
Low-power
Normal Range 2
run and
mode
sleep
SAI1
2.67
2.48
2.05
2.64
SPI1
1.99
1.86
1.54
2.02
SPI4
1.99
1.86
1.54
2.02
TIM1
10.85
10.13
8.40
9.93
TIM8
10.67
9.96
8.25
9.82
TIM15
4.81
4.48
3.71
4.57
TIM16
3.71
3.45
2.88
3.45
TIM17
3.66
3.41
2.83
3.81
TIM20
10.71
9.99
8.29
10.00
USART1
2.49
2.31
1.91
2.49
SYSCFG/COMP/OPAMP/VREFBUF
1.63
1.52
1.25
0.91
DS12997 Rev 4
Unit
µA/MHz
STM32G483xE
Electrical characteristics
Table 35. Peripheral current consumption (continued)
Bus
Independent
clock domain
All
Range 1
Boost
mode
Peripheral
Range 1
Low-power
Normal Range 2
run and
mode
sleep
ADC1/
ADC2
independent clock domain
0.72
0.67
0.53
0.63
ADC3/
ADC4/
ADC5
independent clock domain
0.67
0.62
0.50
0.22
FDCAN1/
FDCAN2/
FDCAN3
independent clock domain
11.62
10.84
8.95
10.24
I2C1
independent clock domain
4.03
3.76
3.12
4.15
I2C2
independent clock domain
3.78
3.52
2.93
3.23
I2C3
independent clock domain
2.72
2.55
2.11
2.65
I2C4
independent clock domain
3.95
3.67
3.04
2.81
I2S2
independent clock domain
1.49
1.40
1.15
1.63
I2S3
independent clock domain
1.52
1.43
1.16
2.15
LPTIM1
independent clock domain
4.00
3.71
3.08
3.57
LPUART1
independent clock domain
4.43
4.13
3.45
4.02
QUADSPI
independent clock domain
0.54
0.51
0.44
0.75
RNG
independent clock domain
0.83
0.87
NA
NA
USB
independent clock domain
1.10
1.17
NA
NA
SAI1
independent clock domain
3.36
3.14
2.58
3.25
UART4
independent clock domain
6.60
6.17
5.14
6.02
UART5
independent clock domain
6.60
6.16
5.12
6.12
USART1
independent clock domain
7.62
7.12
5.89
6.90
USART2
independent clock domain
7.37
6.86
5.70
6.72
USART3
independent clock domain
7.98
7.44
6.17
8.21
369.00
316.04
266.18
325.00
-
DS12997 Rev 4
Unit
µA/MHz
µA/MHz
111/230
194
Electrical characteristics
5.3.6
STM32G483xE
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 36 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
Table 36. Low-power mode wakeup timings(1)
Symbol
tWUSLEEP
Parameter
Conditions
Typ
Max
-
11
12
-
10
11
Wakeup time from Sleep
mode to Run mode
Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode
tWUSTOP0
tWUSTOP1
Wake up time from Stop 0
mode to Run mode in Flash
Range 1
Wakeup clock HSI16 = 16 MHz
5.8
6
Range 2
Wakeup clock HSI16 = 16 MHz
18.4
19.1
Wake up time from Stop 0
mode to Run mode in
SRAM1
Range 1
Wakeup clock HSI16 = 16 MHz
2.8
3
Range 2
Wakeup clock HSI16 = 16 MHz
2.9
3
Wake up time from Stop 1
mode to Run in Flash
Range 1
Wakeup clock HSI16 = 16 MHz
9.5
9.8
Range 2
Wakeup clock HSI16 = 16 MHz
21.9
22.7
Wake up time from Stop 1
mode to Run mode in
SRAM1
Range 1
Wakeup clock HSI16 = 16 MHz
6.6
6.9
Range 2
Wakeup clock HSI16 = 16 MHz
6.4
6.6
26.1
27.1(2)
Wake up time from Stop 1
mode to Low-power run
mode in Flash
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
Regulator in
Wakeup clock
low-power
HSI16 = 16 MHz,
mode (LPR=1 with HPRE = 8
in PWR_CR1)
14.4
15(2)
Wakeup time from Standby
mode to Run mode
Range 1
Wakeup clock HSI16 = 16 MHz
29.7
33.8
Wakeup time from Standby
with SRAM2 to Run mode
Range 1
Wakeup clock HSI16 = 16 MHz
29.7
33.5
tWUSHDN
Wakeup time from
Shutdown mode to Run
mode
Range 1
Wakeup clock HSI16 = 16 MHz 267.9 274.6(2)
tWULPRUN
Wakeup time from Lowpower run mode to Run
mode(3)
tWUSTBY
tWUSTBY
SRAM2
Wakeup clock HSI16 = 16 MHz
with HPRE = 8
1. Guaranteed by characterization results.
2. Characterization results for temperature range from 0°C to 125°C.
3. Time until REGLPF flag is cleared in PWR_SR2.
112/230
DS12997 Rev 4
5
7
Unit
Nb of
CPU
cycles
µs
STM32G483xE
Electrical characteristics
Table 37. Regulator modes transition times(1)
Symbol
tVOST
Parameter
Conditions
Regulator transition time from Range
2 to Range 1 or
Range 1 to Range 2(2)
Typ
Max
Unit
20
40
μs
Typ
Max
Unit
Stop 0 mode
-
1.7
Stop 1 mode
-
8.5
Wakeup clock HSI16 = 16 MHz
with HPRE = 8
1. Guaranteed by characterization results.
2. Time until VOSF flag is cleared in PWR_SR2.
Table 38. Wakeup time using USART/LPUART(1)
Symbol
tWUUSART
tWULPUART
Parameter
Conditions
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI16
μs
1. Guaranteed by design.
5.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 19: High-speed external clock
source AC timing diagram.
Table 39. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock
source frequency
Conditions
Min
Typ
Max
Voltage scaling
Range 1
-
8
48
Voltage scaling
Range 2
-
8
26
MHz
VHSEH
OSC_IN input pin high
level voltage
-
0.7 VDD
-
VDD
VHSEL
OSC_IN input pin low
level voltage
-
VSS
-
0.3 VDD
Voltage scaling
Range 1
7
-
-
Voltage scaling
Range 2
18
-
-
tw(HSEH)
tw(HSEL)
Unit
V
OSC_IN high or low time
ns
1. Guaranteed by design.
DS12997 Rev 4
113/230
194
Electrical characteristics
STM32G483xE
Figure 19. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
t
tw(HSEL)
THSE
MS19214V2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 20.
Table 40. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User external clock source
frequency
-
-
32.768
1000
VLSEH
OSC32_IN input pin high
level voltage
-
0.7 VDD
-
VDD
VLSEL
OSC32_IN input pin low level
voltage
-
VSS
-
0.3 VDD
-
250
-
-
V
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
ns
1. Guaranteed by design.
Figure 20. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
t
tw(LSEL)
TLSE
MS19215V2
114/230
DS12997 Rev 4
STM32G483xE
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 41. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 41. HSE oscillator characteristics(1)
Symbol
fOSC_IN
RF
Conditions(2)
Min
Typ
Max
Unit
Oscillator frequency
-
4
8
48
MHz
Feedback resistor
-
-
200
-
kΩ
-
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
0.44
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
-
0.45
-
VDD = 3 V,
Rm = 30 Ω,
CL = 5 pF@48 MHz
-
0.68
-
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
-
0.94
-
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
-
1.77
-
Startup
-
-
1.5
mA/V
VDD is stabilized
-
2
-
ms
Parameter
During startup
IDD(HSE)
Gm
HSE current consumption
Maximum critical crystal
transconductance
tSU(HSE)(4) Startup time
(3)
mA
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
DS12997 Rev 4
115/230
194
Electrical characteristics
Note:
STM32G483xE
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
8 MHz
resonator
CL2
REXT (1)
fHSE
RF
Bias
controlled
gain
OSC_OUT
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 42. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
116/230
DS12997 Rev 4
STM32G483xE
Electrical characteristics
Table 42. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
IDD(LSE)
Conditions(2)
Parameter
LSE current consumption
Maximum critical crystal
Gmcritmax
gm
tSU(LSE)(3) Startup time
Min
Typ
Max
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
315
-
LSEDRV[1:0] = 10
Medium high drive capability
-
500
-
LSEDRV[1:0] = 11
High drive capability
-
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
-
-
0.75
LSEDRV[1:0] = 10
Medium high drive capability
-
-
1.7
LSEDRV[1:0] = 11
High drive capability
-
-
2.7
VDD is stabilized
-
2
-
Unit
nA
µA/V
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3.
Note:
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
programmable
amplifier
32.768 kHz
resonator
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS12997 Rev 4
117/230
194
Electrical characteristics
5.3.8
STM32G483xE
Internal clock source characteristics
The parameters given in Table 43 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 43. HSI16 oscillator characteristics(1)
Symbol
fHSI16
TRIM
Parameter
HSI16 Frequency
HSI16 user trimming step
Conditions
Min
Typ
VDD=3.0 V, TA=30 °C
15.88
-
Trimming code is not a
multiple of 64
0.2
0.3
Trimming code is a
multiple of 64
-4
-6
-8
45
-
55
%
-1
-
1
%
-2
-
1.5
%
-0.1
-
0.05
%
DuCy(HSI16)(2) Duty Cycle
-
Unit
16.08 MHz
0.4
%
∆Temp(HSI16)
HSI16 oscillator frequency TA= 0 to 85 °C
drift over temperature
TA= -40 to 125 °C
∆VDD(HSI16)
HSI16 oscillator frequency
VDD=1.62 V to 3.6 V
drift over VDD
tsu(HSI16)(2)
HSI16 oscillator start-up
time
-
-
0.8
1.2
μs
tstab(HSI16)(2)
HSI16 oscillator
stabilization time
-
-
3
5
μs
IDD(HSI16)(2)
HSI16 oscillator power
consumption
-
-
155
190
μA
1. Guaranteed by characterization results.
2. Guaranteed by design.
118/230
Max
DS12997 Rev 4
STM32G483xE
Electrical characteristics
Figure 23. HSI16 frequency versus temperature
MHz
16.4
+2 %
16.3
+1.5 %
16.2
+1 %
16.1
16
15.9
-1 %
15.8
-1.5 %
15.7
-2 %
15.6
-40
-20
0
20
Mean
40
60
80
min
100
120 °C
max
MSv39299V2
High-speed internal 48 MHz (HSI48) RC oscillator
Table 44. HSI48 oscillator characteristics(1)
Symbol
fHSI48
TRIM
USER TRIM
COVERAGE
Parameter
HSI48 Frequency
Conditions
VDD=3.0V, TA=30°C
HSI48 user trimming step
HSI48 user trimming
coverage
±32 steps
DuCy(HSI48) Duty Cycle
-
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48
TA = –15 to 85 °C
ACCHSI48_REL oscillator over temperature
VDD = 1.65 V to 3.6 V,
(factory calibrated)
TA = –40 to 125 °C
DVDD(HSI48)
HSI48 oscillator frequency VDD = 3 V to 3.6 V
drift with VDD
VDD = 1.65 V to 3.6 V
Min
Typ
Max
Unit
-
48
-
MHz
-
0.11(2)
0.18(2)
%
±3(3)
±3.5(3)
-
%
45(2)
-
55(2)
%
-
-
±3(3)
-
-
±4.5(3)
-
0.025(3)
0.05(3)
-
0.05(3)
0.1(3)
%
%
tsu(HSI48)
HSI48 oscillator start-up
time
-
-
2.5(2)
6(2)
μs
IDD(HSI48)
HSI48 oscillator power
consumption
-
-
340(2)
380(2)
μA
DS12997 Rev 4
119/230
194
Electrical characteristics
STM32G483xE
Table 44. HSI48 oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NT jitter
Next transition jitter
Accumulated jitter on 28
cycles(4)
-
-
+/-0.15(2)
-
ns
PT jitter
Paired transition jitter
Accumulated jitter on 56
cycles(4)
-
-
+/-0.25(2)
-
ns
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 24. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
Avg
70
90
min
110
130
°C
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
Table 45. LSI oscillator characteristics(1)
Symbol
fLSI
tSU(LSI)(2)
120/230
Parameter
LSI Frequency
Conditions
Min
Typ
Max
VDD = 3.0 V,
TA = 30 °C
31.04
-
32.96
VDD = 1.62 to 3.6 V,
TA = -40 to 125 °C
29.5
-
34
-
80
130
LSI oscillator start-up
time
DS12997 Rev 4
-
Unit
kHz
μs
STM32G483xE
Electrical characteristics
Table 45. LSI oscillator characteristics(1) (continued)
Symbol
Parameter
tSTAB(LSI)(2)
IDD(LSI)(2)
Conditions
Min
Typ
Max
Unit
LSI oscillator stabilization
5% of final frequency
time
-
125
180
μs
LSI oscillator power
consumption
-
110
180
nA
-
1. Guaranteed by characterization results.
2. Guaranteed by design.
5.3.9
PLL characteristics
The parameters given in Table 46 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17: General operating conditions.
Table 46. PLL characteristics(1)
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock(2)
-
2.66
-
16
MHz
PLL input clock duty cycle
-
45
-
55
%
Voltage scaling Range 1
Boost mode
2.0645
-
170
Voltage scaling Range 1
2.0645
-
150
Voltage scaling Range 2
2.0645
-
26
Voltage scaling Range 1
Boost mode
8
-
170
Voltage scaling Range 1
8
-
150
Voltage scaling Range 2
8
-
26
Voltage scaling Range 1
Boost mode
8
-
170
Voltage scaling Range 1
8
-
150
Voltage scaling Range 2
8
-
26
Voltage scaling Range 1
96
-
344
Voltage scaling Range 2
96
-
128
-
-
15
40
-
28.6
-
-
21.4
-
VCO freq = 96 MHz
-
200
260
VCO freq = 192 MHz
-
300
380
VCO freq = 344 MHz
-
520
650
fPLL_P_OUT PLL multiplier output clock P
fPLL_Q_OUT PLL multiplier output clock Q
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT
tLOCK
Jitter
IDD(PLL)
PLL VCO output
PLL lock time
RMS cycle-to-cycle jitter
RMS period jitter
PLL power consumption on
VDD(1)
System clock 150 MHz
MHz
μs
±ps
μA
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock
values.
DS12997 Rev 4
121/230
194
Electrical characteristics
5.3.10
STM32G483xE
Flash memory characteristics
Table 47. Flash memory characteristics(1)
Symbol
Parameter
Conditions
Typ
Max
Unit
tprog
64-bit programming time
-
81.7
83.35
µs
tprog_row
One row (32 double
word) programming time
Normal programming
2.61
2.7
Fast programming
1.91
1.95
tprog_page
One page (2 Kbytes)
programming time
Normal programming
20.91
21.34
Fast programming
15.29
15.6
22.02
24.47
Normal programming
2.68
2.73
Fast programming
1.96
2
22.13
24.6
Write mode
3.5
-
Erase mode
3.5
-
Write mode
7 (for 6 µs)
-
Erase mode
7 (for 67 µs)
-
tERASE
Page (2 Kbytes) erase
time
tprog_bank
One bank (256 Kbyte)
programming time
tME
IDD
-
Mass erase time
(one or two banks)
-
Average consumption
from VDD
Maximum current (peak)
ms
s
ms
mA
1. Guaranteed by design.
Table 48. Flash memory endurance and data retention
Symbol
NEND
Parameter
Endurance
Conditions
TA = -40 to +105 °C
1
kcycle(2)
at TA = 85 °C
1 kcycle(2) at TA = 105 °C
tRET
Data retention
1 kcycle
10
(2)
at TA = 125 °C
kcycles(2)
Unit
10
kcycles
30
15
7
at TA = 55 °C
30
10 kcycles(2) at TA = 85 °C
15
10 kcycles(2) at TA = 105 °C
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
122/230
Min(1)
DS12997 Rev 4
Years
STM32G483xE
5.3.11
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 49. They are based on the EMS levels and classes
defined in application note AN1709.
Table 49. EMS characteristics
Conditions
Level/
Class
Symbol
Parameter
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-4
5A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
DS12997 Rev 4
123/230
194
Electrical characteristics
STM32G483xE
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 50. EMI characteristics
Symbol
SEMI
Parameter
Peak level
Monitored
frequency band
Conditions
Max vs. [fHSE/fHCLK]
0.1 MHz to 30 MHz
4
30 MHz to 130 MHz
VDD = 3.6 V, TA = 25 °C,
LQFP128 package
130 MHz to 1 GHz
compliant with IEC 61967-2
1 GHz to 2 GHz
0
EMI Level
5.3.12
Unit
8 MHz / 170 MHz
dBµV
16
11
3.5
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 51. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Electrostatic discharge
voltage (human body model)
Conditions
TA = +25 °C, conforming to
ANSI/ESDA/JEDEC JS-001
LQFP100 and
TA = +25 °C, conforming to LQFP128
Electrostatic discharge
ANSI/ESDA/JEDEC JSVESD(CDM)
voltage (charge device model)
Other
002
packages
1. Guaranteed by characterization results.
124/230
DS12997 Rev 4
Class
Maximum
Unit
value(1)
2
2000
C1
250
C2a
500
V
V
STM32G483xE
Electrical characteristics
Static latch-up
Two complementary static tests are required on three parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin.
•
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 52. Electrical sensitivities
Symbol
LU
5.3.13
Parameter
Static latch-up class
Conditions
Class
TA = +125 °C conforming to JESD78E
Class II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 53.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 53. I/O current injection susceptibility
Functional
susceptibility
Symbol
(1)
IINJ
Description
Injected current on pin
Unit
Negative
injection
Positive
injection
All except TT_a, PF10, PB8-BOOT0, PC10
-5
NA
PF10, PB8-BOOT0, PC10
-0
NA
TT_a pins
-5
0
mA
1. Guaranteed by characterization.
DS12997 Rev 4
125/230
194
Electrical characteristics
5.3.14
STM32G483xE
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 17: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 54. I/O static characteristics
Symbol Parameter
I/O input
VIL(1)(2) low level
voltage
I/O input
VIH(1)(2) high level
voltage
VHYS(3)
Input
hysteresis
Conditions
All except
FT_c
1.62 V
工商网监
湘ICP备2023018690号
