STM32G491RET6

STM32G491xC STM32G491xE Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS, up to 512 KB Flash, 112 KB SRAM, rich analog, math accelerator Datasheet - production data Features FBGA Includes ST state-of-the-art patented technology • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions • Operating conditions: – VDD, VDDA voltage range: 1.71 V to 3.6 V WLCSP64 (Pitch 0.4) • Up to 86 fast I/Os – All mappable on external interrupt vectors – Several I/Os with 5 V tolerant capability • 16-channel DMA controller • 3 x ADCs 0.25 µs (up to 36 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range • Memories – 512 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP – 96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes – Routine booster: 16 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) – Quad-SPI memory interface • Reset and supply management – Power-on/power-down reset (POR/PDR/BOR) – Programmable voltage detector (PVD) – Low-power modes: sleep, stop, standby and shutdown – VBAT supply for RTC and backup registers • Clock management – 4 to 48 MHz crystal oscillator – 32 kHz oscillator with calibration – Internal 16 MHz RC with PLL option (± 1%) – Internal 32 kHz RC oscillator (± 5%) This is information on a product in full production. UFBGA64 (5 x 5 mm) • Interconnect matrix • Mathematical hardware accelerators – CORDIC for trigonometric functions acceleration – FMAC: filter mathematical accelerator September 2021 LQFP48 (7 x 7 mm) UFQFPN32 (5 x 5 mm) LQFP64 (10 x 10 mm) UFQFPN48 (7 x 7 mm) LQFP80 (12 x 12 mm) LQFP80 (14 x 14 mm) LQFP100 (14 x 14 mm) • 4 x 12-bit DAC channels – 2 x buffered external channels 1 MSPS – 2 x unbuffered internal channels 15 MSPS • 4 x ultra-fast rail-to-rail analog comparators • 4 x operational amplifiers that can be used in PGA mode, all terminals accessible • Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.9 V) • 15 timers: – 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop – 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop – 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop – 2 x watchdog timers (independent, window) DS13122 Rev 3 1/199 www.st.com STM32G491xC STM32G491xE – 1 x SysTick timer: 24-bit downcounter – 2 x 16-bit basic timers – 1 x low-power timer • Calendar RTC with alarm, periodic wakeup from stop/standby – 3 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I2S interface – 1 x SAI (serial audio interface) – USB 2.0 full-speed interface with LPM and BCD support – IRTIM (infrared interface) – USB Type-C™ /USB power delivery controller (UCPD) • Communication interfaces – 2 x FDCAN controller supporting flexible data rate – 3 x I2C Fast mode plus (1 Mbit/s) with • True random number generator (RNG) 20 mA current sink, SMBus/PMBus, • CRC calculation unit, 96-bit unique ID wakeup from stop – 5 x USART/UARTs (ISO 7816 interface, • Development support: serial wire debug LIN, IrDA, modem control) (SWD), JTAG, Embedded Trace Macrocell™ – 1 x LPUART Table 1. Device summary Reference Part number STM32G491xC STM32G491CC, STM32G491KC, STM32G491RC, STM32G491VC, STM32G491MC STM32G491xE STM32G491CE, STM32G491KE, STM32G491RE, STM32G491VE, STM32G491ME 2/199 DS13122 Rev 3 STM32G491xC STM32G491xE Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21 3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18 3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28 3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DS13122 Rev 3 3/199 6 Contents STM32G491xC STM32G491xE 3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.4 Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 30 3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.24.1 Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 33 3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 36 3.26 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.27 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 Universal synchronous/asynchronous receiver transmitter (USART) . . . 39 3.30 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 40 3.31 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.32 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.32.1 4/199 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.33 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 42 3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.35 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 42 3.36 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.37 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.38 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.38.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.38.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DS13122 Rev 3 STM32G491xC STM32G491xE 4 5 Contents Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3 LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 WLCSP64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6 UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7 LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.8 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.9 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.10 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 74 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 74 5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 DS13122 Rev 3 5/199 6 Contents 6 STM32G491xC STM32G491xE 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 119 5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 120 5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 135 5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 142 5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 152 5.3.27 QUADSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.28 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.4 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.5 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.6 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.7 LQFP80 12 x 12 mm package information . . . . . . . . . . . . . . . . . . . . . . . 184 6.8 LQFP80 14 x 14 mm package information . . . . . . . . . . . . . . . . . . . . . . . 187 6.9 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 195 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6/199 DS13122 Rev 3 STM32G491xC STM32G491xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32G491xC/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32G491xC/xE peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SAI features implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32G491xC/xE pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 74 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 78 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 82 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical current consumption in Run and Low-power run modes, with different codes running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 86 Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 87 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DS13122 Rev 3 7/199 9 List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. 8/199 STM32G491xC STM32G491xE HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 131 ADC accuracy (Multiple ADCs operation) - limited test conditions 2 . . . . . . . . . . . . . . . . 132 ADC accuracy (Multiple ADCs operation) - limited test conditions 3 . . . . . . . . . . . . . . . . 133 DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 WLCSP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DS13122 Rev 3 STM32G491xC STM32G491xE Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. List of tables WLCSP64 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 UFBGA64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . 182 LQFP80 12 x 12 mm - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LQFP80 14 x 14 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 LQPF100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DS13122 Rev 3 9/199 9 List of figures STM32G491xC STM32G491xE List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 10/199 STM32G491xC/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32G491xC/xE UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32G491xC/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32G491xC/xE LQFP48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32G491xC/xE WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32G491xC/xE LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32G491xC/xE UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32G491xC/xE LQFP80 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32G491xC/xE LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFQFPN32 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 UFQFPN48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DS13122 Rev 3 STM32G491xC STM32G491xE Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. List of figures LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LQFP48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 WLCSP64 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 WLCSP64 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 WLCSP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 UFBGA64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 UFBGA64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LQFP80 12 x 12 mm - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LQFP80 12 x 12 mm - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 LQFP80 12 x 12 mm top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 LQFP80 14 x 14 mm - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 LQFP80 14 x 14 mm- recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 LQFP80 14 x 14 mm - top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DS13122 Rev 3 11/199 11 Introduction 1 STM32G491xC STM32G491xE Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32G491xC/xE microcontrollers. This document should be read in conjunction with the reference manual RM0440 “STM32G4 Series advanced Arm® 32-bit MCUs”. The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical reference manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/199 DS13122 Rev 3 STM32G491xC STM32G491xE 2 Description Description The STM32G491xC/xE devices are based on the high-performance Arm® Cortex®-M4 32bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. These devices embed high-speed memories (512 Kbytes of Flash memory, and 112 Kbytes of SRAM), a Quad-SPI Flash memory interface, an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection. The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions). They offer three fast 12-bit ADCs (5 Msps), four comparators, four operational amplifiers, four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a lowpower RTC, one general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer. They also feature standard and advanced communication interfaces such as: - Three I2Cs - Three SPIs multiplexed with two half duplex I2Ss - Three USARTs, two UARTs and one low-power UART. - Two FDCANs - One SAI - USB device - UCPD The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. Some independent power supplies are supported including an analog independent supply input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC and the registers. The STM32G491xC/xE family offers 9 packages from 32-pin to 100-pin. DS13122 Rev 3 13/199 44 Description STM32G491xC STM32G491xE Table 2. STM32G491xC/xE features and peripheral counts Peripheral Flash memory STM32G491Kx STM32G491Cx STM32G491Rx STM32G491Mx STM32G491Vx 256 512 Kbytes Kbytes 256 Kbytes 256 512 256 512 256 512 Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes 512 Kbytes SRAM1 80 Kbytes SRAM2 16 Kbytes CCM SRAM 16 Kbytes QUADSPI Timers 1 Advanced motor control 3 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 2 (16-bit) Low power 1 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 PWM channels (all) 23 32 38 38 44 PWM channels (except complementary) 23 26 28 28 29 SPI(I2S)(1) 3 (2) 2C 3 I Comm. interfac es USART 2 UART 0 3 0 in LQFP48 1 in UFQFPN48 2 LPUART 1 FDCANs 2 USB device Yes UCPD Yes SAI Yes RTC Tamper pins Yes 1 2 2 Random number generator Yes AES No CORDIC Yes 14/199 DS13122 Rev 3 3 STM32G491xC STM32G491xE Description Table 2. STM32G491xC/xE features and peripheral counts (continued) Peripheral STM32G491Kx STM32G491Cx STM32G491Rx STM32G491Mx STM32G491Vx FMAC Yes GPIOs 26 Wakeup pins 2 12-bit ADCs Number of channels 38 in LQFP48 42 in UFQFPN48 3 52 66 86 4 4 5 32 36 3 18 in LQFP48 19 in UFQFPN48 11 12-bit DAC Number of channels 24 2 4 (2 external + 2 internal) Internal voltage reference buffer Yes Analog comparator 4 Operational amplifiers 4 Max. CPU frequency 170 MHz Operating voltage Operating temperature Packages 1.71 V to 3.6 V Ambient operating temperature: -40 to 85 °C / -40 to 125 °C UFQFPN32 LQFP48/ UFQFPN48 LQFP64/ UFBGA4 WLCSP64 LQFP80 LQFP100 1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode. DS13122 Rev 3 15/199 44 Description STM32G491xC STM32G491xE Figure 1. STM32G491xC/xE block diagram JTAG & SW ETM MPU NVIC FPU Arm® Cortex-M4 170 MHz QUADSPI D-BUS I-BUS S-BUS GP-DMA2 8 Chan GP-DMA1 8 Chan ACCEL/ CACHE TRACECK TRACED(3:0) AHB BUS-MATRIX 5M / 8S JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO CLK, NCS, BK1_IO[3:0] FLASH 512 KB CCM SRAM 16 KB @VDDA SRAM2 16 KB CH1 DAC1 OUT1/OUT2 CH2 SRAM1 80 KB DMAMUX AHB2 CH1 DAC3 CH2 RNG @VDDA RNB1 analog SAR ADC1 Ain ADC IF SAR ADC2 PC(15:0) PD(15:0) PE(15:0) PF(10:9,2:0) PG(10:10) IF FMAC AHB1 PB(15:0) VOLT. REG. 3.3V TO 1.2V VDD12 SAR ADC3 PA(15:0) POWER MNGT CORDIC GPIO PORT A @VDD SUPPLY SUPERVISION @VDD USART GPIO2MBps PORT B USART GPIO2MBps PORT C LSI POR PLL Reset Int USART GPIO2MBps PORT D HSI USART GPIO2MBps PORT E HSI48 VDD = 1.71 to 3.6V VSS POR / BOR VDD, VSS, VDDA, VSSA, RESET PVD, PWM USART GPIO2MBps PORT F XTAL OSC 4-48MHz GPIO2MBps PORT G USART IWDG RESET& FS, SCK, SD, MCLK as AF CLOCKCTRL SAI1 OSC_IN OSC_OUT Standby Interface VBAT = 1.55 to 3.6V @VBAT 4 PWM,4PWM, ETR,BKIN as F TIMER8 RTC AWU BKPREG 16b PWM CRC RTC Interface 16b PWM CH as AF TIMER15 USART 2MBps CH as AF TIMER16 USART 2MBps 16b MOSI, MISO SCK, NSS as AF 1 USART SPI 2MBps 4 CH, ETR as AF TIMER3&4 4 CH, ETR as AF PWRCTRL Smcard irDA APB2 60MHzAPB1 USART USART12MBps TIMER2 LP_UART1 RX, TX as AF I2C1&2&3 SCL, SDA, SMBAL as AF WinWATCHDOG LP timer1 RX, TX, SCK,CTS, RTS as AF TIMER6 16b trigg TIMER7 16b trigg CRS USART2&3 UART4&5 SPI2&3 CAN1&2 Vref_Buf Smcard irDA irDA I2S half duplex RX, TX, SCK, CTS, RTS as AF RX, TX, CTS, RTS as AF MOSI, MISO, SCK NSS, as AF RX,TX as AF USBPD OPAMP 1,2,3,6 FIFO @VDDA PHY SysCfg COMP 1,2,3,4 RTC_OUT RTC_TS RTC_TAMPx 16b 16b TIMER17 USART 2MBps OSC32_IN OSC_OUT AHB/APB2 AHB/APB1 16b PWM FIFO TIMER1 TIMER20 XTAL 32kHz USB Device PHY 4 PWM,4PWM, ETR,BKIN as F 4 PWM,4PWM, ETR,BKIN as F CH as AF16b peripheralclocks and system EXT IT. WKUP USART 2MBps APB2 86 AFP D+ D- CC1 CC2 MSv63423V2 1. AF: alternate function on I/O pins. 16/199 DS13122 Rev 3 STM32G491xC STM32G491xE Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of the MCU implementation, with a reduced pin count and with low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional codeefficiency, delivering the expected high-performance from an Arm core in a memory size usually associated with 8-bit and 16-bit devices. The processor supports a set of DSP instructions which allows an efficient signal processing and a complex algorithm execution. Its single precision FPU speeds up the software development by using metalanguage development tools to avoid saturation. With its embedded Arm core, the STM32G491xC/xE family is compatible with all Arm tools and software. Figure 1 shows the general block diagram of the STM32G491xC/xE devices. 3.2 Adaptive real-time memory accelerator (ART accelerator) The ART accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 protected areas, which can be divided in up into 8 subareas each. The protection area sizes range between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.4 Embedded Flash memory The STM32G491xC/xE devices feature 512 kbytes of embedded Flash memory which is available for storing programs and data. Flexible protections can be configured thanks to the option bytes: DS13122 Rev 3 17/199 44 Functional overview STM32G491xC STM32G491xE • Readout protection (RDP) to protect the whole memory. Three levels of protection are available: – Level 0: no readout protection – Level 1: memory readout protection; the Flash memory cannot be read from or written to if either the debug features are connected or the boot in RAM or bootloader are selected – Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible. • Write protection (WRP): the protected area is protected against erasing and programming. • Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. • Securable memory area: a part of Flash memory can be configured by option bytes to be securable. After reset this securable memory area is not secured and it behaves like the remainder of main Flash memory (execute, read, write access). When secured, any access to this securable memory area generates corresponding read/write error. Purpose of the Securable memory area is to protect sensitive code and data (secure keys storage) which can be executed only once at boot, and never again unless a new reset occurs. The Flash memory embeds the error correction code (ECC) feature supporting: 3.5 • Single error detection and correction • Double error detection • The address of the ECC fail can be read in the ECC register • 1 Kbyte (128 double word) OTP (one-time programmable) for user data. The OTP area is available in Bank 1 only. The OTP data cannot be erased and can be written only once. Embedded SRAM STM32G491xC/xE devices feature 112 Kbytes of embedded SRAM. This SRAM is split into three blocks: 18/199 • 80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP register). The first 32 Kbytes of SRAM1 support hardware parity check. • 16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the SRAM2 through the System bus. SRAM2 can be kept in stop and standby modes. • 16 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU through I-Code/D-Code bus for maximum performance. It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1, DMA2) through SBUS contiguously to SRAM1 and SRAM2.The CCM SRAM supports hardware parity check and can be write-protected with 1-Kbyte granularity. • The memory can be accessed in read/write at max CPU clock speed with 0 wait states. DS13122 Rev 3 STM32G491xC STM32G491xE 3.6 Functional overview Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, QUADSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix DMA1 DMA2 S-bus D-bus I-bus Cortex®-M4 with FPU DCode ACCEL ICode FLASH 512 KB SRAM1 CCM SRAM SRAM2 AHB1 peripherals AHB2 peripherals QUADSPI BusMatrix-S MS52814V1 3.7 Boot modes At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed. The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade). DS13122 Rev 3 19/199 44 Functional overview 3.8 STM32G491xC STM32G491xE CORDIC The CORDIC provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks. Cordic features 3.9 • 24-bit CORDIC rotation engine • Circular and Hyperbolic modes • Rotation and Vectoring modes • Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root, Natural logarithm • Programmable precision up to 20-bit • Fast convergence: 4 bits per clock cycle • Supports 16-bit and 32-bit fixed point input and output formats • Low latency AHB slave interface • Results can be read as soon as ready without polling or interrupt • DMA read and write channels Filter mathematical accelerator (FMAC) The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. 20/199 DS13122 Rev 3 STM32G491xC STM32G491xE Functional overview FMAC features 3.10 • 16 x 16-bit multiplier • 24+2-bit accumulator with addition and subtraction • 16-bit input and output data • 256 x 16-bit local memory • Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers • Input and output sample buffers can be circular • Buffer “watermark” feature reduces overhead in interrupt mode • Filter functions: FIR, IIR (direct form 1) • AHB slave interface • DMA read and write data channels Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location. 3.11 Power supply management 3.11.1 Power supply schemes The STM32G491xC/xE devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent supplies, can be provided for specific peripherals: • VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins. • • VDDA = 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation). VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage and should preferably be connected to VDD when these peripherals are not used. VBAT = 1.55 V to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. DS13122 Rev 3 21/199 44 Functional overview • STM32G491xC STM32G491xE VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. When VDDA < 2 V VREF+ must be equal to VDDA. When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA. The internal voltage reference buffer supports three output voltages, which are configured with VRS bits in the VREFBUF_CSR register: – VREF+ = 2.048 V – VREF+ = 2.5 V – VREF+ = 2.9 V VREF- is double bonded with VSSA. 3.11.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a peripheral voltage monitor which compares the independent supply voltages VDDA, with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 3.11.3 Voltage regulator Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero. The device supports dynamic voltage scaling to optimize its power consumption in Run mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. The main regulator (MR) operates in the following ranges: 22/199 • Range 1 boost mode with the CPU running at up to 170 MHz. • Range 1 normal mode with CPU running at up to 150 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. DS13122 Rev 3 STM32G491xC STM32G491xE 3.11.4 Functional overview Low-power modes By default, the microcontroller is in Run mode after system or power Reset. It is up to the user to select one of the low-power modes described below: 3.11.5 • Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode: This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode: This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Low power run mode. • Stop mode: In Stop mode, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. • Standby mode: The Standby mode is used to achieve the lowest power consumption with brown-out reset, BOR. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The BOR always remains active in Standby mode. For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE). • Shutdown mode: The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper). Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. DS13122 Rev 3 23/199 44 Functional overview 3.11.6 STM32G491xC STM32G491xE VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when there is no external battery and when an external supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode. The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: 24/199 When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation. DS13122 Rev 3 STM32G491xC STM32G491xE Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes. Sleep Low-power run Stop Table 3. STM32G491xC/xE peripherals interconnect matrix Run 3.12 Functional overview TIMx Timers synchronization or chaining Y Y Y - ADCx DACx Conversion triggers Y Y Y - DMA Memory to memory transfer trigger Y Y Y - COMPx Comparator output blanking Y Y Y - IRTIM Infrared interface output generation Y Y Y - TIM1, 8, 20 TIM2, 3, 4 Timer input channel, trigger, break from analog signals comparison Y Y Y - LPTIMER1 Low-power timer triggered by analog signals comparison Y Y Y Y TIM1, 8, 20 Timer triggered by analog watchdog Y Y Y - TIM16 Timer input channel from RTC events Y Y Y - LPTIMER1 Low-power timer triggered by RTC alarms or tampers Y Y Y Y All clocks sources (internal and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y - USB TIM2 Timer triggered by USB SOF Y Y - - CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) COMPx PVD TIM1, 8, 20 Timer break TIM15, 16, 17 Y Y Y - TIMx External trigger Y Y Y - LPTIMER1 External trigger Y Y Y - ADCx DACx Conversion external trigger Y Y Y - Interconnect source TIMx TIM16/TIM17 COMPx ADCx Interconnect destination RTC GPIO Interconnect action DS13122 Rev 3 25/199 44 Functional overview 3.13 STM32G491xC STM32G491xE Clocks and startup The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: three different sources can deliver SYSCLK system clock: – 4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL. – System PLL with maximum output frequency of 170 MHz. It can be fed with HSE or HSI16 clocks. • RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can be used to drive the USB or the RNG peripherals. • Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog. • Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI, RNG) have their own clock independent of the system clock. • Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes. Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 170 MHz. 26/199 DS13122 Rev 3 STM32G491xC STM32G491xE 3.14 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.15 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations. The two DMA controllers have 16 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests. The DMA supports: • 16 independently configurable channels (requests) – Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 4. DMA implementation DMA features DMA1 DMA2 Number of regular channels 8 8 DS13122 Rev 3 27/199 44 Functional overview 3.16 STM32G491xC STM32G491xE DMA request router (DMAMUX) When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product. An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs. For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs. 3.17 Interrupts and events 3.17.1 Nested vectored interrupt controller (NVIC) The STM32G491xC/xE devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.17.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 40 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can be connected to the 16 external interrupt lines. 28/199 DS13122 Rev 3 STM32G491xC STM32G491xE 3.18 Functional overview Analog-to-digital converter (ADC) The device embeds three successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 4 Msps maximum conversion rate with full resolution Down to 41.67 ns sampling time – Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit resolution) • One external reference pin is available on all packages, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.18.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into a data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching – Flexible sample time control – Hardware gain and offset compensation Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. DS13122 Rev 3 29/199 44 Functional overview STM32G491xC STM32G491xE Table 5. Temperature sensor calibration values 3.18.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18 and ADC3_IN18 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 6. Internal voltage reference calibration values 3.18.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware enables the application to measure the VBAT battery voltage using the internal ADC1_IN17 channel. As the VBAT voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage. 3.18.4 Operational amplifier internal output (OPAMPxINT): The OPAMPx (x = 1,2,3,6) output OPAMPxINT can be sampled using an ADCx (x = 1,2,3) internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be used as GPIO. 3.19 Digital to analog converter (DAC) Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. 30/199 DS13122 Rev 3 STM32G491xC STM32G491xE Functional overview This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Saw tooth wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor • Up to 1 Msps for external output and 15 Msps for internal output The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.20 Voltage reference buffer (VREFBUF) The STM32G491xC/xE devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports three voltages: • 2.048 V • 2.5 V • 2.9 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 3. Voltage reference buffer VREFBUF VDDA Bandgap + DAC, ADC VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 DS13122 Rev 3 31/199 44 Functional overview 3.21 STM32G491xC STM32G491xE Comparators (COMP) The STM32G491xC/xE devices embed four rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers. 3.22 Operational amplifier (OPAMP) The STM32G491xC/xE devices embed four operational amplifiers (OPAMP1, OPAMP2, OPAMP3, OPAMP6) with external or internal follower routing and PGA capability. The operational amplifier features: 3.23 • 13 MHz bandwidth • Rail-to-rail input/output • PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging of -1, -3, -7, -15, -31 or -63 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.24 Timers and watchdogs The STM32G491xC/xE devices include three advanced motor control timers, up to six general-purpose timers, two basic timers, one low-power timer, two watchdog timers and a SysTick timer. The table below compares the features of the advanced motor control, general purpose and basic timers. Table 7. Timer feature comparison DMA request generation Capture/ compare channels Complementary outputs Up, Any integer down, between 1 and Up/down 65536 Yes 4 4 32-bit Up, Any integer down, between 1 and Up/down 65536 Yes 4 No 16-bit Up, Any integer down, between 1 and Up/down 65536 Yes 4 No Timer type Timer Counter resolution Advanced motor control TIM1, TIM8, TIM20 16-bit Generalpurpose TIM2 Generalpurpose TIM3, TIM4 32/199 Counter type Prescaler factor DS13122 Rev 3 STM32G491xC STM32G491xE Functional overview Table 7. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.24.1 Advanced motor control timer (TIM1, TIM8, TIM20) The advanced motor control timers can each be seen as a four-phase PWM multiplexed on 8 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0-100%) • One-pulse mode output In debug mode, the advanced motor control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs. Many features are shared with the general-purpose TIMx timers (described in Section 3.24.2) using the same architecture, so the advanced motor control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. DS13122 Rev 3 33/199 44 Functional overview 3.24.2 STM32G491xC STM32G491xE General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) There are up to six synchronizable general-purpose timers embedded in the STM32G491xC/xE devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, and TIM4 They are full-featured general-purpose timers: – TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.24.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 34/199 DS13122 Rev 3 STM32G491xC STM32G491xE 3.24.4 Functional overview Low-power timer (LPTIM1) The devices embed a low-power timer. This timer has an independent clock and are running in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system from Stop mode. LPTIM1 is active in Stop mode. This low-power timer supports the following features: 3.24.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.24.6 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.24.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DS13122 Rev 3 35/199 44 Functional overview 3.25 STM32G491xC STM32G491xE Real-time clock (RTC) and backup registers The RTC supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC is supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes. 3.26 36/199 Tamper and backup registers (TAMP) • 32 32-bit backup registers, retained in all low-power modes and also in VBAT mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. • Up to three tamper pins for external tamper detection events. The external tamper pins can be configured for edge detection, edge and level, level detection with filtering. • Five internal tampers events. • Any tamper detection can generate a RTC timestamp event. • Any tamper detection erases the backup registers. • Any tamper detection can generate an interrupt and wake-up the device from all lowpower modes. DS13122 Rev 3 STM32G491xC STM32G491xE 3.27 Functional overview Infrared transmitter The STM32G491xC/xE devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13. To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels. Figure 4. Infrared transmitter TIM17_CH1 IRTIM IR_OUT TIM16_CH1 MS30474V2 DS13122 Rev 3 37/199 44 Functional overview 3.28 STM32G491xC STM32G491xE Inter-integrated circuit interface (I2C) The device embeds three I2Cs. Refer to Table 8: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System management bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power system management protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 8. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X Wakeup from Stop mode on address match X X X 1. X: supported 38/199 DS13122 Rev 3 STM32G491xC STM32G491xE 3.29 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32G491xC/xE devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable. The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability. The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode. The wakeup from Stop mode can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled All USART interfaces can be served by the DMA controller. Table 9. USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X - - - Smartcard mode X X X - - - Single-wire half-duplex communication X X X X X X IrDA SIR ENDEC block X X X X X - LIN mode X X X X X - Dual clock domain X X X X X X Wakeup from Stop mode X X X X X X Receiver timeout interrupt X X X X X - Modbus communication X X X X X - Auto baud rate detection Driver Enable X (4 modes) X X LPUART/USART data length X X X X 7, 8 and 9 bits DS13122 Rev 3 39/199 44 Functional overview STM32G491xC STM32G491xE Table 9. USART/UART/LPUART features (continued) USART modes/features(1) USART1 USART2 USART3 UART4 Tx/Rx FIFO X Tx/Rx FIFO size 8 UART5 LPUART1 1. X = supported. 3.30 Low-power universal asynchronous receiver transmitter (LPUART) The STM32G491xC/xE devices embed one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. It has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop mode can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interface can be served by the DMA controller. 3.31 Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation. Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. All SPI interfaces can be served by the DMA controller. 40/199 DS13122 Rev 3 STM32G491xC STM32G491xE 3.32 Functional overview Serial audio interfaces (SAI) The device embeds 1 SAI. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. 3.32.1 SAI peripheral supports • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. Table 10. SAI features implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability X 16 slots X DS13122 Rev 3 41/199 44 Functional overview STM32G491xC STM32G491xE Table 10. SAI features implementation (continued) SAI features Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit FIFO size Support(1) X X (8 word) SPDIF X 1. X: supported. 3.33 Controller area network (FDCAN1, FDCAN2) The controller area network (CAN) subsystem consists of two CAN modules and message RAM memory. The two CAN modules (FDCAN1, and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. A 2-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers. 3.34 Universal serial bus (USB) The STM32G491xC/xE devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.35 USB Type-C™ / USB Power Delivery controller (UCPD) The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications. The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring: 42/199 • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB Power Delivery message transmission and reception • FRS (fast role swap) support DS13122 Rev 3 STM32G491xC STM32G491xE Functional overview The digital controller handles notably: • USB Type-C level detection with de-bounce, generating interrupts • FRS detection, generating an interrupt • Byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible) • USB Power Delivery timing dividers (including a clock pre-scaler) • CRC generation/checking • 4b5b encode/decode • Ordered sets (with a programmable ordered set mask at receive) • Frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling. 3.36 Clock recovery system (CRS) The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.37 Quad-SPI memory interface (QUADSPI) The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external Flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory. Both throughput and capacity can be increased two-fold using dual-flash mode, where two quad SPI Flash memories are accessed simultaneously. DS13122 Rev 3 43/199 44 Functional overview STM32G491xC STM32G491xE The Quad-SPI interface supports: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external Flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode – Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external Flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error 3.38 Development support 3.38.1 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.38.2 Embedded trace macrocell™ The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32G491xC/xE devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded trace macrocell operates with third party debugger software tools. 44/199 DS13122 Rev 3 STM32G491xC STM32G491xE Pinouts and pin description 4 Pinouts and pin description 4.1 UFQFPN32 pinout description PB3 PA15 PB5 PB4 PB7 PB6 VSS PB8-BOOT0 Figure 5. STM32G491xC/xE UFQFPN32 pinout VDD 1 32 31 30 29 28 27 26 25 24 PA14 PF0-OSC_IN 2 23 PA13 PF1-OSC_OUT 3 22 PA12 PG10-NRST 4 21 PA11 PA0 5 20 PA10 PA1 6 19 PA9 PA2 7 18 PA8 PA3 8 17 VDD VSS VDDA PB0 VSSA PA5 PA7 10 11 12 13 14 15 16 PA6 9 PA4 UFQFPN32 MSv47174V3 1. The above figure shows the package top view. DS13122 Rev 3 45/199 68 Pinouts and pin description 4.2 STM32G491xC STM32G491xE UFQFPN48 pinout description VDD PB9 PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PC11 PC10 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 6. STM32G491xC/xE UFQFPN48 pinout VBAT 1 36 PA13 PC13 2 35 VDD PC14-OSC32_IN 3 34 PA12 PC15-OSC32_OUT 4 33 PA11 PF0-OSC_IN 5 32 PA10 PF1-OSC_OUT 6 31 PA9 PG10-NRST 7 30 PA8 PA0 8 29 PC6 PA1 9 28 PB15 PA2 10 27 PB14 PA3 11 26 PB13 PA4 12 25 PB12 UFQFPN48 24 VSS PB11 23 VDD 22 PB10 21 VDDA 20 VREF+ 19 PB2 18 PB1 17 PB0 16 PC4 15 PA7 14 PA6 PA5 13 Exposed pad MSv47172V1 1. The above figure shows the package top view. 2. VSS pads are connected to the exposed pad. 4.3 LQFP48 pinout description VDD VSS PB9 PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 PA13 48 47 46 45 44 43 42 41 40 39 38 37 Figure 7. STM32G491xC/xE LQFP48 pinout VBAT 1 36 VDD PC13 2 35 VSS PC14 - OSC32_IN 3 34 PA12 PC15 - OSC32_OUT 4 33 PA11 PF0 - OSC_IN 5 32 PA10 PF1 - OSC_OUT 6 31 PA9 PG10 - NRST 7 30 PA8 PA0 8 29 PB15 PA1 9 28 PB14 PA2 10 27 PB13 PA3 11 26 PB12 PA4 12 25 PB11 13 14 15 16 17 18 19 20 21 22 23 24 PA5 PA6 PA7 PB0 PB1 PB2 VSSA VREF+ VDDA PB10 VSS VDD LQFP48 1. The above figure shows the package top view. 46/199 DS13122 Rev 3 MSv42659V2 STM32G491xC STM32G491xE 4.4 Pinouts and pin description WLCSP64 ballout description Figure 8. STM32G491xC/xE WLCSP64 ballout 1 2 3 4 5 6 7 8 A VDD PC11 PC12 PD2 PB5 PB7 PB9 VDD B PA12 VSS PC10 PA15 PB6 PB8BOOT0 VSS VBAT C PA11 PA10 PA13 PA14 PB4 PC13 PC1 PC14OSC32 _IN D PA9 PA8 PC9 PB3 PA2 PC2 PG10 -NRST PC15OSC32 _OUT E PC7 PC8 PC6 PA5 PA4 PC3 PF1OSC_OUT PF0OSC_IN F PB15 PB14 PB0 PC5 PA7 PA3 PA1 PC0 G PB13 VSS PB12 PB2 VSSA PC4 VSS PA0 H VDD PB10 PB11 VDDA VREF+ PB1 PA6 VDD MSv63424V1 1. The above figure shows the package top view. LQFP64 pinout description VDD VSS PB9 PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 PA13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 9. STM32G491xC/xE LQFP64 pinout VBAT 1 48 VDD PC13 2 47 VSS PC14-OSC32_IN 3 46 PA12 PC15-OSC32_OUT 4 45 PA11 PF0-OSC_IN 5 44 PA10 PF1-OSC_OUT 6 43 PA9 PG10-NRST 7 42 PA8 PC0 8 41 PC9 PC1 9 40 PC8 PC2 10 39 PC7 PC3 11 38 PC6 PA0 12 37 PB15 PA1 13 36 PB14 PA2 14 35 PB13 VSS 15 34 PB12 VDD 16 33 PB11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 VSSA VREF+ VDDA PB10 VSS VDD LQFP64 PA3 4.5 MSv42658V2 1. The above figure shows the package top view. DS13122 Rev 3 47/199 68 Pinouts and pin description 4.6 STM32G491xC STM32G491xE UFBGA64 ballout description Figure 10. STM32G491xC/xE UFBGA64 ballout 1 2 3 4 5 6 7 8 A VDD PB9 PB7 PB6 PB3 PC12 PA15 VDD B PC13 VSS PB8-BOOT0 PB5 PD2 PC11 VSS PA12 C PC14OSC32_IN VBAT PC1 PB4 PC10 PA14 PA13 PA11 D PC15OSC32_OUT PG10-NRST PC2 PA4 PC4 PA10 PA9 PC9 E PF0-OSC_IN PC0 PA1 PA5 PB0 PA8 PC7 PC6 F PF1-OSC_OUT PA0 PA2 PC5 PB1 PC8 PB15 PB14 PA6 VSSA VREF+ PB13 VSS PB12 PA7 PB2 VDDA PB10 PB11 VDD G PC3 VSS H VDD PA3 MSv47177V3 1. The above figure shows the package top view. 48/199 DS13122 Rev 3 STM32G491xC STM32G491xE LQFP80 pinout description VDD VSS PB9 PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PA13 VDD VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Figure 11. STM32G491xC/xE LQFP80 pinout VBAT 1 60 PA12 PC13 2 59 PA11 PC14-OSC32_IN 3 58 PA10 PC15-OSC32_OUT 4 57 PA9 PF0-OSC_IN 5 56 PA8 PF1-OSC_OUT 6 55 PC9 PG10-NRST 7 54 PC8 PC0 8 53 PC7 PC1 9 52 PC6 PC2 10 51 VDD PC3 11 50 VSS PA0 12 49 PD10 PA1 13 48 PD9 PA2 14 47 PD8 VSS 15 46 PB15 VDD 16 45 PB14 PA3 17 44 PB13 PA4 18 43 PB12 PA5 19 42 PB11 PA6 20 41 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PA7 PC5 PB0 PB1 PB2 VSSA VREF+ VDDA PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VSS LQFP80 PC4 4.7 Pinouts and pin description MSv60826V1 1. The above figure shows the package top view. DS13122 Rev 3 49/199 68 Pinouts and pin description 4.8 STM32G491xC STM32G491xE LQFP100 pinout description VDD VSS PE1 PE0 PB9 PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PA13 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 12. STM32G491xC/xE LQFP100 pinout PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 PA12 PE5 4 72 PA11 PE6 5 71 PA10 VBAT 6 70 PA9 PC13 7 69 PA8 PC14-OSC32_IN 8 68 PC9 PC15-OSC32_OUT 9 67 PC8 PF9 10 66 PC7 PF10 11 65 PC6 PF0-OSC_IN 12 64 VDD PF1-OSC_OUT 13 63 VSS PG10-NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 PF2 19 57 PD10 PA0 20 56 PD9 PA1 21 55 PD8 PA2 22 54 PB15 VSS 23 53 PB14 VDD 24 52 PB13 PA3 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 VSSA VREF+ VDDA PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VSS VDD PB11 LQFP100 1. The above figure shows the package top view. 50/199 DS13122 Rev 3 MSv42661V3 STM32G491xC STM32G491xE 4.9 Pinouts and pin description Pin definition Table 11. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O B Dedicated BOOT0 pin NRST I/O structure Pin functions Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os _a I/O, with Analog switch function supplied by VDDA _c I/O, USB Type-C PD capable _d I/O, USB Type-C PD Dead Battery function _f I/O, Fm+ capable _u Notes Definition (1) I/O, with USB function Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 1. The related I/O structures in are FT_u. DS13122 Rev 3 51/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) - - - - - 1 I/O PE2 I/O structure Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 - Pin name (function after reset) FT Notes - LQFP48 UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions - TRACECK, TIM3_CH1, SAI1_CK1, TIM20_CH1, SAI1_MCLK_A, EVENTOUT - - - - - - - - - 2 PE3 I/O FT - TRACED0, TIM3_CH2, TIM20_CH2, SAI1_SD_B, EVENTOUT - - - - - - - 3 PE4 I/O FT - TRACED1, TIM3_CH3, SAI1_D2, TIM20_CH1N, SAI1_FS_A, EVENTOUT - - TRACED2, TIM3_CH4, SAI1_CK2, TIM20_CH2N, SAI1_SCK_A, EVENTOUT - WKUP3, RTC_TAMP3 - - - - - - - 4 I/O PE5 FT - - - - - - - 5 PE6 I/O FT - TRACED3, SAI1_D1, TIM20_CH3N, SAI1_SD_A, EVENTOUT - 1 1 B8 1 C2 1 6 VBAT S - - - - TIM1_BKIN, TIM1_CH1N, TIM8_CH4N, EVENTOUT WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT1 EVENTOUT OSC32_IN (3) EVENTOUT OSC32_OUT - TIM20_BKIN, TIM15_CH1, SPI2_SCK, QUADSPI1_BK1_IO1, SAI1_FS_B, EVENTOUT - - TIM20_BKIN2, TIM15_CH2, SPI2_SCK, QUADSPI1_CLK, SAI1_D3, EVENTOUT - - 2 2 C6 2 B1 2 7 PC13 I/O FT - 3 3 C8 3 C1 3 8 PC14OSC32_IN I/O FT - 4 4 D8 4 D1 4 9 PC15OSC32_OUT I/O FT - - 52/199 - - - - - - - - - - - - 10 11 PF9 PF10 (2) (3) (2) I/O I/O FT FT DS13122 Rev 3 (3) (2) STM32G491xC STM32G491xE Pinouts and pin description Table 12. STM32G491xC/xE pin definition(1) (continued) Notes I/O structure Pin name (function after reset) Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 UFQFPN48 UFQFPN32 Pin Number Alternate functions FT_f PF0-OSC_IN I/O a - I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N, EVENTOUT Additional functions ADC1_IN10, OSC_IN 2 5 5 E8 5 E1 5 12 3 6 6 E7 6 F1 6 13 PF1OSC_OUT I/O FT_ a - SPI2_SCK/I2S2_CK, EVENTOUT ADC2_IN10, COMP3_INM, OSC_OUT 4 7 7 D7 7 D2 7 14 PG10-NRST I/O FT - MCO, EVENTOUT NRST - - - F8 8 E2 8 15 PC0 I/O FT_ a - LPTIM1_IN1, TIM1_CH1, LPUART1_RX, EVENTOUT ADC12_IN6, COMP3_INM - LPTIM1_OUT, TIM1_CH2, LPUART1_TX, QUADSPI1_BK2_IO0, SAI1_SD_A, EVENTOUT ADC12_IN7, COMP3_INP - LPTIM1_IN2, TIM1_CH3, COMP3_OUT, TIM20_CH2, QUADSPI1_BK2_IO1, EVENTOUT ADC12_IN8 ADC12_IN9 - - - - - - C7 D6 9 10 C3 D3 9 10 16 17 PC1 PC2 I/O I/O TT_ a FT_ a - - - E6 11 G1 11 18 PC3 I/O FT_ a - LPTIM1_ETR, TIM1_CH4, SAI1_D1, TIM1_BKIN2, QUADSPI1_BK2_IO2, SAI1_SD_A, EVENTOUT - - - - - - - 19 PF2 I/O FT - TIM20_CH3, I2C2_SMBA, EVENTOUT - - TIM2_CH1, USART2_CTS, COMP1_OUT, TIM8_BKIN, TIM8_ETR, TIM2_ETR, EVENTOUT ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2, WKUP1 - RTC_REFIN, TIM2_CH2, USART2_RTS_DE, TIM15_CH1N, EVENTOUT ADC12_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, OPAMP6_VINM 5 6 8 9 8 9 G8 F7 12 13 F2 E3 12 13 20 21 PA0 PA1 I/O I/O TT_ a TT_ a DS13122 Rev 3 53/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) (continued) TT_ I/O a Notes I/O structure Pin name (function after reset) Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions - TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, QUADSPI1_BK1_NCS, LPUART1_TX, UCPD1_FRSTX, ADC1_IN3, COMP2_INM, OPAMP1_VOUT, WKUP4/LSCO 7 10 10 D5 14 F3 14 22 PA2 - - - G7 15 G2 15 23 VSS S - - - - - - - H8 16 H1 16 24 VDD S - - - - - TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, QUADSPI1_CLK, LPUART1_RX, SAI1_MCLK_A, EVENTOUT ADC1_IN4, COMP2_INP, OPAMP1_VINM/ OPAMP1_VINP - TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, SAI1_FS_B, EVENTOUT ADC2_IN17, DAC1_OUT1, COMP1_INM - TIM2_CH1, TIM2_ETR, SPI1_SCK, UCPD1_FRSTX, EVENTOUT ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM 8 9 10 11 12 - 11 12 13 14 15 16 54/199 11 12 13 14 15 - F6 E5 E4 H7 F5 G6 17 18 19 20 21 22 H2 D4 E4 G3 H3 D5 17 18 19 20 21 22 25 26 27 28 29 30 PA3 TT_ I/O a PA4 TT_ I/O a PA5 TT_ I/O a PA6 I/O TT_ a PA7 TT_ I/O a PC4 FT_f I/O a DS13122 Rev 3 - TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, ADC2_IN3, COMP1_OUT, OPAMP2_VOUT QUADSPI1_BK1_IO3, LPUART1_CTS, EVENTOUT - TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, QUADSPI1_BK1_IO2, UCPD1_FRSTX, ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP - TIM1_ETR, I2C2_SCL, USART1_TX, QUADSPI1_BK2_IO3, EVENTOUT ADC2_IN5 STM32G491xC STM32G491xE Pinouts and pin description Table 12. STM32G491xC/xE pin definition(1) (continued) 13 - - 17 18 16 17 F4 F3 H6 23 24 25 F4 E5 F5 23 24 25 31 32 33 I/O structure Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 - Pin name (function after reset) TT_ I/O a PC5 I/O PB0 I/O PB1 TT_ a TT_ a Notes - UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions - TIM15_BKIN, SAI1_D3, TIM1_CH4N, USART1_RX, EVENTOUT ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM, WKUP5 - TIM3_CH3, TIM8_CH2N, TIM1_CH2N, QUADSPI1_BK1_IO1, UCPD1_FRSTX, EVENTOUT ADC1_IN15/AD C3_IN12, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP - TIM3_CH4, TIM8_CH3N, ADC1_IN12/AD TIM1_CH3N, C3_IN1, COMP4_OUT, COMP1_INP, QUADSPI1_BK1_IO0, OPAMP3_VOUT, LPUART1_RTS_DE, OPAMP6_VINM EVENTOUT - 19 18 G4 26 H4 26 34 PB2 I/O TT_ a - RTC_OUT2, LPTIM1_OUT, TIM20_CH1, I2C3_SMBA, QUADSPI1_BK2_IO1, EVENTOUT 14 - 19 G5 27 G4 27 35 VSSA S - - - - - 20 20 H5 28 G5 28 36 VREF+ S - - - VREFBUF_OUT - 21 21 H4 29 H5 29 37 VDDA S - - - - 15 - - - - - - - VDDA/VREF+ S - - - - - - - - - - 30 38 PE7 I/O TT_ a - TIM1_ETR, SAI1_SD_B, EVENTOUT ADC3_IN4, COMP4_INP - - - - - - 31 39 PE8 I/O FT_ a - TIM1_CH1N, SAI1_SCK_B, EVENTOUT ADC3_IN6, COMP4_INM - - - - - - 32 40 PE9 I/O FT_ a - TIM1_CH1, SAI1_FS_B, EVENTOUT ADC3_IN2 - TIM1_CH2N, QUADSPI1_CLK, SAI1_MCLK_B, EVENTOUT ADC3_IN14 FT_ a - TIM1_CH2, QUADSPI1_BK1_NCS, EVENTOUT ADC3_IN15 - - - - - - 33 41 PE10 FT_ I/O a - - - - - - 34 42 PE11 I/O DS13122 Rev 3 ADC2_IN12, COMP4_INM, OPAMP3_VINM 55/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) (continued) UFQFPN32 UFQFPN48 LQFP48 WLCSP64 LQFP64 UFBGA64 LQFP80 LQFP100 Pin type I/O structure Notes Pin Number Alternate functions - - - - - - 35 43 PE12 I/O FT_ a - TIM1_CH3N, QUADSPI1_BK1_IO0, EVENTOUT ADC3_IN16 - - - - - - 36 44 PE13 I/O FT_ a - TIM1_CH3, QUADSPI1_BK1_IO1, EVENTOUT ADC3_IN3 - TIM1_CH4, TIM1_BKIN2, QUADSPI1_BK1_IO2, EVENTOUT - - TIM1_BKIN, TIM1_CH4N, USART3_RX, QUADSPI1_BK1_IO3, EVENTOUT - OPAMP3_VINM - - - - - - - - - - - - 37 38 45 46 Pin name (function after reset) PE14 PE15 I/O I/O FT FT Additional functions - 22 22 H2 30 H6 39 47 PB10 I/O TT_ a - TIM2_CH3, USART3_TX, LPUART1_RX, QUADSPI1_CLK, TIM1_BKIN, SAI1_SCK_A, EVENTOUT 16 - 23 G2 31 G7 40 48 VSS S - - - - 17 23 24 H1 32 H8 41 49 VDD S - - - - - TIM2_CH4, USART3_RX, LPUART1_TX, QUADSPI1_BK1_NCS, EVENTOUT ADC12_IN14, OPAMP6_VOUT - I2C2_SMBA, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, LPUART1_RTS_DE, FDCAN2_RX, EVENTOUT ADC1_IN11, OPAMP6_VINP - SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, LPUART1_CTS, FDCAN2_TX, EVENTOUT ADC3_IN5, OPAMP3_VINP, OPAMP6_VINP - - - 24 25 26 56/199 25 26 27 H3 G3 G1 33 34 35 H7 G8 G6 42 43 44 50 51 52 PB11 PB12 PB13 I/O I/O I/O TT_ a TT_ a TT_ a DS13122 Rev 3 STM32G491xC STM32G491xE Pinouts and pin description Table 12. STM32G491xC/xE pin definition(1) (continued) 27 F2 36 F8 45 53 PB14 I/O I/O structure Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 28 Pin name (function after reset) TT_ a Notes - UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions - TIM15_CH1, SPI2_MISO, TIM1_CH2N, USART3_RTS_DE, COMP4_OUT, EVENTOUT ADC1_IN5, OPAMP2_VINP ADC2_IN15 - 28 29 F1 37 F7 46 54 PB15 I/O FT_ a - RTC_REFIN, TIM15_CH2, TIM15_CH1N, COMP3_OUT, TIM1_CH3N, SPI2_MOSI/I2S2_SD, EVENTOUT - - - - - - 47 55 PD8 I/O FT_ a - USART3_TX, EVENTOUT - - - - - - - 48 56 PD9 I/O TT_ a - USART3_RX, EVENTOUT OPAMP6_VINP - - - - - - 49 57 PD10 I/O FT_ a - USART3_CK, EVENTOUT ADC3_IN7 - - - - - - - 58 PD11 I/O FT_ a - USART3_CTS, EVENTOUT ADC3_IN8 - - - - - - - 59 PD12 I/O FT_ a - TIM4_CH1, USART3_RTS_DE, EVENTOUT ADC3_IN9 - - - - - - - 60 PD13 I/O FT_ a - TIM4_CH2, EVENTOUT ADC3_IN10 - - - - - - - 61 PD14 I/O TT_ a - TIM4_CH3, EVENTOUT ADC3_IN11, OPAMP2_VINP - - - - - - - 62 PD15 I/O FT - TIM4_CH4, SPI2_NSS, EVENTOUT - - - - - - - 50 63 VSS S - - - - - - - - - - 51 64 VDD S - - - - - 29 - E3 38 E8 52 65 PC6 I/O FT - TIM3_CH1, TIM8_CH1, I2S2_MCK, EVENTOUT - - - - E1 39 E7 53 66 PC7 I/O FT - TIM3_CH2, TIM8_CH2, I2S3_MCK, EVENTOUT - - - - E2 40 F6 54 67 PC8 I/O FT_f - TIM3_CH3, TIM8_CH3, TIM20_CH3, I2C3_SCL, EVENTOUT - DS13122 Rev 3 57/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) (continued) WLCSP64 LQFP64 UFBGA64 LQFP80 LQFP100 - D3 41 D8 55 68 18 19 20 21 30 31 32 33 30 31 32 33 D2 D1 C2 C1 42 43 44 45 E6 D7 D6 C8 56 57 58 59 69 70 71 72 PC9 PA8 PA9 PA10 PA11 Notes LQFP48 - I/O structure UFQFPN48 - Pin name (function after reset) Pin type UFQFPN32 Pin Number Alternate functions Additional functions - TIM3_CH4, TIM8_CH4, I2SCKIN, TIM8_BKIN2, I2C3_SDA, EVENTOUT - - MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, SAI1_CK2, SAI1_SCK_A, EVENTOUT - FT_f (4) d I2C3_SMBA, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, SAI1_FS_A, EVENTOUT UCPD1_DBCC1 FT_ da (4) TIM17_BKIN, USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, TIM1_CH3, USART1_RX, TIM2_CH4, TIM8_BKIN, SAI1_D1, SAI1_SD_A, UCPD1_DBCC2 - SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2, EVENTOUT USB_DM USB_DP I/O FT_f I/O FT_f I/O I/O I/O FT_ u 22 34 34 B1 46 B8 60 73 PA12 I/O FT_ u - TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, TIM1_ETR, EVENTOUT - - 35 B2 47 B7 61 74 VSS S - - - - - 35 36 A1 48 A8 62 75 VDD S - - - - 58/199 DS13122 Rev 3 STM32G491xC STM32G491xE Pinouts and pin description Table 12. STM32G491xC/xE pin definition(1) (continued) 24 25 - - 36 37 38 39 40 38 39 - - C3 C4 B4 B3 A2 49 50 51 52 53 C7 C6 A7 C5 B6 63 64 65 66 67 76 77 78 79 80 PA13 PA14 PA15 PC10 PC11 I/O structure Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 37 Pin name (function after reset) I/O FT_f I/O FT_f I/O FT_f I/O FT I/O FT_f Notes 23 UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions (5) SWDIO-JTMS, TIM16_CH1N, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3, SAI1_SD_B, EVENTOUT - (5) SWCLK-JTCK, LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, SAI1_FS_B, EVENTOUT - (5) JTDI, TIM2_CH1, TIM8_CH1, TIM20_ETR, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, UART4_RTS_DE, TIM1_BKIN, TIM2_ETR, - - TIM8_CH1N, UART4_TX, SPI3_SCK/I2S3_CK, USART3_TX, EVENTOUT - - TIM8_CH2N, UART4_RX, SPI3_MISO, USART3_RX, I2C3_SDA, EVENTOUT - - - - - A3 54 A6 68 81 PC12 I/O FT - TIM8_CH3N, UART5_TX, SPI3_MOSI/I2S3_SD, USART3_CK, UCPD1_FRSTX, EVENTOUT - - - - - - 69 82 PD0 I/O FT - TIM8_CH4N, FDCAN1_RX, EVENTOUT - - TIM8_CH4, TIM8_BKIN2, FDCAN1_TX, EVENTOUT - - - - - - - 70 83 PD1 I/O FT DS13122 Rev 3 59/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) (continued) WLCSP64 LQFP64 UFBGA64 LQFP80 LQFP100 - A4 55 B5 71 84 - - - - - - - 85 PD2 I/O PD3 I/O Notes LQFP48 - I/O structure UFQFPN48 - Pin name (function after reset) Pin type UFQFPN32 Pin Number Alternate functions Additional functions FT - TIM3_ETR, TIM8_BKIN, UART5_RX, EVENTOUT - - TIM2_CH1/TIM2_ETR, USART2_CTS, QUADSPI1_BK2_NCS, EVENTOUT - - FT - - - - - - - 86 PD4 I/O FT - TIM2_CH2, USART2_RTS_DE, QUADSPI1_BK2_IO0, EVENTOUT - - - - - - - 87 PD5 I/O FT - USART2_TX, QUADSPI1_BK2_IO1, EVENTOUT - - TIM2_CH4, SAI1_D1, USART2_RX, QUADSPI1_BK2_IO2, SAI1_SD_A, EVENTOUT - - TIM2_CH3, USART2_CK, QUADSPI1_BK2_IO3, EVENTOUT - (5) JTDO/TRACESWO, TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, SAI1_SCK_B, EVENTOUT - JTRST, TIM16_CH1, TIM3_CH1, TIM8_CH2N, SPI1_MISO, SPI3_MISO, USART2_RX, UART5_RTS_DE, TIM17_BKIN, SAI1_MCLK_B, EVENTOUT UCPD1_CC2 - - - 26 27 - 41 42 60/199 - - 40 41 - - D4 C5 - - 56 57 - - A5 C4 - - 72 73 88 89 90 91 PD6 PD7 PB3 PB4 I/O I/O I/O I/O FT FT FT FT_ c DS13122 Rev 3 (4) (5) STM32G491xC STM32G491xE Pinouts and pin description Table 12. STM32G491xC/xE pin definition(1) (continued) 29 30 31 - 43 44 45 46 47 43 44 45 46 A5 B5 A6 B6 A7 58 59 60 61 62 B4 A4 A3 B3 A2 74 75 76 77 78 92 93 94 95 96 I/O structure I/O FT_f PB5 PB7 PB8-BOOT0 Alternate functions Additional functions - TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, FDCAN2_RX, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B, UART5_CTS, EVENTOUT - FT_ c TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, (4) COMP4_OUT, FDCAN2_TX, TIM8_BKIN2, LPTIM1_ETR, SAI1_FS_B, EVENTOUT I/O FT_f TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2, UART4_CTS, EVENTOUT PVD_IN I/O FT_f (6) TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, TIM1_BKIN, SAI1_MCLK_A, EVENTOUT - I/O FT_f TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT, FDCAN1_TX, TIM8_CH3, TIM1_CH3N, SAI1_FS_A, EVENTOUT - I/O PB6 PB9 Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 LQFP48 42 Pin name (function after reset) Notes 28 UFQFPN48 UFQFPN32 Pin Number DS13122 Rev 3 - - UCPD1_CC1 61/199 68 Pinouts and pin description STM32G491xC STM32G491xE Table 12. STM32G491xC/xE pin definition(1) (continued) - - - - - 97 PE0 I/O I/O structure Pin type LQFP100 LQFP80 UFBGA64 LQFP64 WLCSP64 - Pin name (function after reset) FT Notes - LQFP48 UFQFPN48 UFQFPN32 Pin Number Alternate functions Additional functions - TIM4_ETR, TIM20_CH4N, TIM16_CH1, TIM20_ETR, USART1_TX, EVENTOUT - - - - - - - - - 98 PE1 I/O FT - TIM17_CH1, TIM20_CH4, USART1_RX, EVENTOUT 32 - 47 B7 63 B2 79 99 VSS S - - - - 1 48 48 A8 64 A1 80 100 VDD S - - - - 1. Function availability depends on the chosen device. 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). 3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit MCUs". 4. After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1, UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down on PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have UCPD_CC functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the UCPD_DBCC pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead battery disable) in the PWR_CR3 register. 5. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. 6. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left unconnected. 62/199 DS13122 Rev 3 Alternate functions Table 13. Alternate function AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PA0 - TIM2_CH1 - - - - - USART2_CTS COMP1_OUT TIM8_BKIN TIM8_ETR - - - TIM2_ET R EVENT OUT PA1 RTC_REFIN TIM2_CH2 - - - - - USART2_RTS _DE - TIM15_CH1 N - - - - - EVENT OUT PA2 - TIM2_CH3 - - - - - USART2_TX COMP2_OUT TIM15_CH1 QUADSPI1_ BK1_NCS - LPUART1_T X - UCPD1_F RSTX EVENT OUT PA3 - TIM2_CH4 - SAI1_CK1 - - - USART2_RX - TIM15_CH2 QUADSPI1_ CLK - LPUART1_R X SAI1_M CLK_A - EVENT OUT PA4 - - TIM3_CH2 - - SPI1_NSS SPI3_NSS/I2 S3_WS USART2_CK - - - - - SAI1_FS _B - EVENT OUT PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - - - - - - - UCPD1_F RSTX EVENT OUT PA6 - TIM16_CH1 TIM3_CH1 - TIM8_BKIN SPI1_MISO TIM1_BKIN - COMP1_OUT - QUADSPI1_ BK1_IO3 - LPUART1_C TS - - EVENT OUT PA7 - TIM17_CH1 TIM3_CH2 - TIM8_CH1N SPI1_MOSI TIM1_CH1N - COMP2_OUT - QUADSPI1_ BK1_IO2 - - - UCPD1_F RSTX EVENT OUT PA8 MCO - I2C3_SCL - I2C2_SDA I2S2_MCK TIM1_CH1 USART1_CK - - TIM4_ETR - SAI1_CK2 - SAI1_SC K_A EVENT OUT PA9 - - I2C3_SMBA - I2C2_SCL I2S3_MCK TIM1_CH2 USART1_TX - TIM15_BKIN TIM2_CH3 - - - SAI1_FS_ A EVENT OUT PA10 - TIM17_BKIN - USB_CRS_S YNC I2C2_SMBA SPI2_MISO TIM1_CH3 USART1_RX - - TIM2_CH4 TIM8_BK IN SAI1_D1 - SAI1_SD_ A EVENT OUT PA11 - - - - - SPI2_MOSI/I 2S2_SD TIM1_CH1N USART1_CTS COMP1_OUT FDCAN1_RX TIM4_CH1 TIM1_CH 4 TIM1_BKIN2 - - EVENT OUT PA12 - TIM16_CH1 - - - I2SCKIN TIM1_CH2N USART1_RTS _DE COMP2_OUT FDCAN1_TX TIM4_CH2 TIM1_ET R - - - EVENT OUT PA13 SWDIOJTMS TIM16_CH1N - - I2C1_SCL IR_OUT - USART3_CTS - - TIM4_CH3 - - SAI1_SD _B - EVENT OUT PA14 SWCLKJTCK LPTIM1_OUT - - I2C1_SDA TIM8_CH2 TIM1_BKIN USART2_TX - - - - - SAI1_FS _B - EVENT OUT PA15 JTDI TIM2_CH1 TIM8_CH1 TIM20_ETR I2C1_SCL SPI1_NSS SPI3_NSS/I2 S3_WS USART2_RX UART4_RTS_ DE TIM1_BKIN - - - - TIM2_ET R EVENT OUT DS13122 Rev 3 Port A Port 63/199 Pinouts and pin description AF0 STM32G491xC STM32G491xE 4.10 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PB0 - - TIM3_CH3 - TIM8_CH2N - TIM1_CH2N - - - QUADSPI1_ BK1_IO1 - - - UCPD1_F RSTX EVENT OUT PB1 - - TIM3_CH4 - TIM8_CH3N - TIM1_CH3N - COMP4_OUT - QUADSPI1_ BK1_IO0 - LPUART1_R TS_DE - - EVENT OUT PB2 RTC_OUT2 LPTIM1_OUT - TIM20_CH1 I2C3_SMBA - - - - - QUADSPI1_ BK2_IO1 - - - - EVENT OUT PB3 JTDO/TRAC ESWO TIM2_CH2 TIM4_ETR USB_CRS_S YNC TIM8_CH1N SPI1_SCK SPI3_SCK/I2 S3_CK USART2_TX - - TIM3_ETR - - - SAI1_SC K_B EVENT OUT PB4 JTRST TIM16_CH1 TIM3_CH1 - TIM8_CH2N SPI1_MISO SPI3_MISO USART2_RX UART5_RTS_ DE - TIM17_BKIN - - - SAI1_MC LK_B EVENT OUT PB5 - TIM16_BKIN TIM3_CH2 TIM8_CH3N I2C1_SMBA SPI1_MOSI SPI3_MOSI/I 2S3_SD USART2_CK I2C3_SDA FDCAN2_RX TIM17_CH1 LPTIM1_ IN1 SAI1_SD_B - UART5_C TS EVENT OUT PB6 - TIM16_CH1N TIM4_CH1 - - TIM8_CH1 TIM8_ETR USART1_TX COMP4_OUT FDCAN2_TX TIM8_BKIN2 LPTIM1_ ETR - - SAI1_FS_ B EVENT OUT PB7 - TIM17_CH1N TIM4_CH2 - I2C1_SDA TIM8_BKIN - USART1_RX COMP3_OUT - TIM3_CH4 LPTIM1_ IN2 - - UART4_C TS EVENT OUT PB8 - TIM16_CH1 TIM4_CH3 SAI1_CK1 I2C1_SCL - - USART3_RX COMP1_OUT FDCAN1_RX TIM8_CH2 - TIM1_BKIN - SAI1_MC LK_A EVENT OUT PB9 - TIM17_CH1 TIM4_CH4 SAI1_D2 I2C1_SDA - IR_OUT USART3_TX COMP2_OUT FDCAN1_TX TIM8_CH3 - TIM1_CH3N - SAI1_FS_ A EVENT OUT PB10 - TIM2_CH3 - - - - - USART3_TX LPUART1_RX - QUADSPI1_ CLK - TIM1_BKIN - SAI1_SC K_A EVENT OUT PB11 - TIM2_CH4 - - - - - USART3_RX LPUART1_TX - QUADSPI1_ BK1_NCS - - - - EVENT OUT PB12 - - - - I2C2_SMBA SPI2_NSS/I2 S2_WS TIM1_BKIN USART3_CK LPUART1_RTS _DE FDCAN2_RX - - - - - EVENT OUT PB13 - - - - - SPI2_SCK/I2 S2_CK TIM1_CH1N USART3_CTS LPUART1_CTS FDCAN2_TX - - - - - EVENT OUT PB14 - TIM15_CH1 - - - SPI2_MISO TIM1_CH2N USART3_RTS _DE COMP4_OUT - - - - - - EVENT OUT PB15 RTC_REFIN TIM15_CH2 TIM15_CH1N COMP3_OUT TIM1_CH3N SPI2_MOSI/I 2S2_SD - - - - - - - - - EVENT OUT DS13122 Rev 3 Port B Port STM32G491xC STM32G491xE AF0 Pinouts and pin description 64/199 Table 13. Alternate function (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PC0 - LPTIM1_IN1 TIM1_CH1 - - - - - LPUART1_RX - - - - - - EVENT OUT PC1 - LPTIM1_OUT TIM1_CH2 - - - - - LPUART1_TX - QUADSPI1_ BK2_IO0 - - SAI1_SD _A - EVENT OUT PC2 - LPTIM1_IN2 TIM1_CH3 COMP3_OUT - - TIM20_CH2 - - - QUADSPI1_ BK2_IO1 - - - - EVENT OUT PC3 - LPTIM1_ETR TIM1_CH4 SAI1_D1 - - TIM1_BKIN2 - - - QUADSPI1_ BK2_IO2 - - SAI1_SD _A - EVENT OUT PC4 - - TIM1_ETR - I2C2_SCL - - USART1_TX - - QUADSPI1_ BK2_IO3 - - - - EVENT OUT PC5 - - TIM15_BKIN SAI1_D3 - - TIM1_CH4N USART1_RX - - - - - - - EVENT OUT PC6 - - TIM3_CH1 - TIM8_CH1 - I2S2_MCK - - - - - - - - EVENT OUT PC7 - - TIM3_CH2 - TIM8_CH2 - I2S3_MCK - - - - - - - - EVENT OUT PC8 - - TIM3_CH3 - TIM8_CH3 - TIM20_CH3 - I2C3_SCL - - - - - - EVENT OUT PC9 - - TIM3_CH4 - TIM8_CH4 I2SCKIN TIM8_BKIN2 - I2C3_SDA - - - - - - EVENT OUT PC10 - - - - TIM8_CH1N UART4_TX SPI3_SCK/I2 S3_CK USART3_TX - - - - - - - EVENT OUT PC11 - - - - TIM8_CH2N UART4_RX SPI3_MISO USART3_RX I2C3_SDA - - - - - - EVENT OUT PC12 - - - - TIM8_CH3N UART5_TX SPI3_MOSI/I 2S3_SD USART3_CK - - - - - - UCPD1_F RSTX EVENT OUT PC13 - - TIM1_BKIN - TIM1_CH1N - TIM8_CH4N - - - - - - - - EVENT OUT PC14 - - - - - - - - - - - - - - - EVENT OUT PC15 - - - - - - - - - - - - - - - EVENT OUT DS13122 Rev 3 Port C Port 65/199 Pinouts and pin description AF0 STM32G491xC STM32G491xE Table 13. Alternate function (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PD0 - - - - - - TIM8_CH4N - - FDCAN1_RX - - - - - EVENT OUT PD1 - - - - TIM8_CH4 - TIM8_BKIN2 - - FDCAN1_TX - - - - - EVENT OUT PD2 - - TIM3_ETR - TIM8_BKIN UART5_RX - - - - - - - - - EVENT OUT PD3 - - TIM2_CH1/TI M2_ETR - - - - USART2_CTS - - QUADSPI1_ BK2_NCS - - - - EVENT OUT PD4 - - TIM2_CH2 - - - - USART2_RTS _DE - - QUADSPI1_ BK2_IO0 - - - - EVENT OUT PD5 - - - - - - - USART2_TX - - QUADSPI1_ BK2_IO1 - - - - EVENT OUT PD6 - - TIM2_CH4 SAI1_D1 - - - USART2_RX - - QUADSPI1_ BK2_IO2 - - SAI1_SD _A - EVENT OUT PD7 - - TIM2_CH3 - - - - USART2_CK - - QUADSPI1_ BK2_IO3 - - - - EVENT OUT PD8 - - - - - - - USART3_TX - - - - - - - EVENT OUT PD9 - - - - - - - USART3_RX - - - - - - - EVENT OUT PD10 - - - - - - - USART3_CK - - - - - - - EVENT OUT PD11 - - - - - - - USART3_CTS - - - - - - - EVENT OUT PD12 - - TIM4_CH1 - - - - USART3_RTS _DE - - - - - - - EVENT OUT PD13 - - TIM4_CH2 - - - - - - - - - - - - EVENT OUT PD14 - - TIM4_CH3 - - - - - - - - - - - - EVENT OUT PD15 - - TIM4_CH4 - - - SPI2_NSS - - - - - - - - EVENT OUT DS13122 Rev 3 Port D Port STM32G491xC STM32G491xE AF0 Pinouts and pin description 66/199 Table 13. Alternate function (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PE0 - - TIM4_ETR TIM20_CH4N TIM16_CH1 - TIM20_ETR USART1_TX - - - - - - - EVENT OUT PE1 - - - - TIM17_CH1 - TIM20_CH4 USART1_RX - - - - - - - EVENT OUT PE2 TRACECK - TIM3_CH1 SAI1_CK1 - - TIM20_CH1 - - - - - - SAI1_M CLK_A - EVENT OUT PE3 TRACED0 - TIM3_CH2 - - - TIM20_CH2 - - - - - - SAI1_SD _B - EVENT OUT PE4 TRACED1 - TIM3_CH3 SAI1_D2 - - TIM20_CH1N - - - - - - SAI1_FS _A - EVENT OUT PE5 TRACED2 - TIM3_CH4 SAI1_CK2 - - TIM20_CH2N - - - - - - SAI1_SC K_A - EVENT OUT PE6 TRACED3 - - SAI1_D1 - - TIM20_CH3N - - - - - - SAI1_SD _A - EVENT OUT PE7 - - TIM1_ETR - - - - - - - - - - SAI1_SD _B - EVENT OUT PE8 - - TIM1_CH1N - - - - - - - - - - SAI1_SC K_B - EVENT OUT PE9 - - TIM1_CH1 - - - - - - - - - - SAI1_FS _B - EVENT OUT PE10 - - TIM1_CH2N - - - - - - - QUADSPI1_ CLK - - SAI1_M CLK_B - EVENT OUT PE11 - - TIM1_CH2 - - - - - - - QUADSPI1_ BK1_NCS - - - - EVENT OUT PE12 - - TIM1_CH3N - - - - - - - QUADSPI1_ BK1_IO0 - - - - EVENT OUT PE13 - - TIM1_CH3 - - - - - - - QUADSPI1_ BK1_IO1 - - - - EVENT OUT PE14 - - TIM1_CH4 - - - TIM1_BKIN2 - - - QUADSPI1_ BK1_IO2 - - - - EVENT OUT PE15 - - TIM1_BKIN - - - TIM1_CH4N USART3_RX - - QUADSPI1_ BK1_IO3 - - - - EVENT OUT DS13122 Rev 3 Port E Port 67/199 Pinouts and pin description AF0 STM32G491xC STM32G491xE Table 13. Alternate function (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS_AF LPTIM1/TIM2 /15/16/17 COMP1/I2C3 /TIM1/2/3/4/8/ 15/20 COMP3/SAI1/ TIM8/15/20/U SB I2C1/2/3/TIM 1/8/16/17 I2S2/3/Infrar ed/SPI1/2/TI M8/UART4/5 I2S2/3/Infrare d/SPI2/3/TIM 1/8/20 USART1/2/3 COMP1/2/3/4/I 2C3/LPUART1/ UART4/5 FDCAN1/2/T IM1/8/15 QUADSPI1/ TIM2/3/4/8/1 7 LPTIM1/ TIM1/8 LPUART1/S AI1/TIM1 SAI1 SAI1/TIM 2/15/UAR T4/5/UCP D1 EVENT PF0 - - - - I2C2_SDA SPI2_NSS/I2 S2_WS TIM1_CH3N - - - - - - - - EVENT OUT PF1 - - - - - SPI2_SCK/I2 S2_CK - - - - - - - - - EVENT OUT PF2 - - TIM20_CH3 - I2C2_SMBA - - - - - - - - - - EVENT OUT PF9 - - TIM20_BKIN TIM15_CH1 - SPI2_SCK - - - - QUADSPI1_ BK1_IO1 - - SAI1_FS _B - EVENT OUT PF10 - - TIM20_BKIN 2 TIM15_CH2 - SPI2_SCK - - - - QUADSPI1_ CLK - - SAI1_D3 - EVENT OUT PG10 MCO - - - - - - - - - - - - - - EVENT OUT Port G Port F Port Pinouts and pin description 68/199 Table 13. Alternate function (continued) DS13122 Rev 3 STM32G491xC STM32G491xE STM32G491xC STM32G491xE Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 13. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 14. Figure 13. Pin loading conditions Figure 14. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 DS13122 Rev 3 MS19211V1 69/199 164 Electrical characteristics 5.1.6 STM32G491xC STM32G491xE Power supply scheme Figure 15. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch VDD VCORE n x VDD Regulator OUT n x 100 nF GPIOs IN +1 x 4.7 μF Level shifter VDDIO IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDA VREF+ VREF VREF+ 10 nF +1 μF Reset block Temp. sensor PLL, HSI16, HSI48 VDDA 100 nF +1 μF VREF- ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF Standby circuitry (Wakeup logic, IWDG) VSSA MS60206V1 Caution: 70/199 Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS13122 Rev 3 STM32G491xC STM32G491xE 5.1.7 Electrical characteristics Current consumption measurement Figure 16. Current consumption measurement IDD_VBAT IDD IDDA VBAT VDD VDDA MS60200V1 The IDD_ALL parameters given in Table 21 to Table 33 represent the total MCU consumption including the current supplying VDD, VDDA and VBAT. 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 14. Voltage characteristics(1) Symbol VDD - VSS VIN(2) |∆VDDx| |VSSx-VSS| Ratings Min Max -0.3 4.0 Input voltage on FT_xxx pins except FT_c pins VSS-0.3 min (VDD, VDDA) + 4.0(3)(4) Input voltage on FT_c pins VSS-0.3 5.5 Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on any other pins VSS-0.3 4.0 - 50 - 50 - 0.4 External main supply voltage (including VDD, VDDA, VBAT and VREF+) Variations between different VDDX power pins of the same domain Variations between all the different ground pins VREF+-VDDA Allowed voltage difference for VREF+ > VDDA (5) Unit V mV V 1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. DS13122 Rev 3 71/199 164 Electrical characteristics STM32G491xC STM32G491xE 2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 15. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 150 ∑IVSS (sink)(1) 150 IVDD(PIN) IVSS(PIN) IIO(PIN) Total current out of sum of all VSS ground lines (1) 100 (sink)(1) 100 Maximum current into each VDD power pin (source) Maximum current out of each VSS ground pin Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin ∑IIO(PIN) Total output current sunk by sum of all I/Os and control Unit mA 20 pins(2) 100 Total output current sourced by sum of all I/Os and control pins(2) IINJ(PIN)(3) Injected current on FT_xxx, TT_xx, NRST pins ∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 100 -5/0(4) ±25 1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14: Voltage characteristics for the minimum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 16. Thermal characteristics Symbol TSTG TJ 72/199 Ratings Storage temperature range Maximum junction temperature DS13122 Rev 3 Value Unit –65 to +150 °C 150 °C STM32G491xC STM32G491xE Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 17. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 170 fPCLK1 Internal APB1 clock frequency - 0 170 fPCLK2 Internal APB2 clock frequency - 0 170 Standard operating voltage - 1.71(1) 3.6 VDD VDDA Analog supply voltage ADC or COMP used 1.62 DAC 1 MSPS or DAC 15 MSPS 1.71 OPAMP used 2.0 VREFBUF used 2.4 ADC, DAC, OPAMP, COMP, VREFBUF not used VBAT VIN Backup operating voltage - TA TJ Power dissipation V 3.6 TT_xx -0.3 VDD+0.3 FT_c I/O -0.3 5 -0.3 MIN(MIN(VDD, VDDA)+3.6 V, 5.5 V)(2)(3) V V See Section 6.10: Thermal characteristics for application appropriate thermal resistance and package. Power dissipation is then calculated according ambient temperature (TA) and maximum junction temperature (TJ) and selected thermal resistance. Ambient temperature for the suffix 6 version Maximum power dissipation -40 85 Low-power dissipation(4) -40 105 Ambient temperature for the suffix 3 version Maximum power dissipation -40 125 Low-power dissipation(4) -40 130 Suffix 6 version -40 105 Suffix 3 version -40 130 Junction temperature range V 3.6 3.6 I/O input voltage MHz 3.6 1.55 All I/O except TT_xx and FT_c PD 0 Unit mW °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10: Thermal characteristics). DS13122 Rev 3 73/199 164 Electrical characteristics 5.3.2 STM32G491xC STM32G491xE Operating conditions at power-up / power-down The parameters given in Table 18 are derived from tests performed under the ambient temperature condition summarized in Table 17. Table 18. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD Min Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ - VDD fall time rate VDDA rise time rate tVDDA 5.3.3 Conditions - VDDA fall time rate Unit µs/V µs/V Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under the ambient temperature conditions summarized in Table 17: General operating conditions. Table 19. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) 74/199 Parameter Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 VDD rising DS13122 Rev 3 V V V V V V V V V STM32G491xC STM32G491xE Electrical characteristics Table 19. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Symbol Parameter VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Unit V V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and IDD (BOR_PVD)(2) PVD consumption from VDD - - 1.1 1.6 µA Vhyst_BOR_PVD VPVM1 VDDA peripheral voltage monitoring (COMP/ADC) Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM2 VDDA peripheral voltage monitoring (OPAMP/DAC) Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM1 PVM1 hysteresis - - 10 - mV Vhyst_PVM2 PVM2 hysteresis - - 10 - mV - - 2 - µA IDD PVM1 and PVM2 (PVM1/PVM2) consumption from VDD (2) 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS13122 Rev 3 75/199 164 Electrical characteristics 5.3.4 STM32G491xC STM32G491xE Embedded voltage reference The parameters given in Table 20 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions. Table 20. Embedded internal voltage reference Symbol Parameter VREFINT Internal reference voltage Conditions Min –40 °C < TA < +130 °C 1.182 1.212 Max Unit 1.232 V ADC sampling time when reading the internal reference voltage - 4(2) - - µs Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs VREFINT buffer consumption from VDD IDD(VREFINTBUF) when converted by ADC - - 12.5 20(2) µA tS_vrefint (1) tstart_vrefint ∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV TCoeff Average temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm Average voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V 24 25 26 49 50 51 74 75 76 VDDCoeff VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage - 1. The shortest sampling time is determined in the application by multiple iterations. 2. Guaranteed by design. 76/199 Typ DS13122 Rev 3 % VREFINT STM32G491xC STM32G491xE Electrical characteristics Figure 17. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V2 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code The current consumption is measured as described in Figure 16: Current consumption measurement. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “number of wait states according to CPU clock (HCLK) frequency” available in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit MCUs"). • When the peripherals are enabled fPCLK = fHCLK • The voltage scaling Range 1 is adjusted to fHCLK frequency as follows: – Voltage Range 1 Boost mode for 150 MHz < fHCLK ≤ 170 MHz – Voltage Range 1 Normal mode for 26 MHz < fHCLK ≤ 150 MHz The parameters given in Table 26 to Table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions. DS13122 Rev 3 77/199 164 Condition Symbol Parameter - Typ Voltage scaling Range 2 DS13122 Rev 3 IDD (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK Max Unit 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 26 MHz 3.55 3.80 4.40 5.35 6.85 3.80 4.60 7.10 11.0 16.0 16 MHz 2.25 2.45 3.10 4.00 5.50 2.60 3.40 5.90 9.00 15.0 8 MHz 1.25 1.45 2.05 2.95 4.45 1.60 2.50 4.90 8.00 14.0 4 MHz 0.715 0.915 1.50 2.40 3.90 1.10 2.00 4.40 7.50 13.0 2 MHz 0.445 0.645 1.25 2.15 3.60 0.850 1.70 4.10 7.20 13.0 1 MHz 0.310 0.510 1.10 2.00 3.50 0.720 1.60 4.00 7.10 13.0 100 KHz 0.195 0.390 0.990 1.90 3.35 0.600 1.40 3.90 7.00 13.0 Range 1 Boost 170 MHz mode 26.5 27.0 28.0 29.5 31.5 28.0 29.0 33.0 38.0 45.0 150 MHz 22.0 22.0 23.0 24.5 26.5 23.0 24.0 28.0 32.0 38.0 120 MHz 17.5 18.0 19.0 20.0 22.0 19.0 20.0 23.0 27.0 34.0 80 MHz 12.0 12.0 13.0 14.5 16.0 13.0 14.0 18.0 22.0 28.0 72 MHz 10.5 11.0 12.0 13.0 15.0 12.0 13.0 16.0 20.0 27.0 64 MHz 9.55 9.90 11.0 12.0 14.0 11.0 12.0 15.0 19.0 26.0 48 MHz 7.65 8.05 8.95 10.0 12.0 7.80 9.20 13.0 17.0 24.0 32 MHz 5.25 5.55 6.40 7.60 9.40 5.60 6.80 11.0 15.0 21.0 24 MHz 3.90 4.20 5.00 6.15 7.95 4.40 5.70 8.90 13.0 20.0 16 MHz 2.70 3.00 3.75 4.90 6.70 3.30 4.50 7.70 12.0 19.0 mA STM32G491xC STM32G491xE Range 1 Electrical characteristics 78/199 Table 21. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) Condition Symbol Parameter - fHCLK = fHSE all peripherals disable Supply current IDD (LPRun) in Low-power run mode fHCLK = fHSI / HPRE all peripherals disable Typ Voltage scaling fHCLK Max Unit DS13122 Rev 3 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 2 MHz 390 590 1200 2000 3500 990 2000 4900 8600 15000 1 MHz 240 440 1050 1850 3350 840 1800 4700 8400 15000 250 KHz 130 330 940 1700 3250 690 1700 4700 8400 15000 62.5 KHz 100 300 915 1700 3200 670 1700 4700 8400 15000 2 MHz 815 1000 1600 2400 3950 1500 2600 5400 9300 16000 1 MHz 695 890 1500 2300 3800 1400 2400 5300 9100 15000 250 KHz 605 800 1400 2200 3750 1300 2200 5200 9000 15000 62.5 KHz 580 775 1400 2200 3700 1200 2300 5200 9000 15000 μA STM32G491xC STM32G491xE Table 21. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued) Electrical characteristics 79/199 Typ Condition Symbol Parameter - Voltage scaling Range 2 DS13122 Rev 3 IDD (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK Max Unit 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 26 MHz 3.15 3.40 4.05 4.95 6.50 3.40 4.30 6.70 9.80 15.0 16 MHz 2.00 2.25 2.85 3.75 5.30 2.40 3.20 5.60 8.80 14.0 8 MHz 1.10 1.30 1.95 2.85 4.35 1.50 2.30 4.70 7.90 13.0 4 MHz 0.650 0.855 1.45 2.35 3.90 0.970 1.90 4.30 7.40 13.0 2 MHz 0.415 0.615 1.20 2.10 3.65 0.750 1.70 4.10 7.20 13.0 1 MHz 0.295 0.495 1.10 2.00 3.50 0.640 1.50 3.90 7.10 13.0 100 KHz 0.190 0.385 0.985 1.90 3.40 0.530 1.40 3.80 7.00 12.0 Range 1 Boost 170 MHz mode 23.5 24.0 25.0 26.5 28.5 25.0 26.0 30.0 35.0 42.0 150 MHz 19.5 19.5 20.5 22.0 24.0 20.0 22.0 25.0 29.0 36.0 120 MHz 15.5 16.0 17.0 18.0 20.0 17.0 18.0 21.0 25.0 32.0 80 MHz 10.5 11.0 11.5 13.0 15.0 12.0 13.0 16.0 20.0 27.0 72 MHz 9.50 9.85 10.5 12.0 14.0 11.0 12.0 15.0 19.0 26.0 64 MHz 8.50 8.85 9.65 11.0 12.5 9.00 11.0 14.0 18.0 25.0 48 MHz 6.85 7.25 8.10 9.30 11.0 7.00 8.40 12.0 16.0 23.0 32 MHz 4.70 5.05 5.85 7.00 8.90 5.10 6.30 9.50 14.0 21.0 24 MHz 3.50 3.80 4.60 5.75 7.60 4.00 5.30 8.50 13.0 19.0 16 MHz 2.45 2.70 3.50 4.60 6.45 3.00 4.20 7.40 12.0 18.0 Range 1 Electrical characteristics 80/199 Table 22. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 mA STM32G491xC STM32G491xE Condition Symbol Parameter - fHCLK = fHSE all peripherals disable Supply current IDD (LPRun) in Low-power run mode fHCLK = fHSI / HPRE all peripherals disable Typ Voltage scaling fHCLK Max Unit DS13122 Rev 3 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 2 MHz 350 550 1150 1950 3450 840 1900 5000 8700 15000 1 MHz 220 420 1050 1850 3450 710 1800 4800 8700 15000 250 KHz 120 320 930 1750 3350 610 1800 4500 8700 15000 62.5 KHz 93.0 290 905 1750 3300 580 1800 4600 8400 15000 2 MHz 775 970 1600 2450 4000 1500 2600 5400 9200 15000 1 MHz 670 865 1450 2350 3900 1400 2400 5300 9200 15000 250 KHz 595 790 1400 2250 3850 1300 2300 5200 8900 15000 62.5 KHz 575 770 1400 2250 3800 1300 2300 5200 8900 15000 μA STM32G491xC STM32G491xE Table 22. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 (continued) Electrical characteristics 81/199 Conditions Symbol Parameter Code - Voltage scaling Range2 fHCLK=26MHz DS13122 Rev 3 IDD (Run) Supply current in Run mode fHCLK= fHSE up to 48 MHZ included, bypass Range 1 mode PLL ON above = 150 MHz f 48 MHz all peripherals HCLK disable IDD (LPRun) Supply current in Low-power run SYSCLK source is HSI fHCLK = 2 MHz all peripherals disable TYP Single Bank Mode Unit 25°C Unit 25°C Pseudo-dhrystone 3.55 mA 137 Coremark 3.60 mA 138 Dhrystone2.1 3.55 mA 137 Fibonacci 3.75 mA 144 While(1) 3.10 mA 119 Pseudo-dhrystone 22.0 mA 147 Coremark 21.5 mA 143 Dhrystone2.1 22.0 mA 147 Fibonacci 23.0 mA 153 While(1) 19.0 mA 127 Pseudo-dhrystone 26.5 mA 156 Coremark 26.5 mA 156 Dhrystone2.1 26.5 mA 156 Fibonacci 27.5 mA 162 While(1) 23.0 mA 135 Pseudo-dhrystone 815 uA 408 Coremark 840 uA 420 Dhrystone2.1 835 uA 418 Fibonacci 850 uA 425 While(1) 795 uA 398 µA/MHz µA/MHz - µA/MHz µA/MHz STM32G491xC STM32G491xE Range 1 Boost mode fHCLK= 170 MHz TYP Single Bank Mode Electrical characteristics 82/199 Table 23. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol TYP 25°C Parameter Code - Voltage scaling Range2 fHCLK=26 MHz DS13122 Rev 3 IDD (Run) fHCLK = fHSE up to 48 MHZ Range 1 Supply current in included, bypass mode PLL ON above 48 MHz all fHCLK= 150 MHz Run mode peripherals disable Range 1 Boost mode fHCLK= 170 MHz SYSCLK source is HSI Supply current in fHCLK = 2 MHz Low-power run all peripherals disable Unit Single bank mode 83/199 Pseudo-dhrystone 3.15 mA 121 Coremark 3.25 mA 125 Dhrystone2.1 3.15 mA 121 Fibonacci 3.15 mA 121 While(1) 3.25 mA 125 Pseudo-dhrystone 19.5 mA 130 Coremark 20.0 mA 133 Dhrystone2.1 19.5 mA 130 Fibonacci 20.0 mA 133 While(1) 17.0 mA 113 Pseudo-dhrystone 23.5 mA 138 Coremark 24.5 mA 144 Dhrystone2.1 23.5 mA 138 Fibonacci 24.0 mA 141 While(1) 21.0 mA 124 Pseudo-dhrystone 775 uA 388 Coremark 815 uA 408 Dhrystone2.1 800 uA 400 Fibonacci 805 uA 403 While(1) 770 uA 385 Unit µA/MHz µA/MHz µA/MHz µA/MHz Electrical characteristics IDD (LPRun) Single bank mode TYP 25°C STM32G491xC STM32G491xE Table 24. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions Symbol TYP 25°C Parameter Code - Voltage scaling Range2 fHCLK=26 MHz DS13122 Rev 3 IDD (Run) fHCLK = fHSE up to 48 MHZ Range 1 Supply current in included, bypass mode PLL ON above 48 MHz all fHCLK= 150 MHz Run mode peripherals disable Range 1 Boost mode fHCLK= 170 MHz SYSCLK source is HSI Supply current in fHCLK = 2 MHz Low-power run all peripherals disable Unit Single bank mode Pseudo-dhrystone 2.55 mA 98 Coremark 2.65 mA 102 Dhrystone2.1 2.55 mA 98 Fibonacci 2.45 mA 94 While(1) 2.35 mA 90 Pseudo-dhrystone 15.0 mA 100 Coremark 15.5 mA 103 Dhrystone2.1 15.0 mA 100 Fibonacci 14.5 mA 97 While(1) 13.5 mA 90 Pseudo-dhrystone 18.0 mA 106 Coremark 19.0 mA 112 Dhrystone2.1 18.0 mA 106 Fibonacci 17.5 mA 103 While(1) 16.5 mA 97 Pseudo-dhrystone 720 uA 360 Coremark 760 uA 380 Dhrystone2.1 745 uA 373 Fibonacci 735 uA 368 While(1) 725 uA 363 Unit µA/MHz µA/MHz µA/MHz µA/MHz STM32G491xC STM32G491xE IDD (LPRun) Single bank mode TYP 25°C Electrical characteristics 84/199 Table 25. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM2 Conditions Symbol TYP 25°C Parameter Code - Voltage scaling Range2 fHCLK=26 MHz DS13122 Rev 3 IDD (Run) fHCLK = fHSE up to 48 MHZ Range 1 Supply current in included, bypass mode PLL ON above 48 MHz all fHCLK= 150 MHz Run mode peripherals disable Range 1 Boost mode fHCLK= 170 MHz SYSCLK source is HSI Supply current in fHCLK = 2 MHz Low-power run all peripherals disable Unit Single bank mode Pseudo-dhrystone 3.10 mA 119 Coremark 3.35 mA 129 Dhrystone2.1 3.10 mA 119 Fibonacci 3.55 mA 137 While(1) 3.40 mA 131 Pseudo-dhrystone 18.5 mA 123 Coremark 20.5 mA 137 Dhrystone2.1 18.5 mA 123 Fibonacci 22.0 mA 147 While(1) 21.0 mA 140 Pseudo-dhrystone 22.5 mA 132 Coremark 25.0 mA 147 Dhrystone2.1 22.5 mA 132 Fibonacci 27.0 mA 159 While(1) 25.5 mA 150 Pseudo-dhrystone 770 uA 385 Coremark 820 uA 410 Dhrystone2.1 790 uA 395 Fibonacci 830 uA 415 While(1) 820 uA 410 Unit µA/MHz µA/MHz µA/MHz µA/MHz 85/199 Electrical characteristics IDD (LPRun) Single bank mode TYP 25°C STM32G491xC STM32G491xE Table 26. Typical current consumption in Run and Low-power run modes, with different codes running from CCM Typ Condition Symbol Parameter - Voltage scaling Range 2 DS13122 Rev 3 IDD (Sleep) Supply current in Sleep mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK Max Unit 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 26 MHz 1.20 1.40 2.05 2.95 4.45 1.50 2.30 4.70 7.80 13.0 16 MHz 0.790 1.00 1.60 2.50 4.00 1.20 2.00 4.40 7.50 13.0 8 MHz 0.500 0.705 1.30 2.20 3.70 0.800 1.70 4.10 7.20 13.0 4 MHz 0.345 0.545 1.15 2.05 3.50 0.670 1.60 4.00 7.10 13.0 2 MHz 0.265 0.460 1.05 1.95 3.45 0.600 1.50 3.90 7.00 13.0 1 MHz 0.220 0.420 1.00 1.90 3.40 0.560 1.50 3.90 7.00 13.0 100 KHz 0.185 0.380 0.980 1.85 3.35 0.530 1.40 3.80 6.90 12.0 Range 1 Boost 170 MHz mode 6.45 6.80 7.70 8.95 11.0 7.30 8.70 13.0 17.0 24.0 150 MHz 5.35 5.65 6.50 7.65 9.45 6.10 7.30 11.0 15.0 22.0 120 MHz 4.40 4.70 5.50 6.60 8.45 5.10 6.30 9.50 14.0 20.0 80 MHz 3.10 3.35 4.15 5.25 7.10 3.70 4.90 8.20 13.0 19.0 72 MHz 2.80 3.10 3.90 5.00 6.80 3.50 4.70 7.90 12.0 19.0 64 MHz 2.55 2.85 3.60 4.75 6.55 3.20 4.40 7.60 12.0 19.0 48 MHz 2.40 2.75 3.55 4.70 6.50 2.70 3.80 7.00 12.0 18.0 32 MHz 1.70 2.05 2.85 3.95 5.75 2.10 3.30 6.50 11.0 17.0 24 MHz 1.25 1.55 2.35 3.45 5.25 1.80 3.00 6.20 11.0 17.0 16 MHz 0.930 1.20 2.00 3.10 4.85 1.50 2.70 5.90 9.90 17.0 Range 1 Electrical characteristics 86/199 Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON mA STM32G491xC STM32G491xE Condition Symbol Parameter - Typ Voltage scaling fHCLK = fHSE all peripherals disable IDD (LPSleep) Supply current in Low-power sleep mode fHCLK = fHSI / HPRE all peripherals disable fHCLK Max Unit 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 2 MHz 180 385 1000 1750 3300 1500 2500 5400 9000 15000 1 MHz 135 335 950 1850 3450 1000 2100 5000 8700 15000 250 KHz 100 300 915 1800 3400 600 1700 4700 8200 15000 62.5 KHz 92.5 295 905 1800 3400 590 1600 4100 7400 13000 2 MHz 600 795 1400 2300 3900 1300 2300 5300 8800 15000 1 MHz 585 785 1400 2300 3900 1300 2300 5300 8800 15000 250 KHz 575 775 1400 2250 3900 1300 2300 5300 8800 15000 62.5 KHz 575 770 1400 2250 3900 1300 2300 5300 8800 15000 μA STM32G491xC STM32G491xE Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON (continued) DS13122 Rev 3 Table 28. Current consumption in low-power sleep modes, Flash in power-down Condition Symbol Parameter - fHCLK = fHSE all peripherals disable Voltage scaling - Supply current in low-power sleep mode fHCLK = fHSI all peripherals disable - fHCLK Max Unit 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 2 MHz 175 380 990 1750 3300 670 1700 4800 8500 15000 1 MHz 130 330 945 1850 3450 620 1700 4700 8300 15000 250 KHz 95.5 295 905 1800 3400 590 1700 4500 8300 15000 62.5 KHz 87.0 285 895 1800 3400 530 1400 3800 6900 12000 2 MHz 595 790 1400 2300 3900 1300 2300 5200 9000 15000 1 MHz 580 775 1400 2300 3900 1300 2300 5200 9000 15000 250 KHz 570 765 1350 2250 3850 1300 2200 5200 8800 15000 62.5 KHz 570 765 1350 2250 3850 1000 1900 4300 7400 13000 μA 87/199 Electrical characteristics IDD (LPSleep) Typ Conditions Symbol Parameter 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 64.5 250 800 1600 3000 440 1000 3400 6300 11000 2.4 V 67.5 250 805 1600 3050 440 1000 3500 6400 11000 3.0 V 68.0 250 805 1650 3100 440 1000 3500 6400 12000 3.6 V 68.5 250 810 1650 3100 440 1200 3500 6400 12000 1.8 V 65.5 250 800 1600 3000 440 1000 3400 6300 11000 2.4 V 67.5 250 805 1600 3050 440 1000 3500 6400 11000 3.0 V 68.5 250 805 1650 3100 440 1200 3500 6400 12000 3.6 V 69.0 250 815 1650 3100 450 1200 3500 6400 12000 1.8 V 65.5 250 800 1600 3000 - - - - - 2.4 V 67.5 250 805 1600 3050 - - - - - 3.0 V 68.5 250 805 1650 3100 - - - - - 3.6 V 69.0 250 810 1650 3100 - - - - - 1.8 V 56.5 215 700 1450 - - - - - - 2.4 V 57.0 215 705 1450 - - - - - - 3.0 V 57.0 215 710 1450 - - - - - - 3.6 V 58.0 220 715 1450 - - - - - - Wakeup clock is HSI = 16 MHz, 3.0 V 1.70 - - - - - - - - - Wakeup clock is HSI = 4 MHz, (HPRE divider=4), voltage Range 2 3.0 V 1.25 - - - - - - - - - RTC clocked by LSI DS13122 Rev 3 IDD Supply current RTC clocked by LSE in Stop 1 mode, bypassed at 32768 (Stop 1 with RTC) RTC enabled Hz RTC clocked by LSE quartz in low drive mode at 32768 Hz IDD (Stop 1 with RTC) µA mA 1. Guaranteed by characterization results, unless otherwise specified. STM32G491xC STM32G491xE 25°C Supply current in Stop 1 mode, RTC disabled RTC disabled Supply current during wakeup from Stop 1 mode Unit VDD - IDD (Stop 1) MAX(1) TYP Electrical characteristics 88/199 Table 29. Current consumption in Stop 1 mode Conditions Symbol Parameter - IDD(Stop 0) Supply current in Stop 0 mode, RTC disabled MAX(1) TYP Unit VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 170 365 955 1800 3350 570 1400 3800 6900 12000 2.4 V 170 365 955 1800 3350 570 1400 3800 6900 12000 3V 175 370 960 1850 3350 580 1400 3800 6900 12000 3.6 V 175 370 960 1850 3400 580 1400 3800 6900 12000 µA 1. Guaranteed by characterization results, unless otherwise specified. STM32G491xC STM32G491xE Table 30. Current consumption in Stop 0 mode Table 31. Current consumption in Standby mode Conditions Symbol Parameter DS13122 Rev 3 - No independent watchdog IDD (Standby) Supply current in Standby mode (backup registers retained), RTC disabled With independent watchdog MAX(1) TYP Unit 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 105 325 1650 4750 12500 190 500 2900 7800 21000 2.4 V 115 370 1900 5500 14500 210 570 3200 8800 23000 3V 130 430 2250 6400 17000 230 670 3700 10000 26000 3.6 V 180 560 2700 7600 20000 330 890 4400 12000 30000 1.8 V 285 - - - - - - - - - 2.4 V 335 - - - - - - - - - 3V 395 - - - - - - - - - 3.6 V 495 - - - - - - - - - nA 89/199 Electrical characteristics VDD 25°C Conditions Symbol Parameter 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 435 660 2000 5050 12500 530 850 3200 8100 21000 2.4 V 545 810 2350 5900 15000 650 1200 3700 9200 24000 3V 675 985 2750 6900 17500 800 1400 4200 11000 27000 3.6 V 855 1250 3350 8250 20500 1100 1700 5100 13000 31000 1.8 V 470 - - - - - - - - - 2.4 V 600 - - - - - - - - - 3V 735 - - - - - - - - - 3.6 V 935 - - - - - - - - - 1.8 V 320 540 1900 4950 12500 - - - - - 2.4 V 410 670 2250 5850 15000 - - - - - 3V 530 830 2650 6800 17500 - - - - - 3.6 V 695 1100 3200 8150 20500 - - - - - 1.8 V 455 670 1950 4500 11500 - - - - - RTC clocked by 2.4 V LSE quartz(2) in low 3V drive mode 565 810 2300 5250 13500 - - - - - 705 1000 2700 6100 15500 - - - - - 3.6 V 900 1250 3300 7250 18500 - - - - - 1.8 V 340 1125 4250 9750 20500 - - - - - DS13122 Rev 3 IDD (SRAM2)(3) Supply current to be added in Standby mode when SRAM2 is retained 2.4 V 340 1130 4250 10000 21000 - - - - - 3V 340 1120 4250 9600 21000 - - - - - 3.6 V 345 1140 4250 9900 21500 - - - - - RTC clocked by LSI, with independent watchdog RTC clocked by LSE bypassed at 32768 Hz - nA nA nA STM32G491xC STM32G491xE 55°C RTC clocked by LSI, no independent watchdog Supply current in Standby mode (backup registers (Standby with retained), RTC) RTC enabled Unit VDD 25°C - IDD MAX(1) TYP Electrical characteristics 90/199 Table 31. Current consumption in Standby mode (continued) Conditions Symbol Parameter VDD 25°C - IDD (wakeup Supply current during wakeup Wakeup clock is from Standby) from Standby mode HSI16 = 16 MHz(4) MAX(1) TYP 3.0 2.3 Unit 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C - - - - - - - - - mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby + RTC) + IDD_ALL(SRAM2). 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings. STM32G491xC STM32G491xE Table 31. Current consumption in Standby mode (continued) Table 32. Current consumption in Shutdown mode Conditions DS13122 Rev 3 Symbol Parameter - IDD (Shutdown) Supply current in Shutdown mode (backup registers retained) RTC disabled - MAX(1) TYP Unit VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 26.0 160 1050 3350 9800 51.0 320 2200 6300 18000 2.4 V 28.0 195 1200 3900 11500 66.0 370 2400 7000 20000 3V 42.0 230 1450 4550 13500 89.0 450 2800 8000 22000 3.6 V 69.0 335 1850 5500 15500 170 630 3400 9500 26000 nA Electrical characteristics 91/199 Conditions Symbol Parameter Supply current in Shutdown IDD mode (backup (Shutdown with registers RTC) retained) RTC enabled DS13122 Rev 3 IDD(wakeup from Shutdown) Supply current during wakeup from Shutdown mode MAX(1) TYP Unit - VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C RTC clocked by LSE bypassed at 32768 Hz 1.8 V 230 370 1250 3550 10000 - - - - - 2.4 V 330 495 1550 4200 11500 - - - - - 3V 440 640 1850 4950 13500 - - - - - 3.6 V 595 855 2350 6050 16500 - - - - - RTC clocked by LSE quartz(2) in low drive mode 1.8 V 370 510 1350 3550 - - - - - - 2.4 V 470 640 1650 4200 - - - - - - 3V 615 810 2000 5000 - - - - - - 3.6 V 805 1050 2500 6100 - - - - - - 3V 1.60 - - - - - - - - - Wakeup clock is HSI16 = 16 MHz(3) Electrical characteristics 92/199 Table 32. Current consumption in Shutdown mode (continued) nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings. STM32G491xC STM32G491xE Conditions Symbol Parameter 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C 1.8 V 4.00 31.0 220 680 1950 - - - - - 2.4 V 5.00 41.0 255 780 2250 - - - - - 3V 7.00 45.0 300 910 2600 - - - - - 3.6 V 13.0 66.0 370 1100 3000 - - - - - RTC enabled and clocked by LSE bypassed at 32768 Hz 1.8 V 215 245 435 895 - - - - - - 2.4 V 300 340 555 1100 - - - - - - 3V 405 445 695 1300 - - - - - - 3.6 V 530 575 865 1600 - - - - - - RTC enabled and clocked by LSE quartz(2) 1.8 V 355 395 580 785 2050 - - - - - 2.4 V 460 500 720 890 2350 - - - - - 3V 585 635 890 1000 2650 - - - - - 3.6 V 735 800 1100 1200 3100 - - - - - RTC disabled Backup domain supply current Unit VBAT - IDD(VBAT) MAX(1) TYP STM32G491xC STM32G491xE Table 33. Current consumption in VBAT mode nA DS13122 Rev 3 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Electrical characteristics 93/199 Electrical characteristics STM32G491xC STM32G491xE I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 53: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This is done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 35: Low-power mode wakeup timings), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 94/199 DS13122 Rev 3 STM32G491xC STM32G491xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 34. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 14: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 34. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 34. Peripheral current consumption Range 1 Boost Mode Range 1 Range 2 Low-power run and sleep Bus Matrix 0.56 0.49 0.38 1.58 QUADSPI clock domain 3.94 3.67 3.03 3.44 QUADSPI independent clock domain 0.38 0.37 0.25 0.46 DMA1 3.16 2.94 2.39 2.81 DMA2 3.48 3.22 2.64 2.95 DMAMUX 6.73 6.26 5.17 5.96 CORDIC 1.17 1.10 0.89 1.10 FMAC 3.82 3.55 2.99 3.45 FLASH 4.88 4.53 3.73 4.38 SRAM1 0.39 0.35 0.33 0.35 BUS AHB AHB1 Peripheral DS13122 Rev 3 Unit µA/MHz µA/MHz 95/199 164 Electrical characteristics STM32G491xC STM32G491xE Table 34. Peripheral current consumption (continued) Range 1 Boost Mode Range 1 Range 2 Low-power run and sleep CRC 0.90 0.84 0.68 1.02 GPIOA 0.60 0.56 0.43 0.46 GPIOB 0.59 0.55 0.44 0.58 GPIOC 0.65 0.61 0.52 0.52 GPIOD 0.52 0.48 0.41 0.62 GPIOE 0.59 0.55 0.44 0.71 GPIOF 0.61 0.56 0.48 0.68 GPIOG 0.68 0.63 0.51 0.66 CCMSRAM 0.05 0.04 0.03 0.03 SRAM2 0.12 0.11 0.12 0.28 ADC12 clock domain 6.30 5.85 4.86 5.65 ADC12 independent clock domain 0.61 0.55 0.42 0.54 ADC3 clock domain 3.67 3.40 2.84 3.13 ADC3 independent clock domain 0.81 0.73 0.56 0.91 DAC1 5.24 4.86 4.05 4.70 DAC3 5.17 4.80 4.01 4.67 RNG clock domain 2.93 2.72 NA NA RNG independent clock domain 3.38 3.70 NA NA TIM2 10.28 9.57 7.88 9.19 TIM3 8.30 7.72 6.36 7.40 TIM4 8.24 7.67 6.31 7.26 TIM6 2.42 2.25 1.86 2.14 TIM7 2.52 2.35 1.92 2.14 CRS 0.91 0.84 0.70 0.82 RTC 3.75 3.49 2.91 3.68 WWDG 1.14 1.06 0.88 1.22 SPI2 5.19 4.83 3.99 4.60 SPI3 5.17 4.83 3.99 4.57 I2S2 clock domain 3.55 3.30 2.75 3.12 I2S2 independent clock domain 1.64 1.53 1.24 1.48 I2S3 clock domain 3.55 3.31 2.75 3.29 I2S3 independent clock domain 1.63 1.52 1.23 1.28 BUS AHB2 APB1 96/199 Peripheral DS13122 Rev 3 Unit µA/MHz µA/MHz STM32G491xC STM32G491xE Electrical characteristics Table 34. Peripheral current consumption (continued) Range 1 Boost Mode Range 1 Range 2 Low-power run and sleep USART2 clock domain 3.93 3.66 3.05 3.44 USART2 independent clock domain 7.56 7.05 5.81 6.84 USART3 clock domain 3.55 3.30 2.77 3.07 USART3 independent clock domain 7.76 7.23 5.95 6.98 UART4 clock domain 3.23 3.01 2.52 2.93 UART4 independent clock domain 6.28 5.85 4.81 5.41 UART5 clock domain 3.92 3.65 3.06 3.41 UART5 independent clock domain 6.35 5.92 4.86 5.77 I2C1 clock domain 1.91 1.79 1.50 1.53 I2C1 independent clock domain 4.34 4.04 3.32 4.06 I2C2 clock domain 1.89 1.76 1.47 1.58 I2C2 independent clock domain 4.07 3.80 3.11 3.60 USB clock domain 0.34 0.31 NA NA USB independent clock domain 3.27 3.60 NA NA FDCAN1 clock domain 21.82 20.36 16.90 18.16 FDCAN1 independent clock domain 3.04 2.77 2.24 3.78 PWR 0.88 0.81 0.69 0.72 I2C3 clock domain 1.79 1.67 1.41 1.54 I2C3 independent clock domain 5.00 4.65 3.79 4.45 LPTIM1 clock domain 1.74 1.62 1.37 1.61 LPTIM1 independent clock domain 4.90 4.56 3.72 4.22 LPUART1 clock domain 2.56 2.38 2.01 2.18 LPUART1 independent clock domain 5.07 4.71 3.86 4.62 UCPD1 clock domain 3.26 3.04 2.51 2.92 UCPD1 independent clock domain 2.36 2.57 NA NA BUS APB1 Peripheral DS13122 Rev 3 Unit µA/MHz 97/199 164 Electrical characteristics STM32G491xC STM32G491xE Table 34. Peripheral current consumption (continued) Peripheral Range 1 Boost Mode Range 1 Range 2 Low-power run and sleep SYSCFG/VREFBUF/COMPx/OPAMPx 1.64 1.54 1.31 1.51 TIM1 11.26 10.49 8.68 9.97 SPI1 2.92 2.73 2.23 2.61 TIM8 11.08 10.32 8.53 9.73 USART1 clock domain 2.94 2.74 2.30 2.34 USART1 independent clock domain 6.91 6.46 5.33 6.36 TIM15 5.82 5.44 4.49 5.18 TIM16 4.12 3.85 3.16 3.61 TIM17 3.99 3.73 3.08 3.62 TIM20 10.87 10.12 8.37 9.61 SAI1 clock domain 2.55 2.39 1.99 2.37 SAI1 independent clock domain 2.60 2.42 1.95 2.10 ALL peripherals 278 260 215 248 BUS APB2 98/199 DS13122 Rev 3 Unit µA/MHz STM32G491xC STM32G491xE 5.3.6 Electrical characteristics Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 35 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 35. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Conditions Typ Max - 11 12 - 10 11 Wakeup time from Sleep mode to Run mode Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode tWUSTOP0 tWUSTOP1 Wake up time from Stop 0 mode to Run mode in Flash Range 1 Wakeup clock HSI16 = 16 MHz 6.8 7 Range 2 Wakeup clock HSI16 = 16 MHz 18.1 18.4 Wake up time from Stop 0 mode to Run mode in SRAM1 Range 1 Wakeup clock HSI16 = 16 MHz 2.9 3.1 Range 2 Wakeup clock HSI16 = 16 MHz 2.9 3.1 Wake up time from Stop 1 mode to Run in Flash Range 1 Wakeup clock HSI16 = 16 MHz 10.4 10.8 Range 2 Wakeup clock HSI16 = 16 MHz 21.6 22 Wake up time from Stop 1 mode to Run mode in SRAM1 Range 1 Wakeup clock HSI16 = 16 MHz 6.6 6.9 Range 2 Wakeup clock HSI16 = 16 MHz 6.4 6.7 31.4 37 Wake up time from Stop 1 mode to Low-power run mode in Flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 tWUSTBY tWUSTBY SRAM2 tWUSHDN tWULPRUN Regulator in Wakeup clock low-power HSI16 = 16 MHz, mode (LPR=1 with HPRE = 8 in PWR_CR1) 15.5 19.2 Range 1 Wakeup clock HSI16 = 16 MHz 24.4 29.6 Wakeup time from Standby with SRAM2 to Run mode Range 1 Wakeup clock HSI16 = 16 MHz 24.4 29.6 Wakeup time from Shutdown mode to Run mode Range 1 Wakeup clock HSI16 = 16 MHz 261 305 5 7 Wakeup clock HSI16 = 16 MHz HPRE = 8 Nb of CPU cycles µs Wakeup time from Standby mode to Run mode Wakeup time from Lowpower run mode to Run mode(2) Unit 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. DS13122 Rev 3 99/199 164 Electrical characteristics STM32G491xC STM32G491xE Table 36. Regulator modes transition times(1) Symbol tVOST Parameter Conditions Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(2) Typ Max Unit 20 40 μs Typ Max Unit Stop 0 mode - 1.7 Stop 1 mode - 8.5 Wakeup clock HSI16 = 16 MHz HPRE = 8 1. Guaranteed by characterization results. 2. Time until VOSF flag is cleared in PWR_SR2. Table 37. Wakeup time using USART/LPUART(1) Symbol tWUUSART tWULPUART Parameter Conditions Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is HSI16 μs 1. Guaranteed by design. 5.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. However, the recommended clock input waveform is shown in Figure 18: High-speed external clock source AC timing diagram. Table 38. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 OSC_IN input pin high level voltage - 0.7 VDD - VDD VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDD Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 - - V OSC_IN high or low time 1. Guaranteed by design. 100/199 MHz VHSEH tw(HSEH) tw(HSEL) Unit DS13122 Rev 3 ns STM32G491xC STM32G491xE Electrical characteristics Figure 18. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 5.3.14. However, the recommended clock input waveform is shown in Figure 19. Table 39. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDD - VDD VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDD - 250 - - V tw(LSEH) OSC32_IN high or low time tw(LSEL) ns 1. Guaranteed by design. Figure 19. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 DS13122 Rev 3 101/199 164 Electrical characteristics STM32G491xC STM32G491xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 102/199 DS13122 Rev 3 STM32G491xC STM32G491xE Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 20. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 41. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DS13122 Rev 3 103/199 164 Electrical characteristics STM32G491xC STM32G491xE Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Conditions(2) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - Unit nA µA/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. Note: tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: 104/199 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS13122 Rev 3 STM32G491xC STM32G491xE 5.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 42. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step Conditions Min Typ VDD=3.0 V, TA=30 °C 15.88 - Trimming code is not a multiple of 64 0.2 0.3 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % DuCy(HSI16)(2) Duty Cycle - Max Unit 16.08 MHz 0.4 % ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA 1. Guaranteed by characterization results. 2. Guaranteed by design. DS13122 Rev 3 105/199 164 Electrical characteristics STM32G491xC STM32G491xE Figure 22. HSI16 frequency versus temperature MHz 16.4 +2 % 16.3 +1.5 % 16.2 +1 % 16.1 16 15.9 -1 % 15.8 -1.5 % 15.7 -2 % 15.6 -40 -20 0 20 Mean 40 60 80 min 100 120 °C max MSv39299V2 High-speed internal 48 MHz (HSI48) RC oscillator Table 43. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter HSI48 Frequency Conditions VDD=3.0V, TA=30°C HSI48 user trimming step HSI48 user trimming coverage ±32 steps DuCy(HSI48) Duty Cycle - VDD = 3.0 V to 3.6 V, Accuracy of the HSI48 TA = –15 to 85 °C ACCHSI48_REL oscillator over temperature VDD = 1.65 V to 3.6 V, (factory calibrated) TA = –40 to 125 °C DVDD(HSI48) 106/199 HSI48 oscillator frequency VDD = 3 V to 3.6 V drift with VDD VDD = 1.65 V to 3.6 V Min Typ Max Unit - 48 - MHz - 0.11(2) 0.18(2) % ±3(3) ±3.5(3) - % 45(2) - 55(2) % - - ±3(3) - - ±4.5(3) - 0.025(3) 0.05(3) - 0.05(3) 0.1(3) % % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA DS13122 Rev 3 STM32G491xC STM32G491xE Electrical characteristics Table 43. HSI48 oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. Figure 23. HSI48 frequency versus temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 10 30 50 Avg 70 90 min 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 44. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) Parameter LSI Frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - 80 130 LSI oscillator start-up time DS13122 Rev 3 - Unit kHz μs 107/199 164 Electrical characteristics STM32G491xC STM32G491xE Table 44. LSI oscillator characteristics(1) (continued) Symbol Parameter tSTAB(LSI)(2) IDD(LSI)(2) Conditions Min Typ Max Unit LSI oscillator stabilization 5% of final frequency time - 125 180 μs LSI oscillator power consumption - 110 180 nA - 1. Guaranteed by characterization results. 2. Guaranteed by design. 5.3.9 PLL characteristics The parameters given in Table 45 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17: General operating conditions. Table 45. PLL characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 2.66 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 Boost mode 2.0645 - 170 Voltage scaling Range 1 2.0645 - 150 Voltage scaling Range 2 2.0645 - 26 Voltage scaling Range 1 Boost mode 8 - 170 Voltage scaling Range 1 8 - 150 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 Boost mode 8 - 170 Voltage scaling Range 1 8 - 150 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 96 - 128 - - 15 40 - 28.6 - - 21.4 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 150 MHz 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. 108/199 DS13122 Rev 3 MHz μs ±ps μA STM32G491xC STM32G491xE 5.3.10 Electrical characteristics Flash memory characteristics Table 46. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.7 83.35 µs tprog_row One row (32 double word) programming time Normal programming 2.61 2.7 Fast programming 1.91 1.95 tprog_page One page (2 Kbytes) programming time Normal programming 20.91 21.34 Fast programming 15.29 15.6 22.02 24.47 Normal programming 5.36 5.46 Fast programming 3.92 4 22.13 24.6 Write mode 3.5 - Erase mode 3.5 - Write mode 7 (for 6 µs) - Erase mode 7 (for 67 µs) - tERASE Page (2 Kbytes) erase time tprog_bank One bank (512 Kbyte) programming time tME IDD - Mass erase time - Average consumption from VDD Maximum current (peak) ms s ms mA 1. Guaranteed by design. Table 47. Flash memory endurance and data retention Symbol NEND tRET Min(1) Unit TA = -40 to +105 °C 10 kcycles 1 kcycle(2) at TA = 85 °C 30 Parameter Endurance Data retention Conditions 1 kcycle (2) 1 kcycle (2) at TA = 105 °C 15 at TA = 125 °C 7 (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles (2) at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS13122 Rev 3 109/199 164 Electrical characteristics 5.3.11 STM32G491xC STM32G491xE EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 48. They are based on the EMS levels and classes defined in application note AN1709. Table 48. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 170 MHz, conforming to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 170 MHz, conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. 110/199 DS13122 Rev 3 STM32G491xC STM32G491xE Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 49. EMI characteristics Symbol SEMI Parameter Peak level Monitored frequency band Conditions Max vs. [fHSE/fHCLK] 0.1 MHz to 30 MHz 5 30 MHz to 130 MHz VDD = 3.6 V, TA = 25 °C, LQFP100 package 130 MHz to 1 GHz compliant with IEC 61967-2 1 GHz to 2 GHz 4 EMI Level 5.3.12 Unit 8 MHz / 170 MHz dBµV 20 13 3.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 50. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Electrostatic discharge voltage (human body model) Conditions TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001 LQFP80 (14 x 14 mm), TA = +25 °C, conforming to LQFP100 Electrostatic discharge ANSI/ESDA/JEDEC JSVESD(CDM) WLCSP64 voltage (charge device model) 002 Other packages Class Maximum Unit value(1) 2 2000 C1 250 C2a 500 C2a 500 V V 1. Guaranteed by characterization results. DS13122 Rev 3 111/199 164 Electrical characteristics STM32G491xC STM32G491xE Static latch-up Two complementary static tests are required on three parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78E IC latch-up standard. Table 51. Electrical sensitivities Symbol LU 5.3.13 Parameter Static latch-up class Conditions Class TA = +125 °C conforming to JESD78E Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 52. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 52. I/O current injection susceptibility Functional susceptibility Symbol (1) IINJ Description Injected current on pin Unit Negative injection Positive injection All except TT_a, PF2, PC9, PA9, PA10 -5 NA PF2, PC9 -0 NA TT_a pins, PA9, PA10 -5 0 1. Guaranteed by characterization. 112/199 DS13122 Rev 3 mA STM32G491xC STM32G491xE 5.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the conditions summarized in Table 17: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 53. I/O static characteristics Symbol Parameter I/O input VIL(1)(2) low level voltage I/O input VIH(1)(2) high level voltage VHYS(3) Input hysteresis Conditions All except FT_c 1.62 V