STM32H563RGT6

STM32H562xx and STM32H563xx Arm® Cortex®-M33 32-bit MCU + TrustZone® + FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP64 (10 x 10 mm) VFQFPN68 (8 x 8 mm) LQFP100 14 x 14 mm) Core LQFP144 (20 x 20 mm) ® ® ® • Arm Cortex -M33 CPU with TrustZone , FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1) ART Accelerator UFBGA LQFP176 (24 x 24 mm) UFBGA169 (7 x 7 mm) UFBGA 176+25 (10 x 10 mm) WLCSP80 (3.50 X 3.27 mm) • 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories Clock management • 4-Kbyte data cache for external memories • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI Benchmarks • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE • 1.5 DMIPS/MHz (Drystone 2.1) • 1023 CoreMark® (4.092 CoreMark®/MHz) General-purpose inputs/outputs Memories • Up to 140 fast I/Os with interrupt capability (most of them 5 V-tolerant) • Up to 2 Mbytes of embedded flash memory with ECC, two banks read-while-write • Up to ten I/Os with independent supply down to 1.08 V • Up to 48-Kbyte per bank with high-cycling capability (100 K cycles) for data flash Low-power consumption • 2-Kbyte OTP (one-time programmable) • Sleep, Stop, and Standby modes • 640 Kbytes of SRAM (64-Kbyte SRAM2 with ECC and 320-Kbyte SRAM3 with flexible ECC) • VBAT supply for RTC, 32 backup registers (32-bit) • 4 Kbytes of backup SRAM available in the lowest power modes Security • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • One Octo-SPI memory interface with support for serial PSRAM/NAND/NOR, hyper RAM/flash frame formats • Two SD/SDIO/MMC interfaces January 2025 This is information on a product in full production. • Arm® TrustZone® with Armv8-M mainline security extension • Up to eight configurable SAU regions • TrustZone® aware and securable peripherals • Flexible life cycle scheme with secure debug authentication • SFI (secure firmware installation) • Secure firmware upgrade support with TF-M DS14258 Rev 5 1/270 www.st.com STM32H562xx and STM32H563xx • HASH hardware accelerator • One I3C • ECDSA signature verification • Up to 12 U(S)ARTs (ISO7816 interface, LIN, IrDA, modem control) and one LPUART • True random number generator, NIST SP800-90B compliant Two DMA controllers to offload the CPU • Up to six SPIs, including three muxed in full-duplex I2S audio class accuracy via internal audio PLL or external clock, and up to five additional SPIs from five USARTs when configured in Synchronous mode (one additional SPI with OctoSPI) • Two dual-port DMAs with FIFO • Two SAIs Mathematical acceleration • Two FDCANs • 96-bit unique ID • Active tampers • One 8- to 14-bit camera interface • CORDIC for trigonometric functions acceleration • One 16-bit parallel slave synchronousinterface • FMAC (filter mathematical accelerator) • One HDMI-CEC Reset and supply management • 1.71 V to 3.6 V application supply and I/O • One Ethernet MAC interface with DMA controller • POR, PDR, PVD, and BOR • One USB 2.0 full-speed host and device • Embedded regulator (LDO) or SMPS stepdown converter regulator with configurable scalable output to supply the digital circuitry Analog • One USB Type-C®/USB Power Delivery r3.1 • Two 12-bit ADCs with up to 5 Msps in 12-bit Up to 24 timers • One 12-bit DAC with two channels • 18 16-bit timers (including six low-power 16-bit timers available in Stop mode) • Digital temperature sensor • Two 32-bit timers with up to four IC/OC/PWM or pulse counters and quadrature (incremental) encoder input • Two watchdogs • Authenticated debug and flexible device life cycle • Serial wire-debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM) • Two SysTick timers Up to 34 communication interfaces • Up to four I2Cs Fm+ Debug ECOPACK2 compliant packages (SMBus/PMBus®) Table 1. Device summary Reference Part numbers STM32H562xx STM32H562AG, STM32H562AI, STM32H562IG, STM32H562II, STM32H562RG, STM32H562RI, STM32H562VG, STM32H562VI, STM32H562ZG, STM32H562ZI STM32H563xx STM32H563AG, STM32H563AI, STM32H563IG, STM32H563II, STM32H563MI, STM32H563RG, STM32H563RI, STM32H563VG, STM32H563VI, STM32H563ZG, STM32H563ZI 2/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 19 3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 3.4.1 FLASH security and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 Security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.1 STM32H562/H563xx boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10 3.9.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.10.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.10.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.11 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.12.1 3.13 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DS14258 Rev 5 3/270 Contents STM32H562xx and STM32H563xx 3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14.1 3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.16 General purpose direct memory access controller (GPDMA) . . . . . . . . . 35 3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37 3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37 3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 38 3.19 CORDIC coprocessor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.20 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.21 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.22 3.21.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.21.2 FMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.22.1 4/270 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.23 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.24 Analog-to-digital converters (ADC1 and ADC2) . . . . . . . . . . . . . . . . . . . . 41 3.24.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.24.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.24.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.25 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.26 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.27 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.28 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.29 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 44 3.30 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.31 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.32 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.33.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . 47 3.33.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.33.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6) . . . . . . . . . . . 47 DS14258 Rev 5 STM32H562xx and STM32H563xx 3.34 4 5 Contents 3.33.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.33.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.33.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 49 3.34.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.34.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.35 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.36 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.37 Universal synchronous/asynchronous receiver transmitter (USART/UART) and low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.37.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.37.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 55 3.38 Serial peripheral interface (SPI) / inter-integrated sound interfaces (I2S) 56 3.39 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.40 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 59 3.41 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.42 USB full speed (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.43 USB Type-C/USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 61 3.44 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 61 3.45 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.46 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.46.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.46.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Pinout, pin description, and alternate functions . . . . . . . . . . . . . . . . . 63 4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 DS14258 Rev 5 5/270 Contents 6/270 STM32H562xx and STM32H563xx 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.3.4 Operating conditions at power-up/down . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 133 5.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 5.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 159 5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 175 5.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.3.19 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.3.21 DCMI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.3.22 PSSI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.3.25 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 214 5.3.26 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 215 5.3.27 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.3.28 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.3.30 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 DS14258 Rev 5 STM32H562xx and STM32H563xx 6 Contents 5.3.32 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.2 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.3 VFQFPN68 package information (B029) . . . . . . . . . . . . . . . . . . . . . . . . 243 6.4 WLCSP80 package information (B0D4) . . . . . . . . . . . . . . . . . . . . . . . . . 245 6.5 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 6.6 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6.7 UFBGA169 package information (A0YV) . . . . . . . . . . . . . . . . . . . . . . . . 255 6.8 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 6.9 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 262 6.10 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 6.10.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 DS14258 Rev 5 7/270 List of tables STM32H562xx and STM32H563xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. 8/270 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32H56xxx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3) . . . . . . . . . . . 24 STM32H562/H563 boot mode when TrustZone is enabled (TZEN = 0xB4). . . . . . . . . . . . 25 ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 52 USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 STM32H562xx and STM32H563xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Alternate functions AF0 to AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Alternate functions AF8 to AF15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 130 Operating conditions at power-up/down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 133 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Typical and maximum current consumption in Run mode, code with data processing running from flash memory, 2-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 136 Typical and maximum current consumption in Run mode, code with data processing running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 137 Typical and maximum current consumption in Run mode, code with data processing running from SRAM with cache 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Typical and maximum current consumption in Run mode, code with data processing running from SRAM with cache 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical consumption in Run mode with CoreMark running from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical consumption in Run mode with SecureMark running from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 140 Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 141 Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 141 Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 142 Peripheral current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DS14258 Rev 5 STM32H562xx and STM32H563xx Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. List of tables Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8 . . . . . . . . 163 Output voltage characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Output voltage characteristics for PC13 and PI8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Output timing characteristics VDDIO2 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . . 171 Output timing characteristics VDDIO2 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . 173 Output timing characteristics for FT_c I/Os (PB13/PB14). . . . . . . . . . . . . . . . . . . . . . . . . 174 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 177 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 177 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 178 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 179 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 180 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 OCTOSPI characteristics in DTR mode (with DQS) / HyperBus . . . . . . . . . . . . . . . . . . . 197 Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DS14258 Rev 5 9/270 10 List of tables Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. 10/270 STM32H562xx and STM32H563xx 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Dynamic characteristics: eMMC, VDD = 1.71 to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Dynamic characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . . 234 Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 234 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 VFQFPN68 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 WLCSP80 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 WLCSP80 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 257 LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 263 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 DS14258 Rev 5 STM32H562xx and STM32H563xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. STM32H562xx and STM32H563xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32H562xx and STM32H563xx power supply overview (with SMPS) . . . . . . . . . . . . . 29 STM32H562xx and STM32H563xx power supply overview (with LDO). . . . . . . . . . . . . . . 30 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VFQFPN68 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 WLCSP80 SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP100 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 LQFP144 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 UFBGA169 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 LQFP176 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 UFBGA176+25 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Power supply scheme with SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Power supply scheme with LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SMPS efficiency versus load current in Run, Sleep, and Stop modes with SVOS3 mode, TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SMPS efficiency versus load current in Run, Sleep, and Stop modes with SVOS3 mode, TJ = 130 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C. . . . . . . . . . . . 132 SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C. . . . . . . . . . . 132 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 176 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 178 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 179 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 181 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 187 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 190 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 191 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DS14258 Rev 5 11/270 12 List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. 12/270 STM32H562xx and STM32H563xx OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DCMI timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 209 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 210 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 USB timings - definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SDIO high-speed/eMMC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 SD default speed timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DDR mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 VFQFPN68 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 VFQFPN68 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 WLCSP80 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 WLCSP80 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 WLCSP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 UFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 LQFP176 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 LQFP176 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 DS14258 Rev 5 STM32H562xx and STM32H563xx 1 Introduction Introduction This document provides the ordering information and mechanical device characteristics of the STM32H562xx and STM32H563xx microcontrollers. For information on the device errata with respect to the datasheet and reference manual, refer to the STM32H562xx and STM32H563xx errata sheet. For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS14258 Rev 5 13/270 13 Description 2 STM32H562xx and STM32H563xx Description The STM32H562xx and STM32H563xx devices are high-performance microcontrollers of the STM32H5 series, based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 250 MHz. The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm® single-precision data-processing instructions and all the data types. This core implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security. The devices embed high-speed memories (up to 2 Mbytes of dual bank flash memory and 640 Kbytes of SRAM), a flexible external memory controller (FMC) for devices with packages of 100 pins and more, one OCTOSPI memory interface (at least one Quad-SPI available on all packages), and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the trusted-based security architecture (TBSA) requirements from Arm®. They embed the features to implement a secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of protection and secure debug authentication. Firmware hardware isolation is supported thanks to securable peripherals, memories, and I/Os, and to privilege configuration of peripherals and memories. The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure, and hide protection areas. Dedicated peripherals reinforce security: an HASH hardware accelerator, and a true random number generator. The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring, generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. The devices offer two fast 12-bit ADCs, two DAC channels, an internal voltage reference buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers, and six 16-bit low-power timers. The devices also feature standard and advanced communication interfaces, namely: four I2Cs, one I3C, six SPIs, three I2Ss, six USARTs, six UARTs and one low-power UART, two SAIs, one digital camera interface (DCMI), up to two SDMMCs, up to two FDCANs, one USB full-speed, one USB Type-C®/USB power delivery controller, an Ethernet interface (available only on STM32H563xx). The devices operate in the -40 to +85 °C (+130 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges, with a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allow the design of low-power applications. Independent power supplies are supported: an analog independent supply input for ADC, DACs, a 3.3 V dedicated supply input for USB, and a dedicated supply input for some GPIOs and SDMMC. A VBAT input is available to connect a backup battery, to preserve the RTC functionality, and to backup 32 32-bit registers and a 4-Kbyte SRAM. 14/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Description The devices offer eight packages, from 64 to 176 pins. All packages are available with LDO or SMPS supply options for the VCORE (except for LQFP64 and VFQFPN68 packages, not available in SMPS, and WLCSP80, not available in LDO). Flash memory SRAM STM32H562II/G STM32H563II/G STM32H562AI/G STM32H563AI/G STM32H562ZI/G STM32H563ZI/G Up to 2 Mbytes System 640 (256 + 64 + 320) Kbytes Backup 4 Kbytes Flexible memory controller for external memories (FMC) No Yes(1) Yes Yes (2) OCTOSPI Timers STM32H562VI/G STM32H563VI/G STM32H563MI STM32H562RI/G Peripherals STM32H563RI/G Table 2. STM32H56xxx features and peripheral counts 1 Advanced control 2 (16 bits) General purpose 2 (32 bits) and 8 (16 bits) Basic 2 (16 bits) Low power 6 (16 bits) SysTick timer 2 Watchdog timers (independent, window) 2 DS14258 Rev 5 15/270 18 Description STM32H562xx and STM32H563xx 1 2 1 2 1 1 2 1 2 1 No Yes/ Yes No Yes/ Yes No 5/3 6/3 I2C 4 I3C 1(3) USART 5 6 UART 5 6 LPUART 1 SAI 2 FDCAN 2 1 2 1 2 USB Yes UCPD Yes SDMMC 1 2 1 Digital camera interface (DCMI)/PSSI(4) 2 Yes Ethernet Yes/ (legacy/SMPS) No No No/Yes Yes/ No No HDMI-CEC Yes/ No Yes CORDIC co-processor Yes Filter mathematical accelerator (FMAC) Yes Real time clock (RTC) Yes Tamper pins (legacy/SMPS) (5) Active tampers (legacy/SMPS) STM32H562AI/G STM32H563AI/G STM32H562ZI/G STM32H563ZI/G STM32H562VI/G STM32H563VI/G STM32H562II/G Communication interfaces 4/3 STM32H563II/G SPI / I2S STM32H563MI Peripherals STM32H562RI/G STM32H563RI/G Table 2. STM32H56xxx features and peripheral counts (continued) 5/NA NA/5 8/8 4/NA NA/4 7/7 True random number generator Yes HASH (SHA-512) Yes PKA (ECDSA signature verification) Yes GPIOs (legacy/SMPS) 53(6)/NA NA/57 80 /78 80 /NA 112 /110 112 /NA 136 136 140(7) /134 /eNA /139 140 Wake-up pins (legacy/SMPS) 6/NA(8) NA/6 7/7 7 /NA 7/7 7 /NA 8/8 8 /NA 8/8 8 /NA Number of I/Os down to 1.08 V (legacy/SMPS) 0/NA NA/0 0/0 0 /NA 10 /10 10 /NA 10/7 10 /NA 10/7 10 /NA 16/270 DS14258 Rev 5 (7) STM32H562xx and STM32H563xx Description DAC STM32H562AI/G STM32H563II/G STM32H562II/G 20 /18 20 /NA 20 /20 20/ NA 20 /20 20/ NA 2 16/NA NA / 16 16 /14 16 /NA 12-bit DAC controller 1 Number of 12-bit D to A converters 2 Internal voltage reference buffer STM32H563AI/G Number of channels (legacy/SMPS) ADC STM32H562ZI/G 12-bit ADC STM32H563ZI/G STM32H562VI/G STM32H563VI/G STM32H563MI STM32H562RI/G Peripherals STM32H563RI/G Table 2. STM32H56xxx features and peripheral counts (continued) No Yes Maximum CPU frequency 250 MHz Operating voltage 1.71 to 3.6 V Operating temperature Ambient -40 to 85 or 105 °C / -40 to 125 °C Junction Voltage range VOS0 (up to 250 MHz): -40 to 105 °C Voltage range VOS1 (up to 200 MHz): -40 to 130 °C Package LQFP64 WLCSP80 VFQFPN68 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176 1. 8-bit to interface LCD controller. 2. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 chip select. 3. Shares the I/Os with I2C4. 4. DCMI and PSSI cannot be used at the same time, as they share the same circuitry. 5. Active tampers in output sharing mode (one output shared by all inputs). 6. 49 for LQFP64. 7. 136 for LQFP176. 8. 5 for VFQFPN68. DS14258 Rev 5 17/270 18 Description STM32H562xx and STM32H563xx Figure 1. STM32H562xx and STM32H563xx block diagram MPU ETM NVIC Arm Cortex-M33 250 MHz C-BUS TrustZone FPU SDMMC1 FIFO SDMMC2 SRAM 4 KB MAC ETHERNET DCACHE (4 Kbytes) IO[7:0], CLK, NCLK, NCS. DQS as AF OCTOSPI1 memory interface RNG Flash memory (up to 2 Mbytes) HASH SRAM1 (256 Kbytes) VDDA SRAM2 (64 Kbytes) ITF DAC1_OUT2 DCMI/PSSI VDD VDD VDD Power management Voltage regulator LDO or SMPS 3.3 to 1.2 V HSI48 HS64 Reset BOR PF[15:0] GPIO port F PG[15:0] GPIO port G PH[15:0] GPIO port H PI[7:0] GPIO port I 16 AF EXT IT. WKP CRC VDDA ADC1 20xIN GTZC1 4 channels, ETR as AF CORDIC TIM3 16-bit 4 channels, ETR as AF FMAC TIM4 16-bit 4 channels, ETR as AF TIM5 32-bit 4 channels, ETR as AF EXTI AHB/APB1 16-bit 1 channel, 1 compl. channel, BKIN as AF TIM16 16-bit TIM17 16-bit smcard USART1 irDA APB2 250 MHz TIM15 TIM6 16-bit SPI6 TIM7 16-bit SAI2 FIFO PHY VDDUSB USB FS AHB/APB3 VBAT XTAL 32k RTC TAMP VDDA LPTIM1 I2C3/SMBUS SCL, SDA, SMBA as AF I2C4/SMBUS APB3 250 MHz VREF buffer SCL, SDA, SMBA as AF MOSI, MISO, SCK, NSS as AF RX, TX, CK, CTS, RTS_DE as AF SPI2/I2S2 MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF FDCAN1 FDCAN2 UCPD1 TX, RX as AF TX, RX as AF CC1, DBCC1, CC2, DBCC2, FRSCC1, FRSCC2 as AF IN1, IN2, CH1, CH2, ETR as AF TIM12 16-bit 2 channels, ETR as AF TIM13 16-bit 1 channel, ETR as AF TIM14 16-bit AHB3 250 MHz Temperature monitoring RX, TX, CTS, RTS_DE as AF RX, TX, CTS, RTS_DE as AF smcard USART6 irDA LPTIM2 AUDIOCLK as AF VREF+ UART5 SAI1 MCLK_A, SD_A, FS_A, SCK_A, MCLK_B, SD_B, FS_B, SCK_B as AF IN1, IN2, CH1, CH2, ETR as AF RX, TX, CTS, RTS_DE as AF FIFO SPI4 MOSI, MISO, SCK, NSS as AF RTC_OUT[8:1], RTC_IN[8:1] RX, TX, CK, CTS, RTS_DE as AF UART4 PHY IWDG MCLK_A, SD_A, FS_A, SCK_A, MCLK_B, SD_B, FS_B, SCK_B as AF RTC_OUT1, RTC_OUT2, RTC_REFIN, RTC_TS RX, TX, CK, CTS, RTS_DE as AF smcard USART3 irDA SPI1/I2S1 MOSI, MISO, SCK, NSS as AF DP DM smcard USART2 irDA SPI3/I2S3 DTS WWDG MOSI, MISO, SCK, NSS as AF WKUPx (x=1 to 8) 32-bit 16-bit 2 channels, 1 compl. channel, BKIN as AF RX, TX, CK,CTS, RTS_DE as AF AHB/APB2 16-bit TIM8/PWM 1 channel, 1 compl. channel, BKIN as AF Standby interface TIM2 APB1 250 MHz (max) TIM1/PWM 3 compl. channels (TIM1_CH[1:3]N), 6 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF Reset and clock control SRAM 512 B ITF OSC_IN OSC_OUT IWDG CRS ADC2 3 compl. channels (TIM1_CH[1:3]N), 6 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF VDD XTAL OSC 4- 50 MHz HCLKx GPIO port E PE[15:0] RAMCFG VDDIO, VDDUSB, VDDA, VSSA, VDD, VSS, NRST PVD, PVM PLL 1, 2, 3 FCLK GPIO port D AHB3 250 MHz GPIO port B GPIO port C AHB1 250 MHz PB[15:0] PD[15:0] Int LSI BKPSRAM (4 Kbytes) PCLKx GPIO port A VDD = 1.71 to 3.6 V VSS VDD Supply supervision CSI VBAT PC[15:0] D[15:0], CK, CMD as AF AHB2 250 MHz GPDMA1 GPDMA2 PA[15:0] DAC1_OUT1 DAC1 SRAM3 (320 Kbytes) FIFO D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin D0dir, D2dir FIFO S-BUS CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT, SDCLK,SDCLKE[1:0], SDNE[1:0], SDNWE, NRAS, NCAS, as AF Flexible memory controller (FMC): SDRAM, SRAM, PSRAM, NOR flash, FRAM, NAND flash AHB bus-matrix TRACECLK, TRACED[3:0] JTAG/ SW ICACHE (8 Kbytes) NJTRST, JTDI, JTCK/SWCLK, JTMS/SWDIO, JTDO 1 channel, ETR as AF UART7 RX, TX, CTS, RTS_DE as AF UART8 RX, TX, CTS, RTS_DE as AF UART9 RX, TX, CTS, RTS_DE as AF smcard irDA RX, TX, CK, CTS, RTS_DE as AF smcard irDA RX, TX, CK, CTS, RTS_DE as AF USART10 USART11 UART12 HDMI-CEC I3C1 RX, TX, CTS, RTS_DE as AF CEC SCL, SDA LPUART1 SPI5 SBS IN1, IN2, CH1, CH2, ETR as AF LPTIM3 IN1, ETR as AF LPTIM4 IN1, IN2, CH1, CH2, ETR as AF LPTIM5 IN1, IN2, CH1, CH2, ETR as AF LPTIM6 VDD power domain VDDA power domain VDDUSB power domain VBAT power domain MSv67308V6 Note: 18/270 PC[15:13] are in the VBAT domain. DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview 3 Functional overview 3.1 Arm Cortex-M33 core with TrustZone and FPU The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for microcontrollers and deeply embedded applications, especially those requiring efficient security. This processor delivers a high computational performance with low-power consumption and an advanced response to interrupts. It features: • Arm TrustZone technology, using the Armv8-M main extension supporting secure and nonsecure states • Memory protection units (MPUs), supporting up to 16 regions for secure and nonsecure applications • Configurable secure attribute unit (SAU) supporting up to eight memory regions as secure or nonsecure • Floating-point arithmetic functionality with support for single precision arithmetic The processor supports a set of DSP instructions that allows an efficient signal processing and a complex algorithm execution. The Cortex-M33 processor supports the following bus interfaces: • System AHB bus: The system AHB (S-AHB) bus interface is used for any instruction fetch and data access to the memory-mapped SRAM, peripheral, external RAM and external device, or Vendor_SYS regions of the Armv8-M memory map. • Code AHB bus: The code AHB (C-AHB) bus interface is used for any instruction fetch and data access to the code region of the Armv8-M memory map. Figure 1 shows the general block diagram of the STM32H562xx and STM32H563xx devices. 3.2 ART Accelerator (ICACHE and DCACHE) 3.2.1 Instruction cache (ICACHE) The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex-M33 processor to improve performance when fetching instruction (or data) from both internal and external memories. ICACHE offers the following features: • Multi-bus interface: – slave port receiving the memory requests from the Cortex-M33 C-AHB code execution port – master1 port performing refill requests to internal memories (flash memory and SRAMs) – master2 port performing refill requests to external memories (external flash memory and RAMs through Octo-SPI and FMC interfaces) – a second slave port dedicated to ICACHE registers access DS14258 Rev 5 19/270 62 Functional overview • 3.2.2 STM32H562xx and STM32H563xx Close to 0 wait-states instructions/data access performance: – 0 wait-states on cache hit – hit-under-miss capability, allowing to serve new processor requests while a line refill (due to a previous cache miss) is still ongoing – critical-word-first refill policy, minimizing processor stalls on cache miss – hit ratio improved by two-way set-associative architecture and pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree), algorithm with best complexity/performance balance – dual master ports allowing to decouple internal and external memory traffic, respectively, on fast and slow buses, minimizing impact on interrupt latency – optimal cache line refill thanks to AHB burst transactions (of the cache line size) – performance monitoring by means of a hit counter and a miss counter • Extension of cacheable region beyond the code memory space, by means of address remapping logic that allows four cacheable external regions to be defined • Power consumption reduced intrinsically (more accesses to cache memory rather than to bigger main memories); even improved by configuring ICACHE as direct mapped (rather than the default two-way set-associative mode) • TrustZone security support • Maintenance operation for software management of cache coherency • Error management: detection of unexpected cacheable write access, with optional interrupt raising Data cache (DCACHE) The data cache (DCACHE) is introduced on S-AHB system bus of Cortex-M33 processor to improve the performance of data traffic to/from external memories. DCACHE offers the following features: • • 20/270 Multi-bus interface: – slave port receiving the memory requests from the Cortex-M33 S-AHB system port – master port performing refill requests to external memories (external flash memory and RAMs through Octo-SPI and FMC interfaces) – a second slave port dedicated to DCACHE registers access Close to zero wait-states external data access performance: – zero wait-states on cache hit – hit-under-miss capability, allowing to serve new processor requests to cached data, while a line refill (due to a previous cache miss) is still ongoing – critical-word-first refill policy for read transactions, minimizing processor stalls on cache miss – hit ratio improved by two-way set-associative architecture and pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree), algorithm with best complexity/performance balance – optimal cache line refill thanks to AHB burst transactions (of the cache line size) – performance monitoring by means of two hit counters (for read and write) and two miss counters (for read and write) DS14258 Rev 5 STM32H562xx and STM32H563xx • Supported cache accesses: – supports both write-back and write-through policies (selectable with AHB bufferable attribute) – read and write-back always allocated – write-through always non-allocated (write-around) – supports byte, half-word and word writes • TrustZone security support • Maintenance operations for software management of cache coherency: • 3.3 Functional overview – full cache invalidation (non interruptible) – address range clean and/or invalidate operations (background task, interruptible) Error management: detection of error for master port request initiated by DCACHE (line eviction or clean operation), with optional interrupt raising Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by other active tasks. This memory area is organized into up to 20 protected areas (12 secure and 8 nonsecure). The MPU regions and registers are banked across secure and nonsecure states. The MPU is especially helpful for applications where critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area settings based on the process to be executed. 3.4 Embedded flash memory The devices feature up to 2 Mbytes of embedded flash memory for storing programs and data. The flash memory supports a high-cycle data area of up to 100 K cycles. The flash memory interface features dual-bank operating modes, and read-while-write (RWW). This allows a read operation to be performed on one bank while an erase or program operation is performed on the other bank. Each bank contains 128 8-Kbyte pages. The flash memory embeds a 2-Kbyte OTP (one-time programmable) for user data, and up to 96 Kbytes supporting high cycling capability (100 K cycles), to use for data (EEPROM emulation). DS14258 Rev 5 21/270 62 Functional overview STM32H562xx and STM32H563xx Option bytes are available to set the flash memory protection mechanisms: • Different product states for protecting memory content from debug access • Write protection (WRP) to protect areas against erasing and programming. Two areas per bank can be selected with 8-Kbyte granularity. • Sector group write-protection (WRPSG), protecting up to 32 groups of four sectors (32 Kbytes) per bank • Two secure-only areas (one per user flash memory bank). When enabled, this area is accessible only if the device operates in Secure-access mode • One HDP area per bank providing temporal isolation for startup code The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.4.1 • Single-error detection and correction • Double-error detection • ECC fail address report FLASH security and protections Sensitive information is stored in the flash memory and it is important to protect the memory against unwanted operations such as reading confidential areas, illegal programming of immutable sectors, or malicious flash memory erasing. For that purpose the following protection mechanisms are implemented: • TrustZone backed watermark and block security protection • Temporal isolation protection (HDP) • Configuration protection • User flash memory write protection • Device non-volatile security life cycle and application boot state management • OTP locking Refer to the product reference manual for a detailed description of the security mechanisms. 3.4.2 FLASH privilege protection Each flash memory sector can be programmed on the fly as privileged or unprivileged. 3.5 Embedded SRAMs Four SRAMs are embedded in the STM32H562xx and STM32H563xx devices, each with specific features. SRAM1, SRAM2, and SRAM3 are the main SRAMs. These SRAMs are made of several blocks that can be powered down in Stop mode to reduce consumption: 22/270 • SRAM1: 256 Kbytes • SRAM2: 64 Kbytes with ECC • SRAM3: 320 Kbytes with optional ECC (when enabled, 64 bytes are reserved for it) • BKPSRAM (backup SRAM): 4 Kbytes with optional ECC, can be retained in all lowpower modes and when VDD is off in VBAT mode DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview Note: The ECC is supported by SRAM2, SRAM3, and BKPSRAM when enabled with the SRAM2_ECC, SRAM3_ECC, and BKPRAM_ECC user option bits. 3.5.1 SRAMs TrustZone security When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1, SRAM2, SRAM3, can be programmed as secure or nonsecure by blocks, using the MPCBB (block-based memory protection controller). The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone controller). 3.5.2 SRAMs privilege protection The SRAM1, SRAM2, SRAM3, can be programmed as privileged or non-privileged by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page of 512 bytes. Backup SRAM regions can be programmed as privileged or non-privileged with watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone controller). 3.6 Security overview The STM32H562xx and STM32H563xx security enables the possibility to reopen the debug mode even if the product is in secure state. The reopening of the debug mode is controlled with a debug authentication procedure which permits the authentication of the host. Sensible assets (such as keys or secret codes) must be protected when opening the debug mode. The protection is made via code protection and hardware keys storage solutions where all root of trust can be protected thanks to hardware mechanisms. In cases where sensitive information cannot be protected, a partial or a full regression can be launched to start a debug. Regressions are enabled by a debug authentication method. Developers can introduce their own root of trust solution (OEM-iROT), including their installation in a non-trusted environment, thanks to a secure firmware install (SFI) solution. The boot stages are isolated via a hardware mechanism called HDPL (temporal isolation level). The HDPL guarantees isolation of the different boot stages: ST assets, iROT (immutable root of trust), uROT (updatable root of trust), secure operating system and nonsecure applications. The devices embed a hardware key storage solution with a dedicated flash memory area per boot stages with access-control based on HDPL, which can be secure or nonsecure. STM32H562xx and STM32H563xx are powered by an Arm Cortex-M33 core, associated with all the TrustZone isolation infrastructure. This design permits to benefit from a run time isolation to run secure applications. DS14258 Rev 5 23/270 62 Functional overview 3.7 STM32H562xx and STM32H563xx Boot modes At startup, a BOOT0 pin and NSBOOTADD[31:8]/SECBOOTADD[31:8] option bytes are used to select the boot memory address that includes: • Boot from any address in user flash memory • Boot from system memory – Bootloader – ST immutable root of trust (ST-iROT) – Root security service (RSS) – Debug authentication library (RSS-DA) Embedded bootloader The embedded bootloader is located in the system memory, programmed by ST during production. It is used to reprogram the flash memory by using USART, I2C, I3C, SPI, FDCAN, or USB_FS in device mode through the DFU (device firmware upgrade). Refer to AN2606 “STM32 microcontroller system memory boot mode”. Embedded root security services (RSS) The embedded RSS are located in the secure information block, programmed by ST during production. Refer to AN4992 “Overview secure firmware install (SFI)”. Embedded immutable root of trust (ST-iROT) The embedded ST-iROT in the system memory, programmed by ST during production. STiROT is the immutable root of trust managing the secure boot and secure install of the first updatable level to execute in a boot sequence. Embedded debug authentication (ST-DA) The embedded ST-DA in the system memory is programmed by ST during production. ST-DA is the library that manages the debug authentication protocol, making it possible to securely reopen the debug or to launch regressions on secured products in the field. 3.7.1 STM32H562/H563xx boot modes Table 3 and Table 4, respectively, provide the detail of the boot mode when TrustZone is disabled (TZEN = 0xC3) and enabled (TZEN = 0xB4). Table 3. STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3) PRODUCT_STATE BOOT0 pin Boot address option byte selection Boot area ST programmed default value Open 0 NSBOOTADD[31:8] Boot address defined by user option byte NSBOOTADD[31:8] Flash: 0x0800 0000 - 1 NA Bootloader Bootloader Provisioning x NA RSS RSS 24/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview Table 3. STM32H562/H563 boot mode when TrustZone is disabled (TZEN = 0xC3) (continued) PRODUCT_STATE BOOT0 pin Boot address option byte selection Boot area ST programmed default value Provisioned, Closed, Locked x NSBOOTADD[31:8] Boot address defined by user option byte NSBOOTADD[31:8] Flash: 0x0800 0000 Table 4. STM32H562/H563 boot mode when TrustZone is enabled (TZEN = 0xB4) PRODUCT_STATE BOOT0 pin Boot address optionbyte selection Boot area ST programmed default value Open 0 SECBOOTADD[31:8] Boot address defined by user option byte SECBOOTADD[31:8] Flash: 0x0C00 0000 - 1 NA Bootloader Bootloader Provisioning x NA RSS RSS Provisioned, TZ_Closed, Closed, Locked x SECBOOTADD[31:8] Boot address defined by user option byte SECBOOTADD[31:8] Flash: 0x0C00 0000 When TrustZone is enabled the boot space must be in secure area. SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address. A unique boot entry option can be selected by setting the SECBOOT_LOCK option bit. 3.8 Global TrustZone controller (GTZC) GTZC is used to configure TrustZone and privileged attributes within the full system. The GTZC includes three different sub-blocks: • TZSC: TrustZone security controller This sub-block defines the secure/privilege state of slave/master peripherals. It also controls the nonsecure area size for the watermark memory peripheral controller (MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about the secure status of each securable peripheral, by sharing with RCC and I/O logic. • TZIC: TrustZone illegal access controller This sub-block gathers all security illegal access events in the system and generates a secure interrupt towards NVIC. • MPCBB: MPCBB: block-based memory protection controller This sub-block controls secure states of all memory blocks (512-byte pages) of the associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone system product having segmented SRAM with programmable-security and privileged attributes. DS14258 Rev 5 25/270 62 Functional overview STM32H562xx and STM32H563xx The GTZC main features are: • Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB • MPCBB and TZIC accessible only with secure transactions – Secure and nonsecure access supported for privileged/non-privileged part of TZSC • Set of registers to define product security settings: – 3.9 Enable illegal access events that may trigger a secure interrupt • Secure/privilege regions for external memories – Secure/privilege access mode for securable peripherals – Secure/privilege access mode for securable legacy masters TrustZone security architecture The security architecture is based on Arm TrustZone with the Armv8-M main extension. The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register. When the TrustZone is enabled, the SAU (security attribution unit) and IDAU (implementation defined attribution unit) define the access permissions based on secure and nonsecure state. • SAU: up to eight SAU configurable regions are available for security attribution. • IDAU: It provides a first memory partition as nonsecure or nonsecure callable attributes. It is then combined with the results from the SAU security attribution and the higher security state is selected. Based on IDAU security attribution, the flash memory, system SRAMs and peripherals memory space is aliased twice for secure and nonsecure states. However, the external memories space is not aliased. 3.9.1 TrustZone peripheral classification When the TrustZone security is active, a peripheral can be either securable or TrustZoneaware type as follows: 3.9.2 • securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to define security properties • TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing a specific TrustZone behavior such as a subset of registers being secure Default TrustZone security state The default system security state is detailed below: • CPU: – • Memory map: – • SAU is fully secure after reset. Consequently, all memory map is fully secure. Up to eight SAU configurable regions are available for security attribution. Flash memory: – 26/270 Cortex-M33 is in secure state after reset. The boot address must be in secure address. Flash memory security area is defined by watermark user options. DS14258 Rev 5 STM32H562xx and STM32H563xx – • FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection watermark based controller) is secure. Peripherals – Securable peripherals are nonsecure after reset. – TrustZone-aware peripherals are nonsecure after reset. Their secure configuration registers are secure. • All GPIOs are secure after reset. • Interrupts: – • 3.10 All SRAMs are secure after reset. MPCBB (memory protection block based controller) is secure. External memories: – • Flash memory block based area is nonsecure after reset. SRAMs: – • Functional overview NVIC: All interrupts are secure after reset. NVIC is banked for secure and nonsecure state. TZIC: All illegal access interrupts are disabled after reset. Power supply management The power controller (PWR) main features are: • • • • Power supplies and supply domains – Core domain (VCORE) – VDD domain – Backup domain (VBAT) – Analog domain (VDDA) – SMPS power stage (VDDSMPS, available only on SMPS packages) – VDDIO2 domain – VDDUSB for USB transceiver System supply voltage regulation – SMPS step down converter – Voltage regulator (LDO) Power supply supervision – POR/PDR monitor – BOR monitor – PVD monitor Power management – Operating modes – Voltage scaling control – Low-power modes • VBAT battery charging • TrustZone security and privileged protection DS14258 Rev 5 27/270 62 Functional overview 3.10.1 STM32H562xx and STM32H563xx Power supply schemes The devices require a 1.71 to 3.6 V VDD operating voltage supply. Several independent supplies can be provided for specific peripherals: • VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins. • VDDA = 1.62 V (ADCs), 1.8 V (DACs), or 2.1 V (VREFBUF) to 3.6 V VDDA is the external analog power supply for ADCs, DACs and voltage reference buffer. This voltage level is independent from VDD, and must preferably be connected to VDD when these peripherals are not used. • VDDSMPS = 1.71 V to 3.6 V VDDSMPS is the external power supply for the SMPS step down converter. It is provided externally through VDDSMPS supply pin and must be connected to the same supply than VDD. • VLXSMPS is the switched SMPS step down converter output. The SMPS power supply pins are available only on packages with SMPS step down converter option. • VDDUSB = 3.0 V to 3.6 V VDDUSB is the external independent power supply for USB transceivers. It is independent from VDD, and must preferably be connected to VDD when the USB is not used. • VDDIO2 = 1.08 V to 3.6 V VDDIO2 is the external power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9). This voltage level is independent from VDD, voltage and must preferably be connected to VDD when those pins are not used. • VBAT = 1.2 V to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. • VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. VREF+ can be grounded when ADC and DAC are not active. VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively. When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disabled. VREF- must always be equal to VSSA. Depending upon the package, the devices embed an LDO and/or an SMPS regulator, to provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3, and embedded flash memory. The SMPS generates this voltage on VCAP (two pins), with a total external capacitor of 10 μF (typical). The SMPS requires an external coil. The LDO generates this voltage on VCAP pin connected to an external capacitor of 2x 2.2 μF (typical). Both regulators can provide four different voltages (voltage scaling), and can operate in Stop modes. 28/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview Figure 2. STM32H562xx and STM32H563xx power supply overview (with SMPS) VDDA domain A/D converters VDDA VSSA D/A converters Voltage reference buffer VDDUSB VSS VDDIO2 VSS USB transceiver VDDIO2 domain VDDIO2 I/O ring VDD domain VDDIO1 I/O ring Reset block Temperature sensor 3 x PLL Internal RC oscillators VCORE domain Core VSS Standby circuitry (Wakeup logic, IWDG) SRAM1 SRAM2 SRAM3 VDD Voltage regulator VCORE 2x VCAP VLXSMPS VDDSMPS VSSSMPS SMPS regulator Digital peripherals Flash memory Low-voltage detector Backup domain VBAT LSE crystal 32kHz oscillator Backup registers RCC_BDCR register RTC TAMP BKPSRAM MSv64010V2 DS14258 Rev 5 29/270 62 Functional overview STM32H562xx and STM32H563xx Figure 3. STM32H562xx and STM32H563xx power supply overview (with LDO) VDDA domain A/D converters VDDA VSSA D/A converters Voltage reference buffer VDDUSB VSS VDDIO2 VSS USB transceiver VDDIO2 domain VDDIO2 I/O ring VDD domain VDDIO1 I/O ring VSS VDD VCORE domain Reset block Temperature sensor 3 x PLL Internal RC oscillators Core SRAM1 SRAM2 SRAM3 Standby circuitry (Wakeup logic, IWDG) VCORE VCAP LDO regulator Digital peripherals Flash memory Low-voltage detector Backup domain VBAT LSE crystal 32kHz oscillator Backup registers RCC_BDCR register RTC TAMP BKPSRAM MSv64011V1 During power-up and power-down phases, the following power sequence requirements must be respected: 30/270 • When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. • During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the powerdown transient phase. DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview Figure 4. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2. 3.10.2 Power supply supervisor The devices have an integrated ultra-low-power brownout reset (BOR) active in all modes; The BOR ensures proper operation of the devices after power on and during power down. The devices remain in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The devices feature an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the devices embed a peripheral voltage monitor that compares the independent supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional supply range. The devices support dynamic voltage scaling to optimize power consumption in Run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system maximum operating frequency. The main regulator operates in the following ranges: • VOS0 (VCORE = 1.35 V) with CPU and peripherals running at up to 250 MHz • VOS1 (VCORE = 1.2 V) with CPU and peripherals running at up to 200 MHz • VOS2 (VCORE = 1.1 V) with CPU and peripherals running at up to 150 MHz • VOS3 (VCORE = 1.0 V) with CPU and peripherals running at up to 100 MHz DS14258 Rev 5 31/270 62 Functional overview STM32H562xx and STM32H563xx Low-power modes By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low-power modes described below: • Sleep mode Only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode This mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI, the HSI, the HSI48, and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). The system clock when exiting from Stop mode can be either HSI up to 64 MHz, or CSI (4 MHz), depending on software configuration. • Standby mode This mode is used to achieve the lowest power consumption with BOR. The PLL, the HSI, the CSI, the HSI48, and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The BOR always remains active. The I/Os state during Standby mode can be retained. After entering Standby mode, SRAMs and register contents are lost, except for registers and backup SRAM in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a WKUP pin event (configurable rising or falling edge), an RTC event (alarm, periodic wake-up, timestamp), or a tamper detection occurs. The tamper detection can be due to external pins or to an internal failure detection. The system clock after wake-up is HSI at 32 MHz. 3.10.3 Reset mode To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). 3.10.4 VBAT operation The VBAT pin allows the device VBAT domain to be powered from an external battery or by an external super-capacitor. The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers, and 4-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode. The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: 32/270 When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation. DS14258 Rev 5 STM32H562xx and STM32H563xx 3.10.5 Functional overview PWR TrustZone security When the TrustZone security is activated by the TZEN option bit, the PWR is switched in TrustZone security mode. The PWR TrustZone security secures the following configuration: • Low-power mode • Wake-up (WKUP) pins • Voltage detection and monitoring • VBAT mode Some of the PWR configuration bits security are defined by the security of other peripherals: 3.11 • The voltage scaling (VOS) configuration is secure when the system clock selection is secure in RCC. • The I/O pull-up/pull-down in Standby mode configuration is secure when the corresponding GPIO is secure. • The backup domain write protection is secure when the RTC is secure. Peripheral interconnect matrix Several peripherals have direct connections between them, for autonomous communication, and to support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency. Depending on the peripherals, these interconnections can operate in Run and Sleep modes. 3.12 Reset and clock controller (RCC) The clock controller distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low-power modes and ensures the clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Clock security system: clock sources can be changed safely on the fly in Run mode through a configuration register. • Clock management: to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals, or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE), can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 64 MHz high-speed internal RC oscillator (HSI), trimmable by software, can supply a PLL. – 4 MHz low-power internal oscillator (CSI), trimmable by software, can supply a PLL. – System PLL, which can be fed by HSE, HSI, or CSI, with a maximum frequency at 250 MHz. DS14258 Rev 5 33/270 62 Functional overview STM32H562xx and STM32H563xx • RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48), can be used to drive the USB. • UCPD kernel clock, derived from HSI clock. The HSI RC oscillator must be enabled prior to the UCPD kernel clock use. • Auxiliary clock source: two ultra-low power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. • Peripheral clock sources: several peripherals have their own independent clock, whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, USB, SDMMC, RNG, FDCAN1, OCTOSPI, and the two SAIs. • Startup clock: after reset, the microcontroller restarts by default with an internal 32 MHz clock (HSI/2). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock automatically switches to HSI and a software interrupt is generated if enabled. LSE failure can also be detected and generates an interrupt. • Clock-out capability: – MCO (microcontroller clock output): outputs one of the internal clocks for external use by the application. – LSCO (low-speed clock output): outputs LSI or LSE in all low-power modes (except VBAT mode). Several prescalers allow AHB and APB frequencies configuration. The maximum frequency of the AHB and the APB clock domains is 250 MHz. 3.12.1 RCC TrustZone security When the TrustZone security is activated by the TZEN option bit, the RCC is switched in TrustZone security mode. The RCC TrustZone security secures some RCC system configuration and peripheral configuration clock from being read or modified by nonsecure accesses: when a peripheral is secure, the related peripheral clock, reset, clock source selection and clock enable during low-power modes control bits are secure. A peripheral is in secure state: 3.13 • when its corresponding SEC security bit is set in the TZSC (TrustZone security controller), for securable peripherals. • when a security feature of this peripheral is enabled through its dedicated bits, for TrustZone-aware peripherals. Clock recovery system (CRS) The devices embed a special block that allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. The trimming is based on the external synchronization signal, derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin, or generated 34/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview by user software. For faster lock-in during startup, automatic and manual trimming actions can be combined. 3.14 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. After reset, all GPIOs are in analog mode to reduce power consumption. If needed, the I/Os alternate function configuration can be locked following a specific sequence, to avoid spurious writing to the I/Os registers. Ten I/Os (PD6, PD7, PG9:14, PB8, PB9) can be independently supplied by a dedicated VDDIO supply. 3.14.1 GPIOs TrustZone security Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O pin is configured as secure, its corresponding configuration bits for alternate function, mode selection, I/O data are secure against a nonsecure access. The associated registers bit access is restricted to a secure software only. After reset, all GPIO ports are secure. 3.15 Multi-AHB bus matrix A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2, SDMMC1, SDMMC2, Ethernet) and the slaves (flash memory, FMC, OCTOSPI, SRAMs, AHB and APB) peripherals. It ensures seamless and efficient operation, even when several high-speed peripherals work simultaneously. 3.16 General purpose direct memory access controller (GPDMA) The GPDMA controller is a bus master and system peripheral. It used to perform programmable data transfers between memory-mapped peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU. The GPDMA main features are: • Dual bidirectional AHB master • Memory-mapped data transfers from a source to a destination: – Peripheral-to-memory – Memory-to-peripheral – Memory-to-memory – Peripheral-to-peripheral • Autonomous data transfers during Sleep mode • Transfers arbitration based on a four-grade programmed priority at a channel level: – One high-priority traffic class, for time-sensitive channels (queue 3) – Three low-priority traffic classes, with a weighted round-robin allocation for non time-sensitive channels (queues 0, 1, 2) DS14258 Rev 5 35/270 62 Functional overview • Per channel event generation, on any of the following events: transfer complete or half transfer complete or data transfer error or user setting error, and/or update linked-list item error or completed suspension • Per channel interrupt generation, with separately programmed interrupt enable per event • Eight concurrent DMA channels: • • • • 36/270 STM32H562xx and STM32H563xx – Per channel FIFO for queuing source and destination transfers – Intra-channel DMA transfers chaining via programmable linked-list into memory, supporting two execution modes: run-to-completion and link step mode – Intra-channel and inter-channel DMA transfers chaining via programmable DMA input triggers connection to DMA task completion events Per linked-list item within a channel: – Separately programmed source and destination transfers – Programmable data handling between source and destination: byte-based reordering, packing or unpacking, padding or truncation, sign extension and left/right realignment – Programmable number of data bytes to be transferred from the source, defining the block level – 12 channels with linear source and destination addressing: either fixed or contiguously incremented addressing, programmed at a block level, between successive single transfers – Four channels with 2D source and destination addressing: programmable signed address offsets between successive burst transfers (non-contiguous addressing within a block, combined with programmable signed address offsets between successive blocks, at a second 2D/repeated block level) – Support for scatter-gather (multi-buffer transfers), data interleaving and de-interleaving via 2D addressing – Programmable DMA request and trigger selection – Programmable DMA half-transfer and transfer complete events generation – Pointer to the next linked-list item and its data structure in memory, with automatic update of the DMA linked-list control registers Debug: – Channel suspend and resume support – Channel status reporting including FIFO level and event flags TrustZone support: – Support for secure and nonsecure DMA transfers, independently at a first channel level, and independently at a source/destination and link sub-levels – Secure and nonsecure interrupts reporting, resulting from any of the respectively secure and nonsecure channels – TrustZone-aware AHB slave port, protecting any DMA secure resource (register, register field) from a nonsecure access Privileged/unprivileged support: – Support for privileged and unprivileged DMA transfers, independently at a channel level – Privileged-aware AHB slave port DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview 3.17 Interrupts and events 3.17.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels and to handle up to 125 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33. The NVIC benefits are the following: • closely coupled NVIC giving low-latency interrupt processing • interrupt entry vector table address passed directly to the core • early processing of interrupts • processing of late arriving higher priority interrupts • support for tail chaining • processor state automatically saved • interrupt entry restored on interrupt exit with no instruction overhead • TrustZone support: NVIC registers banked across secure and nonsecure states The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.17.2 Extended interrupt/event controller (EXTI) The extended interrupts and event controller (EXTI) manages the individual CPU and system wake-up through configurable event inputs. It provides wake-up requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional event generation block (EVG) is needed to generate the CPU event signal. The EXTI wake-up requests allow the system to be woken up from Stop modes. The interrupt request and event request generation can also be used in Run modes. The EXTI also includes the EXTI multiplexer IO port selection. The EXTI main features are the following: • All event inputs allowed to wake up the system • Configurable events (signals from I/Os or peripherals able to generate a pulse) • – Selectable active trigger edge – Interrupt pending status register bit independent for the rising and falling edge – Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt and event generation – Software trigger possibility TrustZone secure events – • The access to control and configuration bits of secure input events can be made secure EXTI IO port selection DS14258 Rev 5 37/270 62 Functional overview 3.18 STM32H562xx and STM32H563xx Cyclic redundancy check calculation unit (CRC) The CRC is used to get a CRC code using a configurable generator with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and that can be stored at a given memory location. 3.19 CORDIC coprocessor (CORDIC) The CORDIC coprocessor provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks. The CORDIC main features are: 3.20 • 24-bit CORDIC rotation engine • Circular and hyperbolic modes • Rotation and vectoring modes • Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural logarithm • Programmable precision • Low-latency AHB slave interface • Results can be read as soon as ready without polling or interrupt • DMA read and write channels • Multiple register read/write by DMA Filter math accelerator (FMAC) The FMAC performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic that allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be done. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. The FMAC main features are: 38/270 • 16 x 16-bit multiplier • 24 + 2-bit accumulator with addition and subtraction • 16-bit input and output data DS14258 Rev 5 STM32H562xx and STM32H563xx 3.21 Functional overview • 256 x 16-bit local memory • Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers • Input and output buffers can be circular • Filter functions: FIR, IIR (direct form 1) • Vector functions: dot product, convolution, correlation • AHB slave interface • DMA read and write data channels Flexible memory controller (FMC) The FMC includes three memory controllers: • NOR/PSRAM memory controller • NAND memory controller • SDRAM memory controller The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – 3.21.1 Static random access memory (SRAM) – NOR flash memory/OneNAND flash memory – PSRAM (four memory banks) – NAND flash memory with ECC hardware to check up to 8 Kbytes of data – Ferroelectric RAM (FRAM, FeRAM) • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) • 8-,16- bit data bus width • Independent chip select control for each memory bank • Independent configuration for each memory bank • Write FIFO LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high-performance solutions using external controllers with dedicated acceleration. 3.21.2 FMC TrustZone security When the TrustZone security is enabled, the whole FMC banks are secure after reset. Nonsecure area can be configured using the TZSC MPCWMx controller. • The FMC NOR/PSRAM bank: – • Up to two nonsecure area can be configured thought the TZSC MPCWM2 controller with a 64-Kbyte granularity The FMC NAND bank: DS14258 Rev 5 39/270 62 Functional overview – STM32H562xx and STM32H563xx Can be either configured as fully secure or fully nonsecure using the TZSC MPCWM3 controller The FMC registers can be configured as secure through the TZSC controller. 3.22 Octo-SPI interface (OCTOSPI) The OCTOSPI supports most external serial memories such as serial PSRAMs, serial NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with the following functional modes: • Indirect mode: all the operations are performed using the OCTOSPI registers. • Status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting. • Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation. The OCTOSPI supports the following protocols with associated frame formats: • the standard frame format with the command, address, alternate byte, dummy cycles and data phase • the HyperBus™ frame format The OCTOSPI offers the following features: 3.22.1 • Three functional modes: Indirect, Status-polling, and Memory-mapped • Read and write support in Memory-mapped mode • Supports for single, dual, quad and octal communication • Dual-quad mode, where eight bits can be sent/received simultaneously by accessing two quad memories in parallel. • SDR (single-data rate) and DTR (double-transfer rate) support • Data strobe support • Fully programmable opcode • Fully programmable frame format • HyperBus support • Integrated FIFO for reception and transmission • 8-, 16-, and 32-bit data accesses allowed • DMA channel for Indirect mode operations • Interrupt generation on FIFO threshold, timeout, operation complete, and access error OCTOSPI TrustZone security When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset. Up to two nonsecure area can be configured thought the TZSC MPCWM1 controller with a granularity of 64 Kbytes. The OCTOSPI registers can be configured as secure through the TZSC controller. 40/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 3.23 Functional overview Delay block (DLYB) The delay block (DLYB) is used to generate an output clock dephased from the input clock. The phase of the output clock must be programmed by the user application. The output clock is then used to clock the data received by another peripheral such as an SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may require the application to re-configure and recenter the output clock phase with the received data. The delay block main features are: 3.24 • Input clock frequency ranging from 25 to 250 MHz • Up to 12 oversampling phases Analog-to-digital converters (ADC1 and ADC2) The devices embed two successive approximation analog-to-digital converters. Table 5. ADC features Mode/feature ADC1 ADC2 Resolution 12 bit Maximum sampling speed 5 Msps (12-bit resolution) Dual mode operation X Hardware offset calibration X Hardware linearity calibration - Single-end input X Differential input X Injected channel conversion X Oversampling Up to x256 Data register 16 bits Data register FIFO depth 3 stages DMA support X Parallel data output to ADF - Offset compensation X Gain compensation - Number of analog watchdogs 3 Option register - DS14258 Rev 5 X 41/270 62 Functional overview 3.24.1 STM32H562xx and STM32H563xx Analog temperature sensor This sensor generates a voltage (VSENSE) that varies linearly with temperature. It is internally connected to an ADC input channel used to convert the output voltage into a digital value. The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the temperature measurement. As the offset depends upon process variation, the uncalibrated internal temperature sensor is suitable for applications that detect only temperature changes. To improve the measurement accuracy, each device is individually factory-calibrated by ST. The calibration data are stored in the system memory area, accessible in read-only mode. 3.24.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC. The VREFINT is internally connected to ADC input channel. The precise voltage of VREFINT is individually measured for each part during manufacturing, and stored in the system memory area. It is accessible in read-only mode. 3.24.3 VBAT battery voltage monitoring This embedded hardware enables the application to measure the VBAT battery voltage using ADC or input channel. As the VBAT voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by four. As a consequence, the converted digital value is a quarter of the VBAT voltage. 3.25 Digital temperature sensor (DTS) The devices embeds a sensor that converts the temperature into a square wave, whose frequency is proportional to the temperature. The PCLK or the LSE clock can be used as reference clock for the measurements. Use the formula given in the product reference manual to calculate the temperature according to the measured frequency stored in the DTS_DR register. 3.26 Digital to analog converter (DAC) The DAC module is a 12-bit voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode, and can be used in conjunction with the DMA controller. In 12-bit mode, the data can be left- or right-aligned. The DAC features two output channels, each with its own converter. In dual DAC channel mode, conversions can be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, VREF+ (shared with others analog peripherals), is available for better resolution. An internal reference can also be set on the same input. The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC output is disconnected from output pad and connected to on chip peripheral. The DAC output buffer can be optionally enabled to allow a high drive output current. An individual 42/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview calibration can be applied on each DAC output channel. The DAC output channels support a low power mode, the Sample and hold mode. The digital interface supports the following features: 3.27 • One DAC interface, maximum two output channels • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave and triangular-wave generation • Sawtooth wave generation • Dual DAC channel for independent or simultaneous conversions • DMA capability for each channel including DMA underrun error detection • Double data DMA capability to reduce the bus activity • External triggers for conversion • DAC output channel buffered/unbuffered modes • Buffer offset calibration • Each DAC output can be disconnected from the DAC_OUTx output pin • DAC output connection to on chip peripherals • Sample and Hold mode for low-power operation in Stop mode. The DAC voltage can be changed autonomously with the DMA while the device is in Stop mode. • Voltage reference input Voltage reference buffer (VREFBUF) The devices embed a voltage reference buffer that can be used as reference for ADCs and DACs, and also as reference for external components through the VREF+ pin. The internal voltage reference buffer supports three voltages: 1.8, 2.048, and 2.5 V. An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. 3.28 Digital camera interface (DCMI) The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG). It can be used with black and white cameras, X24 and X5 cameras (it is assumed that all preprocessing such as resizing is performed in the camera module). Main features: • 8-, 10-, 12-, or 14-bit parallel interface • Embedded/external line and frame synchronization • Continuous or snapshot mode • Crop feature • Support of the following data formats: DS14258 Rev 5 43/270 62 Functional overview 3.29 STM32H562xx and STM32H563xx – 8/10/12/14-bit progressive video: monochrome or raw Bayer – YCbCr 4:2:2 progressive video – RGB 565 progressive video – Compressed data: JPEG Parallel synchronous slave interface (PSSI) The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a result, these two peripherals cannot be used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the same interrupt vector. The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It enables the transmitter to send a data valid signal that indicates when the data is valid, and the receiver to output a flow control signal that indicates when it is ready to sample the data. The PSSI peripheral main features are the following: • Slave mode operation • 8-bit or 16-bit parallel data input or output • 4-word (16-byte) FIFO • Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate function output When selected, these inputs can either enable the transmitter to indicate when the data is valid, or allow the receiver to indicate when it is ready to sample the data, or both. 3.30 True random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a non-deterministic random bit generator (NDRBG). The true random generator: 44/270 • delivers 32-bit true random numbers, produced by an analog entropy source conditioned by a NIST SP800-90B approved conditioning stage • can be used as entropy source to construct a non-deterministic random bit generator (NDRBG) • produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz (256 RNG clock cycles otherwise) • embeds start-up and NIST SP800-90B approved continuous health tests (repetition count and adaptive proportion tests), associated with specific error management • can be disabled to reduce power consumption, or enabled with an automatic low-power mode (default configuration) • has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (else an AHB bus error is generated, and the write accesses are ignored) DS14258 Rev 5 STM32H562xx and STM32H563xx 3.31 Functional overview HASH hardware accelerator (HASH) The HASH is a fully compliant implementation of the secure hash (SHA-1, SHA-224, SHA-256, SHA-512) and the HMAC (keyed-hash message authentication code) algorithms. HMAC is suitable for applications requiring message authentication. The HASH computes FIPS (Federal information processing standards) approved digests of length of 160, 224, 256, 512 bits, for messages of up to (264 – 1). The HASH main features are: • • Suitable for data authentication applications, compliant with: – FIPS PUB 180-4, Secure Hash Standard (SHA-1 and SHA-2 family) – FIPS PUB 186-4, Digital Signature Standard (DSS) – Internet Engineering Task Force (IETF) Request For Comments RFC 2104, HMAC: Keyed-Hashing for Message Authentication and Federal Information Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message Authentication Code (HMAC) Fast computation of SHA-1, SHA-224, SHA-256, SHA-512 – • 3.32 82 (respectively 66) clock cycles for processing one 512-bit block of data using SHA-1 (respectively SHA-256) algorithm Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message – Automatic 32-bit words swapping to comply with the internal little-endian representation of the input bit string – Word swapping supported: bits, bytes, half-words and 32-bit words • Automatic padding to complete the input bit string to fit digest minimum block size of 512 bits (16 × 32 bits) • Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words, corresponding to one block size • AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB error is generated) • 8 × 32-bit words (H0 to H7) for output message digest • Automatic data flow control with support of direct memory access (DMA) using one channel. Single or fixed burst of 4 supported. • Interruptible message digest computation, on a per-32-bit word basis – Re-loadable digest registers – Hashing computation suspend/resume mechanism, including using DMA Public key accelerator (PKA) The PKA can verify ECDSA signatures, with all needed computation performed within the accelerator. The application CPU is needed only to manage the inputs and the outputs of the operation. DS14258 Rev 5 45/270 62 Functional overview STM32H562xx and STM32H563xx The PKA main features are: 3.33 • ECDSA signature verification • Capability to handle operands up to 640 bits • AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (otherwise an AHB bus error is generated, and write accesses are ignored) Timers and watchdogs The devices include two advanced control timers, up to seven general-purpose timers, two basic timers, six low-power timers, two watchdog timers and two SysTick timers. Table 6 compares the features of the advanced control, general-purpose and basic timers. Table 6. Timer features Type Timer Counter resolution Advanced control TIM1, TIM8 16 bits General purpose General purpose Basic 3.33.1 TIM2, TIM5 32 bits TIM3, TIM4 16 bits Counter type Prescaler factor DMA request generation Up, down, up/down Any integer between 1 and 65536 TIM12, TIM15 TIM13, TIM14, TIM16, TIM17 16 bits Up TIM6, TIM7 16 bits Up Yes Capture/ compare channels Complementary outputs 4 3 4 No 4 No 2 1 1 1 0 No Advanced-control timers (TIM1, TIM8) These timers can be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0 - 100 %) • One-pulse mode output In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with the general-purpose TIMx timers (described in the next section) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 46/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 3.33.2 Functional overview General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) The devices embed up to seven synchronizable general-purpose timers (see Table 6), each of them can be used to generate PWM outputs, or act as a simple time base. • TIM2 and TIM5 Full-featured general-purpose timers with 32-bit auto-reload up/down counter and 32-bit prescaler. These timers feature four independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in Debug mode. All have independent DMA request generation and support quadrature encoders. • TIM3 and TIM4 Full-featured general-purpose timers, with 16-bit auto-reload up/down counter and 16-bit prescaler. These timers feature four independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in Debug mode. All have independent DMA request generation and support quadrature encoders. • TIM12, TIM13, TIM14, TIM15, TIM16, and TIM17 General-purpose timers with mid-range features, with 16-bit auto-reload up counter and 16-bit prescaler. – TIM12 and TIM15 have two channels and one complementary channel – TIM13, TIM14, TIM16, and TIM17 have one channel and one complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in Debug mode. 3.33.3 Basic timers (TIM6, TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebase. 3.33.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6) The devices embed six low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wake up the system from Stop mode. The low-power timers support the following features: • 16-bit up counter with 16-bit autoreload register DS14258 Rev 5 47/270 62 Functional overview 3.33.5 STM32H562xx and STM32H563xx • 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128) • Selectable clock – Internal clock sources: LSE, LSI, HSI or APB clock – External clock source over LPTIM input (working with no LP oscillator running, used by Pulse Counter application) • 16-bit ARR autoreload register • 16-bit capture/compare register • Continuous/One-shot mode • Selectable software/hardware input trigger • Programmable digital glitch filter • Configurable output: pulse, PWM • Configurable I/O polarity • Encoder mode (except for LPTIM4) • Repetition counter • Up to two independent channels (except for LPTIM4) for: – Input capture – PWM generation (edge-aligned mode) – One-pulse mode output • Interrupt generation on ten events • DMA request generation on the following events: – Update event – Input capture Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in Debug mode. 3.33.6 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. 3.33.7 SysTick timer The Cortex-M33 with TrustZone embeds two SysTick timers. When TrustZone is activated, two SysTick timer are available: 48/270 • SysTick, secure instance • SysTick, nonsecure instance DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview When TrustZone is disabled, only one SysTick timer is available. This timer (secure or nonsecure) is dedicated to real-time operating systems, but can also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 3.34 Real-time clock (RTC), tamper and backup registers 3.34.1 Real-time clock (RTC) The RTC supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date, month, year, in BCD (binary-coded decimal) format • Binary mode with 32-bit free-running counter • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month • Two programmable alarms • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy • Timestamp feature that can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode • 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable resolution and period • TrustZone support: – RTC fully securable – Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure configuration – Alarm A, alarm B, wake-up timer and timestamp individual privileged protection The RTC is supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The RTC clock sources can be one of the following: • 32.768 kHz external crystal (LSE) • external resonator or oscillator (LSE) • internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) • high-speed external clock (HSE), divided by a prescaler in the RCC. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. DS14258 Rev 5 49/270 62 Functional overview STM32H562xx and STM32H563xx All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up the device from the low-power modes. 3.34.2 Tamper and backup registers (TAMP) The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32 32-bit backup registers are retained in all low-power modes and in VBAT mode. The backup registers, as well as other secrets in the device, are protected by this anti-tamper detection circuit with eight tamper pins and nine internal tampers. The external tamper pins can be configured for edge detection, or level detection with or without filtering, or active tamper that increases the security level by auto checking that the tamper pins are not externally opened or shorted. TAMP main features: • A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches and cryptographic peripherals. • 32 32-bit backup registers: – • Note: The backup registers (TAMP_BKPxR) are implemented in the Backup domain that remains powered-on by VBAT when the VDD power is switched off. Up to 8 tamper pins for 8 external tamper detection events: – Active tamper mode: continuous comparison between tamper output and input to protect from physical open-short attacks – Flexible active tamper I/O management: from 4 meshes (each input associated to its own exclusive output) to 7 meshes (single output shared for up to 7 tamper inputs) – Passive tampers: ultra-low power edge or level detection with internal pull-up hardware management – Configurable digital filter As input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT modes. As output, only PC13 and PA1, and PI8 are functional in Standby and VBAT modes. • Internal tamper events to protect against transient or environmental perturbation attacks • Each tamper can be configured in two modes: – Hardware mode: immediate erase of secrets on tamper detection, including backup registers erase – Software mode: erase of secrets following a tamper detection launched by software • Any tamper detection can generate an RTC time stamp event. • TrustZone support: – Tamper secure or nonsecure configuration. – Backup registers configuration in three configurable-size areas: - 1 read/write secure area - 1 write secure/read nonsecure area - 1 read/write nonsecure area – 50/270 Secret key, stored in backup registers, protected against read and write access • Tamper configuration and backup registers privilege protection • Monotonic counter DS14258 Rev 5 STM32H562xx and STM32H563xx 3.35 Functional overview Inter-integrated circuit interface (I2C) The devices embed four I2Cs. Refer to Table 7 for the implemented features. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Target and controller modes, multicontroller capability – Standard-mode (Sm), with a bit rate up to 100 Kbit/s – Fast-mode (Fm), with a bit rate up to 400 Kbit/s – Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os – 7- and 10-bit addressing modes, multiple 7-bit target addresses – Programmable setup and hold times – Optional clock stretching System management bus (SMBus) specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power system management protocol (PMBus) specification rev 1.3 compatibility • Independent clock: a choice of independent clock sources allowing the I2C commun.ication speed to be independent from the PCLK reprogramming • Wake-up from Stop capability • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 7. I2C implementation Feature(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 Kbit/s) X X X X Fast-mode (up to 400 Kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X Wake-up capability X X X X 1. X: supported DS14258 Rev 5 51/270 62 Functional overview 3.36 STM32H562xx and STM32H563xx Improved inter-integrated circuit (I3C) The I3C interface handles communication between the MCU and others, like sensors and host processor(s), all connected on an I3C bus. The peripheral implements the required features of the MIPI I3C specification v1.1. It can control I3C bus-specific sequencing, protocol, arbitration and timing, and can act as controller (formerly known as master) or as target (formerly known as slave). When acting as controller the peripheral improves the features of the I2C interface, preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not perform clock stretching. The I3C peripheral can be used with DMA to off-load the CPU. Table 8. I3C peripheral controller/target features versus MIPI v1.1 Feature MIPI When When v1.1 controller target Comments I3C SDR message X X X Legacy I2C message (Fm/Fm+) X X - HDR DDR message X - - HDR-TSL/TSP, HDR-BT X - - Dynamic address assignment X X X Static address X X - No (intended) support of I3C peripheral as a target on an I2C bus. Grouped addressing X X - Optional in MIPI v1.1 CCCs X X X Mandatory and some optional CCCs supported. Error detection and recovery X X X - In-band interrupt (with MDB) X X X - Secondary controller X X X - Hot-join mechanism X X X - Target reset X X X - Synchronous timing control X X - Asynchronous timing control 0 X X - Asynchronous timing control 1, 2, 3 X - - Device to device tunneling X X - Multi-lane data transfer X X - Monitoring device early termination X - - 52/270 Mandatory when controller, and the I3C bus is mixed with (external) legacy I2C target(s). Optional in MIPI v1.1 when target. Optional in MIPI v1.1 - Optional in MIPI v1.1 DS14258 Rev 5 STM32H562xx and STM32H563xx 3.37 Functional overview Universal synchronous/asynchronous receiver transmitter (USART/UART) and low-power universal asynchronous receiver transmitter (LPUART) The devices have six embedded universal synchronous receiver transmitters (USART1/USART2/USART3/USART6/USART10/USART11), six universal asynchronous receiver transmitters (UART4/UART5/UART7/UART8/UART9/UART12), and one low-power universal asynchronous receiver transmitter (LPUART1). Table 9. USART, UART and LPUART features USART 1/2/3/6/10/11 UART 4/5/7/8/9/12 LPUART 1 Hardware flow control for modem X X X Continuous communication using DMA X X X Multiprocessor communication X X X Synchronous mode (master/slave) X - - Smartcard mode X - - Single-wire half-duplex communication X X X IrDA SIR ENDEC block X X - LIN mode X X - Dual-clock domain and wake-up from Stop mode (2) X(2) X(2) Mode/feature(1) X Receiver timeout interrupt X X - Modbus communication X X - Auto-baud rate detection X X - Driver enable X X X USART data length 7, 8, and 9 bits Tx/Rx FIFO X Tx/Rx FIFO size X X 8 bytes 1. X = supported. 2. Wake-up supported from Stop mode. 3.37.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) The USART offers a flexible means to perform full-duplex data exchange with external equipments requiring an industry standard NRZ asynchronous serial data format. A very wide range of baud rates can be achieved through a fractional baud rate generator. The USART supports both synchronous one-way and half-duplex single-wire communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA (infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS). Multiprocessor communications are also supported. High-speed data communication (up to 20 Mbauds) is possible by using the DMA (direct memory access) for multibuffer configuration. DS14258 Rev 5 53/270 62 Functional overview STM32H562xx and STM32H563xx The USART main features are: • Full-duplex asynchronous communication • NRZ standard format (mark/space) • Configurable oversampling method by 16 or by 8, to achieve the best compromise between speed and clock tolerance • Baud rate generator systems • Two internal FIFOs for transmit and receive data Each FIFO can be enabled/disabled by software and come with a status flag. • A common programmable transmit and receive baud rate • Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK • Auto baud rate detection • Programmable data word length (7, 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Synchronous Master/Slave mode and clock output/input for synchronous communications • SPI slave transmission underrun error flag • Single-wire half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Interrupt sources with flags • Multiprocessor communications: wake-up from Mute mode by idle line detection or address mark detection • Autonomous functionality in Stop mode with wake-up from stop capability • LIN master synchronous break send capability and LIN slave break detection capability – • IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode • Smartcard mode • 54/270 13-bit break generation and 10/11-bit break detection when USART is hardware configured for LIN – Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in the ISO/IEC 7816-3 standard – 0.5 and 1.5 stop bits for Smartcard operation Support for Modbus communication – Timeout feature – CR/LF character recognition DS14258 Rev 5 STM32H562xx and STM32H563xx 3.37.2 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The LPUART supports bidirectional asynchronous serial communication with minimum power consumption. It also supports half-duplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher-speed clock can be used to reach higher baud-rates. The LPUART interface can be served by the DMA controller. The LPUART main features are: • Full-duplex asynchronous communications • NRZ standard format (mark/space) • Programmable baud rate • From 300 to 9600 bauds using a 32.768 kHz clock source • Higher baud rates can be achieved by using a higher frequency clock source • Two internal FIFOs to transmit and receive data Each FIFO can be enabled/disabled by software and come with status flags for FIFOs states. • Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK • Programmable data word length (7 or 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Single-wire half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Transfer detection flags: • • • – Receive buffer full – Transmit buffer empty – Busy and end of transmission flags Parity control: – Transmits parity bit – Checks parity of received data byte Four error detection flags: – Overrun error – Noise detection – Frame error – Parity error Interrupt sources with flags DS14258 Rev 5 55/270 62 Functional overview 3.38 STM32H562xx and STM32H563xx • Multiprocessor communications: wake-up from Mute mode by idle line detection or address mark detection • Wake-up from Stop capability Serial peripheral interface (SPI) / inter-integrated sound interfaces (I2S) The devices embed six serial peripheral interfaces (SPI) that can be used to communicate with external devices while using the specific synchronous protocol. The SPI protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master or slave, and can operate in multi-slave or multimaster configurations. The device configured as master provides communication clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied optionally just to set up communication with concrete slave and to assure it handles the data flow properly. The Motorola data format is used by default, but some other specific modes are supported as well. The SPI main features are: 56/270 • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) • 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only • Multi master or multi slave mode capability • Dual-clock domain, separated clock for the peripheral kernel that can be independent of PCLK • Baud rate prescaler up to kernel frequency divided by 2 or bypass from RCC in Master mode • Protection of configuration and setting • Hardware or software management of SS for both master and slave • Adjustable minimum delays between data and between SS and data flow • Configurable SS signal polarity and timing, MISO x MOSI swap capability • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Programmable number of data within a transaction to control SS and CRC • Dedicated transmission and reception flags with interrupt capability • SPI Motorola and TI formats support • Hardware CRC feature can secure communication at the end of transaction by: – Adding CRC value in Tx mode – Automatic CRC error checking for Rx mode • Error detection with interrupt capability in case of data overrun, CRC error, data underrun at slave, mode fault at master • Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability • Programmable number of data in transaction • Configurable FIFO thresholds (data packing) DS14258 Rev 5 STM32H562xx and STM32H563xx Functional overview • Configurable behavior at slave underrun condition (support of cascaded circular buffers) • Wake-up from Stop capability • Optional status pin RDY signalizing the slave device ready to handle the data flow. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in Master or Slave mode, in full-duplex communication modes, and can be configured to operate with configurable resolution as input or output channel. I2S main features: • Full duplex communication • Simplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler • Data length may be 16, 24 or 32 bits • Channel length can be 16 or 32 in master, any value in slave • Programmable clock polarity • Error flags signaling for improved reliability: Underrun, Overrun, and Frame Error • Embedded Rx and TxFIFOs • Supported I2S protocols: – I2S Philips standard – MSB-Justified standard (left-justified) – LSB-Justified standard (right-justified) – PCM standard (with short and long frame synchronization) • Data ordering programmable (LSb or MSb first) • DMA capability for transmission and reception • Master clock can be output to drive an external audio component. The ratio is fixed at 256 x FWS (where FWS is the audio sampling frequency) Table 10. SPI features SPI1, SPI2, SPI3 (full feature set instances) SPI4, SPI5, SPI6 (full feature set instances) Data size Configurable from 4- to 32-bit Configurable from 4- to 16-bit CRC computation CRC polynomial length configurable from 5- to 33-bit CRC polynomial length configurable from 5- to 17-bit 16x 8-bit 8x 8-bit Feature Size of FIFOs Number of transfered data Up to 65535 I2S feature 3.39 Yes No Serial audio interface (SAI) The devices embed two SAIs. Refer to Table 11 for the features implementation. The SAI bus interface handles communications between the MCU and the serial audio protocol. DS14258 Rev 5 57/270 62 Functional overview STM32H562xx and STM32H563xx The SAI peripheral supports: • Two independent audio sub-blocks that can be transmitters or receivers with their respective FIFO • 8-word integrated FIFOs for each audio sub-block • Synchronous or Asynchronous mode between the audio sub-blocks • Master or slave configuration independent for both audio sub-blocks • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit • Peripheral with large configurability and flexibility, allowing to target the following audio protocols: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame • Number of bits by frame may be configurable • Frame synchronization active level configurable (offset, bit length, level) • First active bit position in the slot is configurable • LSB first or MSB first for data transfer • Mute mode • Stereo/mono audio frame capability • Communication clock strobing edge configurable (SCK) • Error flags with associated interrupts if enabled respectively • • – Overrun and underrun detection – Anticipated frame synchronization signal detection in Slave mode – Late frame synchronization signal detection in Slave mode – Codec not ready for the AC’97 mode in reception Interruption sources when enabled: – Errors – FIFO requests DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. Table 11. SAI implementation Feature(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 words) X (8 words) SPDIF X X PDM X - FIFO size 1. X: supported 58/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 3.40 Functional overview Secure digital input/output and MultiMediaCards interface (SDMMC) The SD/SDIO, embedded MultiMediaCard (eMMC™) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards, and eMMC devices. The MultiMediaCard system specifications are available through the MultiMediaCard association website at www.mmca.org, published by the MMCA technical committee. SD memory card and SD I/O card system specifications are available through the SD card association website at www.sdcard.org. The SDMMC features include the following: • Compliance with Embedded MultiMediaCard System Specification Version 5.1 Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit (HS200 SDMMC_CK speed limited to maximum allowed I/O speed, HS400 is not supported). • • Full compatibility with previous versions of MultiMediaCards (backward compatibility). Full compliance with SD memory card specifications version 6.0 (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). • Full compliance with SDIO card specification version 4.0 Card support for two different databus modes: 1-bit (default) and 4-bit (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). • Data transfer up to 208 Mbyte/s for the 8-bit mode, depending maximum allowed I/O speed. • Data and command output enable signals to control external bidirectional drivers • IDMA linked list support The MultiMediaCard/SD bus connects cards to the host. The current version of the SDMMC supports only one SD/SDIO/eMMC card at any one time and a stack of eMMC. Table 12. SDMMC features Mode/feature (1) SDMMC1 SDMMC2 Variable delay (SDR104, HS200) X X SDMMC_CKIN X X SDMMC_CDIR, SDMMC_D0DIR X - SDMMC_D123DIR X - 1. X = supported. DS14258 Rev 5 59/270 62 Functional overview STM32H562xx and STM32H563xx When SDMMC peripherals are used simultaneously: 3.41 • Only one can be used in eMMC with 8-bit bus width. • Usage of SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 eMMC with 8-bit bus width. • If SDMMC1 must support SDIO UHS-I modes (SDR12, SDR25, SDR50, SDR104, or DDR50), SDMMC2 cannot support eMMC with 8-bit bus width. • If SDMMC2 must support eMMC with 8-bit bus width, SDMMC1 can only support SDIO Default mode and High-speed mode. Controller area network (FDCAN) The controller area network (CAN) subsystem consists of one CAN module, a shared message RAM memory and a configuration block. The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and transmits FIFOs. The FDCAN main features are: 3.42 • Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4 • CAN FD with maximum 64 data bytes supported • CAN error logging • AUTOSAR and J1939 support • Improved acceptance filtering • Two receive FIFOs of three payloads each (up to 64 bytes per payload) • Separate signaling on reception of high priority messages • Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload) • Configurable transmit Event FIFO • Programmable loop-back test mode • Maskable module interrupts • Two clock domains: APB bus interface and CAN core kernel clock • Power-down support USB full speed (USB) USB main features: 60/270 • USB specification version 2.0 full-speed compliant • Host and device functions • 2048 bytes of dedicated SRAM data buffer memory with 32-bit access • USB clock recovery • Configurable number of endpoints from 1 to 8 • Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted (NRZI) encoding/decoding and bit-stuffing • Isochronous transfers support DS14258 Rev 5 STM32H562xx and STM32H563xx 3.43 Functional overview • Double-buffered bulk/isochronous endpoint support • USB suspend/resume operations • Frame-locked clock pulse generation • USB 2.0 Link power management support • Battery charging specification revision 1.2 support in device USB Type-C/USB Power Delivery controller (UCPD) The devices embed one controller (UCPD) compliant with USB Type-C Cable and Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications. The controller uses specific I/Os supporting the USB Type-C and USB power delivery requirements, featuring: • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB power delivery message transmission and reception • FRS (fast role swap) support The digital controller handles: • USB Type-C level detection with debounce, generating interrupts • FRS detection, generating an interrupt • Byte-level interface for USB power delivery payload, generating interrupts (DMA compatible) • USB power delivery timing dividers (including a clock pre-scaler) • CRC generation/checking • 4b5b encode/decode • Ordered sets (with a programmable ordered set mask at receive) • Frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB power delivery messages and FRS signaling. 3.44 Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for Ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: • Support of 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation DS14258 Rev 5 61/270 62 Functional overview 3.45 STM32H562xx and STM32H563xx • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal 2-Kbyte FIFOs to buffer transmit and receive frames • Support of hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Trigger of interrupt when system time becomes greater than target time High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed an HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wake up the MCU from Stop mode on data reception. 3.46 Development support 3.46.1 Serial-wire/JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.46.2 Embedded Trace Macrocell The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The ETM operates with third party debugger software tools. 62/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions 4 Pinout, pin description, and alternate functions 4.1 Pinout/ballout schematics VSS VCAP PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 VCAP VSS VDD LQFP64 MSv67303V4 VDD 64 Figure 5. LQFP64 pinout 1. The above figure shows the package top view. DS14258 Rev 5 63/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx VDD VSS VCAP PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PC12 PC11 PC10 PA15 PA14 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Figure 6. VFQFPN68 pinout VBAT 1 51 PC13 2 50 PC14-OSC32_IN 3 49 PC15-OSC32_OUT 4 48 PH0-OSC_IN 5 47 PH1-OSC_OUT 6 46 NRST 7 45 PC0 8 44 PC1 9 PC2 10 42 PC3 VFQFPN68 43 11 41 VSSA 12 40 VDDA 13 39 PA0 14 38 PA1 15 37 PA2 16 PA3 17 36 Exposed pad 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP VSS VDD PB12 35 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD12 PD11 PB15 PB14 PB13 VSS MS56628V1 1. The above figure shows the package top view. 2. VSS pads are connected to the exposed pad. Figure 7. WLCSP80 SMPS ballout 1 A B C D E F G H J K L M N P R T 2 VDD 3 4 PD0 VDDUSB PA12 VSS VDD PA8 VSS PD15 PC6 PD14 PB15 PC7 PB13 VSS VCAP PC3 PA2 PB1 VLXSMP S PC2 VSSA VSS PB0 PE7 PH0OSC_IN PA0 PC5 PE9 VDD PH1OSC_OU T PA5 PC4 PB10 VDDSMP S VDD VSS PA1 PE8 PC15OSC32_ OUT PC0 PA7 PE10 VSSSMP S PB8 PC1 PB2 PC14OSC32_I N NRST PA6 PC8 PB12 PB14 PB6 PA10 PA9 VBAT PC13 BOOT0 PC12 10 VCAP PB7 PC11 9 VSS PB5 PA13 8 VDD PB3 PA14 7 PB4 PA15 PC9 6 PD2 PD1 PC10 PA11 5 VDDA PA4 VDD PA3 MSv73080V1 1. The above figure shows the package top view. 64/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions VDD VSS VCAP PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 8. LQFP100 pinout PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDDUSB PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP VSS VDD LQFP100 MSv67304V3 1. The above figure shows the package top view. DS14258 Rev 5 65/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx VDD VSS VCAP PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 9. LQFP100 SMPS pinout PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDDUSB PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF+ 20 56 PD9 VDDA 21 55 PD8 PA0 22 54 PB15 PA1 23 53 PB14 PA2 24 52 PB13 PA3 25 51 VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS VDD PA4 PA5 PA6 PA7 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VLXSMPS VDDSMPS VSSSMPS VCAP VSS LQFP100 MSv64012V3 1. The above figure shows the package top view. 66/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS VCAP PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDIO2 VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 10. LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 MSv67305V3 1. The above figure shows the package top view. DS14258 Rev 5 67/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG10 PG9 PD7 PD6 VDDIO2 VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 11. LQFP144 SMPS pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 VDD VSS VDD PA4 PA5 PA6 PA7 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VLXSMPS VDDSMPS VSSSMPS VCAP VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREF+ VDDA PA0 PA1 PA2 PA3 1. The above figure shows the package top view. 68/270 DS14258 Rev 5 MSv64013V3 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions Figure 12. UFBGA169 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 A PE2 PI7 VDD PB9 PB6 PB4 VDDIO2 PG10 PD3 VDD PC11 PA14 PI2 B PC14OSC32 _IN PE3 VSS VCAP BOOT0 PG15 VSS PD7 PC12 VSS PA15 PI1 PI0 C PC15OSC32 _OUT PE5 PI6 PI4 PE0 PB5 PG14 PG12 PD2 PC10 PI3 VSS VDD D VDD VSS PE6 PE4 PE1 PB7 PG13 PD5 PD0 PH14 PH15 PH13 VDDUS B E PF1 VBAT PI8 PC13 PB8 PB3 PG11 PD6 PD1 PA10 PA9 PA13 PA12 F PF4 PF2 PF0 PI11 PF3 PF5 PG9 PD4 PC6 PC7 PG8 PA8 PA11 G VDD VSS PF7 PF6 PF8 PF10 PE8 PG7 PG3 PG5 PG6 PC8 PC9 H PH0OSC_IN PH1OSC_O UT PF9 NRST PC3 PC5 PF13 PE10 PD15 PD11 PD14 VSS VDD J PC0 PC1 PC2 PA0 PA1 PF11 PF15 PE14 PD9 PB15 PD10 PG2 PG4 K VREF- VSSA PH2 PA5 PA7 PB1 PG1 PE12 PB10 PH6 PB12 PD12 PD13 L VDDA VREF+ PA2 PA4 PB0 PB2 PG0 PE9 PE13 PH7 PB13 PD8 VDD M VDD VSS PH5 VSS PA6 PF14 VSS PE11 PB11 PH8 PH10 VSS PB14 N PH4 PH3 PA3 VDD PC4 PF12 VDD PE7 PE15 VCAP VDD PH11 PH12 MSv68827V2 1. The above figure shows the package top view. DS14258 Rev 5 69/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx Figure 13. UFBGA169 SMPS ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 A PI7 PI6 VDD VCAP PB4 VDDIO2 PD5 VDD PC11 PC10 VDD PI3 PH15 B VDD VSS PI5 VSS BOOT0 PG15 PD7 VSS PD1 PA15 VSS PI0 PA12 C VBAT PE5 PE2 PI4 PE1 PB6 PG10 PD3 PD0 PA14 PI1 PH13 PA11 D PC14OSC32 _IN PE6 PE4 PE3 PE0 PB7 PG12 PD4 PC12 PI2 PH14 PA13 VDD E PC15OSC32 _OUT PF0 PC13 PI8 PB9 PB5 PG9 PD2 PC8 PA8 PA10 VSS VDDUS B F PF7 VSS PF1 PF2 PB8 PB3 PD6 PG5 PG7 PC6 PC7 PC9 PA9 G VDD PF9 PF5 PF8 PF4 PF3 PF6 PD13 PG3 PD15 PG4 PG6 PG8 H PH0OSC_IN VSS NRST PF10 PA1 PB1 PF13 PD11 PD9 PB15 PD12 PD14 PG2 J PH1OSC_O UT PC0 PC1 PH2 PA5 PF11 PF15 PE8 PE14 PB14 PD8 VSS VDD K PC2 PC3 PA0 PA3 PA7 PF12 PG1 PE13 PB10 PH10 PB12 PB13 PD10 L VSSA VREF- PA2 PH5 PC4 PF14 PE7 PE10 PE15 PB11 PH7 PH12 PH11 M VDDA VREF+ VSS PA4 PC5 PG0 VSS PE11 PE12 VSSSM PS VSS PH8 PH9 N PH4 PH3 VDD PA6 PB0 PB2 VDD PE9 VLXSM PS VDDSM PS VCAP VDD PH6 MSv64014V3 1. The above figure shows the package top view. 70/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 VDD VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDIO2 VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 Figure 14. LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD PH12 PH11 PH4 PH5 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDD PH6 PH7 PH8 PH9 PH10 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14-OSC32_IN PC15-OSC32_OUT PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 MSv67307V3 1. The above figure shows the package top view. DS14258 Rev 5 71/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 VDD VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDIO2 VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 Figure 15. LQFP176 SMPS pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PI1 PI0 PH15 PH14 PH13 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VSS PH12 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VLXSMPS VDDSMPS VSSSMPS VCAP VSS VDD PH6 PH7 PH9 PH10 PH11 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14-OSC32_IN PC15-OSC32_OUT PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 PH2 PH3 PA3 MSv67301V3 1. The above figure shows the package top view. 72/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Pinout, pin description, and alternate functions Figure 16. UFBGA176+25 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD VCAP VDD VDDIO2 VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14OSC32_ IN PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15OSC32_ OUT VSS VDD PH2 VSS VSS VSS VSS VSS VSS VDD PC9 PA8 G PH0OSC_IN VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1OSC_O UT PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUS B PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 VSS PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 MSv67306V3 1. The above figure shows the package top view. DS14258 Rev 5 73/270 75 Pinout, pin description, and alternate functions STM32H562xx and STM32H563xx Figure 17. UFBGA176+25 SMPS ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A PI7 PI5 VCAP PB9 BOOT0 PB5 PG15 PG14 PG10 PD7 PD5 PD3 PD1 PI3 PI1 B VBAT PE3 PI4 PE1 PB8 PB6 PB3 PG12 PG9 PD6 PD4 PD0 PA14 PI2 PH13 C VSS PE6 PE4 PI6 PE0 PB7 PB4 PG13 PG11 PD2 PC12 PC11 PA15 PH15 PA12 PE5 PE2 VDD VSS VDDIO2 VDD VSS VDD VSS PC10 PH14 VSS PA11 VDD PA13 PA10 PA9 D PC15PC14OSC32_ OSC32_ OUT IN E PI9 PI8 PC13 VDD F PF1 PF0 PI11 PI10 VSS VSS VSS VSS VSS VDD33U SB PC9 PC8 PA8 G PF4 PF3 PF2 VSS VSS VSS VSS VSS VSS VSS PC7 PC6 PG8 H PF6 PF8 PF5 VDD VSS VSS VSS VSS VSS VSS PG7 PG3 PG5 J PH0OSC_IN PH1OSC_O UT PF9 PF10 VSS VSS VSS VSS VSS VDD PD15 PG6 PG4 K VSS PF7 NRST PC2 VSS VSS VSS VSS VSS PD10 PD14 PD12 PG2 L PC0 PC1 PA1 VDD PB12 PD9 PD11 PD13 M VDDA VSSA PA2 VSS PA4 VDD VSS VDD VSS PB10 VDD PH9 PH12 PB15 PD8 N VREF+ VREF- PC3 PC4 PA3 PB1 PF12 PF15 PE9 PE14 PE15 PB11 PH8 PH10 PB14 P PH5 PA0 PH3 PC5 PA6 PB2 PF13 PG1 PE8 PE11 PE13 VSSSM PS PH6 PH7 PH11 R PH4 PH2 PA5 PA7 PB0 PF11 PF14 PG0 PE7 PE10 PE12 VLXSM PS VDDSM PS VCAP PB13 MSv67300V3 1. The above figure shows the package top view. 74/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 4.2 Pinout, pin description, and alternate functions Pin description Table 13. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input/output pin FT 5 V-tolerant I/O TT 3.6 V-tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os(1) I/O structure Notes _a I/O, with analog switch function supplied by VDDA _c I/O with USB Type-C power delivery function _d I/O with USB Type-C power delivery dead battery function _f I/O, Fm+ capable _h I/O with high-speed low-voltage mode _s I/O supplied only by VDDIO2 _t I/O with tamper function functional in VBAT mode _u I/O, with USB function supplied by VDDUSB Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in the following table are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a. DS14258 Rev 5 75/270 75 76/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition DS14258 Rev 5 C3 1 D4 - 1 1 A1 1 A2 - PE2 I/O FT_h - - 2 2 D4 2 B2 - 2 2 B2 2 A1 - PE3 I/O FT_h - TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX, FMC_A19, EVENTOUT TAMP_IN6/TAMP_OUT3 - 3 3 D3 3 C3 - 3 3 D4 3 B1 - PE4 I/O FT_h - TRACED1, SAI1_D2, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4/PSSI_D4, EVENTOUT TAMP_IN7/TAMP_OUT8 - 4 4 C2 4 D3 - 4 4 C2 4 B2 - PE5 I/O FT_h - TRACED2, SAI1_CK2, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6/PSSI_D6, EVENTOUT TAMP_IN8/TAMP_OUT7 TAMP_IN3/TAMP_OUT6 LQFP176 1 LQFP144 1 LQFP100 - TRACECLK, LPTIM1_IN2, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, USART10_RX, UART8_TX, OCTOSPI1_IO2, ETH_MII_TXD3, FMC_A23, DCMI_D3/PSSI_D3, EVENTOUT LQFP64 Alternate functions Additional functions - - 5 5 D2 5 C2 - 5 5 D3 5 B3 - PE6 I/O FT_h - TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7/PSSI_D7, EVENTOUT A1 - - - - - - - - - - - - VDD S - - - - B8 - - - - - - - - - - - - VSS S - - - - B10 6 6 C1 6 B1 1 6 6 E2 6 C1 1 VBAT S - - - - D2 - - - - - - - - - - - - VSS S - - - - STM32H562xx and STM32H563xx Notes I/O structure Pin name (function after reset)(3)(4) Pin type VFQFPN68 UFBGA176+25 UFBGA169 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - - E4 7 E2 - - - E3 7 D2 - PI8 I/O FT_t (5) EVENTOUT TAMP_IN2/TAMP_OUT3, RTC_OUT2, WKUP3 C9 7 7 E3 8 E3 2 7 7 E4 8 D1 2 PC13 I/O FT_t (5) EVENTOUT TAMP_IN1/TAMP_OUT2/ TAMP_OUT3, RTC_OUT1/ RTC_TS, WKUP4 G9 - - - - - - - - - - - - VSS S - - - - D10 8 8 D1 9 D2 3 8 8 B1 9 E1 3 PC14OSC32_IN (OSC32_IN) I/O FT - EVENTOUT OSC32_IN F10 9 9 E1 10 D1 4 9 9 C1 10 F1 4 PC15OSC32_OUT (OSC32_OUT) I/O FT - EVENTOUT OSC32_OUT - - - - 11 E1 - - - - 11 D3 - PI9 I/O FT_h - UART4_RX, FDCAN1_RX, EVENTOUT - - - - - 12 F4 - - - - 12 E3 - PI10 I/O FT_h - FDCAN1_RX, ETH_MII_RX_ER, PSSI_D14, EVENTOUT - - - - - 13 F3 - - - F4 13 E4 - PI11 I/O FT - PSSI_D15, EVENTOUT TAMP_IN4/TAMP_OUT5 - - - B2 14 C1 - - - D2 14 D5 - VSS S - - - - - - - B1 15 D5 - - - D1 15 C5 - VDD S - - - - - - 10 E2 16 F2 - - 10 F3 16 E2 - PF0 I/O FT_f - I2C2_SDA, FMC_A0, LPTIM5_CH1, EVENTOUT - - - 11 F3 17 F1 - - 11 E1 17 H3 - PF1 I/O FT_f - I2C2_SCL, FMC_A1, LPTIM5_CH2, EVENTOUT - Pin name (function after reset)(3)(4) Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 77/270 78/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - 12 F4 18 G3 - - 12 F2 18 H2 - PF2 I/O FT_h - LPTIM3_CH2, LPTIM3_IN2, I2C2_SMBA, UART12_TX, USART11_CK, FMC_A2, LPTIM5_IN1, EVENTOUT - - - 13 G6 19 G2 - - 13 F5 19 J2 - PF3 I/O FT_h - LPTIM3_IN1, USART11_TX, FMC_A3, LPTIM5_IN2, EVENTOUT - - - 14 G5 20 G1 - - 14 F1 20 J3 - PF4 I/O FT_h - LPTIM3_ETR, USART11_RX, FMC_A4, EVENTOUT - - Pin name (function after reset)(3)(4) Additional functions - 15 G3 21 H3 - - 15 F6 21 K3 - PF5 I/O FT_fh - H2 10 16 F2 22 G4 - 10 16 G2 22 F2 - VSS S - - - - A7 11 17 G1 23 E4 - 11 17 G1 23 F3 - VDD S - - - - - - 18 G7 24 H1 - - 18 G4 24 K2 - PF6 I/O FT_h - TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, OCTOSPI1_IO3, LPTIM5_CH1, EVENTOUT - - - 19 F1 25 K2 - - 19 G3 25 K1 - PF7 I/O FT_h - TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, OCTOSPI1_IO2, LPTIM5_CH2, EVENTOUT - - TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, TIM13_CH1, OCTOSPI1_IO0, LPTIM5_IN1, EVENTOUT - - - 20 G4 26 H2 - - 20 G5 26 L3 - PF8 I/O FT_h STM32H562xx and STM32H563xx - LPTIM3_CH1, I2C4_SCL, I3C1_SCL, UART12_RX, USART11_CTS/USART11_NSS, FMC_A5, LPTIM3_IN1, EVENTOUT LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - 21 G2 27 J3 - - 21 H3 27 L2 - PF9 I/O FT_h - TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, OCTOSPI1_IO1, LPTIM5_IN2, EVENTOUT - - - 22 H4 - J4 - - 22 G6 28 L1 - PF10 I/O FT_h - TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPI1_CLK, DCMI_D11/PSSI_D11, EVENTOUT - K10 12 23 H1 28 J1 5 12 23 H1 29 G1 5 PH0OSC_IN(PH0) I/O FT - EVENTOUT OSC_IN J9 13 24 J1 29 J2 6 13 24 H2 30 H1 6 PH1OSC_OUT(PH1) I/O FT - EVENTOUT OSC_OUT F8 14 25 H3 30 K3 7 14 25 H4 31 J1 7 NRST I/O RST - - - - TIM16_BKIN, SAI1_MCLK_A, SPI2_RDY, SAI2_FS_B, FMC_A25, OCTOSPI1_IO7, FMC_SDNWE, EVENTOUT ADC12_INP10 - TRACED0, SAI1_D1, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, USART11_RTS/USART11_DE, SAI2_SD_A, SDMMC2_CK, OCTOSPI1_IO4, ETH_MDC, EVENTOUT ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5, WKUP6 - PWR_CSLEEP, TIM17_CH1, TIM4_CH4, SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5, OCTOSPI1_IO2, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC12_INP12, ADC12_INN11 H8 G7 M10 15 16 17 26 27 28 J2 J3 K1 31 32 33 L1 L2 K4 8 9 10 15 16 17 26 27 28 J1 J2 J3 32 33 34 M2 M3 M4 8 9 10 Pin name (function after reset)(3)(4) PC0 PC1 PC2 I/O I/O I/O FT_a FT_ah FT_a Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 79/270 80/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) DS14258 Rev 5 29 K2 34 N3 11 18 29 H5 35 M5 11 PC3 I/O FT_a - G1 - - - 35 H4 - - 30 M1 36 G3 - VDD S - - - LQFP176 18 LQFP144 L9 PWR_CSTOP, SAI1_D3, LPTIM3_CH1, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6, OCTOSPI1_IO0, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin name (function after reset)(3)(4) Pin type VFQFPN68 UFBGA176+25 UFBGA169 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) Additional functions ADC12_INP13, ADC12_INN12 - - - H2 - K1 - - - M2 - G2 - VSS S - - - - 19 30 L1 36 M2 12 19 31 K2 37 M1 12 VSSA S - - - - - - - L2 - N2 - 20 - K1 - N1 - VREF- S - - - - - 20 31 M2 37 N1 - 21 32 L2 38 P1 - VREF+ S - - - - P10 21 32 M1 38 M1 13 22 33 L1 39 R1 13 VDDA S - - - - (5) TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS, SPI3_RDY, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, TIM2_ETR, EVENTOUT ADC12_INP0, ADC12_INN1, TAMP_IN2/TAMP_OUT1, WKUP1 (5) TIM2_CH2, TIM5_CH2, TIM15_CH1N, LPTIM1_IN1, OCTOSPI1_DQS, USART2_RTS/USART2_DE, UART4_RX, OCTOSPI1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_RE F_CLK, EVENTOUT ADC12_INP1, TAMP_IN5/TAMP_OUT4 K8 J7 22 23 33 34 K3 H5 39 40 P2 L3 14 15 23 24 34 35 J4 J5 40 41 N3 N2 14 15 PA0 PA1 I/O I/O FT_at FT_aht STM32H562xx and STM32H563xx P2 N9 LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions M8 24 35 L3 41 M3 16 25 36 L3 42 P2 16 PA2 I/O FT_hat (5) TIM2_CH3, TIM5_CH3, TIM15_CH1, LPTIM1_IN2, USART2_TX, SAI2_SCK_B, ETH_MDIO, EVENTOUT ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2 - - - J4 42 R2 - - - K3 43 F4 - PH2 I/O FT_h - LPTIM1_IN2, OCTOSPI1_IO4, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, EVENTOUT - H10 - - - - L4 - - - - - K4 - VDD S - - - - P8 - - - - M4 - - - - - L4 - VSS S - - - - - - - N2 43 P3 - - - N2 44 G4 - PH3 I/O FT_ah - OCTOSPI1_IO5, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, EVENTOUT - - - - N1 - R1 - - - N1 45 H4 - PH4 I/O FT_fa - I2C2_SCL, SPI5_RDY, SPI6_RDY, PSSI_D14, EVENTOUT - - - - L4 - P1 - - - M3 46 J4 - PH5 I/O FT_fa - I2C2_SDA, SPI5_NSS, SPI6_RDY, FMC_SDNWE, EVENTOUT - ADC12_INP15 Pin name (function after reset)(3)(4) Additional functions T10 25 36 K4 44 N5 17 26 37 N3 47 R2 17 PA3 I/O FT_ah - TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, TIM15_CH2, SPI2_NSS/I2S2_WS, SAI1_SD_B, USART2_RX, ETH_MII_COL, EVENTOUT - 26 37 M3 45 M7 18 27 38 M4 48 M8 18 VSS S - - - - R1 27 38 N3 46 M6 19 28 39 N4 49 N8 19 VDD S - - - - STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 81/270 82/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) DS14258 Rev 5 L7 H6 M6 29 30 31 - 40 41 42 - M4 J5 N4 K5 L5 47 48 49 50 51 M5 R3 P5 R4 N4 20 21 22 23 24 29 30 31 32 33 40 41 42 43 44 L4 K4 M5 K5 N5 50 51 52 53 54 N4 P4 P3 R3 N5 20 21 22 23 24 PA4 PA5 PA6 PA7 PC4 I/O I/O I/O I/O I/O I/O structure Pin type VFQFPN68 UFBGA176+25 LQFP176 UFBGA169 LQFP144 LQFP100 LQFP64 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS 39 TT_a TT_ah FT_ah FT_ah FT_a Alternate functions Additional functions - TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, DCMI_HSYNC/PSSI_DE, EVENTOUT ADC12_INP18, DAC1_OUT1 - TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, ETH_MII_TX_EN/ETH_RMII_TX_ EN, PSSI_D14, TIM2_ETR, EVENTOUT ADC12_INP19, ADC12_INN18, DAC1_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3, USART11_TX, SPI6_MISO, TIM13_CH1, DCMI_PIXCLK/PSSI_PDCK, EVENTOUT ADC12_INP3 - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, USART11_RX, SPI6_MOSI, TIM14_CH1, OCTOSPI1_IO2, ETH_MII_RX_DV/ETH_RMII_CRS _DV, FMC_SDNWE, FMC_NWE, EVENTOUT ADC12_INP7, ADC12_INN3 - TIM2_CH4, SAI1_CK1, LPTIM2_ETR, I2S1_MCK, USART3_RX, ETH_MII_RXD0/ETH_RMII_RXD0 , FMC_SDNE0, EVENTOUT ADC12_INP4 STM32H562xx and STM32H563xx K6 28 Pin name (function after reset)(3)(4) Notes R9 LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) DS14258 Rev 5 - M5 52 P4 25 34 45 H6 55 P5 25 PC5 I/O FT_ah - T8 - - - - M8 - - - - - - - VDD S - - - - ADC12_INP9, ADC12_INN5 LQFP176 - LQFP144 N7 TIM1_CH4N, SAI1_D3, PSSI_D15, SAI1_FS_A, UART12_RTS/UART12_DE, OCTOSPI1_DQS, ETH_MII_RXD1/ETH_RMII_RXD1 , FMC_SDCKE0, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin name (function after reset)(3)(4) Pin type VFQFPN68 UFBGA176+25 UFBGA169 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) Additional functions ADC12_INP8, ADC12_INN4 R7 32 43 N5 53 R5 26 35 46 L5 56 R5 26 PB0 I/O FT_ah - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, OCTOSPI1_IO1, USART11_CK, UART4_CTS, ETH_MII_RXD2, LPTIM3_CH1, EVENTOUT P6 33 44 H6 54 N6 27 36 47 K6 57 R4 27 PB1 I/O FT_ah - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OCTOSPI1_IO0, ETH_MII_RXD3, LPTIM3_CH2, EVENTOUT ADC12_INP5 - RTC_OUT2, SAI1_D1, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, OCTOSPI1_CLK, OCTOSPI1_DQS, SDMMC1_CMD, LPTIM5_ETR, EVENTOUT LSCO ADC1_INP2 ADC1_INP6, ADC1_INN2 L5 34 45 N6 55 P6 28 37 48 L6 58 M6 28 PB2 I/O FT_ah 83/270 - - 46 J6 56 R6 - - 49 J6 59 R6 - PF11 I/O FT_ah - SPI5_MOSI, OCTOSPI1_NCLK, SAI2_SD_B, FMC_NRAS, DCMI_D12/PSSI_D12, LPTIM6_CH1, EVENTOUT - - 47 K6 57 N7 - - 50 N6 60 P6 - PF12 I/O FT_ah - FMC_A6, LPTIM6_CH2, EVENTOUT STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 84/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes Alternate functions - - 48 M7 58 - - - 51 M7 61 - - VSS S - - - - - - 49 N7 59 - - - 52 N7 62 N9 - VDD S - - - - - - 50 H7 60 P7 - - 53 H7 63 N6 - PF13 I/O FT_ah - I2C4_SMBA, FMC_A7, LPTIM6_IN1, EVENTOUT ADC2_INP2 - - 51 L6 61 R7 - - 54 M6 64 R7 - PF14 I/O FT_fah - FMC_A8, LPTIM6_IN2, EVENTOUT ADC2_INP6, ADC2_INN2 - - 52 J7 62 N8 - - 55 J7 65 P7 - PF15 I/O FT_fh - I2C4_SDA, I3C1_SDA, FMC_A9, EVENTOUT - - - 53 M6 63 R8 - - 56 L7 66 N7 - PG0 I/O FT_h - UART9_RX, FMC_A10, LPTIM4_IN1, EVENTOUT - - - 54 K7 64 P8 - - 57 K7 67 M7 - PG1 I/O FT_h - SPI2_MOSI/I2S2_SDO, UART9_TX, FMC_A11, EVENTOUT - - TIM1_ETR, UART12_RTS/UART12_DE, UART7_RX, OCTOSPI1_IO4, FMC_D4/FMC_AD4, EVENTOUT - - TIM1_CH1N, UART12_CTS/UART12_NSS, UART7_TX, OCTOSPI1_IO5, FMC_D5/FMC_AD5, EVENTOUT - - T6 N5 35 36 55 56 L7 J8 65 66 R9 P9 - - 38 39 58 59 N8 G7 68 69 R8 P8 - - Pin name (function after reset)(3)(4) PE7 PE8 I/O I/O FT_ah FT_ah Additional functions R5 37 57 N8 67 N9 - 40 60 L8 70 P9 - PE9 I/O FT_ah - TIM1_CH1, UART12_RX, UART7_RTS/UART7_DE, OCTOSPI1_IO6, FMC_D6/FMC_AD6, EVENTOUT - - 58 - 68 - - - 61 - 71 - - VSS S - - - - - - 59 - 69 - - - 62 - 72 - - VDD S - - - - STM32H562xx and STM32H563xx LQFP100 SMPS DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions M4 38 60 L8 70 R10 - 41 63 H8 73 R9 - PE10 I/O FT_ah - TIM1_CH2N, UART12_TX, UART7_CTS, OCTOSPI1_IO7, FMC_D7/FMC_AD7, EVENTOUT - - 39 61 M8 71 P10 - 42 64 M8 74 P10 - PE11 I/O FT_ah - TIM1_CH2, SPI1_RDY, SPI4_NSS, OCTOSPI1_NCS, SAI2_SD_B, FMC_D8/FMC_AD8, EVENTOUT - - 40 62 M9 72 R11 - 43 65 K8 75 R10 - PE12 I/O FT_h - TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_AD9, EVENTOUT - - TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_AD10, EVENTOUT - - TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_AD11, EVENTOUT - - TIM1_BKIN, TIM1_CH4N, USART10_CK, FMC_D12/FMC_AD12, EVENTOUT - - TIM2_CH3, LPTIM3_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS, ETH_MII_RX_ER, EVENTOUT - - - - P4 41 42 43 44 63 64 65 66 K8 J9 L9 K9 73 74 75 76 P11 N10 N11 M10 - - - 29 44 45 46 47 66 67 68 69 L9 J8 N9 K9 76 77 78 79 N11 P11 R11 R12 - - - 29 Pin name (function after reset)(3)(4) PE13 PE14 PE15 PB10 I/O I/O I/O I/O FT_h FT_h FT_h FT_f Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 85/270 86/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) DS14258 Rev 5 L10 77 N12 - - - M9 80 R13 30 PB11 I/O FT_f - T4 46 68 N9 78 R12 - - - - - - - VLXSMPS S - - - - R3 47 69 N10 79 R13 - - - - - - - VDDSMPS S - - - - N3 48 70 M10 80 P12 - - - - - - - VSSSMPS S - - - - T2 49 71 N11 81 R14 30 48 70 N10 81 M10 31 VCAP S - - - - - 50 72 M11 82 M9 31 49 71 M12 82 M9 32 VSS S - - - - - 51 73 N12 83 M11 32 50 72 N11 83 N10 33 VDD S - - - - - LQFP176 67 LQFP144 45 LQFP100 - TIM2_CH4, LPTIM2_ETR, I2C2_SDA, SPI2_RDY, SPI4_RDY, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_ EN, FMC_NBL1, EVENTOUT LQFP64 Alternate functions Additional functions - - - - N13 84 P13 - - - K10 84 M11 - PH6 I/O FT - TIM1_CH3N, TIM12_CH1, TIM8_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8/PSSI_D8, EVENTOUT - - - L11 85 P14 - - - L10 85 N12 - PH7 I/O FT_f - TIM1_CH3, TIM8_CH1N, I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9/PSSI_D9, EVENTOUT - - TIM1_CH2N, TIM5_ETR, TIM8_CH2, I2C3_SDA, SPI5_MOSI, DCMI_HSYNC/PSSI_DE, EVENTOUT - - - - M12 - N13 - - - M10 86 M12 - PH8 I/O FT_fh STM32H562xx and STM32H563xx Notes I/O structure Pin name (function after reset)(3)(4) Pin type VFQFPN68 UFBGA176+25 UFBGA169 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - - M13 86 M12 - - - - 87 M13 - PH9 I/O FT_h - TIM1_CH2, TIM12_CH2, TIM8_CH2N, I2C3_SMBA, SPI5_NSS, DCMI_D0/PSSI_D0, EVENTOUT - - - - K10 87 N14 - - - M11 88 L13 - PH10 I/O FT_h - TIM1_CH1N, TIM5_CH1, TIM8_CH3, I2C4_SMBA, SPI5_RDY, DCMI_D1/PSSI_D1, EVENTOUT - - - - L13 88 P15 - - - N12 89 L12 - PH11 I/O FT_fh - TIM1_CH1, TIM5_CH2, TIM8_CH3N, I2C4_SCL, I3C1_SCL, DCMI_D2/PSSI_D2, EVENTOUT - - - - L12 89 M13 - - - N13 90 K12 - PH12 I/O FT_fh - TIM1_BKIN, TIM5_CH3, TIM8_BKIN, I2C4_SDA, I3C1_SDA, TIM8_CH4N, DCMI_D3/PSSI_D3, EVENTOUT - - - - - 90 H12 - - - - - - - VSS S - - - - - - - - 91 J12 - - - L13 91 J12 - VDD S - - - - - TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, ETH_MII_TXD0/ETH_RMII_TXD0, UART5_RX, EVENTOUT - L3 - - K11 92 L12 33 51 73 K11 92 P12 34 Pin name (function after reset)(3)(4) PB12 I/O FT_fh Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 87/270 88/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) DS14258 Rev 5 N1 52 53 75 K12 J10 93 94 R15 N15 34 35 52 53 74 75 L11 M13 93 94 P13 R14 35 36 PB13 PB14 I/O I/O I/O structure Pin type VFQFPN68 UFBGA176+25 LQFP176 UFBGA169 LQFP144 LQFP100 LQFP64 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS 74 Pin name (function after reset)(3)(4) FT_c FT_c Alternate functions Additional functions (6) TIM1_CH1N, LPTIM3_IN1, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/USART3_NSS, FDCAN2_TX, SDMMC1_D0, UART5_TX, EVENTOUT UCPD1_CC1 (6) TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SDMMC2_D0, LPTIM3_ETR, EVENTOUT UCPD1_CC2 PVD_IN L1 54 76 H10 95 M14 36 54 76 J10 95 R15 37 PB15 I/O FT_h - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, USART11_CTS/USART11_NSS, UART4_CTS, SDMMC2_D1, OCTOSPI1_CLK, ETH_MII_TXD1/ETH_RMII_TXD1, DCMI_D2/PSSI_D2, UART5_RX, EVENTOUT - 55 77 J11 96 M15 - 55 77 L12 96 P15 - PD8 I/O FT_h - USART3_TX, FMC_D13/FMC_AD13, EVENTOUT - - - - - - G12 - - - - - - - VSS S - - - - - 56 78 H9 97 L13 - 56 78 J9 97 P14 - PD9 I/O FT_h - USART3_RX, FDCAN2_RX, FMC_D14/FMC_AD14, EVENTOUT - STM32H562xx and STM32H563xx Notes M2 LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 79 K13 98 K12 - 57 79 J11 98 N15 - - 58 80 H8 99 L14 - 58 80 H10 99 N14 38 PD10 I/O PD11 I/O Notes LQFP144 SMPS 57 I/O structure LQFP100 SMPS - Pin name (function after reset)(3)(4) Pin type WLCSP80 SMPS Pin number(1)(2) Alternate functions Additional functions FT_h - LPTIM2_CH2, USART3_CK, FMC_D15/FMC_AD15, EVENTOUT - - SAI1_CK1, LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, UART4_RX, OCTOSPI1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I3C1_SCL, SAI1_D1, USART3_RTS/USART3_DE, UART4_TX, OCTOSPI1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, DCMI_D12/PSSI_D12, EVENTOUT - - FT_h DS14258 Rev 5 - 59 81 H11 100 K14 - 59 81 K12 100 N13 39 PD12 I/O FT_fh 89/270 - 60 82 G8 101 L15 - 60 82 K13 101 M15 - PD13 I/O FT_fh - LPTIM1_CH1, TIM4_CH2, LPTIM2_CH1, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3, SAI2_SCK_A, UART9_RTS/UART9_DE, FMC_A18, DCMI_D13/PSSI_D13, LPTIM4_IN1, EVENTOUT - - 83 J12 102 - - - 83 H12 102 H12 - VSS S - - - - - - 84 J13 103 - - - 84 H13 103 J13 - VDD S - - - - K2 61 85 H12 104 K13 - 61 85 H11 104 M14 - PD14 I/O FT_h - TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/FMC_AD0, EVENTOUT - STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 90/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes Alternate functions J1 62 86 G10 105 J13 - 62 86 H9 105 L14 - PD15 I/O FT_h - TIM4_CH4, UART8_RTS/UART8_DE, UART9_TX, FMC_D1/FMC_AD1, EVENTOUT - - - - - - - - - - - - - - VDD S - - - - - - - - - - - - - - - - - VSS S - - - - - - 87 H13 106 K15 - - 87 J12 106 L15 - PG2 I/O FT_h - TIM8_BKIN, UART12_RX, FMC_A12, LPTIM6_ETR, EVENTOUT - - - 88 G9 107 H14 - - 88 G9 107 K15 - PG3 I/O FT_h - TIM8_BKIN2, UART12_TX, FMC_A13, LPTIM5_ETR, EVENTOUT - - - 89 G11 108 J15 - - 89 J13 108 K14 - PG4 I/O FT_h - TIM1_BKIN2, FMC_A14/FMC_BA0, LPTIM4_ETR, EVENTOUT - - - 90 F8 109 H15 - - 90 G10 109 K13 - PG5 I/O FT_h - TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT - - TIM17_BKIN, I3C1_SDA, I2C4_SDA, SPI1_RDY, OCTOSPI1_NCS, UCPD1_FRSTX, FMC_NE3, DCMI_D12/PSSI_D12, EVENTOUT - - SAI1_CK2, I3C1_SCL, I2C4_SCL, SAI1_MCLK_A, USART6_CK, UCPD1_FRSTX, FMC_INT, DCMI_D13/PSSI_D13, EVENTOUT - - - - - 91 92 G12 F9 110 111 J14 H13 - - - - 91 92 G11 G8 110 111 J15 J14 - - Pin name (function after reset)(3)(4) PG6 PG7 I/O I/O FT_fh FT_fh Additional functions STM32H562xx and STM32H563xx LQFP100 SMPS DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - 93 G13 112 G15 - - 93 F11 112 H14 - PG8 I/O FT_h - TIM8_ETR, SPI6_NSS, USART6_RTS/USART6_DE, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT - - - 94 - 113 - - - 94 - 113 - - VSS S - - - - - - 95 - 114 - - - 95 - 114 - - VDD S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0/PSSI_D0, EVENTOUT - - TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1/PSSI_D1, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE, FMC_NE2/FMC_NCE, FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2/PSSI_D2, EVENTOUT - - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3/PSSI_D3, EVENTOUT UCPD1_DB2 J3 K4 J5 F2 63 64 65 66 96 97 98 99 F10 F11 E9 F12 115 116 117 118 G14 G13 F14 F13 37 38 39 40 63 64 65 66 96 97 98 99 F9 F10 G12 G13 115 116 117 118 H15 G15 G14 F14 40 41 42 43 Pin name (function after reset)(3)(4) PC6 PC7 PC8 PC9 I/O I/O I/O I/O FT_h FT_h FT_h FT_fh Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 91/270 92/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes Alternate functions - - - - - - - - - - - G12 - VSS S - - - - - - - - - - - - - - - G13 - VDD S - - - - - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI1_RDY, USART1_CK, USB_SOF, UART7_RX, FMC_NOE, DCMI_D3/PSSI_D3, EVENTOUT - - TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, ETH_MII_TX_ER, FMC_NWE, DCMI_D0/PSSI_D0, EVENTOUT UCPD1_DB1 - TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1/PSSI_D1, EVENTOUT - - TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, USB_DM, EVENTOUT - - TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX, USB_DP, EVENTOUT - G3 DS14258 Rev 5 H4 G5 E1 C1 67 68 69 70 71 100 101 102 103 104 E10 F13 E11 C13 B13 119 120 121 122 123 F15 E15 E14 D15 C15 41 42 43 44 45 67 68 69 70 71 100 101 102 103 104 F12 E11 E10 F13 E13 119 120 121 122 123 F15 E15 D15 C15 B15 44 45 46 47 48 Pin name (function after reset)(3)(4) PA8 PA9 PA10 PA11 PA12 I/O I/O I/O I/O I/O FT_fh FT_d FT_h FT_u FT_u Additional functions STM32H562xx and STM32H563xx WLCSP80 SMPS Pin number(1)(2) LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes 93/270 LQFP100 SMPS DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions F4 72 105 D12 124 E13 46 72 105 E12 124 A15 49 PA13 (JTMS/SWDIO) I/O FT (7) JTMS/SWDIO, EVENTOUT - - 74 107 E12 126 D14 47 74 107 C12 126 F12 50 VSS S - - - - - 75 108 D13 127 E12 48 75 108 C13 127 F13 51 VDD S - - - - B2 73 106 E13 125 F12 - 73 106 D13 125 H13 - VDDUSB S - - - - - - - C12 128 B15 - - - D12 128 E12 - PH13 I/O FT_h - LPTIM1_IN2, TIM8_CH1N, UART8_TX, UART4_TX, FDCAN1_TX, DCMI_D3/PSSI_D3, EVENTOUT - - - - D11 129 D13 - - - D10 129 E13 - PH14 I/O FT_h - TIM8_CH2N, UART4_RX, FDCAN1_RX, DCMI_D4/PSSI_D4, EVENTOUT - - - - A13 130 C14 - - - D11 130 D13 - PH15 I/O FT_h - TIM8_CH3N, DCMI_D11/PSSI_D11, EVENTOUT - - - - B12 131 - - - - B13 131 E14 - PI0 I/O FT_h - TIM5_CH4, SPI2_NSS/I2S2_WS, DCMI_D13/PSSI_D13, EVENTOUT - - - - C11 132 A15 - - - B12 132 D14 - PI1 I/O FT_h - TIM8_BKIN2, SPI2_SCK/I2S2_CK, DCMI_D8/PSSI_D8, EVENTOUT - - - - D10 133 B14 - - - A13 133 C14 - PI2 I/O FT_h - TIM8_CH4, SPI2_MISO/I2S2_SDI, DCMI_D9/PSSI_D9, EVENTOUT - - - - A12 134 A14 - - - C11 134 C13 - PI3 I/O FT_h - TIM8_ETR, SPI2_MOSI/I2S2_SDO, DCMI_D10/PSSI_D10, EVENTOUT - Pin name (function after reset)(3)(4) Additional functions STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 94/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes Alternate functions - - - B8 135 D9 - - - B10 135 D9 - VSS S - - - - - - - A8 136 D8 - - - A10 136 C9 - VDD S - - - - E3 76 109 C10 137 B13 49 76 109 A12 137 A14 52 PA14 (JTCK/SWCLK) I/O FT (7) JTCK/SWCLK, EVENTOUT - (7) JTDI, TIM2_CH1, LPTIM3_IN2, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, UART7_TX, FMC_NBL1, DCMI_D11/PSSI_D11, TIM2_ETR, EVENTOUT - - LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, ETH_MII_TXD0/ETH_RMII_TXD0, SDMMC1_D2, DCMI_D8/PSSI_D8, EVENTOUT - - LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4, EVENTOUT - - TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9, EVENTOUT - D4 C3 E5 F6 77 78 79 80 110 111 112 113 B10 A10 A9 D9 138 139 140 141 C13 D12 C12 C11 50 51 52 53 77 78 79 80 110 111 112 113 B11 C10 A11 B9 138 139 140 141 A13 B14 B13 A12 53 54 55 56 Pin name (function after reset)(3)(4) PA15(JTDI) PC10 PC11 PC12 I/O I/O I/O I/O FT FT_h FT_h FT_h Additional functions STM32H562xx and STM32H563xx LQFP100 SMPS DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - - B11 - D11 - - - - - - - VSS S - - - - - - - A11 - D10 - - - - - - - VDD S - - - - A3 81 114 C9 142 B12 - 81 114 D9 142 B12 - PD0 I/O FT_h - TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS, FMC_D2/FMC_AD2, EVENTOUT - B4 82 115 B9 143 A13 - 82 115 E9 143 C12 - PD1 I/O FT_h - UART4_TX, FDCAN1_TX, FMC_D3/FMC_AD3, EVENTOUT - WKUP7 Pin name (function after reset)(3)(4) Additional functions A5 83 116 E8 144 C10 54 83 116 C9 144 D12 - PD2 I/O FT_h - TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11, LPTIM4_ETR, EVENTOUT - 84 117 C8 145 A12 - 84 117 A9 145 D11 - PD3 I/O FT_h - SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK, DCMI_D5/PSSI_D5, EVENTOUT WKUP8 - 85 118 D8 146 B11 - 85 118 F8 146 D10 - PD4 I/O FT_h - USART2_RTS/USART2_DE, OCTOSPI1_IO4, FMC_NOE, EVENTOUT - - 86 119 A7 147 A11 - 86 119 D8 147 C11 - PD5 I/O FT_h - TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5, FMC_NWE, EVENTOUT - - - 120 - 148 - - - 120 B7 148 D8 - VSS S - - - - - - 121 A6 149 D7 - - 121 A7 149 C8 - VDDIO2 S - - - - STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 95/270 96/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 87 F7 150 B10 - 87 122 E8 150 B11 - PD6 I/O I/O structure Pin type VFQFPN68 UFBGA176+25 LQFP176 UFBGA169 LQFP144 LQFP100 LQFP64 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS 122 Pin name (function after reset)(3)(4) FT_sh DS14258 Rev 5 Notes - LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) Alternate functions Additional functions - SAI1_D1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, OCTOSPI1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10, EVENTOUT - - - 88 123 B7 151 A10 - 88 123 B8 151 A11 - PD7 I/O FT_sh - SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD, FMC_NE1/FMC_NCE, LPTIM4_OUT, EVENTOUT - - - - - D6 - - - - - - - VSS S - - - - - - 124 E7 152 B9 - - 124 F7 152 C10 - PG9 I/O FT_sh - - - 125 C7 153 A9 - - 125 A8 153 B10 - PG10 I/O FT_sh - SPI1_NSS/I2S1_WS, SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2, EVENTOUT - - LPTIM1_IN2, SPI1_SCK/I2S1_CK, USART10_RX, USART11_RTS/USART11_DE, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_TX_ EN, DCMI_D3/PSSI_D3, EVENTOUT - - - - - 154 C9 - - 126 E7 154 B9 - PG11 I/O FT_sh STM32H562xx and STM32H563xx - SPI1_MISO/I2S1_SDI, USART6_RX, OCTOSPI1_IO6, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC/PSSI_RDY, EVENTOUT DS14258 Rev 5 - - - 127 D7 - 155 156 B8 C8 - - - - 127 128 C8 D7 155 156 B8 A8 - - PG12 PG13 I/O I/O I/O structure Pin type VFQFPN68 UFBGA176+25 LQFP176 UFBGA169 LQFP144 LQFP100 LQFP64 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS 126 Pin name (function after reset)(3)(4) FT_sh FT_sh Notes - LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) Alternate functions Additional functions - LPTIM1_IN1, PSSI_D15, SPI6_MISO, USART10_TX, USART6_RTS/USART6_DE, SDMMC2_D3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_NE4, DCMI_D11/PSSI_D11, LPTIM5_CH1, EVENTOUT - - TRACED0, LPTIM1_CH1, SPI6_SCK, USART10_CTS/USART10_NSS, USART6_CTS/USART6_NSS, SDMMC2_D6, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_A24, LPTIM5_CH2, EVENTOUT - - - - 128 - 157 A8 - - 129 C7 157 A7 - PG14 I/O FT_sh - TRACED1, LPTIM1_ETR, LPTIM1_CH2, SPI6_MOSI, USART10_RTS/USART10_DE, USART6_TX, OCTOSPI1_IO7, SDMMC2_D7, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25, LPTIM5_IN1, EVENTOUT - - 129 B4 158 - - - 130 - 158 D7 - VSS S - - - - - - 130 A3 159 - - - 131 - 159 C7 - VDD S - - - - - SPI4_RDY, USART10_CK, USART6_CTS/USART6_NSS, FMC_NCAS, DCMI_D13/PSSI_D13, EVENTOUT - - - 131 B6 160 A7 - - 132 B6 160 B7 - PG15 I/O FT_h STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 97/270 98/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) DS14258 Rev 5 B6 E7 90 91 92 133 134 135 F6 A5 E6 C6 161 162 163 164 B7 C7 A6 B6 55 56 57 58 89 90 91 92 133 134 135 136 E6 A6 C6 A5 161 162 163 164 A10 A9 A6 B6 57 58 59 60 PB3(JTDO/TRA CESWO) PB4(NJTRST) PB5 PB6 I/O I/O I/O I/O I/O structure Pin type VFQFPN68 UFBGA176+25 LQFP176 UFBGA169 LQFP144 LQFP100 LQFP64 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS 132 FT_fh FT_h FT_h FT_f Alternate functions Additional functions - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, UART12_CTS/UART12_NSS, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, LPTIM6_ETR, EVENTOUT - - NJTRST, TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX, DCMI_D7/PSSI_D7, EVENTOUT - - TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10/PSSI_D10, UART5_RX, EVENTOUT - - TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, FMC_SDNE1, DCMI_D5/PSSI_D5, UART5_TX, EVENTOUT - STM32H562xx and STM32H563xx D6 89 Pin name (function after reset)(3)(4) Notes C5 LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) DS14258 Rev 5 136 D6 165 C6 59 93 137 D6 165 B5 61 PB7 I/O FT_fa - D8 94 137 B5 166 A5 60 94 138 B5 166 D6 62 BOOT0 I B - - - - TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6/PSSI_D6, EVENTOUT - - TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, SDMMC1_D5, DCMI_D7/PSSI_D7, EVENTOUT - - LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, LPTIM2_ETR, SPI3_RDY, UART8_RX, FDCAN1_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2/PSSI_D2, EVENTOUT - E9 - - 95 96 97 138 139 140 F5 E5 D5 167 168 169 B5 A4 C5 61 - - 95 96 97 139 140 141 E5 A4 C5 LQFP176 93 LQFP144 C7 TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, FMC_NL, DCMI_VSYNC/PSSI_RDY, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin name (function after reset)(3)(4) Pin type VFQFPN68 UFBGA176+25 UFBGA169 UFBGA176+25 SMPS LQFP176 SMPS UFBGA169 SMPS LQFP144 SMPS LQFP100 SMPS WLCSP80 SMPS Pin number(1)(2) 167 168 169 A5 B4 A4 63 64 65 PB8 PB9 PE0 I/O I/O I/O FT_fhs FT_fhs FT_h Additional functions WKUP5 STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 99/270 100/270 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes - 141 C5 170 B4 - - - D5 170 A3 - PE1 I/O FT_h - LPTIM1_IN2, UART8_TX, FDCAN1_TX, FMC_NBL1, DCMI_D3/PSSI_D3, EVENTOUT - 98 142 A4 171 A3 62 98 142 B4 171 C6 66 VCAP S - - - - 99 143 - - - 63 99 143 B3 - - 67 VSS S - - - - - 100 144 - 172 - 64 100 144 A3 172 - 68 VDD S - - - - - - - C4 173 B3 - - - C4 173 D4 - PI4 I/O FT_h - TIM8_BKIN, SPI2_RDY, SAI2_MCLK_A, DCMI_D5/PSSI_D5, EVENTOUT - - - - B3 174 A2 - - - - 174 C4 - PI5 I/O FT_h - TIM8_CH1, SAI2_SCK_A, DCMI_VSYNC/PSSI_RDY, EVENTOUT - - - - A2 175 C4 - - - C3 175 C3 - PI6 I/O FT_h - TIM8_CH2, SAI2_SD_A, DCMI_D6/PSSI_D6, EVENTOUT - - - - A1 176 A1 - - - A2 176 C2 - PI7 I/O FT_h - TIM8_CH3, SAI2_FS_A, DCMI_D7/PSSI_D7, EVENTOUT - - - - - - F6 - - - - - F6 - VSS S - - - - - - - - - F7 - - - - - F7 - VSS S - - - - - - - - - F8 - - - - - F8 - VSS S - - - - - - - - - F9 - - - - - F9 - VSS S - - - - - - - - - F10 - - - - - F10 - VSS S - - - - - - - - - G6 - - - - - G6 - VSS S - - - - - - - - - G7 - - - - - G7 - VSS S - - - - - - - - - G8 - - - - - G8 - VSS S - - - - WLCSP80 SMPS Alternate functions A9 - Pin name (function after reset)(3)(4) Additional functions STM32H562xx and STM32H563xx LQFP144 SMPS DS14258 Rev 5 LQFP100 SMPS Pin number(1)(2) LQFP100 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP176 SMPS UFBGA176+25 SMPS LQFP64 LQFP100 LQFP144 UFBGA169 LQFP176 UFBGA176+25 VFQFPN68 Pin type I/O structure Notes DS14258 Rev 5 WLCSP80 SMPS Pin number(1)(2) Alternate functions - - - - - G9 - - - - - G9 - VSS S - - - - - - - - - G10 - - - - - G10 - VSS S - - - - - - - - - H6 - - - - - H6 - VSS S - - - - - - - - - H7 - - - - - H7 - VSS S - - - - - - - - - H8 - - - - - H8 - VSS S - - - - - - - - - H9 - - - - - H9 - VSS S - - - - - - - - - H10 - - - - - H10 - VSS S - - - - - - - - - J6 - - - - - J6 - VSS S - - - - - - - - - J7 - - - - - J7 - VSS S - - - - - - - - - J8 - - - - - J8 - VSS S - - - - - - - - - J9 - - - - - J9 - VSS S - - - - - - - - - J10 - - - - - J10 - VSS S - - - - - - - - - K6 - - - - - K6 - VSS S - - - - - - - - K7 - - - - - K7 - VSS S - - - - - - - - - K8 - - - - - K8 - VSS S - - - - - - - - - K9 - - - - - K9 - VSS S - - - - - - - - - K10 - - - - - K10 - VSS S - - - - - Pin name (function after reset)(3)(4) Additional functions 1. The devices with SMPS correspond to commercial code STM32H563xIxxQ. 101/270 2. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer (VREFBUF) is not available and must be kept disabled. 3. PC13, PC14 and PC15 are supplied through the power switch (by VSW). This switch sinks a limited amount of current, hence the use of PC13 to PC15 GPIOs in output mode is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED). STM32H562xx and STM32H563xx Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) 102/270 4. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends upon the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual. 5. As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and VBAT mode. 6. For the output timing characteristics refer to Table 67. 7. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated too. DS14258 Rev 5 STM32H562xx and STM32H563xx Alternate functions Table 15. Alternate functions AF0 to AF7(1) AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN SPI6_NSS SPI3_RDY USART2_CTS/ USART2_NSS PA1 - TIM2_CH2 TIM5_CH2 - TIM15_CH1N LPTIM1_IN1 OCTOSPI1_DQS USART2_RTS/ USART2_DE PA2 - TIM2_CH3 TIM5_CH3 - TIM15_CH1 LPTIM1_IN2 - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 OCTOSPI1_CLK TIM15_CH2 SPI2_NSS/I2S2_WS SAI1_SD_B USART2_RX PA4 - - TIM5_ETR LPTIM2_CH1 - SPI1_NSS/I2S1_WS SPI3_NSS/ I2S3_WS USART2_CK PA5 - TIM2_CH1 - TIM8_CH1N - SPI1_SCK/I2S1_CK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO/I2S1_SDI OCTOSPI1_IO3 USART11_TX PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I2S1_SDO - USART11_RX PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL SPI1_RDY - USART1_CK PA9 - TIM1_CH2 - LPUART1_TX I2C3_SMBA SPI2_SCK/I2S2_CK - USART1_TX PA10 - TIM1_CH3 - LPUART1_RX LPTIM2_IN2 - UCPD1_FRSTX USART1_RX PA11 - TIM1_CH4 - LPUART1_CTS - SPI2_NSS/I2S2_WS UART4_RX USART1_CTS/ USART1_NSS PA12 - TIM1_ETR - LPUART1_RTS/ LPUART1_DE - SPI2_SCK/I2S2_CK UART4_TX USART1_RTS/ USART1_DE PA13 JTMS/SWDIO - - - - - - - PA14 JTCK/SWCLK - - - - - - - PA15 JTDI TIM2_CH1 LPTIM3_IN2 - HDMI_CEC SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_ WS SPI6_NSS Port DS14258 Rev 5 A AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx 4.3 103/270 104/270 Table 15. Alternate functions AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - OCTOSPI1_IO1 USART11_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - OCTOSPI1_IO0 - PB2 RTC_OUT2 - SAI1_D1 TIM8_CH4N SPI1_RDY LPTIM1_CH1 SAI1_SD_A SPI3_MOSI/ I2S3_SDO PB3 JTDO/TRACE SWO TIM2_CH2 - - I2C2_SDA SPI1_SCK/I2S1_CK SPI3_SCK/I2S3_ CK UART12_CTS/ UART12_NSS PB4 NJTRST TIM16_BKIN TIM3_CH1 OCTOSPI1_CLK LPTIM1_CH2 SPI1_MISO/I2S1_SDI SPI3_MISO/I2S3 _SDI SPI2_NSS/ I2S2_WS PB5 - TIM17_BKIN TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA SPI1_MOSI/I2S1_SDO I2C4_SMBA SPI3_MOSI/ I2S3_SDO PB6 - TIM16_CH1N TIM4_CH1 I3C1_SCL I2C1_SCL HDMI_CEC I2C4_SCL USART1_TX PB7 - TIM17_CH1N TIM4_CH2 I3C1_SDA I2C1_SDA - I2C4_SDA USART1_RX PB8 - TIM16_CH1 TIM4_CH3 I3C1_SCL I2C1_SCL SPI4_RDY I2C4_SCL SDMMC1_CKIN PB9 - TIM17_CH1 TIM4_CH4 I3C1_SDA I2C1_SDA SPI2_NSS/I2S2_WS I2C4_SDA SDMMC1_CDIR PB10 - TIM2_CH3 LPTIM3_CH1 LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK - USART3_TX PB11 - TIM2_CH4 - LPTIM2_ETR I2C2_SDA SPI2_RDY SPI4_RDY USART3_RX PB12 - TIM1_BKIN - OCTOSPI1_NCLK I2C2_SDA SPI2_NSS/I2S2_WS UCPD1_FRSTX USART3_CK PB13 - TIM1_CH1N LPTIM3_IN1 LPTIM2_CH1 I2C2_SMBA SPI2_SCK/I2S2_CK - USART3_CTS/ USART3_NSS PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX SPI2_MISO/I2S2_SDI - USART3_RTS/ USART3_DE PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI2_MOSI/I2S2_SDO - USART11_CTS/ USART11_NSS Port DS14258 Rev 5 B AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PC0 - TIM16_BKIN - - - - SAI1_MCLK_A SPI2_RDY PC1 TRACED0 - SAI1_D1 - - SPI2_MOSI/I2S2_SDO SAI1_SD_A USART11_RTS/ USART11_DE PC2 PWR_CSLEEP TIM17_CH1 TIM4_CH4 - - SPI2_MISO/I2S2_SDI OCTOSPI1_IO5 - PC3 PWR_CSTOP - SAI1_D3 LPTIM3_CH1 - SPI2_MOSI/I2S2_SDO OCTOSPI1_IO6 - PC4 - TIM2_CH4 SAI1_CK1 LPTIM2_ETR - I2S1_MCK - USART3_RX PC5 - TIM1_CH4N SAI1_D3 - PSSI_D15 - SAI1_FS_A UART12_RTS/ UART12_DE PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK SAI1_SCK_A USART6_TX PC7 TRGIO - TIM3_CH2 TIM8_CH2 - - I2S3_MCK USART6_RX PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - USART6_CK PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA AUDIOCLK - - PC10 - - LPTIM3_ETR - - - SPI3_SCK/ I2S3_CK USART3_TX PC11 - - LPTIM3_IN1 - - - SPI3_MISO/ I2S3_SDI USART3_RX PC12 TRACED3 - TIM15_CH1 - - SPI6_SCK SPI3_MOSI/ I2S3_SDO USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port DS14258 Rev 5 C AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx Table 15. Alternate functions AF0 to AF7(1) (continued) 105/270 106/270 Table 15. Alternate functions AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PD0 - - - TIM8_CH4N - - - - PD1 - - - - - - - - PD2 TRACED2 - TIM3_ETR - TIM15_BKIN - - - PD3 - - - - - SPI2_SCK/I2S2_CK - USART2_CTS/ USART2_NSS PD4 - - - - - - - USART2_RTS/ USART2_DE PD5 - TIM1_CH4N - - - SPI2_RDY - USART2_TX PD6 - - SAI1_D1 - - SPI3_MOSI/I2S3_SDO SAI1_SD_A USART2_RX PD7 - - - - - SPI1_MOSI/I2S1_SDO - USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - LPTIM2_CH2 - - - USART3_CK PD11 - - SAI1_CK1 LPTIM2_IN2 I2C4_SMBA - - USART3_CTS/ USART3_NSS PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 I2C4_SCL I3C1_SCL SAI1_D1 USART3_RTS/ USART3_DE PD13 - LPTIM1_CH1 TIM4_CH2 LPTIM2_CH1 I2C4_SDA I3C1_SDA - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - Port DS14258 Rev 5 D AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PE0 - LPTIM1_ETR TIM4_ETR LPTIM2_CH2 LPTIM2_ETR - SPI3_RDY - PE1 - LPTIM1_IN2 - - - - - - PE2 TRACECLK LPTIM1_IN2 SAI1_CK1 - - SPI4_SCK SAI1_MCLK_A USART10_RX PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B USART10_TX PE4 TRACED1 - SAI1_D2 - TIM15_CH1N SPI4_NSS SAI1_FS_A - PE5 TRACED2 - SAI1_CK2 - TIM15_CH1 SPI4_MISO SAI1_SCK_A - PE6 TRACED3 TIM1_BKIN2 SAI1_D1 - TIM15_CH2 SPI4_MOSI SAI1_SD_A - PE7 - TIM1_ETR - - - - UART12_RTS/ UART12_DE UART7_RX PE8 - TIM1_CH1N - - - - UART12_CTS/ UART12_NSS UART7_TX PE9 - TIM1_CH1 - - - - UART12_RX UART7_RTS/ UART7_DE PE10 - TIM1_CH2N - - - - UART12_TX UART7_CTS PE11 - TIM1_CH2 - - SPI1_RDY SPI4_NSS OCTOSPI1_NCS - PE12 - TIM1_CH3N - - - SPI4_SCK - - PE13 - TIM1_CH3 - - - SPI4_MISO - - PE14 - TIM1_CH4 - - - SPI4_MOSI - - PE15 - TIM1_BKIN - TIM1_CH4N - - - USART10_CK Port DS14258 Rev 5 E AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx Table 15. Alternate functions AF0 to AF7(1) (continued) 107/270 108/270 Table 15. Alternate functions AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - PF2 - - LPTIM3_CH2 LPTIM3_IN2 I2C2_SMBA - UART12_TX USART11_CK PF3 - - LPTIM3_IN1 - - - - USART11_TX PF4 - - LPTIM3_ETR - - - - USART11_RX PF5 - - LPTIM3_CH1 - I2C4_SCL I3C1_SCL UART12_RX USART11_CTS/ USART11_NSS PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK_B UART7_TX PF8 - TIM16_CH1N - - - SPI5_MISO SAI1_SCK_B UART7_RTS/ UART7_DE PF9 - TIM17_CH1N - - - SPI5_MOSI SAI1_FS_B UART7_CTS PF10 - TIM16_BKIN SAI1_D3 - PSSI_D15 - - - PF11 - - - - - SPI5_MOSI - - PF12 - - - - - - - - PF13 - - - - I2C4_SMBA - - - PF14 - - - - - - - - PF15 - - - - I2C4_SDA I3C1_SDA - - Port DS14258 Rev 5 F AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PG0 - - - - - - - - PG1 - - - - - - - SPI2_MOSI/ I2S2_SDO PG2 - - - TIM8_BKIN - - - UART12_RX PG3 - - - TIM8_BKIN2 - - - UART12_TX PG4 - TIM1_BKIN2 - - - - - - PG5 - TIM1_ETR - - - - - - PG6 - TIM17_BKIN - I3C1_SDA I2C4_SDA SPI1_RDY - - PG7 - - SAI1_CK2 I3C1_SCL I2C4_SCL - SAI1_MCLK_A USART6_CK PG8 - - - TIM8_ETR - SPI6_NSS - USART6_RTS/ USART6_DE PG9 - - - - - SPI1_MISO/I2S1_SDI - USART6_RX PG10 - - - - - SPI1_NSS/I2S1_WS - - PG11 - LPTIM1_IN2 - - - SPI1_SCK/I2S1_CK USART10_RX USART11_RTS/ USART11_DE PG12 - LPTIM1_IN1 - - PSSI_D15 SPI6_MISO USART10_TX USART6_RTS/ USART6_DE PG13 TRACED0 LPTIM1_CH1 - - - SPI6_SCK USART10_CTS/ USART10_NSS USART6_CTS/ USART6_NSS PG14 TRACED1 LPTIM1_ETR - - LPTIM1_CH2 SPI6_MOSI USART10_RTS/ USART10_DE USART6_TX PG15 - - - - - SPI4_RDY USART10_CK USART6_CTS/ USART6_NSS Port DS14258 Rev 5 G AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx Table 15. Alternate functions AF0 to AF7(1) (continued) 109/270 110/270 Table 15. Alternate functions AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PH0 - - - - - - - - PH1 - - - - - - - - PH2 - LPTIM1_IN2 - - - - - - PH3 - - - - - - - - PH4 - - - - I2C2_SCL SPI5_RDY - SPI6_RDY PH5 - - - - I2C2_SDA SPI5_NSS - SPI6_RDY PH6 - TIM1_CH3N TIM12_CH1 TIM8_CH1 I2C2_SMBA SPI5_SCK - - PH7 - TIM1_CH3 - TIM8_CH1N I2C3_SCL SPI5_MISO - - PH8 - TIM1_CH2N TIM5_ETR TIM8_CH2 I2C3_SDA SPI5_MOSI - - PH9 - TIM1_CH2 TIM12_CH2 TIM8_CH2N I2C3_SMBA SPI5_NSS - - PH10 - TIM1_CH1N TIM5_CH1 TIM8_CH3 I2C4_SMBA SPI5_RDY - - PH11 - TIM1_CH1 TIM5_CH2 TIM8_CH3N I2C4_SCL I3C1_SCL - - PH12 - TIM1_BKIN TIM5_CH3 TIM8_BKIN I2C4_SDA I3C1_SDA - - PH13 - LPTIM1_IN2 - TIM8_CH1N - - - UART8_TX PH14 - - - TIM8_CH2N - - - - PH15 - - - TIM8_CH3N - - - - Port DS14258 Rev 5 H AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx AF0 AF1 AF2 AF3 AF4 AF5 SYS LPTIM1/ TIM1/2/16/17 LPTIM3/ PDM_SAI1/ TIM3/4/5/12/15 I3C1/LPTIM2/3/ LPUART1/ OCTOSPI/TIM1/8 CEC/DCMI/ I2C1/2/3/4/ LPTIM1/2/SPI1/ I2S1/TIM15/ USART1 CEC/I3C1/LPTIM1/ SPI1/I2S1/SPI2/I2S2/ SPI3/I2S3/SPI4/5/6 PI0 - - TIM5_CH4 - - SPI2_NSS/I2S2_WS - - PI1 - - - TIM8_BKIN2 - SPI2_SCK/I2S2_CK - - PI2 - - - TIM8_CH4 - SPI2_MISO/I2S2_SDI - - PI3 - - - TIM8_ETR - SPI2_MOSI/I2S2_SDO - - PI4 - - - TIM8_BKIN - - - SPI2_RDY PI5 - - - TIM8_CH1 - - - - PI6 - - - TIM8_CH2 - - - - PI7 - - - TIM8_CH3 - - - - PI8 - - - - - - - - PI9 - - - - - - - - PI10 - - - - - - - - PI11 - - - - - - - - Port I DS14258 Rev 5 1. Refer to the next table for AF8 to AF15. AF6 AF7 SDMMC1/SPI2/ I2C4/OCTOSPI/ SAI1/SPI3/I2S3/ I2S2/SPI3/I2S3/ SPI4/UART4/12/ SPI6/UART7/8/12 /USART1/2/3/6/ USART10/ 10/11 USB_PD STM32H562xx and STM32H563xx Table 15. Alternate functions AF0 to AF7(1) (continued) 111/270 112/270 Table 16. Alternate functions AF8 to AF15(1) AF8 Port AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS DS14258 Rev 5 UART4_TX SDMMC2_CMD SAI2_SD_B ETH_MII_CRS - - TIM2_ETR EVENTOUT PA1 UART4_RX OCTOSPI1_IO3 SAI2_MCLK_B ETH_MII_RX_CLK /ETH_RMII_REF_ CLK - - - EVENTOUT PA2 SAI2_SCK_B - - ETH_MDIO - - - EVENTOUT PA3 - - - ETH_MII_COL - - - EVENTOUT PA4 SPI6_NSS - - - - DCMI_HSYNC/ PSSI_DE - EVENTOUT PA5 SPI6_SCK - - ETH_MII_TX_EN/ ETH_RMII_TX_EN - PSSI_D14 TIM2_ETR EVENTOUT PA6 SPI6_MISO TIM13_CH1 - - - DCMI_PIXCLK/ PSSI_PDCK - EVENTOUT PA7 SPI6_MOSI TIM14_CH1 OCTOSPI1_IO2 ETH_MII_RX_DV/ ETH_RMII_CRS_ DV FMC_SDNWE FMC_NWE - EVENTOUT PA8 - - USB_SOF UART7_RX FMC_NOE DCMI_D3/PSSI_D3 - EVENTOUT PA9 - - - ETH_MII_TX_ER FMC_NWE DCMI_D0/PSSI_D0 - EVENTOUT PA10 - FDCAN2_TX - - SDMMC1_D0 DCMI_D1/PSSI_D1 - EVENTOUT PA11 - FDCAN1_RX USB_DM - - - - EVENTOUT PA12 SAI2_FS_B FDCAN1_TX USB_DP - - - - EVENTOUT PA13 - - - - - - - EVENTOUT PA14 - - - - - - - EVENTOUT PA15 UART4_RTS/ UART4_DE - - UART7_TX FMC_NBL1 DCMI_D11/PSSI_D11 TIM2_ETR EVENTOUT A STM32H562xx and STM32H563xx PA0 AF8 Port DS14258 Rev 5 B AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS PB0 UART4_CTS - - ETH_MII_RXD2 - - LPTIM3_CH1 EVENTOUT PB1 - - - ETH_MII_RXD3 - - LPTIM3_CH2 EVENTOUT PB2 - OCTOSPI1_CLK OCTOSPI1_DQS - SDMMC1_CMD LPTIM5_ETR - EVENTOUT PB3 SPI6_SCK SDMMC2_D2 CRS_SYNC UART7_RX - - LPTIM6_ETR EVENTOUT PB4 SPI6_MISO SDMMC2_D3 - UART7_TX - DCMI_D7/PSSI_D7 - EVENTOUT PB5 SPI6_MOSI FDCAN2_RX - ETH_PPS_OUT FMC_SDCKE1 DCMI_D10/PSSI_D10 UART5_RX EVENTOUT PB6 LPUART1_TX FDCAN2_TX OCTOSPI1_NCS - FMC_SDNE1 DCMI_D5/PSSI_D5 UART5_TX EVENTOUT PB7 LPUART1_RX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN FMC_NL DCMI_VSYNC/ PSSI_RDY - EVENTOUT PB8 UART4_RX FDCAN1_RX SDMMC2_D4 ETH_MII_TXD3 SDMMC1_D4 DCMI_D6/PSSI_D6 - EVENTOUT PB9 UART4_TX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN SDMMC1_D5 DCMI_D7/PSSI_D7 - EVENTOUT PB10 - OCTOSPI1_NCS - ETH_MII_RX_ER - - - EVENTOUT PB11 - - - ETH_MII_TX_EN/ ETH_RMII_TX_EN FMC_NBL1 - - EVENTOUT PB12 - FDCAN2_RX - ETH_MII_TXD0/ ETH_RMII_TXD0 - - UART5_RX EVENTOUT PB13 - FDCAN2_TX - - SDMMC1_D0 - UART5_TX EVENTOUT PB14 UART4_RTS/ UART4_DE SDMMC2_D0 - - - - LPTIM3_ETR EVENTOUT PB15 UART4_CTS SDMMC2_D1 OCTOSPI1_CLK ETH_MII_TXD1/ ETH_RMII_TXD1 - DCMI_D2/PSSI_D2 UART5_RX EVENTOUT STM32H562xx and STM32H563xx Table 16. Alternate functions AF8 to AF15(1) (continued) 113/270 114/270 Table 16. Alternate functions AF8 to AF15(1) (continued) AF8 Port DS14258 Rev 5 C AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS SAI2_FS_B FMC_A25 OCTOSPI1_IO7 - FMC_SDNWE - - EVENTOUT PC1 SAI2_SD_A SDMMC2_CK OCTOSPI1_IO4 ETH_MDC - - - EVENTOUT PC2 - OCTOSPI1_IO2 - ETH_MII_TXD2 FMC_SDNE0 - - EVENTOUT PC3 - OCTOSPI1_IO0 - ETH_MII_TX_CLK FMC_SDCKE0 - - EVENTOUT PC4 - - - ETH_MII_RXD0/ ETH_RMII_RXD0 FMC_SDNE0 - - EVENTOUT PC5 - - OCTOSPI1_DQS ETH_MII_RXD1/ ETH_RMII_RXD1 FMC_SDCKE0 - - EVENTOUT PC6 SDMMC1_D0D IR FMC_NWAIT SDMMC2_D6 OCTOSPI1_IO5 SDMMC1_D6 DCMI_D0/PSSI_D0 - EVENTOUT PC7 SDMMC1_D12 3DIR FMC_NE1 SDMMC2_D7 OCTOSPI1_IO6 SDMMC1_D7 DCMI_D1/PSSI_D1 - EVENTOUT PC8 UART5_RTS/ UART5_DE FMC_NE2/ FMC_NCE FMC_INT FMC_ALE SDMMC1_D0 DCMI_D2/PSSI_D2 - EVENTOUT PC9 UART5_CTS OCTOSPI1_IO0 - FMC_CLE SDMMC1_D1 DCMI_D3/PSSI_D3 - EVENTOUT PC10 UART4_TX OCTOSPI1_IO1 - ETH_MII_TXD0/ ETH_RMII_TXD0 SDMMC1_D2 DCMI_D8/PSSI_D8 - EVENTOUT PC11 UART4_RX OCTOSPI1_NCS - - SDMMC1_D3 DCMI_D4/PSSI_D4 - EVENTOUT PC12 UART5_TX - - - SDMMC1_CK DCMI_D9/PSSI_D9 - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT STM32H562xx and STM32H563xx PC0 AF8 Port DS14258 Rev 5 D AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS PD0 UART4_RX FDCAN1_RX - UART9_CTS FMC_D2/FMC_AD2 - - EVENTOUT PD1 UART4_TX FDCAN1_TX - - FMC_D3/FMC_AD3 - - EVENTOUT PD2 UART5_RX - - - SDMMC1_CMD DCMI_D11/PSSI_D11 LPTIM4_ETR EVENTOUT PD3 - - - - FMC_CLK DCMI_D5/PSSI_D5 - EVENTOUT PD4 - - OCTOSPI1_IO4 - FMC_NOE - - EVENTOUT PD5 - FDCAN1_TX OCTOSPI1_IO5 - FMC_NWE - - EVENTOUT PD6 - - OCTOSPI1_IO6 SDMMC2_CK FMC_NWAIT DCMI_D10/PSSI_D10 - EVENTOUT PD7 - - OCTOSPI1_IO7 SDMMC2_CMD FMC_NE1/ FMC_NCE - LPTIM4_OUT EVENTOUT PD8 - - - - FMC_D13/ FMC_AD13 - - EVENTOUT PD9 - FDCAN2_RX - - FMC_D14/ FMC_AD14 - - EVENTOUT PD10 - - - - FMC_D15/ FMC_AD15 - - EVENTOUT PD11 UART4_RX OCTOSPI1_IO0 SAI2_SD_A - FMC_A16/FMC_CLE - - EVENTOUT PD12 UART4_TX OCTOSPI1_IO1 SAI2_FS_A - FMC_A17/FMC_ALE DCMI_D12/PSSI_D12 - EVENTOUT PD13 - OCTOSPI1_IO3 SAI2_SCK_A UART9_RTS/ UART9_DE FMC_A18 DCMI_D13/PSSI_D13 LPTIM4_IN1 EVENTOUT PD14 UART8_CTS - - UART9_RX FMC_D0/FMC_AD0 - - EVENTOUT PD15 UART8_RTS/ UART8_DE - - UART9_TX FMC_D1/FMC_AD1 - - EVENTOUT STM32H562xx and STM32H563xx Table 16. Alternate functions AF8 to AF15(1) (continued) 115/270 116/270 Table 16. Alternate functions AF8 to AF15(1) (continued) AF8 Port DS14258 Rev 5 E AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS UART8_RX FDCAN1_RX SAI2_MCLK_A - FMC_NBL0 DCMI_D2/PSSI_D2 - EVENTOUT PE1 UART8_TX FDCAN1_TX - - FMC_NBL1 DCMI_D3/PSSI_D3 - EVENTOUT PE2 UART8_TX OCTOSPI1_IO2 - ETH_MII_TXD3 FMC_A23 DCMI_D3/PSSI_D3 - EVENTOUT PE3 - - - - FMC_A19 - - EVENTOUT PE4 - - - - FMC_A20 DCMI_D4/PSSI_D4 - EVENTOUT PE5 - - - - FMC_A21 DCMI_D6/PSSI_D6 - EVENTOUT PE6 - - SAI2_MCLK_B - FMC_A22 DCMI_D7/PSSI_D7 - EVENTOUT PE7 - - OCTOSPI1_IO4 - FMC_D4/FMC_AD4 - - EVENTOUT PE8 - - OCTOSPI1_IO5 - FMC_D5/FMC_AD5 - - EVENTOUT PE9 - - OCTOSPI1_IO6 - FMC_D6/FMC_AD6 - - EVENTOUT PE10 - - OCTOSPI1_IO7 - FMC_D7/FMC_AD7 - - EVENTOUT PE11 - - SAI2_SD_B - FMC_D8/FMC_AD8 - - EVENTOUT PE12 - - SAI2_SCK_B - FMC_D9/FMC_AD9 - - EVENTOUT PE13 - - SAI2_FS_B - FMC_D10/ FMC_AD10 - - EVENTOUT PE14 - - SAI2_MCLK_B - FMC_D11/ FMC_AD11 - - EVENTOUT PE15 - - - - FMC_D12/ FMC_AD12 - - EVENTOUT STM32H562xx and STM32H563xx PE0 AF8 Port DS14258 Rev 5 F AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS PF0 - - - - FMC_A0 LPTIM5_CH1 - EVENTOUT PF1 - - - - FMC_A1 LPTIM5_CH2 - EVENTOUT PF2 - - - - FMC_A2 LPTIM5_IN1 - EVENTOUT PF3 - - - - FMC_A3 LPTIM5_IN2 - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - LPTIM3_IN1 EVENTOUT PF6 - - OCTOSPI1_IO3 - - LPTIM5_CH1 - EVENTOUT PF7 - - OCTOSPI1_IO2 - - LPTIM5_CH2 - EVENTOUT PF8 - TIM13_CH1 OCTOSPI1_IO0 - - LPTIM5_IN1 - EVENTOUT PF9 - TIM14_CH1 OCTOSPI1_IO1 - - LPTIM5_IN2 - EVENTOUT PF10 - OCTOSPI1_CLK - - - DCMI_D11/PSSI_D11 - EVENTOUT PF11 - OCTOSPI1_NCLK SAI2_SD_B - FMC_NRAS DCMI_D12/PSSI_D12 LPTIM6_CH1 EVENTOUT PF12 - - - - FMC_A6 - LPTIM6_CH2 EVENTOUT PF13 - - - - FMC_A7 - LPTIM6_IN1 EVENTOUT PF14 - - - - FMC_A8 - LPTIM6_IN2 EVENTOUT PF15 - - - - FMC_A9 - - EVENTOUT STM32H562xx and STM32H563xx Table 16. Alternate functions AF8 to AF15(1) (continued) 117/270 118/270 Table 16. Alternate functions AF8 to AF15(1) (continued) AF8 Port DS14258 Rev 5 G AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS - - - UART9_RX FMC_A10 - LPTIM4_IN1 EVENTOUT PG1 - - - UART9_TX FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 - LPTIM6_ETR EVENTOUT PG3 - - - - FMC_A13 LPTIM5_ETR - EVENTOUT PG4 - - - - FMC_A14/FMC_BA0 - LPTIM4_ETR EVENTOUT PG5 - - - - FMC_A15/FMC_BA1 - - EVENTOUT PG6 - - OCTOSPI1_NCS UCPD1_FRSTX FMC_NE3 DCMI_D12/PSSI_D12 - EVENTOUT PG7 - - - UCPD1_FRSTX FMC_INT DCMI_D13/PSSI_D13 - EVENTOUT PG8 - - - ETH_PPS_OUT FMC_SDCLK - - EVENTOUT PG9 - OCTOSPI1_IO6 SAI2_FS_B SDMMC2_D0 FMC_NE2/ FMC_NCE DCMI_VSYNC/ PSSI_RDY - EVENTOUT PG10 - - SAI2_SD_B SDMMC2_D1 FMC_NE3 DCMI_D2/PSSI_D2 - EVENTOUT PG11 - - SDMMC2_D2 ETH_MII_TX_EN/ ETH_RMII_TX_EN - DCMI_D3/PSSI_D3 - EVENTOUT PG12 - - SDMMC2_D3 ETH_MII_TXD1/ ETH_RMII_TXD1 FMC_NE4 DCMI_D11/PSSI_D11 LPTIM5_CH1 EVENTOUT PG13 - - SDMMC2_D6 ETH_MII_TXD0/ ETH_RMII_TXD0 FMC_A24 LPTIM5_CH2 - EVENTOUT PG14 - OCTOSPI1_IO7 SDMMC2_D7 ETH_MII_TXD1/ ETH_RMII_TXD1 FMC_A25 LPTIM5_IN1 - EVENTOUT PG15 - - - - FMC_NCAS DCMI_D13/PSSI_D13 - EVENTOUT STM32H562xx and STM32H563xx PG0 AF8 Port DS14258 Rev 5 H AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH2 - OCTOSPI1_IO4 SAI2_SCK_B ETH_MII_CRS FMC_SDCKE0 - - EVENTOUT PH3 - OCTOSPI1_IO5 SAI2_MCLK_B ETH_MII_COL FMC_SDNE0 - - EVENTOUT PH4 - - - - - PSSI_D14 - EVENTOUT PH5 - - - - FMC_SDNWE - - EVENTOUT PH6 - - - ETH_MII_RXD2 FMC_SDNE1 DCMI_D8/PSSI_D8 - EVENTOUT PH7 - - - ETH_MII_RXD3 FMC_SDCKE1 DCMI_D9/PSSI_D9 - EVENTOUT PH8 - - - - - DCMI_HSYNC/ PSSI_DE - EVENTOUT PH9 - - - - - DCMI_D0/PSSI_D0 - EVENTOUT PH10 - - - - - DCMI_D1/PSSI_D1 - EVENTOUT PH11 - - - - - DCMI_D2/PSSI_D2 - EVENTOUT PH12 - - TIM8_CH4N - - DCMI_D3/PSSI_D3 - EVENTOUT PH13 UART4_TX FDCAN1_TX - - - DCMI_D3/PSSI_D3 - EVENTOUT PH14 UART4_RX FDCAN1_RX - - - DCMI_D4/PSSI_D4 - EVENTOUT PH15 - - - - - DCMI_D11/PSSI_D11 - EVENTOUT STM32H562xx and STM32H563xx Table 16. Alternate functions AF8 to AF15(1) (continued) 119/270 120/270 Table 16. Alternate functions AF8 to AF15(1) (continued) AF8 Port DS14258 Rev 5 I AF9 AF10 AF11 AF12 AF13 FDCAN1/2/FMC FMC[NAND16)/ ETH[MII/RMII)/ DCMI/FMC[NAND16)/ CRS/FMC[NAND [NAND16)/FMC FMC[NORmux)/ FMC[NAND16)/ LPUART1/SAI2 FMC[NORmux)/ 16)/OCTOSPI/S [NORmux)/FMC FMC[NOR_RAM)/ OCTOSPI/ /SDMMC1/SPI6 FMC[NOR_RAM)/ AI2/SDMMC2/ [NOR_RAM)/ FMC[SDRAM_16bit) SDMMC2/ /UART4/5/8 LPTIM5 TIM8/USB_PD OCTOSPI/ /SDMMC1 UART7/9/USB_PD SDMMC2/TIM13/14 AF14 AF15 LPTIM3/4/5/6/ TIM2/UART5 SYS - - - - - DCMI_D13/PSSI_D13 - EVENTOUT PI1 - - - - - DCMI_D8/PSSI_D8 - EVENTOUT PI2 - - - - - DCMI_D9/PSSI_D9 - EVENTOUT PI3 - - - - - DCMI_D10/PSSI_D10 - EVENTOUT PI4 - - SAI2_MCLK_A - - DCMI_D5/PSSI_D5 - EVENTOUT PI5 - - SAI2_SCK_A - - DCMI_VSYNC/ PSSI_RDY - EVENTOUT PI6 - - SAI2_SD_A - - DCMI_D6/PSSI_D6 - EVENTOUT PI7 - - SAI2_FS_A - - DCMI_D7/PSSI_D7 - EVENTOUT PI8 - - - - - - - EVENTOUT PI9 UART4_RX FDCAN1_RX - - - - - EVENTOUT PI10 - FDCAN1_RX - ETH_MII_RX_ER - PSSI_D14 - EVENTOUT PI11 - - - - - PSSI_D15 - EVENTOUT 1. Refer to the previous table for AF0 to AF7. STM32H562xx and STM32H563xx PI0 STM32H562xx and STM32H563xx Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes, and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = VDDA = 3.3 V (for the 1.71 ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 18. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 19. Figure 18. Pin loading conditions Figure 19. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V DS14258 Rev 5 MS19211V 121/270 238 Electrical characteristics 5.1.6 STM32H562xx and STM32H563xx Power supply scheme Figure 20. Power supply scheme with SMPS STM32H5 SMPS disabled VDDSMPS SMPS packages VDDSMPS ȝ) 4.7 ȝ) ȝ) ȝ) ȝ+ SMPS Switched Mode Power Supply step down converter VLXSMPS floating 100 pF or 200 pF VSSSMPS VCAP1/2 Core domain 100 nF LDO Voltage regulator SMPS enabled VDDIO2 VDDIO2 ȝ) VDDIO2 IOs 100 nF Two different possible use cases VDD 100 nF VDD IOs VDD VDD ȝ) VDDLDO 100 nF VDD domain VSS Power switch Backup domain Two different possible use cases VBAT Battery ȝ) 100 nF BKUP IOs VDD Two different possible use cases VDDUSB VDDUSB 100 nF ȝ) VDDA VDDA VREF+ 100 nF ȝ) Three different possible use cases Analog domain 100 nF ȝ) Ÿ USB FS IOs VREF+ VREFVSSA ȝ) Defines different use case options Internal VREFBUF enabled Define power domaines MSv71967V3 122/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Figure 21. Power supply scheme with LDO STM32H5 LDO packages VDDSMPS VLXSMPS VSSSMPS SMPS Switched Mode Power Supply step down converter VCAP1/2 [ȝ) 100 nF LDO enabled Core domain LDO Voltage regulator LDO disabled VDDIO2 VDDIO2 ȝ) 100 nF Two different possible use cases VDDLDO VDDIO2 IOs VDD 100 nF VDD IOs VDD VDD ȝ) 100 nF VDD domain VSS Power switch Two different possible use cases Backup domain VBAT Battery ȝ) 100 nF BKUP IOs VDD Two different possible use cases VDDUSB VDDUSB ȝ) 100 nF USB FS IOs VDDA VDDA ȝ) 100 nF Ÿ 100 nF VREF+ ȝ) Three different possible use cases VREF+ VREFVSSA Analog domain ȝ) Defines different use case options Internal VREFBUF enabled Note: Define power domaines MSv71966V3 Refer to “Getting started with STM32H5 Series hardware development” (AN5711) for more details. DS14258 Rev 5 123/270 238 Electrical characteristics STM32H562xx and STM32H563xx Caution: Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 17, Table 18, and Table 19 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 17. Voltage characteristics(1) Symbol VDDx - VSS VDDIOx(4) VSS VIN(5) Ratings Min Max Unit External main supply voltage (including VDDSMPS(2), VDDA, VDDUSB, VDDIO2(2)(3)(4), VBAT, and VREF+) -0.3 4.0 V I/O supply when HSLV(2) = 0 -0.3 4.0 -0.3 2.75 Input voltage on FT_xxx pins except FT_c pins VSS - 0.3 min (min(VDD, VDDA, VDDUSB, VDDIO2) + 4.0, 6.0 V)(6)(7) Input voltage on FT_t in VBAT mode VSS - 0.3 min (min(VBAT, VDDA, VDDUSB, VDDIO2) + 4.0V, 6.0 V) Input voltage on TT_xx pins VSS - 0.3 4.0 Input voltage on BOOT0 pin VSS min (min(VDD, VDDA, VDDUSB, VDDIO2) + 4.0, 6.0 V)(6) Input voltage on FT_c pins VSS - 0.3 5.5 Input voltage on any other pins VSS - 0.3 4.0 (2) I/O supply when HSLV =1 VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 |∆VDDx| Variations between different VDDX power pins of the same domain - 50.0 Variations between all the different ground pins - 50.0 |VSSx-VSS| V V V mV 1. All main power (VDD, VDDA, VDDUSB, VDDIO2, VREF+, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481. 3. If HSLV = 0. 4. VDDIO1 or VDDIO2. VDDIO1 = VDD. 5. VIN maximum must always be respected. Refer to the maximum allowed injected current values. 6. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 7. This formula must be applied on power supplies related to the I/O structure described by the pin definition table. 124/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 18. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 350 ∑IVSS (sink)(1) 350 Total current out of sum of all VSS ground lines IVDD Maximum current into each VDD power pin (source)(1) 100 IVSS Maximum current out of each VSS ground pin (sink)(1) 100 IIO(PIN) Output current sunk/sourced by any I/O and control pin Total output current sunk by sum of all I/Os and control pins 140 (2) Total output current sourced by sum of all I/Os and control pins IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins ∑|IINJ(PIN)| Total injected current (sum of all I/Os and control mA 20 (2) ∑IIO(PIN) Unit 140 -5 / 0 pins)(5) ±25 1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the allowed range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os, and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 17 for the minimum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). Table 19. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Value Unit -65 to +150 °C 130(1) °C Maximum junction temperature 1. The junction temperature is limited to 105 °C in the VOS0 voltage range. 5.3 Operating conditions 5.3.1 General operating conditions Table 20. General operating conditions Symbol VDD Parameter Standard operating voltage Supply voltage for the VDDSMPS internal SMPS step-down converter Operating conditions HSLV(1) = 0 HSLV (1) =1 Min Typ Max 1.71(2) - 3.6 (2) - 2.7 - VDD 1.71 VDD VDD DS14258 Rev 5 Unit V V 125/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 20. General operating conditions (continued) Symbol VDDIO2 Parameter PB8, PB9, PD6, PD7, PG[9:14] I/Os supply voltage Operating conditions Min Typ Max At least one I/O in PB8, PB9, PD6, PD7, PG[9:14] is used, HSLV(1) = 0 1.08 - 3.6 At least one I/O in PB8, PB9, PD6, PD7, PG[9:14] is used, HSLV(1) = 1 1.08 - 2.7 PB8, PB9, PD6, PD7, PG[9:14] are not used VDDUSB USB supply voltage VDDA Analog supply voltage USB is used - 3.6 0 - 3.6 ADC is used 1.62 - DAC is used 1.8 - VREFBUF is used 2.1 - 0 - 1.2 - USB is not used Backup domain supply voltage - All I/Os except FT_c and TT_xx -0.3 V 3.6 3.0 ADC, DAC, and VREFBUF are not used VBAT 0 Unit - V 3.6 V 3.6 V min (min (VDD, VDDA, VDDUSB, VDDIO2) + 3.6V, 5.5 V) (3)(4) VIN I/O input voltage Input voltage on FT_t in VBAT mode -0.3 - min (min (VBAT, VDDA, VDDUSB, VDDIO2) + 3.6 V, 5.5 V) (3)(4) 126/270 FT_c I/O -0.3 - 5.0 TT_xx I/O -0.3 - VDDIOx + 0.3 DS14258 Rev 5 V STM32H562xx and STM32H563xx Electrical characteristics Table 20. General operating conditions (continued) Symbol Parameter Operating conditions Min Typ Max VOS0 (max frequency for AHB and APB: 250 MHz) 1.30 1.35 1.40 VOS1 (max frequency for AHB and APB: 200 MHz) 1.15 1.20 1.26 VOS2 (max frequency for AHB and APB: 150 MHz) 1.05 1.10 1.15 VOS3 (max frequency for AHB and APB: 100 MHz) 0.95 1.00 1.05 VOS0(5) 1.32 1.35 1.40 VOS1 1.17 1.20 1.26 VOS2 1.07 1.10 1.15 VOS3 0.97 1.00 1.05 SVOS3 - 1.0 - SVOS4 - 0.9 - SVOS5 - 0.74 - - - 250 VOS1 - - 200 VOS2 - - 150 VOS3 - - 100 VOS0(5) - - 250 VOS1 - - 200 VOS2 - - 150 VOS3 - - 100 (5) Internal regulator ON VCORE Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins Stop mode VOS0 fHCLK AHB clock frequency fPCLKx APB1, APB2, APB3 (x=1,2,3) clock frequency (5) LQFP64 PD Power dissipation at TA = 85 or 105 °C for suffix 6 or 7 versions(6) V See Table 140 for appropriate thermal resistance and package. Power dissipation is calculated according to ambient temperature (TA), maximum junction temperature (TJ), and selected thermal resistance. LQFP100 LQFP144 LQFP176 UFBGA169 UFBGA176 VFQFPN68 Unit V V MHz MHz mW WLCSP80 DS14258 Rev 5 127/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 20. General operating conditions (continued) Symbol Parameter Operating conditions Min LQFP100 Power dissipation at TA = 125 °C for suffix 3 version(6) LQFP176 UFBGA169 UFBGA176 WLCSP80 Ambient temperature for the suffix 3 version TA TJ Max See Table 140 for appropriate thermal resistance and package. Power dissipation is calculated according to ambient temperature (TA), maximum junction temperature (TJ), and selected thermal resistance. LQFP144 PD Typ Maximum power dissipation -40 - 125 Ambient temperature for the suffix 6 version Maximum power dissipation -40 - 85 In LDO bypass mode -40 - 125 Ambient temperature for the suffix 7 version Maximum power dissipation -40 - 105 In LDO bypass mode -40 - 125 Junction temperature range VOS0 -40 - 105 VOS1, VOS2, and VOS3 -40 - 130 Unit mW °C °C 1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481. 2. When RESET is released functionality is guaranteed down to BOR level 0 minimum voltage. 3. This formula must be applied on power supplies related to the I/O structure described by the pin definition table. Maximum I/O input voltage is the smallest value between min (VDD, VDDA, VDDIO2) + 3.6 V and 5.5 V. 4. For operation with voltages higher than min (VDD, VDDA, VDDIO2) + 0.3V, the internal pull-up and pull-down resistors must be disabled. 5. In VOS0 mode the max TJ is 105 °C. 6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19). Table 21. Maximum allowed clock frequencies Symbol(1)(2) 128/270 Parameter VOS0 VOS1 VOS2 VOS3 fCPU CPU 250 200 150 100 fHCLK AHB 250 200 150 100 fPCLK APB 250 200 150 100 - FMC 250 200 150 100 foctospi_ker_ck OCTOSPI[1:2] 250 200 150 100 fsdmmc_ker_ck SDMMC[1:2] 250 200 150 100 - HDMI_CEC 4 4 4 4 ffdcan_ker_ck FDCAN 250 200 150 100 fI2C_ker_ck I2C[1:4] 250 200 150 100 fI3C_ker_ck I3C 250 200 150 100 flptim_ker_ck LPTIM[1:6] 250 200 150 100 DS14258 Rev 5 Unit MHz STM32H562xx and STM32H563xx Electrical characteristics Table 21. Maximum allowed clock frequencies (continued) Symbol(1)(2) VOS0 VOS1 VOS2 VOS3 TIM[1:8], TIM[12:17] 250 200 150 100 TIM6/17 64 64 64 64 RNG 50 50 50 50 SAI1/2 250 200 150 100 SPI(I2S)1,2,3 125 100 75 50 SPI4,5,6 125 100 75 50 flpuart_ker_ck LPUART1 250 200 150 100 fusart_ker_ck USART/UART 250 200 150 100 fusb_ker_ck USB FS 50 50 50 50 250 200 150 100 ftim_ker_ck frng_clk fsai_a_ker_ck fsai_b_ker_ck fspi_ker_ck Parameter fadc_ker_ck_input ADC fadc_ker_ck(3) ADC 125 100 75 50 fdac_ker_ck DAC 250 200 150 100 fucpd_ker_ck USBPD 64 64 64 64 frtc_ker_ck RTC 1 1 1 1 - DCMI 250 200 150 100 Unit MHz 1. Specified by design - Not tested in production. 2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency (refer to each peripheral electrical characteristics). 3. This maximum kernel clock frequency does not consider the maximum ADC clock frequency (refer to Table 95). 5.3.2 VCAP external capacitor The stabilization for the embedded LDO regulator is achieved by connecting an external capacitor CEXT (whose value is specified in Table 22) to the VCAPx (one or two pins, depending upon the package). Two external capacitors must be connected to VCAP pins (refer to AN5711 “STM32H5 Series hardware development”). Figure 22. External capacitor CEXT C ESR R Leak MS19044V2 DS14258 Rev 5 129/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 22. Supply voltage and maximum frequency configuration Symbol Parameter Conditions CEXT External capacitor for LDO enabled 2.2 μF(1) ESR Equivalent series resistance of the external capacitor < 100 mΩ 1. This value corresponds to CEXT typical value. A variation of ±20% is tolerated 5.3.3 SMPS step-down converter The devices embed a high power efficiency SMPS step-down converter requiring external components. Table 23. Characteristics of SMPS step-down converter external components Symbol Cin Cfilt COUT Parameter Capacitance of external capacitor on VDDSMPS pins ESR of external capacitor Capacitance of external capacitor on VLXSMPS pin Capacitance of external capacitor on VCAP pin ESR of external capacitor Inductance of external inductor on VLXSMPS pin L Series DC resistance Conditions Min Typ Max Unit - - 4.7(1) - µF 2.4 MHz - - 10 mΩ - - 220 - pF - - 10(1) - µF 2.4 MHz - 20 mΩ - µH - - 2.2(1) All packages - - 150 WLCSP80 package, VDDSMPS > 3 V - - 300 ISAT DC current at which the inductance drops 30% from the value without current - 1 - - IRMS Average current for which the temperature of the inductor is raised 40 °C by the DC current - 1 - - mΩ A 1. Tolerance: -50% and + 30% for all conditions. The SMPS current consumption can be determined using the following formula based on the maximum LDO current consumption provided in Section 5.3.7: IDDSMPS = IDDLDO × VCORE / (VDD × efficiency) IDDLDO is the current in LDO configuration given in the following tables, VCORE is the digital core supply (VCAP), and efficiency is defined in the following curves. 130/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Figure 23. SMPS efficiency versus load current in Run, Sleep, and Stop modes with SVOS3 mode, TJ = 30 °C Efficiency (%) 100 90 VDDSMPS = 1.8V, VOS0 VDDSMPS = 3.3V, VOS0 VDDSMPS = 1.8V, VOS1 VDDSMPS = 3.3V, VOS1 VDDSMPS = 1.8V, VOS2 VDDSMPS = 3.3V, VOS2 VDDSMPS = 1.8V, VOS3 VDDSMPS = 3.3V, VOS3 80 70 60 50 40 30 1 Note: 10 100 1000 Current (mA) MSv71968V1 SVOS3 is equivalent to VOS3 in Run and Sleep modes. Figure 24. SMPS efficiency versus load current in Run, Sleep, and Stop modes with SVOS3 mode, TJ = 130 °C Efficiency (%) 100 90 VDDSMPS = 1.8V, VOS0 VDDSMPS = 3.3V, VOS0 80 VDDSMPS = 1.8V, VOS0 VDDSMPS = 3.3V, VOS0 70 VDDSMPS = 1.8V, VOS1 VDDSMPS = 3.3V, VOS1 VDDSMPS = 1.8V, VOS2 60 VDDSMPS = 3.3V, VOS2 VDDSMPS = 1.8V, VOS3 VDDSMPS = 3.3V, VOS3 50 40 Current (mA) 30 1 Note: 10 100 1000 MSv71969V1 SVOS3 is equivalent to VOS3 in Run and Sleep modes. DS14258 Rev 5 131/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 25. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C Figure 26. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C 132/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 5.3.4 Electrical characteristics Operating conditions at power-up/down Subject to general operating conditions for TA. v Table 24. Operating conditions at power-up/down (regulator ON) Symbol TVDD TVDDA TVDDUSB TVDDIO2 TVBAT 5.3.5 Parameter Min Max VDD rise time rate 0 ∞ VDD fall time rate 10 ∞ VDDA rise time rate 0 ∞ VDDA fall time rate 10 ∞ TVDDUSB rise time rate 0 ∞ TVDDUSB fall time rate 10 ∞ TVDDIO2 rise time rate 0 ∞ TVDDIO2 fall time rate 10 ∞ TVBAT rise time rate 0 ∞ TVBAT fall time rate 10 ∞ Unit μs/V Embedded reset and power control block characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 20. Table 25. Embedded reset and power control block characteristics(1) Symbol tRSTTEMPO(2) Parameter Conditions Reset temporization after BOR0 detection VDD rising Min Typ Max Unit - 377 550 μs Power-on/down reset threshold (BORH_EN =0) Rising edge 1.62 1.67 1.71 Falling edge 1.58 1.62 1.68 VBOR1 Brownout reset threshold 1 (BORH_EN =1) Rising edge 2.04 2.10 2.15 Falling edge 1.95 2.00 2.06 VBOR2 Brownout reset threshold 2 (BORH_EN =1) Rising edge 2.34 2.41 2.47 Falling edge 2.25 2.31 2.37 VBOR3 Brownout reset threshold 3 (BORH_EN =1) Rising edge 2.63 2.70 2.78 Falling edge 2.54 2.61 2.68 VPOR/PDR DS14258 Rev 5 V V 133/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 25. Embedded reset and power control block characteristics(1) (continued) Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Conditions Min Typ Max Rising edge 1.90 1.96 2.01 Falling edge 1.81 1.86 1.91 Rising edge 2.05 2.10 2.16 Falling edge 1.96 2.01 2.06 Rising edge 2.19 2.26 2.32 Falling edge 2.10 2.15 2.21 Rising edge 2.35 2.41 2.47 Falling edge 2.25 2.31 2.37 Rising edge 2.49 2.56 2.62 Falling edge 2.39 2.45 2.51 Rising edge 2.64 2.71 2.78 Falling edge 2.55 2.61 2.68 Rising edge 2.78 2.86 2.94 Falling edge 2.69 2.76 2.83 VPOR/PDR Hysteresis for power-on/down reset Hysteresis in Run mode - 43 - Vhyst_BOR_PVD Hysteresis voltage of BOR (unless BORH_EN = 0) and PVD - - 100 - IDD_BOR_PVD(2) BOR and PVD consumption from VDD - - - 0.630 IDD_POR_PDR POR and PDR consumption from VDD - 0.8 - 1.2 Rising edge 1.66 1.71 1.76 Falling edge 1.56 1.61 1.66 Rising edge 2.06 2.12 2.19 Falling edge 1.96 2.02 2.08 Rising edge 2.42 2.50 2.58 Falling edge 2.35 2.42 2.49 Rising edge 2.74 2.83 2.91 Falling edge 2.64 2.72 2.80 VAVD0 VDDA voltage monitor 0 threshold VAVD1 VDDA voltage monitor 1threshold Unit V mV µA V VAVD2 VDDA voltage monitor 2 threshold VAVD3 VDDA voltage monitor 3 threshold VIO2VM VDDIO2 voltage monitor threshold - - 0.9 - V Hysteresis of VDDA voltage monitor - - 100 - mV IDD_AVD_IO2VM(2) Power voltage detector consumption from VDD (AVD, IO2VM) - - - 0.25 IDD_AVD_A(2) Analog voltage detector consumption from VDDA (resistor bridge) - - - 0.25 Vhyst_AVD µA 1. Evaluated by characterization and not tested in production, unless otherwise specified. 2. Specified by design - Not tested in production 134/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 5.3.6 Electrical characteristics Embedded reference voltage The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20. Table 26. Embedded reference voltage Symbol Parameter VREFINT(1) Conditions Internal reference voltage ADC sampling time when reading the internal reference voltage tS_vbat VBAT sampling time when reading the internal VBAT voltage tstart_vrefint(3) Start time of reference voltage buffer when the ADC is enabled ∆VREFINT(3) TCoeff VDDcoeff VREFINT_DIV1 (3) - VREFINT_DIV3 Max Unit V 4.3 - - 9 - - - - - 4.4 Reference buffer consumption for ADC VDD = 3.3 V 9 13.5 23 µA Internal reference voltage spread over -40 °C < TJ < +130 °C the temperature range - 5 15 mV µs Average temperature coefficient Average temperature coefficient - 20 70 ppm/°C Average voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V - 25 - - 50 - - 75 - 1/4 reference voltage VREFINT_DIV2(3) 1/2 reference voltage (3) Typ -40 °C < TJ < +130 °C 1.180 1.216 1.255 tS_vrefint(2)(3) Irefbuf(3) Min - 3/4 reference voltage %VREFINT 1. VREFINT does not take into account package and soldering effects. 2. The shortest sampling time for the application can be determined by multiple iterations. 3. Specified by design - Not tested in production. Table 27. Internal reference voltage calibration value Symbol VREFINT_CAL 5.3.7 Parameter Raw data acquired at 30 °C, VDDA = 3.3 V Memory address 0x08FF F810 - 0x08FF F811 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. All the run-mode current consumption measurements given in this section are performed with a CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode. DS14258 Rev 5 135/270 238 Electrical characteristics STM32H562xx and STM32H563xx • All peripherals are disabled except when explicitly mentioned. • The flash memory access time is adjusted with the minimum wait-state number, depending on the fHCLK frequency (refer to the tables “FLASH recommended number of wait states and programming delay” available in the reference manual). • When the peripherals are enabled, the AHB clock frequency is the CPU frequency and the APB clock frequency is AHB frequency. The parameters given in the following tables are derived from tests performed under supply voltage conditions summarized in Table 20, and, unless otherwise specified, at ambient temperature. The maximum current consumption is given for LDO regulator ON. Table 28. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, 2-way instruction cache ON, PREFETCH ON Max(1)(2) Symbol Parameter Conditions VOS0 VOS1 All peripherals disabled VOS2 VOS3 Supply current IDD(Run) in Run mode VOS0 VOS1 All peripherals enabled VOS2 VOS3 136/270 fHCLK (MHz) Typ LDO Typ SMPS 250 32.1 17.5 37 65 87 - 215 27.9 15.0 32 60 82 - 200 25.7 13.8 30 59 81 - 200 22.1 11.0 25 45 62 93 180 20.3 10.1 23 43 59 90 168 18.8 9.3 21 42 58 89 150 16.9 8.5 20 40 56 88 150 15.4 7.4 17 33 47 73 100 10.8 5.2 13 28 41 68 100 9.8 4.5 11 23 34 55 60 6.4 3.0 8.0 20 30 52 25 3.2 1.7 5.0 17 27 49 250 86.8 49.8 90 118 140 - 215 75.0 43.2 78 107 128 - 200 69.5 40.1 72 102 123 - 200 60.7 31.7 62 82 99 130 180 55.1 28.5 56 76 92 124 150 45.8 23.4 47 68 84 116 150 41.9 20.0 43 59 72 98 100 28.5 13.8 30 45 58 85 100 25.9 11.7 27 39 49 71 60 16.2 7.5 17 29 40 61 25 7.5 3.8 9.0 21 31 53 DS14258 Rev 5 TJ = 25 °C TJ = TJ = TJ = 85 °C 105 °C 130 °C Unit mA STM32H562xx and STM32H563xx Electrical characteristics 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. Table 29. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, 1-way instruction cache ON, PREFETCH ON Max(1)(2) Symbol Parameter Conditions fHCLK (MHz) Typ LDO Typ SMPS 250 29.2 15.9 34 62 84 - 200 23.3 12.5 28 56 78 - 200 20.1 10.0 23 43 59 91 180 18.5 9.2 21 41 57 89 150 15.4 7.8 18 38 54 86 150 14.0 6.7 16 32 45 71 100 9.8 4.8 12 27 40 67 100 8.9 4.2 10 22 33 54 25 3.0 1.6 4.0 17 27 49 VOS0 VOS1 Supply current All peripherals IDD(Run) in Run mode disabled VOS2 VOS3 TJ = TJ = TJ = TJ = 25 °C 85 °C 105 °C 130 °C Unit mA 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. Symbol Table 30. Typical and maximum current consumption in Run mode, code with data processing running from SRAM with cache 1-way Max(1)(2) Parameter Conditions VOS0 VOS1 Supply current All peripherals disabled (Run) in Run mode IDD VOS2 VOS3 fHCLK (MHz) Typ LDO Typ SMPS 250 27.8 15.5 32 61 82 - 215 24.1 13.4 29 57 79 - 200 22.1 12.3 27 55 77 - 200 19.1 9.9 22 42 58 90 180 17.6 9.1 20 40 56 88 150 14.6 7.6 22 42 58 90 150 13.3 6.6 17 37 53 85 100 9.4 4.7 11 27 40 66 100 8.5 4.1 10 22 33 54 60 5.6 2.8 7 19 30 51 25 2.9 1.6 4 16 27 48 TJ = TJ = TJ = TJ = 25 °C 85 °C 105 °C 130 °C Unit mA 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. DS14258 Rev 5 137/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 31. Typical and maximum current consumption in Run mode, code with data processing running from SRAM with cache 2-way Max(1)(2) Symbol Parameter Conditions fHCLK (MHz) Typ LDO Typ SMPS 250 30.8 17.2 35 64 86 - 215 26.7 14.4 31 60 81 - 200 24.6 13.3 29 58 80 - 200 21.2 10.5 24 44 61 93 180 19.5 9.7 22 42 58 90 168 18.0 9.0 21 41 57 89 150 16.2 8.4 19 39 55 87 150 14.8 7.2 17 33 46 72 100 10.3 5.1 12 28 41 67 100 9.4 4.5 11 23 33 55 60 6.1 2.9 8.0 20 30 52 25 3.2 1.7 5.0 17 27 49 VOS0 VOS1 IDD(Run) Supply current All peripherals in Run mode disabled VOS2 VOS3 TJ = TJ = TJ = TJ = 25 °C 85 °C 105 °C 130 °C Unit mA 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. 138/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 32. Typical consumption in Run mode with CoreMark running from flash memory and SRAM(1) Conditions Symbol Parameter Peripheral All peripherals disabled, instruction cache 2-way, prefetch ON IDD(Run) Supply current in Run mode All peripherals disabled, instruction cache 1-way, prefetch ON All peripherals disabled, instruction cache 2-way All peripherals disabled, instruction cache 1-way Code FLASH FLASH SRAM SRAM fHCLK (MHz) Typ LDO Typ SMPS 250 32.1 200 Typ LDO Typ SMPS 17.5 128.6 70.1 22.1 10.97 110.7 54.8 168 18.8 9.3 111.8 55.6 150 15.4 8.5 102.7 56.9 100 9.8 4.5 97.9 45.3 250 29.2 15.9 116.6 63.8 200 20.1 12.5 100.4 62.7 150 14.0 10.0 93.3 66.4 100 8.9 4.2 88.9 41.7 250 30.8 17.2 123.3 68.7 200 21.2 10.5 106.2 52.6 168 18.0 9.0 107.3 53.4 150 14.8 7.2 98.5 48.2 100 9.4 4.5 94.1 44.6 250 27.8 15.5 111.1 61.9 200 19.1 9.9 95.4 49.3 150 13.3 6.6 88.9 43.8 100 8.5 4.1 84.9 40.7 Unit mA Unit μA/MHz 1. Evaluated by characterization - Not tested in production. DS14258 Rev 5 139/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 33. Typical consumption in Run mode with SecureMark running from flash memory and SRAM(1) Conditions Symbol Parameter Peripheral Code All peripherals disabled, instruction cache 2-way, prefetch ON fHCLK (MHz) FLASH Supply IDD(Run) current in Run mode All peripherals disabled, instruction cache 1-way, prefetch ON FLASH Typ Typ Unit LDO SMPS Typ LDO Typ SMPS 250 34.1 17.9 136.3 71.8 180 21.8 10.6 120.9 58.8 168 20.1 9.8 119.7 58.5 150 24.9 7.7 166.2 51.2 100 10.6 4.8 106.0 47.6 250 31.3 16.6 125.2 66.3 180 20.1 9.8 111.6 54.5 168 18.5 9.1 110.4 54.2 150 18.8 7.2 125.1 47.7 100 9.8 4.5 98.3 44.5 mA Unit μA/MHz 1. Evaluated by characterization - Not tested in production. Table 34. Typical and maximum current consumption in Sleep mode Max(1) (2) Symbol Parameter Conditions VOS0 VOS1 IDD(sleep) Supply current All peripherals in sleep mode disabled VOS2 VOS3 fHCLK (MHz) Typ LDO Typ SMPS 250 7.3 200 TJ = 25°C TJ = 85°C 4.2 12 40 61 - 5.8 3.3 10 38 60 - 200 4.8 2.6 8 27 43 75 180 4.8 2.6 8 27 43 75 168 4.3 2.3 7 26 42 74 150 3.9 2.2 7 26 42 74 150 3.5 1.9 6 21 34 60 100 2.8 1.6 5 20 33 59 100 2.5 1.4 4 16 26 48 60 2.0 1.2 4 15 26 47 TJ = TJ = 105°C 130°C Unit mA 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. 140/270 DS14258 Rev 5 STM32H562xx and STM32H563xx v Electrical characteristics Table 35. Typical and maximum current consumption in Stop mode Max(1) (2) Typ LDO Typ SMPS SVOS3 0.37 0.09 2.00 13.98 24.00 44.39 SVOS4 0.27 0.07 1.40 10.48 18.37 34.76 SVOS5 0.19 0.06 0.86 7.08 12.88 25.31 SVOS3 0.38 0.10 2.02 14.01 24.06 44.55 SVOS4 Supply current IDD(stop) SVOS3 Flash memory in in Stop low power mode, SVOS4 SRAMs OFF except SRAM2 16 Kbytes ON SVOS5 0.29 0.09 1.42 10.52 18.46 34.88 0.34 0.09 1.93 13.28 22.75 41.99 0.25 0.07 1.35 9.87 17.33 32.65 0.17 0.05 0.81 6.46 11.68 22.86 SVOS3 0.35 0.10 1.95 13.45 23.02 42.52 SVOS4 0.26 0.08 1.36 10.01 17.52 33.10 SVOS5 0.17 0.08 0.82 6.59 11.92 23.37 Symbol Parameter Conditions Flash memory in low power mode, SRAMs ON Flash memory in normal mode, SRAMs ON Flash memory in low power mode, SRAMs OFF except SRAM2 ON TJ = TJ = TJ = TJ = 25 °C 85 °C 105 °C 130 °C Unit mA 1. Evaluated by characterization - Not tested in production. 2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3 for the SMPS maximum current consumption. Table 36. Typical and maximum current consumption in Standby mode Typ(1) Conditions Symbol Parameter Supply current in IDD(standby) standby mode, IWDG OFF Backup RTC and 1.8 V 2.4 V RAM LSE(2) Max(1) 3V 3.3 V TJ = TJ = 25 °C 85 °C TJ = TJ = 105 °C 130 °C OFF OFF 2.58 2.78 3.01 3.19 5.9 11.7 21.2 53 ON OFF 3.79 4.05 4.38 4.63 8.2 21.0 37.0 90 OFF ON 2.91 3.15 3.47 3.67 6.9 12.9 22.5 55 ON ON 4.16 4.46 4.85 5.12 9.2 22.2 38.3 92 Unit μA 1. Evaluated by characterization - Not tested in production. 2. LSE is in medium-low drive mode. DS14258 Rev 5 141/270 238 Electrical characteristics v STM32H562xx and STM32H563xx Table 37. Typical and maximum current consumption in VBAT mode(1) Conditions Symbol IDD(VBAT) Parameter Supply current in VBAT mode Typ Backup RTC and 1.8 V 2.4 V RAM LSE(2) Max 3V TJ = TJ = TJ = TJ = 3.3 V 25 °C 85 °C 105 °C 130 °C OFF OFF 0.01 0.01 0.02 0.02 0.2 2.45 6.2 19.0 ON OFF 1.11 1.14 1.17 1.29 4.5 16.05 30.0 72.2 OFF ON 0.45 0.46 0.48 0.59 1.2 3.65 7.5 21.0 ON ON 1.56 1.57 1.62 1.84 5.5 17.25 31.3 74.2 Unit μA 1. Evaluated by characterization - Not tested in production. 2. LSE is in medium-low drive mode. I/O system current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 58. To estimate the current consumption for the output pins, consider also external pull-downs or loads. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this current consumption can be avoided by configuring the I/Os in analog mode. This is notably the case of ADC input pins, to be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done by using pull-up/down resistors, or by configuring the pins in output mode. In addition to the internal peripheral current consumption, the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDx × f SW × C L where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 142/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration • All peripherals are disabled unless otherwise mentioned • The I/O compensation cell is enabled • fHCLK is the CPU clock, fPCLK = frcc_cpu_ck, and fHCLK = frcc_cpu_ck. The given value is calculated by measuring the difference of current consumption: • with all peripherals clocked off • with only one peripheral clocked on • frcc_cpu_ck = 250 MHz (Scale 0), frcc_cpu_ck = 200 MHz (Scale 1), frcc_cpu_ck = 150 MHz (Scale 2), frcc_cpu_ck= 100 MHz (Scale 3) • the ambient operating temperature is 25 °C and VDD = 3.0 V Table 38. Peripheral current consumption in Sleep mode Bus AHB1 IDD (typ) Peripheral Unit VOS0 VOS1 VOS2 VOS3 SRAM1 0.9 0.85 0.78 0.7 BKPRAM 0.95 0.89 0.82 0.74 CORDIC 0.5 0.45 0.42 0.4 CRC 0.22 0.21 0.18 0.18 DCACHE 0.66 0.59 0.55 0.51 ETH 11.33 10 9.13 8.32 FLASH 10.19 8.87 8.09 7.35 FMAC 2.07 1.84 1.68 1.56 GPDMA1 0.62 0.55 0.51 0.45 GPDMA2 0.45 0.43 0.38 0.35 GTZC1 1.19 1.05 0.97 0.9 ICACHE 0.86 0.81 0.75 0.67 RAMCFG 0.88 0.79 0.71 0.67 AHB1 1.09 0.94 0.86 0.79 DS14258 Rev 5 μA/MHz 143/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 38. Peripheral current consumption in Sleep mode (continued) Bus AHB2 AHB4 144/270 IDD (typ) Peripheral Unit VOS0 VOS1 VOS2 VOS3 ADC12 2.35 2.1 1.9 1.74 DAC1 1.35 1.19 1.07 0.98 DCMI 3.49 3.09 2.83 2.55 GPIOA 0.1 0.08 0.07 0.08 GPIOB 0.07 0.06 0.05 0.05 GPIOC 0.08 0.05 0.04 0.04 GPIOD 0.09 0.06 0.05 0.04 GPIOE 0.09 0.09 0.08 0.05 GPIOF 0.06 0.08 0.08 0.05 GPIOG 0.07 0.07 0.06 0.04 GPIOH 0.07 0.07 0.05 0.06 GPIOI 0.07 0.07 0.06 0.04 HASH1 1.37 1.2 1.1 1 PKA 5.43 4.78 4.37 3.98 RNG1 1.12 0.99 0.9 0.82 SRAM2 1.33 1.18 1.06 0.96 SRAM3 1.5 1.33 1.22 1.1 AHB2 1.59 1.39 1.29 1.16 FMC 9.73 8.48 7.69 6.95 OSPI1 2.88 2.54 2.29 2.08 SDMMC1 8.71 7.64 6.98 6.36 SDMMC2 8.46 7.45 6.82 6.2 AHB4 0.36 0.32 0.32 0.28 DS14258 Rev 5 μA/MHz uA/MHz STM32H562xx and STM32H563xx Electrical characteristics Table 38. Peripheral current consumption in Sleep mode (continued) Bus APB1 IDD (typ) Peripheral Unit VOS0 VOS1 VOS2 VOS3 CEC 0.15 0.15 0.14 0.11 CRS 0.22 0.23 0.20 0.19 FDCAN1 6.37 5.63 5.14 4.70 I2C1 0.57 0.5 0.49 0.42 I2C2 0.57 0.52 0.5 0.46 I3C1 0.28 0.27 0.28 0.25 LPTIM2 0.91 0.81 0.75 0.69 SPI2 1.04 0.93 0.89 0.78 SPI3 1.00 0.92 0.85 0.76 TIM12 1.41 1.26 1.18 1.06 TIM13 0.92 0.82 0.77 0.70 TIM14 0.89 0.78 0.75 0.66 TIM2 2.86 2.51 2.30 2.11 TIM3 2.52 2.21 2.03 1.87 TIM4 2.43 2.15 1.96 1.79 TIM5 2.79 2.48 2.26 2.06 TIM6 0.54 0.49 0.45 0.42 TIM7 0.56 0.5 0.48 0.43 UART12 1.17 1.06 0.95 0.88 UART4 1.12 0.98 0.93 0.83 UART5 1.09 0.99 0.93 0.84 UART7 1.28 1.14 1.05 0.93 UART8 1.17 1.06 0.94 0.86 UART9 1.12 1.00 0.90 0.84 UCPD1 1.1 1.00 0.90 0.84 USART10 1.35 1.22 1.14 1.02 USART11 1.24 1.11 1.04 0.94 USART2 1.42 1.29 1.19 1.07 USART3 1.35 1.24 1.14 1.02 USART6 1.19 1.08 1.02 0.92 WWDG1 0.39 0.35 0.35 0.30 APB1 1.85 1.61 1.49 1.34 DS14258 Rev 5 μA/MHz 145/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 38. Peripheral current consumption in Sleep mode (continued) Bus APB2 APB3 IDD (typ) Peripheral Unit VOS0 VOS1 VOS2 VOS3 SAI1 1.13 0.99 0.93 0.82 SAI2 1.06 0.9 0.85 0.75 SPI1 1.03 0.91 0.85 0.75 SPI4 1.03 0.89 0.83 0.73 SPI6 1.03 0.9 0.85 0.74 TIM1 4.35 3.86 3.52 3.2 TIM15 2.08 1.84 1.69 1.54 TIM16 1.43 1.26 1.16 1.05 TIM17 1.44 1.25 1.17 1.05 TIM8 4.33 3.82 3.5 3.18 USART1 1.24 1.11 1.02 0.91 USBFS 2.53 2.22 2.04 1.84 APB2 1.04 0.92 0.84 0.77 I2C3 2.43 2.14 1.93 1.76 I2C4 2.37 2.08 1.89 1.73 LPTIM1 0.92 0.82 0.75 0.67 LPTIM3 0.88 0.77 0.71 0.65 LPTIM4 0.49 0.45 0.41 0.37 LPTIM5 0.84 0.76 0.69 0.63 LPTIM6 0.93 0.82 0.76 0.70 LPUART1 0.84 0.74 0.66 0.63 RTCAPB 1.93 1.70 1.54 1.38 SBS 0.45 0.41 0.38 0.34 SPI5 1.05 0.93 0.84 0.75 VREFBUF 0.08 0.08 0.07 0.05 APB3 0.64 0.57 0.53 0.48 μA/MHz uA/MHz Wake-up time from low-power modes The times given in Table 39 are measured starting from the wake-up event trigger up to the first instruction executed by the CPU: • for Stop or Sleep modes: the wake-up event is WFE. • WKUP (PA0) pin is used to wake-up from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD = 3.0 V. 146/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 39. Low-power mode wake-up timings(1) Symbol tWUSLEEP tWUSTOP tWUSTBY Parameter Conditions Wake-up time from Sleep mode Wake-up time from Stop mode Wake-up time from Standby mode Typ Max Unit Instruction cache enabled 15 16 Instruction cache disabled 15 16 CPU clock cycles SVOS3, HSI 64 MHz, flash memory in normal mode 4.0 4.8 SVOS3, HSI 64 MHz, flash memory in low-power mode 7.9 11.5 SVOS4, HSI 64 MHz, flash memory in normal mode 13.8 16.0 SVOS4, HSI 64 MHz, flash memory in low-power mode 17.7 21.9 SVOS5, HSI 64 MHz, flash memory in low-power mode 31.4 36.8 SVOS3, CSI 4 MHz, flash memory in normal mode 25.5 31.0 SVOS3, CSI 4 MHz, flash memory in low power mode 27.7 34.2 SVOS4, CSI 4 MHz, flash memory in normal mode 35.3 40.8 SVOS4, CSI 4 MHz, flash memory in low-power mode 37.5 44.0 SVOS5, CSI 4 MHz, flash memory in low-power mode 51.2 58.9 VCAP capacitors discharged 506.0 653.6 µs 1. Evaluated by characterization - Not tested in production. 5.3.8 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal must respect the Table 40 in addition to Table 58. The external clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer must be activated (refer to RM0481). Table 40. High-speed external user clock characteristics(1) Symbol Parameter fHSE_ext User external clock source frequency VHSEH Digital OSC_IN input high-level voltage VHSEL Digital OSC_IN input low-level voltage tw(HSEH) / tw(HSEL)(2) Digital OSC_IN input high or low time Conditions External digital/analog clock Min Typ Max Unit 4 25 50 MHz 0.7 VDD - VDD VSS - 0.3 VDD 7 - - V External digital clock External digital clock DS14258 Rev 5 ns 147/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 40. High-speed external user clock characteristics(1) (continued) Symbol Parameter Visw(HSEH) (VHSEH -VHSEL)(3) DuCyHSE tr(HSE) / tf(HSE) Conditions Analog low-swing OSC_IN peak-to-peak External analog low amplitude swing clock Analog low-swing OSC_IN duty cycle Analog low-swing OSC_IN rise and fall times Min Typ Max Unit 0.2 - 2/3 VDD V 45 50 55 % - 0.3 / fHSE_ext ns External analog low 0.05 / fHSE_ext swing clock, 10% to 90% 1. Specified by design - Not tested in production.. 2. The rise and fall times for a digital input signal are not specified, but the VHSEH and VHSEL conditions must be fulfilled anyway. 3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS. Figure 27. High-speed external clock source AC timing diagram VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32 ai17528b Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal must respect the Table 41 in addition to Table 58. The external clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer must be activated (refer to RM0481). Table 41. Low-speed external user clock characteristics(1) Symbol Parameter Conditions fLSE_ext User external clock source External digital/analog clock frequency VLSEH Digital OSC32_IN input high-level voltage VLSEL Digital OSC32_IN input low-level voltage 148/270 Min Typ Max Unit - 32.768 1000 kHz 0.7 VDD - VDD VSS - 0.3 VDD V External digital clock DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 41. Low-speed external user clock characteristics(1) (continued) Symbol Parameter tw(LSEH)/tw(LSEL) Digital OSC_IN input high or low time Visw_H Analog low-swing OSC_IN high-level voltage Visw_L ViswLSE (VLSEH -VLSEL) Conditions Min Typ Max Unit External digital clock 250 - - ns 0.6 - 1.225 0.35 - 0.8 0.5 - 0.875 45 50 55 % - 100 200 ns Analog low-swing OSC_IN low-level voltage External analog low swing Analog low-swing OSC_IN clock peak-to-peak amplitude Analog low-swing OSC_IN duty cycle DuCyLSE tr(LSE)/tf(LSE) Analog low-swing OSC_IN External analog low swing rise and fall times clock, 10% to 90% V 1. Specified by design - Not tested in production. Note: For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs” available from www.st.com. Figure 28. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32 ai17529b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 42. In the application, the resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DS14258 Rev 5 149/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 42. 4-50 MHz HSE oscillator characteristics(1) Symbol F RF Operating conditions(2) Min Typ Max Unit Oscillator frequency - 4 - 50 MHz Feedback resistor - - 200 - kΩ - - 10 VDD = 3 V, Rm = 20 Ω, CL = 10 pF at 4 MHz - 0.44 - VDD = 3 V, Rm = 20 Ω, CL = 10 pF at 8 MHz - 0.44 - VDD = 3 V, Rm = 20 Ω, CL = 10 pF at 16 MHz - 0.55 - VDD = 3 V, Rm = 20 Ω, CL = 10 pF at 32 MHz - 0.67 - VDD = 3 V, Rm = 20 Ω, CL = 10 pF at 48 MHz - 1.17 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) HSE current consumption Gmcritmax Maximum critical crystal gm tSU(HSE) (4) Startup time (3) mA 1. Evaluated by design - Not tested in production. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs”, available from www.st.com. Figure 29. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF OSC_OU T Bias controlled gain STM32 ai17530b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph is based on design simulation results obtained with typical external components specified in Table 43. In the application, the resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator 150/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 43. Low-speed external user clock characteristics(1) Symbol F IDD Conditions(2) Min Typ Max Unit - - 32.768 - kHz LSEDRV[1:0] = 00 Low drive capability - 246 - LSEDRV[1:0] = 01 Medium low drive capability - 333 - LSEDRV[1:0] = 10 Medium high drive capability - 462 - LSEDRV[1:0] = 11 High drive capability - 747 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - Parameter Oscillator frequency LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time nA µA/V s 1. Specified by design - Not tested in production. 2. Refer to the note and caution paragraphs below the table, and to AN2867 “Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs”. 3. Note: tSU(LSE) is the startup time measured from the moment it is enabled (by software) to when a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer For information on selecting the crystal, refer to AN2867 “Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs”, available from www.st.com. Figure 30. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kHz resonator RF OSC32_OUT Bias controlled gain STM32 CL2 ai17531d Note: An external resistor is not required between OSC32_IN and OSC32_OUT, and it is forbidden to add one. DS14258 Rev 5 151/270 238 Electrical characteristics 5.3.9 STM32H562xx and STM32H563xx Internal clock source characteristics The parameters given in Table 44 to Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 20. 48 MHz high-speed internal RC oscillator (HSI48) Table 44. HSI48 oscillator characteristics Symbol Parameter fHSI48 Conditions (1) HSI48 frequency TRIM(3) VDD = 3.3 V, TJ= 30 °C 47.5 User trimming step - USER TRIM COVERAGE(2) User trimming coverage DuCy(HSI48)(3) Duty cycle ACCHSI48_REL(3) Min Typ 48 Max 48.5 (1) Unit MHz - 0.175 0.250 ±4.70 ±5.6 - 45 - 55 % -4.5 - 4 % VDD = 3.0 to 3.6 V - 0.025 0.05 VDD = 1.71 to 3.6 V - 0.05 0.1 ±32 steps - Accuracy of the HSI48 oscillator over TJ = -40 to 130 °C temperature (reference is 30 °C) % ∆VDD(HSI48) HSI48 oscillator frequency drift with VDD (reference is 3.3 V) tsu(HSI48)(3) HSI48 oscillator start-up time - - 2.1 4.0 μs IDD(HSI48)(3) HSI48 oscillator power consumption - - 350 400 μA NT jitter(3) Next transition jitter accumulated jitter on 28 cycles - - ±0.15 - PT jitter(3) Paired transition jitter accumulated jitter on 56 cycles(4) - - ±0.25 - Typ Max % ns 1. Calibrated during manufacturing tests. 2. Evaluated by characterization - Not tested in production. 3. Specified by design - Not tested in production. 4. Jitter measurements are performed without clock sources activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 45. HSI oscillator characteristics(1) Symbol fHSI Parameter Frequency Conditions Min 63.7(2) 64.0(2) 64.3(2) VDD = 3.3 V, TJ = 30 °C Trimming is not a multiple of 32(3) - 0.24 0.32 -5.2 -1.8 - -1.4 -0.8 - Other trimmings are multiples of 32 (not including multiples of 64 and 128)(3) -0.6 -0.25 - - 45 - 55 Trimming is 128, 256, and 384(3) TRIM User trimming step DuCy(HSI) Duty cycle 152/270 Trimming is 64, 192, 320, and DS14258 Rev 5 488(3) Unit MHz % % STM32H562xx and STM32H563xx Electrical characteristics Table 45. HSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max -0.12 - 0.03 -1(4) - 1(4) -2(4) - 1(4) - 1.4 2.0 At 1% of target frequency - 4 8 At 1% of target frequency - - 4 - 300 450 μA Min Typ Max Unit 3.96(2) 4 4.04(2) MHz Trimming is not a multiple of 16 - 0.40 0.75 Trimming is not a multiple of 32 -4.75 -2.75 0.75 Other trimmings are a multiple of 32 (not including multiples of 64 and 128) -0.43 0.00 0.75 - 45 - 55 % % ∆VDD(HSI) Frequency drift with VDD VDD= 1.71 to 3.6 V (reference is 3.3 V) ∆TEMP(HSI) Frequency drift with VDD TJ= -20 to 105 °C (reference is 64 MHz) TJ= -40 to 130 °C tsu(HSI) Start-up time - tstab(HSI) Stabilization time IDD(HSI) Power consumption - Unit % μs μs 1. Specified by design - Not tested in production, unless otherwise specified. 2. Calibrated during manufacturing tests. 3. Trimming value of HSICAL[8:0]. 4. Guaranteed by characterization - Not tested in production. 4 MHz low-power internal RC oscillator (CSI) Table 46. CSI oscillator characteristics(1) Symbol fCSI TRIM DuCy(CSI) Parameter Frequency User trimming step VDD = 3.3 V, TJ = 30 °C Duty cycle ∆TEMP(CSI) Frequency drift over temperature ∆VDD(CSI) Frequency drift over VDD tsu(CSI) Conditions % TJ= 0 to 85 °C -3.7(3) - 4.5(3) TJ= -40 to TJ = 130 °C -11(3) - 7.5(3) % VDD= 1.71 to 3.6 V -0.06 - 0.06 % Start-up time - - 1 2 μs tstab(CSI) Stabilization time (to reach ± 3% of fCSI) - - - 4 cycle IDD(CSI) Power consumption - - 23 30 μA 1. Specified by design - Not tested in production, unless otherwise specified. 2. Calibrated during manufacturing tests. 3. Evaluated by characterization - Not tested in production. DS14258 Rev 5 153/270 238 Electrical characteristics STM32H562xx and STM32H563xx Low-speed internal (LSI) RC oscillator Table 47. LSI oscillator characteristics Symbol fLSI Parameter Frequency Conditions Min Typ Max VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1) TJ = -40 to 110 °C, VDD =1.71 to 3.6 V 29.76(2) - 33.6(2) - (2) TJ = -40 to 130 °C, VDD =1.71 to 3.6 V tsu(LSI) (3) (2) 29.4 Unit kHz 33.6 Start-up time - - 80 130 tstab(LSI)(3) Stabilization time (5% of final value) - - 120 170 IDD(LSI)(3) Power consumption - - 130 280 μs nA 1. Calibrated during manufacturing tests. 2. Evaluated by characterization - Not tested in production. 3. Specified by design - Not tested in production. 5.3.10 PLL characteristics The parameters given in Table 48 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 20. Table 48. PLL characteristics (wide VCO frequency range)(1) Symbol fPLL_IN fPLL_P_OUT fVCO_OUT tLOCK 154/270 Parameter Conditions Min Typ Max Unit PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % PLL multiplier output clock P, Q, R PLL VCO output PLL lock time VOS0 1 - 250(2) VOS1 1 - 200(2) VOS2 1 - 150(2) MHz VOS3 1 - 100(2) - 128 - 560(2) Normal mode - 45 100(3) 60 120(3) Sigma-delta mode (fPLL_IN ≥ 8 MHz) DS14258 Rev 5 - μs STM32H562xx and STM32H563xx Electrical characteristics Table 48. PLL characteristics (wide VCO frequency range)(1) (continued) Symbol Parameter Conditions Min Typ Max fVCO_OUT = 128 MHz - 60 - fVCO_OUT = 200 MHz - 50 - fVCO_OUT = 400 MHz - 20 - fVCO_OUT = 560 MHz - 15 - Normal mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz - ±0.2 - Normal mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz - ±0.8 - Sigma-delta mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz - ±0.2 - Sigma-delta mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz - ±0.8 - VDD - 330 420 VCORE - 630 - VDD - 155 230 VCORE - 170 - Cycle-to-cycle jitter Jitter Long term jitter IDD(PLL) PLL power consumption on VDD fVCO_OUT = 560 MHz fVCO_OUT = 128 MHz Unit ±ps % μA 1. Specified by design - Not tested in production, unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Evaluated by characterization - Not tested in production. Table 49. PLL characteristics (medium VCO frequency range) Symbol fPLL_IN fPLL_OUT fVCO_OUT tLOCK Parameter Conditions Min(1) Typ(1) Max(1) Unit PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % VOS0 1.17 - 210 VOS1 1.17 - 210 VOS2 1.17 - 160(2) PLL multiplier output clock P, Q, R PLL VCO output PLL lock time VOS3 1.17 - 88 - 150 - 420 Normal mode - 45 80(3) Sigma-delta mode DS14258 Rev 5 Forbidden MHz (2) μs 155/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 49. PLL characteristics (medium VCO frequency range) (continued) Symbol Parameter Cycle-to-cycle jitter Jitter Period jitter fVCO_OUT = 150 MHz - - 60 - fVCO_OUT = 200 MHz - - 40 - fVCO_OUT = 400 MHz - - 18 - fVCO_OUT = 420 MHz - - 15 - fVCO_OUT = 150 MHz fPLL_OUT = 50 MHz - 75 - - 25 - Normal mode fVCO_OUT = 400 MHz - ±0.2 - VDD - 275 360 VCORE - 450 - VDD - 160 240 VCORE - 165 - fVCO_OUT = 400 MHz Long term jitter IDD(PLL) Min(1) Typ(1) Max(1) Conditions PLL power consumption on VDD fVCO_OUT = 420 MHz fVCO_OUT = 150 MHz Unit ±ps % μA 1. Specified by design - Not tested in production, unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Evaluated by characterization - Not tested in production. 5.3.11 Memory characteristics Flash memory The characteristics are given at TJ = -40 to 130 °C unless otherwise specified. The devices are shipped to customers with the flash memory erased. Table 50. Flash memory characteristics Symbol IDD Min Typ Max(1) Word program(2) - 2.5 3.6 Sector erase - 1.8 4 Mass erase - 2.0 4 Parameter Supply current Conditions Unit mA 1. Specified by design - Not tested in production 2. Data are evaluated with a write of 50% of the programmed bits equal to 0. Table 51. Flash memory programming(1) Min(2) Typ Max(1) 128 bits (user area) - 31 100 16 bits (OTP area) - 31 100 Sector erase time (8 Kbytes) - 2 10 tME Mass erase time - 0.512 2.6 tBE Bank erase time - 0.256 1.3 1.71 - 3.6 Symbol tprog tERASE Vprog 156/270 Parameter Conditions Word program time Programming voltage DS14258 Rev 5 Unit µs ms s V STM32H562xx and STM32H563xx Electrical characteristics 1. Data are valid for program memory and high-cycling data memory. 2. Specified by design - Not tested in production. Table 52. Flash memory endurance and data retention Symbol Parameter Conditions Min(1) NPEND Endurance program memory TJ = -40 to +130 °C 10 NDEND Endurance data memory TJ = -40 to +130 °C 100 1 kcycle at TA = 125 °C 10 1 kcycles at TA = 85 °C 30 10 kcycles at TA = 55 °C 30 100 kcycle at TA = 125 °C 1 100 kcycles at TA = 85 °C 10 100 kcycles at TA = 55 °C 10 tPRET tDRET Program memory, data retention Data retention for data memory Unit kcycles Years 1. Evaluated by characterization - Not tested in production, unless otherwise specified. 5.3.12 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed (toggling two LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD), positive and negative, is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows to resume normal operation. The test results are given in Table 53. They are based on the EMS levels and classes defined in AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”. Table 53. EMS characteristics Symbol VFESD VFTB Parameter Voltage limits to apply on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to apply through 100 pF on VDD and VSS pins to induce a functional disturbance Conditions VDD = 3.3 V, TA = 25 °C, LQFP176-SMPS, frcc_cpu_ck = 250 MHz, conform to IEC 61000-4-2 Level/Class 2B 5A As a consequence, it is recommended to add a serial resistor (1 kΩ), located as close as possible to the MCU, to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). DS14258 Rev 5 157/270 238 Electrical characteristics STM32H562xx and STM32H563xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. Note that good EMC performance is highly dependent upon the user application, and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for its application. Software recommendations The software flow must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical data corruption (such as control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST or on the oscillator pins for 1 s. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015 “Software techniques for improving microcontrollers EMC performance”). Electromagnetic interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard, which specifies the test board and the pin loading. Table 54. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/250 MHz SEMI Peak level(1) VDD = 3.6 V, TA = 25 °C, LQFP176-SMPS package, conforming to IEC61967-2 0.1 to 30 MHz 21 30 to 130 MHz 22 130 MHz to 1 GHz 29 1 GHz to 2 GHz 21 EMI level 4 dBµV - 1. Refer to the EMI radiated test chapter of application note AN1709 “EMC design guide for STM8, STM32 and legacy MCUs” available from the ST website www.st.com. 158/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 5.3.13 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive pulse followed by a negative one) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards. Table 55. ESD absolute maximum ratings Symbol Ratings Conditions Electrostatic discharge VESD(HBM) voltage (human body model) VESD(CDM) TA = 25 °C, conforming to ANSI/ESDA/JEDEC JS-001 Maximum Unit value(1) Packages Class Packages with SMPS 1C 1000(2) Packages without SMPS 2 2000 C2a 500 Electrostatic discharge TA = 25 °C, conforming to All packages voltage (charge device model) ANSI/ESDA/JEDEC JS-002 V V 1. Evaluated by characterization - Not tested in production. 2. The electrostatic discharge is 2000 V for all pins, except VFBSMPS, for which the test fails at 2000 V and passes at 1600 V. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with the JESD78 IC latch-up standard. Table 56. Electrical sensitivities Symbol LU 5.3.14 Parameter Static latch-up class Conditions TJ = 130 °C, conforming to JESD78 Class II level A I/O current injection characteristics As a general rule, avoid current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) during the normal product operation. To give an indication of the device robustness when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the characterization. Functional susceptibility to I/O current injection While a simple application is executed, the device is stressed by injecting current into the I/O pins (one at the time) programmed in floating input mode, and checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain DS14258 Rev 5 159/270 238 Electrical characteristics STM32H562xx and STM32H563xx limit (higher than 5 LSB TUE), out of conventional limits (-5 / +0 µA range) of induced leakage current on adjacent pins, or other functional failures (such as reset, oscillator frequency deviation). The following table shows I/Os current injection susceptibility data. Negative/positive induced leakage currents are caused, respectively, by negative/positive injection. Table 57. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on pins PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2 0 0 Injected current on all other pins 5 N/A Unit mA 1. Evaluated by characterization - Not tested in production. 5.3.15 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL compliant (except for BOOT0). Note: For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for hardware settings and low-power consumption”, available on www.st.com. Table 58. I/O static characteristics(1) Symbol Parameter Conditions Min Typ Max - - 0.3 VDDIOx(2) - - 0.4 VDDIOx - 0.1(3) - - 0.19 VDDIOx + 0.1(3) 0.7 VDDIOx(2) - - 0.52 VDDIOx + 0.18(3) - - 0.17 VDDIOx + 0.6(3) - - - 250 - I/O input low level voltage except BOOT0 VIL I/O input low level voltage except BOOT0 1.08 V < VDD < 3.6 V BOOT0 I/O input low level voltage I/O input high level voltage except BOOT0 VIH I/O input high level voltage except BOOT0 1.08 V < VDD < 3.6 V BOOT0 I/O input high level voltage VHYS(3) 160/270 TT_xx, FT_xxx and NRST I/O input hysteresis 1.08 V < VDD < 3.6 V BOOT0 I/O input hysteresis 1.71 V < VDD < 3.6 V Unit V V mV DS14258 Rev 5 - 200 - STM32H562xx and STM32H563xx Electrical characteristics Table 58. I/O static characteristics(1) (continued) Symbol Parameter FT_xx input leakage current(3) Ileak(4) TT_xx input leakage current BOOT0 RPU Weak pull-up equivalent resistor(6) RPD Weak pull-down equivalent resistor(6) CIO I/O pin capacitance Conditions Min Typ Max 0 < VIN ≤ Max(VDDXXX)(7) - - ±200 Max(VDDXXX) < VIN ≤ Max(VDDXXX) + 1 V) (5)(7) - - 2500 Max(VDDXXX) < VIN ≤ 5.5 V (5)(7) - - 750 0 < VIN ≤ Max(VDDXXX) (7) - - ±200 0 < VIN ≤ VDDOX - - 15 VIN = VSS 30 40 50 Unit nA kΩ VIN = VDD (7) - 30 40 50 - 5 - pF 1. VDDIOx represents VDD or VDDIO2. 2. Compliant with CMOS requirements. 3. Specified by design - Not tested in production. 4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max). 5. VIN must be lower than Max(VDDXXX) + 3.6 V. 6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10%). 7. Max(VDDXXX) is the maximum value of all the I/O supplies. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in the following figure. DS14258 Rev 5 161/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 31. VIL/VIH for all I/Os except BOOT0 3 2.5 Minimum required logic level 1 zone TTL standard requirement VIHmin = 2V 2 xV DDIO VIN (V) 1.5 Teste Based OS n (CM uctio rod d in p VIHmin ulation ard stand = 0.52 nt) V IH ireme requ VDDIO + = 0.7 min 0.18 Undefined input range on sim 1 Based on simulation VILmax = 0.4 VDDIO - 0.1 ment) VILmax dard require S stan tion (CMO ed in produc 0.5 TTL standard requirement VILmax = 0.8V = 0.3 VDDIO Test Minimum required logic level 0 zone 0 1.6 1.8 2.0 2.2 Device characteristics 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDDIO (V) Tested thresholds MSv47925V1 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins that can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 18). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 18). Output voltage levels Unless otherwise specified, the parameters given in Table 59 and Table 61 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 20. All I/Os are CMOS and TTL compliant. 162/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 59. Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8 Symbol Parameter Conditions(1) Min Max VOL Output low level voltage CMOS port(2), IIO = 8 mA 2.7 V ≤ VDD ≤ 3.6 V - 0.4 VOH Output high level voltage CMOS port(2), IIO = -8 mA 2.7 V ≤ VDD ≤ 3.6 V VDD− 0.4 - VOL(3) Output low level voltage TTL port(2), IIO = 8 mA 2.7 V ≤ VDD ≤ 3.6 V - 0.4 VOH(3) Output high level voltage TTL port(2), IIO = -8 mA 2.7 V ≤ VDD ≤ 3.6 V 2.4 - VOL(3) Output low level voltage IIO = 20 mA 2.7 V ≤ VDD ≤ 3.6 V - 1.3 VOH(3) Output high level voltage IIO = -20 mA 2.7 V ≤ VDD ≤ 3.6 V VDD - 1.3 - VOL(3) Output low level voltage IIO = 4 mA 1.71 V ≤ VDD ≤ 3.6 V - 0.4 VOH (3) Output high level voltage IIO = -4 mA 1.71 V ≤ VDD 3.0V) • For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 95 MHz at 15 pF • For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 90 MHz at 20 pF Figure 45. SDRAM read access waveforms (CL = 1) FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS th(SDCLKL_NCAS) td(SDCLKL_NCAS) FMC_SDNCAS FMC_SDNWE tsu(SDCLKH_Data) th(SDCLKH_Data) Data1 FMC_D[31:0] Data2 Datai Datan MS32751V2 Table 84. SDRAM read timings(1) Symbol Parameter Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck + 0.5 tsu(SDCLKH _Data) Data input setup time 3 - th(SDCLKH_Data) Data input hold time 0.5 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - 1. Evaluated by characterization - Not tested in production. 192/270 Min DS14258 Rev 5 Unit ns STM32H562xx and STM32H563xx Electrical characteristics Table 85. LPSDR SDRAM read timings(1) Symbol Parameter Min Max Unit tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck + 0.5 tsu(SDCLKH_Data) Data input setup time 3 - th(SDCLKH_Data) Data input hold time 0.5 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 1.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - ns 1. Evaluated by characterization - Not tested in production. Figure 46. SDRAM write access waveforms FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS td(SDCLKL_NCAS) th(SDCLKL_NCAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_SDNCAS FMC_SDNWE td(SDCLKL_Data) FMC_D[31:0] Data1 Data2 Datai Datan th(SDCLKL_Data) td(SDCLKL_NBL) FMC_NBL[3:0] MS32752V2 DS14258 Rev 5 193/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 86. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5 td(SDCLKL _Data) Data output valid time - 1 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2 td(SDCLKL_SDNWE) SDNWE valid time - 1 th(SDCLKL_SDNWE) SDNWE hold time 0 - td(SDCLKL_ SDNE) Chip select valid time - 1 th(SDCLKL-_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Evaluated by characterization - Not tested in production. Table 87. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck+0.5 td(SDCLKL _Data) Data output valid time - 1 th(SDCLKL _Data) Data output hold time 0. - td(SDCLKL_Add) Address valid time - 2 td(SDCLKL-SDNWE) SDNWE valid time - 1 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - 1. Evaluated by characterization - Not tested in production. 194/270 DS14258 Rev 5 Unit ns STM32H562xx and STM32H563xx 5.3.19 Electrical characteristics Octo-SPI interface characteristics Unless otherwise specified, the parameters given in Table 88 and Table 89 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Refer to Section 5.3.15 for more details on the input/output alternate function characteristics. Table 88. OCTOSPI characteristics in SDR mode(1)(2) Symbol F(CLK) Parameter Clock frequency tw(CLKH) Clock high and low time, even division t w(CLKL) tw(CLKH) tw(CLKL) Clock high and low time, odd division Conditions Min Typ Max(3) 1.71 V < VDD < 1.9 V, CL = 15 pF - - 110 1.71 V < VDD < 3.6 V, CL =15 pF - - 150 t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5 t(CLK) / 2 - 0.5 - t(CK) / 2 + 0.5 (n / 2) * t(CLK) / (n + 1) - 0.5 - (n / 2) * t(CLK) / (n + 1) + 0.5 (n / 2 + 1) * t(CLK) / (n + 1) - 0.5 - (n / 2 + 1) * t(CLK) / (n + 1) + 0.5 PRESCALER[7:0] = n (= 0, 1, 3, 5,..., 255) PRESCALER[7:0] = n (= 2, 4, 6, ..., 254) Unit MHz ts(IN) Data input setup time - 4 - - th(IN) Data input hold time - 1 - - tv(OUT) Data output valid time - - 0.5 1 th(OUT) Data output hold time - 0 - - ns 1. All values apply to Octal- and Quad-SPI mode. 2. Evaluated by characterization - Not tested in production. 3. At VOS1 these values are degraded by up to 5%. Figure 47. OCTOSPI SDR read/write timing diagram tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tv(OUT) Data output th(OUT) D1 D0 ts(IN) Data input D0 D2 th(IN) D1 D2 MSv36878V3 DS14258 Rev 5 195/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 89. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3) Symbol FCLK Parameter OCTOSPI clock frequency tw(CLKH) OCTOSPI clock high and low time t w(CLKL) tw(CLKH) tw(CLKL) OCTOSPI clock high and low time Conditions Min Typ Max 1.71 V < VDD < 1.9 V, CL = 15 pF - - 100(4) 2.7 V < VDD < 3.6 V, CL = 15 pF - - 125(4) t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5 t(CLK) / 2 - 0.5 - t(CLK) / 2 + 0.5 (n / 2) * t(CLK)/ (n + 1) - 0.5 - (n / 2) * t(CLK)/ (n + 1) + 0.5 - (n / 2 + 1) * t(CLK)/ (n + 1) + 0.5 PRESCALER[7:0] = n (= 0, 1, 3, 5, .., 255) MHz PRESCALER[7:0] = n (= 2, 4, 6, 8, ..., 254) (n / 2 + 1) * t (CLK)/ (n + 1) - 0.5 tv(CLK) Clock valid time - - - t(CLK) +0.5 tsr(IN), tsf(IN) Data input setup time - 4 - - thr(IN), thf(IN) Data input hold time - 1.5 - - DHQC = 0 - 2.5 3.5 DHQC = 1, Prescaler [7:0] = 1, 2... - t(CLK) / 4 + 0.5 t(CLK) / 4 + 1 DHQC = 0 1.5 - - DHQC = 1, Prescaler [7:0] = 1, 2... t(CLK) / 4 - 1 - - tvr(OUT) tvf(OUT) Data output valid time thr(OUT) thf(OUT) Data output hold time 1. All values apply to Octal and Quad-SPI mode. 2. Evaluated by characterization - Not tested in production. 3. Delay block bypassed. 4. DHQC must be set to reach the mentioned frequency. 196/270 Unit DS14258 Rev 5 ns ns ns STM32H562xx and STM32H563xx Electrical characteristics Table 90. OCTOSPI characteristics in DTR mode (with DQS) / HyperBus(1)(2) Symbol FCLK tw(CLKH) tw(CLKL) tw(CLKH) tw(CLKL) Parameter OCTOSPI clock frequency OCTOSPI clock high and low time OCTOSPI clock high and low time Conditions Min Typ Max 1.71 V < VDD < 1.9 V, CL = 15 pF - - 125(3)(4) 2.7 V < VDD < 3.6 V, CL = 15 pF - - 125(3)(5) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 (n/2)*t(CLK)/ (n+1) - 0.5 - (n/2)*t(CLK)/ (n+1) + 0.5 (n/2+1)*t(CLK)/ (n+1) - 0.5 - (n/2+1)*t(CLK)/ (n+1) + 0.5 PRESCALER[7:0] = n = (0, 1, 3, 5, …, 255) PRESCALER[7:0] = n = (2, 4, 6, 8, …, 254) MHz tv(CLK) Clock valid time - - - t(CLK) + 2 th(CLK) Clock hold time - t(CLK)/2 - 1 - - tODr(CLK)(5) CLK, NCLK crossing level on CLK rising edge VDD = 1.8 V 890 - 1300 tODf(CLK)(5) CLK, NCLK crossing level on CLK falling edge VDD = 1.8 V 790 - 1080 Chip select high time - 3 * t(CLK) - - tv(DQ) Data input valid time - 3 - - tv(DS) Data strobe input valid time - 1 - - th(DS) Data strobe input hold time - 0 - - Data strobe output valid time - - - 3 * t(CLK) tsr(DQ), tsf(DQ) Data input setup time - -0.5 - - thr(DQ), thf(DQ) Data input hold time - 2 - - DHQC = 0 - 2.5 3.5 DHQC = 1, all prescaler values except 0 - t(CLK)/4 + 0.5 t(CLK)/4 + 1 DHQC = 0 1.5 - - DHQC = 1, all prescaler values except 0 t(CLK)/4 - 1 - - tvr(OUT) tvf(OUT) thr(OUT) thf(OUT) Data output valid time Data output hold time ns mV tw(CS) tv(RWDS) Unit ns ns 1. Evaluated by characterization - Not tested in production. 2. Delay block activated. 3. Maximum frequency value are given for a maximum RWDS to DQ skew of ± 1.0 ns. 4. DHQC must be set to reach the mentioned frequency. 5. It is recommended that PF10/PB5, PB4/PB5 and PA3/PB5 are in line with crossing specification. DS14258 Rev 5 197/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 48. OCTOSPI timing diagram - DTR mode tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tvf(OUT) thr(OUT) Data output D0 tvr(OUT) D1 D2 thf(OUT) D3 D4 tsf(IN) thf(IN) Data input D0 D1 D5 tsr(IN) thr(IN) D2 D4 D3 D5 MSv36879V4 Figure 49. OCTOSPI HyperBus clock tr(CLK) tf(NCLK) tw(CLKH) tw(NCLKL) t(CLK) t(NCLK) tw(CLKL) tw(NCLKH) tf(CLK) tr(NCLK) NCLK VOD(CLK) CLK MSv47732V3 Figure 50. OCTOSPI HyperBus read tw(CS) NCS tv(CLK) th(CLK) t ACC= Initial access CLK, NCLK tv(RWDS) tv(DS) th(DS) RWDS tv(OUT) DQ[7:0] 47:40 39:32 th(OUT) 31:24 23:16 Latency count 15:8 7:0 Command address Host drives DQ[7:0] and the memory drives RWDS. 198/270 DS14258 Rev 5 tv(DQ) ts(DQ) th(DQ) Dn A Dn+1 A Dn B Dn+1 B Memory drives DQ[7:0] and RWDS. MSv47733V3 STM32H562xx and STM32H563xx Electrical characteristics Figure 51. OCTOSPI HyperBus write tw(CS) NCS Read write recovery Access latency tv(CLK) th(CLK) CLK, NCLK tv(RWDS) High = 2x latency count RWDS tv(OUT) th(OUT) tv(OUT) th(OUT) Low = 1x latency count Latency count DQ[7:0] tv(OUT) th(OUT) 47:40 31:24 39:32 23:16 15:8 Dn A 7:0 Command address Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and RWDS. Host drives DQ[7:0] and the memory drives RWDS. MSv47734V3 5.3.20 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 91 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20, with the following configuration: Table 91. Delay block characteristics 5.3.21 Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 750 1100 1700 ps t∆ Unit delay - 38 44 54 ps DCMI interface characteristics Unless otherwise specified, the parameters given in Table 92 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits • Capacitive load CL = 30 pF • Measurement points done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling VOS0 selected DS14258 Rev 5 199/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 92. DCMI characteristics(1) Symbol Min Max Unit Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 - Pixel clock input - 100 MHz Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2.5 - th(DATA) Data hold time 2 - 2.5 - 1.5 - DCMI_PIXCLK DPIXEL Parameter tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times th(HSYNC), th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times ns 1. Evaluated by characterization - Not tested in production. Figure 52. DCMI timing diagrams 1/DCMI_PIXCLK DCMI_PIXCLK tsu(HSYNC) th(HSYNC) DCMI_HSYNC tsu(VSYNC) th(HSYNC) DCMI_VSYNC tsu(DATA) th(DATA) DATA[0:13] MS32414V2 5.3.22 PSSI interface characteristics Unless otherwise specified, the parameters given in Table 92 and Table 93 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20 and Section 5.3.1, with the following configuration: 200/270 • PSSI_PDCK polarity: falling • PSSI_RDY and PSSI_DE polarity: low • Bus width: 16 lines • DATA width: 32 bits • Capacitive load CL= 30 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling VOS0 selected DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 93. PSSI transmit characteristics(1) Symbol Parameter Conditions Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK - - 0.4 - (2) 2.7 V ≤ VDD ≤ 3.6 V - 1.71 V ≤ VDD ≤ 3.6 V - 86 30 70 2.7 V ≤ VDD ≤ 3.6 V - 11 1.71 V ≤ VDD ≤ 3.6 V - 11.5 Data output hold time 5.5 - tov((DE) DE output valid time - 11.5 toh(DE) DE output hold time 5.5 - tsu(RDY) RDY input setup time 0.5 - th(RDY) RDY input hold time 0.5 - Min Max Unit - 0.4 - 1.71 V ≤ VDD ≤ 3.6 V - 100 MHz - 30 70 % PSSI_PDCK PSSI clock input Dpixel PSSI clock input duty cycle tov(DATA) Data output valid time toh(DATA) 1.71 V ≤ VDD ≤ 3.6 V 90 MHz % ns 1. Evaluated by characterization - Not tested in production. 2. This maximal frequency does not consider receiver setup and hold timings. Table 94. PSSI receive characteristics(1) Symbol PSSI_PDCK Dpixel Parameter Conditions Frequency ratio PSSI_PDCK/fHCLK PSSI clock input PSSI clock input duty cycle tsu(DATA) Data input setup time 2 - th(DATA) Data input hold time 2.5 - tsu((DE) DE input setup time 1.5 - th(DE) DE input hold time 2 - 1.71 V ≤ VDD ≤ 3.6 V tov(RDY) RDY output valid time - 16.5 toh(RDY) RDY output hold time 5.5 - ns 1. Evaluated by characterization - Not tested in production. DS14258 Rev 5 201/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 53. PSSI transmit timing diagram tc(PDCK) PSSI_PDCK (input) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) CKPOL = 0 CKPOL = 1 tov(DATA) PSSI_RDY (input) PSSI_DE (output) PSSI D[15:0] (output) Invalid data OUT toh(DATA) Valid data OUT Invalid data OUT DEPOL = 0 tov(DE) toh(DE) DEPOL = 1 RDYPOL = 0 th(RDY) tsu(RDY) RDYPOL = 1 MSv65388V1 Figure 54. PSSI receive timing diagram tc(PDCK) PSSI_PDCK (input) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) CKPOL = 0 CKPOL = 1 tsu(DATA) thDATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN tsu(DE) PSSI_DE (output) th(DE) DEPOL = 0 DEPOL = 1 PSSI_RDY (input) tov(RDY) toh(RDY) RDYPOL = 0 RDYPOL = 1 MSv65389V1 202/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 5.3.23 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 95 are derived from tests performed under the ambient temperature, fHCLK frequency, and VDDA supply voltage conditions summarized in Table 20. Table 95. 12-bit ADC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage for ADC ON - 1.62 - 3.6 VREF+ Positive reference voltage - 1.62 - VDDA V VREF- Negative reference voltage - fadc_ker_ck(3) Clock frequency 1.62 V ≤ VDDA ≤ 3.6 V MHz Continuous mode Resolution = 12 bits Single or Discontinuous mode Sampling rate for fast channels (VIN[0:5]) Continuous mode Resolution = 10 bits fS(4) with RAIN = 47 Ω Single or Discontinuous mode and CPCB = 22 pF VSSA Resolution = 6 bits Resolution = 10 bits Resolution = 8 bits 75 - 5.00 - 1.6V ≤ VDDA ≤ 3.6V fadc_ker_ck = 70 MHz - 4.66 - 2.4V ≤ VDDA ≤ 3.6V fadc_ker_ck = 60 MHz - 4.00 - 1.6V ≤ VDDA ≤ 3.6V fadc_ker_ck = 50 MHz - 3.33 - - 5.77 - - 5.77 - - 5.00 - - 6.82 - - 8.33 - - 2.30 - - 2.70 - fadc_ker_ck = 50 MHz - 4.50 - fadc_ker_ck = 50 MHz - 5.50 - 1.6V ≤ VDDA ≤ 3.6V fadc_ker_ck = 75 MHz 2.4V ≤ VDDA ≤ 3.6V -40°C ≤ TJ ≤ 130°C 1.6V ≤ VDDA ≤ 3.6V Resolution = 12 bits Sampling rate for slow channels - fadc_ker_ck = 75 MHz Resolution = 8 bits All modes 1.5 1.8V ≤ VDDA ≤ 3.6V 1.6V ≤ VDDA ≤ 3.6V Unit fadc_ker_ck = 65 MHz SMP =2.5 MSPS fadc_ker_ck = 75 MHz fadc_ker_ck = 35 MHz All modes(5) 1.6V ≤ VDDA ≤ 3.6V Resolution = 6 bits tTRIG External trigger period Resolution = 12 bits - - 15 VAIN(2) Conversion voltage range - 0 - VREF+ VCMIV Common mode input voltage - VREF / 2 − 10% VREF / 2 VREF / 2 + 10% 1/fadc_ker_ck V DS14258 Rev 5 203/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 95. 12-bit ADC characteristics(1)(2) (continued) Symbol RAIN(6) Parameter External input impedance Conditions Min Typ Max Resolution = 12 bits, TJ = 130°C (tolerance 4 LSBs) - - 321 Resolution = 12 bits, TJ = 125°C - - 220 Resolution = 10 bits, TJ = 130°C - - 1039 Resolution = 10 bits, TJ = 125°C - - 2100 Resolution = 8 bits, TJ = 130°C - - 6327 Resolution = 8 bits, TJ = 125°C - - 12000 Resolution = 6 bits, TJ = 130°C - - 47620 Resolution = 6 bits, TJ = 125°C - - 80000 Unit Ω CADC Internal sample and hold capacitor - - 3 - pF tADCVREG_ STUP LDO startup time - - 5 10 µs tSTAB Power-up time LDO already started 1 - - Conversion cycle tOFF_CAL Offset calibration time CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 tLATR Trigger conversion latency for regular and injected channels without aborting the conversion CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 Trigger conversion latency for regular and injected channels when a regular conversion is aborted CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 tS Sampling time - 2.5 - 640.5 tCONV Total conversion time (including sampling) N-bits resolution tS + 0.5 +N - - fs = 5 MSPS - 600 - IDDA_D(ADC) Consumption on VDDA and VREF, differential mode tLATRINJ IDDA_SE(ADC) Consumption on VDDA and VREF, singleended mode 1335 1/fadc_ker_ck fs = 1 MSPS - 190 - fs = 0.1 MSPS - 50 - fs = 5 MSPS - 500 - fs = 1 MSPS - 150 - fs = 0.1 MSPS - 50 - fadc_ker_ck = 75 MHz - 265 - 175 - µA fadc_ker_ck = 50 MHz IDD(ADC) Consumption on VDD fadc_ker_ck = 25 MHz - 90 - fadc_ker_ck = 12.5 MHz - 45 - fadc_ker_ck = 6.25 MHz - 22 - fadc_ker_ck = 3.125 MHz - 11 - 1. Specified by design - Not tested in production. 2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches). 204/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics 3. This frequency is the analog ADC specification, it must respect the value in Table 21. 4. These values are valid on BGA packages. 5. Depending upon the package, VREF+ can be internally connected to VDDA, and VREF- to VSSA. 6. The tolerance is two LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified. Table 96. Minimum sampling time versus RAIN(1)(2) Minimum sampling time (s) Resolution 12 bits 10 bits RAIN (Ω) Fast channel Slow channel(3) 47 3.75E-08 6.12E-08 68 3.94E-08 6.25E-08 100 4.36E-08 6.51E-08 150 5.11E-08 7.00E-08 220 6.54E-08 7.86E-08 330 8.80E-08 9.57E-08 470 1.17E-07 1.23E-07 680 1.60E-07 1.65E-07 47 3.19E-08 5.17E-08 68 3.35E-08 5.28E-08 100 3.66E-08 5.45E-08 150 4.35E-08 5.83E-08 220 5.43E-08 6.50E-08 330 7.18E-08 7.89E-08 470 9.46E-08 1.00E-07 680 1.28E-07 1.33E-07 1000 1.81E-07 1.83E-07 1500 2.63E-07 2.63E-07 2200 3.79E-07 3.76E-07 3300 5.57E-07 5.52E-07 DS14258 Rev 5 205/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 96. Minimum sampling time versus RAIN(1)(2) (continued) Minimum sampling time (s) Resolution 8 bits 6 bits RAIN (Ω) Fast channel Slow channel(3) 47 2.64E-08 4.17E-08 68 2.76E-08 4.24E-08 100 3.02E-08 4.39E-08 150 3.51E-08 4.66E-08 220 4.27E-08 5.13E-08 330 5.52E-08 6.19E-08 470 7.17E-08 7.72E-08 680 9.68E-08 1.00E-07 1000 1.34E-07 1.37E-07 1500 1.93E-07 1.94E-07 2200 2.76E-07 2.74E-07 3300 4.06E-07 4.01E-07 4700 5.73E-07 5.62E-07 6800 8.21E-07 7.99E-07 10000 1.20E-06 1.17E-06 15000 1.79E-06 1.74E-06 47 2.14E-08 3.16E-08 68 2.23E-08 3.21E-08 100 2.40E-08 3.31E-08 150 2.68E-08 3.52E-08 220 3.13E-08 3.87E-08 330 3.89E-08 4.51E-08 470 4.88E-08 5.39E-08 680 6.38E-08 6.79E-08 1000 8.70E-08 8.97E-08 1500 1.23E-07 1.24E-07 2200 1.73E-07 1.73E-07 3300 2.53E-07 2.49E-07 4700 3.53E-07 3.45E-07 6800 5.04E-07 4.90E-07 10000 7.34E-07 7.11E-07 15000 1.09E-06 1.05E-06 1. Specified by design - Not tested in production. 2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V. 206/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics 3. Slow channels correspond to all ADC inputs except for the fast channels. Figure 55. ADC conversion timing diagram CLK Mux 1/2 Sampling(1) 15 14 SMP 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Number of CLK clock cycles = ADC resolution / 2 Total conversion time: 0.5 +Tsamp + N/2 1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details). Table 97. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Conditions Min Typ Max Fast and slow channels Single ended - ±3.5 ±12 Differential - ±2.5 ±7.5 - Single ended - ±3 ±5.5 - Differential - ±2 ±3.5 - Single ended - ±3.5 ±11 - Differential ±2.5 ±7 - Single ended - ±0.75 +2/-1 - Differential - ±0.75 +2/-1 Fast and slow channels Single ended - ±2 ±6.5 Differential - ±1 ±4 Single ended - 10.8 - Differential - 11.5 - Single ended - 68 - Differential - 71 - Single ended - 70 - Differential - 72 - Single ended - -70 - Differential - -80 - 1. Evaluated by characterization for BGA packages. The values for LQFP package can differ. Not tested in production. 2. ADC DC accuracy values are measured after internal calibration in continuous mode. DS14258 Rev 5 Unit LSB Bits dB 207/270 238 Electrical characteristics Note: STM32H562xx and STM32H563xx ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins, which may potentially inject negative currents. Figure 56. ADC accuracy characteristics VREF+ [1LSB = 2n Output code VDDA (or )] 2n EG (1) Example of an actual transfer curve (2) Ideal transfer curve (3) End-point correlation line 2n-1 2n-2 2n-3 (2) (3) ET EL EO ED (2n/2n)*VREF+ (2n-1/2n)*VREF+ (2n-2/2n)*VREF+ (2n-3/2n)*VREF+ (7/2n)*VREF+ (6/2n)*VREF+ (5/2n)*VREF+ (4/2n)*VREF+ (3/2n)*VREF+ 1 LSB ideal (2/2n)*VREF+ 0 VSSA (1) (1/2n)*VREF+ 7 6 5 4 3 2 1 n = ADC resolution ET = total unadjusted error: maximum deviation between the actual and ideal transfer curves EO = offset error: maximum deviation between the first actual transition and the first ideal one EG = gain error: deviation between the last ideal transition and the last actual one ED = differential linearity error: maximum deviation between actual steps and the ideal one EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line VREF+ (VDDA) MSv19880V6 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. 5. EO = Offset error: deviation between the first actual transition and the first ideal one. 6. EG = Gain error: deviation between the last ideal transition and the last actual one. 7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. 8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 57. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function VDDA(4) VREF+(4) Sample-and-hold ADC converter I/O analog switch RAIN(1) RADC Converter VAIN Cparasitic(2) Ilkg(3) VSS CADC Sampling switch with multiplexing VSS VSSA MSv67871V3 1. Refer to Table 95 for the values of RAIN, and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the 208/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics pad capacitance (refer to Table 58). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 3. Refer to Table 58 for the value of Ilkg. 4. Refer to Figure 20. General PCB design guidelines It is recommended to perform power supply decoupling as shown in Figure 58 or Figure 59, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors must be ceramic (good quality), and placed as close as possible to the chip. Figure 58. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+(1) 1 μF // 100 nF VDDA 1 μF // 100 nF VSSA/VREF-(1) MSv50648V2 1. VREF+ input is not available on all packages (refer to Table 14), VREF- is available only on UFBGA176+25, UFBGA169 with SMPS, LQFP100, UFBGA169, and UFBGA176+25 packages. When VREF+ is not available, it is internally connected to VSSA. DS14258 Rev 5 209/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 59. Power supply and reference decoupling (VREF+ connected to VDDA) STM32 VREF+/VDDA(1) 1 μF // 100 nF VREF-/VSSA(1) MSv50649V1 1. VREF+ input is not available on all packages (refer to Table 14), VREF- is available only on UFBGA176+25, UFBGA169 with SMPS, LQFP100, UFBGA169, and UFBGA176+25 packages. When VREF- is not available, it is internally connected to VSSA. If VREF- is available and connected to VDDA, refer to Figure 20 for more detailsIf. 5.3.24 DAC characteristics Table 98. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.8 - VDDA VREF- Negative reference voltage - - VSSA - Connected to VSSA 5 - - Connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.8 VDD = 2.0 V - - 18.7 DAC output buffer OFF - - 50 pF Sample and Hold mode - 0.1 1 µF DAC output buffer ON 0.2 - VDDA −0.2 V DAC output buffer OFF 0 - VREF+ RL RO Resistive load DAC output buffer ON Output impedance DAC output buffer OFF RBON Output impedance sample and hold mode, output buffer ON DAC output buffer ON RBOFF Output impedance sample and hold mode, output buffer OFF DAC output buffer OFF CL CSH VDAC_OUT 210/270 Capacitive load Voltage on DAC_OUT output DS14258 Rev 5 V kΩ kΩ kΩ STM32H562xx and STM32H563xx Electrical characteristics Table 98. DAC characteristics(1) (continued) Symbol Parameter Settling time (full scale: for a 12-bit code transition between the lowest and the tSETTLING highest input codes when DAC_OUT reaches the final value of ±0.5LSB, ±1LSB, ±2LSB, ±4LSB, ±8LSB) Conditions Min Typ Max ±0.5 LSB - 2.05 3 ±1 LSB - 1.97 2.87 ±2 LSB - 1.67 2.84 ±4 LSB - 1.66 2.78 ±8 LSB - 1.65 2.7 Normal mode, DAC output buffer OFF, ±1LSB CL= 10 pF - 1.7 2 5 7.5 Normal mode, DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ Unit µs Wake-up time from off state (setting the ENx bit in the DAC control register) until the final value of ±1LSB is reached Normal mode, DAC output buffer ON, CL ≤ 50 pF, RL = 5 kΩ - Normal mode, DAC output buffer OFF, CL ≤ 10 pF - 2 5 PSRR DC VDDA supply rejection ratio Normal mode, DAC output buffer ON, CL ≤ 50 pF, RL = 5 kΩ - -80 -28 MODE_V12 = 100/101 (BUFFER ON) - 0.7 2.6 tSAMP Sampling time in Sample and Hold mode, CL= 100 nF (code transition between the lowest and the highest input code when DAC_OUT reaches the ±1LSB final value) MODE_V12 = 110 (BUFFER OFF) - 11.5 18.7 MODE_V12=111(3) (INTERNAL BUFFER OFF) - 0.3 0.6 µs tWAKEUP (2) µs dB ms Ileak Output leakage current - - - (4) nA CIint Internal sample and hold capacitor - 1.8 2.2 2.6 pF tTRIM Middle code offset trim time Minimum time to verify each code 50 - - µs Voffset Middle code offset for 1 trim code step VREF+ = 3.6 V - 850 - VREF+ = 1.8 V - 425 - No load, middle code (0x800) - 360 - No load, worst code (0xF1C) - 490 - No load, middle/ worst code (0x800) - 20 - - 360*TON/ (TON+TOFF)(5) - DAC output buffer ON DAC quiescent consumption IDDA(DAC) from VDDA DAC output buffer OFF Sample and Hold mode, CSH = 100 nF DS14258 Rev 5 µV µA 211/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 98. DAC characteristics(1) (continued) Symbol Parameter Conditions DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ Min Typ Max No load, middle code (0x800) - 170 - No load, worst code (0xF1C) - 170 - No load, middle/ worst code (0x800) - 160 - Sample and Hold mode, buffer ON, CSH = 100 nF (worst code) - 170*TON/ (TON+TOFF)(5) - Sample and Hold mode, buffer OFF, CSH = 100 nF (worst code) - 160*TON/ (TON+TOFF)(5) - DAC output buffer OFF Unit µA 1. Specified by design - Not tested in production, unless otherwise specified. 2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value). 3. DACx_OUT pin is not connected externally (internal connection only). 4. Refer to Table 58. 5. TON is the refresh phase duration, TOFF is the hold phase duration. Refer to the reference manual for more details. Table 99. DAC accuracy(1) Symbol DNL - INL Offset Offset1 Parameter Min Typ Max Differential non linearity(2) DAC output buffer ON −2 - 2 DAC output buffer OFF −2 - 2 Monotonicity 10 bits - - - DAC output buffer ON, CL≤50 pF, RL≥5 kΩ −4 - 4 DAC output buffer OFF, CL ≤ 50 pF, no RL −4 - 4 VREF+ = 3.6 V - - ±12 VREF+ = 1.8 V - - ±25 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±8 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±5 VREF+ = 3.6 V - - ±5 VREF+ = 1.8 V - - ±7 Integral non linearity(3) Offset error at code 0x800 (3) Offset error at code 0x001(4) Offset error at code OffsetCal 0x800 after factory calibration 212/270 Conditions DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ DS14258 Rev 5 Unit LSB - LSB STM32H562xx and STM32H563xx Electrical characteristics Table 99. DAC accuracy(1) (continued) Symbol Gain TUE TUECal SNR THD SINAD ENOB Parameter Gain error(5) Total unadjusted error Conditions Min Typ Max DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ - - ±1 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±1 DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ - - ±30 Signal-to-noise ratio(6) Total harmonic distortion(6) Signal-to-noise and distortion ratio(6) % DAC output buffer OFF, CL≤50 pF, no RL Total unadjusted error DAC output buffer ON, after calibration CL≤50 pF, RL ≥5 kΩ ±12 - - ±23 DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ, 1 kHz, BW = 500 kHz - 67.8 - DAC output buffer OFF, CL ≤ 50 pF, no RL,1 kHz, BW = 500 kHz - 67.8 - DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ, 1 kHz - −78.6 - DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - −78.6 - DAC output buffer ON, CL≤50 pF, RL ≥5 kΩ, 1 kHz - 67.5 - DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 67.5 - DAC output buffer ON, CL≤50 pF, RL ≥ 5 kΩ, 1 kHz - 10.9 - DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - Effective number of bits Unit LSB dB bits 10.9 - 1. Evaluated by characterization - Not tested in production. 2. Difference between two consecutive codes minus 1 LSB. 3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON. 6. Signal is −0.5 dBFS with Fsampling = 1 MHz. DS14258 Rev 5 213/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 60. 12-bit buffered/non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly, without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 Analog temperature sensor characteristics Table 100. Analog temperature sensor characteristics Symbol Parameter TL(1) Avg_Slope(2) V30(3) tstart_run tS_temp (1) Isens(1) Isensbuf(1) Min Typ Max VSENSE linearity with temperature (from VSENSOR voltage) - - 3 VSENSE linearity with temperature (from ADC counter) - - 3 Average slope (from VSENSOR voltage) - 2 - Average slope (from ADC counter) - 2 - Voltage at 30 °C ± 5 °C - 0.62 - Startup time in Run mode (buffer startup) - - 25.2 ADC sampling time when reading the temperature 9 - - Sensor consumption - 0.18 0.31 Sensor buffer consumption - 3.8 Unit °C mV/°C 6.5 V µs µA 1. Specified by design - Not tested in production. 2. Evaluated by characterization - Not tested in production. 3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 bytes. Table 101. Temperature sensor calibration values Symbol 214/270 Parameter Memory address TS_CAL1 Temperature sensor raw data acquired value at 30 °C, VDDA = 3.3 V 0x08FF F814 -0x08FF F815 TS_CAL2 Temperature sensor raw data acquired value at 130 °C, VDDA = 3.3 V 0x08FF F818 - 0x08FF F819 DS14258 Rev 5 STM32H562xx and STM32H563xx 5.3.26 Electrical characteristics Digital temperature sensor characteristics Table 102. Digital temperature sensor characteristics(1) Symbol Parameter fDTS(2) Output clock frequency TLC(2) Temperature linearity coefficient TTOTAL_ERROR(2) TVDD_CORE tTRIM tWAKE_UP IDDCORE_DTS Conditions Min Typ Max Unit - 500 750 1150 kHz VOS2 1660 2100 2750 Hz/°C TJ = −40 to 30 °C -13 - 4 TJ = 30 °C to TJmax -7 - 2 VOS2 0 - 0 VOS0, VOS1, VOS3 -1 - 1 Calibration time - - - 2 ms Wake-up time from off state until DTS ready bit is set - - 67 116 μs DTS consumption on VDD_CORE - 8.5 30 70 μA Min Typ Max Unit 1 - - μs Temperature offset measurement, all VOS Additional error due to supply variation °C °C 1. Specified by design - Not tested in production, unless otherwise specified. 2. Evaluated by characterization - Not tested in production. 5.3.27 VCORE monitoring characteristics Table 103. VCORE monitoring characteristics(1) Symbol TS_VCORE Parameter ADC sampling time when reading the VCORE voltage 1. Specified by design - Not tested in production. 5.3.28 Temperature and VBAT monitoring Table 104. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 4 x 26 - kΩ Q Ratio on VBAT measurement - 4 - - -10 - +10 % 9 - - µs (1) Er Error on Q tS_vbat(1) ADC sampling time when reading VBAT input VBAThigh High supply monitoring 3.50 3.575 3.63 VBATlow Low supply monitoring - 1.36 - IVBATbuf Sensor buffer consumption - 3.8 6.5 V µA 1. Specified by design - Not tested in production. DS14258 Rev 5 215/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 105. VBAT charging characteristics Symbol RBC Parameter Conditions Battery charging resistor Min Typ Max VBRS in PWR_CR3 = 0 - 5 - VBRS in PWR_CR3 = 1 - 1.5 - Unit kΩ Table 106. Temperature monitoring characteristics Symbol 5.3.29 Parameter Min Typ Max TEMPhigh High temperature monitoring - 126 - TEMPlow Low temperature monitoring - -37 - Unit °C Voltage booster for analog switch Table 107. Voltage booster for analog switch characteristics(1) Symbol VDD Parameter Conditions Min Typ Max Unit - 1.71 2.6 3.6 V - - - 50 µs 1.71 V ≤ VDD ≤ 2.7 V - - 125 2.7 V < VDD < 3.6 V - - 250 Supply voltage tSU(BOOST) Booster startup time IDD(BOOST) Booster consumption µA 1. Evaluated by characterization - Not tested in production. 5.3.30 VREFBUF characteristics Table 108. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode at VDDA = 3.3 V VDDA Analog supply voltage Degraded mode(2) Normal mode at 30 °C, ILOAD = 100 µA VREFBUF_ Voltage reference buffer output OUT Degraded mode(2) TRIM 216/270 Trim step resolution - Min Typ Max VRS = 000 2.8 3.3 3.6 VRS = 001 2.4 - 3.6 VRS = 010 2.1 - 3.6 VRS = 000 1.62 - 2.80 VRS = 001 1.62 - 2.40 VRS = 010 1.62 - 2.10 VRS = 000 2.498(3) 2.5000 2.5035(3) VRS = 001 2.0460 2.0490 2.0520 VRS = 010 1.8010 1.8040 1.8060 VRS = 000 VDDA − 150 mV - 2.5035 VRS = 001 VDDA − 150 mV - 2.0520 VRS = 010 VDDA − 150 mV - 1.8060 - - ±0.05 ±0.1 DS14258 Rev 5 Unit V V % STM32H562xx and STM32H563xx Electrical characteristics Table 108. VREFBUF characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CL Load capacitor - - 0.5 1 1.50 μF esr Equivalent serial resistor of CL - - - - 2 Ω Iload Static load current - - - - 4 mA Iload = 500 µA - 200 - Iload = 4 mA - 100 - ppm/ V Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload_reg Load regulation 500 µA ≤ Iload ≤ 4 mA Normal mode - 50 - ppm/ mA Tcoeff Temperature coefficient -40 °C < TJ < +130 °C - - - 100 ppm/ °C PSRR Power supply rejection DC - - 60 - 100 kHz - - 40 - CL= 0.5 µF - - 300 - CL= 1 µF - - 500 - CL= 1.5 µF - - 650 - - 8 - tSTART IINRUSH Start-up time Control of maximum DC current drive on VREFBUF_OUT during startup(4) IDDA(VREF Consumption from VDDA BUF) - ILOAD = 0 µA - - 15 25 ILOAD = 500 µA - - 16 30 ILOAD = 4 mA - - 32 50 dB µs mA µA 1. Specified by design - Not tested in production, unless otherwise specified. 2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage). 3. Evaluated by characterization - Not tested in production. 4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage must be in the range of 2.1 V - 3.6 V, 2.4 V -3.6 V, and 2.8 V - 3.6 V, respectively, for VRS = 010, 001, and 000. DS14258 Rev 5 217/270 238 Electrical characteristics 5.3.31 STM32H562xx and STM32H563xx Timer characteristics The parameters given in Table 109 are guaranteed by design. Refer to Section 5.3.15 for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 109. TIMx characteristics(1)(2) Symbol Conditions(3) Parameter tres(TIM) Timer resolution time Timer external clock frequency on CH1 to CH4 fEXT ResTIM Min Max Unit AHB/APBx prescaler = 1, 2, or 4, fTIMxCLK = 250 MHz 1 - tTIMxCLK AHB/APBx prescaler > 4, fTIMxCLK = 125 MHz 1 - tTIMxCLK 0 fTIMxCLK / 2 MHz - 16 / 32 bit - 65536 × 65536 tTIMxCLK fTIMxCLK = 250 MHz Timer resolution Maximum possible count with 32-bit counter tMAX_COUNT - 1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Specified by design - Not tested in production. 3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4 x Frcc_pclkx1 or TIMxCLK = 4 x Frcc_pclkx2. 5.3.32 Low-power timer characteristics Table 110. LPTIMx characteristics(1)(2) Symbol tres(TIM) flptim_ker_ck fEXT ResTIM tMAX_COUNT Parameter Min Max Unit Timer resolution time 1 - tlptim_ker_ck Timer kernel clock 0 250 Timer external clock frequency on Input1 and Input2 0 flptim_ker_ck / 3 Timer resolution - 16 bit Maximum possible count - 65535 tlptim_ker_ck 1. LPTIMx is used as a general term for LPTIM1 to LPTIM6 timers. 2. Specified by design - Not tested in production. 218/270 DS14258 Rev 5 MHz STM32H562xx and STM32H563xx 5.3.33 Electrical characteristics Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual revision 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are specified by design, not tested in production, when the I2C peripheral is properly configured (refer to the product reference manual) The SDA and SCL I/O requirements are met with the following restrictions: • The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to Section 5.3.15 for the I2C I/Os characteristics All I2C SDA and SCL I/Os embed an analog filter, refer to Table 111 for its characteristics. Table 111. I2C analog filter characteristics(1)(2) Symbol tAF Parameter Maximum pulse width of spikes suppressed by analog filter Min Max Unit 50(3) 160(4) ns 1. Evaluated by characterization - Not tested in production. 2. Measurement points are done at 50% VDD. 3. Spikes with widths below tAF(min) are filtered. 4. Spikes with widths above tAF(max) are not filtered. USART interface characteristics Unless otherwise specified, the parameters given in Table 112 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • VOS level set to VOS0 • HSLV activated when VDD ≤ 2.7 V Refer to Section 5.3.15 for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART). DS14258 Rev 5 219/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 112. USART characteristics(1) Symbol fCK Parameter USART clock frequency Conditions Min Typ Max Master receiver 1.71 V < VDD < 3.6 V 31 Master transmitter 1.71 V < VDD < 3.6 V 31/6(2) Master transmitter 2.7 V < VDD < 3.6 V 31/6(2) Slave receiver 1.71 V < VDD < 3.6 V - - MHz 83 Slave transmitter 1.71 V < VDD < 3.6 V 32/6(2) Slave transmitter 2.7 V < VDD < 3.6 V 35/6(2) tsu(NSS) NSS setup time Slave mode tker(3) + 3.5 - - th(NSS) NSS hold time Slave mode 2.5 - - tw(SCKH) tw(SCKL) CK high and low time Master mode 1/fck/2 -1 1/fck/2 1/fck/2 +1 tsu(RX) Data input setup time Master mode 13 - - Slave mode 3.5 - - th(RX) Data input hold time Master mode 0.5 - - Slave mode 1.5 - - Slave mode, 1.71 V < VDD < 3.6 V - Slave mode, 2.7 V < VDD < 3.6 V - 14/35(2) Slave mode, 1.71 V < VDD < 3.6 V - 3/52(2) Slave mode, 2.7 V < VDD < 3.6 V - Slave mode 7.5 - - Master mode 0 - - tv(TX) th(TX) Data output valid time Data output hold time 1. Evaluated by characterization - Not tested in production. 2. For PB14 with OSPEEDRy[1:0] = 01. 3. Tker is the usart_ker_ck_pres clock period. 220/270 DS14258 Rev 5 Unit ns 15.5/71(2) 11.5 2.5 3/22(2) ns STM32H562xx and STM32H563xx Electrical characteristics Figure 61. USART timing diagram in Master mode CK output CK output 1/fCK CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(CKH) tw(CKL) tsu(RX) RX INPUT BIT6 IN MSB IN LSB IN th(RX) TX OUTPUT BIT1 OUT MSB OUT tv(TX) LSB OUT th(TX) MSv65386V4 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 62. USART timing diagram in Slave mode NSS input 1/fCK CK input tsu(NSS) th(NSS) tw(CKH) CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 tw(CKL) tv(TX) First bit OUT TX output th(TX) Next bits OUT Last bit OUT th(RX) tsu(RX) RX input First bit IN Next bits IN Last bit IN MSv65387V4 I3C interface characteristics The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1. The I3C peripheral supports: • I3C SDR-only as controller • I3C SDR-only as target • I3C SCL bus clock frequency up to 12.5 MHz DS14258 Rev 5 221/270 238 Electrical characteristics STM32H562xx and STM32H563xx The parameters given in Table 113 are obtained with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 The timings are in line with MIPI specification, except for the ones given in Table 113 and Table 114. For tSU_OD and tSU_PP this can be mitigated by increasing the corresponding SCL low duration in the I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling and adjusting the clock stall time both on the address ACK phase and on the data read Tbit phase in the I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low duration in the I3C_TIMINGR0 register. For further details refer to AN5879. Table 113. I3C open-drain measured timing Symbol tSU_OD Parameter Conditions SDA data setup time during open drain mode I3C open drain mode (specification) Controller 1.71 V < VDD < 3.6 V Min Max 3 - Timing measurements Unit 16.5 ns Timing measurements Unit 12 ns Table 114. I3C push-pull measured timing Symbol tSU_PP Parameter SDA signal data setup in push-pull mode Conditions I3C open drain mode (specification) Controller 1.71 V < VDD < 3.6 V Min Max 3 - SPI interface characteristics Unless otherwise specified, the parameters given in Table 115 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Refer to Section 5.3.15 for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). 222/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 115. SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Master receiver mode 2.7 V < VDD < 3.6 V - - 135/3(2) Master receiver mode 1.71 V < VDD < 2.7 V - - 120/3(2) Master transmitter mode 2.7 V < VDD < 3.6 V fSCK 1/tSCK SPI clock frequency Unit 135/3(2) Master transmitter mode 1.71 V < VDD < 3.6 V - - 120/3(2) Slave receiver mode 1.71 V < VDD < 3.6 V - - 120 Slave transmitter mode 2.7 V < VDD < 3.6 V - - 43/6(3) Slave transmitter mode 1.71 V < VDD < 2.7 V - - 41/6(3) MHz tsu(NSS) NSS setup time Slave mode 3.5 - - ns th(NSS) NSS hold time Slave mode 4.5 - - ns SCK high and low time Master mode (tSCK/2) - 1 (tSCK/2) (tSCK/2) + 1 ns Master mode 3.5 - - Slave mode 2 - - Master mode 1 - - Slave mode 1.5 - - tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ns ns ta(SO) Data output access time Slave mode 6.5 - 15 ns tdis(SO) Data output disable time Slave mode 7.5 - 18 ns Slave mode, 2.7 V < VDD < 3.6 V - 8.5/25(3) 11.5/33(3) Slave mode, 1.71 V < VDD < 3.6 V - 10/59(3) 12/76(3) tv(MO) Master mode - 1.5 2 th(SO) Slave mode, 1.71 V < VDD < 3.6 V 6.5/20.5(3) - - Master mode 0 - - tv(SO) Data output valid time Data output hold time th(MO) ns ns 1. Evaluated by characterization - Not tested in production. 2. When using PB13. 3. When using PB14. DS14258 Rev 5 223/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 63. SPI timing diagram - Master mode High SS input (1) tc(SCK) SCK output CPHA=0 CPOL=0 SCK output tw(SCKH) CPHA=1 CPOL=0 CPHA=0 CPOL=1 tw(SCKL) CPHA=1 CPOL=1 tsu(MI) MISO input MOSI output th(MI) First bit IN Next bits IN First bit OUT Next bits OUT tv(MO) Last bit IN Last bit OUT th(MO) MSv69586V2 1. The SS input can be configured to active low or active high. Figure 64. SPI timing diagram - Slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) First bit OUT th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 224/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Figure 65. SPI timing diagram - Slave mode and CPHA = 1 SS input(1) th(SS) tc(SCK) SCK input tsu(SS) CPHA=1 CPOL=0 tw(SCKH) CPHA=1 CPOL=1 ta(SO) tw(SCKL) tv(SO) MISO output Next bits OUT First bit OUT tsu(SI) Last bit OUT th(SI) First bit IN MOSI input tdis(SO) th(SO) Next bits IN Last bit IN MSv69585V2 1. The SS input can be configured to active low or active high. I2S interface characteristics Unless otherwise specified, the parameters given in Table 116 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Refer to Section 5.3.15 for more details on the input/output alternate function characteristics (CK,SD,WS). Table 116. I2S dynamic characteristics(1) Symbol fMCK fCK Parameter Conditions Min Max - - 50 Master transmitter - 50 Slave transmitter (TX) - 21 Slave receiver (RX) - 50 I2S main clock output I2S clock output DS14258 Rev 5 Unit MHz 225/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 116. I2S dynamic characteristics(1) (continued) Symbol Parameter tv(WS) WS valid time th(WS) WS hold time tsu(WS) WS setup time th(WS) WS hold time tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time Conditions Min Max - 2 0.5 - 3 - 1.5 - Master receiver 4 - Slave receiver 2 - Master receiver 1 - Slave receiver 1.5 - Slave transmitter (after enable edge) - 14 Master transmitter (after enable edge) - 1 Slave transmitter (after enable edge) 5.5 - Master transmitter (after enable edge) 0 - Master mode Slave mode 1. Evaluated by characterization - Not tested in production. Figure 66. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 226/270 DS14258 Rev 5 Unit ns STM32H562xx and STM32H563xx Electrical characteristics Figure 67. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USB full speed (FS) characteristics The USB interface is fully compliant with the USB specification version 2.0. Table 117. USB DC electrical characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDD USB full speed transceiver operating voltage - 3.0(2) - 3.6 VDI(3) Differential input sensitivity Over VCM range 0.2 - - VCM(3) Differential input common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver input threshold 0.8 - 2.0 - - 0.3 2.8 - 3.6 14.25 - 24.8 0.9 1.25 1.575 1.425 2.25 3.09 - VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) VOH Static output level high RL of 15 kΩ to VSS(4) Pull down resistor on PA11, PA12 (USB_DP/DM) VIN = VDD Pull-up resistor on PA12 (USB_DP) VIN = VSS, during idle Pull-up resistor on PA12 (USB_DP) VIN = VSS during reception RPD(3) RPU(3) V V V kΩ 1. All the voltages are measured from the local ground potential. 2. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics, which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Specified by design - Not tested in production. DS14258 Rev 5 227/270 238 Electrical characteristics STM32H562xx and STM32H563xx 4. RL is the load connected on the USB full speed drivers. Figure 68. USB timings - definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 118. USB startup time Symbol Parameter tSTARTUP(1) Max Unit 1 μs USB transceiver startup time 1. Specified by design - Not tested in production. Table 119. USB electrical characteristics(1) Driver characteristics Symbol trLS tfLS trfmLS trFS tfFS Parameter Min Max Unit CL = 200 to 600 pF 75 300 ns CL = 200 to 600 pF 75 300 ns Rise/fall time matching in LS tr/tf 80 125 % Rise time in FS(2) CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 111 % 1.3 2.0 V 28 44 Ω Rise time in LS(2) Fall time in Fall time in LS(2) FS(2) trfmFS Rise/fall time matching in FS VCRS Output signal crossover voltage (LS/FS) ZDRV Output driver impedance(3) Conditions Driving high or low 1. Specified by design - Not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB specification chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. Table 120. USB BCD DC electrical characteristics(1) Symbol Conditions Min Typ Max Primary detection mode consumption - - - 300 Secondary detection mode consumption - - - 300 RDAT_LKG Data line leakage resistance - 300 - - kΩ VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V IDD(USBBCD) 228/270 Parameter DS14258 Rev 5 Unit μA STM32H562xx and STM32H563xx Electrical characteristics Table 120. USB BCD DC electrical characteristics(1) (continued) Symbol Conditions Min Typ Max Unit Dedicated charging port resistance across D+/D- - - - 200 Ω VLGC_HI Logic high - 2.0 - 3.6 VLGC_LOW Logic low - - - 0.8 Logic threshold - 0.8 - 2.0 VDAT_REF Data detect voltage - 0.25 - 0.4 VDP_SRC D+ source voltage - 0.5 - 0.7 VDM_SRC D- source voltage - 0.5 - 0.7 IDP_SINK D+ sink current - 25 - 175 IDM_SINK D- sink current - 25 - 175 RDCP_DAT VLGC Parameter V μA 1. Specified by design - Not tested in production. SAI characteristics Unless otherwise specified, the parameters given in Table 121 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • I/O compensation cell activated • Measurement points are done at CMOS levels: 0.5 VDD • VOS level set to VOS0 Refer to Section 5.3.15 for more details on the input/output alternate function characteristics (SCK, SD, WS). Table 121. SAI characteristics(1) Symbol fMCK fCK Parameter SAI main clock output SAI clock frequency Conditions Min Max - - 50 Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 38 Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 38 Master receiver, 1.71 V ≤ VDD ≤ 3.6 V - 38 Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 34 Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 33 Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - 50 DS14258 Rev 5 Unit MHz 229/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 121. SAI characteristics(1) (continued) Symbol Parameter tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Conditions Min Max Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 13 Master mode, 1.71 V ≤ VDD ≤ 3.6 V - 13 Slave mode 3 - Master mode 5 - Slave mode 2 - Master receiver 4 - Slave receiver 3.5 - Master receiver 1.5 - Slave receiver 0.5 - Slave transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 14.5 Slave transmitter (after enable edge), 1.71 V ≤ VDD ≤ 3.6 V - 15 Slave transmitter (after enable edge) 7 - Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 13 Master transmitter (after enable edge), 1.71 V ≤ VDD ≤ 3.6 V - 13 Master transmitter (after enable edge) 5.5 - Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time Unit ns 1. Evaluated by characterization - Not tested in production. Figure 69. SAI master timing waveforms 1/fSCK SAI_SCK_X (CKSTR = 0) SAI_SCK_X (CKSTR = 1) th(FS) SAI_FS_X (output) tv(FS) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) th(SD_MT) Slot n+2 th(SD_MR) Slot n MS32771V2 230/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Figure 70. SAI slave timing waveforms 1/fSCK SAI_SCK_X (CKSTR = 0) SAI_SCK_X (CKSTR = 1) tw(CKH_X) tw(CKL_X) th(FS) SAI_FS_X (input) tv(SD_ST) tsu(FS) SAI_SD_X (transmit) th(SD_ST) Slot n Slot n+2 tsu(SD_SR) SAI_SD_X (receive) th(SD_SR) Slot n MS32772V2 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 122 and Table 123 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL= 30 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V Refer to Section 5.3.15 for more details on the input/output characteristics. Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V(1) Symbol Parameter Conditions Min Typ fPP Clock frequency in data transfer mode - 0 - 8.5 9.5 - 8.5 9.5 - tW(CKL) Clock low time fPP = 52 MHz tW(CKH) Clock high time Max Unit 130(2)/6(3) MHz ns CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode tISU Input setup time HS - 3 - - tIH Input hold time HS - 1 - - Input valid window (variable window) - 4.5 - - tIDW(5) ns CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode tOV Output valid time HS - - 5 5.5/38(3) tOH Output hold time HS - 3 - - DS14258 Rev 5 ns 231/270 238 Electrical characteristics STM32H562xx and STM32H563xx Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD - 2.5 - tIHD Input hold time SD - 1.5 - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD - - 0.5 1/33(3) tOHD Output hold default time SD - 0 - - ns 1. Evaluated by characterization - Not tested in production. 2. CL applied is 20 pF. 3. When using PB13 and PB14. 4. For SD 1.8 V support, an external voltage converter is needed. 5. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 123. Dynamic characteristics: eMMC, VDD = 1.71 to 1.9 V(1) Symbol Parameter Conditions Min Typ fPP Clock frequency in data transfer mode - 0 - 8.5 9.5 - 8.5 9.5 - tW(CKL) Clock low time tW(CKH) Clock high time fPP =52 MHz Max Unit 110(2)/6(3) MHz ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS - 1.5 - - tIH Input hold time HS - 1.5 - - Input valid window (variable window) - 4 - - tIDW(4) ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS - - 5.5 6/75(3) tOH Output hold time HS - 3 - - 1. Evaluated by characterization - Not tested in production. 2. CL = 20 pF. 3. When using PB13 and PB14. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. 232/270 DS14258 Rev 5 ns STM32H562xx and STM32H563xx Electrical characteristics Figure 71. SDIO high-speed/eMMC timing MSv72345V1 Figure 72. SD default speed timings CK tOV tOH D, CMD output MSv69710V1 Figure 73. DDR mode timings Valid data D input tISU Valid data tIH tISU tIH tW(CKH) CK tW(CKL) tOV tOV tOH tOH D output Valid data Valid data MSv69158V1 DS14258 Rev 5 233/270 238 Electrical characteristics STM32H562xx and STM32H563xx Ethernet interface characteristics Unless otherwise specified, the parameters given in Table 124, Table 125, and Table 126 are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL= 20 pF • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.5 V Refer to Section 5.3.15 for more details on the input/output characteristics. Table 124. Dynamic characteristics: Ethernet MAC signals for SMI (1) Symbol tMDC Parameter MDC cycle time (2.5 MHz) Min Typ Max 400 400 403 Td(MDIO) Write data valid time 0 0.5 1 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Evaluated by characterization - Not tested in production. Table 125. Dynamic characteristics: Ethernet MAC signals for RMII (1) Symbol Parameter Typ Max tsu(RXD) Receive data setup time 3 - - tih(RXD) Receive data hold time 1 - - tsu(CRS) Carrier sense setup time 2 - - tih(CRS) Carrier sense hold time 1 - - td(TXEN) Transmit enable valid delay time 7.5 9.5 15 td(TXD) Transmit data valid delay time 7.5 10 15.5 1. Evaluated by characterization - Not tested in production. 234/270 Min DS14258 Rev 5 Unit ns STM32H562xx and STM32H563xx Electrical characteristics Table 126. Dynamic characteristics: Ethernet MAC signals for MII (1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 3 - - tih(RXD) Receive data hold time 1.5 - - tsu(DV) Data valid setup time 2 - - tih(DV) Data valid hold time 1 - - tsu(ER) Error setup time 3 - - tih(ER) Error hold time 1 - - 7.5 10 16 8 10.5 16.5 td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time Unit ns 1. Evaluated by characterization - Not tested in production. Figure 74. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b DS14258 Rev 5 235/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 75. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668b Figure 76. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 127 and Table 128 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL= 30 pF • HSLV activated when VDD ≤ 2.7 V • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.15 for more details on the input/output characteristics: 236/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Electrical characteristics Table 127. Dynamic JTAG characteristics Symbol FTCK 1/tc(TCK) Parameter TCK clock frequency Conditions Min Typ Max 2.7 V < VDD < 3.6 V - - 50 1.71 V < VDD < 3.6 V - - 45 tisu(TMS) TMS input setup time - 2 - - tih(TMS) TMS input hold time - 1.5 - - tisu(TDI) TDI input setup time - 1.5 - - tih(TDI) TDI input hold time - 1.5 - - 2.7V < VDD < 3.6 V - 8 10 1.71 < VDD < 3.6 V - 8 11 - 6.5 - - tov(TDO) TDO output valid time toh(TDO) TDO output hold time Unit MHz ns Table 128. Dynamic SWD characteristics Symbol FSWCLK 1/tc(SWCLK) Parameter SWCLK clock frequency Conditions Min Typ Max 2.7 V < VDD < 3.6 V - - 80 1.71 V < VDD < 3.6 V - - 71 tisu(SWDIO) SWDIO input setup time - 1.5 - - tih(SWDIO) SWDIO input hold time - 1.5 - - tov(SWDIO) SWDIO output valid time 2.7 V < VDD < 3.6 V - 10.5 12.5 1.71 V < VDD < 3.6 V - 10.5 14.0 toh(SWDIO) SWDIO output hold time - 8.5 - - Unit MHz ns Figure 77. JTAG timing diagram tc(TCK) TCK tsu(TMS/TDI) th(TMS/TDI) tw(TCKL) tw(TCKH) TDI/TMS tov(TDO) toh(TDO) TDO MSv40458V1 DS14258 Rev 5 237/270 238 Electrical characteristics STM32H562xx and STM32H563xx Figure 78. SWD timing diagram tc(SWCLK) SWCLK tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH) SWDIO (receive) tov(SWDIO) toh(SWDIO) SWDIO (transmit) MSv40459V1 238/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 Device marking Refer to “Reference device marking schematics for STM32 microcontrollers and microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1. Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection. DS14258 Rev 5 239/270 265 Package information 6.2 STM32H562xx and STM32H563xx LQFP64 package information (5W) This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package. Note: See list of notes in the notes section. Figure 79. LQFP64 - Outline(15) BOTTOM VIEW 2 1 (2) R1 R2 GAUGE PLANE 0.25 B D 1/4 SE C TI O N B- B H (6) S B 3 E 1/4 4x N/4 TIPS aaa C A-B D L (L1) (1) (11) bbb H A-B D 4x SECTION A-A (13) (N – 4)x e C A 0.05 A2 A1 (12) b ddd C A-B D ccc C D (9) (11) D (3) (10) E 1/4 WITH PLATING (11) (11) c D 1/4 B (3) (6) A (Section A-A) c1 (5) (2) E1 A E b1 (11) BASE METAL SECTION B-B 5W_LQFP64_ME_V1 TOP VIEW 240/270 b (4) N 1 2 3 (3) A (4) D1 (5) (2) DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Table 129. LQFP64 - Mechanical data Symbol inches(14) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1(12) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0570 (9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106 (11) b 0.17 0.20 0.23 0.0067 0.0079 0.0091 c(11) 0.09 - 0.20 0.0035 - 0.0079 c1(11) 0.09 - 0.16 0.0035 - 0.0063 b1 (4) 12.00 BSC 0.4724 BSC (2)(5) 10.00 BSC 0.3937 BSC 12.00 BSC 0.4724 BSC 10.00 BSC 0.3937 BSC 0.50 BSC 0.1970 BSC D D1 E(4) (2)(5) E1 e L 0.45 L1 0.60 0.75 0.0177 1.00 REF 0.0236 0.0295 0.0394 REF N(13) 64 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - (1) 0.20 0.0079 (1) 0.20 0.0079 ccc (1) 0.08 0.0031 ddd(1) 0.08 0.0031 aaa bbb DS14258 Rev 5 241/270 265 Package information STM32H562xx and STM32H563xx Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. Figure 80. LQFP64 - Footprint example 48 33 0.30 0.5 49 32 12.70 10.30 10.30 17 64 1.20 16 1 7.80 12.70 1. Dimensions are expressed in millimeters. 242/270 DS14258 Rev 5 5W_LQFP64_FP_V2 STM32H562xx and STM32H563xx 6.3 Package information VFQFPN68 package information (B029) This VFQFPN is a 68 pins, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package. Figure 81. VFQFPN68 - Outline PIN 1 IDENTIFIER LASER MARKING ddd C D A A1 A2 68 67 1 2 E (2X) E 0.10 C C TOP VIEW L SEATING PLANE SIDE VIEW D2 E2 2 1 PIN 1 ID C 0.30 X 45' 68 67 e b EXPOSED PAD AREA BOTTOM VIEW B029_VFQFPN68_ME_V1 1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed version. Very thin profile: 0.80 < A ≤ 1.00mm. 2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional. DS14258 Rev 5 243/270 265 Package information STM32H562xx and STM32H563xx Table 130. VFQFPN68 - Mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0 0.02 0.05 0 0.0008 0.0020 A3 - 0.20 - - 0.0008 - b 0.15 0.20 0.25 0.0059 0.0079 0.0098 D 7.85 8.00 8.15 0.3091 0.3150 0.3209 D2 6.30 6.40 6.50 0.2480 0.2520 0.2559 E 7.85 8.00 8.15 0.3091 0.3150 0.3209 E2 6.30 6.40 6.50 0.2480 0.2520 0.2559 e - 0.40 - - 0.0157 - L 0.40 0.50 0.60 0.0157 0.0197 0.0236 ddd - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. VFQFPN68 - Footprint example 8.30 7.00 6.65 6.40 0.15 8.30 7.00 6.65 6.40 0.25 0.82 0.65 0.40 B029_VFQFPN68_FP_V2 1. Dimensions are expressed in millimeters. 244/270 DS14258 Rev 5 STM32H562xx and STM32H563xx WLCSP80 package information (B0D4) This WLCSP is a 80 ball, 3.50 x 3.27 mm, 0.35 mm pitch, wafer level chip scale package. Figure 83. WLCSP80 - Outline G F e1 (DETAIL A) (DETAIL B) K e e e e2 DETAIL B BOTTOM VIEW A3 A bbb C BACKSIDE CODE 6.4 Package information SIDE VIEW A2 SIDE VIEW DETAIL A BUMP D A1 eee Z E b (80x) ccc Z X Y ddd Z 4x A1 Orientation ref aaa C DETAIL A ROTATED 90 SEATING PLANE TOP VIEW B0D4_WLCSP80_ME_V1 1. Drawing is not to scale. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone. DS14258 Rev 5 245/270 265 Package information STM32H562xx and STM32H563xx Table 131. WLCSP80 - Mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A(2) - - 0.58 - - 0.228 A1 - 0.17 - - 0.0067 - A2 - 0.38 - - 0.0150 - - 0.025 - - 0.0098 - b 0.22 0.24 0.27 0.0087 0.0094 0.0106 D 3.47 3.50 3.52 0.1366 0.1378 0.1386 E 3.25 3.27 3.30 0.1279 0.1287 0.1299 e - 0.35 - - 0.138 - e1 - 2.73 - - 0.1075 - e2 - 2.45 - - 0.0964 - F(4) - 0.384 - - 0.0151 - G(4) - 0.484 - - 0.0190 - H - 0.1025 - - 0.0040 - aaa - - 0.10 - - 0.0039 bbb (3) A3 - - 0.10 - - 0.0039 (5) - - 0.10 - - 0.0039 (6) - - 0.05 - - 0.0020 - - 0.05 - - 0.0020 ccc ddd eee 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal and tolerances values of A1 and A2. 3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability. 4. Calculated dimensions are rounded to the 3rd decimal place 5. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone. 6. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone. Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones. 246/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Figure 84. WLCSP80 - Footprint example Dpad Dsm BGA_WLCSP_FT_V1 Table 132. WLCSP80 - Example of PCB design rules Dimension Values Pitch 0.35 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on soldermask registration tolerance) Stencil opening 0.235 mm Stencil thickness 0.080 mm Example of device marking for WLCSP80 The following figure gives an example of the locations and orientation of the marking areas versus ball A1, and allows engineering samples to be identified. With the device text markings oriented as in the figure, ball A1 is always located at top left. Figure 85. WLCSP80 marking example (package top view) Ball 1 identifier Product identification Date code Y ww Revision code MS56506V1 DS14258 Rev 5 247/270 265 Package information 6.5 STM32H562xx and STM32H563xx LQFP100 package information (1L) This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package. Note: See list of notes in the notes section. Figure 86. LQFP100 - Outline(15) ș ș2 (2) R1 R2 O N BB H B SE C TI (6) D1/4 GAUGE PLANE S ș 4x N/4 TIPS L 4x aaa C A-B D (L1) bbb H A-B D (1) (11) SECTION A-A BOTTOM VIEW (N-4) x e (13) C A 0.05 ș B E1/4 (9) (11) b A2 A1 (12) aaa b ccc C C A-BD WITH PLATING SIDE VIEW D D1 (2) (5) (4) (11) D (3) (10) c c1 (11) (4) N b1 BASE METAL (11) 1 2 3 E1/4 D1/4 SECTION B-B (2) (6) B A (5) E1 E SECTION A-A A A TOP VIEW 248/270 1L_LQFP100_ME_V3 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Table 133. LQFP100 - Mechanical data inches(14) millimeters Symbol A (12) A1 A2 Min Typ Max Min Typ Max - 1.50 1.60 - 0.0590 0.0630 0.05 - 0.15 0.0019 - 0.0059 1.35 1.40 1.45 0.0531 0.0551 0.0570 (9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106 (11) 0.17 0.20 0.23 0.0067 0.0079 0.0090 0.09 - 0.20 0.0035 - 0.0079 0.09 - 0.16 0.0035 - 0.0063 b b1 (11) c c1(11) (4) 16.00 BSC 0.6299 BSC (2)(5) D 14.00 BSC 0.5512 BSC E(4) 16.00 BSC 0.6299 BSC E1(2)(5) 14.00 BSC 0.5512 BSC e 0.50 BSC 0.0197 BSC D1 L L1 0.45 (1)(11) 0.60 0.75 1.00 N(13) 0.177 0.0236 0.0295 - 0.0394 - 100 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1) 0.20 0.0079 (1) bbb 0.20 0.0079 ccc(1) 0.08 0.0031 (1) 0.08 0.0031 ddd DS14258 Rev 5 249/270 265 Package information STM32H562xx and STM32H563xx Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. Figure 87. LQFP100 - Footprint example 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 1L_LQFP100_FP_V1 1. Dimensions are expressed in millimeters. 250/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 6.6 Package information LQFP144 package information (1A) This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package. Note: See list of notes in the notes section. Figure 88. LQFP144 - Outline(15) BOTTOM VIEW 2 1 (2) R1 R2 B GAUGE PLANE 0.25 (6) SE C TI O N B- B H D 1/4 S B 3 E 1/4 L (L1) (1) (11) 4x N/4 TIPS aaa C A-B D SECTION A-A bbb H A-B D 4x (N-4)x e C A 0.05 A2 A1 (12) b ddd C A-B D D D1 (3) (10) ccc C (4) (2) (5) D 1 2 3 (9) (11) (4) N b WITH PLATING E 1/4 (11) D 1/4 (6) c1 (11) (2) (5) B (3) (3) A c E1 E b1 (11) BASE METAL SECTION B-B A (Section A-A) A TOP VIEW 1A_LQFP144_ME_V2 DS14258 Rev 5 251/270 265 Package information STM32H562xx and STM32H563xx Table 134. LQFP144 - Mechanical data inches(14) millimeters Symbol A (12) A1 A2 b Min Typ Max Min Typ Max - - 1.60 - - 0.0630 0.05 - 0.15 0.0020 - 0.0059 1.35 1.40 1.45 0.0531 0.0551 0.0571 (9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106 (11) 0.17 0.20 0.23 0.0067 0.0079 0.0090 0.09 - 0.20 0.0035 - 0.0079 0.09 - 0.16 0.0035 - 0.0063 b1 c (11) c1(11) (4) 22.00 BSC 0.8661 BSC (2)(5) D 20.00 BSC 0.7874 BSC E(4) 22.00 BSC 0.8661 BSC E1(2)(5) 20.00 BSC 0.7874 BSC e 0.50 BSC 0.0197 BSC D1 L 0.45 L1 0.60 0.75 1.00 REF 0.0236 0.0295 0.0394 REF N(13) 252/270 0.0177 144 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa 0.20 0.0079 bbb 0.20 0.0079 ccc 0.08 0.0031 ddd 0.08 0.0031 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. DS14258 Rev 5 253/270 265 Package information STM32H562xx and STM32H563xx Figure 89. LQFP144 - Footprint example 108 109 73 1.35 72 0.35 0.50 19.90 17.85 22.60 144 37 1 36 19.90 22.60 1A_LQFP144_FP 1. Dimensions are expressed in millimeters. 254/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 6.7 Package information UFBGA169 package information (A0YV) This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package. Figure 90. UFBGA169 - Outline E1 SE e N M L K J H G F E D C B A SD e D1 1 2 3 4 5 6 7 8 9 10 11 12 13 Øb (169 balls) Ø eee M C A B Ø fff M C A1 ball pad corner BOTTOM VIEW Detail A A3 A ccc C Mold resin A2 Seating plane C SIDE VIEW 2 C ddd C Substrate Solder balls A1 A5 DETAIL A E B A 3 A1 ball pad corner (DATUM A) D (DATUM B) aaa C (4x) TOP VIEW A0YV_UFBGA169_ME_V2 1. Drawing is not to scale. 2. Primary datum C is defined by the plane established by the contact points of three or more solder balls that support the device when it is placed on top of a planar surface. 3. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. DS14258 Rev 5 255/270 265 Package information STM32H562xx and STM32H563xx Table 135. UFBGA169 - Mechanical data inches(1) millimeters Symbol A(2) (3) A1 A2 b (4) (5) D D1 (5) E(5) Min. Typ. Max. Min. Typ. Max. - - 0.60 - - 0.0236 0.05 - - 0.0020 - - - 0.43 - - 0.0169 - 0.23 0.28 0.33 0.0091 0.0110 0.0130 7.00 BSC 0.2756 BSC 6.00 BSC 0.2362 BSC 7.00 BSC 0.2756 BSC (5) 6.00 BSC 0.2362 BSC (5)(6) 0.50 BSC 0.0197 BSC E1 e N(7) 169 SD(5)(8) 0.50 BSC 0.0197 BSC SE(5)(8) 0.50 BSC 0.0197 BSC (9) 0.15 0.0059 (9) 0.20 0.0079 ddd(9) 0.08 0.0031 (9) 0.15 0.0059 0.05 0.0020 aaa ccc eee fff (9) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured perpendicular to the seating plane. 3. A1 is defined as the distance from the seating plane to the lowest point on the package body. 4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C. 5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form and position table. 6. e represents the solder ball grid pitch. 7. N represents the total number of balls on the BGA. 8. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the position of the centre ball(s) in the outer row or column of a fully populated matrix. 9. Tolerance of form and position drawing 256/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Figure 91. UFBGA169 - Footprint example Dpad Dsm BGA_WLCSP_FT_V1 Table 136. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) Dimension Values Pitch 0.5 mm Dpad 0.27 mm Dsm 0.35 mm typ. (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter. Note: Non-solder mask defined (NSMD) pads are recommended. Note: 4 to 6 mils solder paste screen printing process. DS14258 Rev 5 257/270 265 Package information 6.8 STM32H562xx and STM32H563xx LQFP176 package information (1T) This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package. Note: See list of notes in the notes section. Figure 92. LQFP176 - Outline(15) ș1 ș2 R1 (2) R2 H B(See SECTION B-B) GAUGE PLANE (6) 0.25 D1/4 S (L1) 4x bbb H A-B D aaa C A-B D (1) (11) SECTION A-A BOTTOM VIEW A2 0.05 L ș E1/4 4x N/4 TIPS ș B  (N-4) x e C A A1 (12) ddd b ccc C C A-BD SIDE VIEW D N (10) (4) D D1 (2) (5)  (9) (11) b (4) WITH PLATING E1/4 D1/4 (6) A B  (5) (2) E1 E (11) c c1 (11) b1 (11) BASE METAL SECTION A-A A A TOP VIEW 258/270 SECTION B-B 1T_LQFP176_ME_V2 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Table 137. LQFP176 - Mechanical data Symbol inches(14) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1(12) 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 (9)(11) 0.170 0.220 0.270 0.0067 0.0087 0.0106 (11) 0.170 0.200 0.230 0.0067 0.0079 0.0091 0.090 - 0.200 0.0035 - 0.0079 0.090 - 0.160 0.0035 - 0.063 b b1 c(11) (11) c1 (4) 26.000 1.0236 (2)(5) 24.000 0.9449 26.000 0.0197 24.000 0.9449 0.500 0.1970 D D1 E(4) (2)(5) E1 e L 0.450 L1(1)(11) 0.600 0.750 0.0177 1 0.0236 0.0295 0.0394 REF N(13) 176 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.080 - - 0.0031 - - R2 0.080 - 0.200 0.0031 - 0.0079 S 0.200 - - 0.0079 - - (1) 0.200 0.0079 (1) 0.200 0.0079 (1) 0.080 0.0031 ddd(1) 0.080 0.0031 aaa bbb ccc DS14258 Rev 5 259/270 265 Package information STM32H562xx and STM32H563xx Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. 260/270 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Figure 93. LQFP176 - Footprint example 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters. DS14258 Rev 5 261/270 265 Package information 6.9 STM32H562xx and STM32H563xx UFBGA(176+25) package information (A0E7) This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package. Figure 94. UFBGA(176+25) - Outline Seating plane C A4 ddd C A2 A3 A1 b e A A1 ball identifier E1 A1 ball index area A E F A F D D1 e B R 15 1 BOTTOM VIEW Øb (176 + 25 balls) TOP VIEW Ø eee M C A B Ø fff M C A0E7_ME_V10 1. Drawing is not to scale. Table 138. UFBGA(176+25) - Mechanical data inches(1) millimeters Symbol 262/270 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 - 0.450 - - 0.0177 - A3 - 0.130 - - 0.0051 - A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.100 - - 0.3583 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - F - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 DS14258 Rev 5 STM32H562xx and STM32H563xx Package information Table 138. UFBGA(176+25) - Mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 95. UFBGA(176+25) - Footprint example Dpad Dsm BGA_WLCSP_FT_V1 Table 139. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) Dimension Values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS14258 Rev 5 263/270 265 Package information 6.10 STM32H562xx and STM32H563xx Package thermal characteristics The maximum chip-junction temperature, TJmax in degrees Celsius, can be calculated using the following equation: TJmax = TAmax + (PDmax × ΘJA) Where: • TAmax is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax), • PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins: PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 140. Package thermal characteristics Symbol ΘJA ΘJB 264/270 Definition Thermal resistance junction-ambient Thermal resistance junction-board Parameter Value LQFP64 (10 x 10 mm) 48.1 VFQFPN68 (8 x 8 mm) 24.2 WLCSP80 (3.50 x 3.27 mm) 47.3 LQFP100 (14 x 14 mm) 35.9 LQFP144 (20 x 20 mm) 37.5 LQFP176 (24 x 24 mm) 38.3 UFBGA169 (7 x 7 mm) 40.6 UFBGA176 (10 x 10 mm) 39.1 LQFP64 (10 x 10 mm) 24.1 VFQFPN68 (8 x 8 mm) 9.4 WLCSP80 (3.50 x 3.27 mm) 23.0 LQFP100 (14 x 14 mm) 21.9 LQFP144 (20 x 20 mm) 26.3 LQFP176 (24 x 24 mm) 28.3 UFBGA169 (7 x 7 mm) 26.4 UFBGA176 (10 x 10 mm) 27.0 DS14258 Rev 5 Unit °C/W °C/W STM32H562xx and STM32H563xx Package information Table 140. Package thermal characteristics (continued) Symbol ΘJC 6.10.1 Definition Thermal resistance junction-case Parameter Value LQFP64 (10 x 10 mm) 10.3 VFQFPN68 (8 x 8 mm) 10.8 WLCSP80 (3.50 x 3.27 mm) 2.3 LQFP100 (14 x 14 mm) 8.5 LQFP144 (20 x 20 mm) 8.6 LQFP176 (24 x 24 mm) 9.1 UFBGA169 (7 x 7 mm) 11.2 UFBGA176 (10 x 10 mm) 10.9 Unit °C/W Reference documents • JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. • For information on thermal management, refer to AN5036 “Guidelines for thermal management on STM32 applications”, available from www.st.com. DS14258 Rev 5 265/270 265 Ordering information 7 STM32H562xx and STM32H563xx Ordering information Example: STM32 H 563 V I T 6 Q TR Device family STM32 = Arm based 32-bit microcontroller Product type H = high performance Device subfamily 562 = STM32H562xx devices without Ethernet 563 = STM32H563xx devices Pin count R = 64 pins / 68 pins M = 80 pins V = 100 pins Z = 144 pins A = 169 balls I = 176 pins Flash memory size G = 1 Mbyte I = 2 Mbytes Package V = VFQFPN T = LQFP I = UFBGA (7 x 7 mm) K = UFBGA (10 x 10) Y = WLCSP Temperature range 6 = Industrial, -40 to 85 °C (130 °C junction), available only in LDO option 7 = Industrial, -40 to 105 °C (130 °C junction), available only in LDO option 3 = Industrial, -40 to 125 °C (130 °C junction), available only in SMPS option Dedicated pinout Q = Dedicated pinout supporting SMPS step-down converter Packing TR = tape and reel xxx = programmed parts For a list of available options (such as speed or package) or for further information on any aspect of this device, contact the nearest ST sales office. 266/270 DS14258 Rev 5 STM32H562xx and STM32H563xx 8 Important security notice Important security notice The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: • ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. • Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. • Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. • While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. • All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. DS14258 Rev 5 267/270 267 Revision history 9 STM32H562xx and STM32H563xx Revision history Table 141. Document revision history Date Revision 06-Mar-2023 1 Initial release. 2 Updated Features and Section 3.10.1: Power supply schemes. Updated Table 2: STM32H56xxx features and peripheral counts, Table 18: Current characteristics, Table 20: General operating conditions, tables 30 to 32, tables 34 to 35, Table 58: I/O static characteristics, and Table 64: Output timing characteristics (HSLV ON). Updated Figure 7: WLCSP80 SMPS ballout, Figure 41: NAND controller waveforms for read access, Figure 42: NAND controller waveforms for write access, Figure 63: SPI timing diagram - Master mode, Figure 65: SPI timing diagram - Slave mode and CPHA = 1, Figure 69: SAI master timing waveforms, and Figure 70: SAI slave timing waveforms. Added Section 3.32: Public key accelerator (PKA), Section 6.1: Device marking, and Example of device marking for WLCSP80. Minor text edits across the whole document. 3 Updated Figure 1: STM32H562xx and STM32H563xx block diagram, Figure 6: VFQFPN68 pinout, Figure 17: UFBGA176+25 SMPS ballout, Figure 31: VIL/VIH for all I/Os except BOOT0, and Figure 63: SPI timing diagram - Master mode. Updated Table 14: STM32H562xx and STM32H563xx pin/ball definition, Table 15: Alternate functions AF0 to AF7, Table 21: Maximum allowed clock frequencies, Table 23: Characteristics of SMPS step-down converter external components, Table 30: Typical and maximum current consumption in Run mode, code with data processing running from SRAM with cache 1-way, Table 45: HSI oscillator characteristics, tables 53 to 55, Table 122: Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V, and Table 123: Dynamic characteristics: eMMC, VDD = 1.71 to 1.9 V. Updated Section 3.24.1: Analog temperature sensor. Added Section 3.25: Digital temperature sensor (DTS), Section 5.3.14: I/O current injection characteristics, and USB full speed (FS) characteristics. Added Table 60: Output voltage characteristics for FT_c I/Os and Table 67: Output timing characteristics for FT_c I/Os (PB13/PB14). Added Figure 36: Asynchronous multiplexed PSRAM/NOR write waveforms. Minor text edits across the whole document. 20-Oct-2023 28-May-2024 268/270 Changes DS14258 Rev 5 STM32H562xx and STM32H563xx Revision history Table 141. Document revision history Date Revision Changes 13-Dec-2024 4 Updated Features, Section 3.28: Digital camera interface (DCMI), Wake-up time from low-power modes, and Section 7: Ordering information. Updated Table 2: STM32H56xxx features and peripheral counts, Table 10: SPI features, Table 20: General operating conditions, Table 21: Maximum allowed clock frequencies, Table 36: Typical and maximum current consumption in Standby mode, Table 37: Typical and maximum current consumption in VBAT mode, Table 40: High-speed external user clock characteristics, Table 51: Flash memory programming, Table 89: OCTOSPI characteristics in DTR mode (no DQS), Table 90: OCTOSPI characteristics in DTR mode (with DQS) / HyperBus, Table 95: 12-bit ADC characteristics, Table 110: LPTIMx characteristics, and Table 135: UFBGA169 - Mechanical data. Updated Figure 5: LQFP64 pinout and Figure 90: UFBGA169 - Outline. Minor text edits across the whole document. 02-Jan-2025 5 Updated Table 36: Typical and maximum current consumption in Standby mode. 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For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2025 STMicroelectronics – All rights reserved 270/270 DS14258 Rev 5