STM32H723VE STM32H723VG
STM32H723ZE STM32H723ZG
Arm® Cortex®-M7 32-bit 550 MHz MCU, up to 1 MB Flash, 564 KB
RAM, Ethernet, USB, 3x FD-CAN, Graphics, 2x 16-bit ADCs
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
LQFP100
(14x14 mm)
Core
LQFP144
(20x20 mm)
FBGA
• 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1
cache: 32-Kbyte data cache and 32-Kbyte
instruction cache allowing 0-wait state
execution from embedded Flash memory and
external memories, frequency up to 550 MHz,
MPU, 1177 DMIPS/2.14 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Clock, reset and supply management
Memories
• 1.62 V to 3.6 V application supply and I/O
• Up to 1 Mbyte of embedded Flash memory with
ECC
• POR, PDR, PVD and BOR
• SRAM: total 564 Kbytes all with ECC, including
128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to
256 Kbytes can remap on instruction TCM
RAM for critical real time instructions) +
4 Kbytes of backup SRAM (available in the
lowest-power modes)
• Embedded LDO regulator
• Flexible external memory controller with up to
16-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• 2 x Octo-SPI interface with XiP
• Dedicated USB power
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-50 MHz HSE,
32.768 kHz LSE
Low power
• Sleep, Stop and Standby modes
• VBAT supply for RTC, 32×32-bit backup
registers
• 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to
18 channels and 7.2 MSPS in doubleinterleaved mode
• Bootloader
Graphics
• Chrom-ART Accelerator graphical hardware
accelerator enabling enhanced graphical user
interface to reduce CPU load
December 2021
UFBGA144
(7x7 mm)
Analog
• 2 x SD/SDIO/MMC interface
• LCD-TFT controller supporting up to XGA
resolution
TFBGA100
(8x8 mm)
FBGA
• 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12
channels
• 2 x comparators
• 2 x operational amplifier GBW = 8 MHz
• 2× 12-bit D/A converters
DS13313 Rev 3
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STM32H723xE/G
Digital filters for sigma delta modulator
(DFSDM)
• 8 channels/4 filters
• SWPMI single-wire protocol master I/F
• MDIO slave interface
Mathematical acceleration
4 DMA controllers to offload the CPU
• 1 × MDMA with linked list support
• CORDIC for trigonometric functions
acceleration
• 2 × dual-port DMAs with FIFO
• FMAC: Filter mathematical accelerator
• 1 × basic DMA with request router capabilities
Digital temperature sensor
24 timers
True random number generator
• Seventeen 16-bit (including 5 x low power
16-bit timer available in stop mode) and four
32-bit timers, each with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 2x watchdogs, 1x SysTick timer
CRC calculation unit
RTC with sub-second accuracy and
hardware calendar
ROP, PC-ROP, tamper detection
Debug mode
96-bit unique ID
• SWD and JTAG interfaces
All packages are ECOPACK2 compliant
• 2-Kbyte embedded trace buffer
Up to 114 I/O ports with interrupt
capability
Up to 35 communication interfaces
• Up to 5 × I2C FM+ interfaces
(SMBus/PMBus™)
• Up to 5 USARTs/5 UARTs (ISO7816 interface,
LIN, IrDA, modem control) and 1 x LPUART
• Up to 6 SPIs with 4 with muxed duplex I2S for
audio class accuracy via internal audio PLL or
external clock and up to 5 x SPI (from 5 x
USART when configured in synchronous
mode)
• 2x SAI (serial audio interface)
• 1× FD/TT-CAN and 2x FD-CAN
• 8- to 14-bit camera interface
• 16-bit parallel slave synchronous interface
• SPDIF-IN interface
• HDMI-CEC
• Ethernet MAC interface with DMA controller
• USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip FS PHY and ULPI for external
HS PHY
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Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5
CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.7
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.14
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 31
3.15
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 31
3.16
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 31
3.17
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18
Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.19
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.20
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21
Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.23
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 36
3.27
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28
PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.30
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.31
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.31.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.31.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.31.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 43
3.31.5
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.6
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.32
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 44
3.33
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.34
Universal synchronous/asynchronous receiver transmitter (USART) . . . 45
3.35
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46
3.36
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 47
3.37
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.38
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.39
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 48
3.40
Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 49
3.41
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 49
3.42
Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 49
3.43
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 50
3.44
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 50
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Contents
3.45
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.46
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5
Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 53
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.3
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 93
6.3.4
Embedded reset and power control block characteristics . . . . . . . . . . . 94
6.3.5
Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . . 95
6.3.6
Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
I/O system current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
On-chip peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
6.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111
High-speed external user clock generated from an external source . . . . . . . . .111
Low-speed external user clock generated from an external source . . . . . . . . . .112
High-speed external clock generated from a crystal/ceramic resonator. . . . . . .113
Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .114
6.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .115
64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .116
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4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .117
Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
6.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.12
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
6.3.13
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .123
Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .123
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6.3.14
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 124
Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
6.3.15
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .125
6.3.16
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .130
Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .132
Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.3.17
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.18
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Synchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
SDRAM waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.3.19
Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.20
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.21
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
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6.3.22
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.23
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.24
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.25
Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 181
6.3.26
Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 182
6.3.27
Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.28
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.3.29
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
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Contents
6.3.30
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.31
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 187
6.3.32
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 189
6.3.33
Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 190
6.3.34
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 191
6.3.35
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.36
Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.37
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .205
USB OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
7.2
TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
7.3
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
7.4
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Device marking for UFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
7.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.5.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
DS13313 Rev 3
7/234
7
List of tables
STM32H723xE/G
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
8/234
STM32H723xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STM32H723 pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STM32H723 pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 92
VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical and maximum current consumption in Run mode,
code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 100
Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 101
Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 102
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 120
PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 121
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DS13313 Rev 3
STM32H723xE/G
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
List of tables
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 128
Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 129
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 138
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 138
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 141
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 147
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 159
Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
DS13313 Rev 3
9/234
10
List of tables
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
10/234
STM32H723xE/G
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . 205
Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V . . . . . . . . . . . . . . 206
USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 209
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 210
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 211
Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . 221
LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
UFBGA144 - Recommended PCB design rules (0.50 mm pitch BGA). . . . . . . . . . . . . . . 227
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
DS13313 Rev 3
STM32H723xE/G
List of figures
List of figures
Figure 1.
STM32H723xE/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2.
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3.
STM32H723xE/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4.
TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 5.
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6.
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 7.
UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 8.
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 9.
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 10. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 12. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 13. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 14. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 15. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 17. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 18. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 135
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 137
Figure 21. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 22. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 23. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 24. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 25. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 26. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 27. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 28. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 151
Figure 29. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 152
Figure 30. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 31. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 32. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 33. OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 34. OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 35. OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 36. OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 37. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 38. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function168
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 169
Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 169
Figure 41. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 42. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 43. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 44. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 45. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 46. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 47. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DS13313 Rev 3
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12
List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
12/234
STM32H723xE/G
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
LQFP100- Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
TFBGA100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
TFBGA100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
UFBGA144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
UFBGA144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
UFBGA144 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DS13313 Rev 3
STM32H723xE/G
1
Introduction
Introduction
This document provides information on STM32H723xE/G microcontrollers, such as
description, functional overview, pin assignment and definition, packaging, and ordering
information.
This document should be read in conjunction with the STM32H723xE/G reference manual
(RM0468), available from the STMicroelectronics website www.st.com.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32H723 errata sheet (ES0491) available on the STMicroelectronics website
www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS13313 Rev 3
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52
Description
2
STM32H723xE/G
Description
STM32H723xE/G devices are based on the high-performance Arm® Cortex®-M7 32-bit
RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit
(FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision
data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of
instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set
of DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte
of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared
between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI,
128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access. To improve application robustness, all memories feature error code
correction (one error correction, two error detections).
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the
devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power
comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit
timers including two PWM timers for motor control, five low-power timers, a true random
number generator (RNG). The devices support four digital filters for external sigma-delta
modulators (DFSDM). They also feature standard and advanced communication interfaces.
•
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Standard peripherals
–
Five I2Cs
–
Five USARTs, five UARTs and one LPUART
–
Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization (note that the five USARTs also provide SPI slave
capability).
–
Two SAI serial audio interfaces
–
One SPDIFRX interface with four inputs
–
One SWPMI (Single Wire Protocol Master Interface)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces
–
A USB OTG high-speed interface with full-speed capability (with the ULPI)
–
Two FDCANs plus one TT-FDCAN interface
–
An Ethernet interface
–
Chrom-ART Accelerator
–
HDMI-CEC
DS13313 Rev 3
STM32H723xE/G
•
Description
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
Two Octo-SPI memory interfaces
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
Refer to Table 1: STM32H723xE/G features and peripheral counts for the list of peripherals
available on each part number.
STM32H723xE/G devices operate in the –40 to +85 °C ambient temperature range from a
1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an
external power supervisor (see Section 3.7.2: Power supply supervisor) and connecting the
PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the
embedded power voltage detector enabled.
Dedicated supply inputs for USB are available to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H723xE/G devices are offered in several packages ranging from 100 to 144
pins/balls. The set of included peripherals changes with the device chosen.
These features make STM32H723xE/G microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS13313 Rev 3
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52
Description
STM32H723xE/G
Figure 1. STM32H723xE/G block diagram
MII / RMII
To APB1-2
peripherals
MDIO
as AF
AHB1
D-TCM
64KB
I-TCM 64KB
Arm CPU
Cortex-M7
550 MHz
1 MB FLASH
LCD-TFT
FIFO
WWDG
OCTOSPI1
FMC_signals
CORDIC
FMAC
SRAM1 SRAM2
16 KB 16 KB
ADC1
AHB3
FIFO
SDMMC1
TIM6
AXI/AHB34 (275MHz)
16b
TIM7
16b
SWPMI
AHB4
AHB2 (275MHz)
DCMI
PSSI
Up to 20 analog inputs Most
are common to ADC1 & 2
ADC2
AHB/APB
DLYBOS1-2
AHB/APB
DLYBSD2
HSYNC, VSYNC, PIXCLK, D[13:0]
PDCK, DE, RDY, D[15:0]
RNG
OCTOSPI2
signals
DLYBSD1
D[7:0], D123DIR, D0DIR,
CMD, CKas AF
DMA
Mux1
OCTOSPI1
signals
OCTOSPI2
APB3 (138MHz)
FIFO
64-bit AXI BUS-MATRIX
16 Streams
FIFO
CHROM-ART
(DMA2D)
32-bit AHB BUS-MATRIX
FMC
AHBS
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
DMA/
FIFO
FIFO
AXIM
D-Cache
32KB
MDMA
DMA/
FIFO
8 Stream 8 Stream
FIFOs
FIFOs
AXI/AHB12 (275MHz)
ETM
I-Cache
32KB
DMA2
(275MHz)
PHY
ETHER
SDMMC2 OTG_HS
MAC
AHB1 (275
TRACECLK
TRACED[3:0]
JTAG/SW
128 KB AXI
SRAM
AHB2 (275MHz)
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWDIO, JTDO
DMA1
Shared AXI
I-TCM 192KB
AHBP
OCTOSPIM
D-TCM
64KB
D[7:0],DP, DM, STP,
D123DIR, NXT,ULPI:CK
D0DIR, , D[7:0], DIR,
CMD, CKas AF ID, VBUS
32b
TIM2
CH[4;1], ETR as AF
16b
TIM3
CH[4;1], ETR as AF
16b
TIM4
CH[4;1], ETR as AF
32b
TIM5
CH[4;1], ETR as AF
32b
TIM23
CH[4;1], ETR as AF
32b
TIM24
CH[4;1], ETR as AF
16b
TIM12
CH[2;1] as AF
16b
TIM13
CH1 as AF
16b
TIM14
CH1 as AF
AHB/APB
USART2
RX, TX, CK, CTS, RTS, DE as A
USART3
FIFO
AHB4
USART10
RX, TX, CK, CTS, RTS, DE as AF
USART6
16b
16b
A P B 10 MHz
3
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SCL, SDA, SMBA as AF
I2C3/SMBUS
I2C5/SMBUS
SCL, SDA, SMBA as AF
MDIOS
MDC, MDIO as AF
TT-FDCAN1
FDCAN2
FDCAN3
16 KB SRAM
4 KB BKP
RAM
SPDIFRX1
HDMI-CEC
GPIO PORTJ,K
16b
RCC
Reset &
control
SAI4
COMP1&2
LPTIM5
16b
OUT as AF
LPTIM4
16b
OUT as AF
LPTIM3
16b
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
RX, TX, CK, CTS, RTS as AF
LPUART1
IN1, IN2, ETR, OUT as AF
LPTIM2
16b
AHB/APB
VREF
IN1, IN2, ETR, OUT as AF
VINM, VINP, VOUT as AF
OPAMP2
VINM, VINP, VOUT as AF
Voltage
regulator
3.3 to 1.2V
@VDD
IWDG
HSI RC
HSI
HSI48
HSI48 RC
CSI RC
CSI
LSI
LSI RC
VDD
VSS
VCAP, VDDLDO
VBAT
XTAL 32 kHz
Temperature
sensor
CEC as AF
OUT1, OUT2 as AF
LPTIM1
@VSW
SYSCFG
EXTI WKUP
IN[1:4] as AF
OPAMP1
LS
OUT as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
@VDD
VCORE BBgen + POWER MNGT
PWRCTRL
GPIO PORTA.. H
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
USBCR
DAC
PA..H[15:0]
SCL, SDA, SMBA as AF
CRC
ADC3
PJ,PK[11:0]
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
HSEM
RX, TX, CTS, RTS, DE as AF
SPI2/I2S2
I2C2/SMBUS
RTC
Backup registers
LS
Up to 17 analog inputs
Some common to ADC1 and 2
TIM1/PWM
TIM8/PWM
AHB4 (275MHz)
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
USART1
RX, TX, CTS, RTS, DE as AF
UART8
SPI3/I2S3
RAM
I/F
32-bit AHB BUS-MATRIX
APB4
(max)
APB4
138138MHz
MHz (max)
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
DAP
RX, TX, CTS, RTS, DE as AF
UART7
FIFO
RX, TX, CK, CTS, RTS, DE as AF
BDMA
AHB4
RX, TX, CK, CTS, RTS, DE as AF
DMA
Mux2
RX, TX, CTS, RTS, DE as AF
UART5
I2C1/SMBUS
APB1 138MHz (max)
UART9
10 KB SRAM
SPI1/I2S1
AHB4
RX, TX, CTS, RTS, DE as AF
SPI4
AHB4_MEMD3 (275MHz)
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TIM15
AHB4 (275MHz)
MOSI, MISO, SCK, NSS as AF
RX, TX, CK, CTS, RTS, DE as A
UART4
Digital filter
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
TIM17
TIM16
AHB4
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
SPI5
APB2 138 MHz (max)
MOSI, MISO, SCK, NSS as AF
SAI1
AHB4
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
DFSDM
APB4 138 MHz (max)
CKOUT, DATIN[7:0], CKIN[7:0]
AWU
OSC32_IN
OSC32_OUT
TS, TAMP1, TAMP3,
OUT, REFIN
@VDD
XTAL OSC
4- 48 MHz
PLL1+PLL2+PLL3
OSC_IN
OSC_OUT
@VDD
POR
reset
Int
SUPPLY SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[1;2;4;6]
MSv52561V3
16/234
DS13313 Rev 3
STM32H723xE/G
Description
Table 1. STM32H723xE/G features and peripheral counts
STM32H723 STM32H723 STM32H723 STM32H723
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Peripherals
Flash memory (Kbytes)(1)
SRAM (Kbytes)
1024 / 512
1024 / 512
SRAM mapped onto AXI bus
128
SRAM1 (D2 domain)
16
SRAM2 (D2 domain)
16
SRAM4 (D3 domain)
16
RAM shared between ITCM and AXI (Kbytes)
192
ITCM RAM (instruction)
64
DTCM RAM (data)
128
TCM RAM (Kbytes)
Backup SRAM (Kbytes)
1024 / 512
1024 / 512
4
Interface
1
NOR Flash
memory/RAM
controller
-
-
yes
yes
Multiplexed I/O
NOR Flash
memory
yes
yes
yes
yes
16-bit NAND
Flash memory
yes
yes
yes
yes
16-bit SDRAM
controller
-
-
yes
yes
GPIO
80
80
112
114
Octo-SPI interface
1
1
2
2
FMC
OTFDEC
no
CORDIC
yes
FMAC
yes
Timers
Wakeup pins
General purpose 32 bits
4
4
4
4
General purpose 16 bits
10
10
10
10
Advanced control
(PWM)
2
2
2
2
Basic
2
2
2
2
Low-power
5
5
5
5
RTC
1
1
1
1
Window watchdog /
independent watchdog
2
2
2
2
4
4
4
4
DS13313 Rev 3
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52
Description
STM32H723xE/G
Table 1. STM32H723xE/G features and peripheral counts (continued)
STM32H723 STM32H723 STM32H723 STM32H723
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Peripherals
Tamper pins
2
2
Random number generator
yes
Cryptographic accelerator
no
SPI / I2S
5/4
6/4
6/4
5
5
5
5
USART/UART/
LPUART
5/5/1
5/5/1
5/5/1
5/5/1
SAI/PDM
2/1(2)
2/1(2)
2/1
2/1
SPDIFRX
1
HDMI-CEC
1
SWPMI
1
MDIO
1
SDMMC
2
FDCAN/TT-FDCAN
2/1
2/1
2/1
2/1
USB [OTG_HS(ULPI)/FS(PHY)]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
Ethernet [MII/RMII]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
yes
yes
Camera interface/PSSI
LCD-TFT
yes
yes
yes
Chrom-ART Accelerator (DMA2D)
yes
Number of ADCs
16-bit ADCs
2
Number of direct
channelsADC1/ADC2
2/2
0
0
2/2
Number of fast channels
ADC1/ADC2
3/2
3/2
4/3
4/3
Number of slow channels
ADC1/ADC2
9/8
11/10
12/11
12/11
Number of ADCs
12-bit ADCs
1
Number of direct channels
2
2
2
2
Number of fast channels
6
2
6
6
Number of slow channels
9
0
4
9
Present in IC
12-bit DAC
DFSDM
18/234
2
5/4
I2C
Communication
interfaces
2
yes
Number of channels
2
Comparators
2
Operational amplifiers
2
Present in IC
yes
DS13313 Rev 3
STM32H723xE/G
Description
Table 1. STM32H723xE/G features and peripheral counts (continued)
Peripherals
STM32H723 STM32H723 STM32H723 STM32H723
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Maximum CPU frequency
USB separate supply pad
USB internal regulator
550 MHz
yes
-
yes
yes
-
-
-
-
-
-
LDO
yes
SMPS step-down converter
Operating voltage
Operating
temperatures
Package
-
-
1.62 to
3.6 V
1.71 to
3.6 V
1.62 to 3.6 V
Ambient temperature
-40°C to +85°C
Junction temperature
-40°C to +125°C
TFBGA100
LQFP100
LQFP144
UFBGA144
1. STM32H723xGy products have 1024 Kbytes of Flash memory, whereas STM32H723xEy products have 512 Kbytes
2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7: STM32H723 pin
and ball descriptions.
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52
Functional overview
STM32H723xE/G
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache)
•
64-bit AXI interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H723xE/G family.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H723xE/G devices embed up to 1 Mbyte of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
one Flash word (8 words, 32 bytes or 256 bits)
•
10 ECC bits (single-error correction and double-error detection).
The Flash memory is organized as follows:
3.3.2
•
up to 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
•
128 Kbytes of system Flash memory from which the device can boot
•
2 Kbytes (64 Flash words) of user option bytes for user configuration
Embedded SRAM
All devices feature:
•
from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain
•
SRAM1 mapped on D2 domain: 16 Kbytes
•
SRAM2 mapped on D2 domain: 16 Kbytes
•
SRAM4 mapped on D3 domain: 16 Kbytes
•
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the
Cortex®-M7CPU(AHBSAHBP):
–
64 to 256 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected
above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte
granularity.
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52
Functional overview
STM32H723xE/G
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
7 ECC bits are added per 32-bit word.
•
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
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DS13313 Rev 3
STM32H723xE/G
3.4
Functional overview
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space
•
All RAM address space: ITCM, DTCM RAMs and SRAMs
•
The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to
application note AN2606 “STM32 microcontroller System memory Boot mode” for details.
3.5
CORDIC co-processor (CORDIC)
The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
CORDIC features
•
24-bit CORDIC rotation engine
•
Circular and Hyperbolic modes
•
Rotation and Vectoring modes
•
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
Programmable precision up to 20-bit
•
Fast convergence: 4 bits per clock cycle
•
Supports 16-bit and 32-bit fixed point input and output formats
•
Low latency AHB slave interface
•
Results can be read as soon as ready without polling or interrupt
•
DMA read and write channels
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52
Functional overview
3.6
STM32H723xE/G
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
FMAC features
•
16 x 16-bit multiplier
•
24+2-bit accumulator with addition and subtraction
•
16-bit input and output data
•
256 x 16-bit local memory
•
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
Input and output sample buffers can be circular
•
Buffer “watermark” feature reduces overhead in interrupt mode
•
Filter functions: FIR, IIR (direct form 1)
•
AHB slave interface
•
DMA read and write data channels
3.7
Power supply management
3.7.1
Power supply scheme
STM32H723xE/G power supply voltages are the following:
24/234
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•
VDD33USB: allows the support of a VDD supply different from 3.3 V while powering the
USB transceiver with 3.3V on VDD33USB.
•
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•
VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The
VCORE domain is split into the following power domains that can be independently
switch off.
–
D1 domain containing some peripherals and the Cortex®-M7 core
–
D2 domain containing a large part of the peripherals
–
D3 domain containing some peripherals and the system control
DS13313 Rev 3
STM32H723xE/G
Functional overview
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
•
When VDD is below VDDmin, other power supplies (VDDA, VDD33USB) must remain
below VDD + 300 mV.
•
When VDD is above VDDmin, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
Figure 2. Power-up/power-down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB.
3.7.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
DS13313 Rev 3
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52
Functional overview
3.7.3
STM32H723xE/G
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
•
3.8
Run mode (VOS0 to VOS3)
–
Scale 0: boosted performance
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The
peripheral functionality is disabled but wakeup from Stop mode is possible through
GPIO or asynchronous interrupt.
Low-power strategy
There are several ways to reduce power consumption on STM32H723xE/G:
•
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
•
Save power when the CPU is idle, by selecting among the available low-power modes
according to the user application needs. This allows the best compromise between
short startup time and low power consumption to be achieved, according to the
available wakeup sources.
The devices feature several low-power modes:
•
CSleep (CPU clock stopped)
•
CStop (CPU sub-system clock stopped)
•
DStop (Domain bus matrix clock stopped)
•
Stop (System clock stopped)
•
DStandby (Domain powered down)
•
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
26/234
DS13313 Rev 3
STM32H723xE/G
Functional overview
Table 2. System versus domain low-power mode
System power mode
D1 domain power mode
D2 domain power mode
D3 domain power mode
Run
DRun/DStop/DStandby
DRun/DStop/DStandby
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
3.9
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), thus the system frequency can be changed without modifying the
baudrate.
3.9.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
•
Internal oscillators:
–
64 MHz HSI clock
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
DS13313 Rev 3
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52
Functional overview
3.9.2
STM32H723xE/G
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
3.10
•
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Window watchdog
•
Independent watchdog
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.11
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
the interconnection of bus masters with bus slaves (see Figure 3).
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DS13313 Rev 3
STM32H723xE/G
Figure 3. STM32H723xE/G bus matrix
AHBS
OR
DMA2D
LTDC
D1-to-D2 AHB
DMA2_MEM
MDMA
DMA1_MEM
SDMMC1
DMA2
Ethernet SDMMC2 USBHS1
MAC
DMA2_PERIPH
DMA1
AHBP
AXIM
I$
D$
32KB 32KB
ITCM
64 Kbyte
ITCM
192 Kbyte
DTCM
128 Kbyte
DMA1_PERIPH
CPU
Cortex-M7
AXI SRAM
192K byte
SRAM1 16
Kbyte
SRAM2 16
Kbyte
Flash A
Up to 1 Mbyte
AHB1
DS13313 Rev 3
AXI SRAM
128 Kbyte
AHB2
OCTOSPI1
OCTOSPI2
APB1
FMC
APB2
AHB3
APB3
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
Legend
32-bit bus
AHB4
TCM AHB
AXI
APB
29/234
64-bit bus
Master interface
Bus multiplexer
Slave interface
APB4
SRAM4
16 Kbyte
Backup
SRAM
4 Kbyte
MSv65313V1
Functional overview
BDMA
32-bit AHB bus matrix
D3 domain
Functional overview
3.12
STM32H723xE/G
DMA controllers
The devices feature four DMA instances and a DMA request router to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
•
A DMA request multiplexer (DMAMUX)
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing
managing the DMA requests with a high flexibility, maximizing the number of DMA
requests that run concurrently, as well as generating DMA requests from peripheral
output trigger or DMA event.
3.13
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation.
It can perform the following operations:
•
Filling a part or the whole of a destination image with a specific color
•
Copying a part or the whole of a source image into a part or the whole of a destination
•
image
•
Copying a part or the whole of a source image into a part or the whole of a destination
•
image with a pixel format conversion
•
Blending a part and/or two complete source images with different pixel format and copy
•
the result into a part or the whole of a destination image with a different color format.
•
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel
with indexed or direct color mode, including block based YCbCr to handle JPEG
decoder output.
•
The DMA2D has its own dedicated memories for CLUTs (color look-up tables).
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automated and are running independently from the CPU or the
DMAs.
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DS13313 Rev 3
STM32H723xE/G
3.14
Functional overview
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.15
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events
and 54 direct events.
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.16
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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52
Functional overview
3.17
STM32H723xE/G
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
3.18
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
Octo-SPI memory interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal
SPI memories. The STM32H723xE/G embeds two separate Octo-SPI interfaces.
Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of
single/dual/quad/octal SPI over the same bus can be achieved using the integrated OctoSPI I/O manager (OCTOSPIM).
The OCTOSPI can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers
•
Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory supporting both read and write operations.
The OCTOSPI supports two frame formats supported by most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and
Hyper Flash memories.
Multi chip package (MCP) combining any of the above mentioned memory types can also
be supported.
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•
The classical frame format with the command, address, alternate byte, dummy cycles
and data phase
•
The HyperBus™ frame format.
DS13313 Rev 3
STM32H723xE/G
3.19
Functional overview
Analog-to-digital converters (ADCs)
STM32H723xE/G devices embed three analog-to-digital converters, two of 16-bit resolution,
and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14,
12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some, or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers.
3.20
Temperature sensor
STM32H723xE/G devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 to +125°C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.21
Digital temperature sensor (DTS)
STM32H723xE/G devices embed a sensor that converts the temperature into a square
wave the frequency of which is proportional to the temperature. The PCLK or the LSE clock
can be used as the reference clock for the measurements. A formula given in the product
reference manual allows calculation of the temperature according to the measured
frequency stored in the DTS_DR register.
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52
Functional overview
3.22
STM32H723xE/G
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
3.23
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
external triggers for conversion
•
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
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DS13313 Rev 3
STM32H723xE/G
3.24
Functional overview
Ultra-low-power comparators (COMP)
STM32H723xE/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
An external I/O
•
A DAC output channel
•
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.25
Operational amplifiers (OPAMP)
STM32H723xE/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
One positive input connected to DAC
•
Output connected to internal ADC
•
Low input bias current down to 1 nA
•
Low input offset voltage down to 1.5 mV
•
Gain bandwidth up to 7.3 MHz
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
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52
Functional overview
3.26
STM32H723xE/G
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
up to 24-bit output data resolution, signed output data format
•
automatic data offset correction (offset stored in register by user)
•
continuous or single conversion
•
start-of-conversion triggered by:
•
•
•
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internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
DS13313 Rev 3
STM32H723xE/G
•
Functional overview
extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
•
DMA capability to read the final conversion data
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
•
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Pulse skipper feature to support beamforming applications (delay-line like behavior).
Table 3. DFSDM implementation
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
DS13313 Rev 3
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52
Functional overview
3.27
STM32H723xE/G
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
3.28
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports Continuous mode or Snapshot (a single frame) mode
•
Capability to automatically crop the image
PSSI
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The main PSSI features are:
•
Slave mode operation
•
8- or 16-bit parallel data input or output
•
8-word (32-byte) FIFO
•
Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data is
valid or, the receiver to indicate when it is ready to sample the data, or both.
The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore
cannot be used simultaneously with the DCMI.
3.29
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024 x 768) resolution with the following features:
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•
2 display layers with dedicated FIFO (64x64-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
•
AXI master interface with burst of 16 words
DS13313 Rev 3
STM32H723xE/G
3.30
Functional overview
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as
a NIST SP 800-90B compliant entropy source.
The RNG true random number generator has been tested using German BSI statistical tests
of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite.
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52
Functional overview
3.31
STM32H723xE/G
Timers and watchdogs
The devices include two advanced-control timers, twelve general-purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Timer
type
Advanced
-control
Timer
TIM1,
TIM8
TIM2,
TIM5,
TIM23,
TIM24
TIM3,
TIM4
TIM12
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
TIM15
TIM16,
TIM17
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Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
Yes
137.5
275
32-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
137.5
275
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
137.5
275
16-bit
Up
Any
integer
between 1
and
65536
No
2
No
137.5
275
Up
Any
integer
between 1
and
65536
No
1
No
137.5
275
Up
Any
integer
between 1
and
65536
Yes
2
1
137.5
275
Up
Any
integer
between 1
and
65536
Yes
1
1
137.5
275
General
purpose
TIM13,
TIM14
Complementary
output
16-bit
16-bit
16-bit
DS13313 Rev 3
STM32H723xE/G
Functional overview
Table 4. Timer feature comparison (continued)
Timer
type
Timer
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and
65536
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32,
64, 128
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
Yes
0
No
137.5
275
No
0
No
137.5
275
1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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52
Functional overview
3.31.1
STM32H723xE/G
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (Edge- or Center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.31.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H723xE/G
devices (see Table 4: Timer feature comparison for differences).
•
TIM2, TIM3, TIM4, TIM5, TIM23, TIM24
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5,
TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit
auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent
channels for input capture/output compare, PWM or One-pulse mode output. This
gives up to 24 input capture/output compare/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together,
or with the other general-purpose timers and the advanced-control timers TIM1 and
TIM8 via the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request
generation. They are capable of handling quadrature (incremental) encoder signals
and the digital outputs from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5,
TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases.
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DS13313 Rev 3
STM32H723xE/G
3.31.3
Functional overview
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.31.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.31.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / One-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
A window option allows the device to be reset when a reload operation is made too early
after the previous reload.
3.31.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.31.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
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52
Functional overview
3.32
STM32H723xE/G
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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STM32H723xE/G
3.33
Functional overview
Inter-integrated circuit interface (I2C)
STM32H723xE/G devices embed five I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
3.34
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H723xE/G devices have five embedded universal synchronous receiver transmitters
(USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous
receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 5:
USART features for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
17 Mbit/s.
USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO
7816 compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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52
Functional overview
STM32H723xE/G
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6/10
UART4/5/7/8/9
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
16
1. X = supported.
3.35
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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DS13313 Rev 3
STM32H723xE/G
Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.36
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available.
They can be operated in Master or Slave mode, in Simplex communication modes, and can
be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6
which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are
supported. When either or both of the I2S interfaces is/are configured in Master mode, the
master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA
capability.
3.37
Serial audio interfaces (SAI)
The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono
audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF
output is available when the audio block is configured as a transmitter. To bring this level of
flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each
block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
DS13313 Rev 3
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52
Functional overview
3.38
STM32H723xE/G
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.39
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
Full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
48/234
DS13313 Rev 3
STM32H723xE/G
3.40
Functional overview
Management data input/output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
3.41
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from Stop mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.42
Controller area network (FDCAN1, FDCAN2, FDCAN3)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the three modules - FDCAN1 FDCAN2 and FDCAN3.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
DS13313 Rev 3
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52
Functional overview
3.43
STM32H723xE/G
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral
that supports both full-speed and high-speed operations. It integrates the transceivers for
full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external
PHY device connected to the ULPI is required.
The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
3.44
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
50/234
DS13313 Rev 3
STM32H723xE/G
Functional overview
The devices include the following features:
3.45
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.46
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
Breakpoint debugging
•
Code execution tracing
•
Software instrumentation
•
JTAG debug port
•
Serial-wire debug port
•
Trigger input and output
•
Serial-wire trace port
•
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The trace port performs data capture for logging and analysis.
DS13313 Rev 3
51/234
52
Memory mapping
4
STM32H723xE/G
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
52/234
DS13313 Rev 3
STM32H723xE/G
5
Pinouts, pin descriptions and alternate functions
Pinouts, pin descriptions and alternate functions
Figure 4. TFBGA100 pinout
1
2
3
4
5
6
7
8
9
10
A
PC14OSC32_IN
PC13
PE2
PB9
PB7
PB4
PB3
PA15
PA14
PA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
PH0-OSC_IN
VSS
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
PH1OSC_OUT
VDD
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PC2_C
PE6
VSS
VSS
VSS
VCAP
PD1
PC9
PC7
F
PC0
PC1
PC3_C
VDD
VDD
VDD33USB
PDR_ON
VCAP
PC8
PC6
G
VSSA
PA0
PA4
PC4
PB2
PE10
PE14
PD15
PD11
PB15
H
VDDA
PA1
PA5
PC5
PE7
PE11
PE15
PD14
PD10
PB14
J
VSS
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDD
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
MSv52520V1.
1. The above figure shows the package top view.
DS13313 Rev 3
53/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 5. LQFP100 pinout
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VCAP
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2_C
17
59
PD12
PC3_C
18
58
PD11
VSSA
19
57
PD10
VREF+
20
56
PD9
VDDA
21
55
PD8
PA0
22
54
PB15
PA1
23
53
PB14
PA2
24
52
PB13
PA3
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
LQFP100
MSv52521V1.
1. The above figure shows the package top view.
54/234
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 6. LQFP144 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
MSv52522V1.
1. The above figure shows the package top view.
DS13313 Rev 3
55/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Figure 7. UFBGA144 ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PC13
PE3
PE2
PE1
PE0
PB4
PB3
PD6
PD7
PA15
PA14
PA13
B
PC14OSC32_IN
PE4
PE5
PE6
PB9
PB5
PG15
PG12
PD5
PC11
PC10
PA12
C
PC15OSC32_OUT
VBAT
PF0
PF1
PB8
PB6
PG14
PG11
PD4
PC12
VDD33USB
PA11
D
PH0-OSC_IN
VSS
VDD
PF2
BOOT0
PB7
PG13
PG10
PD3
PD1
PA10
PA9
E
PH1OSC_OUT
PF3
PF4
PF5
PDR_ON
VSS
VSS
PG9
PD2
PD0
PC9
PA8
F
NRST
PF7
PF6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PC8
PC7
G
PF10
PF9
PF8
VSS
VDD
VDD
VDD
VSS
VCAP
VSS
PG8
PC6
H
PC0
PC1
PC2
PC3
VSS
VSS
VCAP
PE11
PD11
PG7
PG6
PG5
J
VSSA
PA0
PA4
PC4
PB2
PG1
PE10
PE12
PD10
PG4
PG3
PG2
K
VREF-
PA1
PA5
PC5
PF13
PG0
PE9
PE13
PD9
PD13
PD14
PD15
L
VREF+
PA2
PA6
PB0
PF12
PF15
PE8
PE14
PD8
PD12
PB14
PB15
M
VDDA
PA3
PA7
PB1
PF11
PF14
PE7
PE15
PB10
PB11
PB12
PB13
MSv52523V1.
1. The above figure shows the package top view.
Table 6. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
I/O structure
Notes
56/234
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 6. Legend/abbreviations used in the pinout table (continued)
Name
Pin functions
Abbreviation
Definition
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 7. STM32H723 pin and ball descriptions
1
A3
PE2
I/O
FT_h
-
B3
2
2
A2
PE3
I/O
FT_h
-
TRACED0, TIM15_BKIN, SAI1_SD_B,
SAI4_SD_B, USART10_TX, FMC_A19,
EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3, TIM15_CH1N,
SPI4_NSS, SAI1_FS_A, SAI4_FS_A,
SAI4_D2, FMC_A20,
DCMI_D4/PSSI_D4, LCD_B0,
EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2, FMC_A21,
DCMI_D6/PSSI_D6, LCD_G0,
EVENTOUT
-
-
C3
D3
3
4
3
4
UFBGA144
1
LQFP144
A3
TRACECLK, SAI1_CK1,
USART10_RX, SPI4_SCK,
SAI1_MCLK_A, SAI4_MCLK_A,
OCTOSPIM_P1_IO2, SAI4_CK1,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin type
Pin number
B2
B3
Pin name (function
after reset)
PE4
PE5
I/O
I/O
FT_h
FT_h
Additional
functions
-
E3
5
5
B4
PE6
I/O
FT_h
-
TRACED3, TIM1_BKIN2, SAI1_D1,
TIM15_CH2, SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1, SAI4_MCLK_B,
TIM1_BKIN2_COMP12, FMC_A22,
DCMI_D7/PSSI_D7, LCD_G1,
EVENTOUT
B2
6
6
C2
VBAT
S
-
-
-
-
A2
7
7
A1
PC13
I/O
FT
-
EVENTOUT
RTC_TAMP1/
RTC_TS,
WKUP4
A1
8
8
B1
PC14-OSC32_IN
I/O
FT
-
EVENTOUT
OSC32_IN
B1
9
9
C1
PC15-OSC32_OUT
I/O
FT
-
EVENTOUT
OSC32_OUT
DS13313 Rev 3
57/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
Pin name (function
after reset)
Pin type
I/O structure
Notes
Pin number
Alternate functions
-
-
10
C3
PF0
I/O
FT_fh
-
I2C2_SDA(boot), I2C5_SDA,
OCTOSPIM_P2_IO0, FMC_A0,
TIM23_CH1, EVENTOUT
-
-
-
11
C4
PF1
I/O
FT_fh
-
I2C2_SCL(boot), I2C5_SCL,
OCTOSPIM_P2_IO1, FMC_A1,
TIM23_CH2, EVENTOUT
-
-
-
12
D4
PF2
I/O
FT_h
-
I2C2_SMBA, I2C5_SMBA,
OCTOSPIM_P2_IO2, FMC_A2,
TIM23_CH3, EVENTOUT
-
-
-
13
E2
PF3
I/O
FT_ha
-
OCTOSPIM_P2_IO3, FMC_A3,
TIM23_CH4, EVENTOUT
ADC3_INP5
-
-
14
E3
PF4
I/O
FT_ha
-
OCTOSPIM_P2_CLK, FMC_A4,
EVENTOUT
ADC3_INN5,
ADC3_INP9
-
-
15
E4
PF5
I/O
FT_ha
-
OCTOSPIM_P2_NCLK, FMC_A5,
EVENTOUT
ADC3_INP4
-
10
16
-
VSS
S
-
-
-
-
-
11
17
-
VDD
S
-
-
-
-
-
-
18
F3
PF6
I/O
FT_ha
-
TIM16_CH1, FDCAN3_RX, SPI5_NSS,
SAI1_SD_B, UART7_RX, SAI4_SD_B,
OCTOSPIM_P1_IO3, TIM23_CH1,
EVENTOUT
ADC3_INN4,
ADC3_INP8
-
TIM17_CH1, FDCAN3_TX, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
SAI4_MCLK_B, OCTOSPIM_P1_IO2,
TIM23_CH2, EVENTOUT
ADC3_INP3
-
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B, TIM13_CH1,
OCTOSPIM_P1_IO0, TIM23_CH3,
EVENTOUT
ADC3_INN3,
ADC3_INP7
ADC3_INP2
-
-
-
-
19
20
F2
G3
PF7
PF8
I/O
I/O
FT_ha
FT_ha
Additional
functions
-
-
21
G2
PF9
I/O
FT_ha
-
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS, SAI4_FS_B,
TIM14_CH1, OCTOSPIM_P1_IO1,
TIM23_CH4, EVENTOUT
-
-
22
G1
PF10
I/O
FT_ha
-
TIM16_BKIN, SAI1_D3, PSSI_D15,
OCTOSPIM_P1_CLK, SAI4_D3,
DCMI_D11/PSSI_D11, LCD_DE,
EVENTOUT
ADC3_INN2,
ADC3_INP6
C1
12
23
D1
PH0-OSC_IN
I/O
FT
-
EVENTOUT
OSC_IN
58/234
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
Pin name (function
after reset)
Pin type
I/O structure
Notes
Pin number
Alternate functions
D1
13
24
E1
PH1-OSC_OUT
I/O
FT
-
EVENTOUT
OSC_OUT
E1
14
25
F1
NRST
I/O
RST
-
-
-
-
FMC_D12/FMC_AD12,
DFSDM1_CKIN0, DFSDM1_DATIN4,
SAI4_FS_B, FMC_A25,
OTG_HS_ULPI_STP, LCD_G2,
FMC_SDNWE, LCD_R5, EVENTOUT
ADC123_INP10
-
TRACED0, SAI4_D1, SAI1_D1,
DFSDM1_DATIN0, DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, SAI1_SD_A,
SAI4_SD_A, SDMMC2_CK,
OCTOSPIM_P1_IO4, ETH_MDC,
MDIOS_MDC, LCD_G5, EVENTOUT
ADC123_INN10,
ADC123_INP11,
RTC_TAMP3,
WKUP6
ADC123_INN11,
ADC123_INP12
F1
F2
15
16
26
27
-
-
-
E2
17
28
(1)
(1)
(1)
H1
H2
PC0
PC1
I/O
I/O
FT_ha
FT_ha
Additional
functions
H3
PC2
I/O
FT_a
-
PWR_DEEPSLEEP, DFSDM1_CKIN1,
OCTOSPIM_P1_IO5,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OCTOSPIM_P1_IO2,
OTG_HS_ULPI_DIR, ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
-
PC2_C
AN
A
TT_a
-
-
ADC3_INN1,
ADC3_INP0
ADC12_INN12,
ADC12_INP13
H4
PC3
I/O
FT_a
-
PWR_SLEEP, DFSDM1_DATIN1,
OCTOSPIM_P1_IO6,
SPI2_MOSI/I2S2_SDO,
OCTOSPIM_P1_IO0,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK, FMC_SDCKE0,
EVENTOUT
(1)
-
PC3_C
AN
A
TT_a
-
-
ADC3_INP1
-
30
-
VDD
S
-
-
-
-
G1
19
31
J1
VSSA
S
-
-
-
-
-
-
-
K1
VREF-
S
-
-
-
-
-
20
32
L1
VREF+
S
-
-
-
-
H1
21
33
M1
VDDA
S
-
-
-
-
-
-
-
F3
18
29
-
(1)
(1)
DS13313 Rev 3
59/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
H2
J2
22
23
24
35
36
J2
K2
L2
PA0
PA1
PA2
I/O
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
34
Pin name (function
after reset)
FT_ha
FT_ha
FT_ha
Notes
G2
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
TIM2_CH1/TIM2_ETR, TIM5_CH1,
TIM8_ETR, TIM15_BKIN,
SPI6_NSS/I2S6_WS,
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI4_SD_B, ETH_MII_CRS,
FMC_A19, EVENTOUT
ADC1_INP16,
WKUP1
-
TIM2_CH2, TIM5_CH2, LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX, OCTOSPIM_P1_IO3,
SAI4_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII_REF_C
LK, OCTOSPIM_P1_DQS, LCD_R2,
EVENTOUT
ADC1_INN16,
ADC1_INP17
-
TIM2_CH3, TIM5_CH3, LPTIM4_OUT,
TIM15_CH1, OCTOSPIM_P1_IO0,
USART2_TX(boot), SAI4_SCK_B,
ETH_MDIO, MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP2
ADC12_INP15
K2
25
37
M2
PA3
I/O
FT_ha
-
TIM2_CH4, TIM5_CH4, LPTIM5_OUT,
TIM15_CH2, I2S6_MCK,
OCTOSPIM_P1_IO2,
USART2_RX(boot), LCD_B2,
OTG_HS_ULPI_D0, ETH_MII_COL,
OCTOSPIM_P1_CLK, LCD_B5,
EVENTOUT
-
26
38
-
VSS
S
-
-
-
-
-
27
39
-
VDD
S
-
-
-
-
-
D1PWREN, TIM5_ETR,
SPI1_NSS(boot)/I2S1_WS,
SPI3_NSS/I2S3_WS, USART2_CK,
SPI6_NSS/I2S6_WS,
FMC_D8/FMC_AD8,
DCMI_HSYNC/PSSI_DE,
LCD_VSYNC, EVENTOUT
ADC12_INP18,
DAC1_OUT1
-
D2PWREN, TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK(boot)/I2S1_CK,
SPI6_SCK/I2S6_CK,
OTG_HS_ULPI_CK,
FMC_D9/FMC_AD9, PSSI_D14,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
G3
H3
60/234
28
29
40
41
J3
K3
PA4
PA5
I/O
I/O
TT_ha
TT_ha
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
K3
G4
H4
J4
K4
G5
30
31
32
33
34
35
36
43
44
45
46
47
48
L3
M3
J4
K4
L4
M4
J5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
42
Pin name (function
after reset)
FT_ha
TT_ha
TT_ha
TT_ha
TT_ha
FT_ha
FT_ha
Notes
J3
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
TIM1_BKIN, TIM3_CH1, TIM8_BKIN,
SPI1_MISO(boot)/I2S1_SDI,
OCTOSPIM_P1_IO3,
SPI6_MISO/I2S6_SDI, TIM13_CH1,
TIM8_BKIN_COMP12, MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK/PSSI_PDCK, LCD_G2,
EVENTOUT
ADC12_INP3
-
TIM1_CH1N, TIM3_CH2, TIM8_CH1N,
SPI1_MOSI(boot)/I2S1_SDO,
SPI6_MOSI/I2S6_SDO, TIM14_CH1,
OCTOSPIM_P1_IO2,
ETH_MII_RX_DV/ETH_RMII_CRS_DV,
FMC_SDNWE, LCD_VSYNC,
EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
-
PWR_DEEPSLEEP, FMC_A22,
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX1_IN3, SDMMC2_CKIN,
ETH_MII_RXD0/ETH_RMII_RXD0,
FMC_SDNE0, LCD_R7, EVENTOUT
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
-
PWR_SLEEP, SAI4_D3, SAI1_D3,
DFSDM1_DATIN2, PSSI_D15,
SPDIFRX1_IN4, OCTOSPIM_P1_DQS,
ETH_MII_RXD1/ETH_RMII_RXD1,
FMC_SDCKE0, COMP1_OUT,
LCD_DE, EVENTOUT
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
-
TIM1_CH2N, TIM3_CH3, TIM8_CH2N,
OCTOSPIM_P1_IO1,
DFSDM1_CKOUT, UART4_CTS,
LCD_R3, OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
-
TIM1_CH3N, TIM3_CH4, TIM8_CH3N,
OCTOSPIM_P1_IO0,
DFSDM1_DATIN1, LCD_R6,
OTG_HS_ULPI_D2, ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
-
RTC_OUT, SAI4_D1, SAI1_D1,
DFSDM1_CKIN1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO, SAI4_SD_A,
OCTOSPIM_P1_CLK,
OCTOSPIM_P1_DQS, ETH_TX_ER,
TIM23_ETR, EVENTOUT
COMP1_INP
DS13313 Rev 3
61/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
49
M5
PF11
I/O
FT_ha
-
-
-
50
L5
PF12
I/O
FT_ha
-
OCTOSPIM_P2_DQS, FMC_A6,
TIM24_CH2, EVENTOUT
ADC1_INN2,
ADC1_INP6
-
-
51
-
VSS
S
-
-
-
-
-
-
52
-
VDD
S
-
-
-
-
-
-
53
K5
PF13
I/O
FT_ha
-
DFSDM1_DATIN6, I2C4_SMBA,
FMC_A7, TIM24_CH3, EVENTOUT
ADC2_INP2
-
-
54
M6
PF14
I/O FT_fha
-
DFSDM1_CKIN6, I2C4_SCL, FMC_A8,
TIM24_CH4, EVENTOUT
ADC2_INN2,
ADC2_INP6
-
-
55
L6
PF15
I/O
FT_fh
-
I2C4_SDA, FMC_A9, EVENTOUT
-
-
-
56
K6
PG0
I/O
FT_h
-
OCTOSPIM_P2_IO4, UART9_RX,
FMC_A10, EVENTOUT
-
-
-
57
J6
PG1
I/O
TT_h
-
OCTOSPIM_P2_IO5, UART9_TX,
FMC_A11, EVENTOUT
OPAMP2_VINM
H5
37
58
M7
PE7
I/O
TT_ha
-
TIM1_ETR, DFSDM1_DATIN2,
UART7_RX, OCTOSPIM_P1_IO4,
FMC_D4/FMC_AD4, EVENTOUT
OPAMP2_VOUT,
COMP2_INM
OPAMP2_VINM
UFBGA144
-
LQFP144
-
SPI5_MOSI, OCTOSPIM_P1_NCLK,
SAI4_SD_B, FMC_NRAS,
DCMI_D12/PSSI_D12, TIM24_CH1,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin type
Pin number
Pin name (function
after reset)
Additional
functions
ADC1_INP2
J5
38
59
L7
PE8
I/O
TT_ha
-
TIM1_CH1N, DFSDM1_CKIN2,
UART7_TX, OCTOSPIM_P1_IO5,
FMC_D5/FMC_AD5, COMP2_OUT,
EVENTOUT
K5
39
60
K7
PE9
I/O
TT_ha
-
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
OCTOSPIM_P1_IO6,
FMC_D6/FMC_AD6, EVENTOUT
OPAMP2_VINP,
COMP2_INP
-
-
61
-
VSS
S
-
-
-
-
-
-
62
-
VDD
S
-
-
-
-
G6
40
63
J7
PE10
I/O
FT_ha
-
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS, OCTOSPIM_P1_IO7,
FMC_D7/FMC_AD7, EVENTOUT
COMP2_INM
-
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS(boot), SAI4_SD_B,
OCTOSPIM_P1_NCS,
FMC_D8/FMC_AD8, LCD_G3,
EVENTOUT
COMP2_INP
H6
62/234
41
64
H8
PE11
I/O
FT_ha
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
65
J8
PE12
I/O
FT_h
-
K6
43
66
K8
PE13
I/O
FT_h
-
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO(boot), SAI4_FS_B,
FMC_D10/FMC_AD10, COMP2_OUT,
LCD_DE, EVENTOUT
-
G7
44
67
L8
PE14
I/O
FT_h
-
TIM1_CH4, SPI4_MOSI(boot),
SAI4_MCLK_B, FMC_D11/FMC_AD11,
LCD_CLK, EVENTOUT
-
-
TIM1_BKIN, USART10_CK,
FMC_D12/FMC_AD12,
TIM1_BKIN_COMP12, LCD_R7,
EVENTOUT
-
-
TIM2_CH3, LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7, USART3_TX(boot),
OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3, ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
-
H7
J7
45
46
68
69
UFBGA144
42
LQFP144
J6
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK(boot), SAI4_SCK_B,
FMC_D9/FMC_AD9, COMP1_OUT,
LCD_B4, EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin type
Pin number
M8
M9
Pin name (function
after reset)
PE15
PB10
I/O
I/O
FT_h
FT_fh
Additional
functions
-
K7
47
70
M10
PB11
I/O
FT_f
-
TIM2_CH4, LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX(boot),
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMII_TX_EN,
LCD_G5, EVENTOUT
F8
48
71
H7
VCAP
S
-
-
-
-
-
49
-
-
VSS
S
-
-
-
-
-
50
72
-
VDD
S
-
-
-
-
-
TIM1_BKIN, OCTOSPIM_P1_NCLK,
I2C2_SMBA, SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1, USART3_CK,
FDCAN2_RX, OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TXD0,
OCTOSPIM_P1_IO0,
TIM1_BKIN_COMP12, UART5_RX,
EVENTOUT
-
K8
51
73
M11
PB12
I/O
FT_h
DS13313 Rev 3
63/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
H10
52
53
75
M12
L11
PB13
PB14
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
74
Pin name (function
after reset)
FT_h
FT_h
Notes
J8
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
TIM1_CH1N, LPTIM2_OUT,
OCTOSPIM_P1_IO2,
SPI2_SCK/I2S2_CK, DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FDCAN2_TX, OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TXD1,
SDMMC1_D0, DCMI_D2/PSSI_D2,
UART5_TX, EVENTOUT
-
-
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_DE,
UART4_RTS/UART4_DE,
SDMMC2_D0, FMC_D10/FMC_AD10,
LCD_CLK, EVENTOUT
-
-
G10
54
76
L12
PB15
I/O
FT_h
-
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX, SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2, UART4_CTS,
SDMMC2_D1, FMC_D11/FMC_AD11,
LCD_G7, EVENTOUT
K9
55
77
L9
PD8
I/O
FT_h
-
DFSDM1_CKIN3, USART3_TX(boot),
SPDIFRX1_IN2,
FMC_D13/FMC_AD13, EVENTOUT
-
J9
56
78
K9
PD9
I/O
FT_h
-
DFSDM1_DATIN3, USART3_RX(boot),
FMC_D14/FMC_AD14, EVENTOUT
-
H9
57
79
J9
PD10
I/O
FT_h
-
DFSDM1_CKOUT, USART3_CK,
FMC_D15/FMC_AD15, LCD_B3,
EVENTOUT
-
-
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
OCTOSPIM_P1_IO0, SAI4_SD_A,
FMC_A16/FMC_CLE, EVENTOUT
-
-
LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,
I2C4_SCL, FDCAN3_RX,
USART3_RTS/USART3_DE,
OCTOSPIM_P1_IO1, SAI4_FS_A,
FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12, EVENTOUT
-
G9
K10
64/234
58
59
80
81
H9
L10
PD11
PD12
I/O
I/O
FT_h
FT_fh
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
82
K10
PD13
I/O
FT_fh
-
-
-
83
-
VSS
S
-
-
-
-
-
-
84
-
VDD
S
-
-
-
-
H8
61
85
K11
PD14
I/O
FT_h
-
TIM4_CH3, UART8_CTS, UART9_RX,
FMC_D0/FMC_AD0, EVENTOUT
-
G8
62
86
K12
PD15
I/O
FT_h
-
TIM4_CH4, UART8_RTS/UART8_DE,
UART9_TX, FMC_D1/FMC_AD1,
EVENTOUT
-
-
-
87
J12
PG2
I/O
FT_h
-
TIM8_BKIN, TIM8_BKIN_COMP12,
FMC_A12, TIM24_ETR, EVENTOUT
-
-
-
88
J11
PG3
I/O
FT_h
-
TIM8_BKIN2, TIM8_BKIN2_COMP12,
FMC_A13, TIM23_ETR, EVENTOUT
-
-
-
89
J10
PG4
I/O
FT_h
-
TIM1_BKIN2, TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0, EVENTOUT
-
-
-
90
H12
PG5
I/O
FT_h
-
TIM1_ETR, FMC_A15/FMC_BA1,
EVENTOUT
-
-
-
91
H11
PG6
I/O
FT_h
-
TIM17_BKIN, OCTOSPIM_P1_NCS,
FMC_NE3, DCMI_D12/PSSI_D12,
LCD_R7, EVENTOUT
-
-
-
92
H10
PG7
I/O
FT_h
-
SAI1_MCLK_A, USART6_CK,
OCTOSPIM_P2_DQS, FMC_INT,
DCMI_D13/PSSI_D13, LCD_CLK,
EVENTOUT
-
-
UFBGA144
60
LQFP144
J10
LPTIM1_OUT, TIM4_CH2, I2C4_SDA,
FDCAN3_TX, OCTOSPIM_P1_IO3,
SAI4_SCK_A,
UART9_RTS/UART9_DE, FMC_A18,
DCMI_D13/PSSI_D13, EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin type
Pin number
Pin name (function
after reset)
Additional
functions
-
-
-
93
G11
PG8
I/O
FT_h
-
TIM8_ETR, SPI6_NSS/I2S6_WS,
USART6_RTS/USART6_DE,
SPDIFRX1_IN3, ETH_PPS_OUT,
FMC_SDCLK, LCD_G7, EVENTOUT
-
-
94
-
VSS
S
-
-
-
-
F6
-
95
C11
VDD33USB
S
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX, SDMMC1_D0DIR,
FMC_NWAIT, SDMMC2_D6,
SDMMC1_D6, DCMI_D0/PSSI_D0,
LCD_HSYNC, EVENTOUT
SWPMI_IO
F10
63
96
G12
PC6
I/O
FT_h
DS13313 Rev 3
65/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
F9
E9
D9
C9
D10
C10
B10
66/234
64
65
66
67
68
69
70
71
98
99
100
101
102
103
104
F12
F11
E11
E12
D12
D11
C12
B12
PC7
PC8
PC9
PA8
PA9
PA10
PA11
PA12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
97
Pin name (function
after reset)
FT_h
FT_h
FT_fh
FT_fh
FT_u
FT_u
FT_u
FT_u
Notes
E10
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
DBTRGIO, TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX, SDMMC1_D123DIR,
FMC_NE1, SDMMC2_D7, SWPMI_TX,
SDMMC1_D7, DCMI_D1/PSSI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1, TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE, FMC_INT,
SWPMI_RX, SDMMC1_D0,
DCMI_D2/PSSI_D2, EVENTOUT
-
-
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA(boot), I2S_CKIN,
I2C5_SDA, UART5_CTS,
OCTOSPIM_P1_IO0, LCD_G3,
SWPMI_SUSPEND, SDMMC1_D1,
DCMI_D3/PSSI_D3, LCD_B2,
EVENTOUT
-
-
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL(boot), I2C5_SCL,
USART1_CK, OTG_HS_SOF,
UART7_RX, TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6, EVENTOUT
-
-
TIM1_CH2, LPUART1_TX,
I2C3_SMBA, SPI2_SCK/I2S2_CK,
I2C5_SMBA, USART1_TX(boot),
ETH_TX_ER, DCMI_D0/PSSI_D0,
LCD_R5, EVENTOUT
OTG_HS_VBUS
-
TIM1_CH3, LPUART1_RX,
USART1_RX(boot), OTG_HS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1/PSSI_D1, LCD_B1,
EVENTOUT
-
-
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, LCD_R4, EVENTOUT
OTG_HS_DM
(boot)
-
TIM1_ETR,
LPUART1_RTS/LPUART1_DE,
SPI2_SCK/I2S2_CK, UART4_TX,
USART1_RTS/USART1_DE,
SAI4_FS_B, FDCAN1_TX,
TIM1_BKIN2, LCD_R5, EVENTOUT
OTG_HS_DP
(boot)
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
Pin name (function
after reset)
Pin type
I/O structure
Notes
Pin number
Alternate functions
A10
72
105
A12
PA13(JTMS/SWDIO)
I/O
FT
-
JTMS/SWDIO, EVENTOUT
-
E7
73
106
G9
VCAP
S
-
-
-
-
-
74
107
-
VSS
S
-
-
-
-
-
75
108
-
VDD
S
-
-
-
-
A9
76
109
A11
PA14(JTCK/SWCLK)
I/O
FT
-
JTCK/SWCLK, EVENTOUT
-
-
JTDI, TIM2_CH1/TIM2_ETR, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS(boot)/I2S3_WS,
SPI6_NSS/I2S6_WS,
UART4_RTS/UART4_DE, LCD_R3,
UART7_TX, LCD_B6, EVENTOUT
-
-
DFSDM1_CKIN5, I2C5_SDA,
SPI3_SCK(boot)/I2S3_CK,
USART3_TX, UART4_TX,
OCTOSPIM_P1_IO1, LCD_B1,
SWPMI_RX, SDMMC1_D2,
DCMI_D8/PSSI_D8, LCD_R2,
EVENTOUT
-
-
DFSDM1_DATIN5, I2C5_SCL,
SPI3_MISO(boot)/I2S3_SDI,
USART3_RX, UART4_RX,
OCTOSPIM_P1_NCS, SDMMC1_D3,
DCMI_D4/PSSI_D4, LCD_B4,
EVENTOUT
-
-
TRACED3, FMC_D6/FMC_AD6,
TIM15_CH1, I2C5_SMBA,
SPI6_SCK/I2S6_CK,
SPI3_MOSI(boot)/I2S3_SDO,
USART3_CK, UART5_TX,
SDMMC1_CK, DCMI_D9/PSSI_D9,
LCD_R6, EVENTOUT
-
-
-
A8
B9
B8
C8
77
78
79
80
110
111
112
113
A10
B11
B10
C10
PA15(JTDI)
PC10
PC11
PC12
I/O
I/O
I/O
I/O
FT
FT_fh
FT_fh
FT_h
D8
81
114
E10
PD0
I/O
FT_h
-
DFSDM1_CKIN6, UART4_RX,
FDCAN1_RX(boot), UART9_CTS,
FMC_D2/FMC_AD2, LCD_B1,
EVENTOUT
E8
82
115
D10
PD1
I/O
FT_h
-
DFSDM1_DATIN6, UART4_TX,
FDCAN1_TX(boot),
FMC_D3/FMC_AD3, EVENTOUT
DS13313 Rev 3
Additional
functions
67/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
83
E9
PD2
I/O
I/O structure
Pin type
UFBGA144
LQFP144
116
Pin name (function
after reset)
FT_h
Notes
B7
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
TRACED2, FMC_D7/FMC_AD7,
TIM3_ETR, TIM15_BKIN, UART5_RX,
LCD_B7, SDMMC1_CMD,
DCMI_D11/PSSI_D11, LCD_B2,
EVENTOUT
-
-
C7
84
117
D9
PD3
I/O
FT_h
-
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
FMC_CLK, DCMI_D5/PSSI_D5,
LCD_G7, EVENTOUT
D7
85
118
C9
PD4
I/O
FT_h
-
USART2_RTS/USART2_DE,
OCTOSPIM_P1_IO4, FMC_NOE,
EVENTOUT
-
B6
86
119
B9
PD5
I/O
FT_h
-
USART2_TX, OCTOSPIM_P1_IO5,
FMC_NWE, EVENTOUT
-
-
-
120
-
VSS
S
-
-
-
-
-
-
121
-
VDD
S
-
-
-
-
-
SAI4_D1, SAI1_D1, DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO, SAI1_SD_A,
USART2_RX, SAI4_SD_A,
OCTOSPIM_P1_IO6, SDMMC2_CK,
FMC_NWAIT, DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
-
-
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1, USART2_CK,
SPDIFRX1_IN1, OCTOSPIM_P1_IO7,
SDMMC2_CMD, FMC_NE1,
EVENTOUT
-
-
FDCAN3_TX, SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
OCTOSPIM_P1_IO6, SAI4_FS_B,
SDMMC2_D0, FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY, EVENTOUT
-
-
FDCAN3_RX, OCTOSPIM_P2_IO6,
SPI1_NSS/I2S1_WS, LCD_G3,
SAI4_SD_B, SDMMC2_D1, FMC_NE3,
DCMI_D2/PSSI_D2, LCD_B2,
EVENTOUT
-
C6
D6
-
-
68/234
87
88
-
-
122
123
124
125
A8
A9
E8
D8
PD6
PD7
PG9
PG10
I/O
I/O
I/O
I/O
FT_h
FT_h
FT_h
FT_h
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
-
-
-
-
-
127
128
C8
B8
D7
PG11
PG12
PG13
I/O
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
126
Pin name (function
after reset)
FT_h
FT_h
FT_h
Notes
-
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
LPTIM1_IN2, USART10_RX,
SPI1_SCK/I2S1_CK, SPDIFRX1_IN1,
OCTOSPIM_P2_IO7, SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_TX_EN,
DCMI_D3/PSSI_D3, LCD_B3,
EVENTOUT
-
-
LPTIM1_IN1, OCTOSPIM_P2_NCS,
USART10_TX, SPI6_MISO/I2S6_SDI,
USART6_RTS/USART6_DE,
SPDIFRX1_IN2, LCD_B4,
SDMMC2_D3,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_NE4, TIM23_CH1, LCD_B1,
EVENTOUT
-
-
TRACED0, LPTIM1_OUT,
USART10_CTS/USART10_NSS,
SPI6_SCK/I2S6_CK,
USART6_CTS/USART6_NSS,
SDMMC2_D6,
ETH_MII_TXD0/ETH_RMII_TXD0,
FMC_A24, TIM23_CH2, LCD_R0,
EVENTOUT
-
-
-
-
129
C7
PG14
I/O
FT_h
-
TRACED1, LPTIM1_ETR,
USART10_RTS/USART10_DE,
SPI6_MOSI/I2S6_SDO, USART6_TX,
OCTOSPIM_P1_IO7, SDMMC2_D7,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_A25, TIM23_CH3, LCD_B0,
EVENTOUT
-
-
130
-
VSS
S
-
-
-
-
-
-
131
-
VDD
S
-
-
-
-
-
-
132
B7
PG15
I/O
FT_h
-
USART6_CTS/USART6_NSS,
OCTOSPIM_P2_DQS, USART10_CK,
FMC_NCAS, DCMI_D13/PSSI_D13,
EVENTOUT
-
-
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK/I2S6_CK, SDMMC2_D2,
CRS_SYNC, UART7_RX, TIM24_ETR,
EVENTOUT
-
A7
89
133
A7
PB3
(JTDO/TRACESWO)
I/O
FT_h
DS13313 Rev 3
69/234
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
C5
B5
90
91
92
135
136
A6
B6
C6
PB4(NJTRST)
PB5
PB6
I/O
I/O
I/O
I/O structure
Pin type
UFBGA144
LQFP144
134
Pin name (function
after reset)
FT_h
FT_h
FT_fh
Notes
A6
LQFP100
TFBGA100
Pin number
Alternate functions
Additional
functions
-
NJTRST, TIM16_BKIN, TIM3_CH1,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO/I2S6_SDI, SDMMC2_D3,
UART7_TX, EVENTOUT
-
-
TIM17_BKIN, TIM3_CH2, LCD_B5,
I2C1_SMBA, SPI1_MOSI/I2S1_SDO,
I2C4_SMBA, SPI3_MOSI/I2S3_SDO,
SPI6_MOSI/I2S6_SDO, FDCAN2_RX,
OTG_HS_ULPI_D7, ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT
-
-
TIM16_CH1N, TIM4_CH1,
I2C1_SCL(boot), CEC, I2C4_SCL,
USART1_TX, LPUART1_TX,
FDCAN2_TX, OCTOSPIM_P1_NCS,
DFSDM1_DATIN5, FMC_SDNE1,
DCMI_D5/PSSI_D5, UART5_TX,
EVENTOUT
-
PVD_IN
A5
93
137
D6
PB7
I/O
FT_fa
-
TIM17_CH1N, TIM4_CH2, I2C1_SDA,
I2C4_SDA, USART1_RX,
LPUART1_RX, DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC/PSSI_RDY,
EVENTOUT
D5
94
138
D5
BOOT0
I
B
-
-
VPP
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4, ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6/PSSI_D6,
LCD_B6, EVENTOUT
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA(boot),
SPI2_NSS/I2S2_WS, I2C4_SDA,
SDMMC1_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5,
DCMI_D7/PSSI_D7, LCD_B7,
EVENTOUT
-
B4
A4
70/234
95
96
139
140
C5
B5
PB8
PB9
I/O
I/O
FT_fh
FT_fh
DS13313 Rev 3
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
141
A5
PE0
I/O
FT_h
-
C4
98
142
A4
PE1
I/O
FT_h
-
LPTIM1_IN2, UART8_TX, FMC_NBL1,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
-
-
99
-
-
VSS
S
-
-
-
-
F7
-
143
E5
PDR_ON
S
-
-
-
-
-
100
144
-
VDD
S
-
-
-
-
C2
-
-
D2
VSS
S
-
-
-
-
E6
-
-
E6
VSS
S
-
-
-
-
J1
-
-
E7
VSS
S
-
-
-
-
E4
-
-
G4
VSS
S
-
-
-
-
E5
-
-
G8
VSS
S
-
-
-
-
-
-
-
G10
VSS
S
-
-
-
-
-
-
-
H5
VSS
S
-
-
-
-
-
-
-
H6
VSS
S
-
-
-
-
D2
-
-
D3
VDD
S
-
-
-
-
F5
-
-
F4
VDD
S
-
-
-
-
K1
-
-
F5
VDD
S
-
-
-
-
F4
-
-
F6
VDD
S
-
-
-
-
-
-
-
F7
VDD
S
-
-
-
-
-
-
-
F8
VDD
S
-
-
-
-
-
-
-
F9
VDD
S
-
-
-
-
-
-
-
F10
VDD
S
-
-
-
-
-
-
-
G5
VDD
S
-
-
-
-
-
-
-
G6
VDD
S
-
-
-
-
-
-
-
G7
VDD
S
-
-
-
-
UFBGA144
97
LQFP144
D4
LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
SAI4_MCLK_A, FMC_NBL0,
DCMI_D2/PSSI_D2, LCD_R0,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin type
Pin number
Pin name (function
after reset)
Additional
functions
-
1. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available
on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the
product reference manual for a detailed description of the switch configuration bits
DS13313 Rev 3
71/234
85
AF0
Port
SYS
DS13313 Rev 3
Port A
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
TIM2_CH
1/TIM2_
ETR
TIM5_CH1
TIM8_
ETR
TIM15_
BKIN
SPI6_
NSS/I2S
6_WS
-
USART2
_CTS/
USART2
_NSS
UART4_
TX
SDMMC2_
CMD
SAI4_SD_
B
ETH_MII_
CRS
FMC_A19
-
-
EVENT
OUT
PA1
-
TIM2_CH
2
TIM5_CH2
LPTIM3_
OUT
TIM15_
CH1N
-
-
USART2
_RTS/
USART2
_DE
UART4_
RX
OCTOSPI
M_P1_IO3
SAI4_
MCLK_B
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
OCTOSPI
M_P1_
DQS
-
LCD_
R2
EVENT
OUT
PA2
-
TIM2_CH
3
TIM5_CH3
LPTIM4_
OUT
TIM15_
CH1
-
OCTOSPI
M_P1_IO0
USART2
_TX
SAI4_SCK
_B
-
-
ETH_MDIO
MDIOS_
MDIO
-
LCD_R
1
EVENT
OUT
PA3
-
TIM2_CH
4
TIM5_CH4
LPTIM5_
OUT
TIM15_
CH2
I2S6_
MCK
OCTOSPI
M_P1_IO2
USART2
_RX
-
LCD_B2
OTG_HS_
ULPI_D0
ETH_MII_
COL
OCTOSPI
M_P1_
CLK
-
LCD_B
5
EVENT
OUT
PA4
D1PWR
EN
-
TIM5_
ETR
-
-
SPI1_
SPI3_NSS
NSS/
/I2S3_WS
I2S1_WS
USART2
_CK
SPI6_NSS
/I2S6_WS
-
-
-
FMC_D8/
FMC_AD8
DCMI_
HSYNC/
PSSI_DE
LCD_
VSYNC
EVENT
OUT
PA5
D2PWR
EN
TIM2_CH
1/TIM2_
ETR
-
TIM8_CH
1N
-
SPI1_
SCK/
I2S1_CK
-
SPI6_SCK
/I2S6_CK
-
OTG_HS_
ULPI_CK
-
FMC_D9/
FMC_AD9
PSSI_D1
4
LCD_R
4
EVENT
OUT
PA6
-
TIM1_
BKIN
TIM3_CH1
TIM8_
BKIN
-
SPI1_
OCTOSPI
MISO/
M_P1_IO3
I2S1_SDI
-
SPI6_
TIM13_CH
MISO/I2S6
1
_SDI
TIM8_
BKIN_
COMP12
MDIOS_
MDC
TIM1_
BKIN_
COMP12
DCMI_
PIXCLK/
PSSI_
PDCK
LCD_G
2
EVENT
OUT
PA7
-
TIM1_CH
1N
TIM3_CH2
TIM8_CH
1N
-
SPI1_
MOSI/I2S
1_SDO
-
SPI6_
TIM14_CH
MOSI/I2S6
1
_SDO
OCTOSPI
M_P1_IO2
ETH_MII_
RX_DV/
ETH_RMII_
CRS_DV
FMC_SDN
WE
-
LCD_
VSYNC
EVENT
OUT
-
-
STM32H723xE/G
PA0
Pinouts, pin descriptions and alternate functions
72/234
Table 8. STM32H723 pin alternate functions
AF0
Port
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
TIM1_CH
1
-
TIM8_
BKIN2
I2C3_
SCL
-
I2C5_SCL
USART1
_CK
-
-
OTG_HS_
SOF
UART7_RX
TIM8_
BKIN2_
COMP12
LCD_B3
LCD_R
6
EVENT
OUT
PA9
-
TIM1_CH
2
-
LPUART
1_TX
I2C3_
SMBA
SPI2_
SCK/
I2S2_CK
I2C5_
SMBA
USART1
_TX
-
-
-
ETH_TX_
ER
-
DCMI_
D0/PSSI
_D0
LCD_R
5
EVENT
OUT
PA10
-
TIM1_CH
3
-
LPUART
1_RX
-
-
-
USART1
_RX
-
-
OTG_HS_
ID
MDIOS_
MDIO
LCD_B4
DCMI_
D1/PSSI
_D1
LCD_B
1
EVENT
OUT
PA11
-
TIM1_CH
4
-
LPUART
1_CTS
-
SPI2_
NSS/
I2S2_WS
UART4_
RX
USART1
_CTS/
USART1
_NSS
-
FDCAN1_
RX
-
-
-
-
LCD_R
4
EVENT
OUT
PA12
-
TIM1_
ETR
-
LPUART
1_RTS/
LPUART
1_DE
-
SPI2_
SCK/
I2S2_CK
UART4_
TX
USART1
_RTS/
USART1
_DE
SAI4_FS_
B
FDCAN1_
TX
-
-
TIM1_
BKIN2
-
LCD_R
5
EVENT
OUT
PA13
JTMS/
SWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCK/
SWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_
CH1/TIM2
_ETR
-
-
CEC
UART4_
RTS/
UART4_
DE
LCD_R3
-
UART7_TX
-
-
LCD_B
6
EVENT
OUT
Port A
MCO1
SPI1_
SPI6_
SPI3_NSS
NSS/
NSS/
/I2S3_WS
I2S1_WS
I2S6_WS
73/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
PA8
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port B
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
TIM1_CH
2N
TIM3_CH3
OCTO
TIM8_CH
SPIM_P1
2N
_IO1
-
DFSDM1_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
-
-
LCD_G
1
EVENT
OUT
PB1
-
TIM1_CH
3N
TIM3_CH4
OCTO
TIM8_CH
SPIM_P1
3N
_IO0
-
DFSDM1_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
-
-
LCD_G
0
EVENT
OUT
PB2
RTC_
OUT
SAI4_D1
SAI1_D1
-
DFSDM1
_CKIN1
-
SPI3_
SAI1_SD_
SAI4_SD_
MOSI/I2S
A
A
3_SDO
OCTO
SPIM_P1_
CLK
OCTO
SPIM_P1_
DQS
ETH_TX_
ER
-
TIM23_
ETR
-
EVENT
OUT
PB3
JTDO/
TRACE
SWO
TIM2_CH
2
-
-
-
SPI1_
SCK/
I2S1_CK
SPI3_SCK
/I2S3_CK
-
CRS_
SYNC
UART7_RX
-
-
TIM24_
ETR
EVENT
OUT
PB4
NJT
RST
TIM16_
BKIN
TIM3_CH1
-
-
SPI1_
MISO/
I2S1_SDI
SPI3_
MISO/
I2S3_SDI
SPI2_
NSS/
I2S2_WS
SDMMC2_
D3
-
UART7_TX
-
-
-
EVENT
OUT
PB5
-
TIM17_
BKIN
TIM3_CH2
LCD_B5
I2C1_
SMBA
SPI1_
MOSI/I2S
1_SDO
I2C4_
SMBA
SPI3_
SPI6_
MOSI/I2S MOSI/I2S6
3_SDO
_SDO
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_SDC
KE1
DCMI_
D10/PSS
I_D10
UART5
_RX
EVENT
OUT
PB6
-
TIM16_
CH1N
TIM4_CH1
-
I2C1_
SCL
CEC
I2C4_SCL
USART1
_TX
LPUART1
_TX
FDCAN2_
TX
OCTO
SPIM_P1_
NCS
DFSDM1_
DATIN5
FMC_SDN
E1
DCMI_
D5/PSSI
_D5
UART5
_TX
EVENT
OUT
PB7
-
TIM17_
CH1N
TIM4_CH2
-
I2C1_
SDA
-
I2C4_SDA
USART1
_RX
LPUART1
_RX
-
-
DFSDM1_
CKIN5
FMC_NL
DCMI_
VSYNC/
PSSI_
RDY
-
EVENT
OUT
PB8
-
TIM16_C
H1
TIM4_CH3
DFSDM1
_CKIN7
I2C1_
SCL
-
I2C4_SCL
SDMMC1
_CKIN
UART4_
RX
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4
DCMI_
D6/PSSI
_D6
LCD_B
6
EVENT
OUT
PB9
-
TIM17_
CH1
TIM4_CH4
DFSDM1
_DATIN7
I2C1_
SDA
SPI2_
NSS/I2S
2_WS
I2C4_SDA
SDMMC1
_CDIR
UART4_
TX
FDCAN1_
TX
SDMMC2_
D5
I2C4_
SMBA
SDMMC1_
D5
DCMI_
D7/PSSI
_D7
LCD_B
7
EVENT
OUT
SPI6_SCK SDMMC2_
/I2S6_CK
D2
SPI6_
MISO/
I2S6_SDI
STM32H723xE/G
PB0
Pinouts, pin descriptions and alternate functions
74/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
TIM2_CH
3
-
LPTIM2_
IN1
I2C2_
SCL
SPI2_
SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3
_TX
-
OCTO
SPIM_P1_
NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
-
-
LCD_G
4
EVENT
OUT
PB11
-
TIM2_CH
4
-
LPTIM2_
ETR
I2C2_
SDA
-
DFSDM1_
CKIN7
USART3
_RX
-
-
OTG_HS_
ULPI_D4
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
-
LCD_G
5
EVENT
OUT
PB12
-
TIM1_BKI
N
-
OCTO
SPIM_P1
_NCLK
I2C2_SM
BA
SPI2_
NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3
_CK
-
FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_
TXD0/
ETH_RMII_
TXD0
OCTOSPI
M_P1_IO0
TIM1_
BKIN_
COMP12
UART5
_RX
EVENT
OUT
PB13
-
TIM1_CH
1N
-
LPTIM2_
OUT
OCTO
SPIM_P1
_IO2
SPI2_
SCK/
I2S2_CK
DFSDM1_
CKIN1
USART3
_CTS/
USART3
_NSS
-
FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/
ETH_RMII_
TXD1
SDMMC1_
D0
DCMI_
D2/PSSI
_D2
UART5
_TX
EVENT
OUT
PB14
-
TIM1_CH
2N
TIM12_CH TIM8_CH
1
2N
USART1
_TX
SPI2_
DFSDM1_
MISO/
DATIN2
I2S2_SDI
USART3
_RTS/
USART3
_DE
UART4_
RTS/UAR
T4_DE
SDMMC2_
D0
-
-
FMC_D10/
FMC_
AD10
-
LCD_C
LK
EVENT
OUT
PB15
RTC_
REFIN
TIM1_CH
3N
TIM12_CH TIM8_CH
2
3N
USART1
_RX
SPI2_
DFSDM1_
MOSI/I2S
CKIN2
2_SDO
-
UART4_
CTS
SDMMC2_
D1
-
-
FMC_D11/
FMC_AD1
1
-
LCD_G
7
EVENT
OUT
Port B
-
75/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
PB10
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port C
AF1
AF2
AF3
AF4
AF12
AF13
AF14
AF15
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
PC0
-
FMC_D12
/FMC_AD
12
-
DFSDM1
_CKIN0
-
PC1
TRACE
D0
SAI4_D1
SAI1_D1
DFSDM1
_DATIN0
DFSDM1
_CKIN4
PC2
PWR_
DEEP
SLEEP
-
-
PC3
PWR_
SLEEP
-
PC4
PWR_
DEEP
SLEEP
PC5
AF5
AF6
AF7
AF8
AF9
AF10
AF11
-
SAI4_FS_
B
FMC_A25
OTG_HS_
ULPI_STP
LCD_G2
FMC_SDN
WE
-
LCD_R
5
EVENT
OUT
SPI2_
SAI1_SD_
MOSI/I2S
A
2_SDO
-
SAI4_SD_ SDMMC2_
A
CK
OCTO
SPIM_P1_
IO4
ETH_MDC
MDIOS_
MDC
-
LCD_G
5
EVENT
OUT
DFSDM1
_CKIN1
OCTO
SPI2_
DFSDM1_
SPIM_P1 MISO/I2S
CKOUT
_IO5
2_SDI
-
-
OCTOSPI
M_P1_IO2
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDN
E0
-
-
EVENT
OUT
-
DFSDM1
_DATIN1
OCTO
SPI2_
SPIM_P1 MOSI/I2S
_IO6
2_SDO
-
-
-
OCTOSPI
M_P1_IO0
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SDC
KE0
-
-
EVENT
OUT
FMC_A22
-
DFSDM1
_CKIN2
-
I2S1_
MCK
-
-
-
ETH_MII_
SPDIFRX1 SDMMC2_ RXD0/ETH
_IN3
CKIN
_RMII_RXD
0
FMC_SDN
E0
-
LCD_R
7
EVENT
OUT
PWR_
SLEEP
SAI4_D3
SAI1_D3
DFSDM1
_DATIN2
PSSI_D1
5
-
-
-
-
SPDIFRX1
_IN4
OCTOSPI
M_P1_DQ
S
ETH_MII_R
XD1/ETH_
RMII_RXD1
FMC_SDC
KE0
COMP1_
OUT
LCD_D
E
EVENT
OUT
PC6
-
-
TIM3_CH1
TIM8_CH
1
DFSDM1
_CKIN3
I2S2_
MCK
-
USART6
_TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1_
D6
DCMI_
D0/PSSI
_D0
LCD_H
SYNC
EVENT
OUT
PC7
DB
TRGIO
-
TIM3_CH2
TIM8_CH
2
DFSDM1
_DATIN3
-
I2S3_
MCK
USART6
_RX
SDMMC1_
FMC_NE1
D123DIR
SDMMC2_
D7
SWPMI_TX
SDMMC1_
D7
DCMI_
D1/PSSI
_D1
LCD_G
6
EVENT
OUT
PC8
TRACE
D1
-
TIM3_CH3
TIM8_CH
3
-
-
-
USART6
_CK
FMC_INT
SWPMI_RX
SDMMC1_
D0
DCMI_
D2/PSSI
_D2
-
EVENT
OUT
UART5_
RTS/
UART5_
DE
FMC_NE2
/FMC_
NCE
STM32H723xE/G
DFSDM1_
DATIN4
-
Pinouts, pin descriptions and alternate functions
76/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
PC9
MCO2
-
TIM3_CH4
TIM8_CH
4
I2C3_
SDA
I2S_
CKIN
I2C5_SDA
-
UART5_C
TS
OCTO
SPIM_P1_
IO0
LCD_G3
SWPMI_
SUSPEND
SDMMC1_
D1
DCMI_D
3/PSSI_
D3
LCD_B
2
EVENT
OUT
PC10
-
-
-
DFSDM1
_CKIN5
I2C5_
SDA
-
SPI3_SCK
/I2S3_CK
USART3
_TX
UART4_
TX
OCTO
SPIM_P1_
IO1
LCD_B1
SWPMI_RX
SDMMC1_
D2
DCMI_D
8/PSSI_
D8
LCD_R
2
EVENT
OUT
PC11
-
-
-
DFSDM1
_DATIN5
I2C5_
SCL
-
SPI3_
MISO/
I2S3_SDI
USART3
_RX
UART4_
RX
OCTO
SPIM_P1_
NCS
-
-
SDMMC1_
D3
DCMI_
D4/PSSI
_D4
LCD_B
4
EVENT
OUT
PC12
TRACE
D3
-
I2C5_
SMBA
SPI6_
SCK/
I2S6_CK
SPI3_
MOSI/
I2S3_SDO
USART3
_CK
UART5_
TX
-
-
-
SDMMC1_
CK
DCMI_
D9/PSSI
_D9
LCD_R
6
EVENT
OUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
FMC_D6/ TIM15_CH
FMC_AD6
1
77/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
Port C
SYS
AF1
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port D
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
-
-
DFSDM1
_CKIN6
-
-
-
-
UART4_
RX
FDCAN1_
RX
-
UART9_
CTS
FMC_D2/
FMC_AD2
-
LCD_B
1
EVENT
OUT
PD1
-
-
-
DFSDM1
_DATIN6
-
-
-
-
UART4_
TX
FDCAN1_
TX
-
-
FMC_D3/
FMC_AD3
-
-
EVENT
OUT
PD2
TRACE
D2
FMC_D7/
FMC_AD7
TIM3_
ETR
-
TIM15_
BKIN
-
-
-
UART5_
RX
LCD_B7
-
-
SDMMC1_
CMD
DCMI_
D11/PSSI
_D11
LCD_B
2
EVENT
OUT
PD3
-
-
-
DFSDM1
_CKOUT
-
SPI2_
SCK/
I2S2_CK
-
USART2
_CTS/
USART2
_NSS
-
-
-
-
FMC_CLK
DCMI_
D5/PSSI
_D5
LCD_G
7
EVENT
OUT
PD4
-
-
-
-
-
-
-
USART2
_RTS/
USART2
_DE
-
-
OCTOSPI
M_P1_IO4
-
FMC_NOE
-
-
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2
_TX
-
-
OCTOSPI
M_P1_IO5
-
FMC_NWE
-
-
EVENT
OUT
PD6
-
SAI4_D1
SAI1_D1
DFSDM1
_CKIN4
DFSDM1
_DATIN1
SPI3_
SAI1_SD_
MOSI/I2S
A
3_SDO
USART2
_RX
SAI4_SD_
A
-
OCTO
SPIM_P1_
IO6
SDMMC2_
CK
FMC_
NWAIT
DCMI_D
10/PSSI_
D10
LCD_B
2
EVENT
OUT
PD7
-
-
-
DFSDM1
_DATIN4
-
SPI1_
DFSDM1_
MOSI/I2S
CKIN1
1_SDO
USART2
_CK
-
SPDIFRX1
_IN1
OCTO
SPIM_P1_
IO7
SDMMC2_
CMD
FMC_NE1
-
-
EVENT
OUT
PD8
-
-
-
DFSDM1
_CKIN3
-
USART3
_TX
-
SPDIFRX1
_IN2
-
-
FMC_D13/
FMC_
AD13
-
-
EVENT
OUT
-
-
STM32H723xE/G
PD0
Pinouts, pin descriptions and alternate functions
78/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
PD9
-
-
-
DFSDM1
_DATIN3
-
-
-
USART3
_RX
-
-
-
-
FMC_D14/
FMC_AD1
4
-
-
EVENT
OUT
PD10
-
-
-
DFSDM1
_CKOUT
-
-
-
USART3
_CK
-
-
-
-
FMC_D15/
FMC_AD1
5
-
LCD_B
3
EVENT
OUT
PD11
-
-
-
LPTIM2_I I2C4_SM
N2
BA
-
-
USART3
_CTS/
USART3
_NSS
-
OCTOSPI
M_P1_IO0
SAI4_SD_
A
-
FMC_A16/
FMC_CLE
-
-
EVENT
OUT
PD12
-
LPTIM1_
IN1
TIM4_CH1
LPTIM2_
IN1
I2C4_
SCL
FDCAN3
_RX
-
USART3
_RTS/
USART3
_DE
-
OCTO
SPIM_P1_
IO1
SAI4_FS_
A
-
FMC_A17/
FMC_ALE
DCMI_
D12/PSS
I_D12
-
EVENT
OUT
PD13
-
LPTIM1_
OUT
TIM4_CH2
-
I2C4_
SDA
FDCAN3
_TX
-
-
-
OCTO
SPIM_P1_
IO3
SAI4_
SCK_A
UART9_
RTS/
UART9_DE
FMC_A18
DCMI_
D13/
PSSI_
D13
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
UART8_
CTS
-
-
UART9_RX
FMC_D0/
FMC_AD0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
-
-
UART8_
RTS/
UART8_
DE
-
-
UART9_TX
FMC_D1/
FMC_AD1
-
-
EVENT
OUT
79/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
Port D
SYS
AF1
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port E
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
LPTIM1_
ETR
TIM4_
ETR
-
LPTIM2_
ETR
-
-
-
UART8_
RX
-
SAI4_
MCLK_A
-
FMC_NBL
0
DCMI_
D2/PSSI
_D2
LCD_R
0
EVENT
OUT
PE1
-
LPTIM1_
IN2
-
-
-
-
-
-
UART8_
TX
-
-
-
FMC_NBL
1
DCMI_
D3/
PSSI_D3
LCD_R
6
EVENT
OUT
PE2
TRACE
CLK
-
SAI1_
CK1
-
USART1
0_RX
SPI4_
SCK
SAI1_
MCLK_A
-
SAI4_
MCLK_A
OCTOSPI
M_P1_IO2
SAI4_CK1
ETH_MII_
TXD3
FMC_A23
-
-
EVENT
OUT
PE3
TRACE
D0
-
-
-
TIM15_
BKIN
-
SAI1_SD_
B
-
SAI4_SD_
B
-
-
USART10_
TX
FMC_A19
-
-
EVENT
OUT
PE4
TRACE
D1
-
SAI1_D2
DFSDM1
_DATIN3
TIM15_
CH1N
SPI4_NS
S
SAI1_FS_
A
-
SAI4_FS_
A
-
SAI4_D2
-
FMC_A20
DCMI_
D4/PSSI
_D4
LCD_B
0
EVENT
OUT
PE5
TRACE
D2
-
SAI1_CK2
DFSDM1
_CKIN3
TIM15_
CH1
SPI4_
MISO
SAI1_SCK
_A
-
SAI4_SCK
_A
-
SAI4_CK2
-
FMC_A21
DCMI_
D6/PSSI
_D6
LCD_G
0
EVENT
OUT
PE6
TRACE
D3
TIM1_
BKIN2
SAI1_D1
-
TIM15_
CH2
SPI4_
MOSI
SAI1_SD_
A
-
SAI4_SD_
A
SAI4_D1
SAI4_
MCLK_B
TIM1_BKIN
2_COMP12
FMC_A22
DCMI_
D7/PSSI
_D7
LCD_G
1
EVENT
OUT
PE7
-
TIM1_ET
R
-
DFSDM1
_DATIN2
-
-
-
UART7_
RX
-
-
OCTO
SPIM_P1_
IO4
-
FMC_D4/
FMC_AD4
-
-
EVENT
OUT
PE8
-
TIM1_CH
1N
-
DFSDM1
_CKIN2
-
-
-
UART7_
TX
-
-
OCTO
SPIM_P1_
IO5
-
FMC_D5/
FMC_AD5
COMP2_
OUT
-
EVENT
OUT
PE9
-
TIM1_CH
1
-
DFSDM1
_CKOUT
-
-
-
UART7_
RTS/
UART7_
DE
-
-
OCTO
SPIM_P1_
IO6
-
FMC_D6/
FMC_AD6
-
-
EVENT
OUT
STM32H723xE/G
PE0
Pinouts, pin descriptions and alternate functions
80/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
PE10
-
TIM1_CH
2N
-
DFSDM1
_DATIN4
-
-
-
UART7_
CTS
-
-
OCTO
SPIM_P1_
IO7
-
FMC_D7/
FMC_AD7
-
-
EVENT
OUT
PE11
-
TIM1_CH
2
-
DFSDM1
_CKIN4
-
SPI4_
NSS
-
-
-
-
SAI4_SD_
B
OCTO
SPIM_P1_
NCS
FMC_D8/
FMC_AD8
-
LCD_G
3
EVENT
OUT
PE12
-
TIM1_CH
3N
-
DFSDM1
_DATIN5
-
SPI4_
SCK
-
-
-
-
SAI4_SCK
_B
-
FMC_D9/
FMC_AD9
COMP1_
OUT
LCD_B
4
EVENT
OUT
PE13
-
TIM1_CH
3
-
DFSDM1
_CKIN5
-
SPI4_
MISO
-
-
-
-
SAI4_FS_
B
-
FMC_D10/
FMC_
AD10
COMP2_
OUT
LCD_
DE
EVENT
OUT
PE14
-
TIM1_CH
4
-
-
-
SPI4_
MOSI
-
-
-
-
SAI4_
MCLK_B
-
FMC_D11/
FMC_
AD11
-
LCD_
CLK
EVENT
OUT
PE15
-
TIM1_
BKIN
-
-
-
-
-
-
-
-
-
USART10_
CK
FMC_D12/
FMC_
AD12
TIM1_
BKIN_
COMP12
LCD_
R7
EVENT
OUT
81/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
Port E
SYS
AF1
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port F
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
-
-
-
I2C2_
SDA
-
I2C5_SDA
-
-
OCTO
SPIM_P2_
IO0
-
-
FMC_A0
TIM23_
CH1
-
EVENT
OUT
PF1
-
-
-
-
I2C2_
SCL
-
I2C5_SCL
-
-
OCTO
SPIM_P2_
IO1
-
-
FMC_A1
TIM23_
CH2
-
EVENT
OUT
PF2
-
-
-
-
I2C2_
SMBA
-
I2C5_
SMBA
-
-
OCTO
SPIM_P2_
IO2
-
-
FMC_A2
TIM23_
CH3
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
IO3
-
-
FMC_A3
TIM23_
CH4
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
CLK
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
NCLK
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
TIM16_
CH1
FDCAN3_
RX
-
-
SPI5_
NSS
SAI1_SD_
B
UART7_
RX
SAI4_SD_
B
-
OCTO
SPIM_P1_
IO3
-
-
TIM23_
CH1
-
EVENT
OUT
PF7
-
TIM17_
CH1
FDCAN3_
TX
-
-
SPI5_
SCK
SAI1_
MCLK_B
UART7_
TX
SAI4_
MCLK_B
-
OCTO
SPIM_P1_
IO2
-
-
TIM23_
CH2
-
EVENT
OUT
PF8
-
TIM16_
CH1N
-
-
-
SPI5_
MISO
SAI1_SCK
_B
UART7_
RTS/
UART7_
DE
SAI4_SCK TIM13_CH
_B
1
OCTO
SPIM_P1_
IO0
-
-
TIM23_
CH3
-
EVENT
OUT
PF9
-
TIM17_
CH1N
-
-
-
SPI5_
MOSI
SAI1_FS_
B
UART7_
CTS
SAI4_FS_
B
OCTO
SPIM_P1_
IO1
-
-
TIM23_
CH4
-
EVENT
OUT
TIM14_CH
1
STM32H723xE/G
PF0
Pinouts, pin descriptions and alternate functions
82/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
PF10
-
TIM16_BK
IN
SAI1_D3
-
PSSI_
D15
-
-
-
-
OCTO
SPIM_P1_
CLK
SAI4_D3
-
-
DCMI_
D11/PSSI
_D11
LCD_D
E
EVENT
OUT
PF11
-
-
-
-
-
SPI5_
MOSI
-
-
-
OCTO
SPIM_P1_
NCLK
SAI4_SD_
B
-
FMC_
NRAS
DCMI_
D12/PSS
I_D12
TIM24_
CH1
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
DQS
-
-
FMC_A6
-
TIM24_
CH2
EVENT
OUT
PF13
-
-
-
DFSDM1
_DATIN6
I2C4_
SMBA
-
-
-
-
-
-
-
FMC_A7
-
TIM24_
CH3
EVENT
OUT
PF14
-
-
-
DFSDM1
_CKIN6
I2C4_
SCL
-
-
-
-
-
-
-
FMC_A8
-
TIM24_
CH4
EVENT
OUT
PF15
-
-
-
-
I2C4_
SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
83/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
Port F
SYS
AF1
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
DS13313 Rev 3
Port G
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
IO4
-
UART9_RX
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
IO5
-
UART9_TX
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
TIM8_
BKIN
-
-
-
-
-
-
-
TIM8_BKIN
_COMP12
FMC_A12
-
TIM24_
ETR
EVENT
OUT
PG3
-
-
-
TIM8_
BKIN2
-
-
-
-
-
-
-
TIM8_
BKIN2_
COMP12
FMC_A13
TIM23_
ETR
-
EVENT
OUT
PG4
-
TIM1_BKI
N2
-
-
-
-
-
-
-
-
-
TIM1_
BKIN2_
COMP12
FMC_A14/
FMC_BA0
-
-
EVENT
OUT
PG5
-
TIM1_
ETR
-
-
-
-
-
-
-
-
-
-
FMC_A15/
FMC_BA1
-
-
EVENT
OUT
PG6
-
TIM17_
BKIN
-
-
-
-
-
-
-
-
OCTO
SPIM_P1_
NCS
-
FMC_NE3
DCMI_D
12/PSSI_
D12
LCD_R
7
EVENT
OUT
PG7
-
-
-
-
-
-
SAI1_
MCLK_A
USART6
_CK
-
OCTO
SPIM_P2_
DQS
-
-
FMC_INT
DCMI_D
13/PSSI_
D13
LCD_
CLK
EVENT
OUT
PG8
-
-
-
TIM8_
ETR
-
SPI6_
NSS/I2S
6_WS
-
USART6
_RTS/
USART6
_DE
SPDIFRX1
_IN3
-
-
ETH_PPS_
OUT
FMC_
SDCLK
-
LCD_G
7
EVENT
OUT
PG9
-
-
FDCAN3_
TX
-
-
SPI1_
MISO/I2S
1_SDI
-
USART6
_RX
OCTO
SPDIFRX1
SPIM_P1_
_IN4
IO6
SAI4_FS_
B
SDMMC2_
D0
FMC_NE2/
FMC_NCE
DCMI_
VSYNC/
PSSI_
RDY
-
EVENT
OUT
STM32H723xE/G
PG0
Pinouts, pin descriptions and alternate functions
84/234
Table 8. STM32H723 pin alternate functions (continued)
AF0
Port
SYS
AF2
AF3
AF4
AF5
AF6
AF7
AF9
AF10
AF11
CEC/
DCMI/
CRS/
DFSDM1/
FDCAN1/2
DFSDM1
PSSI/
DFSDM1/I SDMMC1
FMC/
ETH/I2C4/
CEC/
LPUART1/
/FMC/
/LCD/
DFSDM1
2C4/5/
/SPI2/I2S
LCD/
LCD/MDIO
FMC/
FDCAN3/
FDCAN3/
SAI4/
LCD/
LPTIM2/ /I2C1/2/3/
OCTO
2/SPI3/
OCTO
S/OCTOSP
LPTIM1/
PDM_
SPI1/I2S
SDMMC1/
OCTO
3/4/5/
4/5/
SPIM_P1/
I2S3/
SPIM_P1/
IM_P1/
SAI4/TIM1
SAI1/
1/SPI2/
SPDIFRX1 SPIM_P1/
LPUART LPTIM2/
SAI1/
SPI6/
OTG1_FS/ SDMMC2/
6/17/TIM1 TIM3/4/5/1
I2S2/SPI
/SPI6/
2/SAI4/
1/OCTO
OCTO
SPI3/
UART7/
OTG1_HS/ SWPMI1/
x/TIM2x
2/15
3/I2S3/
UART4/5/ SDMMC2/
SPIM_P1 SPIM_P1
I2S3/
USART1/
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/2/TIM8
/TIM15/
UART4
2/3/6
SDMMC2/ 8/UART7/9/
/TIM13/14
USART1/
TIM8
USART10
10
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
TIM8
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
SAI4_SD_
B
SDMMC2_
D1
FMC_NE3
DCMI_
D2/PSSI
_D2
LCD_B
2
EVENT
OUT
OCTO
SPDIFRX1
SPIM_P2_
_IN1
IO7
SDMMC2_
D2
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
DCMI_
D3/PSSI
_D3
LCD_B
3
EVENT
OUT
USART6
_RTS/
USART6
_DE
SPDIFRX1
_IN2
LCD_B4
SDMMC2_
D3
ETH_MII_
TXD1/ETH
_RMII_TXD
1
FMC_NE4
TIM23_
CH1
LCD_B
1
EVENT
OUT
-
USART6
_CTS/
USART6
_NSS
-
-
SDMMC2_
D6
ETH_MII_
TXD0/ETH
_RMII_TXD
0
FMC_A24
TIM23_
CH2
LCD_R
0
EVENT
OUT
SPI6_
MOSI/I2S
6_SDO
-
USART6
_TX
-
OCTO
SPIM_P1_
IO7
SDMMC2_
D7
ETH_MII_
TXD1/ETH
_RMII_TXD
1
FMC_A25
TIM23_
CH3
LCD_B
0
EVENT
OUT
-
-
-
USART6
_CTS/
USART6
_NSS
-
OCTO
SPIM_P2_
DQS
-
USART10_
CK
FMC_NCA
S
DCMI_D
13/PSSI_
D13
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG10
-
-
FDCAN3_
RX
OCTO
SPIM_P2
_IO6
-
SPI1_
NSS/I2S
1_WS
-
-
PG11
-
LPTIM1_
IN2
-
-
USART1
0_RX
SPI1_
SCK/I2S
1_CK
-
-
PG12
-
LPTIM1_
IN1
-
OCTO
SPIM_P2
_NCS
USART1
0_TX
SPI6_
MISO/I2S
6_SDI
-
PG13
TRACE
D0
LPTIM1_
OUT
-
-
USART1
0_CTS/
USART1
0_NSS
SPI6_
SCK/I2S
6_CK
PG14
TRACE
D1
LPTIM1_
ETR
-
-
USART1
0_RTS/
USART1
0_DE
PG15
-
-
-
-
PH0
-
-
-
PH1
-
-
-
Port G
AF8
-
LCD_G3
85/234
Pinouts, pin descriptions and alternate functions
DS13313 Rev 3
Port H
AF1
STM32H723xE/G
Table 8. STM32H723 pin alternate functions (continued)
Electrical characteristics
6
6.1
STM32H723xE/G
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
86/234
DS13313 Rev 3
MS19010V2
STM32H723xE/G
Power supply scheme
Figure 10. Power supply scheme
VCAP
IOs
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
Power
switch
VSS
Power
switch
Core domain (VCORE)
LDO
voltage
regulator
VDDLDO
Level shifter
6.1.6
Electrical characteristics
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
Flash
VSS
VDD domain
VDD
VBAT
charging
LSI, HSI,
CSI, HSI48,
HSE, PLLs
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power
switch
Power switch
LSE, RTC,
Wakeup logic,
backup
IO
logic registers, Reset
BKUP
IOs
VSS
Backup
RAM
VSS
VDD33USB
USB
FS IOs
VDDA
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
OPAMP,
Comparator
VSSA
MSv65399V2
1. Refer to application note AN5419 “Getting started with STM32H723/733, STM32H725/735 and
STM32H730 Value Line hardware development“ for the possible power scheme and connected capacitors.
DS13313 Rev 3
87/234
214
Electrical characteristics
6.1.7
STM32H723xE/G
Current consumption measurement
Figure 11. Current consumption measurement scheme
LDO ON
IDD_VBAT
VBAT
IDD
VDD
VDDLDO
VDDA
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics,
Table 10: Current characteristics, and Table 11: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 9. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
VDDX - VSS(1)
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS−0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
Variations between different VDDX power
pins of the same domain
-
50
mV
Variations between all the different ground
pins
-
50
mV
VIN(2)
Input voltage on any other pins
|∆VDDX|
|VSSx-VSS|
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
88/234
DS13313 Rev 3
STM32H723xE/G
Electrical characteristics
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 10. Current characteristics
Symbols
Ratings
Max
ΣIVDD
(1)
Total current into sum of all VDD power lines (source)
620
ΣIVSS
Total current out of sum of all VSS ground lines (sink)(1)
620
IVDD
IVSS
IIO
ΣI(PIN)
IINJ(PIN)
(3)(4)
ΣIINJ(PIN)
Maximum current into each VDD power pin
(source)(1)
100
(1)
100
Maximum current out of each VSS ground pin (sink)
Output current sunk by any I/O and control pin, except Px_C
20
Output current sunk by Px_C pins
1
Total output current sunk by sum of all I/Os and control
pins(2)
Unit
mA
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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