STM32H730AB STM32H730IB
STM32H730VB STM32H730ZB
32-bit Arm® Cortex®-M7 550 MHz MCU, 128 KB Flash, 564 KB
RAM, 35 comms peripherals and analog interfaces, HW crypto/hash
Datasheet - production data
Features
FBGA
Core
• 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1
cache: 32-Kbyte data cache and 32-Kbyte
instruction cache allowing 0-wait state
execution from embedded Flash memory and
external memories, frequency up to 550 MHz,
MPU, 1177 DMIPS/2.14 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
LQFP100 (14 x 14 mm)
LQFP144 (20 x 20 mm)
LQFP176 (24 x 24 mm)
FBGA
UFBGA144 (7 x 7 mm)
UFBGA 169 (7 x 7 mm)
UFBGA 176+25 (10 x 10 mm)
Memories
• 128 Kbytes of embedded Flash memory with
ECC
• SRAM: total 564 Kbytes all with ECC, including
128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to
256 Kbytes can remap on instruction TCM
RAM for critical real time instructions) +
4 Kbytes of backup SRAM (available in the
lowest-power modes)
• Flexible external memory controller with up to
24-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• 2 x Octo-SPI interface with XiP and on-the-fly
decryption support
• 2 x SD/SDIO/MMC interface
• Bootloader with security services support (SFI
and SB-SFU)
Graphics
• Chrom-ART Accelerator graphical hardware
accelerator enabling enhanced graphical user
interface to reduce CPU load
• LCD-TFT controller supporting up to XGA
resolution
TFBGA100 (8 x 8 mm)
Clock, reset and supply management
• 1.62 V to 3.6 V application supply and I/O
• POR, PDR, PVD and BOR
• Dedicated USB power
• Embedded DCDC and LDO regulator
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-50 MHz HSE,
32.768 kHz LSE
Low power
• Sleep, Stop and Standby modes
• VBAT supply for RTC, 32×32-bit backup
registers
Analog
• 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to
22 channels and 7.2 MSPS in doubleinterleaved mode
• 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12
channels
• 2 x comparators
• 2 x operational amplifier GBW = 8 MHz
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STM32H730xB
• 2× 12-bit D/A converters
Digital filters for sigma delta modulator
(DFSDM)
• 8 channels/4 filters
DMA, on-chip FS PHY and ULPI for external
HS PHY
• SWPMI single-wire protocol master I/F
• MDIO slave interface
Mathematical acceleration
4 DMA controllers to offload the CPU
• 1 × MDMA with linked list support
• CORDIC for trigonometric functions
acceleration
• 2 × dual-port DMAs with FIFO
• FMAC: Filter mathematical accelerator
• 1 × basic DMA with request router capabilities
24 timers
• Seventeen 16-bit (including 5 x low power
16-bit timer available in stop mode) and four
32-bit timers, each with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
• 2x watchdogs, 1x SysTick timer
Digital temperature sensor
Cryptographic/HASH acceleration
• AES 128, 192, 256, TDES, HASH (MD5, SHA1, SHA-2), HMAC
• 2x OTFDEC AES-128 in CTR mode for OctoSPI memory encryption/decryption
True random number generator
Debug mode
CRC calculation unit
• SWD and JTAG interfaces
• 2-Kbyte embedded trace buffer
RTC with sub-second accuracy and
hardware calendar
Up to 128 I/O ports with interrupt
capability
ROP, PC-ROP, tamper detection, secure
firmware upgrade support
Up to 35 communication interfaces
96-bit unique ID
• Up to 5 × I2C FM+ interfaces
(SMBus/PMBus™)
• Up to 5 USARTs/5 UARTs (ISO7816 interface,
LIN, IrDA, modem control) and 1 x LPUART
All packages are ECOPACK2 compliant
• Up to 6 SPIs with 4 with muxed duplex I2S for
audio class accuracy via internal audio PLL or
external clock and up to 5 x SPI (from 5 x
USART when configured in synchronous
mode)
• 2x SAI (serial audio interface)
• 1× FD/TT-CAN and 2xFD-CAN
• 8- to 14-bit camera interface
• 16-bit parallel slave synchronous interface
• SPDIF-IN interface
• HDMI-CEC
• Ethernet MAC interface with DMA controller
• USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
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Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4
Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6
CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.7
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.8
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.13
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.14
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34
3.16
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34
3.17
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34
3.18
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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3.19
Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.20
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22
Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.28
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29
PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.30
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.31
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.32
Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 42
3.33
On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.34
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.34.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 47
3.34.5
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.6
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.35
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 48
3.36
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37
Universal synchronous/asynchronous receiver transmitter (USART) . . . 49
3.38
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 50
3.39
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 51
3.40
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.41
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.42
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 52
3.43
Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 53
3.44
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 53
3.45
Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 53
DS13315 Rev 2
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Contents
3.46
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 54
3.47
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 54
3.48
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.49
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5
Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 57
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.3
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.4
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
6.3.5
Embedded reset and power control block characteristics . . . . . . . . . . 115
6.3.6
Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . 116
6.3.7
Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . 117
6.3.8
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Typical SMPS efficiency versus load current and temperature . . . . . . . . . . . . .124
I/O system current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6.3.9
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.10
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
High-speed external user clock generated from an external source . . . . . . . . .129
Low-speed external user clock generated from an external source . . . . . . . . . .130
High-speed external clock generated from a crystal/ceramic resonator. . . . . . .131
Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .132
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6.3.11
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 133
48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .133
64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .134
4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .135
Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
6.3.12
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.13
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
6.3.14
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .141
Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .141
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.3.15
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 143
Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.3.16
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .144
6.3.17
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .149
Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .151
Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .152
6.3.18
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.19
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Synchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
SDRAM waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
6.3.20
Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.3.21
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.22
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
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6.3.23
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.3.24
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3.25
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.26
Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 200
6.3.27
Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 201
6.3.28
Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DS13315 Rev 2
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Contents
6.3.29
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.30
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.31
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.32
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 206
6.3.33
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 209
6.3.34
Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 210
6.3.35
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 211
6.3.36
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.3.37
Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.3.38
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .225
USB OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
7.2
TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
7.3
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
7.4
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Device marking for UFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
7.5
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Device marking for UFBGA169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
7.6
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Device marking for LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
7.7
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Device marking for UFBGA176+25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
7.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
DS13315 Rev 2
7/262
8
Contents
STM32H730xB
7.8.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
8/262
DS13315 Rev 2
STM32H730xB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
STM32H730xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
STM32H730xB pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STM32H730xB pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . 109
VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 111
SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 111
Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . 112
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 114
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption in Run mode,
code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 121
Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical current consumption in System Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 124
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 138
PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 139
DS13315 Rev 2
9/262
11
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
10/262
STM32H730xB
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 147
Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 148
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 157
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 157
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 160
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 166
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 178
Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
DS13315 Rev 2
STM32H730xB
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
List of tables
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 225
Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 226
USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 230
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 231
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 231
Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 240
LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
UFBGA144 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 246
UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 249
LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 256
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
DS13315 Rev 2
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11
List of figures
STM32H730xB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
12/262
STM32H730xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32H730xB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TFBGA100 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LQFP100 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TFBGA144 ballout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LQFP144 pinout (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LQFP176 pinout (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
UFBGA169 ballout (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
UFBGA176+25 ballout (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 124
Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . . 125
Typical SMPS efficiency (%) vs load current (A) in Stop and
DStop modes at TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 126
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 154
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 156
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 158
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 165
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 170
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 171
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 188
DS13315 Rev 2
STM32H730xB
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
List of figures
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 188
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
LQFP100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
UFBGA144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
UFBGA144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
UFBGA144 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
UFBGA169 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
LQFP176 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
UFBGA176+25 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
DS13315 Rev 2
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13
Introduction
1
STM32H730xB
Introduction
This document provides information on STM32H730xB microcontrollers, such as
description, functional overview, pin assignment and definition, packaging, and ordering
information.
This document should be read in conjunction with the STM32H730xB reference manual
(RM0468), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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DS13315 Rev 2
STM32H730xB
2
Description
Description
STM32H730xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. The Cortex -M7 core includes 32 Kbytes of
instruction cache and 32 Kbytes of data cache. STM32H730xB devices support a full set of
DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H730xB devices incorporate high-speed embedded memories with 128 Kbytes of
Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between
ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI,
128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access. To improve application robustness, all memories feature error code
correction (one error correction, two error detections).
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC co-processor for trigonometric functions and FMAC unit for filter functions). All the
devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power
comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit
timers including two PWM timers for motor control, five low-power timers, a true random
number generator (RNG), and a cryptographic acceleration cell, and a HASH processor.
The devices support four digital filters for external sigma-delta modulators (DFSDM). They
also feature standard and advanced communication interfaces.
•
Standard peripherals
–
Five I2Cs
–
Five USARTs, five UARTs and one LPUART
–
Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization. (Note that the five USARTs also provide SPI slave
capability.)
–
Two SAI serial audio interfaces
–
One SPDIFRX interface with four inputs
–
One SWPMI (Single Wire Protocol Master Interface)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces
–
A USB OTG high-speed interface with full-speed capability (with the ULPI)
–
Two FDCANs plus one TT-FDCAN interface
–
An Ethernet interface
–
Chrom-ART Accelerator
–
HDMI-CEC
DS13315 Rev 2
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56
Description
STM32H730xB
•
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
Two Octo-SPI memory interfaces with on-the-fly decryption (OTFDEC)
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
Refer to Table 1: STM32H730xB features and peripheral counts for the list of peripherals
available on each part number.
To reduce the power consumption some STM32H730xB devices include an optional stepdown converter that can be used either for internal or external supply, or both.
STM32H730xB devices operate in the –40 to +85 °C ambient temperature range from a
1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an
external power supervisor (see Section 3.8.2: Power supply supervisor) and connecting the
PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the
embedded power voltage detector enabled.
Dedicated supply inputs for USB are available to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H730xB devices are offered in several packages ranging from 100 to 176 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H730xB microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
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DS13315 Rev 2
STM32H730xB
Description
Figure 1. STM32H730xB block diagram
MII / RMII
To APB1-2
peripherals
MDIO
as AF
AHB1
D-TCM
64KB
I-TCM 64KB
AHBP
FIFO
LCD-TFT
WWDG
OCTOSPI1
signals
AHB4
CH[4;1], ETR as AF
32b
TIM23
CH[4;1], ETR as AF
32b
TIM24
CH[4;1], ETR as AF
16b
TIM12
CH[2;1] as AF
16b
TIM13
CH1 as AF
16b
TIM14
CH1 as AF
USART2
RX, TX, CK, CTS, RTS, DE as AF
USART3
RX, TX, CK, CTS, RTS, DE as AF
UART4
RX, TX, CTS, RTS, DE as AF
UART5
RX, TX, CTS, RTS, DE as AF
UART7
RX, TX, CTS, RTS, DE as AF
RX, TX, CTS, RTS, DE as AF
SPI1/I2S1
UART9
AHB4
DMA
Mux2
AHB4
BDMA
DAP
TIM1/PWM
16b
HSEM
16b
CRC
ADC3
I2C2/SMBUS
I2C3/SMBUS
SCL, SDA, SMBA as AF
I2C5/SMBUS
SCL, SDA, SMBA as AF
MDIOS
MDC, MDIO as AF
TT-FDCAN1
FDCAN2
FDCAN3
16 KB SRAM
4 KB BKP
RAM
SPDIFRX1
HDMI-CEC
DAC
16b
LPTIM4
16b
OUT as AF
LPTIM3
16b
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
RX, TX, CK, CTS, RTS as AF
LPUART1
IN1, IN2, ETR, OUT as AF
LPTIM2
16b
AHB/APB
VREF
VINM, VINP, VOUT as AF
Voltage
regulator
3.3 to 1.2V
IWDG
Temperature
sensor
HSI RC
HSI
HSI48
HSI48 RC
CSI RC
CSI
LSI
LSI RC
VDD
VSS
VCAP, VDDLDO
VDDSMPS, VSSSMPS,
VLXSMPS, VFBSMPS
VBAT
XTAL 32 kHz
@VDD
IN1, IN2, ETR, OUT as AF
OPAMP2
@VSW
SYSCFG
EXTI WKUP
CEC as AF
OUT1, OUT2 as AF
VINM, VINP, VOUT as AF
LS
LPTIM5
IN[1:4] as AF
OPAMP1
VCORE BBgen + POWER MNGT
RTC
Backup registers
LS
OUT as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
@VDD
PWRCTRL
SAI4
COMP1&2
OUT as AF
LPTIM1
16b
RCC
Reset &
control
AHB4 (275MHz)
GPIO PORTJ,K
APB4
MHz
(max)
APB4
138138
MHz
(max)
PJ,PK[11:0]
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
USBCR
FIFO
USART1
TIM8/PWM
SPI3/I2S3
I2C1/SMBUS
RAM
I/F
32-bit AHB BUS-MATRIX
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI2/I2S2
APB1 138 MHz (max)
SPI4
10 KB SRAM
TIM15
GPIO PORTA.. H
SCL, SDA, SMBA as AF
CH[4;1], ETR as AF
TIM5
A P B 10 MHz
3
TIM17
TIM16
PA..H[15:0]
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
TIM4
32b
UART8
USART6
Up to 17 analog inputs
Some common to ADC1 and 2
16b
SPI5
USART10
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
CH[4;1], ETR as AF
FIFO
SAI1
RX, TX, CK, CTS, RTS, DE as AF
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
16b
CH[4;1], ETR as AF
TIM3
DFSDM
RX, TX, CK, CTS, RTS, DE as AF
RX, TX, CK, CTS, RTS, DE as AF
TIM7
TIM2
16b
AHB/APB
AHB4
RX, TX, CTS, RTS, DE as AF
16b
SWPMI
AHB4_MEMD3 (275MHz)
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
PSSI
AHB4 (275MHz)
MOSI, MISO, SCK, NSS as AF
TIM6
32b
Digital filter
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
DCMI
AHB4
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
FMAC
AHB2 (275MHz)
Up to 20 analog inputs Most
are common to ADC1 & 2
ADC2
AHB/APB
CORDIC
AXI/AHB34 (275MHz)
APB2 138 MHz (max)
MOSI, MISO, SCK, NSS as AF
ADC1
AHB4
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
3DES/AES
AHB3
FIFO
SDMMC1
APB4 138 MHz (max)
CKOUT, DATIN[7:0], CKIN[7:0]
HASH
SRAM1 SRAM2
16 KB 16 KB
DLYBOS1-2
AHB/APB
DLYBSD2
HSYNC, VSYNC, PIXCLK, D[13:0]
PDCK, DE, RDY, D[15:0]
RNG
OCTOSPI2
signals
DLYBSD1
D[7:0], D123DIR, D0DIR,
CMD, CKas AF
DMA/
FIFO
FIFO
32-bit AHB BUS-MATRIX
DMA
Mux1
FMC_signals
AHB2 (275MHz)
FIFO
OTFDEC2
APB3 (138MHz)
CHROM-ART
(DMA2D)
64-bit AXI BUS-MATRIX
16 Streams
FIFO
OTFDEC1
AHBS
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
DMA/
FIFO
8 Stream 8 Stream
FIFOs
FIFOs
128KB
FLASH
FMC
D-Cache
32KB
MDMA
PHY
ETHER
SDMMC2 OTG_HS
MAC
AHB1 (275MHz)
AXIM
ETM
I-Cache
32KB
DMA2
(275MHz)
AXI/AHB12 (275MHz)
OCTOSPIM
TRACECLK
TRACED[3:0]
128 KB AXI
SRAM
Arm CPU
JTAG/SW
Cortex-M7
550 MHz
OCTOSPI1
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWDIO, JTDO
DMA1
Shared AXI
I-TCM 192KB
OCTOSPI2
D-TCM
64KB
D[7:0],DP, DM, STP,
D123DIR, NXT,ULPI:CK
D0DIR, , D[7:0], DIR,
CMD, CKas AF ID, VBUS
AWU
OSC32_IN
OSC32_OUT
TS, TAMP1, TAMP3,
OUT, REFIN
@VDD
XTAL OSC
4- 48 MHz
PLL1+PLL2+PLL3
OSC_IN
OSC_OUT
@VDD
POR
reset
Int
SUPPLY SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[1;2;4;6]
MSv65314V2
DS13315 Rev 2
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56
Description
STM32H730xB
Table 1. STM32H730xB features and peripheral counts
STM32H730IBT6Q
-
yes
yes
yes
yes
yes
Multiplexed I/O
NOR Flash
memory
yes
yes
yes
yes
yes
yes
yes
16-bit NAND
Flash memory
yes
yes
yes
yes
yes
yes
yes
16-bit SDRAM
controller
-
-
yes
yes
yes
yes
yes
24-bit SDRAM
controller(1)
-
-
-
-
-
yes
-
112
114
121
128
119
STM32H730VBT6
Flash memory (Kbytes)
SRAM
(Kbytes)
128
SRAM mapped
onto AXI bus
128
SRAM1
(D2 domain)
16
SRAM2
(D2 domain)
16
SRAM4
(D3 domain)
16
RAM shared between ITCM
and AXI (Kbytes)
192
ITCM RAM
TCM RAM (instruction)
in Kbytes
DTCM RAM
64
128
(data)
Backup SRAM (Kbytes)
4
Interface
FMC
GPIO
18/262
STM32H730ZBI6
-
STM32H730ZBT6
NOR Flash
memory/RAM
controller
Peripherals
STM32H730VBH6
STM32H730IBK6Q
SMPS
STM32H730ABI6Q
no SMPS
1
80
DS13315 Rev 2
STM32H730xB
Description
Table 1. STM32H730xB features and peripheral counts (continued)
STM32H730ZBT6
STM32H730ZBI6
STM32H730ABI6Q
STM32H730IBK6Q
STM32H730IBT6Q
Octo-SPI interface
STM32H730VBH6
Peripherals
SMPS
STM32H730VBT6
no SMPS
2(2)
2(2)
2
2
2
2
2
OTFDEC
yes
Cordic
yes
FMAC
yes
General purpose
32 bits
2
2
2
2
2
2
2
General purpose
16 bits
10
10
10
10
10
10
10
Advanced control
(PWM)
2
2
2
2
2
2
2
Basic
2
2
2
2
2
2
2
Low-power
5
5
5
5
5
5
5
RTC
1
1
1
1
1
1
1
Window
watchdog /
independent
watchdog
2
2
2
2
2
2
2
Wakeup pins
4
4
4
4
4
4
4
Tamper pins
2
2
2
2
2
2
2
Timers
Random number generator
yes
Cryptographic accelerator
yes
DS13315 Rev 2
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56
Description
STM32H730xB
Table 1. STM32H730xB features and peripheral counts (continued)
STM32H730VBH6
STM32H730ZBT6
STM32H730ZBI6
STM32H730ABI6Q
STM32H730IBK6Q
STM32H730IBT6Q
SMPS
STM32H730VBT6
no SMPS
5/4
5/4
6/4
6/4
4/4
6/4
6/4
5
5
5
5
5
5
5
USART/UART/
LPUART
5/5/1
5/5/1
5/5/1
5/5/1
5/5/1
5/5/1
5/5/1
SAI/PDM
2/1(3)
2/1(3)
2/1
2/1
2/1
2/1
2/1
Peripherals
SPI / I2S
I2C
SPDIFRX
1
HDMI-CEC
Communic
SWPMI
ation
interfaces MDIO
1
1
1
SDMMC
FDCAN/TTFDCAN
2
2/1
2/1
2/1
2/1
2/1
2/1
2/1
USB
[OTG_HS(ULPI)/
FS(PHY)]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
Ethernet
[MII/RMII]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
Camera interface/PSSI
yes
LCD-TFT
yes
Chrom-ART Accelerator
(DMA2D)
yes
Number of ADCs
Number of Direct
channels
ADC1/ADC2
16-bit
ADCs
20/262
2
0
2/2
0
2/2
2/2
2/2
0
Number of Fast
channels
ADC1/ADC2
3/2
3/2
4/3
4/3
6/5
6/5
4/3
Number of Slow
channels
ADC1/ADC2
11/10
9/8
12/11
12/11
12/11
12/11
12/11
DS13315 Rev 2
STM32H730xB
Description
Table 1. STM32H730xB features and peripheral counts (continued)
STM32H730IBT6Q
2
2
2
2
2
2
2
Number of Fast
channels
2
6
6
6
6
6
6
Number of Slow
channels
0
9
4
9
9
9
4
STM32H730ZBI6
STM32H730ZBT6
STM32H730VBH6
Number of Direct
channels
Peripherals
STM32H730VBT6
STM32H730IBK6Q
SMPS
STM32H730ABI6Q
no SMPS
Number of ADCs
12-bit
ADCs
1
Present in IC
yes
12-bit DAC Number of
channels
2
Comparators
2
Operational amplifiers
2
DFSDM
Present in IC
yes
Maximum CPU frequency
550 MHz
USB separate supply pad
-
yes
yes
yes
yes
yes
yes
USB internal regulator
-
-
-
-
yes
yes
yes
LDO
yes
SMPS step-down converter
Operating voltage
no
yes
1.71 to
3.6 V
1.62 to 3.6 V
Operating temperature
Package
-40°C to +85°C
LQFP
100
TFBGA
100
LQFP
144
UFBGA
144
UFBGA
169
UFBGA
176+25
LQFP176
1. The 24-bit SDRAM controller is a 32-bit controller with only a 24-bit data bus and without NBL2-3. It can be used for
graphical purposes to access aligned 32-bit words ignoring upper 8 bits.
2. The two Octo-SPI/Quad-SPI interfaces are available only in Muxed mode.
3. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7: STM32H730xB pin
and ball descriptions.
DS13315 Rev 2
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56
Functional overview
STM32H730xB
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache)
•
64-bit AXI interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H730xB family.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
22/262
DS13315 Rev 2
STM32H730xB
Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H730xB devices embed 128 Kbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
one Flash word (8 words, 32 bytes or 256 bits)
•
10 ECC bits (single-error correction and double-error detection).
The Flash memory is organized as follows:
3.3.2
•
One sector of 128 Kbytes of user Flash memory (4 K Flash memory words)
•
128 Kbytes of system Flash memory from which the device can boot
•
2 Kbytes (64 Flash words) of user option bytes for user configuration
Embedded SRAM
All devices feature:
•
from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain
•
SRAM1 mapped on D2 domain: 16 Kbytes
•
SRAM2 mapped on D2 domain: 16 Kbytes
•
SRAM4 mapped on D3 domain: 16 Kbytes
•
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the
Cortex®-M7CPU(AHBSAHBP):
–
64 to 256 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected
above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte
granularity.
DS13315 Rev 2
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56
Functional overview
STM32H730xB
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
7 ECC bits are added per 32-bit word.
•
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4
Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H730xB
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
•
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
•
User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services is activated for the next reset exits through an option bit.
24/262
DS13315 Rev 2
STM32H730xB
3.5
Functional overview
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space
•
All RAM address space: ITCM, DTCM RAMs and SRAMs
•
The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to
application note AN2606 “STM32 microcontroller System memory Boot mode” for details.
3.6
CORDIC co-processor (CORDIC)
The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
CORDIC features
•
24-bit CORDIC rotation engine
•
Circular and Hyperbolic modes
•
Rotation and Vectoring modes
•
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
Programmable precision up to 20-bit
•
Fast convergence: 4 bits per clock cycle
•
Supports 16-bit and 32-bit fixed point input and output formats
•
Low latency AHB slave interface
•
Results can be read as soon as ready without polling or interrupt
•
DMA read and write channels
DS13315 Rev 2
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56
Functional overview
3.7
STM32H730xB
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
FMAC features
•
16 x 16-bit multiplier
•
24+2-bit accumulator with addition and subtraction
•
16-bit input and output data
•
256 x 16-bit local memory
•
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
Input and output sample buffers can be circular
•
Buffer “watermark” feature reduces overhead in interrupt mode
•
Filter functions: FIR, IIR (direct form 1)
•
AHB slave interface
•
DMA read and write data channels
3.8
Power supply management
3.8.1
Power supply scheme
STM32H730xB power supply voltages are the following:
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•
VDD33USB: allows the support of a VDD supply different from 3.3 V while powering the
USB transceiver with 3.3V on VDD33USB.
•
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows support of a VDD supply different to 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
26/262
•
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•
VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The
DS13315 Rev 2
STM32H730xB
Functional overview
VCORE domain is split into the following power domains that can be independently
switch off.
–
D1 domain containing some peripherals and the Cortex®-M7 core
–
D2 domain containing a large part of the peripherals
–
D3 domain containing some peripherals and the system control
•
VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply VDDSMPS
must be kept at the same voltage level as VDD
•
VLXSMPS = SMPS step-down converter output coupled to an inductor
•
VFBSMPS = VCORE or 1.8 V or 2.5 V external SMPS step-down converter feedback
voltage sense input.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
•
When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•
When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
Figure 2. Power-up/power-down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
DS13315 Rev 2
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56
Functional overview
3.8.2
STM32H730xB
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
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DS13315 Rev 2
STM32H730xB
3.8.3
Functional overview
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
•
3.9
Run mode (VOS0 to VOS3)
–
Scale 0: boosted performance (available only with LDO regulator)
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The
peripheral functionality is disabled but wakeup from Stop mode is possible through
GPIO or asynchronous interrupt.
Low-power strategy
There are several ways to reduce power consumption on STM32H730xB:
•
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
•
Save power when the CPU is idle, by selecting among the available low-power modes
according to the user application needs. This allows the best compromise between
short startup time and low power consumption to be achieved, according to the
available wakeup sources.
The devices feature several low-power modes:
•
CSleep (CPU clock stopped)
•
CStop (CPU sub-system clock stopped)
•
DStop (Domain bus matrix clock stopped)
•
Stop (System clock stopped)
•
DStandby (Domain powered down)
•
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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Functional overview
STM32H730xB
Table 2. System versus domain low-power mode
System power mode
D1 domain power mode
D2 domain power mode
D3 domain power mode
Run
DRun/DStop/DStandby
DRun/DStop/DStandby
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
3.10
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), thus the system frequency can be changed without modifying the
baudrate.
3.10.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
•
Internal oscillators:
–
64 MHz HSI clock
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
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3.10.2
Functional overview
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
3.11
•
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Window watchdog
•
Independent watchdog
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.12
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
the interconnection of bus masters with bus slaves (see Figure 3).
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STM32H730xB
Figure 3. STM32H730xB bus matrix
AHBS
OR
DMA2D
LTDC
D1-to-D2 AHB
DMA2_MEM
MDMA
DMA1_MEM
SDMMC1
DMA2
Ethernet SDMMC2 USBHS1
MAC
DMA2_PERIPH
DMA1
AHBP
AXIM
I$
D$
32KB 32KB
ITCM
64 Kbyte
ITCM
192 Kbyte
DTCM
128 Kbyte
DMA1_PERIPH
CPU
Cortex-M7
AXI SRAM
192K byte
SRAM1 16
Kbyte
SRAM2 16
Kbyte
Flash A
128 Kbytes
AHB1
DS13315 Rev 2
AXI SRAM
128 Kbyte
OTFDEC1
OCTOSPI1
OTFDEC2
OCTOSPI2
AHB2
APB1
FMC
AHB3
APB2
APB3
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
Legend
32-bit bus
AHB4
TCM AHB
AXI
APB
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64-bit bus
Master interface
Bus multiplexer
Slave interface
APB4
SRAM4
16 Kbyte
Backup
SRAM
4 Kbyte
MSv65315V1
Functional overview
BDMA
32-bit AHB bus matrix
D3 domain
STM32H730xB
3.13
Functional overview
DMA controllers
The devices feature four DMA instances and a DMA request router to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
•
A DMA request multiplexer (DMAMUX)
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing
managing the DMA requests with a high flexibility, maximizing the number of DMA
requests that run concurrently, as well as generating DMA requests from peripheral
output trigger or DMA event.
3.14
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation.
It can perform the following operations:
•
Filling a part or the whole of a destination image with a specific color
•
Copying a part or the whole of a source image into a part or the whole of a destination
•
image
•
Copying a part or the whole of a source image into a part or the whole of a destination
•
image with a pixel format conversion
•
Blending a part and/or two complete source images with different pixel format and copy
•
the result into a part or the whole of a destination image with a different color format.
•
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel
with indexed or direct color mode, including block based YCbCr to handle JPEG
decoder output.
•
The DMA2D has its own dedicated memories for CLUTs (color look-up tables).
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automated and are running independently from the CPU or the
DMAs.
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Functional overview
3.15
STM32H730xB
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.16
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events
and 54 direct events.
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.17
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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3.18
Functional overview
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
3.19
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-, 24-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
Octo-SPI memory interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal
SPI memories. The STM32H730xB embeds two separate Octo-SPI interfaces.
Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of
single/dual/quad/octal SPI over the same bus can be achieved using the integrated OctoSPI I/O manager (OCTOSPIM).
The OCTOSPI can operate in any of the three following modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers
•
Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory supporting both read and write operations.
The OCTOSPI supports two frame formats supported by most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and
Hyper Flash memories.
Multi chip package (MCP) combining any of the above mentioned memory types can also
be supported.
•
The classical frame format with the command, address, alternate byte, dummy cycles
and data phase
•
The HyperBus™ frame format.
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Functional overview
3.20
STM32H730xB
Analog-to-digital converters (ADCs)
STM32H730xB devices embed three analog-to-digital converters, two of 16-bit resolution,
and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14,
12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some, or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers.
3.21
Temperature sensor
STM32H730xB devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 to +125°C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.22
Digital temperature sensor (DTS)
STM32H730xB devices embed a sensor that converts the temperature into a square wave
the frequency of which is proportional to the temperature. The PCLK or the LSE clock can
be used as the reference clock for the measurements. A formula given in the product
reference manual allows calculation of the temperature according to the measured
frequency stored in the DTS_DR register.
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3.23
Functional overview
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
3.24
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
external triggers for conversion
•
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
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Functional overview
3.25
STM32H730xB
Ultra-low-power comparators (COMP)
STM32H730xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
An external I/O
•
A DAC output channel
•
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.26
Operational amplifiers (OPAMP)
STM32H730xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
One positive input connected to DAC
•
Output connected to internal ADC
•
Low input bias current down to 1 nA
•
Low input offset voltage down to 1.5 mV
•
Gain bandwidth up to 7.3 MHz
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
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3.27
Functional overview
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
up to 24-bit output data resolution, signed output data format
•
automatic data offset correction (offset stored in register by user)
•
continuous or single conversion
•
start-of-conversion triggered by:
•
•
•
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
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Functional overview
•
STM32H730xB
extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
•
DMA capability to read the final conversion data
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
•
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Pulse skipper feature to support beamforming applications (delay-line like behavior).
Table 3. DFSDM implementation
DFSDM features
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DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
DS13315 Rev 2
STM32H730xB
3.28
Functional overview
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
3.29
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports Continuous mode or Snapshot (a single frame) mode
•
Capability to automatically crop the image
PSSI
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The main PSSI features are:
•
Slave mode operation
•
8- or 16-bit parallel data input or output
•
8-word (32-byte) FIFO
•
Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data is
valid or, the receiver to indicate when it is ready to sample the data, or both.
The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore
cannot be used simultaneously with the DCMI.
3.30
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024 x 768) resolution with the following features:
•
2 display layers with dedicated FIFO (64x64-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
•
AXI master interface with burst of 16 words
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Functional overview
3.31
STM32H730xB
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as
a NIST SP 800-90B compliant entropy source.
The RNG true random number generator has been tested using German BSI statistical tests
of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite.
3.32
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and nonrepudiation when exchanging messages
with a peer:
•
•
Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal HASH
–
– SHA-1 and SHA-2 (secure HASH algorithms)
–
– MD5
–
– HMAC
The cryptographic accelerator supports DMA request generation.
3.33
On-the-fly decryption engine (OTFDEC)
The embedded OTFDEC decrypts in real-time the encrypted content stored in the external
Octo-SPI memories used in Memory-mapped mode.
The OTFDEC uses the AES-128 algorithm in counter mode (CTR).
Code execution on external Octo-SPI memories can be protected against fault injection
thanks to
STMicroelectronics enhanced encryption mode (refer to RM0468 for details).
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Functional overview
The OTFDEC main features are as follow:
•
•
On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or
multiple).
–
AES-CTR algorithm with keystream FIFO (depth= 4)
–
Support for any read size
Up to four independent encrypted regions
–
Region definition granularity: 4096 bytes
–
Region configuration write locking mechanism
–
Two optional decryption modes: execute-only and execute-never
•
128-bit key for each region, two-byte firmware version, and eight-byte applicationdefined nonce
•
Encryption keys confidentiality and integrity protection
•
–
Write only registers with software locking mechanism
–
Availability of 8-bit CRC as public key information
Support for STM32 Octo-SPI prefetching mechanism.
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Functional overview
3.34
STM32H730xB
Timers and watchdogs
The devices include two advanced-control timers, twelve general-purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Timer
type
Advanced
-control
Timer
TIM1,
TIM8
TIM2,
TIM5,
TIM23,
TIM24
TIM3,
TIM4
TIM12
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
TIM15
TIM16,
TIM17
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Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
Yes
137.5
275
32-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
137.5
275
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
137.5
275
16-bit
Up
Any
integer
between 1
and
65536
No
2
No
137.5
275
Up
Any
integer
between 1
and
65536
No
1
No
137.5
275
Up
Any
integer
between 1
and
65536
Yes
2
1
137.5
275
Up
Any
integer
between 1
and
65536
Yes
1
1
137.5
275
General
purpose
TIM13,
TIM14
Complementary
output
16-bit
16-bit
16-bit
DS13315 Rev 2
STM32H730xB
Functional overview
Table 4. Timer feature comparison (continued)
Timer
type
Timer
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and
65536
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32,
64, 128
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
Yes
0
No
137.5
275
No
0
No
137.5
275
1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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Functional overview
3.34.1
STM32H730xB
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (Edge- or Center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.34.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H730xB
devices (see Table 4: Timer feature comparison for differences).
•
TIM2, TIM3, TIM4, TIM5, TIM23, TIM24
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5,
TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit
auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent
channels for input capture/output compare, PWM or One-pulse mode output. This
gives up to 24 input capture/output compare/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together,
or with the other general-purpose timers and the advanced-control timers TIM1 and
TIM8 via the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request
generation. They are capable of handling quadrature (incremental) encoder signals
and the digital outputs from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5,
TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases.
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3.34.3
Functional overview
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.34.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.34.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / One-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
A window option allows the device to be reset when a reload operation is made too early
after the previous reload.
3.34.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.34.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
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Functional overview
3.35
STM32H730xB
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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3.36
Functional overview
Inter-integrated circuit interface (I2C)
STM32H730xB devices embed five I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
3.37
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H730xB devices have five embedded universal synchronous receiver transmitters
(USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous
receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 5:
USART features for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO
7816 compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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Functional overview
STM32H730xB
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6/10
UART4/5/7/8/9
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
16
1. X = supported.
3.38
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.39
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available.
They can be operated in Master or Slave mode, in Simplex communication modes, and can
be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6
which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are
supported. When either or both of the I2S interfaces is/are configured in Master mode, the
master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA
capability.
3.40
Serial audio interfaces (SAI)
The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono
audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF
output is available when the audio block is configured as a transmitter. To bring this level of
flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each
block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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Functional overview
3.41
STM32H730xB
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.42
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
Full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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3.43
Functional overview
Management data input/output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
3.44
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from Stop mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.45
Controller area network (FDCAN1, FDCAN2, FDCAN3)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the three modules - FDCAN1 FDCAN2 and FDCAN3.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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56
Functional overview
3.46
STM32H730xB
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral
that supports both full-speed and high-speed operations. It integrates the transceivers for
full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external
PHY device connected to the ULPI is required.
The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
3.47
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
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Functional overview
The devices include the following features:
3.48
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.49
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
Breakpoint debugging
•
Code execution tracing
•
Software instrumentation
•
JTAG debug port
•
Serial-wire debug port
•
Trigger input and output
•
Serial-wire trace port
•
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The trace port performs data capture for logging and analysis.
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Memory mapping
4
STM32H730xB
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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5
Pinouts, pin descriptions and alternate functions
Pinouts, pin descriptions and alternate functions
Figure 4. TFBGA100 pinout (without SMPS)
1
2
3
4
5
6
7
8
9
10
A
PC14OSC32_IN
PC13
PE2
PB9
PB7
PB4
PB3
PA15
PA14
PA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
PH0-OSC_IN
VSS
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
PH1OSC_OUT
VDD
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PC2_C
PE6
VSS
VSS
VSS
VCAP
PD1
PC9
PC7
F
PC0
PC1
PC3_C
VDD
VDD
VDD33USB
PDR_ON
VCAP
PC8
PC6
G
VSSA
PA0
PA4
PC4
PB2
PE10
PE14
PD15
PD11
PB15
H
VDDA
PA1
PA5
PC5
PE7
PE11
PE15
PD14
PD10
PB14
J
VSS
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDD
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
MSv52520V1.
1. The above figure shows the package top view.
DS13315 Rev 2
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102
Pinouts, pin descriptions and alternate functions
STM32H730xB
VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 5. LQFP100 pinout (without SMPS)
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VCAP
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA11
PC13
7
69
PA10
PC14-OSC32_IN
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0-OSC_IN
12
64
PC7
PH1-OSC_OUT
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2_C
17
59
PD12
PC3_C
18
58
PD11
VSSA
19
57
PD10
VREF+
20
56
PD9
VDDA
21
55
PD8
PA0
22
54
PB15
PA1
23
53
PB14
PA2
24
52
PB13
PA3
25
51
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
LQFP100
MSv52521V1.
1. The above figure shows the package top view.
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Pinouts, pin descriptions and alternate functions
Figure 6. TFBGA144 ballout (without SMPS)
1
2
3
4
5
6
7
8
9
10
11
12
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
F
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
G
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
MSv65136V1
1. The above figure shows the package top view.
DS13315 Rev 2
59/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 7. LQFP144 pinout (without SMPS)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
MSv52522V1.
1. The above figure shows the package top view.
60/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD
VDDLDO
PDR_ON
VSS
VCAP
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VSS
VDD
VDDLDO
VSS
VCAP
Figure 8. LQFP176 pinout (with SMPS)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LQFP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA13
PA12
PA11
PA10
PA9
PA8
VDD
PC9
PC8
PC7
PC6
VDD33USB
VDD50USB
VSS
PG8
PG7
PG6
PG5
PG4
VDD
VSS
PG3
PG2
PK2
PK1
PK0
VSS
VDD
PJ11
PJ10
PJ9
PJ8
VSS
VDD
PD15
PD14
PD13
PD12
PD11
VSS
VDD
PD10
PD9
PD8
VSS
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
PF13
PF14
PF15
PG0
VSS
VDD
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDDLDO
VSS
VDD
PB12
PB13
PB14
PB15
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PE2
PE3
PE4
PE5
PE6
VSS
VDD
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PA1
PA2
VDD
MSv52553V1.
1. The above figure shows the package top view.
DS13315 Rev 2
61/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Figure 9. UFBGA169 ballout (with SMPS)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PE4
PE2
VDD
VCAP
PB6
VDD
VDD
PG10
PD5
VDD
PC12
PC10
PH14
B
PC15OSC32_OUT
PE3
VSS
VDDLDO
PB8
PB4
VSS
PG11
PD6
VSS
PC11
PA14
PH13
C
PC14OSC32_IN
PE6
PE5
PDR_ON
PB9
PB5
PG14
PG9
PD4
PD1
PA15
VSS
VDD
D
VDD
VSS
PC13
PE1
PE0
PB7
PG13
PD7
PD3
PD0
PA13
VDDLDO
VCAP
E
VLXSMPS
VSSSMPS
VBAT
PF1
PF3
BOOT0
PG15
PG12
PD2
PA10
PA9
PA8
PA12
F
VDDSMPS
VFBSMPS
PF0
PF2
PF5
PF7
PB3
PG4
PC6
PC7
PC9
PC8
PA11
G
VDD
VSS
PF4
PF6
PF9
NRST
PF13
PE7
PG6
PG7
PG8
VDD50USB
VDD33USB
H
PH0-OSC_IN
PH1OSC_OUT
PF10
PF8
PC2
PA4
PF14
PE8
PG2
PG3
PG5
VSS
VDD
J
PC0
PC1
VSSA
PC3
PA0
PA7
PF15
PE9
PE14
PD11
PD13
PD15
PD14
K
PC3_C
PC2_C
PA0_C
PA1
PA6
PC4
PG0
PE13
PH10
PH12
PD9
PD10
PD12
L
VDDA
VREF+
PA1_C
PA5
PB1
PB2
PG1
PE12
PB10
PH11
PB13
VSS
VDD
M
VDD
VSS
PH3
VSS
PB0
PF11
VSS
PE10
PB11
VDDLDO
VSS
PD8
PB15
N
PA2
PH2
PA3
VDD
PC5
PF12
VDD
PE11
PE15
VCAP
VDD
PB12
PB14
MSv52551V1.
1. The above figure shows the package top view.
Figure 10. UFBGA176+25 ballout (with SMPS)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
VSS
PB8
VDDLDO
VCAP
PB6
PB3
PG11
PG9
PD3
PD1
PA15
PA14
VDDLDO
VCAP
VSS
B
PE4
PE3
PB9
PE0
PB7
PB4
PG13
PD7
PD5
PD2
PC12
PH14
PA13
PA8
PA12
C
PC13
VSS
PE2
PE1
BOOT0
PB5
PG14
PG10
PD4
PD0
PC11
PC10
PH13
PA10
PA11
D
PC15OSC32_OUT
PC14OSC32_IN
PE5
PDR_ON
VDD
VSS
PG15
PG12
PD6
VSS
VDD
PH15
PA9
PC8
PC7
E
VSS
VBAT
PE6
VDD
VDD
PC9
PC6
VDD50USB
F
VLXSMPS
VSSSMPS
PF1
PF0
VSS
VSS
VSS
VSS
VSS
VSS
VDD33USB
PG6
PG5
G
VDDSMPS
VFBSMPS
PF2
VDD
VSS
VSS
VSS
VSS
VSS
PG8
PG7
PG4
PG2
H
PF6
PF4
PF5
PF3
VSS
VSS
VSS
VSS
VSS
VDD
PG3
PD14
PD13
J
PH0-OSC_IN
PF8
PF7
PF9
VSS
VSS
VSS
VSS
VSS
PD15
PD11
VSS
PD12
K
PH1OSC_OUT
VSS
PF10
VDD
VSS
VSS
VSS
VSS
VSS
VSS
PD9
PB15
PB14
L
NRST
PC0
PC1
VREF-
VDD
PD10
PD8
PB13
M
PC2
PC3
VREF+
VDDA
VDD
VSS
PC5
PH11
PH9
PB12
N
PC2_C
PC3_C
VSSA
PH2
PA3
PA7
P
PA0
PA1
PA1_C
PH4
PA4
PA5
R
VSS
PA2
PA0_C
PH3
PH5
PC4
PB1
VDD
VSS
PH7
PE14
PF11
PE8
PB2
PG0
PG1
PF15
PF13
PB10
PH8
PH10
PH12
PE7
PB11
PF12
PE12
PE13
PE15
PH6
PA6
PB0
PE10
PF14
PE9
PE11
VCAP
VDDLDO
VSS
MSv52552V1.
1. The above figure shows the package top view.
62/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 6. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
I/O structure
Notes
Pin functions
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DS13315 Rev 2
63/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions
B3
C3
D3
1
2
3
4
1
2
3
4
A2
B2
B3
A2
B2
A1
C3
C3
B2
B1
D3
1
2
3
4
PE2
PE3
PE4
I/O
FT
_h
I/O
FT
_h
I/O
PE5
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
A3
Pin name
(function after
reset)
I/O
FT
_h
FT
_h
Notes
A3
LQFP144
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
TRACECLK, SAI1_CK1,
USART10_RX, SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
OCTOSPIM_P1_IO2,
SAI4_CK1, ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
-
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
USART10_TX, FMC_A19,
EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N, SPI4_NSS,
SAI1_FS_A, SAI4_FS_A,
SAI4_D2, FMC_A20,
DCMI_D4/PSSI_D4, LCD_B0,
EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21,
DCMI_D6/PSSI_D6, LCD_G0,
EVENTOUT
-
-
E3
5
5
B4
C2
E3
5
PE6
I/O
FT
_h
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI4_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22,
DCMI_D7/PSSI_D7, LCD_G1,
EVENTOUT
-
-
-
-
-
-
6
VSS
S
-
-
-
-
-
-
-
-
-
-
7
VDD
S
-
-
-
-
B2
6
6
C2
E3
E2
8
VBAT
S
-
-
-
-
A2
7
7
A1
D3
C1
9
PC13
I/O
FT
-
EVENTOUT
RTC_TAMP1/
RTC_TS, WKUP4
A1
8
8
B1
C1
D2
10
PC14-OSC32_IN
I/O
FT
-
EVENTOUT
OSC32_IN
64/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
Pin type
I/O structure
Notes
Pin Number
Alternate functions
B1
9
9
C1
B1
D1
11
PC15OSC32_OUT
I/O
FT
-
EVENTOUT
OSC32_OUT
-
-
-
-
-
-
12
VSS
S
-
-
-
-
-
-
-
-
-
-
13
VDD
S
-
-
-
-
-
-
-
-
E2
F2
14
VSSSMPS
S
-
-
-
-
-
-
-
-
E1
F1
15
VLXSMPS
S
-
-
-
-
-
-
-
-
F1
G1
16
VDDSMPS
S
-
-
-
-
-
-
-
-
F2
G2
17
VFBSMPS
S
-
-
-
-
-
I2C2_SDA(boot), I2C5_SDA,
OCTOSPIM_P2_IO0,
FMC_A0, TIM23_CH1,
EVENTOUT
-
-
I2C2_SCL(boot), I2C5_SCL,
OCTOSPIM_P2_IO1,
FMC_A1, TIM23_CH2,
EVENTOUT
-
-
Pin name
(function after
reset)
-
-
10
C3
F3
F4
18
PF0
I/O
FT
_fh
-
-
11
C4
E4
F3
19
PF1
I/O
FT
_fh
-
I2C2_SMBA, I2C5_SMBA,
OCTOSPIM_P2_IO2,
FMC_A2, TIM23_CH3,
EVENTOUT
Additional
functions
-
-
12
D4
F4
G3
20
PF2
I/O
FT
_h
-
-
13
E2
E5
H4
21
PF3
I/O
FT
_ha
-
OCTOSPIM_P2_IO3,
FMC_A3, TIM23_CH4,
EVENTOUT
ADC3_INP5
-
-
14
E3
G3
H2
22
PF4
I/O
FT
_ha
-
OCTOSPIM_P2_CLK,
FMC_A4, EVENTOUT
ADC3_INN5,
ADC3_INP9
-
-
15
E4
F5
H3
23
PF5
I/O
FT
_ha
-
OCTOSPIM_P2_NCLK,
FMC_A5, EVENTOUT
ADC3_INP4
-
10
16
-
-
-
24
VSS
S
-
-
-
-
-
11
17
-
-
-
25
VDD
S
-
-
-
-
-
TIM16_CH1, FDCAN3_RX,
SPI5_NSS, SAI1_SD_B,
UART7_RX, SAI4_SD_B,
OCTOSPIM_P1_IO3,
TIM23_CH1, EVENTOUT
ADC3_INN4,
ADC3_INP8
-
-
18
F3
G4
H1
26
PF6
FT
I/O
_ha
DS13315 Rev 2
65/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
-
-
-
-
-
19
20
21
G3
G2
F6
H4
G5
J3
J2
J4
27
28
29
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
F2
Pin name
(function after
reset)
FT
I/O
_ha
PF7
PF8
I/O
PF9
I/O
FT
_ha
FT
_ha
Notes
-
LQFP144
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
TIM17_CH1, FDCAN3_TX,
SPI5_SCK, SAI1_MCLK_B,
UART7_TX, SAI4_MCLK_B,
OCTOSPIM_P1_IO2,
TIM23_CH2, EVENTOUT
ADC3_INP3
-
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B, TIM13_CH1,
OCTOSPIM_P1_IO0,
TIM23_CH3, EVENTOUT
ADC3_INN3,
ADC3_INP7
-
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
SAI4_FS_B, TIM14_CH1,
OCTOSPIM_P1_IO1,
TIM23_CH4, EVENTOUT
ADC3_INP2
ADC3_INN2,
ADC3_INP6
-
-
22
G1
H3
K3
30
PF10
I/O
FT
_ha
-
TIM16_BKIN, SAI1_D3,
PSSI_D15,
OCTOSPIM_P1_CLK,
SAI4_D3,
DCMI_D11/PSSI_D11,
LCD_DE, EVENTOUT
C1
12
23
D1
H1
J1
31
PH0-OSC_IN
I/O
FT
-
EVENTOUT
OSC_IN
D1
13
24
E1
H2
K1
32
PH1-OSC_OUT
I/O
FT
-
EVENTOUT
OSC_OUT
E1
14
25
F1
G6
L1
33
NRST
I/O
RS
T
-
-
-
-
FMC_D12/FMC_AD12,
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI4_FS_B, FMC_A25,
OTG_HS_ULPI_STP,
LCD_G2, FMC_SDNWE,
LCD_R5, EVENTOUT
ADC123_INP10
-
TRACED0, SAI4_D1,
SAI1_D1, DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK,
OCTOSPIM_P1_IO4,
ETH_MDC, MDIOS_MDC,
LCD_G5, EVENTOUT
ADC123_INN10,
ADC123_INP11,
RTC_TAMP3,
WKUP6
F1
F2
15
16
66/262
26
27
H1
H2
J1
J2
L2
L3
34
35
PC0
PC1
I/O
FT
_ha
FT
I/O
_ha
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
H5
M1
-
PC2
I/O
FT
_a
-
E2
17
28
-
K2
N1
36
PC2_C
AN
A
TT
_a
-
-
ADC3_INN1,
ADC3_INP0
ADC12_INN12,
ADC12_INP13
LQFP176
H3
UFBGA169
-
UFBGA144
-
LQFP144
-
PWR_DEEPSLEEP,
DFSDM1_CKIN1,
OCTOSPIM_P1_IO5,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OCTOSPIM_P1_IO2,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
Additional
functions
ADC123_INN11,
ADC123_INP12
-
-
-
H4
J4
M2
-
PC3
I/O
FT
_a
-
PWR_SLEEP,
DFSDM1_DATIN1,
OCTOSPIM_P1_IO6,
SPI2_MOSI/I2S2_SDO,
OCTOSPIM_P1_IO0,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT
F3
18
29
-
K1
N2
37
PC3_C
AN
A
TT
_a
-
-
ADC3_INP1
-
-
30
-
-
-
-
VDD
S
-
-
-
-
G1
19
31
J1
J3
N3
38
VSSA
S
-
-
-
-
-
-
-
K1
-
L4
-
VREF-
S
-
-
-
-
-
20
32
L1
L2
M3
39
VREF+
S
-
-
-
-
H1
21
33
M1
L1
M4
40
VDDA
S
-
-
-
-
ADC1_INP16,
WKUP1
ADC12_INN1,
ADC12_INP0
G2
22
34
J2
J5
P1
41
PA0
I/O
FT
_ha
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
SPI6_NSS/I2S6_WS,
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI4_SD_B, ETH_MII_CRS,
FMC_A19, EVENTOUT
-
-
-
-
K3
R3
-
PA0_C
AN
A
TT
_a
-
-
DS13315 Rev 2
67/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
K4
P2
42
PA1
I/O
FT
_ha
-
-
-
-
-
L3
P3
-
PA1_C
AN
A
TT
_a
-
-
ADC12_INP1
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT, TIM15_CH1,
OCTOSPIM_P1_IO0,
USART2_TX(boot),
SAI4_SCK_B, ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP2
-
LPTIM1_IN2,
OCTOSPIM_P1_IO4,
SAI4_SCK_B, ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
ADC3_INP13
J2
24
36
L2
N1
R2
LQFP176
K2
UFBGA169
35
UFBGA144
23
LQFP144
H2
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT, TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX,
OCTOSPIM_P1_IO3,
SAI4_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII
_REF_CLK,
OCTOSPIM_P1_DQS,
LCD_R2, EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
43
FT
_ha
PA2
I/O
FT
I/O
_ha
Additional
functions
ADC1_INN16,
ADC1_INP17
-
-
-
-
N2
N4
-
PH2
-
-
-
-
-
-
44
VDD
S
-
-
-
-
-
-
-
-
-
-
45
VSS
S
-
-
-
-
-
-
-
-
M3
R4
-
PH3
I/O
FT
_ha
-
OCTOSPIM_P1_IO5,
SAI4_MCLK_B,
ETH_MII_COL, FMC_SDNE0,
LCD_R1, EVENTOUT
ADC3_INN13,
ADC3_INP14
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
PSSI_D14, LCD_G4,
EVENTOUT
ADC3_INN14,
ADC3_INP15
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
ADC3_INN15,
ADC3_INP16
-
-
-
-
-
P4
-
PH4
I/O
FT
_fa
-
-
-
-
-
R5
-
PH5
I/O
FT
_fh
a
68/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
N3
N5
46
PA3
I/O
FT
_ha
-
-
26
38
-
-
-
47
VSS
S
-
-
-
-
-
27
39
-
-
-
48
VDD
S
-
-
-
-
-
D1PWREN, TIM5_ETR,
SPI1_NSS(boot)/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
SPI6_NSS/I2S6_WS,
FMC_D8/FMC_AD8,
DCMI_HSYNC/PSSI_DE,
LCD_VSYNC, EVENTOUT
ADC12_INP18,
DAC1_OUT1
-
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK(boot)/I2S1_CK,
SPI6_SCK/I2S6_CK,
OTG_HS_ULPI_CK,
FMC_D9/FMC_AD9,
PSSI_D14, LCD_R4,
EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO(boot)/I2S1_SDI,
OCTOSPIM_P1_IO3,
SPI6_MISO/I2S6_SDI,
TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK/PSSI_PDCK,
LCD_G2, EVENTOUT
ADC12_INP3
G3
H3
J3
28
29
30
40
41
42
J3
K3
L3
H6
L4
K5
P5
P6
R7
LQFP176
M2
UFBGA169
37
UFBGA144
25
LQFP144
K2
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
I2S6_MCK,
OCTOSPIM_P1_IO2,
USART2_RX(boot), LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL,
OCTOSPIM_P1_CLK,
LCD_B5, EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
49
50
51
PA4
PA5
PA6
I/O
I/O
I/O
TT
_ha
TT
_ha
FT
_ha
DS13315 Rev 2
Additional
functions
ADC12_INP15
69/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
G4
H4
J4
K4
31
32
33
34
35
70/262
44
45
46
47
M3
J4
K4
L4
M4
J6
K6
N5
M5
L5
N6
R6
M7
R8
M8
52
53
54
55
56
PA7
PC4
PC5
PB0
PB1
I/O
I/O
I/O
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
43
Pin name
(function after
reset)
TT
_ha
TT
_ha
TT
_ha
TT
I/O
_ha
I/O
FT
_ha
DS13315 Rev 2
Notes
K3
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI(boot)/I2S1_SDO,
SPI6_MOSI/I2S6_SDO,
TIM14_CH1,
OCTOSPIM_P1_IO2,
ETH_MII_RX_DV/ETH_RMII_
CRS_DV, FMC_SDNWE,
LCD_VSYNC, EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
-
PWR_DEEPSLEEP,
FMC_A22, DFSDM1_CKIN2,
I2S1_MCK, SPDIFRX1_IN3,
SDMMC2_CKIN,
ETH_MII_RXD0/ETH_RMII_R
XD0, FMC_SDNE0, LCD_R7,
EVENTOUT
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
-
PWR_SLEEP, SAI4_D3,
SAI1_D3, DFSDM1_DATIN2,
PSSI_D15, SPDIFRX1_IN4,
OCTOSPIM_P1_DQS,
ETH_MII_RXD1/ETH_RMII_R
XD1, FMC_SDCKE0,
COMP1_OUT, LCD_DE,
EVENTOUT
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
OCTOSPIM_P1_IO1,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OCTOSPIM_P1_IO0,
DFSDM1_DATIN1, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_INP5,
COMP1_INM
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
36
J5
L6
P7
57
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
48
Pin name
(function after
reset)
FT
_ha
Notes
G5
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
RTC_OUT, SAI4_D1,
SAI1_D1, DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
OCTOSPIM_P1_CLK,
OCTOSPIM_P1_DQS,
ETH_TX_ER, TIM23_ETR,
EVENTOUT
COMP1_INP
ADC1_INP2
PB2
I/O
-
SPI5_MOSI,
OCTOSPIM_P1_NCLK,
SAI4_SD_B, FMC_NRAS,
DCMI_D12/PSSI_D12,
TIM24_CH1, EVENTOUT
-
-
49
M5
M6
N7
58
PF11
FT
I/O
_ha
-
-
50
L5
N6
P11
59
PF12
I/O
FT
_ha
-
OCTOSPIM_P2_DQS,
FMC_A6, TIM24_CH2,
EVENTOUT
ADC1_INN2,
ADC1_INP6
-
-
51
-
-
-
-
VSS
S
-
-
-
-
-
-
52
-
-
-
-
VDD
S
-
-
-
-
-
-
53
K5
G7
N11
60
PF13
I/O
FT
_ha
-
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
TIM24_CH3, EVENTOUT
ADC2_INP2
-
-
54
M6
H7
R10
61
PF14
I/O
FT
_fh
a
-
DFSDM1_CKIN6, I2C4_SCL,
FMC_A8, TIM24_CH4,
EVENTOUT
ADC2_INN2,
ADC2_INP6
-
-
55
L6
J7
N10
62
PF15
I/O
FT
_fh
-
I2C4_SDA, FMC_A9,
EVENTOUT
-
-
-
56
K6
K7
P8
63
PG0
I/O
FT
_h
-
OCTOSPIM_P2_IO4,
UART9_RX, FMC_A10,
EVENTOUT
-
-
-
-
-
-
-
64
VSS
S
-
-
-
-
-
-
-
-
-
-
65
VDD
S
-
-
-
-
-
-
57
J6
L7
N9
66
PG1
I/O
TT
_h
-
OCTOSPIM_P2_IO5,
UART9_TX, FMC_A11,
EVENTOUT
OPAMP2_VINM
-
TIM1_ETR, DFSDM1_DATIN2,
UART7_RX,
OCTOSPIM_P1_IO4,
FMC_D4/FMC_AD4,
EVENTOUT
OPAMP2_VOUT,
COMP2_INM
H5
37
58
M7
G8
P9
67
PE7
I/O
TT
_ha
DS13315 Rev 2
71/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
38
L7
H8
N8
68
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
59
Pin name
(function after
reset)
PE8
TT
I/O
_ha
TT
I/O
_ha
Notes
J5
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH1N,
DFSDM1_CKIN2, UART7_TX,
OCTOSPIM_P1_IO5,
FMC_D5/FMC_AD5,
COMP2_OUT, EVENTOUT
OPAMP2_VINM
-
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
OCTOSPIM_P1_IO6,
FMC_D6/FMC_AD6,
EVENTOUT
OPAMP2_VINP,
COMP2_INP
K5
39
60
K7
J8
R11
69
PE9
-
-
61
-
-
-
70
VSS
S
-
-
-
-
-
-
62
-
-
-
71
VDD
S
-
-
-
-
-
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
OCTOSPIM_P1_IO7,
FMC_D7/FMC_AD7,
EVENTOUT
COMP2_INM
-
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS(boot), SAI4_SD_B,
OCTOSPIM_P1_NCS,
FMC_D8/FMC_AD8, LCD_G3,
EVENTOUT
COMP2_INP
-
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK(boot),
SAI4_SCK_B,
FMC_D9/FMC_AD9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
-
-
G6
H6
J6
40
41
42
63
64
65
J7
H8
J8
M8
N8
L8
R9
R12
P12
72
73
74
PE10
PE11
PE12
I/O
I/O
I/O
FT
_ha
FT
_ha
FT
_h
K6
43
66
K8
K8
P13
75
PE13
I/O
FT
_h
-
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO(boot),
SAI4_FS_B,
FMC_D10/FMC_AD10,
COMP2_OUT, LCD_DE,
EVENTOUT
G7
44
67
L8
J9
M12
76
PE14
I/O
FT
_h
-
TIM1_CH4, SPI4_MOSI(boot),
SAI4_MCLK_B,
FMC_D11/FMC_AD11,
LCD_CLK, EVENTOUT
72/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
68
M8
N9
P14
77
J7
46
69
M9
K7
47
70
M10
F8
48
71
H7
-
49
-
-
-
-
-
-
-
50
72
-
-
-
-
-
L9
N12
78
PE15
I/O
PB10
I/O
Notes
LQFP144
45
I/O structure
LQFP100
H7
Pin name
(function after
reset)
Pin type
TFBGA100
Pin Number
Alternate functions
Additional
functions
FT
_h
-
TIM1_BKIN, USART10_CK,
FMC_D12/FMC_AD12,
TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
-
-
TIM2_CH3, LPTIM2_IN1,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX(boot),
OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
-
-
FT
_fh
P10
79
PB11
I/O
FT
_f
-
TIM2_CH4, LPTIM2_ETR,
I2C2_SDA, DFSDM1_CKIN7,
USART3_RX(boot),
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMII_T
X_EN, LCD_G5, EVENTOUT
N10 R13
80
VCAP
S
-
-
-
-
81
VSS
S
-
-
-
-
82
VDDLDO
S
-
-
-
-
-
VDD
S
-
-
-
-
I/O
FT
_h
-
TIM12_CH1, I2C2_SMBA,
SPI5_SCK, ETH_MII_RXD2,
FMC_SDNE1,
DCMI_D8/PSSI_D8,
EVENTOUT
-
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9/PSSI_D9,
EVENTOUT
-
-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC/PSSI_DE,
LCD_R2, EVENTOUT
-
-
TIM12_CH2, I2C3_SMBA,
FMC_D17,
DCMI_D0/PSSI_D0, LCD_R3,
EVENTOUT
-
M9
-
-
M10 R14
-
-
-
P15
-
PH6
-
-
-
-
-
M11
-
PH7
I/O
FT
_fh
-
-
-
-
-
N13
-
PH8
I/O
FT
_fh
I/O
FT
_h
-
-
-
-
-
M14
-
PH9
DS13315 Rev 2
73/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
-
-
K9
N14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K8
J8
51
52
74/262
73
74
Additional
functions
FT
_h
-
TIM5_CH1, I2C4_SMBA,
FMC_D18,
DCMI_D1/PSSI_D1, LCD_R4,
EVENTOUT
-
-
TIM5_CH2, I2C4_SCL,
FMC_D19,
DCMI_D2/PSSI_D2, LCD_R5,
EVENTOUT
-
-
PH11
I/O
-
83
VSS
S
-
-
-
-
-
84
VDD
S
-
-
-
-
-
PH12
I/O
FT
_fh
-
TIM5_CH3, I2C4_SDA,
FMC_D20,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
-
-
TIM1_BKIN,
OCTOSPIM_P1_NCLK,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK, FDCAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TX
D0, OCTOSPIM_P1_IO0,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
-
-
TIM1_CH1N, LPTIM2_OUT,
OCTOSPIM_P1_IO2,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TX
D1, SDMMC1_D0,
DCMI_D2/PSSI_D2,
UART5_TX, EVENTOUT
-
L10 M13
K10 N15
L11
I/O
Alternate functions
FT
_fh
M11 N12 M15
M12
PH10
Notes
LQFP144
-
I/O structure
LQFP100
-
Pin name
(function after
reset)
Pin type
TFBGA100
Pin Number
L15
85
86
PB12
PB13
I/O
I/O
FT
_h
FT
_h
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
G10
K9
53
54
55
76
77
L11
L12
L9
N13 K15
M13 K14
M12 L14
87
88
89
PB14
PB15
PD8
I/O
I/O
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
75
Pin name
(function after
reset)
FT
_h
FT
_h
Notes
H10
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_DE,
UART4_RTS/UART4_DE,
SDMMC2_D0,
FMC_D10/FMC_AD10,
LCD_CLK, EVENTOUT
-
-
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS, SDMMC2_D1,
FMC_D11/FMC_AD11,
LCD_G7, EVENTOUT
-
-
DFSDM1_CKIN3,
USART3_TX(boot),
SPDIFRX1_IN2,
FMC_D13/FMC_AD13,
EVENTOUT
-
-
I/O
FT
_h
-
DFSDM1_DATIN3,
USART3_RX(boot),
FMC_D14/FMC_AD14,
EVENTOUT
J9
56
78
K9
K11
K13
90
PD9
I/O
FT
_h
H9
57
79
J9
K12
L13
91
PD10
I/O
FT
_h
-
DFSDM1_CKOUT,
USART3_CK,
FMC_D15/FMC_AD15,
LCD_B3, EVENTOUT
-
-
-
-
-
-
-
92
VDD
S
-
-
-
-
-
-
-
-
-
-
93
VSS
S
-
-
-
-
-
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
OCTOSPIM_P1_IO0,
SAI4_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT
-
G9
58
80
H9
J10
J13
94
PD11
I/O
FT
_h
DS13315 Rev 2
75/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
59
L10
K13
J15
95
PD12
I/O
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
81
Pin name
(function after
reset)
FT
_fh
Notes
K10
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
FDCAN3_RX,
USART3_RTS/USART3_DE,
OCTOSPIM_P1_IO1,
SAI4_FS_A,
FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12,
EVENTOUT
-
-
J10
60
82
K10
J11
H15
96
PD13
I/O
FT
_fh
-
LPTIM1_OUT, TIM4_CH2,
I2C4_SDA, FDCAN3_TX,
OCTOSPIM_P1_IO3,
SAI4_SCK_A,
UART9_RTS/UART9_DE,
FMC_A18,
DCMI_D13/PSSI_D13,
EVENTOUT
-
-
83
-
-
-
-
VSS
S
-
-
-
-
-
-
84
-
-
-
-
VDD
S
-
-
-
-
I/O
FT
_h
-
TIM4_CH3, UART8_CTS,
UART9_RX,
FMC_D0/FMC_AD0,
EVENTOUT
-
-
TIM4_CH4,
UART8_RTS/UART8_DE,
UART9_TX,
FMC_D1/FMC_AD1,
EVENTOUT
-
H8
61
85
K11
J13
H14
97
PD14
G8
62
86
K12
J12
J12
98
PD15
I/O
FT
_h
-
-
-
-
-
-
99
VDD
S
-
-
-
-
-
-
-
-
-
-
100
VSS
S
-
-
-
-
-
-
-
-
-
-
101
PJ8
I/O
FT
-
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
-
-
-
-
-
-
102
PJ9
I/O
FT
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
-
-
-
-
-
-
103
PJ10
I/O
FT
-
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
76/262
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
Pin type
I/O structure
Notes
Pin Number
Alternate functions
-
-
-
-
-
-
104
PJ11
I/O
FT
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
-
-
-
-
-
105
VDD
S
-
-
-
-
-
-
-
-
-
-
106
VSS
S
-
-
-
-
-
-
-
-
-
-
107
PK0
I/O
FT
-
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
-
-
-
-
-
-
108
PK1
I/O
FT
-
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
-
-
-
-
-
-
109
PK2
I/O
FT
-
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
-
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, TIM24_ETR,
EVENTOUT
-
Pin name
(function after
reset)
Additional
functions
-
-
87
J12
H9
G15 110
PG2
I/O
FT
_h
-
-
88
J11
H10 H13 111
PG3
I/O
FT
_h
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, TIM23_ETR,
EVENTOUT
-
-
-
-
-
-
-
112
VSS
S
-
-
-
-
-
-
-
-
-
-
113
VDD
S
-
-
-
-
-
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
-
-
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
-
-
TIM17_BKIN,
OCTOSPIM_P1_NCS,
FMC_NE3,
DCMI_D12/PSSI_D12,
LCD_R7, EVENTOUT
-
-
-
89
J10
F8
G14 114
PG4
I/O
FT
_h
-
-
90
H12
H11
F15 115
PG5
I/O
FT
_h
I/O
FT
_h
-
-
91
H11
G9
F14 116
PG6
DS13315 Rev 2
77/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
-
-
-
-
G12 E15 120
VDD50USB
S
-
-
-
-
C11 G13 F13 121
VDD33USB
S
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT, SDMMC2_D6,
SDMMC1_D6,
DCMI_D0/PSSI_D0,
LCD_HSYNC, EVENTOUT
SWPMI_IO
-
DBTRGIO, TIM3_CH2,
TIM8_CH2, DFSDM1_DATIN3,
I2S3_MCK, USART6_RX,
SDMMC1_D123DIR,
FMC_NE1, SDMMC2_D7,
SWPMI_TX, SDMMC1_D7,
DCMI_D1/PSSI_D1, LCD_G6,
EVENTOUT
-
-
TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE,
FMC_INT, SWPMI_RX,
SDMMC1_D0,
DCMI_D2/PSSI_D2,
EVENTOUT
-
-
-
-
-
F6
-
95
65
78/262
98
LQFP176
S
-
F9
UFBGA176+25
VSS
94
97
-
-
-
64
-
FT
_h
-
E10
-
SAI1_MCLK_A, USART6_CK,
OCTOSPIM_P2_DQS,
FMC_INT,
DCMI_D13/PSSI_D13,
LCD_CLK, EVENTOUT
I/O
93
96
I/O
Additional
functions
PG8
-
63
PG7
Alternate functions
TIM8_ETR,
SPI6_NSS/I2S6_WS,
USART6_RTS/USART6_DE,
SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
F10
UFBGA169
UFBGA144
H10 G10 G13 117
FT
_h
Notes
92
I/O structure
-
Pin name
(function after
reset)
Pin type
-
LQFP144
LQFP100
TFBGA100
Pin Number
G11 G11 G12 118
G12
F12
F11
-
F9
-
119
E14 122
F10 D15 123
F12 D14 124
PC6
PC7
PC8
I/O
I/O
I/O
FT
_h
FT
_h
FT
_h
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
66
99
E11
F11
-
-
-
-
-
D9
C9
D10
C10
67
68
69
70
100 E12
101 D12
102 D11
103 C12
-
126
E12 B14 127
E11 D13 128
E10 C14 129
F13 C15 130
I/O structure
Pin type
LQFP176
E13 125
Pin name
(function after
reset)
Notes
E9
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
LQFP100
TFBGA100
Pin Number
Alternate functions
PC9
I/O
FT
_fh
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA(boot),
I2S_CKIN, I2C5_SDA,
UART5_CTS,
OCTOSPIM_P1_IO0,
LCD_G3, SWPMI_SUSPEND,
SDMMC1_D1,
DCMI_D3/PSSI_D3, LCD_B2,
EVENTOUT
VDD
S
-
-
-
-
-
MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL(boot),
I2C5_SCL, USART1_CK,
OTG_HS_SOF, UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
-
TIM1_CH2, LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
I2C5_SMBA,
USART1_TX(boot),
ETH_TX_ER,
DCMI_D0/PSSI_D0, LCD_R5,
EVENTOUT
OTG_HS_VBUS
-
TIM1_CH3, LPUART1_RX,
USART1_RX(boot),
OTG_HS_ID, MDIOS_MDIO,
LCD_B4, DCMI_D1/PSSI_D1,
LCD_B1, EVENTOUT
-
-
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, LCD_R4,
EVENTOUT
OTG_HS_DM
(boot)
PA8
PA9
PA10
PA11
I/O
I/O
I/O
I/O
FT
_fh
FT
_u
FT
_u
FT
_u
DS13315 Rev 2
Additional
functions
-
79/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
PA12
I/O
FT
_u
-
A10
72
105 A12
D11 B13 132
PA13(JTMS/
SWDIO)
I/O
FT
-
JTMS/SWDIO, EVENTOUT
-
E7
73
106
G9
D13 A14 133
VCAP
S
-
-
-
-
-
74
107
-
VSS
S
-
-
-
-
-
-
-
-
VDDLDO
S
-
-
-
-
-
75
108
-
136
VDD
S
-
-
-
-
-
-
-
-
-
PH13
I/O
FT
_h
-
TIM8_CH1N, UART4_TX,
FDCAN1_TX(boot), FMC_D21,
LCD_G2, EVENTOUT
-
-
TIM8_CH2N, UART4_RX,
FDCAN1_RX(boot),
FMC_D22,
DCMI_D4/PSSI_D4, LCD_G3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A9
76
109
A11
80/262
110
A10
-
B13 C13
-
77
134
D12 A13 135
-
A8
-
LQFP176
E13 B15 131
UFBGA169
104 B12
UFBGA144
71
LQFP144
B10
TIM1_ETR,
LPUART1_RTS/LPUART1_DE
, SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_DE,
SAI4_FS_B, FDCAN1_TX,
TIM1_BKIN2, LCD_R5,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
OTG_HS_DP
(boot)
-
PH14
I/O
FT
_h
D12
-
PH15
I/O
FT
_h
-
TIM8_CH3N, FMC_D23,
DCMI_D11/PSSI_D11,
LCD_G4, EVENTOUT
-
-
137
VSS
S
-
-
-
-
PA14(JTCK/
SWCLK)
I/O
FT
-
JTCK/SWCLK, EVENTOUT
-
-
JTDI, TIM2_CH1/TIM2_ETR,
CEC, SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS/I2S6_WS,
UART4_RTS/UART4_DE,
LCD_R3, UART7_TX,
LCD_B6, EVENTOUT
-
A13 B12
B12 A12 138
C11
Additional
functions
A11 139
PA15(JTDI)
I/O
FT
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
B8
C8
D8
E8
B7
78
79
80
81
82
83
112
B11
B10
113 C10
114
E10
A12 C12 140
B11
A11
C11 141
B11 142
D10 C10 143
115 D10 C10 A10 144
116
E9
E9
B10 145
PC10
PC11
PC12
PD0
PD1
PD2
I/O
I/O
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
111
Pin name
(function after
reset)
FT
_fh
FT
_fh
I/O
FT
_h
I/O
FT
_h
I/O
FT
_h
I/O
FT
_h
DS13315 Rev 2
Notes
B9
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
DFSDM1_CKIN5, I2C5_SDA,
SPI3_SCK(boot)/I2S3_CK,
USART3_TX, UART4_TX,
OCTOSPIM_P1_IO1, LCD_B1,
SWPMI_RX, SDMMC1_D2,
DCMI_D8/PSSI_D8, LCD_R2,
EVENTOUT
-
-
DFSDM1_DATIN5, I2C5_SCL,
SPI3_MISO(boot)/I2S3_SDI,
USART3_RX, UART4_RX,
OCTOSPIM_P1_NCS,
SDMMC1_D3,
DCMI_D4/PSSI_D4, LCD_B4,
EVENTOUT
-
-
TRACED3,
FMC_D6/FMC_AD6,
TIM15_CH1, I2C5_SMBA,
SPI6_SCK/I2S6_CK,
SPI3_MOSI(boot)/I2S3_SDO,
USART3_CK, UART5_TX,
SDMMC1_CK,
DCMI_D9/PSSI_D9, LCD_R6,
EVENTOUT
-
-
DFSDM1_CKIN6, UART4_RX,
FDCAN1_RX(boot),
UART9_CTS,
FMC_D2/FMC_AD2, LCD_B1,
EVENTOUT
-
-
DFSDM1_DATIN6,
UART4_TX,
FDCAN1_TX(boot),
FMC_D3/FMC_AD3,
EVENTOUT
-
-
TRACED2,
FMC_D7/FMC_AD7,
TIM3_ETR, TIM15_BKIN,
UART5_RX, LCD_B7,
SDMMC1_CMD,
DCMI_D11/PSSI_D11,
LCD_B2, EVENTOUT
-
81/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
D9
A9
146
PD3
I/O
FT
_h
-
D7
85
118
C9
C9
C9
147
PD4
I/O
FT
_h
-
USART2_RTS/USART2_DE,
OCTOSPIM_P1_IO4,
FMC_NOE, EVENTOUT
-
B6
86
119
B9
A9
B9
148
PD5
I/O
FT
_h
-
USART2_TX,
OCTOSPIM_P1_IO5,
FMC_NWE, EVENTOUT
-
-
-
120
-
-
-
-
VSS
S
-
-
-
-
-
-
121
-
-
-
-
VDD
S
-
-
-
-
-
SAI4_D1, SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
SAI4_SD_A,
OCTOSPIM_P1_IO6,
SDMMC2_CK, FMC_NWAIT,
DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
-
-
C6
87
122
A8
B9
D9
LQFP176
D9
UFBGA169
117
UFBGA144
84
LQFP144
C7
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
FMC_CLK,
DCMI_D5/PSSI_D5, LCD_G7,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
149
PD6
I/O
FT
_h
Additional
functions
-
D6
88
123
A9
D8
B8
150
PD7
I/O
FT
_h
-
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK, SPDIFRX1_IN1,
OCTOSPIM_P1_IO7,
SDMMC2_CMD, FMC_NE1,
EVENTOUT
-
-
-
-
-
-
151
VSS
S
-
-
-
-
-
-
-
-
-
-
152
VDD
S
-
-
-
-
-
FDCAN3_TX,
SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
OCTOSPIM_P1_IO6,
SAI4_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
-
-
82/262
-
124
E8
C8
A8
153
PG9
I/O
FT
_h
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
-
-
-
-
-
-
-
126
127
128
D8
C8
B8
D7
A8
B8
E8
D7
C8
A7
D8
B7
154
155
156
157
PG10
PG11
PG12
PG13
I/O
I/O
I/O
I/O
I/O structure
Pin type
LQFP176
UFBGA176+25
UFBGA169
UFBGA144
LQFP144
125
Pin name
(function after
reset)
FT
_h
FT
_h
FT
_h
FT
_h
Notes
-
LQFP100
TFBGA100
Pin Number
Alternate functions
Additional
functions
-
FDCAN3_RX,
OCTOSPIM_P2_IO6,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI4_SD_B,
SDMMC2_D1, FMC_NE3,
DCMI_D2/PSSI_D2, LCD_B2,
EVENTOUT
-
-
LPTIM1_IN2, USART10_RX,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
OCTOSPIM_P2_IO7,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_T
X_EN, DCMI_D3/PSSI_D3,
LCD_B3, EVENTOUT
-
-
LPTIM1_IN1,
OCTOSPIM_P2_NCS,
USART10_TX,
SPI6_MISO/I2S6_SDI,
USART6_RTS/USART6_DE,
SPDIFRX1_IN2, LCD_B4,
SDMMC2_D3,
ETH_MII_TXD1/ETH_RMII_TX
D1, FMC_NE4, TIM23_CH1,
LCD_B1, EVENTOUT
-
-
TRACED0, LPTIM1_OUT,
USART10_CTS/USART10_NS
S, SPI6_SCK/I2S6_CK,
USART6_CTS/USART6_NSS,
SDMMC2_D6,
ETH_MII_TXD0/ETH_RMII_TX
D0, FMC_A24, TIM23_CH2,
LCD_R0, EVENTOUT
-
-
-
-
-
129
C7
C7
C7
158
PG14
I/O
FT
_h
-
TRACED1, LPTIM1_ETR,
USART10_RTS/USART10_DE
, SPI6_MOSI/I2S6_SDO,
USART6_TX,
OCTOSPIM_P1_IO7,
SDMMC2_D7,
ETH_MII_TXD1/ETH_RMII_TX
D1, FMC_A25, TIM23_CH3,
LCD_B0, EVENTOUT
-
-
130
-
-
-
159
VSS
S
-
-
-
DS13315 Rev 2
83/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
131
-
-
-
160
-
A7
A6
C5
B5
-
89
90
91
92
84/262
132
133
134
135
136
B7
A7
A6
B6
C6
E7
F7
B6
C6
A5
D7
A6
B6
C6
A5
161
162
163
164
165
Notes
LQFP144
-
I/O structure
LQFP100
-
Alternate functions
Additional
functions
-
-
-
-
-
USART6_CTS/USART6_NSS,
OCTOSPIM_P2_DQS,
USART10_CK, FMC_NCAS,
DCMI_D13/PSSI_D13,
EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK/I2S6_CK,
SDMMC2_D2, CRS_SYNC,
UART7_RX, TIM24_ETR,
EVENTOUT
-
-
NJTRST, TIM16_BKIN,
TIM3_CH1,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO/I2S6_SDI,
SDMMC2_D3, UART7_TX,
EVENTOUT
-
-
TIM17_BKIN, TIM3_CH2,
LCD_B5, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI/I2S6_SDO,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT
-
-
TIM16_CH1N, TIM4_CH1,
I2C1_SCL(boot), CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX, FDCAN2_TX,
OCTOSPIM_P1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1,
DCMI_D5/PSSI_D5,
UART5_TX, EVENTOUT
-
Pin name
(function after
reset)
Pin type
TFBGA100
Pin Number
VDD
S
I/O
FT
_h
PG15
PB3(JTDO/TRAC
ESWO)
PB4(NJTRST)
PB5
PB6
I/O
I/O
I/O
I/O
FT
_h
FT
_h
FT
_h
FT
_fh
DS13315 Rev 2
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
D6
B5
166
PB7
I/O
FT
_fa
-
D5
94
138
D5
E6
C5
167
BOOT0
I
B
-
-
VPP
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4,
DCMI_D6/PSSI_D6, LCD_B6,
EVENTOUT
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA(boot),
SPI2_NSS/I2S2_WS,
I2C4_SDA, SDMMC1_CDIR,
UART4_TX, FDCAN1_TX,
SDMMC2_D5, I2C4_SMBA,
SDMMC1_D5,
DCMI_D7/PSSI_D7, LCD_B7,
EVENTOUT
-
-
B4
A4
95
96
139
140
C5
B5
B5
C5
A2
B3
LQFP176
D6
UFBGA169
137
UFBGA144
93
LQFP144
A5
TIM17_CH1N, TIM4_CH2,
I2C1_SDA, I2C4_SDA,
USART1_RX, LPUART1_RX,
DFSDM1_CKIN5, FMC_NL,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
LQFP100
Alternate functions
TFBGA100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFBGA176+25
Pin Number
168
169
PB8
I/O
PB9
FT
_fh
I/O
FT
_fh
-
LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
SAI4_MCLK_A, FMC_NBL0,
DCMI_D2/PSSI_D2, LCD_R0,
EVENTOUT
Additional
functions
PVD_IN
D4
97
141
A5
D5
B4
170
PE0
I/O
FT
_h
C4
98
142
A4
D4
C4
171
PE1
I/O
FT
_h
-
LPTIM1_IN2, UART8_TX,
FMC_NBL1,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
-
-
-
-
-
A4
A4
172
VCAP
S
-
-
-
-
-
99
-
-
-
-
173
VSS
S
-
-
-
-
F7
-
143
E5
C4
D4
174
PDR_ON
S
-
-
-
-
-
-
-
-
B4
A3
175
VDDLDO
S
-
-
-
-
-
-
-
-
VDD
S
-
-
-
-
-
100 144
DS13315 Rev 2
85/262
102
Pinouts, pin descriptions and alternate functions
STM32H730xB
Table 7. STM32H730xB pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
Pin type
I/O structure
Notes
Pin Number
Alternate functions
-
-
-
-
-
-
176
VDD
S
-
-
-
-
C2
-
-
D2
B3
A1
-
VSS
S
-
-
-
-
E6
-
-
E6
B7
A15
-
VSS
S
-
-
-
-
J1
-
-
E7
B10
C2
-
VSS
S
-
-
-
-
E4
-
-
G4
C12 D10
-
VSS
S
-
-
-
-
E5
-
-
G8
D2
D6
-
VSS
S
-
-
-
-
-
-
-
G10
G2
E1
-
VSS
S
-
-
-
-
-
-
-
H5
H12 F10
-
VSS
S
-
-
-
-
-
-
-
H6
L12
F12
-
VSS
S
-
-
-
-
-
-
-
-
M2
F6
-
VSS
S
-
-
-
-
-
-
-
-
M4
F7
-
VSS
S
-
-
-
-
-
-
-
-
M7
F8
-
VSS
S
-
-
-
-
-
-
-
-
M11
F9
-
VSS
S
-
-
-
-
-
-
-
-
-
G10
-
VSS
S
-
-
-
-
-
-
-
-
-
G6
-
VSS
S
-
-
-
-
-
-
-
-
-
G7
-
VSS
S
-
-
-
-
-
-
-
-
-
G8
-
VSS
S
-
-
-
-
-
-
-
-
-
G9
-
VSS
S
-
-
-
-
-
-
-
-
-
H10
-
VSS
S
-
-
-
-
-
-
-
-
-
H6
-
VSS
S
-
-
-
-
-
-
-
-
-
H7
-
VSS
S
-
-
-
-
-
-
-
-
-
H8
-
VSS
S
-
-
-
-
-
-
-
-
-
H9
-
VSS
S
-
-
-
-
-
-
-
-
-
J10
-
VSS
S
-
-
-
-
-
-
-
-
-
J14
-
VSS
S
-
-
-
-
-
-
-
-
-
J6
-
VSS
S
-
-
-
-
-
-
-
-
-
J7
-
VSS
S
-
-
-
-
-
-
-
-
-
J8
-
VSS
S
-
-
-
-
-
-
-
-
-
J9
-
VSS
S
-
-
-
-
-
-
-
-
-
K10
-
VSS
S
-
-
-
-
86/262
Pin name
(function after
reset)
DS13315 Rev 2
Additional
functions
STM32H730xB
Pinouts, pin descriptions and alternate functions
Table 7. STM32H730xB pin and ball descriptions (continued)
TFBGA100
LQFP100
LQFP144
UFBGA144
UFBGA169
UFBGA176+25
LQFP176
Pin type
I/O structure
Notes
Pin Number
Alternate functions
-
-
-
-
-
K12
-
VSS
S
-
-
-
-
-
-
-
-
-
K2
-
VSS
S
-
-
-
-
-
-
-
-
-
K6
-
VSS
S
-
-
-
-
-
-
-
-
-
K7
-
VSS
S
-
-
-
-
-
-
-
-
-
K8
-
VSS
S
-
-
-
-
-
-
-
-
-
K9
-
VSS
S
-
-
-
-
-
-
-
-
-
M10
-
VSS
S
-
-
-
-
-
-
-
-
-
M6
-
VSS
S
-
-
-
-
-
-
-
-
-
R1
-
VSS
S
-
-
-
-
-
-
-
-
-
R15
-
VSS
S
-
-
-
-
D2
-
-
D3
A3
D5
-
VDD
S
-
-
-
-
F5
-
-
F4
A6
D11
-
VDD
S
-
-
-
-
K1
-
-
F5
A7
E4
-
VDD
S
-
-
-
-
F4
-
-
F6
A10 E12
-
VDD
S
-
-
-
-
-
-
-
F7
C13
G4
-
VDD
S
-
-
-
-
-
-
-
F8
D1
H12
-
VDD
S
-
-
-
-
-
-
-
F9
G1
K4
-
VDD
S
-
-
-
-
-
-
-
F10
H13
L12
-
VDD
S
-
-
-
-
-
-
-
G5
L13
M5
-
VDD
S
-
-
-
-
-
-
-
G6
M1
M9
-
VDD
S
-
-
-
-
-
-
-
G7
N4
-
-
VDD
S
-
-
-
-
-
-
-
-
N7
-
-
VDD
S
-
-
-
-
-
-
-
-
N11
-
-
VDD
S
-
-
-
-
Pin name
(function after
reset)
DS13315 Rev 2
Additional
functions
87/262
102
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PA0
-
TIM2_
CH1/TIM
2_ETR
TIM5_
CH1
TIM8_
ETR
TIM15_
BKIN
SPI6_NSS
/I2S6_WS
-
USART2_
CTS/
USART2_
NSS
UART4_
TX
SDMMC2_
CMD
SAI4_SD_
B
ETH_MII_
CRS
PA1
-
TIM2_CH
2
TIM5_
CH2
LPTIM3_
OUT
TIM15_CH1
N
-
-
USART2_
RTS/
USART2_
DE
UART4_
RX
OCTOSPIM
_P1_IO3
SAI4_
MCLK_B
PA2
-
TIM2_CH
3
TIM5_
CH3
LPTIM4_
OUT
TIM15_CH1
-
OCTOSPI
M_P1_IO0
USART2_
TX
SAI4_
SCK_B
-
PA3
-
TIM2_CH
4
TIM5_
CH4
LPTIM5_
OUT
TIM15_CH2 I2S6_MCK
OCTOSPI
M_P1_IO2
USART2_
RX
-
PA4
D1PW
REN
-
TIM5_
ETR
-
-
SPI1_NSS SPI3_NSS/
/I2S1_WS
I2S3_WS
USART2_
CK
PA5
D2PW
REN
TIM2_CH
1/TIM2_
ETR
-
TIM8_
CH1N
-
SPI1_SCK
/I2S1_CK
-
PA6
-
TIM1_
BKIN
TIM3_C
H1
TIM8_
BKIN
-
SPI1_
MISO/I2S
1_SDI
PA7
-
TIM1_CH
1N
TIM3_
CH2
TIM8_CH
1N
-
PA8
MCO1
TIM1_CH
1
-
TIM8_
BKIN2
I2C3_SCL
Port
DS13315 Rev 2
Port A
AF2
AF3
AF4
AF5
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_A19
-
-
EVENT
OUT
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
OCTOSPI
M_P1_
DQS
-
LCD_R
2
EVENT
OUT
-
ETH_MDIO
MDIOS_
MDIO
-
LCD_R
1
EVENT
OUT
LCD_B2
OTG_HS_
ULPI_D0
ETH_MII_
COL
OCTOSPI
M_P1_
CLK
-
LCD_B
5
EVENT
OUT
SPI6_NS
S/I2S6_
WS
-
-
-
FMC_D8/
FMC_AD
8
DCMI_
HSYNC
/PSSI_
DE
LCD_V
SYNC
EVENT
OUT
-
SPI6_SC
K/I2S6_
CK
-
OTG_HS_
ULPI_CK
-
FMC_D9/
FMC_AD
9
PSSI_
D14
LCD_R
4
EVENT
OUT
OCTOSPI
M_P1_IO3
-
SPI6_MIS
O/I2S6_S
DI
TIM13_CH
1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_
BKIN_
COMP12
DCMI_
PIXCL
K/PSSI
_PDCK
LCD_G
2
EVENT
OUT
SPI1_
MOSI/I2S
1_SDO
-
-
SPI6_
MOSI/I2S
6_SDO
TIM14_CH
1
OCTOSPI
M_P1_IO2
ETH_MII_
RX_DV/ETH
_RMII_CRS
_DV
FMC_SD
NWE
-
LCD_V
SYNC
EVENT
OUT
-
I2C5_SCL
USART1_
CK
-
-
OTG_HS_
SOF
UART7_RX
TIM8_
BKIN2_
COMP12
LCD_B
3
LCD_R
6
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
88/262
Table 8. STM32H730xB pin alternate functions
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PA9
-
TIM1_CH
2
-
LPUART1
_TX
I2C3_
SMBA
SPI2_SCK
/I2S2_CK
PA10
-
TIM1_CH
3
-
LPUART1
_RX
-
-
PA11
-
TIM1_CH
4
-
LPUART1
_CTS
-
PA12
-
TIM1_
ETR
-
LPUART1
_RTS/
LPUART1
_DE
-
PA13
JTMS/
SWDI
O
-
-
-
-
-
PA14
JTCK/
SWCL
K
-
-
-
-
-
PA15
JTDI
TIM2_CH
1/TIM2_
ETR
-
-
CEC
DS13315 Rev 2
Port A
Port
AF2
AF3
AF4
AF5
AF13
AF14
AF15
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
I2C5_
SMBA
USART1_
TX
-
-
-
ETH_TX_ER
-
DCMI_
D0/
PSSI_
D0
LCD_R
5
EVENT
OUT
-
USART1_
RX
-
-
OTG_HS_
ID
MDIOS_
MDIO
LCD_B4
DCMI_
D1/
PSSI_
D1
LCD_B
1
EVENT
OUT
SPI2_NSS
UART4_RX
/I2S2_WS
USART1_
CTS/
USART1_
NSS
-
FDCAN1_
RX
-
-
-
-
LCD_R
4
EVENT
OUT
SPI2_SCK
UART4_TX
/I2S2_CK
USART1_
RTS/
USART1_
DE
SAI4_FS_
B
FDCAN1_
TX
-
-
TIM1_
BKIN2
-
LCD_R
5
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
SPI6_NS
S/I2S6_W
S
UART4_R
TS/UART
4_DE
LCD_R3
-
UART7_TX
-
-
LCD_B
6
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
SPI1_NSS SPI3_NSS/
/I2S1_WS
I2S3_WS
AF7
AF8
AF9
AF10
AF11
AF12
89/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PB0
-
TIM1_
CH2N
TIM3_
CH3
TIM8_
CH2N
OCTOSPIM
_P1_IO1
-
DFSDM1_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
PB1
-
TIM1_
CH3N
TIM3_
CH4
TIM8_CH
3N
OCTOSPIM
_P1_IO0
-
DFSDM1_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
PB2
RTC_
OUT
SAI4_D1
SAI1_D1
-
DFSDM1_
CKIN1
-
SAI1_SD_
A
SPI3_
MOSI/I2S
3_SDO
PB3
JTDO/
TRAC
ESWO
TIM2_CH
2
-
-
-
SPI1_SCK SPI3_SCK/
/I2S1_CK
I2S3_CK
PB4
NJT
RST
TIM16_
BKIN
TIM3_
CH1
-
-
SPI1_
MISO/I2S
1_SDI
PB5
-
TIM17_
BKIN
TIM3_
CH2
LCD_B5
I2C1_
SMBA
PB6
-
TIM16_
CH1N
TIM4_
CH1
-
PB7
-
TIM17_
CH1N
TIM4_
CH2
PB8
-
TIM16_
CH1
PB9
-
TIM17_
CH1
Port
DS13315 Rev 2
Port B
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
-
LCD_G
1
EVENT
OUT
ETH_MII_
RXD3
-
-
LCD_G
0
EVENT
OUT
OCTOSPI
M_P1_
DQS
ETH_TX_ER
-
TIM23_
ETR
-
EVENT
OUT
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
SAI4_SD_ OCTOSPIM
A
_P1_CLK
-
SPI6_
SCK/I2S6
_CK
SDMMC2_
D2
CRS_
SYNC
UART7_RX
-
-
TIM24_
ETR
EVENT
OUT
SPI3_
MISO/I2S3
_SDI
SPI2_
NSS/I2S2
_WS
SPI6_
MISO/I2S
6_SDI
SDMMC2_
D3
-
UART7_TX
-
-
-
EVENT
OUT
SPI1_
MOSI/I2S
1_SDO
I2C4_SMB
A
SPI3_
MOSI/I2S
3_SDO
SPI6_
MOSI/I2S
6_SDO
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_SD
CKE1
DCMI_
D10/
PSSI_
D10
UART5
_RX
EVENT
OUT
I2C1_SCL
CEC
I2C4_SCL
USART1_
TX
LPUART1
_TX
FDCAN2_
TX
OCTOSPI
M_P1_
NCS
DFSDM1_
DATIN5
FMC_SD
NE1
DCMI_
D5/
PSSI_
D5
UART5
_TX
EVENT
OUT
-
I2C1_SDA
-
I2C4_SDA
USART1_
RX
LPUART1
_RX
-
-
DFSDM1_
CKIN5
FMC_NL
DCMI_
VSYNC
/PSSI_
RDY
-
EVENT
OUT
TIM4_
CH3
DFSDM1_
CKIN7
I2C1_SCL
-
I2C4_SCL
SDMMC1
_CKIN
UART4_
RX
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1
_D4
DCMI_
D6/
PSSI_
D6
LCD_B
6
EVENT
OUT
TIM4_
CH4
DFSDM1_
DATIN7
I2C1_SDA
SPI2_NSS
/I2S2_WS
I2C4_SDA
SDMMC1
_CDIR
UART4_
TX
FDCAN1_
TX
SDMMC2_
D5
I2C4_SMBA
SDMMC1
_D5
DCMI_
D7/
PSSI_
D7
LCD_B
7
EVENT
OUT
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
90/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PB10
-
TIM2_
CH3
-
LPTIM2_
IN1
I2C2_SCL
PB11
-
TIM2_
CH4
-
LPTIM2_
ETR
PB12
-
TIM1_
BKIN
-
OCTOSPI
M_P1_
NCLK
PB13
-
TIM1_
CH1N
-
LPTIM2_
OUT
PB14
-
TIM1_
CH2N
TIM12_
CH1
TIM8_
CH2N
PB15
RTC_
REFIN
TIM1_
CH3N
TIM12_
CH2
TIM8_
CH3N
Port
DS13315 Rev 2
P
r
o
t
B
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
SPI2_SCK
/I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
-
OCTOSPIM
_P1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
-
-
LCD_G
4
EVENT
OUT
I2C2_SDA
-
DFSDM1_
CKIN7
USART3_
RX
-
-
OTG_HS_
ULPI_D4
ETH_MII_TX
_EN/ETH_
RMII_TX_
EN
-
-
LCD_G
5
EVENT
OUT
I2C2_
SMBA
SPI2_NSS
/I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
-
FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_TX OCTOSPI
D0/ETH_
M_P1_IO
RMII_TXD0
0
TIM1_
BKIN_
COMP
12
UART5
_RX
EVENT
OUT
OCTOSPIM SPI2_SCK
_P1_IO2
/I2S2_CK
DFSDM1_
CKIN1
USART3_
CTS/
USART3_
NSS
-
FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_TX
D1/ETH_
RMII_TXD1
SDMMC1
_D0
DCMI_
D2/P
SSI_D2
UART5
_TX
EVENT
OUT
USART1_
TX
SPI2_
MISO/
I2S2_SDI
DFSDM1_
DATIN2
USART3_
RTS/
USART3_
DE
UART4_
RTS
/UART4_
DE
SDMMC2_
D0
-
-
FMC_D1
0/FMC_
AD10
-
LCD_
CLK
EVENT
OUT
USART1_
RX
SPI2_MO
SI/I2S2_
SDO
DFSDM1_
CKIN2
-
UART4_
CTS
SDMMC2_
D1
-
-
FMC_D11
/FMC_AD
11
-
LCD_G
7
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
91/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF0
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PC0
-
FMC_D1
2/FMC_
AD12
-
DFSDM1_
CKIN0
PC1
TRA
CED0
SAI4_D1
-
PC2
PWR_
DEEP
SLEEP
-
PC3
PWR_
SLEEP
PC4
Port
DS13315 Rev 2
Prot C
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
DFSDM1_
DATIN4
-
SAI4_FS_
B
FMC_A25
OTG_HS_
ULPI_STP
LCD_G2
FMC_
SDNWE
-
LCD_R
5
EVENT
OUT
DFSDM1_ DFSDM1_C
DATIN0
KIN4
SPI2_MO
SI/I2S2_S
DO
SAI1_SD_
A
-
SAI4_SD_
A
SDMMC2_
CK
OCTOSPI
M_P1_IO4
ETH_MDC
MDIOS_
MDC
-
LCD_G
5
EVENT
OUT
-
DFSDM1_ OCTOSPIM
CKIN1
_P1_IO5
SPI2_MIS
O/I2S2_S
DI
DFSDM1_
CKOUT
-
-
OCTOSPIM
_P1_IO2
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SD
NE0
-
-
EVENT
OUT
-
-
DFSDM1_ OCTOSPIM
DATIN1
_P1_IO6
SPI2_MO
SI/I2S2_S
DO
-
-
-
OCTOSPIM
_P1_IO0
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SD
CKE0
-
-
EVENT
OUT
PWR_
DEEP
SLEEP
FMC_A2
2
-
DFSDM1_
CKIN2
-
I2S1_MCK
-
-
-
SPDIFRX1
_IN3
SDMMC2_
CKIN
ETH_MII_
RXD0/ETH_
RMII_RXD0
FMC_SD
NE0
-
LCD_R
7
EVENT
OUT
PC5
PWR_
SLEEP
SAI4_D3
SAI1_D3
DFSDM1_
DATIN2
PSSI_D15
-
-
-
-
SPDIFRX1
_IN4
OCTOSPI
M_P1_
DQS
ETH_MII_
RXD1/ETH_
RMII_RXD1
FMC_SD
CKE0
COMP
1_OUT
LCD_
DE
EVENT
OUT
PC6
-
-
TIM3_
CH1
TIM8_CH
1
DFSDM1_
CKIN3
I2S2_MCK
-
USART6_
TX
SDMMC1
_D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1
_D6
DCMI_
D0/
PSSI_
D0
LCD_
HSYNC
EVENT
OUT
PC7
DBTR
GIO
-
TIM3_
CH2
TIM8_CH
2
DFSDM1_
DATIN3
-
I2S3_MCK
USART6_
RX
SDMMC1
_D123DIR
FMC_NE1
SDMMC2_
D7
SWPMI_TX
SDMMC1
_D7
DCMI_
D1/PS
SI_D1
LCD_G
6
EVENT
OUT
PC8
TRA
CED1
-
TIM3_
CH3
TIM8_CH
3
-
-
-
USART6_
CK
UART5_
RTS/
UART5_
DE
FMC_NE2/
FMC_NCE
FMC_INT
SWPMI_RX
SDMMC1
_D0
DCMI_
D2/PS
SI_D2
-
EVENT
OUT
PC9
MCO2
-
TIM3_C
H4
TIM8_CH
4
I2C3_SDA
I2S_CKIN
I2C5_SDA
-
UART5_
CTS
OCTOSPIM
_P1_IO0
LCD_G3
SWPMI_SU
SPEND
SDMMC1
_D1
DCMI_
D3/PS
SI_D3
LCD_B
2
EVENT
OUT
STM32H730xB
-
-
Pinouts, pin descriptions and alternate functions
92/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PC10
-
-
-
DFSDM1_
CKIN5
I2C5_SDA
PC11
-
-
-
DFSDM1_
DATIN5
PC12
TRAC
ED3
FMC_D6/
FMC_AD
6
TIM15_
CH1
PC13
-
-
PC14
-
PC15
-
DS13315 Rev 2
Prot C
Port
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_
TX
OCTOSPIM
_P1_IO1
LCD_B1
SWPMI_RX
SDMMC1
_D2
DCMI_
D8/
PSSI_
D8
LCD_R
2
EVENT
OUT
I2C5_SCL
-
SPI3_
MISO/I2S3
_SDI
USART3_
RX
UART4_
RX
OCTOSPIM
_P1_NCS
-
-
SDMMC1
_D3
DCMI_
D4/
PSSI_
D4
LCD_B
4
EVENT
OUT
-
I2C5_SMB
A
SPI6_SCK
/I2S6_CK
SPI3_
MOSI/I2S3
_SDO
USART3_
CK
UART5_
TX
-
-
-
SDMMC1
_CK
DCMI_
D9/
PSSI_
D9
LCD_R
6
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
93/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PD0
-
-
-
DFSDM1_
CKIN6
-
-
-
-
UART4_
RX
FDCAN1_
RX
-
UART9_CTS
PD1
-
-
-
DFSDM1_
DATIN6
-
-
-
-
UART4_
TX
FDCAN1_
TX
-
PD2
TRAC
ED2
FMC_D7/
FMC_AD
7
TIM3_
ETR
-
TIM15_
BKIN
-
-
-
UART5_
RX
LCD_B7
PD3
-
-
-
DFSDM1_
CKOUT
-
SPI2_SCK
/I2S2_CK
-
USART2_
CTS/
USART2_
NSS
-
PD4
-
-
-
-
-
-
-
USART2_
RTS/
USART2_
DE
PD5
-
-
-
-
-
-
-
PD6
-
SAI4_D1
SAI1_D1
DFSDM1_
CKIN4
DFSDM1_
DATIN1
SPI3_
MOSI/I2S
3_SDO
PD7
-
-
-
DFSDM1_
DATIN4
-
PD8
-
-
-
DFSDM1_
CKIN3
PD9
-
-
-
DFSDM1_
DATIN3
Port
DS13315 Rev 2
Port D
AF2
AF3
AF4
AF5
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_D2/
FMC_AD
2
-
LCD_B
1
EVENT
OUT
-
FMC_D3/
FMC_AD
3
-
-
EVENT
OUT
-
-
SDMMC1
_CMD
DCMI_
D11/
PSSI_
D11
LCD_B
2
EVENT
OUT
-
-
-
FMC_
CLK
DCMI_
D5/
PSSI_
D5
LCD_G
7
EVENT
OUT
-
-
OCTOSPI
M_P1_IO4
-
FMC_
NOE
-
-
EVENT
OUT
USART2_
TX
-
-
OCTOSPI
M_P1_IO5
-
FMC_NW
E
-
-
EVENT
OUT
SAI1_SD_
A
USART2_
RX
SAI4_SD_
A
-
OCTOSPI
M_P1_IO6
SDMMC2_
CK
FMC_
NWAIT
DCMI_
D10/
PSSI_
D10
LCD_B
2
EVENT
OUT
SPI1_
MOSI/I2S
1_SDO
DFSDM1_
CKIN1
USART2_
CK
-
SPDIFRX1
_IN1
OCTOSPI
M_P1_IO7
SDMMC2_
CMD
FMC_NE
1
-
-
EVENT
OUT
-
-
-
USART3_
TX
-
SPDIFRX1
_IN2
-
-
FMC_D1
3/FMC_A
D13
-
-
EVENT
OUT
-
-
-
USART3_
RX
-
-
-
-
FMC_D1
4/FMC_
AD14
-
-
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
94/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PD10
-
-
-
DFSDM1_
CKOUT
-
-
-
USART3_
CK
-
-
-
-
PD11
-
-
-
LPTIM2_I
N2
I2C4_SMB
A
-
-
USART3_
CTS/USA
RT3_NSS
-
OCTOSPIM
_P1_IO0
SAI4_SD_
A
PD12
-
LPTIM1_
IN1
TIM4_C
H1
LPTIM2_I
N1
I2C4_SCL
FDCAN3_
RX
-
USART3_
RTS/USA
RT3_DE
-
OCTOSPIM
_P1_IO1
SAI4_FS_
A
PD13
-
LPTIM1_
OUT
TIM4_C
H2
-
I2C4_SDA
FDCAN3_
TX
-
-
-
OCTOSPIM
_P1_IO3
SAI4_SCK
_A
PD14
-
-
TIM4_C
H3
-
-
-
-
-
UART8_C
TS
-
-
UART9_RX
FMC_D0/
FMC_AD
0
PD15
-
-
TIM4_C
H4
-
-
-
-
-
UART8_R
TS/UART
8_DE
-
-
UART9_TX
FMC_D1/
FMC_AD
1
DS13315 Rev 2
Prot D
Port
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_D1
5/FMC_A
D15
-
LCD_B
3
EVENT
OUT
-
FMC_A16
/FMC_CL
E
-
-
EVENT
OUT
-
FMC_A17 DCMI_
/FMC_AL D12/PS
E
SI_D12
-
EVENT
OUT
DCMI_
UART9_RTS
FMC_A18 D13/PS
/UART9_DE
SI_D13
-
EVENT
OUT
-
-
EVENT
OUT
-
-
EVENT
OUT
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
95/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
PE0
-
LPTIM1_
ETR
TIM4_E
TR
-
LPTIM2_ET
R
-
-
-
UART8_R
X
-
SAI4_MCL
K_A
-
PE1
-
LPTIM1_I
N2
-
-
-
-
-
-
UART8_T
X
-
-
-
PE2
TRAC
ECLK
-
SAI1_C
K1
-
USART10_
RX
SPI4_SCK
SAI1_MCL
K_A
-
SAI4_MC
LK_A
OCTOSPIM
_P1_IO2
SAI4_CK1
PE3
TRAC
ED0
-
-
-
TIM15_BKI
N
-
SAI1_SD_
B
-
SAI4_SD_
B
-
PE4
TRAC
ED1
-
SAI1_D2
DFSDM1_ TIM15_CH1
SPI4_NSS SAI1_FS_A
DATIN3
N
-
SAI4_FS_
A
PE5
TRAC
ED2
-
SAI1_C
K2
DFSDM1_
TIM15_CH1
CKIN3
PE6
TRAC
ED3
PE7
-
TIM1_ET
R
PE8
-
PE9
PE10
Port
DS13315 Rev 2
Port E
AF2
TIM1_BKI
SAI1_D1
N2
AF3
AF4
AF5
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_NB
L0
DCMI_
D2/PS
SI_D2
LCD_R
0
EVENT
OUT
FMC_NB
L1
DCMI_
D3/PS
SI_D3
LCD_R
6
EVENT
OUT
ETH_MII_TX
FMC_A23
D3
-
-
EVENT
OUT
-
USART10_T
X
FMC_A19
-
-
EVENT
OUT
-
SAI4_D2
-
FMC_A20
DCMI_
D4/PS
SI_D4
LCD_B
0
EVENT
OUT
-
FMC_A21
DCMI_
D6/PS
SI_D6
LCD_G
0
EVENT
OUT
TIM1_BKIN2
FMC_A22
_COMP12
DCMI_
D7/PS
SI_D7
LCD_G
1
EVENT
OUT
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
SPI4_MIS
O
SAI1_SCK
_A
-
SAI4_SC
K_A
-
SAI4_CK2
-
TIM15_CH2
SPI4_MO
SI
SAI1_SD_
A
-
SAI4_SD_
A
SAI4_D1
SAI4_MCL
K_B
-
DFSDM1_
DATIN2
-
-
-
UART7_R
X
-
-
OCTOSPI
M_P1_IO4
-
FMC_D4/
FMC_AD
4
-
-
EVENT
OUT
TIM1_CH
1N
-
DFSDM1_
CKIN2
-
-
-
UART7_T
X
-
-
OCTOSPI
M_P1_IO5
-
FMC_D5/
FMC_AD
5
COMP
2_OUT
-
EVENT
OUT
-
TIM1_CH
1
-
DFSDM1_
CKOUT
-
-
-
UART7_R
TS/UART
7_DE
-
-
OCTOSPI
M_P1_IO6
-
FMC_D6/
FMC_AD
6
-
-
EVENT
OUT
-
TIM1_CH
2N
-
DFSDM1_
DATIN4
-
-
-
UART7_C
TS
-
-
OCTOSPI
M_P1_IO7
-
FMC_D7/
FMC_AD
7
-
-
EVENT
OUT
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
96/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PE11
-
TIM1_CH
2
-
DFSDM1_
CKIN4
-
SPI4_NSS
-
-
-
-
SAI4_SD_
B
OCTOSPIM
_P1_NCS
PE12
-
TIM1_CH
3N
-
DFSDM1_
DATIN5
-
SPI4_SCK
-
-
-
-
SAI4_SCK
_B
PE13
-
TIM1_CH
3
-
DFSDM1_
CKIN5
-
SPI4_MIS
O
-
-
-
-
PE14
-
TIM1_CH
4
-
-
-
SPI4_MO
SI
-
-
-
PE15
-
TIM1_BKI
N
-
-
-
-
-
-
-
DS13315 Rev 2
Prot E
Port
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_D8/
FMC_AD
8
-
LCD_G
3
EVENT
OUT
-
FMC_D9/
FMC_AD
9
COMP
1_OUT
LCD_B
4
EVENT
OUT
SAI4_FS_
B
-
FMC_D1
0/FMC_A
D10
COMP
2_OUT
LCD_D
E
EVENT
OUT
-
SAI4_MCL
K_B
-
FMC_D11
/FMC_AD
11
-
LCD_C
LK
EVENT
OUT
-
-
USART10_C
K
FMC_D1
2/FMC_A
D12
TIM1_B
KIN_C
OMP12
LCD_R
7
EVENT
OUT
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
97/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PF0
-
-
-
-
I2C2_SDA
-
I2C5_SDA
-
-
OCTOSPIM
_P2_IO0
-
-
PF1
-
-
-
-
I2C2_SCL
-
I2C5_SCL
-
-
OCTOSPIM
_P2_IO1
-
PF2
-
-
-
-
I2C2_SMB
A
-
I2C5_SMB
A
-
-
OCTOSPIM
_P2_IO2
PF3
-
-
-
-
-
-
-
-
-
PF4
-
-
-
-
-
-
-
-
PF5
-
-
-
-
-
-
-
-
PF6
-
TIM16_C
H1
FDCAN3
_RX
-
-
SPI5_NSS
SAI1_SD_
B
PF7
-
TIM17_C
H1
FDCAN3
_TX
-
-
SPI5_SCK
PF8
-
TIM16_C
H1N
-
-
-
SPI5_MIS
O
Port
DS13315 Rev 2
Port F
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_A0
TIM23_
CH1
-
EVENT
OUT
-
FMC_A1
TIM23_
CH2
-
EVENT
OUT
-
-
FMC_A2
TIM23_
CH3
-
EVENT
OUT
OCTOSPIM
_P2_IO3
-
-
FMC_A3
TIM23_
CH4
-
EVENT
OUT
-
OCTOSPIM
_P2_CLK
-
-
FMC_A4
-
-
EVENT
OUT
-
OCTOSPIM
_P2_NCLK
-
-
FMC_A5
-
-
EVENT
OUT
UART7_R SAI4_SD_
X
B
-
OCTOSPI
M_P1_IO3
-
-
TIM23_
CH1
-
EVENT
OUT
SAI1_MCL
K_B
UART7_T
X
SAI4_MC
LK_B
-
OCTOSPI
M_P1_IO2
-
-
TIM23_
CH2
-
EVENT
OUT
SAI1_SCK
_B
UART7_R
TS/UART
7_DE
SAI4_SC
K_B
TIM13_CH
1
OCTOSPI
M_P1_IO0
-
-
TIM23_
CH3
-
EVENT
OUT
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
98/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
AF2
AF3
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PF9
-
TIM17_C
H1N
-
-
PF10
-
TIM16_B
KIN
SAI1_D3
PF11
-
-
PF12
-
PF13
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF14
AF15
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
SPI5_MO
SI
SAI1_FS_B
UART7_C
TS
SAI4_FS_
B
TIM14_CH
1
OCTOSPI
M_P1_IO1
-
-
TIM23_
CH4
-
EVENT
OUT
-
PSSI_D15
-
-
-
-
OCTOSPIM
_P1_CLK
SAI4_D3
-
-
DCMI_
D11/PS
SI_D11
LCD_D
E
EVENT
OUT
-
-
-
SPI5_MO
SI
-
-
-
OCTOSPIM
_P1_NCLK
SAI4_SD_
B
-
FMC_NR
AS
DCMI_
TIM24_
D12/PS
CH1
SI_D12
EVENT
OUT
-
-
-
-
-
-
-
-
OCTOSPIM
_P2_DQS
-
-
FMC_A6
-
TIM24_
CH2
EVENT
OUT
-
-
-
DFSDM1_
DATIN6
I2C4_SMB
A
-
-
-
-
-
-
-
FMC_A7
-
TIM24_
CH3
EVENT
OUT
PF14
-
-
-
DFSDM1_
CKIN6
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
TIM24_
CH4
EVENT
OUT
PF15
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
OCTOSPIM
_P2_IO4
-
UART9_RX
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
OCTOSPIM
_P2_IO5
-
UART9_TX
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
TIM8_BKI
N
-
-
-
-
-
-
-
TIM8_BKIN_
FMC_A12
COMP12
-
TIM24_
ETR
EVENT
OUT
PG3
-
-
-
TIM8_BKI
N2
-
-
-
-
-
-
-
TIM23_
TIM8_BKIN2
FMC_A13
ETR
_COMP12
-
EVENT
OUT
DS13315 Rev 2
Prot F
Port
Port G-
AF13
99/262
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PG4
-
TIM1_BKI
N2
-
-
-
-
-
-
-
-
-
TIM1_BKIN2
_COMP12
PG5
-
TIM1_ET
R
-
-
-
-
-
-
-
-
-
PG6
-
TIM17_B
KIN
-
-
-
-
-
-
-
-
PG7
-
-
-
-
-
-
SAI1_MCL
K_A
USART6_
CK
-
PG8
-
-
-
TIM8_ET
R
-
SPI6_NSS
/I2S6_WS
-
USART6_
RTS/USA
RT6_DE
PG9
-
-
FDCAN3
_TX
-
-
SPI1_MIS
O/I2S1_S
DI
-
PG10
-
-
FDCAN3
_RX
OCTOSPI
M_P2_IO
6
-
SPI1_NSS
/I2S1_WS
PG11
-
LPTIM1_I
N2
-
-
USART10_
RX
PG12
-
LPTIM1_I
N1
-
OCTOSPI
M_P2_NC
S
PG13
TRAC
ED0
LPTIM1_
OUT
-
-
Port
DS13315 Rev 2
Prot G
AF2
AF3
AF4
AF5
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
FMC_A14
/FMC_BA
0
-
-
EVENT
OUT
-
FMC_A15
/FMC_BA
1
-
-
EVENT
OUT
OCTOSPI
M_P1_NC
S
-
FMC_NE
3
DCMI_
D12/PS
SI_D12
LCD_R
7
EVENT
OUT
OCTOSPIM
_P2_DQS
-
-
FMC_INT
DCMI_
D13/PS
SI_D13
LCD_C
LK
EVENT
OUT
SPDIFRX
1_IN3
-
-
ETH_PPS_
OUT
FMC_SD
CLK
-
LCD_G
7
EVENT
OUT
USART6_
RX
SPDIFRX
1_IN4
OCTOSPIM
_P1_IO6
SAI4_FS_
B
SDMMC2_D
0
FMC_NE
2/FMC_N
CE
DCMI_
VSYNC
/PSSI_
RDY
-
EVENT
OUT
-
-
-
LCD_G3
SAI4_SD_
B
SDMMC2_D
1
FMC_NE
3
DCMI_
D2/PS
SI_D2
LCD_B
2
EVENT
OUT
SPI1_SCK
/I2S1_CK
-
-
SPDIFRX
1_IN1
OCTOSPIM
_P2_IO7
SDMMC2_
D2
ETH_MII_TX
_EN/ETH_R
MII_TX_EN
-
DCMI_
D3/PS
SI_D3
LCD_B
3
EVENT
OUT
USART10_
TX
SPI6_MIS
O/I2S6_S
DI
-
USART6_
RTS/USA
RT6_DE
SPDIFRX
1_IN2
LCD_B4
SDMMC2_
D3
ETH_MII_TX
D1/ETH_RM
II_TXD1
FMC_NE
4
TIM23_
CH1
LCD_B
1
EVENT
OUT
USART10_
CTS/USAR
T10_NSS
SPI6_SCK
/I2S6_CK
-
USART6_
CTS/USA
RT6_NSS
-
-
SDMMC2_
D6
ETH_MII_TX
TIM23_
D0/ETH_RM FMC_A24
CH2
II_TXD0
LCD_R
0
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
STM32H730xB
AF0
Pinouts, pin descriptions and alternate functions
100/262
Table 8. STM32H730xB pin alternate functions (continued)
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PG14
TRAC
ED1
LPTIM1_
ETR
-
-
USART10_
RTS/USAR
T10_DE
SPI6_MO
SI/I2S6_S
DO
-
USART6_
TX
-
OCTOSPIM
_P1_IO7
SDMMC2_
D7
PG15
-
-
-
-
-
-
-
USART6_
CTS/USA
RT6_NSS
-
OCTOSPIM
_P2_DQS
-
USART10_C
K
FMC_NC
AS
PH0
-
-
-
-
-
-
-
-
-
-
-
-
PH1
-
-
-
-
-
-
-
-
-
-
-
PH2
-
LPTIM1_I
N2
-
-
-
-
-
-
-
OCTOSPIM
_P1_IO4
PH3
-
-
-
-
-
-
-
-
-
PH4
-
-
-
-
I2C2_SCL
-
-
-
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
PH6
-
-
TIM12_
CH1
-
I2C2_SMB
A
SPI5_SCK
PH7
-
-
-
-
I2C3_SCL
PH8
-
-
TIM5_E
TR
-
PH9
-
-
TIM12_
CH2
-
Prot G
Port
DS13315 Rev 2
Port H
AF2
AF3
AF4
AF5
101/262
AF13
AF14
AF15
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
ETH_MII_TX
TIM23_
D1/ETH_RM FMC_A25
CH3
II_TXD1
LCD_B
0
EVENT
OUT
DCMI_
D13/PS
SI_D13
-
EVENT
OUT
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
SAI4_SCK
_B
ETH_MII_C
RS
FMC_SD
CKE0
-
LCD_R
0
EVENT
OUT
OCTOSPIM
_P1_IO5
SAI4_MCL
K_B
ETH_MII_C
OL
FMC_SD
NE0
-
LCD_R
1
EVENT
OUT
-
LCD_G5
OTG_HS_
ULPI_NXT
-
-
PSSI_
D14
LCD_G
4
EVENT
OUT
-
-
-
-
-
FMC_SD
NWE
-
-
EVENT
OUT
-
-
-
-
-
ETH_MII_R
XD2
FMC_SD
NE1
DCMI_
D8/PS
SI_D8
-
EVENT
OUT
SPI5_MIS
O
-
-
-
-
-
ETH_MII_R
XD3
FMC_SD
CKE1
DCMI_
D9/PS
SI_D9
-
EVENT
OUT
I2C3_SDA
-
-
-
-
-
-
-
FMC_D1
6
DCMI_
HSYNC
/PSSI_
DE
LCD_R
2
EVENT
OUT
I2C3_SMB
A
-
-
-
-
-
-
-
FMC_D1
7
DCMI_
D0/PS
SI_D0
LCD_R
3
EVENT
OUT
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
Pinouts, pin descriptions and alternate functions
AF0
STM32H730xB
Table 8. STM32H730xB pin alternate functions (continued)
AF0
AF1
SYS
FMC/
LPTIM1/
SAI4/
TIM16/17
/TIM1x/
TIM2x
PH10
-
-
TIM5_C
H1
-
I2C4_SMB
A
-
-
-
-
-
-
PH11
-
-
TIM5_C
H2
-
I2C4_SCL
-
-
-
-
-
PH12
-
-
TIM5_C
H3
-
I2C4_SDA
-
-
-
-
PH13
-
-
-
TIM8_CH
1N
-
-
-
-
UART4_T
X
PH14
-
-
-
TIM8_CH
2N
-
-
-
-
PH15
-
-
-
TIM8_CH
3N
-
-
-
-
-
PJ8
-
TIM1_CH
3N
-
TIM8_CH
1
-
-
-
-
PJ9
-
TIM1_CH
3
-
TIM8_CH
1N
-
-
-
PJ10
-
TIM1_CH
2N
-
TIM8_CH
2
-
SPI5_MO
SI
PJ11
-
TIM1_CH
2
-
TIM8_CH
2N
-
SPI5_MIS
O
Port J
DS13315 Rev 2
Prot H
Port
AF2
AF3
AF4
AF5
DFSDM1/ CEC/DCMI/
LCD/
PSSI/
CEC/
FDCAN3
LPTIM2/3/ DFSDM1/
FDCAN3/
/PDM_
4/5/
I2C1/2/3/4/5 SPI1/I2S1/
SAI1/
LPUART1
/LPTIM2/
SPI2/I2S2/
TIM3/4/5
/OCTO
OCTOSPIM SPI3/I2S3/
/12/15
SPIM_P1/ _P1/TIM15/
SPI4/5/6
2/TIM8
USART1/10
AF6
AF13
AF14
AF15
DFSDM1/
CRS/FMC/
SDMMC1/ LPUART1 FDCAN1/2/
ETH/I2C4/ FMC/LCD
LCD/OCT
SPI2/I2S2
/SAI4/
FMC/LCD/
LCD/MDIOS /MDIOS/
OSPIM_P1
/SPI3/I2S SDMMC1/ OCTOSPIM
/OCTOSPIM OCTOSPI
/OTG1_FS/
3/SPI6/
SPDIFRX _P1/2/SAI4
_P1/SDMMC
M_P1/
OTG1_HS/
UART7
1/SPI6/
/SDMMC2/
2/SWPMI1/ SDMMC1
SAI4/
/USART1/ UART4/5/ SPDIFRX1/
TIM1x/TIM8/
/TIM1x/
SDMMC2/
2/3/6
8
TIM13/14
UART7/9/
TIM8
TIM8
USART10
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
LCD/
TIM24/
UART5
SYS
-
FMC_D1
8
DCMI_
D1/PS
SI_D1
LCD_R
4
EVENT
OUT
-
-
FMC_D1
9
DCMI_
D2/PS
SI_D2
LCD_R
5
EVENT
OUT
-
-
-
FMC_D2
0
DCMI_
D3/PS
SI_D3
LCD_R
6
EVENT
OUT
FDCAN1_T
X
-
-
FMC_D2
1
-
LCD_G
2
EVENT
OUT
UART4_R FDCAN1_R
X
X
-
-
FMC_D2
2
DCMI_
D4/PS
SI_D4
LCD_G
3
EVENT
OUT
-
-
-
FMC_D2
3
DCMI_
D11/PS
SI_D11
LCD_G
4
EVENT
OUT
UART8_T
X
-
-
-
-
-
LCD_G
1
EVENT
OUT
-
UART8_R
X
-
-
-
-
-
LCD_G
2
EVENT
OUT
-
-
-
-
-
-
-
-
LCD_G
3
EVENT
OUT
-
-
-
-
-
-
-
-
LCD_G
4
EVENT
OUT
DFSDM1/
I2C4/5/
OCTO
SPIM_P1/
SAI1/SPI3/
I2S3/
UART4
AF7
AF8
AF9
AF10
AF11
AF12
Pinouts, pin descriptions and alternate functions
102/262
Table 8. STM32H730xB pin alternate functions (continued)
STM32H730xB
STM32H730xB
6
6.1
Electrical characteristics
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
DS13315 Rev 2
MS19010V2
103/262
233
Electrical characteristics
6.1.6
STM32H730xB
Power supply scheme
Figure 13. Power supply scheme
VDDSMPS
VLXSMPS
Step
Down
Converter
VFBSMPS
VSSSMPS
VCAP
Level shifter
IOs
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
Power
switch
VSS
Power
switch
Core domain (VCORE)
LDO
voltage
regulator
VDDLDO
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
Flash
VSS
VDD domain
HSI, CSI,
HSI48,
HSE, PLLs
VDD
VBAT
charging
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power
switch
Power switch
LSI, LSE, RTC,
Wakeup logic,
backup
IO
logic registers, Reset
BKUP
IOs
VSS
VDD50USB
Backup
RAM
VSS
USB regulator
VSS
VDD33USB
USB
FS IOs
VDDA
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
OPAMP,
Comparator
VSSA
MSv63814V4
1. Refer to application note AN5419 “Getting started with STM32H723/733, STM32H725/735 and
STM32H730 Value Line hardware development“ for the possible power scheme and connected capacitors.
104/262
DS13315 Rev 2
STM32H730xB
6.1.7
Electrical characteristics
Current consumption measurement
Figure 14. Current consumption measurement scheme
SMPS ON
LDO ON
IDD_VBAT
IDD_VBAT
VBAT
VBAT
IDD
IDD
VDD
VDD
VDDSMPS
VDDLDO
VDDA
VDDA
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics,
Table 10: Current characteristics, and Table 11: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 9. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
VDDX - VSS(1)
External main supply voltage (including VDD,
VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT)
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS−0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
Variations between different VDDX power
pins of the same domain
-
50
mV
Variations between all the different ground
pins
-
50
mV
VIN(2)
Input voltage on any other pins
|∆VDDX|
|VSSx-VSS|
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
DS13315 Rev 2
105/262
233
Electrical characteristics
STM32H730xB
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 10. Current characteristics
Symbols
Ratings
Max
ΣIVDD
(1)
Total current into sum of all VDD power lines (source)
620
ΣIVSS
Total current out of sum of all VSS ground lines (sink)(1)
620
IVDD
IVSS
IIO
ΣI(PIN)
IINJ(PIN)
(3)(4)
ΣIINJ(PIN)
Maximum current into each VDD power pin
(source)(1)
100
(1)
100
Maximum current out of each VSS ground pin (sink)
Output current sunk by any I/O and control pin, except Px_C
20
Output current sunk by Px_C pins
1
Total output current sunk by sum of all I/Os and control
pins(2)
Unit
mA
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN