STM32H735IGK6

STM32H735xG Arm® Cortex®-M7 32-bit 550 MHz MCU, 1 MB Flash, 564 KB RAM, Ethernet, USB, 3x FD-CAN, Graphics, 2x1 6-bit ADCs, crypto/hash Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) Core • 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions VFQFPN 68 (8x8 mm) FBGA FBGA TFBGA100 (8x8 mm) UFBGA 169 (7 x 7 mm) UFBGA 176+25 (10 x 10 mm) Memories • 1 Mbyte of embedded Flash memory with ECC • SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes) • Flexible external memory controller with up to 24-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • 2 x Octo-SPI interface with XiP and on-the-fly decryption support WLCSP 115 0.35 mm pitch Clock, reset and supply management • 1.62 V to 3.6 V application supply and I/O • POR, PDR, PVD and BOR • Dedicated USB power • Embedded DCDC and LDO regulator (*)VFQFPN68 variant is DCDC only • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI • 2 x SD/SDIO/MMC interface • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE • Bootloader with security services support (SFI and SB-SFU) Low power • Sleep, Stop and Standby modes Graphics • Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load • LCD-TFT controller supporting up to XGA resolution December 2021 • VBAT supply for RTC, 32×32-bit backup registers Analog • 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to 22 channels and 7.2 MSPS in doubleinterleaved mode DS13312 Rev 3 1/284 www.st.com STM32H735xG • 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels • 2x SAI (serial audio interface) • 2 x comparators • 8- to 14-bit camera interface • 2 x operational amplifier GBW = 8 MHz • 1× FD/TT-CAN and 2x FD-CAN • 16-bit parallel slave synchronous interface • 2× 12-bit D/A converters • SPDIF-IN interface Digital filters for sigma delta modulator (DFSDM) • HDMI-CEC • 8 channels/4 filters • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY 4 DMA controllers to offload the CPU • 1 × MDMA with linked list support • Ethernet MAC interface with DMA controller • SWPMI single-wire protocol master I/F • 2 × dual-port DMAs with FIFO • 1 × basic DMA with request router capabilities • MDIO slave interface Mathematical acceleration 24 timers • Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • CORDIC for trigonometric functions acceleration • FMAC: Filter mathematical accelerator Digital temperature sensor • 2x watchdogs, 1x SysTick timer Cryptographic/HASH acceleration Debug mode • AES 128, 192, 256, TDES, HASH (MD5, SHA1, SHA-2), HMAC • SWD and JTAG interfaces • 2-Kbyte embedded trace buffer • 2x OTFDEC AES-128 in CTR mode for OctoSPI memory encryption/decryption Up to 128 I/O ports with interrupt capability True random number generator CRC calculation unit Up to 35 communication interfaces RTC with sub-second accuracy and hardware calendar • Up to 5 × I2C FM+ interfaces (SMBus/PMBus™) • Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART • Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode) ROP, PC-ROP, tamper detection, secure firmware upgrade support 96-bit unique ID All packages are ECOPACK2 compliant Table 1. Device summary Reference STM32H735xG 2/284 Part number STM32H735AG, STM32H735IG, STM32H735RG, STM32H735VG, STM32H735ZG DS13312 Rev 3 STM32H735xG Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.4 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.7 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.8 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.8.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.10 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.10.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.10.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.11 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.13 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.14 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.15 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34 3.16 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34 3.17 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34 3.18 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DS13312 Rev 3 3/284 8 Contents 4/284 STM32H735xG 3.19 Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.20 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.24 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.25 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.26 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.27 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39 3.28 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.29 PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.30 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.31 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.32 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 42 3.33 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.34 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.34.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.34.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.34.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 47 3.34.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.35 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 48 3.36 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.37 Universal synchronous/asynchronous receiver transmitter (USART) . . . 49 3.38 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 50 3.39 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 51 3.40 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.41 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.42 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 52 3.43 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 53 3.44 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 53 3.45 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 53 DS13312 Rev 3 STM32H735xG Contents 3.46 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 54 3.47 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 54 3.48 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.49 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 57 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 125 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 126 6.3.6 Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . 127 6.3.7 Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . 128 6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Typical SMPS efficiency versus load current and temperature . . . . . . . . . . . . .136 I/O system current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 On-chip peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 6.3.9 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 147 High-speed external user clock generated from an external source . . . . . . . . .147 Low-speed external user clock generated from an external source . . . . . . . . . .148 High-speed external clock generated from a crystal/ceramic resonator. . . . . . .149 DS13312 Rev 3 5/284 8 Contents STM32H735xG Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .150 6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 151 48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .151 64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .152 4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .153 Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .159 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .159 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 160 Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .161 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .167 Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .169 Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .170 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Synchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 SDRAM waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 6.3.20 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.22 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 6/284 6.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 6.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 218 6.3.26 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 219 6.3.27 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 220 DS13312 Rev 3 STM32H735xG Contents 6.3.28 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.3.30 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.3.31 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.32 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 225 6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 227 6.3.34 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 228 6.3.35 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 229 6.3.36 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.3.37 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.3.38 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .243 USB OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.1 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Device marking for VFQFPN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 7.3 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 7.4 WLCSP115 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Device marking for WLSCP115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Device marking for UFBGA169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 7.7 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Device marking for LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 DS13312 Rev 3 7/284 8 Contents STM32H735xG 7.8 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Device marking for UFBGA176+25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 7.9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 8/284 DS13312 Rev 3 STM32H735xG List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32H735xG features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32H735xG pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STM32H735xG pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . 120 VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 122 SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 122 Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . 123 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Typical and maximum current consumption in Run mode, code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 132 Typical consumption in Run mode and corresponding performance versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 133 Typical and maximum current consumption in System Stop mode . . . . . . . . . . . . . . . . . 134 Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 135 Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 135 Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DS13312 Rev 3 9/284 11 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. 10/284 STM32H735xG PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 156 PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 157 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 165 Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 166 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 173 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 173 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 175 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 175 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 177 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 178 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 184 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 196 Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 DS13312 Rev 3 STM32H735xG Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. List of tables VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . 243 Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V . . . . . . . . . . . . . . 244 USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 247 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 248 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 249 Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 VFQFPN68 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . 261 WLCSP115 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 WLCSP115 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 270 LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 UFBGA176+25 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 UFBGA176+25 - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . 277 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 DS13312 Rev 3 11/284 11 List of figures STM32H735xG List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 12/284 STM32H735xG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32H735xG bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VFQFPN68 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 WLCSP115 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 136 Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . . 136 Typical SMPS efficiency (%) vs load current (A) in Stop and DStop modes at TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 137 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 172 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 174 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 183 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 188 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 189 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Typical connection diagram when using the ADC with FT/TT pins DS13312 Rev 3 STM32H735xG List of figures featuring analog switch function205 Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 206 Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 206 Figure 50. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 51. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 52. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 53. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 54. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 55. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 56. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 57. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 58. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 59. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 60. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Figure 61. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Figure 62. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Figure 63. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Figure 64. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Figure 65. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Figure 66. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Figure 67. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Figure 68. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Figure 69. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Figure 70. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Figure 71. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Figure 72. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Figure 73. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Figure 74. VFQFPN68 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Figure 75. VFQFPN68 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 76. VFQFPN68 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Figure 77. LQFP100- Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Figure 78. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 79. TFBGA100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Figure 80. TFBGA100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Figure 81. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Figure 82. WLCSP115 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Figure 83. WLCSP115 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Figure 84. WLCSP115 marking example (package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Figure 85. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Figure 86. LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Figure 87. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Figure 88. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Figure 89. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Figure 90. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Figure 91. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Figure 92. LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Figure 93. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Figure 94. UFBGA176+25 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Figure 95. UFBGA176+25 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Figure 96. UFBGA176+25 marking example (package top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . 278 DS13312 Rev 3 13/284 13 Introduction 1 STM32H735xG Introduction This document provides information on STM32H735xG microcontrollers, such as description, functional overview, pin assignment and definition, packaging, and ordering information. This document should be read in conjunction with the STM32H735xG reference manual (RM0468), available from the STMicroelectronics website www.st.com. For information on the device errata with respect to the datasheet and reference manual, refer to the STM32H735xG errata sheet (ES0491) available on the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical Reference Manual, available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 14/284 DS13312 Rev 3 STM32H735xG 2 Description Description STM32H735xG devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H735xG devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H735xG devices incorporate high-speed embedded memories with 1 Mbyte of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections). The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell, and a HASH processor. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. • Standard peripherals – Five I2Cs – Five USARTs, five UARTs and one LPUART – Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization (note that the five USARTs also provide SPI slave capability). – Two SAI serial audio interfaces – One SPDIFRX interface with four inputs – One SWPMI (Single Wire Protocol Master Interface) – Management Data Input/Output (MDIO) slaves – Two SDMMC interfaces – A USB OTG high-speed interface with full-speed capability (with the ULPI) – Two FDCANs plus one TT-FDCAN interface – An Ethernet interface – Chrom-ART Accelerator – HDMI-CEC DS13312 Rev 3 15/284 56 Description STM32H735xG • Advanced peripherals including – A flexible memory control (FMC) interface – Two Octo-SPI memory interfaces with on-the-fly decryption (OTFDEC) – A camera interface for CMOS sensors – An LCD-TFT display controller Refer to Table 2: STM32H735xG features and peripheral counts for the list of peripherals available on each part number. To reduce the power consumption the STM32H735xG include an optional step-down converter that can be used either for internal or external supply, or both. STM32H735xG devices operate in the –40 to +125 °C ambient temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.8.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. Dedicated supply inputs for USB are available to allow a greater power supply choice. A comprehensive set of power-saving modes allows the design of low-power applications. STM32H735xG devices are offered in several packages ranging from 68 to 176 pins/balls. The set of included peripherals changes with the device chosen. These features make STM32H735xG microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances • Mobile applications, Internet of Things • Wearable devices: smart watches. Figure 1 shows the device block diagram. 16/284 DS13312 Rev 3 STM32H735xG Description Figure 1. STM32H735xG block diagram MII / RMII To APB1-2 peripherals MDIO as AF AHB1 D-TCM 64KB I-TCM 64KB AHBP LCD-TFT FIFO WWDG PSSI TIM4 CH[4;1], ETR as AF 32b TIM5 CH[4;1], ETR as AF 32b TIM23 CH[4;1], ETR as AF 32b TIM24 CH[4;1], ETR as AF 16b TIM12 CH[2;1] as AF 16b TIM13 CH1 as AF 16b TIM14 CH1 as AF DAP TIM8/PWM 16b HSEM 16b CRC ADC3 AHB4 (275MHz) TIM1/PWM RX, TX, CK, CTS, RTS, DE as A UART4 RX, TX, CTS, RTS, DE as AF UART5 RX, TX, CTS, RTS, DE as AF UART7 RX, TX, CTS, RTS, DE as AF UART8 RX, TX, CTS, RTS, DE as AF SPI2/I2S2 MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF I2C2/SMBUS I2C3/SMBUS SCL, SDA, SMBA as AF I2C5/SMBUS SCL, SDA, SMBA as AF MDIOS MDC, MDIO as AF TT-FDCAN1 FDCAN2 FDCAN3 16 KB SRAM 4 KB BKP RAM SPDIFRX1 HDMI-CEC DAC LPTIM5 16b LPTIM4 16b OUT as AF LPTIM3 16b I2C4 MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6 RX, TX, CK, CTS, RTS as AF LPUART1 IN1, IN2, ETR, OUT as AF LPTIM2 16b AHB/APB VREF VINM, VINP, VOUT as AF Voltage regulator 3.3 to 1.2V @VDD HSI RC HSI HSI48 HSI48 RC CSI RC CSI LSI LSI RC VDD VSS VCAP, VDDLDO VDDSMPS, VSSSMPS, VLXSMPS, VFBSMPS VBAT @VSW IWDG IN1, IN2, ETR, OUT as AF OPAMP2 XTAL 32 kHz Temperature sensor CEC as AF OUT1, OUT2 as AF VINM, VINP, VOUT as AF VCORE BBgen + POWER MNGT SYSCFG EXTI WKUP IN[1:4] as AF OPAMP1 LS OUT as AF TX, RX, RXFD_MODE, TXFD_MODE as AF TX, RX, RXFD_MODE, TXFD_MODE as AF TX, RX, RXFD_MODE, TXFD_MODE as AF @VDD PWRCTRL SAI4 COMP1&2 OUT as AF LPTIM1 16b RCC Reset & control RTC Backup registers LS GPIO PORTJ,K AHB4 (275MHz) GPIO PORTA.. H APB4 MHz (max) APB4 138138 MHz (max) PA..H[15:0] PJ,PK[11:0] SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF USBCR FIFO USART1 RX, TX, CK, CTS, RTS, DE as A USART3 SPI3/I2S3 RAM I/F 32-bit AHB BUS-MATRIX USART2 I2C1/SMBUS APB1 138 MHz (max) BDMA AHB4 USART6 DMA Mux2 10 KB SRAM AHB4 AHB4 UART9 AHB4_MEMD3 (275MHz) TIM15 AHB4 TIM16 USART10 SCL, SDA, SMBA as AF 16b A P B 10 MHz 3 TIM17 RX, TX, CK, CTS, RTS, DE as AF SD_[A;B], SCK_[A;B], FS_[A;B], MCLK_[A;B], D[3:1], CK[2:1] as AF COMPx_INP, COMPx_INM, COMPx_OUT as AF SWPMI CH[4;1], ETR as AF SPI5 RX, TX, CK, CTS, RTS, DE as AF Up to 17 analog inputs Some common to ADC1 and 2 16b CH[4;1], ETR as AF TIM3 FIFO SAI1 SPI4 CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2 as AF TIM7 TIM2 16b DFSDM SPI1/I2S1 CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2 as AF 16b 32b AHB/APB MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF RX, TX, CK, CTS, RTS, DE as AF TIM6 AHB4 DCMI MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS, DE as AF FMAC AHB2 (275MHz) Up to 20 analog inputs Most are common to ADC1 & 2 ADC2 AHB/APB Digital filter 2 compl. chan.(TIM15_CH1[1:2]N), 2 chan. (TIM_CH15[1:2], BKIN as AF ADC1 CORDIC OCTOSPI2 signals AXI/AHB34 (275MHz) APB2 138 MHz (max) 1 compl. chan.(TIM17_CH1N), 1 chan. (TIM17_CH1, BKIN as AF 1 compl. chan.(TIM16_CH1N), 1 chan. (TIM16_CH1, BKIN as AF 3DES/AES SRAM1 SRAM2 16 KB 16 KB AHB4 MOSI, MISO, SCK, NSS as AF HASH AHB3 FIFO SDMMC1 APB4 138MHz (max) SD_[A;B], SCK_[A;B], FS_[A;B], MCLK_[A;B], D[3:1], CK[2:1] as AF RNG DLYBOS1-2 AHB/APB DLYBSD2 CKOUT, DATIN[7:0], CKIN[7:0] AHB1 (275MHz) OCTOSPI1 signals DLYBSD1 HSYNC, VSYNC, PIXCLK, D[13:0] PDCK, DE, RDY, D[15:0] DMA Mux1 FMC_signals AHB2 (275MHz) OTFDEC1 OTFDEC2 APB3 (138MHz) FIFO 64-bit AXI BUS-MATRIX 16 Streams FIFO CHROM-ART (DMA2D) D[7:0], D123DIR, D0DIR, CMD, CKas AF DMA/ FIFO FIFO 32-bit AHB BUS-MATRIX FMC AHBS LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK DMA/ FIFO 8 Stream 8 Stream FIFOs FIFOs 1 MB FLASH D-Cache 32KB MDMA PHY ETHER SDMMC2 OTG_HS MAC AXIM ETM I-Cache 32KB DMA2 (275MHz) AXI/AHB12 (275MHz) OCTOSPIM TRACECLK TRACED[3:0] 128 KB AXI SRAM Arm CPU JTAG/SW Cortex-M7 550 MHz OCTOSPI1 NJTRST, JTDI, JTCK/SWCLK JTDO/SWDIO, JTDO DMA1 Shared AXI I-TCM 192KB OCTOSPI2 D-TCM 64KB D[7:0],DP, DM, STP, D123DIR, NXT,ULPI:CK D0DIR, , D[7:0], DIR, CMD, CKas AF ID, VBUS AWU OSC32_IN OSC32_OUT TS, TAMP1, TAMP3, OUT, REFIN @VDD XTAL OSC 4- 48 MHz PLL1+PLL2+PLL3 OSC_IN OSC_OUT @VDD POR reset Int SUPPLY SUPERVISION POR/PDR/BOR PVD VDDA, VSSA NRESET WKUP[1;2;4;6] MSv52542V3 DS13312 Rev 3 17/284 56 Description STM32H735xG Table 2. STM32H735xG features and peripheral counts Peripherals STM32H STM32H STM32H STM32H STM32H STM32H STM32H STM32H 735RGV 735VGT 735VGH 735ZGT 735VGY 735AGI 735IGK 735IGT Flash memory (Kbytes) SRAM (Kbytes) 1024 SRAM mapped onto AXI bus 128 SRAM1 (D2 domain) 16 SRAM2 (D2 domain) 16 SRAM4 (D3 domain) 16 RAM shared between ITCM and AXI (Kbytes) TCM RAM in Kbytes 192 ITCM RAM (instruction) 64 DTCM RAM (data) 128 Backup SRAM (Kbytes) 4 Interface FMC 1 NOR Flash memory/RAM controller - - - - - yes yes yes Multiplexed I/O NOR Flash memory - yes yes yes - yes yes yes 16-bit NAND Flash memory - yes yes yes yes yes yes yes 16-bit SDRAM controller - - - - - yes yes yes 24-bit SDRAM controller(1) - - - - - - yes - 46 67 74 97 67 121 128 119 1 QuadSPI 1 QuadSPI 1 1 2 QuadSPI 2 2 2 GPIO Octo-SPI interface OTFDEC yes Cordic yes FMAC yes 18/284 DS13312 Rev 3 STM32H735xG Description Table 2. STM32H735xG features and peripheral counts (continued) Peripherals STM32H STM32H STM32H STM32H STM32H STM32H STM32H STM32H 735RGV 735VGT 735VGH 735ZGT 735VGY 735AGI 735IGK 735IGT General purpose 32 bits 4 4 4 4 4 4 4 4 General purpose 16 bits 10 10 10 10 10 10 10 10 Advanced control (PWM) 2(2) 2 2(2) 2 2 2 2 2 Basic 2 2 2 2 2 2 2 2 Low-power 5 5 5 5 5 5 5 5 RTC 1 1 1 1 1 1 1 1 Window watchdog / independent watchdog 2 2 2 2 2 2 2 2 Wakeup pins 3 4 4 4 4 4 4 4 Tamper pins 1 2 2 2 2 2 2 2 Timers Random number generator yes Cryptographic accelerator yes 4/4 5/4(2) 5/4 6/4 4/4 6/4 6/4 6/4 4 5 5 5 5 5 5 5 USART/UART /LPUART 3/4/1 4/4/1 4/6/1 5/5/1 4/4/1 5/5/1 5/5/1 5/5/1 SAI/PDM 1/0(2) 2/1(2) 2/1(2) 2/1 1/1(2) 2/1 2/1 2/1 SPI / I2S I2C Communication interfaces SPDIFRX 1 HDMI-CEC 1 SWPMI 1 MDIO 1 SDMMC 2 FDCAN/ TT-FDCAN 1/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 USB [OTG_HS (ULPI)/FS (PHY)] 1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1] Ethernet [MII/RMII] - 1 [1/1] 1 [1/1] 1 [1/1] 1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1] Camera interface/PSSI yes DS13312 Rev 3 19/284 56 Description STM32H735xG Table 2. STM32H735xG features and peripheral counts (continued) Peripherals STM32H STM32H STM32H STM32H STM32H STM32H STM32H STM32H 735RGV 735VGT 735VGH 735ZGT 735VGY 735AGI 735IGK 735IGT yes(2) LCD-TFT yes(2) yes yes Chrom-ART Accelerator (DMA2D) 16-bit ADCs yes 0 0 2/2 0 2/2 2/2 2/2 0 Number of Fast channels ADC1/ADC2 3/2 3/2 3/2 4/2 3/2 6/5 6/5 4/3 Number of Slow channels ADC1/ADC2 11/10 11/10 9/8 11/11 9/8 12/11 12/11 12/11 Number of Direct 12-bit ADCs channels 1 0 2 2 2 2 2 2 2 Number of Fast channels 0 2 6 4 6 6 6 6 Number of Slow channels 2 0 9 3 9 9 9 4 Present in IC yes Number of channels 2 Comparators 2 Operational amplifiers 2 DFSDM yes 2 Number of ADCs 12-bit DAC yes yes Number of ADCs Number of Direct channels ADC1/ADC2 yes Present in IC yes Maximum CPU frequency 550 MHz USB separate supply pad - yes yes yes yes yes yes yes USB internal regulator - - - yes yes yes yes yes LDO - yes SMPS step-down converter Operating voltage Operating temperature 20/284 yes 1.71 to 3.6 V 1.62 to 3.6 V Ambient temperature -40°C to +85°C Junction temperature -40°C to +125°C DS13312 Rev 3 STM32H735xG Description Table 2. STM32H735xG features and peripheral counts (continued) Peripherals Extended operating temperature (3) Package STM32H STM32H STM32H STM32H STM32H STM32H STM32H STM32H 735RGV 735VGT 735VGH 735ZGT 735VGY 735AGI 735IGK 735IGT Ambient temperature -40°C to +125°C Junction temperature -40°C to +140°C VFQFPN 68 LQFP 100 TFBGA 100 LQFP 144 WLCSP 115 UFBGA 169 UFBGA 176+25 LQFP17 6 1. The 24-bit SDRAM controller is a 32-bit controller with only a 24-bit data bus and without NBL2-3. It can be used for graphical purposes to access aligned 32-bit words ignoring upper 8 bits. 2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 8: STM32H735xG pin and ball descriptions. 3. The extended temperature range is not available on WLCSP115 package. DS13312 Rev 3 21/284 56 Functional overview STM32H735xG 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex®-M7 processor is a highly efficient high-performance featuring: • Six-stage dual-issue pipeline • Dynamic branch prediction • Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache) • 64-bit AXI interface • 64-bit ITCM interface • 2x32-bit DTCM interfaces The following memory interfaces are supported: • Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency • Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses • AXI Bus interface to optimize Burst transfers • Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 1 shows the general block diagram of the STM32H735xG family. 3.2 Memory protection unit (MPU) The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. 22/284 DS13312 Rev 3 STM32H735xG Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H735xG devices embed 1 Mbyte of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: • one Flash word (8 words, 32 bytes or 256 bits) • 10 ECC bits (single-error correction and double-error detection). The Flash memory is organized as follows: 3.3.2 • 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes (4 K Flash memory words) • 128 Kbytes of system Flash memory from which the device can boot • 2 Kbytes (64 Flash words) of user option bytes for user configuration Embedded SRAM All devices feature: • from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain • SRAM1 mapped on D2 domain: 16 Kbytes • SRAM2 mapped on D2 domain: 16 Kbytes • SRAM4 mapped on D3 domain: 16 Kbytes • 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or VBAT mode. • RAM mapped to TCM interface (ITCM and DTCM): Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the Cortex®-M7CPU(AHBSAHBP): – 64 to 256 Kbytes of ITCM-RAM (instruction RAM) This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU. – 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports) The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex®-M7 dual issue capability. The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte granularity. DS13312 Rev 3 23/284 56 Functional overview STM32H735xG Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: • 7 ECC bits are added per 32-bit word. • 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection. 3.4 Secure access mode In addition to other typical memory protection mechanism (RDP, PCROP), STM32H735xG devices introduce the Secure access mode, a new enhanced security feature. This mode allows developing user-defined secure services by ensuring, on the one hand code and data protection and on the other hand code safe execution. Two types of secure services are available: • STMicroelectronics Root Secure Services: These services are embedded in System memory. They provide a secure solution for firmware and third-party modules installation. These services rely on cryptographic algorithms based on a device unique private key. • User-defined secure services: These services are embedded in user Flash memory. Examples of user secure services are proprietary user firmware update solution, secure Flash integrity check or any other sensitive applications that require a high level of protection. The secure firmware is embedded in specific user Flash memory areas configured through option bytes. Secure services are executed just after a reset and preempt all other applications to guarantee protected and safe execution. Once executed, the corresponding code and data are no more accessible. The above secure services is activated for the next reset exits through an option bit. 24/284 DS13312 Rev 3 STM32H735xG 3.5 Functional overview Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space • All RAM address space: ITCM, DTCM RAMs and SRAMs • The System memory bootloader The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to application note AN2606 “STM32 microcontroller System memory Boot mode” for details. 3.6 CORDIC co-processor (CORDIC) The CORDIC co-processor provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks. The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. CORDIC features • 24-bit CORDIC rotation engine • Circular and Hyperbolic modes • Rotation and Vectoring modes • Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root, Natural logarithm • Programmable precision up to 20-bit • Fast convergence: 4 bits per clock cycle • Supports 16-bit and 32-bit fixed point input and output formats • Low latency AHB slave interface • Results can be read as soon as ready without polling or interrupt • DMA read and write channels DS13312 Rev 3 25/284 56 Functional overview 3.7 STM32H735xG Filter mathematical accelerator (FMAC) The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. FMAC features • 16 x 16-bit multiplier • 24+2-bit accumulator with addition and subtraction • 16-bit input and output data • 256 x 16-bit local memory • Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers • Input and output sample buffers can be circular • Buffer “watermark” feature reduces overhead in interrupt mode • Filter functions: FIR, IIR (direct form 1) • AHB slave interface • DMA read and write data channels 3.8 Power supply management 3.8.1 Power supply scheme STM32H735xG power supply voltages are the following: • VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins. • VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE • VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and OPAMP. • VDD33USB: allows the support of a VDD supply different from 3.3 V while powering the USB transceiver with 3.3V on VDD33USB. • VDD50USB can be supplied through the USB cable to generate the VDD33USB via the USB internal regulator. This allows support of a VDD supply different to 3.3 V. The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V. 26/284 • VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present. • VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V, 1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The DS13312 Rev 3 STM32H735xG Functional overview VCORE domain is split into the following power domains that can be independently switch off. – D1 domain containing some peripherals and the Cortex®-M7 core – D2 domain containing a large part of the peripherals – D3 domain containing some peripherals and the system control • VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply VDDSMPS must be kept at the same voltage level as VDD • VLXSMPS = SMPS step-down converter output coupled to an inductor • VFBSMPS = VCORE or 1.8 V or 2.5 V external SMPS step-down converter feedback voltage sense input. During power-up and power-down phases, the following power sequence requirements must be respected (see Figure 2): • When VDD is below VDDmin, other power supplies (VDDA, VDD33USB, VDD50USB) must remain below VDD + 300 mV. • When VDD is above VDDmin, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. Figure 2. Power-up/power-down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB. DS13312 Rev 3 27/284 56 Functional overview 3.8.2 STM32H735xG Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: • Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in Reset mode when VDD is below this threshold, • Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold. The PDR supervisor can be enabled/disabled through PDR_ON pin. • Brownout reset (BOR) The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold. 28/284 DS13312 Rev 3 STM32H735xG 3.8.3 Functional overview Voltage regulator The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off. Voltage regulator output can be adjusted according to application needs through 6 power supply levels: • • 3.9 Run mode (VOS0 to VOS3) – Scale 0: boosted performance – Scale 1: high performance – Scale 2: medium performance and consumption – Scale 3: optimized performance and low-power consumption Stop mode (SVOS3 to SVOS5) – Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C, LPTIM) are operational – Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt. Low-power strategy There are several ways to reduce power consumption on STM32H735xG: • Decrease the dynamic power consumption by slowing down the system clocks even in Run mode and by individually clock gating the peripherals that are not used. • Save power when the CPU is idle, by selecting among the available low-power modes according to the user application needs. This allows the best compromise between short startup time and low power consumption to be achieved, according to the available wakeup sources. The devices feature several low-power modes: • CSleep (CPU clock stopped) • CStop (CPU sub-system clock stopped) • DStop (Domain bus matrix clock stopped) • Stop (System clock stopped) • DStandby (Domain powered down) • Standby (System powered down) CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-Mx core is set after returning from an interrupt service routine. A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode. DS13312 Rev 3 29/284 56 Functional overview STM32H735xG Table 3. System versus domain low-power mode System power mode D1 domain power mode D2 domain power mode D3 domain power mode Run DRun/DStop/DStandby DRun/DStop/DStandby DRun Stop DStop/DStandby DStop/DStandby DStop Standby DStandby DStandby DStandby 3.10 Reset and clock controller (RCC) The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), thus the system frequency can be changed without modifying the baudrate. 3.10.1 Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs. The RCC receives the following clock source inputs: • • Internal oscillators: – 64 MHz HSI clock – 48 MHz RC oscillator – 4 MHz CSI clock – 32 kHz LSI clock External oscillators: – HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated from a crystal/ceramic resonator) – LSE clock: 32.768 kHz The RCC provides three PLLs: one for system clock, two for kernel clocks. The system starts on the HSI clock. The user application can then select the clock configuration. 30/284 DS13312 Rev 3 STM32H735xG 3.10.2 Functional overview System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: 3.11 • Power-on reset (pwr_por_rst) • Brownout reset • Low level on NRST pin (external reset) • Window watchdog • Independent watchdog • Software reset • Low-power mode security reset • Exit from Standby General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs register reset values in the device reference manual). The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.12 Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow the interconnection of bus masters with bus slaves (see Figure 3). DS13312 Rev 3 31/284 56 Functional overview AHBS OR MDMA DMA2D DMA1_MEM SDMMC1 LTDC D1-to-D2 AHB DMA2 DMA2_MEM DMA1 AHBP AXIM I$ D$ 32KB 32KB ITCM 64 Kbyte ITCM 192 Kbyte DTCM 128 Kbyte Ethernet SDMMC2 USBHS1 MAC DMA2_PERIPH CPU Cortex-M7 DMA1_PERIPH 32/284 Figure 3. STM32H735xG bus matrix AXI SRAM 192K byte SRAM1 16 Kbyte SRAM2 16 Kbyte Flash A Up to 1 Mbyte AHB1 DS13312 Rev 3 AXI SRAM 128 Kbyte OTFDEC1 OCTOSPI1 OTFDEC2 OCTOSPI2 AHB2 APB1 FMC AHB3 APB2 APB3 64-bit AXI bus matrix D1 domain 32-bit AHB bus matrix D2 domain D2-to-D1 AHB D2-to-D3 AHB D1-to-D3 AHB BDMA 32-bit AHB bus matrix D3 domain 32-bit bus AHB4 TCM AHB AXI APB 64-bit bus Master interface Bus multiplexer Slave interface APB4 SRAM4 16 Kbyte Backup SRAM 4 Kbyte MSv46613V3 STM32H735xG Legend STM32H735xG 3.13 Functional overview DMA controllers The devices feature four DMA instances and a DMA request router to unload CPU activity: • A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex®-M7 TCM memories. The MDMA is located in D1 domain. It is able to interface with the other DMA controllers located in D2 domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers. • Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request router capabilities. • One basic DMA (BDMA) located in D3 domain, with request router capabilities. • A DMA request multiplexer (DMAMUX) The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event. 3.14 Chrom-ART Accelerator (DMA2D) The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: • Filling a part or the whole of a destination image with a specific color • Copying a part or the whole of a source image into a part or the whole of a destination • image • Copying a part or the whole of a source image into a part or the whole of a destination • image with a pixel format conversion • Blending a part and/or two complete source images with different pixel format and copy • the result into a part or the whole of a destination image with a different color format. • All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with indexed or direct color mode, including block based YCbCr to handle JPEG decoder output. • The DMA2D has its own dedicated memories for CLUTs (color look-up tables). An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automated and are running independently from the CPU or the DMAs. DS13312 Rev 3 33/284 56 Functional overview 3.15 STM32H735xG Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor context automatically saved on interrupt entry, and restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.16 Extended interrupt and event controller (EXTI) The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power domains and/or D3 domain from Stop mode. The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events and 54 direct events. Configurable events have dedicated pending flags, active edge selection, and software trigger capable. Direct events provide interrupts or events from peripherals having a status flag. 3.17 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 34/284 DS13312 Rev 3 STM32H735xG 3.18 Functional overview Flexible memory controller (FMC) The FMC controller main features are the following: • Interface with static-memory mapped devices including: 3.19 – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories • 8-,16-, 24-bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • Read FIFO for SDRAM controller • The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided by 2. Octo-SPI memory interface (OCTOSPI) The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal SPI memories. The STM32H735xG embeds two separate Octo-SPI interfaces. Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of single/dual/quad/octal SPI over the same bus can be achieved using the integrated OctoSPI I/O manager (OCTOSPIM). The OCTOSPI can operate in any of the three following modes: • Indirect mode: all the operations are performed using the OCTOSPI registers • Status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an internal memory supporting both read and write operations. The OCTOSPI supports two frame formats supported by most external serial memories such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and Hyper Flash memories. Multi chip package (MCP) combining any of the above mentioned memory types can also be supported. • The classical frame format with the command, address, alternate byte, dummy cycles and data phase • The HyperBus™ frame format. DS13312 Rev 3 35/284 56 Functional overview 3.20 STM32H735xG Analog-to-digital converters (ADCs) STM32H735xG devices embed three analog-to-digital converters, two of 16-bit resolution, and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14, 12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits. Each ADC shares up to 20 external channels, performing conversions in Single-shot or Scan mode. In Scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC converted values to a destination location without any software action. In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some, or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers. 3.21 Temperature sensor STM32H735xG devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from − 40 to +125°C. The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is accessible in Read-only mode. 3.22 Digital temperature sensor (DTS) STM32H735xG devices embed a sensor that converts the temperature into a square wave the frequency of which is proportional to the temperature. The PCLK or the LSE clock can be used as the reference clock for the measurements. A formula given in the product reference manual allows calculation of the temperature according to the measured frequency stored in the DTS_DR register. 36/284 DS13312 Rev 3 STM32H735xG 3.23 Functional overview VBAT operation The VBAT power domain contains the RTC, the backup registers and the backup SRAM. To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped below the PDR level. The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in which case, the VBAT mode is not functional. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.24 Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel including DMA underrun error detection • external triggers for conversion • input voltage reference VREF+ or internal VREFBUF reference. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. DS13312 Rev 3 37/284 56 Functional overview 3.25 STM32H735xG Ultra-low-power comparators (COMP) STM32H735xG devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output polarity. The reference voltage can be one of the following: • An external I/O • A DAC output channel • An internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into a window comparator. 3.26 Operational amplifiers (OPAMP) STM32H735xG devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability. The operational amplifier main features are: • PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15 • One positive input connected to DAC • Output connected to internal ADC • Low input bias current down to 1 nA • Low input offset voltage down to 1.5 mV • Gain bandwidth up to 7.3 MHz The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 38/284 DS13312 Rev 3 STM32H735xG 3.27 Functional overview Digital filter for sigma-delta modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from internal ADC peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • internal sources: ADC data or memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by: • • • – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from final output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel break signal generation on analog watchdog event or on short circuit detector event DS13312 Rev 3 39/284 56 Functional overview • STM32H735xG extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: • – “regular” conversions can be requested at any time or even in Continuous mode without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Pulse skipper feature to support beamforming applications (delay-line like behavior). Table 4. DFSDM implementation DFSDM features 40/284 DFSDM1 Number of filters 4 Number of input transceivers/channels 8 Internal ADC parallel input X Number of external triggers 16 Regular channel information in identification register X DS13312 Rev 3 STM32H735xG 3.28 Functional overview Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It features: 3.29 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports Continuous mode or Snapshot (a single frame) mode • Capability to automatically crop the image PSSI The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It allows the transmitter to send a data valid signal to indicate when the data is valid, and the receiver to output a flow control signal to indicate when it is ready to sample the data. The main PSSI features are: • Slave mode operation • 8- or 16-bit parallel data input or output • 8-word (32-byte) FIFO • Data enable (DE) alternate function input and Ready (RDY) alternate function output. When enabled, these signals can either allow the transmitter to indicate when the data is valid or, the receiver to indicate when it is ready to sample the data, or both. The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore cannot be used simultaneously with the DCMI. 3.30 LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024 x 768) resolution with the following features: • 2 display layers with dedicated FIFO (64x64-bit) • Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer • Up to 8 input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to 4 programmable interrupt events • AXI master interface with burst of 16 words DS13312 Rev 3 41/284 56 Functional overview 3.31 STM32H735xG True random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as a NIST SP 800-90B compliant entropy source. The RNG true random number generator has been tested using German BSI statistical tests of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite. 3.32 Cryptographic acceleration (CRYP and HASH) The devices embed a cryptographic processor that supports the advanced cryptographic algorithms usually required to ensure confidentiality, authentication, data integrity and nonrepudiation when exchanging messages with a peer: • • Encryption/Decryption – DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key – AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key Universal HASH – – SHA-1 and SHA-2 (secure HASH algorithms) – – MD5 – – HMAC The cryptographic accelerator supports DMA request generation. 3.33 On-the-fly decryption engine (OTFDEC) The embedded OTFDEC decrypts in real-time the encrypted content stored in the external Octo-SPI memories used in Memory-mapped mode. The OTFDEC uses the AES-128 algorithm in counter mode (CTR). Code execution on external Octo-SPI memories can be protected against fault injection thanks to STMicroelectronics enhanced encryption mode (refer to RM0468 for details). 42/284 DS13312 Rev 3 STM32H735xG Functional overview The OTFDEC main features are as follow: • • On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or multiple). – AES-CTR algorithm with keystream FIFO (depth= 4) – Support for any read size Up to four independent encrypted regions – Region definition granularity: 4096 bytes – Region configuration write locking mechanism – Two optional decryption modes: execute-only and execute-never • 128-bit key for each region, two-byte firmware version, and eight-byte applicationdefined nonce • Encryption keys confidentiality and integrity protection • – Write only registers with software locking mechanism – Availability of 8-bit CRC as public key information Support for STM32 Octo-SPI prefetching mechanism. DS13312 Rev 3 43/284 56 Functional overview 3.34 STM32H735xG Timers and watchdogs The devices include two advanced-control timers, twelve general-purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer. All timer counters can be frozen in Debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5. Timer feature comparison Timer type Advanced -control Timer TIM1, TIM8 TIM2, TIM5, TIM23, TIM24 TIM3, TIM4 TIM12 DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels TIM15 TIM16, TIM17 44/284 Max interface clock (MHz) Max timer clock (MHz) (1) 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 137.5 275 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 137.5 275 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 137.5 275 16-bit Up Any integer between 1 and 65536 No 2 No 137.5 275 Up Any integer between 1 and 65536 No 1 No 137.5 275 Up Any integer between 1 and 65536 Yes 2 1 137.5 275 Up Any integer between 1 and 65536 Yes 1 1 137.5 275 General purpose TIM13, TIM14 Complementary output 16-bit 16-bit 16-bit DS13312 Rev 3 STM32H735xG Functional overview Table 5. Timer feature comparison (continued) Timer type Timer DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Complementary output Max interface clock (MHz) Max timer clock (MHz) (1) Yes 0 No 137.5 275 No 0 No 137.5 275 1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register. DS13312 Rev 3 45/284 56 Functional overview 3.34.1 STM32H735xG Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (Edge- or Center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.34.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32H735xG devices (see Table 5: Timer feature comparison for differences). • TIM2, TIM3, TIM4, TIM5, TIM23, TIM24 The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or One-pulse mode output. This gives up to 24 input capture/output compare/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases. 46/284 DS13312 Rev 3 STM32H735xG 3.34.3 Functional overview Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.34.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.34.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous / One-shot mode • Selectable software / hardware input trigger • Selectable clock source: • Internal clock source: LSE, LSI, HSI or APB clock • External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) • Programmable digital glitch filter • Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. A window option allows the device to be reset when a reload operation is made too early after the previous reload. 3.34.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. 3.34.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. DS13312 Rev 3 47/284 56 Functional overview 3.35 STM32H735xG Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 48/284 DS13312 Rev 3 STM32H735xG 3.36 Functional overview Inter-integrated circuit interface (I2C) STM32H735xG devices embed five I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • 3.37 I2C-bus specification and user manual rev. 5 compatibility: – Slave and Master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Universal synchronous/asynchronous receiver transmitter (USART) STM32H735xG devices have five embedded universal synchronous receiver transmitters (USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 6: USART features for a summary of USARTx and UARTx features. These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire Half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 17 Mbit/s. USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. DS13312 Rev 3 49/284 56 Functional overview STM32H735xG All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 6. USART features USART modes/features(1) USART1/2/3/6/10 UART4/5/7/8/9 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode (Master/Slave) X - Smartcard mode X - Single-wire Half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain and wakeup from low power mode X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X USART data length 7, 8 and 9 bits Tx/Rx FIFO X Tx/Rx FIFO size X 16 1. X = supported. 3.38 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART (LPUART1). The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. 50/284 DS13312 Rev 3 STM32H735xG Functional overview The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.39 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability. Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available. They can be operated in Master or Slave mode, in Simplex communication modes, and can be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6 which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in Master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability. 3.40 Serial audio interfaces (SAI) The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. DS13312 Rev 3 51/284 56 Functional overview 3.41 STM32H735xG SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.288 MHz • Stereo stream from 32 to 192 kHz supported • Supports Audio IEC-60958 and IEC-61937, consumer applications • Parity bit management • Communication using DMA for audio samples • Communication using DMA for control and user channel information • Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 3.42 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • Full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 52/284 DS13312 Rev 3 STM32H735xG 3.43 Functional overview Management data input/output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: • – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers • Configurable slave (port) address • Independently maskable interrupts/events: • 3.44 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: – MDIO Register write – MDIO Register read – MDIO protocol error Able to operate in and wake up from Stop mode SD/SDIO/MMC card host interfaces (SDMMC) Two SDMMC host interfaces are available. They support MultiMediaCard System Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits. Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits. Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM. 3.45 Controller area network (FDCAN1, FDCAN2, FDCAN3) The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit. All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is shared between the three modules - FDCAN1 FDCAN2 and FDCAN3. The common clock calibration unit is optional. It can be used to generate a calibrated clock for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1. DS13312 Rev 3 53/284 56 Functional overview 3.46 STM32H735xG Universal serial bus on-the-go high-speed (OTG_HS) The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral that supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external PHY device connected to the ULPI is required. The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It features software-configurable endpoint setting and supports suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The main features are: 3.47 • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. 54/284 DS13312 Rev 3 STM32H735xG Functional overview The devices include the following features: 3.48 • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.49 Debug infrastructure The devices offer a comprehensive set of debug and trace features to support software development and system integration. • Breakpoint debugging • Code execution tracing • Software instrumentation • JTAG debug port • Serial-wire debug port • Trigger input and output • Serial-wire trace port • Trace port • Arm® CoreSight™ debug and trace components The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. The trace port performs data capture for logging and analysis. DS13312 Rev 3 55/284 56 Memory mapping 4 STM32H735xG Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 56/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions VDD VSS VCAP PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Figure 4. VFQFPN68 pinout VBAT 1 51 VDD PC14-OSC32_IN 2 50 VSS PC15-OSC32_OUT 3 49 VCAP VSSSMPS 4 48 PA13 VLXSMPS 5 47 PA12 VDDSMPS 6 46 PA11 VFBSMPS 7 45 PA10 VSS 8 44 PA9 VDD 9 43 PA8 VFQFPN48 PH0-OSC_IN 10 42 PC9 PH1-OSC_OUT 11 41 PC7 NRST 12 40 PC6 PC0 13 39 PB15 PC1 14 38 PB14 VSSA 15 37 PB13 VDDA 16 36 PB12 PA0 17 35 VDD 34 VSS VSS 33 VCAP 32 PB10 31 PB2 30 PB1 29 PB0 28 PC5 27 PC4 26 PA7 25 PA6 24 PA5 23 PA4 22 VDD 21 VSS 20 PA3 19 PA2 18 Exposed pad PA1 5 Pinouts, pin descriptions and alternate functions MSv52556V2 1. The above figure shows the package top view. 2. VSS pads are connected to the exposed pad. Figure 5. TFBGA100 pinout 1 2 3 4 5 6 7 8 9 10 A PE6 PE5 PE2 PB8 BOOT0 PB5 PD6 PD3 PD2 PC12 B PC14OSC32_IN PC15OSC32_OUT PE3 PE0 PB7 PB3 PD4 PD1 PC11 PC10 C VSS VBAT PE4 PE1 PB4 PD7 PD0 PA15 PA14 PA13 D VSSSMPS VLXSMPS PDR_ON PB6 VSS VDD PD5 VCAP PA12 PA11 E VDDSMPS VFBSMPS PB9 PC13 VDD VDDLDO VSS VDD33USB PA9 PA10 F PC1 NRST PC0 PC2_C VSS VDD VDDLDO PC6 PC9 PA8 G PH0-OSC_IN PH1OSC_OUT PA0 PC3_C PA3 VCAP PD14 PD15 PC7 PC8 H VDDA VSSA PA2 PC4 PE7 PE10 PD11 PD9 PD12 PD13 J VREF+ PA1 PA6 PC5 PB2 PE8 PB11 PB13 PD8 PD10 K PA4 PA5 PA7 PB0 PB1 PE9 PB10 PB12 PB14 PB15 MSv65396V2 1. The above figure shows the package top view. DS13312 Rev 3 57/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG VDDLDO VSS VCAP PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 VDD PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD33USB 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD 100 99 Figure 6. LQFP100 pinout PE2 1 75 VDD PE4 2 74 VDDLDO PE5 3 73 VSS VDD 4 72 VCAP VBAT 5 71 PA13 PC13 6 70 PA12 PC14-OSC32_IN 7 69 PA11 PC15-OSC32_OUT 8 68 PA10 VSSSMPS 9 67 PA9 VLXSMPS 10 66 PA8 VDDSMPS 11 65 PC9 VFBSMPS 12 64 PC8 PH0-OSC_IN 13 63 PC7 PH1-OSC_OUT 14 62 PC6 NRST 15 61 PD15 PC0 16 60 PD14 PC1 17 59 VDD PC2_C 18 58 VSS PC3_C 19 57 PD13 VDD 20 56 PD12 VSS 21 55 PD11 VSSA 22 54 PD10 VREF+ 23 53 PD9 VDDA 24 52 PD8 PA0 25 51 PB15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA1 PA2 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PB10 PB11 VCAP VSS VDDLDO VDD PB12 PB13 PB14 LQFP100 MSv52555V1. 1. The above figure shows the package top view. 58/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Figure 7. WLCSP115 ballout 1 A B VCAP H PC6 J K VDD50USB M VDD N P VSS PD12 Y PD8 VDD PB15 VDDLDO VDD VCAP VSS VSS PA2 PC4 VDD PB2 PH1OSC_OUT VSSA VSS VSS PH0-OSC_IN NRST PA5 PB1 VDD PC1 PA6 PE8 VSS VDD PA1 PB0 PB11 PC0 PA3 PB10 VDDSMPS VFBSMPS PA0 PA7 PB12 VBAT PB7 PB13 PB14 VSS W AA PD10 VSSSMPS VLXSMPS PDR_ON PE7 VSS VDD PC13 PB6 PC9 PD9 PD11 U V PD13 PE4 PE0 PC11 PC14OSC32_IN PC15OSC32_OUT PB9 PB3 PA10 PE2 VDD VDDLDO PB4 VDD VREF+ PA4 PC5 11 VSS PB8 PD0 PC8 PD15 R T PC7 PD14 PB5 PA15 10 VCAP BOOT0 PD4 PA9 9 VDD PD5 PC12 PA8 VDD33USB L PD1 PA13 8 VSS VSS PC10 PA12 7 VDD VSS VSS 6 PD3 PA14 VDD 5 PD2 PA11 G 4 VDD VDDLDO E F 3 VDD VSS C D 2 VDDA VDD MSv52557V1 1. The above figure shows the package top view. DS13312 Rev 3 59/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VDDLDO PDR_ON VSS VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 Figure 8. LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA15 PA14 VDD VDDLDO VSS VCAP PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VDD33USB VDD50USB VSS PG8 PG7 PG6 PD15 PD14 PD13 PD12 PD11 VSS VDD PD10 PD9 PD8 PB15 PB14 PB13 PA0 PA1 PA2 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF14 PF15 VSS VDD PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDDLDO VDD PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VSS VDD VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD VSSSMPS VLXSMPS VDDSMPS VFBSMPS VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VDD VSS VSSA VREF+ VDDA MSv52554V1. 1. The above figure shows the package top view. 60/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VDD VDDLDO PDR_ON VSS VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 VDD VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VSS VDD VDDLDO VSS VCAP Figure 9. LQFP176 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA13 PA12 PA11 PA10 PA9 PA8 VDD PC9 PC8 PC7 PC6 VDD33USB VDD50USB VSS PG8 PG7 PG6 PG5 PG4 VDD VSS PG3 PG2 PK2 PK1 PK0 VSS VDD PJ11 PJ10 PJ9 PJ8 VSS VDD PD15 PD14 PD13 PD12 PD11 VSS VDD PD10 PD9 PD8 VSS PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 PF13 PF14 PF15 PG0 VSS VDD PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDDLDO VSS VDD PB12 PB13 PB14 PB15 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PE2 PE3 PE4 PE5 PE6 VSS VDD VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD VSSSMPS VLXSMPS VDDSMPS VFBSMPS PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VSSA VREF+ VDDA PA0 PA1 PA2 VDD MSv52553V1. 1. The above figure shows the package top view. DS13312 Rev 3 61/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Figure 10. UFBGA169 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 A PE4 PE2 VDD VCAP PB6 VDD VDD PG10 PD5 VDD PC12 PC10 PH14 B PC15OSC32_OUT PE3 VSS VDDLDO PB8 PB4 VSS PG11 PD6 VSS PC11 PA14 PH13 C PC14OSC32_IN PE6 PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD D VDD VSS PC13 PE1 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP E VLXSMPS VSSSMPS VBAT PF1 PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12 F VDDSMPS VFBSMPS PF0 PF2 PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11 G VDD VSS PF4 PF6 PF9 NRST PF13 PE7 PG6 PG7 PG8 VDD50USB VDD33USB H PH0-OSC_IN PH1OSC_OUT PF10 PF8 PC2 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD J PC0 PC1 VSSA PC3 PA0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14 K PC3_C PC2_C PA0_C PA1 PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12 L VDDA VREF+ PA1_C PA5 PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD M VDD VSS PH3 VSS PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15 N PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14 MSv52551V1. 1. The above figure shows the package top view. Figure 11. UFBGA176+25 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A VSS PB8 VDDLDO VCAP PB6 PB3 PG11 PG9 PD3 PD1 PA15 PA14 VDDLDO VCAP VSS B PE4 PE3 PB9 PE0 PB7 PB4 PG13 PD7 PD5 PD2 PC12 PH14 PA13 PA8 PA12 C PC13 VSS PE2 PE1 BOOT0 PB5 PG14 PG10 PD4 PD0 PC11 PC10 PH13 PA10 PA11 D PC15OSC32_OUT PC14OSC32_IN PE5 PDR_ON VDD VSS PG15 PG12 PD6 VSS VDD PH15 PA9 PC8 PC7 E VSS VBAT PE6 VDD VDD PC9 PC6 VDD50USB F VLXSMPS VSSSMPS PF1 PF0 VSS VSS VSS VSS VSS VSS VDD33USB PG6 PG5 G VDDSMPS VFBSMPS PF2 VDD VSS VSS VSS VSS VSS PG8 PG7 PG4 PG2 H PF6 PF4 PF5 PF3 VSS VSS VSS VSS VSS VDD PG3 PD14 PD13 J PH0-OSC_IN PF8 PF7 PF9 VSS VSS VSS VSS VSS PD15 PD11 VSS PD12 K PH1OSC_OUT VSS PF10 VDD VSS VSS VSS VSS VSS VSS PD9 PB15 PB14 L NRST PC0 PC1 VREF- VDD PD10 PD8 PB13 M PC2 PC3 VREF+ VDDA VDD VSS PC5 PH11 PH9 PB12 N PC2_C PC3_C VSSA PH2 PA3 PA7 P PA0 PA1 PA1_C PH4 PA4 PA5 R VSS PA2 PA0_C PH3 PH5 PC4 PB1 VDD VSS PH7 PE14 PF11 PE8 PB2 PG0 PG1 PF15 PF13 PB10 PH8 PH10 PH12 PE7 PB11 PF12 PE12 PE13 PE15 PH6 PA6 PB0 PE10 PF14 PE9 PE11 VCAP VDDLDO VSS MSv52552V1. 1. The above figure shows the package top view. 62/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.3 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Notes Pin functions Definition Bidirectional reset pin with embedded weak pull-up resistor Option for TT and FT I/Os _f I2C FM+ option _a analog option (supplied by VDDA) _u USB option (supplied by VDD33USB) _h High-speed low-voltage I/O Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DS13312 Rev 3 63/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions - 64/284 2 3 B3 C3 A2 2 3 4 B11 - F9 - A2 B2 A1 C3 C3 B2 B1 D3 1 2 3 4 PE2 PE3 PE4 PE5 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS 1 I/O I/O I/O I/O FT_h FT_h FT_h FT_h DS13312 Rev 3 Additional functions - - A3 Alternate functions - 1 Notes - TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number - TRACECLK, SAI1_CK1, USART10_RX, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, OCTOSPIM_P1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23, EVENTOUT - - TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, USART10_TX, FMC_A19, EVENTOUT - - TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SAI4_FS_A, SAI4_D2, FMC_A20, DCMI_D4/PSSI_D4, LCD_B0, EVENTOUT - - TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SAI4_SCK_A, SAI4_CK2, FMC_A21, DCMI_D6/PSSI_D6, LCD_G0, EVENTOUT - STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PE6 I/O FT_h - - - - - 6 - - - 6 VSS S - - - - - 4 - 7 - - - 7 VDD S - - - - 1 5 C2 8 K9 E3 E2 8 VBAT S - - - - - 6 E4 9 H9 D3 C1 9 PC13 I/O FT - EVENTOUT RTC_TAMP1/ RTC_TS, WKUP4 - - - - F11 - - - VSS S - - - - 2 7 B1 10 D11 C1 D2 10 PC14OSC32_IN I/O FT - EVENTOUT OSC32_IN 3 8 B2 11 E10 B1 D1 11 PC15OSC32_ OUT I/O FT - EVENTOUT OSC32_OUT - - - 12 F11 - - 12 VSS S - - - - - - - 13 G10 - - 13 VDD S - - - - 4 9 D1 14 H11 E2 F2 14 VSSSMPS S - - - - 5 10 D2 15 J10 E1 F1 15 VLXSMPS S - - - - 6 11 E1 16 K11 F1 G1 16 VDDSMPS S - - - - 7 12 E2 17 L10 F2 G2 17 VFBSMPS S - - - - - I2C2_SDA(boot), I2C5_SDA, OCTOSPIM_P2_IO0, FMC_A0, TIM23_CH1, EVENTOUT - - - - - - F3 F4 18 PF0 Pin type I/O structure 5 LQFP176 SMPS E3 UFBGA176+25 SMPS C2 UFBGA169 SMPS - WLCSP115 SMPS 5 LQFP144 SMPS A1 TFBGA100 SMPS - LQFP100 SMPS - TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI4_SD_A, SAI4_D1, SAI4_MCLK_B, TIM1_BKIN2_COMP1 2, FMC_A22, DCMI_D7/PSSI_D7, LCD_G1, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O FT_fh DS13312 Rev 3 65/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) - E4 F3 19 PF1 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS - I/O FT_fh Additional functions - Alternate functions - Notes - TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number - I2C2_SCL(boot), I2C5_SCL, OCTOSPIM_P2_IO1, FMC_A1, TIM23_CH2, EVENTOUT - - - - - - - F4 G3 20 PF2 I/O FT_h - I2C2_SMBA, I2C5_SMBA, OCTOSPIM_P2_IO2, FMC_A2, TIM23_CH3, EVENTOUT - - - - - E5 H4 21 PF3 I/O FT_ha - OCTOSPIM_P2_IO3, FMC_A3, TIM23_CH4, EVENTOUT ADC3_INP5 - - - - - G3 H2 22 PF4 I/O FT_ha - OCTOSPIM_P2_CLK, FMC_A4, EVENTOUT ADC3_INN5, ADC3_INP9 - - - - - F5 H3 23 PF5 I/O FT_ha - OCTOSPIM_P2_NCL K, FMC_A5, EVENTOUT ADC3_INP4 8 - - 18 M11 - - 24 VSS S - - - - 9 - - 19 N10 - - 25 VDD S - - - - - TIM16_CH1, FDCAN3_RX, SPI5_NSS, SAI1_SD_B, UART7_RX, SAI4_SD_B, OCTOSPIM_P1_IO3, TIM23_CH1, EVENTOUT ADC3_INN4, ADC3_INP8 - TIM17_CH1, FDCAN3_TX, SPI5_SCK, SAI1_MCLK_B, UART7_TX, SAI4_MCLK_B, OCTOSPIM_P1_IO2, TIM23_CH2, EVENTOUT ADC3_INP3 - - 66/284 - - - - 20 21 - - G4 F6 H1 J3 26 27 PF6 PF7 I/O I/O FT_ha FT_ha DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) 23 - - H4 G5 J2 J4 28 29 PF8 PF9 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS - 22 I/O I/O FT_ha FT_ha Additional functions - - Alternate functions - - Notes - LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_ DE, SAI4_SCK_B, TIM13_CH1, OCTOSPIM_P1_IO0, TIM23_CH3, EVENTOUT ADC3_INN3, ADC3_INP7 - TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, SAI4_FS_B, TIM14_CH1, OCTOSPIM_P1_IO1, TIM23_CH4, EVENTOUT ADC3_INP2 ADC3_INN2, ADC3_INP6 - - - 24 - H3 K3 30 PF10 I/O FT_ha - TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPIM_P1_CLK, SAI4_D3, DCMI_D11/PSSI_D11, LCD_DE, EVENTOUT 10 13 G1 25 P11 H1 J1 31 PH0OSC_IN I/O FT - EVENTOUT OSC_IN 11 14 G2 26 T11 H2 K1 32 PH1OSC_OUT I/O FT - EVENTOUT OSC_OUT 12 15 F2 27 R10 G6 L1 33 NRST I/O RST - - - 13 16 F3 28 M9 J1 L2 34 PC0 I/O FT_ha DS13312 Rev 3 - FMC_D12/FMC_AD12 , DFSDM1_CKIN0, DFSDM1_DATIN4, SAI4_FS_B, ADC123_INP10 FMC_A25, OTG_HS_ULPI_STP, LCD_G2, FMC_SDNWE, LCD_R5, EVENTOUT 67/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) 14 17 - - F1 29 - - - 18 F4 30 (2) - (2) (2) P9 - - M1 (1) - K2 N1 36 (1) (1) (1) (2) - 21 - 15 22 H2 Additional functions Alternate functions Notes I/O structure Pin type - PC2_C ANA TT_a - - ADC3_INN1, ADC3_INP0 ADC12_INN12, ADC12_INP13 TT_a - - ADC3_INP1 - - VDD S - - - - - - - VSS S - - - - J3 N3 38 VSSA S - - - - T9 32 FT_a ANA 34 - I/O PC3_C U10 20 PC2 (2) 33 - PWR_DEEPSLEEP, DFSDM1_CKIN1, OCTOSPIM_P1_IO5, SPI2_MISO/I2S2_SDI, ADC123_INN11 DFSDM1_CKOUT, , OCTOSPIM_P1_IO2, ADC123_INP12 OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT - - - - FT_a V11 (2) FT_ha I/O 37 31 I/O PC3 N2 G4 PC1 TRACED0, SAI4_D1, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, ADC123_INN10 SPI2_MOSI/I2S2_SD , O, SAI1_SD_A, ADC123_INP11 SAI4_SD_A, , RTC_TAMP3, SDMMC2_CK, WKUP6 OCTOSPIM_P1_IO4, ETH_MDC, MDIOS_MDC, LCD_G5, EVENTOUT PWR_SLEEP, DFSDM1_DATIN1, OCTOSPIM_P1_IO6, SPI2_MOSI/ I2S2_SDO, OCTOSPIM_P1_IO0, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT K1 - Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS H5 - 19 68/284 35 (1) - (2) L3 M2 - (2) J2 J4 - - UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number (1) (1) (1) DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) VFQFPN68 SMPS LQFP100 SMPS TFBGA100 SMPS LQFP144 SMPS WLCSP115 SMPS UFBGA169 SMPS UFBGA176+25 SMPS LQFP176 SMPS Pin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions Pin number - - - - - - L4 - VREF- S - - - - - 23 J1 35 W10 L2 M3 39 VREF+ S - - - - 16 24 H1 36 Y11 L1 M4 40 VDDA S - - - - ADC1_INP16, WKUP1 17 25 G3 37 N8 - - - - - 18 26 J2 38 R8 - - - - - J5 P1 K3 R3 (1) (1) (1) (1) K4 P2 L3 P3 (1) (1) (1) (1) 41 PA0 I/O FT_ha - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS/I2S6_WS, USART2_CTS/USART 2_NSS, UART4_TX, SDMMC2_CMD, SAI4_SD_B, ETH_MII_CRS, FMC_A19, EVENTOUT - PA0_C ANA TT_a - - ADC12_INN1, ADC12_INP0 ADC1_INN16, ADC1_INP17 ADC12_INP1 42 PA1 I/O FT_ha - TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS/USART 2_DE, UART4_RX, OCTOSPIM_P1_IO3, SAI4_MCLK_B, ETH_MII_RX_CLK/ET H_RMII_REF_CLK, OCTOSPIM_P1_DQS, LCD_R2, EVENTOUT - PA1_C ANA TT_a - - DS13312 Rev 3 69/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) V9 R2 43 PA2 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS N1 I/O FT_ha Additional functions 39 WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS H3 Alternate functions 27 Notes 19 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, OCTOSPIM_P1_IO0, USART2_TX(boot), SAI4_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC12_INP14, WKUP2 ADC3_INP13 - - - - - N2 N4 - PH2 I/O FT_ha - LPTIM1_IN2, OCTOSPIM_P1_IO4, SAI4_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - - - - AA10 - - 44 VDD S - - - - - - - - - - - 45 VSS S - - - - ADC3_INN13, ADC3_INP14 - - - - - M3 R4 - PH3 I/O FT_ha - OCTOSPIM_P1_IO5, SAI4_MCLK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT - - - - - - P4 - PH4 I/O FT_fa - I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, PSSI_D14, LCD_G4, EVENTOUT ADC3_INN14, ADC3_INP15 I/O FT_fh a - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT ADC3_INN15, ADC3_INP16 - 70/284 - - - - - R5 - PH5 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PA3 I/O FT_ha - ADC12_INP15 21 29 - 41 - - - 47 VSS S - - - - 22 30 - 42 - - - 48 VDD S - - - - - D1PWREN, TIM5_ETR, SPI1_NSS(boot)/I2S1 _WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS/I2S6_WS, FMC_D8/FMC_AD8, DCMI_HSYNC/PSSI_ DE, LCD_VSYNC, EVENTOUT ADC12_INP18, DAC1_OUT1 - D2PWREN, TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK(boot)/I2S1 ADC12_INN18, _CK, ADC12_INP19, SPI6_SCK/I2S6_CK, DAC1_OUT2 OTG_HS_ULPI_CK, FMC_D9/FMC_AD9, PSSI_D14, LCD_R4, EVENTOUT 23 24 31 32 K1 K2 43 44 Y9 U8 H6 L4 P5 P6 49 50 PA4 PA5 Pin type I/O structure 46 LQFP176 SMPS N5 UFBGA176+25 SMPS N3 UFBGA169 SMPS P7 WLCSP115 SMPS 40 LQFP144 SMPS G5 TFBGA100 SMPS 28 LQFP100 SMPS 20 TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, I2S6_MCK, OCTOSPIM_P1_IO2, USART2_RX(boot), LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, OCTOSPIM_P1_CLK, LCD_B5, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O I/O TT_ha TT_ha DS13312 Rev 3 71/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) 35 72/284 H4 46 47 T7 R6 W8 K5 J6 K6 R7 N6 R6 51 52 53 PA6 PA7 PC4 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS K3 45 I/O I/O I/O FT_ha TT_ha TT_ha DS13312 Rev 3 Additional functions 27 34 J3 Alternate functions 26 33 Notes 25 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO(boot)/I2S1 _SDI, OCTOSPIM_P1_IO3, SPI6_MISO/I2S6_SDI, TIM13_CH1, TIM8_BKIN_COMP12, MDIOS_MDC, TIM1_BKIN_COMP12, DCMI_PIXCLK/PSSI_ PDCK, LCD_G2, EVENTOUT ADC12_INP3 - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI(boot)/I2S1 _SDO, ADC12_INN3, SPI6_MOSI/I2S6_SD ADC12_INP7, O, TIM14_CH1, OCTOSPIM_P1_IO2, OPAMP1_VINM ETH_MII_RX_DV/ETH _RMII_CRS_DV, FMC_SDNWE, LCD_VSYNC, EVENTOUT - PWR_DEEPSLEEP, FMC_A22, DFSDM1_CKIN2, I2S1_MCK, SPDIFRX1_IN3, SDMMC2_CKIN, ETH_MII_RXD0/ETH_ RMII_RXD0, FMC_SDNE0, LCD_R7, EVENTOUT ADC12_INP4, OPAMP1_ VOUT, COMP1_INM STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Additional functions Alternate functions Notes I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number PWR_SLEEP, SAI4_D3, SAI1_D3, DFSDM1_DATIN2, PSSI_D15, ADC12_INN4, SPDIFRX1_IN4, OCTOSPIM_P1_DQS, ADC12_INP8, ETH_MII_RXD1/ETH_ OPAMP1_VINM RMII_RXD1, FMC_SDCKE0, COMP1_OUT, LCD_DE, EVENTOUT 28 36 J4 48 AA8 N5 M7 54 PC5 I/O TT_ha - - - - - V7 - - - VSS S - - - - - - - - Y7 - - - VDD S - - - - - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, OCTOSPIM_P1_IO1, DFSDM1_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC12_INN5, ADC12_INP9, OPAMP1_VINP, COMP1_INP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OCTOSPIM_P1_IO0, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC12_INP5, COMP1_INM 29 30 37 38 K4 K5 49 50 U6 W6 M5 L5 R8 M8 55 56 PB0 PB1 I/O I/O TT_ha FT_ha DS13312 Rev 3 73/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) AA6 P7 57 PB2 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS L6 I/O FT_ha Additional functions 51 WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS J5 Alternate functions 39 Notes 31 LQFP100 SMPS VFQFPN68 SMPS Pin number - RTC_OUT, SAI4_D1, SAI1_D1, DFSDM1_CKIN1, SAI1_SD_A, SPI3_MOSI/I2S3_SD O, SAI4_SD_A, OCTOSPIM_P1_CLK, OCTOSPIM_P1_DQS, ETH_TX_ER, TIM23_ETR, EVENTOUT COMP1_INP ADC1_INP2 - - - 52 - M6 N7 58 PF11 I/O FT_ha - SPI5_MOSI, OCTOSPIM_P1_NCL K, SAI4_SD_B, FMC_NRAS, DCMI_D12/PSSI_D12, TIM24_CH1, EVENTOUT - - - - - N6 P11 59 PF12 I/O FT_ha - OCTOSPIM_P2_DQS, FMC_A6, TIM24_CH2, EVENTOUT ADC1_INN2, ADC1_INP6 - - - - - G7 N11 60 PF13 I/O FT_ha - DFSDM1_DATIN6, I2C4_SMBA, FMC_A7, TIM24_CH3, EVENTOUT ADC2_INP2 - DFSDM1_CKIN6, I2C4_SCL, FMC_A8, TIM24_CH4, EVENTOUT ADC2_INN2, ADC2_INP6 - I2C4_SDA, FMC_A9, EVENTOUT - - - - - 53 - H7 R10 61 PF14 I/O FT_fh a - - - 54 - J7 N10 62 PF15 I/O FT_fh - - - - - K7 P8 63 PG0 I/O FT_h - OCTOSPIM_P2_IO4, UART9_RX, FMC_A10, EVENTOUT - - - 55 - - - 64 VSS S - - - - - - - 56 - - - 65 VDD S - - - - 74/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) UFBGA176+25 SMPS LQFP176 SMPS L7 N9 66 - - 40 41 H5 J6 57 58 N6 V5 G8 H8 P9 N8 67 68 Additional functions UFBGA169 SMPS - Alternate functions WLCSP115 SMPS - Notes LQFP144 SMPS - I/O structure TFBGA100 SMPS - Pin type LQFP100 SMPS - Pin name (function after reset) VFQFPN68 SMPS Pin number PG1 I/O TT_h - OCTOSPIM_P2_IO5, UART9_TX, FMC_A11, EVENTOUT OPAMP2_VINM PE7 PE8 I/O I/O TT_ha TT_ha - TIM1_ETR, DFSDM1_DATIN2, UART7_RX, OCTOSPIM_P1_IO4, FMC_D4/FMC_AD4, EVENTOUT OPAMP2_ VOUT, COMP2_INM - TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, OCTOSPIM_P1_IO5, FMC_D5/FMC_AD5, COMP2_OUT, EVENTOUT OPAMP2_VINM TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_ OPAMP2_VINP, DE, COMP2_INP OCTOSPIM_P1_IO6, FMC_D6/FMC_AD6, EVENTOUT - - K6 59 - J8 R11 69 PE9 I/O TT_ha - - - - - Y5 - - 70 VSS S - - - - - - - - AA4 - - 71 VDD S - - - - - TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, OCTOSPIM_P1_IO7, FMC_D7/FMC_AD7, EVENTOUT COMP2_INM - TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS(boot), SAI4_SD_B, OCTOSPIM_P1_NCS, FMC_D8/FMC_AD8, LCD_G3, EVENTOUT COMP2_INP - - - - H6 - 60 61 - - M8 N8 R9 R12 72 73 PE10 PE11 I/O I/O FT_ha FT_ha DS13312 Rev 3 75/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) - - - - 32 - 42 76/284 - - - K7 63 64 65 66 - - - - T5 L8 K8 J9 N9 L9 P12 P13 M12 P14 N12 74 75 76 77 78 PE12 PE13 PE14 PE15 PB10 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS 62 I/O I/O I/O I/O I/O FT_h FT_h FT_h FT_h FT_fh DS13312 Rev 3 Additional functions - - Alternate functions - Notes - TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK(boot), SAI4_SCK_B, FMC_D9/FMC_AD9, COMP1_OUT, LCD_B4, EVENTOUT - - TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO(boot), SAI4_FS_B, FMC_D10/FMC_AD10 , COMP2_OUT, LCD_DE, EVENTOUT - - TIM1_CH4, SPI4_MOSI(boot), SAI4_MCLK_B, FMC_D11/FMC_AD11, LCD_CLK, EVENTOUT - - TIM1_BKIN, USART10_CK, FMC_D12/FMC_AD12 , TIM1_BKIN_COMP12, LCD_R7, EVENTOUT - - TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX(boot), OCTOSPIM_P1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PB11 I/O FT_f - - 33 44 G6 68 Y3 N10 R13 80 VCAP S - - - - 34 45 - 69 AA2 - - 81 VSS S - - - - - 46 F7 70 W2 M10 R14 82 VDDLDO S - - - - 35 47 - 71 Y1 - - - VDD S - - - - - TIM12_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8/PSSI_D8, EVENTOUT - - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9/PSSI_D9, EVENTOUT - - TIM5_ETR, I2C3_SDA, FMC_D16, DCMI_HSYNC/PSSI_ DE, LCD_R2, EVENTOUT - - TIM12_CH2, I2C3_SMBA, FMC_D17, DCMI_D0/PSSI_D0, LCD_R3, EVENTOUT - - - - - - - - - - - - - - - - - - - - - - - - - P15 M11 N13 M14 - - - - PH6 PH7 PH8 PH9 Pin type I/O structure 79 LQFP176 SMPS P10 UFBGA176+25 SMPS M9 UFBGA169 SMPS W4 WLCSP115 SMPS 67 LQFP144 SMPS J7 TFBGA100 SMPS 43 LQFP100 SMPS - TIM2_CH4, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX(boot), OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH _RMII_TX_EN, LCD_G5, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O I/O I/O I/O FT_h FT_fh FT_fh FT_h DS13312 Rev 3 77/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PH10 I/O FT_h - - - - - - - L10 M13 - PH11 I/O FT_fh - TIM5_CH2, I2C4_SCL, FMC_D19, DCMI_D2/PSSI_D2, LCD_R5, EVENTOUT - - - - - - - - 83 VSS S - - - - - - - - Y1 - - 84 VDD S - - - - - TIM5_CH3, I2C4_SDA, FMC_D20, DCMI_D3/PSSI_D3, LCD_R6, EVENTOUT - - TIM1_BKIN, OCTOSPIM_P1_NCL K, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_ RMII_TXD0, OCTOSPIM_P1_IO0, TIM1_BKIN_COMP12, UART5_RX, EVENTOUT - - 36 - 48 78/284 - K8 - 72 - U4 K10 N15 N12 M15 - 85 PH12 PB12 Pin type I/O structure - LQFP176 SMPS N14 UFBGA176+25 SMPS K9 UFBGA169 SMPS - WLCSP115 SMPS - LQFP144 SMPS - TFBGA100 SMPS - LQFP100 SMPS - TIM5_CH1, I2C4_SMBA, FMC_D18, DCMI_D1/PSSI_D1, LCD_R4, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O I/O FT_fh FT_h DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) 51 K10 74 75 P5 R4 V3 L11 N13 M13 L15 K15 K14 86 87 88 PB13 PB14 PB15 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS K9 73 I/O I/O I/O FT_h FT_h FT_h DS13312 Rev 3 Additional functions 39 50 J8 Alternate functions 38 49 Notes 37 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM1_CH1N, LPTIM2_OUT, OCTOSPIM_P1_IO2, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART 3_NSS, FDCAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_ RMII_TXD1, SDMMC1_D0, DCMI_D2/PSSI_D2, UART5_TX, EVENTOUT - - TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART 3_DE, UART4_RTS/UART4_ DE, SDMMC2_D0, FMC_D10/FMC_AD10 , LCD_CLK, EVENTOUT - - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SD O, DFSDM1_CKIN2, UART4_CTS, SDMMC2_D1, FMC_D11/FMC_AD11, LCD_G7, EVENTOUT - 79/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PD8 I/O FT_h - - - 53 H8 77 N4 K11 K13 90 PD9 I/O FT_h - DFSDM1_DATIN3, USART3_RX(boot), FMC_D14/FMC_AD14 , EVENTOUT - - Pin type I/O structure 89 LQFP176 SMPS L14 UFBGA176+25 SMPS M12 UFBGA169 SMPS T3 WLCSP115 SMPS 76 LQFP144 SMPS J9 TFBGA100 SMPS 52 LQFP100 SMPS - DFSDM1_CKIN3, USART3_TX(boot), SPDIFRX1_IN2, FMC_D13/FMC_AD13 , EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number - 54 J10 78 P3 K12 L13 91 PD10 I/O FT_h - DFSDM1_CKOUT, USART3_CK, FMC_D15/FMC_AD15 , LCD_B3, EVENTOUT - - - 79 V1 - - 92 VDD S - - - - - - - 80 U2 - - 93 VSS S - - - - - LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART 3_NSS, OCTOSPIM_P1_IO0, SAI4_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, FDCAN3_RX, USART3_RTS/USART 3_DE, OCTOSPIM_P1_IO1, SAI4_FS_A, FMC_A17/FMC_ALE, DCMI_D12/PSSI_D12, EVENTOUT - - - 55 56 80/284 H7 H9 81 82 R2 T1 J10 K13 J13 J15 94 95 PD11 PD12 I/O I/O FT_h FT_fh DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PD13 I/O FT_fh - - - 58 - - - - - - VSS S - - - - - 59 - - - - - - VDD S - - - - - TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/FMC_AD0, EVENTOUT - - - 60 G7 84 L2 J13 H14 97 PD14 Pin type I/O structure 96 LQFP176 SMPS H15 UFBGA176+25 SMPS J11 UFBGA169 SMPS M3 WLCSP115 SMPS 83 LQFP144 SMPS H10 TFBGA100 SMPS 57 LQFP100 SMPS - LPTIM1_OUT, TIM4_CH2, I2C4_SDA, FDCAN3_TX, OCTOSPIM_P1_IO3, SAI4_SCK_A, UART9_RTS/UART9_ DE, FMC_A18, DCMI_D13/PSSI_D13, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O FT_h - 61 G8 85 N2 J12 J12 98 PD15 I/O FT_h - TIM4_CH4, UART8_RTS/UART8_ DE, UART9_TX, FMC_D1/FMC_AD1, EVENTOUT - - - - - - - 99 VDD S - - - - - - - - P1 - - 100 VSS S - - - - - - - - - - - - 101 PJ8 I/O FT - TIM1_CH3N, TIM8_CH1, UART8_TX, LCD_G1, EVENTOUT - - - - - - - 102 PJ9 I/O FT - TIM1_CH3, TIM8_CH1N, UART8_RX, LCD_G2, EVENTOUT - - TIM1_CH2N, TIM8_CH2, SPI5_MOSI, LCD_G3, EVENTOUT - - - - - - - - 103 PJ10 I/O DS13312 Rev 3 FT 81/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) VFQFPN68 SMPS LQFP100 SMPS TFBGA100 SMPS LQFP144 SMPS WLCSP115 SMPS UFBGA169 SMPS UFBGA176+25 SMPS LQFP176 SMPS Pin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions Pin number - - - - - - - 104 PJ11 I/O FT - TIM1_CH2, TIM8_CH2N, SPI5_MISO, LCD_G4, EVENTOUT - - - - - M1 - - 105 VDD S - - - - - - - - - - - 106 VSS S - - - - - - - - - - - - 107 PK0 I/O FT - TIM1_CH1N, TIM8_CH3, SPI5_SCK, LCD_G5, EVENTOUT - - - - - - - 108 PK1 I/O FT - TIM1_CH1, TIM8_CH3N, SPI5_NSS, LCD_G6, EVENTOUT - - TIM1_BKIN, TIM8_BKIN, TIM8_BKIN_COMP12, TIM1_BKIN_COMP12, LCD_G7, EVENTOUT - - TIM8_BKIN, TIM8_BKIN_COMP12, FMC_A12, TIM24_ETR, EVENTOUT - - - - - - - - - - - - - H9 - G15 109 110 PK2 PG2 I/O I/O FT FT_h - - - - - H10 H13 111 PG3 I/O FT_h - TIM8_BKIN2, TIM8_BKIN2_COMP1 2, FMC_A13, TIM23_ETR, EVENTOUT - - - - - - - 112 VSS S - - - - - - - - M1 - - 113 VDD S - - - - - TIM1_BKIN2, TIM1_BKIN2_COMP1 2, FMC_A14/FMC_BA0, EVENTOUT - - 82/284 - - - - F8 G14 114 PG4 I/O FT_h DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) UFBGA176+25 SMPS LQFP176 SMPS H11 F15 115 - - - - - - 86 87 - - G9 G10 F14 G13 116 117 Additional functions UFBGA169 SMPS - Alternate functions WLCSP115 SMPS - Notes LQFP144 SMPS - I/O structure TFBGA100 SMPS - Pin type LQFP100 SMPS - Pin name (function after reset) VFQFPN68 SMPS Pin number PG5 I/O FT_h - TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT - PG6 PG7 I/O I/O FT_h FT_h - TIM17_BKIN, OCTOSPIM_P1_NCS, FMC_NE3, DCMI_D12/PSSI_D12, LCD_R7, EVENTOUT - - SAI1_MCLK_A, USART6_CK, OCTOSPIM_P2_DQS, FMC_INT, DCMI_D13/PSSI_D13, LCD_CLK, EVENTOUT - - - - - 88 - G11 G12 118 PG8 I/O FT_h - TIM8_ETR, SPI6_NSS/I2S6_WS, USART6_RTS/USART 6_DE, SPDIFRX1_IN3, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT - - - 89 P1 - - 119 VSS S - - - - - - - 90 K1 G12 E15 120 VDD50 USB S - - - - - - E8 91 J2 G13 F13 121 VDD33 USB S - - - - - - - 92 - - - - VDD S - - - - DS13312 Rev 3 83/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) 64 84/284 G10 94 95 H1 K3 L4 F9 F10 F12 E14 D15 D14 122 123 124 PC6 PC7 PC8 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS G9 93 I/O I/O I/O FT_h FT_h FT_h DS13312 Rev 3 Additional functions - 63 F8 Alternate functions 41 62 Notes 40 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0/PSSI_D0, LCD_HSYNC, EVENTOUT SWPMI_IO - DBTRGIO, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, SWPMI_TX, SDMMC1_D7, DCMI_D1/PSSI_D1, LCD_G6, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_ DE, FMC_NE2/FMC_NCE, FMC_INT, SWPMI_RX, SDMMC1_D0, DCMI_D2/PSSI_D2, EVENTOUT - STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PC9 I/O FT_fh - - - - - - G2 - - - VSS S - - - - - - - - F1 - - 126 VDD S - - - - - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL(boot), I2C5_SCL, USART1_CK, OTG_HS_SOF, UART7_RX, TIM8_BKIN2_COMP1 2, LCD_B3, LCD_R6, EVENTOUT - - TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, I2C5_SMBA, USART1_TX(boot), ETH_TX_ER, DCMI_D0/PSSI_D0, LCD_R5, EVENTOUT OTG_HS_ VBUS - TIM1_CH3, LPUART1_RX, USART1_RX(boot), OTG_HS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1/PSSI_D1, LCD_B1, EVENTOUT - 43 44 45 66 67 68 F10 E9 E10 97 98 99 H3 J4 K5 E12 E11 E10 B14 D13 C14 127 128 129 PA8 PA9 PA10 Pin type I/O structure 125 LQFP176 SMPS E13 UFBGA176+25 SMPS F11 UFBGA169 SMPS M5 WLCSP115 SMPS 96 LQFP144 SMPS F9 TFBGA100 SMPS 65 LQFP100 SMPS 42 MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA(boot), I2S_CKIN, I2C5_SDA, UART5_CTS, OCTOSPIM_P1_IO0, LCD_G3, SWPMI_SUSPEND, SDMMC1_D1, DCMI_D3/PSSI_D3, LCD_B2, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O I/O I/O FT_fh FT_u FT_u DS13312 Rev 3 85/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) E2 C15 130 PA11 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS F13 I/O FT_u Additional functions 100 WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS D10 Alternate functions 69 Notes 46 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART 1_NSS, FDCAN1_RX, LCD_R4, EVENTOUT OTG_HS_DM (boot) OTG_HS_DP (boot) 47 70 D9 101 F3 E13 B15 131 PA12 I/O FT_u - TIM1_ETR, LPUART1_RTS/LPUA RT1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART 1_DE, SAI4_FS_B, FDCAN1_TX, TIM1_BKIN2, LCD_R5, EVENTOUT 48 71 C10 102 G4 D11 B13 132 PA13 (JTMS/ SWDIO) I/O FT - JTMS/SWDIO, EVENTOUT - 49 72 D8 103 D1 D13 A14 133 VCAP S - - - - 50 73 - 104 B1 - - 134 VSS S - - - - - 74 E6 105 C2 D12 A13 135 VDDLDO S - - - - 51 75 - 106 A2 - - 136 VDD S - - - - - 76 - - - - - - VDD33 USB S - - - - - TIM8_CH1N, UART4_TX, FDCAN1_TX(boot), FMC_D21, LCD_G2, EVENTOUT - - TIM8_CH2N, UART4_RX, FDCAN1_RX(boot), FMC_D22, DCMI_D4/PSSI_D4, LCD_G3, EVENTOUT - - - 86/284 - - - - - - - - B13 A13 C13 B12 - - PH13 PH14 I/O I/O FT_h FT_h DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) VFQFPN68 SMPS LQFP100 SMPS TFBGA100 SMPS LQFP144 SMPS WLCSP115 SMPS UFBGA169 SMPS UFBGA176+25 SMPS LQFP176 SMPS Pin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions Pin number - - - - - - D12 - PH15 I/O FT_h - TIM8_CH3N, FMC_D23, DCMI_D11/PSSI_D11, LCD_G4, EVENTOUT - - - - - - - - 137 VSS S - - - - - - - - A2 - - - VDD S - - - - 52 77 C9 107 D3 B12 A12 I/O FT - JTCK/SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS(boot)/I2S3 _WS, SPI6_NSS/I2S6_WS, UART4_RTS/UART4_ DE, LCD_R3, UART7_TX, LCD_B6, EVENTOUT - - DFSDM1_CKIN5, I2C5_SDA, SPI3_SCK(boot)/I2S3 _CK, USART3_TX, UART4_TX, OCTOSPIM_P1_IO1, LCD_B1, SWPMI_RX, SDMMC1_D2, DCMI_D8/PSSI_D8, LCD_R2, EVENTOUT - - DFSDM1_DATIN5, I2C5_SCL, SPI3_MISO(boot)/I2S3 _SDI, USART3_RX, UART4_RX, OCTOSPIM_P1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4, LCD_B4, EVENTOUT - 53 54 55 78 79 80 C8 B10 B9 108 109 110 H5 E4 L6 C11 A12 B11 A11 C12 C11 PA14 138 (JTCK/SW CLK) 139 PA15(JTDI) 140 141 PC10 PC11 I/O I/O I/O FT FT_fh FT_fh DS13312 Rev 3 87/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PC12 I/O FT_h - - - - - - B3 - - - VDD S - - - - - - - - C4 - - - VSS S - - - - - DFSDM1_CKIN6, UART4_RX, FDCAN1_RX(boot), UART9_CTS, FMC_D2/FMC_AD2, LCD_B1, EVENTOUT - - DFSDM1_DATIN6, UART4_TX, FDCAN1_TX(boot), FMC_D3/FMC_AD3, EVENTOUT - - TRACED2, FMC_D7/FMC_AD7, TIM3_ETR, TIM15_BKIN, UART5_RX, LCD_B7, SDMMC1_CMD, DCMI_D11/PSSI_D11, LCD_B2, EVENTOUT - - DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS/USART 2_NSS, FMC_CLK, DCMI_D5/PSSI_D5, LCD_G7, EVENTOUT - - - 57 - 82 83 84 85 88/284 C7 B8 A9 A8 112 113 114 115 J6 D5 A4 B5 D10 C10 E9 D9 C10 A10 B10 A9 143 144 145 146 PD0 PD1 PD2 PD3 Pin type I/O structure 142 LQFP176 SMPS B11 UFBGA176+25 SMPS A11 UFBGA169 SMPS F5 WLCSP115 SMPS 111 LQFP144 SMPS A10 TFBGA100 SMPS 81 LQFP100 SMPS 56 TRACED3, FMC_D6/FMC_AD6, TIM15_CH1, I2C5_SMBA, SPI6_SCK/I2S6_CK, SPI3_MOSI(boot)/I2S3 _SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9, LCD_R6, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O I/O I/O I/O FT_h FT_h FT_h FT_h DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PD4 I/O FT_h - - - 87 D7 117 E6 A9 B9 148 PD5 I/O FT_h - USART2_TX, OCTOSPIM_P1_IO5, FMC_NWE, EVENTOUT - - - - 118 - - - - VSS S - - - - - 88 - 119 - - - - VDD S - - - - - SAI4_D1, SAI1_D1, DFSDM1_CKIN4, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SD O, SAI1_SD_A, USART2_RX, SAI4_SD_A, OCTOSPIM_P1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10, LCD_B2, EVENTOUT - - - - A7 120 - B9 D9 149 PD6 Pin type I/O structure 147 LQFP176 SMPS C9 UFBGA176+25 SMPS C9 UFBGA169 SMPS G6 WLCSP115 SMPS 116 LQFP144 SMPS B7 TFBGA100 SMPS 86 LQFP100 SMPS - USART2_RTS/USART 2_DE, OCTOSPIM_P1_IO4, FMC_NOE, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number I/O FT_h - - C6 121 - D8 B8 150 PD7 I/O FT_h - DFSDM1_DATIN4, SPI1_MOSI/I2S1_SD O, DFSDM1_CKIN1, USART2_CK, SPDIFRX1_IN1, OCTOSPIM_P1_IO7, SDMMC2_CMD, FMC_NE1, EVENTOUT - - - - C6 - - 151 VSS S - - - - - - - - A6 - - 152 VDD S - - - - DS13312 Rev 3 89/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) 90/284 - - - 123 124 - - - C8 A8 B8 A8 C8 A7 153 154 155 PG9 PG10 PG11 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS 122 I/O I/O I/O FT_h FT_h FT_h DS13312 Rev 3 Additional functions - - - Alternate functions - - Notes - TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number - FDCAN3_TX, SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX1_IN4, OCTOSPIM_P1_IO6, SAI4_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC/PSSI_ RDY, EVENTOUT - - FDCAN3_RX, OCTOSPIM_P2_IO6, SPI1_NSS/I2S1_WS, LCD_G3, SAI4_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2, LCD_B2, EVENTOUT - - LPTIM1_IN2, USART10_RX, SPI1_SCK/I2S1_CK, SPDIFRX1_IN1, OCTOSPIM_P2_IO7, SDMMC2_D2, ETH_MII_TX_EN/ETH _RMII_TX_EN, DCMI_D3/PSSI_D3, LCD_B3, EVENTOUT - STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) 126 - - E8 D7 D8 B7 156 157 PG12 PG13 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS - 125 I/O I/O FT_h FT_h Additional functions - - Alternate functions - - Notes - LQFP100 SMPS VFQFPN68 SMPS Pin number - LPTIM1_IN1, OCTOSPIM_P2_NCS, USART10_TX, SPI6_MISO/I2S6_SDI, USART6_RTS/USART 6_DE, SPDIFRX1_IN2, LCD_B4, SDMMC2_D3, ETH_MII_TXD1/ETH_ RMII_TXD1, FMC_NE4, TIM23_CH1, LCD_B1, EVENTOUT - - TRACED0, LPTIM1_OUT, USART10_CTS/USAR T10_NSS, SPI6_SCK/I2S6_CK, USART6_CTS/USART 6_NSS, SDMMC2_D6, ETH_MII_TXD0/ETH_ RMII_TXD0, FMC_A24, TIM23_CH2, LCD_R0, EVENTOUT - - - - - 127 - C7 C7 158 PG14 I/O FT_h - TRACED1, LPTIM1_ETR, USART10_RTS/USAR T10_DE, SPI6_MOSI/I2S6_SD O, USART6_TX, OCTOSPIM_P1_IO7, SDMMC2_D7, ETH_MII_TXD1/ETH_ RMII_TXD1, FMC_A25, TIM23_CH3, LCD_B0, EVENTOUT - - - 128 - - - 159 VSS S - - - - - - - 129 A6 - - 160 VDD S - - - - DS13312 Rev 3 91/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) 60 90 91 92/284 B6 C5 A6 130 131 132 - H7 F7 D7 E7 F7 B6 C6 D7 A6 B6 C6 161 162 163 164 PG15 PB3(JTDO/ TRACES WO) PB4 (NJTRST) PB5 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS - I/O I/O I/O I/O FT_h FT_h FT_h FT_h DS13312 Rev 3 Additional functions 59 89 - Alternate functions 58 - Notes - TFBGA100 SMPS LQFP100 SMPS VFQFPN68 SMPS Pin number - USART6_CTS/USART 6_NSS, OCTOSPIM_P2_DQS, USART10_CK, FMC_NCAS, DCMI_D13/PSSI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK/I2S6_CK, SDMMC2_D2, CRS_SYNC, UART7_RX, TIM24_ETR, EVENTOUT - - NJTRST, TIM16_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO/I2S6_SDI, SDMMC2_D3, UART7_TX, EVENTOUT - - TIM17_BKIN, TIM3_CH2, LCD_B5, I2C1_SMBA, SPI1_MOSI/I2S1_SD O, I2C4_SMBA, SPI3_MOSI/I2S3_SD O, SPI6_MOSI/I2S6_SD O, FDCAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10/PSSI_D10, UART5_RX, EVENTOUT - STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) Alternate functions Additional functions PB6 I/O FT_fh - - - - - - B7 - - - VSS S - - - - - - - - A8 - - - VDD S - - - - PVD_IN Pin type I/O structure 165 LQFP176 SMPS A5 UFBGA176+25 SMPS A5 UFBGA169 SMPS K7 WLCSP115 SMPS 133 LQFP144 SMPS D4 TFBGA100 SMPS 92 LQFP100 SMPS 61 TIM16_CH1N, TIM4_CH1, I2C1_SCL(boot), CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPIM_P1_NCS, DFSDM1_DATIN5, FMC_SDNE1, DCMI_D5/PSSI_D5, UART5_TX, EVENTOUT VFQFPN68 SMPS Notes Pin name (function after reset) Pin number 62 93 B5 134 M7 D6 B5 166 PB7 I/O FT_fa - TIM17_CH1N, TIM4_CH2, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC/PSSI_ RDY, EVENTOUT 63 94 A5 135 C8 E6 C5 167 BOOT0 I B - - VPP - TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6/PSSI_D6, LCD_B6, EVENTOUT - 64 95 A4 136 E8 B5 A2 168 PB8 I/O FT_fh DS13312 Rev 3 93/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) - 138 G8 J8 C5 D5 B3 B4 169 170 PB9 PE0 I/O structure Pin type Pin name (function after reset) LQFP176 SMPS UFBGA176+25 SMPS UFBGA169 SMPS WLCSP115 SMPS LQFP144 SMPS TFBGA100 SMPS B4 137 I/O I/O FT_fh FT_h Additional functions - E3 Alternate functions 96 Notes 65 LQFP100 SMPS VFQFPN68 SMPS Pin number - TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA(boot), SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7/PSSI_D7, LCD_B7, EVENTOUT - - LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, UART8_RX, SAI4_MCLK_A, FMC_NBL0, DCMI_D2/PSSI_D2, LCD_R0, EVENTOUT - - - - C4 139 - D4 C4 171 PE1 I/O FT_h - LPTIM1_IN2, UART8_TX, FMC_NBL1, DCMI_D3/PSSI_D3, LCD_R6, EVENTOUT 66 97 D8 140 B9 A4 A4 172 VCAP S - - - - 67 98 - 141 A10 - - 173 VSS S - - - - - - D3 142 L8 C4 D4 174 PDR_ON S - - - - - 99 E6 143 D9 B4 A3 175 VDDLDO S - - - - 68 100 - - C10 - - - VDD S - - - - - - - 144 C10 - - 176 VDD S - - - - - - C1 - - B3 A1 - VSS S - - - - - - D5 - - B7 A15 - VSS S - - - - - - E7 - - B10 C2 - VSS S - - - - 94/284 DS13312 Rev 3 STM32H735xG Pinouts, pin descriptions and alternate functions Table 8. STM32H735xG pin and ball descriptions (continued) VFQFPN68 SMPS LQFP100 SMPS TFBGA100 SMPS LQFP144 SMPS WLCSP115 SMPS UFBGA169 SMPS UFBGA176+25 SMPS LQFP176 SMPS Pin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions Pin number - - F5 - - C12 D10 - VSS S - - - - - - - - - D2 D6 - VSS S - - - - - - - - - G2 E1 - VSS S - - - - - - - - - H12 F10 - VSS S - - - - - - - - - L12 F12 - VSS S - - - - - - - - - M2 F6 - VSS S - - - - - - - - - M4 F7 - VSS S - - - - - - - - - M7 F8 - VSS S - - - - - - - - - M11 F9 - VSS S - - - - - - - - - - G10 - VSS S - - - - - - - - - - G6 - VSS S - - - - - - - - - - G7 - VSS S - - - - - - - - - - G8 - VSS S - - - - - - - - - - G9 - VSS S - - - - - - - - - - H10 - VSS S - - - - - - - - - - H6 - VSS S - - - - - - - - - - H7 - VSS S - - - - - - - - - - H8 - VSS S - - - - - - - - - - H9 - VSS S - - - - - - - - - - J10 - VSS S - - - - - - - - - - J14 - VSS S - - - - - - - - - - J6 - VSS S - - - - - - - - - - J7 - VSS S - - - - - - - - - - J8 - VSS S - - - - - - - - - - J9 - VSS S - - - - - - - - - - K10 - VSS S - - - - - - - - - - K12 - VSS S - - - - DS13312 Rev 3 95/284 113 Pinouts, pin descriptions and alternate functions STM32H735xG Table 8. STM32H735xG pin and ball descriptions (continued) VFQFPN68 SMPS LQFP100 SMPS TFBGA100 SMPS LQFP144 SMPS WLCSP115 SMPS UFBGA169 SMPS UFBGA176+25 SMPS LQFP176 SMPS Pin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions Pin number - - - - - - K2 - VSS S - - - - - - - - - - K6 - VSS S - - - - - - - - - - K7 - VSS S - - - - - - - - - - K8 - VSS S - - - - - - - - - - K9 - VSS S - - - - - - - - - - M10 - VSS S - - - - - - - - - - M6 - VSS S - - - - - - - - - - R1 - VSS S - - - - - - - - - - R15 - VSS S - - - - - - D6 - - A3 D5 - VDD S - - - - - - E5 - - A6 D11 - VDD S - - - - - - F6 - - A7 E4 - VDD S - - - - - - - - - A10 E12 - VDD S - - - - - - - - - C13 G4 - VDD S - - - - - - - - - D1 H12 - VDD S - - - - - - - - - G1 K4 - VDD S - - - - - - - - - H13 L12 - VDD S - - - - - - - - - L13 M5 - VDD S - - - - - - - - - M1 M9 - VDD S - - - - - - - - - N4 - - VDD S - - - - - - - - - N7 - - VDD S - - - - - - - - - N11 - - VDD S - - - - 1. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 2. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 96/284 DS13312 Rev 3 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 - TIM2_C H1/TIM2 _ETR TIM5_C H1 TIM8_ET TIM15_B R KIN SPI6_NS S/I2S6_ WS PA1 - TIM2_C H2 TIM5_C H2 LPTIM3_ TIM15_C OUT H1N - PA2 - TIM2_C H3 TIM5_C H3 LPTIM4_ TIM15_C OUT H1 PA3 - TIM2_C H4 TIM5_C H4 LPTIM5_ TIM15_C OUT H2 PA4 D1PWREN - TIM5_ET R - - PA5 D2PWREN TIM2_C H1/TIM2 _ETR - TIM8_C H1N PA6 - TIM1_B KIN TIM3_C H1 TIM8_B KIN Port SYS PA0 DS13312 Rev 3 Port A AF11 AF12 AF13 AF14 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 FMC_A1 9 - - EVENTO UT ETH_MII _RX_CL OCTOS K/ETH_ PIM_P1_ RMII_RE DQS F_CLK - LCD_R2 EVENTO UT ETH_MD IO MDIOS_ MDIO - LCD_R1 EVENTO UT OTG_HS OCTOS ETH_MII _ULPI_D PIM_P1_ _COL 0 CLK - LCD_B5 EVENTO UT COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR M1x/TIM T5 23 AF15 SYS - USART2 _CTS/U SART2_ NSS UART4_ TX SDMMC 2_CMD SAI4_SD ETH_MII _B _CRS - USART2 _RTS/U SART2_ DE UART4_ RX OCTOS PIM_P1_ IO3 SAI4_M CLK_B - OCTOS USART2 PIM_P1_ _TX IO0 SAI4_SC K_B - - I2S6_M CK OCTOS USART2 PIM_P1_ _RX IO2 - LCD_B2 SPI1_NS SPI3_NS USART2 S/I2S1_ S/I2S3_ _CK WS WS SPI6_NS S/I2S6_ WS - - - FMC_D8 /FMC_A D8 DCMI_H SYNC/P SSI_DE LCD_VS YNC EVENTO UT - SPI1_SC K/I2S1_ CK - - SPI6_SC K/I2S6_ CK - OTG_HS _ULPI_C K - FMC_D9 PSSI_D1 /FMC_A 4 D9 LCD_R4 EVENTO UT - SPI1_MI SO/I2S1 _SDI OCTOS PIM_P1_ IO3 - SPI6_MI SO/I2S6 _SDI TIM13_C H1 TIM8_B KIN_CO MP12 MDIOS_ MDC DCMI_PI XCLK/P SSI_PD CK LCD_G2 EVENTO UT TIM1_B KIN_CO MP12 97/284 Pinouts, pin descriptions and alternate functions CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF10 STM32H735xG Table 9. STM32H735xG pin alternate functions AF0 Port SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 TIM3_C H2 TIM8_C H1N - SPI1_M OSI/I2S1 _SDO - - AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 ETH_MII SPI6_M OCTOS _RX_DV TIM14_C FMC_SD OSI/I2S6 PIM_P1_ /ETH_R H1 NWE _SDO IO2 MII_CRS _DV DS13312 Rev 3 - PA8 MCO1 TIM1_C H1 - TIM8_B KIN2 I2C3_SC L - I2C5_SC L USART1 _CK - - OTG_HS _SOF UART7_ RX PA9 - TIM1_C H2 - LPUART 1_TX I2C3_S MBA SPI2_SC K/I2S2_ CK I2C5_S MBA USART1 _TX - - - PA10 - TIM1_C H3 - LPUART 1_RX - - - USART1 _RX - - PA11 - TIM1_C H4 - LPUART 1_CTS - SPI2_NS S/I2S2_ WS UART4_ RX USART1 _CTS/U SART1_ NSS - PA12 - TIM1_ET R - LPUART 1_RTS/L PUART1 _DE - SPI2_SC K/I2S2_ CK UART4_ TX USART1 _RTS/U SART1_ DE PA13 JTMS/SWDIO - - - - - - PA14 JTCK/SWCLK - - - - - - PA15 JTDI TIM2_C H1/TIM2 _ETR - - CEC Port A AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - LCD_VS YNC EVENTO UT TIM8_B KIN2_C OMP12 LCD_B3 LCD_R6 EVENTO UT ETH_TX _ER - DCMI_D 0/PSSI_ D0 LCD_R5 EVENTO UT OTG_HS _ID MDIOS_ MDIO LCD_B4 DCMI_D 1/PSSI_ D1 LCD_B1 EVENTO UT FDCAN1 _RX - - - - LCD_R4 EVENTO UT SAI4_FS _B FDCAN1 _TX - - TIM1_B KIN2 - LCD_R5 EVENTO UT - - - - - - - - EVENTO UT - - - - - - - - EVENTO UT UART4_ RTS/UA RT4_DE LCD_R3 - UART7_ TX - - LCD_B6 EVENTO UT SPI1_NS SPI3_NS SPI6_NS S/I2S1_ S/I2S3_ S/I2S6_ WS WS WS STM32H735xG PA7 TIM1_C H1N AF13 Pinouts, pin descriptions and alternate functions 98/284 Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - TIM1_C H2N TIM3_C H3 TIM8_C H2N OCTOS PIM_P1_ IO1 - DFSDM1 _CKOUT - UART4_ CTS LCD_R3 OTG_HS ETH_MII _ULPI_D _RXD2 1 - - LCD_G1 EVENTO UT PB1 - TIM1_C H3N TIM3_C H4 TIM8_C H3N OCTOS PIM_P1_ IO0 - DFSDM1 _DATIN1 - - LCD_R6 OTG_HS ETH_MII _ULPI_D _RXD3 2 - - LCD_G0 EVENTO UT PB2 RTC_OUT SAI4_D1 SAI1_D1 - DFSDM1 _CKIN1 - SPI3_M OCTOS OCTOS SAI1_SD SAI4_SD OSI/I2S3 PIM_P1_ PIM_P1_ _A _A _SDO CLK DQS ETH_TX _ER - TIM23_E TR - EVENTO UT PB3 JTDO/TRACE SWO TIM2_C H2 - - - SPI1_SC SPI3_SC K/I2S1_ K/I2S3_ CK CK PB4 NJTRST TIM16_B KIN TIM3_C H1 - - SPI1_MI SO/I2S1 _SDI PB5 - TIM17_B KIN TIM3_C H2 LCD_B5 I2C1_S MBA PB6 - TIM16_C H1N TIM4_C H1 - PB7 - TIM17_C H1N TIM4_C H2 - PB8 - TIM16_C H1 PB9 - TIM17_C H1 99/284 - SPI6_SC K/I2S6_ CK SDMMC 2_D2 CRS_SY NC UART7_ RX - - SPI3_MI SO/I2S3 _SDI SPI2_NS S/I2S2_ WS SPI6_MI SO/I2S6 _SDI SDMMC 2_D3 - UART7_ TX - - - EVENTO UT SPI1_M OSI/I2S1 _SDO I2C4_S MBA SPI3_M SPI6_M OTG_HS FDCAN2 OSI/I2S3 OSI/I2S6 _ULPI_D _RX _SDO _SDO 7 ETH_PP S_OUT FMC_SD CKE1 DCMI_D 10/PSSI _D10 UART5_ RX EVENTO UT I2C1_SC L CEC I2C4_SC L USART1 _TX LPUART 1_TX OCTOS FDCAN2 DFSDM1 FMC_SD PIM_P1_ _TX _DATIN5 NE1 NCS DCMI_D 5/PSSI_ D5 UART5_ TX EVENTO UT I2C1_SD A - I2C4_SD A USART1 _RX LPUART 1_RX - - DFSDM1 FMC_NL _CKIN5 DCMI_V SYNC/P SSI_RD Y - EVENTO UT TIM4_C H3 DFSDM1 I2C1_SC _CKIN7 L - I2C4_SC L SDMMC 1_CKIN UART4_ RX FDCAN1 _RX SDMMC 2_D4 ETH_MII _TXD3 SDMMC 1_D4 DCMI_D 6/PSSI_ D6 LCD_B6 EVENTO UT TIM4_C H4 DFSDM1 I2C1_SD _DATIN7 A SPI2_NS I2C4_SD S/I2S2_ A WS SDMMC 1_CDIR UART4_ TX FDCAN1 _TX SDMMC 2_D5 I2C4_S MBA SDMMC 1_D5 DCMI_D 7/PSSI_ D7 LCD_B7 EVENTO UT TIM24_E EVENTO TR UT Pinouts, pin descriptions and alternate functions DS13312 Rev 3 PB0 Port B STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 - TIM2_C H3 PB11 Port SYS - LPTIM2_ I2C2_SC IN1 L SPI2_SC DFSDM1 USART3 K/I2S2_ _DATIN7 _TX CK - TIM2_C H4 - LPTIM2_ I2C2_SD ETR A PB12 - TIM1_B KIN - OCTOS PIM_P1_ NCLK PB13 - TIM1_C H1N - OCTOS SPI2_SC DFSDM1 LPTIM2_ PIM_P1_ K/I2S2_ _CKIN1 OUT IO2 CK PB14 - TIM1_C H2N TIM12_C H1 TIM8_C H2N USART1 _TX SPI2_MI SO/I2S2 _SDI PB15 RTC_REFIN TIM1_C H3N TIM12_C H2 TIM8_C H3N USART1 _RX SPI2_M DFSDM1 OSI/I2S2 _CKIN2 _SDO PB10 DS13312 Rev 3 Port B I2C2_S MBA AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - OCTOS OTG_HS ETH_MII PIM_P1_ _ULPI_D _RX_ER NCS 3 - - LCD_G4 EVENTO UT DFSDM1 USART3 _CKIN7 _RX - ETH_MII OTG_HS _TX_EN/ _ULPI_D ETH_RM 4 II_TX_E N - - LCD_G5 EVENTO UT SPI2_NS DFSDM1 USART3 S/I2S2_ _DATIN1 _CK WS - ETH_MII OTG_HS OCTOS FDCAN2 _TXD0/E _ULPI_D PIM_P1_ _RX TH_RMII 5 IO0 _TXD0 TIM1_B KIN_CO MP12 UART5_ RX EVENTO UT USART3 _CTS/U SART3_ NSS - ETH_MII OTG_HS FDCAN2 _TXD1/E _ULPI_D _TX TH_RMII 6 _TXD1 SDMMC 1_D0 DCMI_D 2/PSSI_ D2 UART5_ TX EVENTO UT USART3 _RTS/U SART3_ DE UART4_ RTS/UA RT4_DE SDMMC 2_D0 - - FMC_D1 0/FMC_ AD10 - LCD_CL K EVENTO UT - UART4_ CTS SDMMC 2_D1 - - FMC_D1 1/FMC_ AD11 - LCD_G7 EVENTO UT - DFSDM1 _DATIN2 - Pinouts, pin descriptions and alternate functions 100/284 Table 9. STM32H735xG pin alternate functions (continued) STM32H735xG AF0 Port SYS AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 PC0 - FMC_D1 2/FMC_ AD12 - PC1 TRACED0 SAI4_D1 SAI1_D1 PC2 PWR_DEEPS LEEP - PC3 PWR_SLEEP PC4 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS 101/284 DFSDM1 _DATIN4 - SAI4_FS _B FMC_A2 5 OTG_HS _ULPI_S TP LCD_G2 FMC_SD NWE - LCD_R5 EVENTO UT SPI2_M DFSDM1 DFSDM1 SAI1_SD OSI/I2S2 _DATIN0 _CKIN4 _A _SDO - SAI4_SD _A SDMMC 2_CK OCTOS ETH_MD PIM_P1_ C IO4 MDIOS_ MDC - LCD_G5 EVENTO UT - OCTOS DFSDM1 PIM_P1_ _CKIN1 IO5 DFSDM1 _CKOUT - - OCTOS OTG_HS ETH_MII FMC_SD PIM_P1_ _ULPI_D _TXD2 NE0 IO2 IR - - EVENTO UT - - OCTOS SPI2_M DFSDM1 PIM_P1_ OSI/I2S2 _DATIN1 IO6 _SDO - - - OCTOS OTG_HS ETH_MII FMC_SD PIM_P1_ _ULPI_N _TX_CL CKE0 IO0 XT K - - EVENTO UT PWR_DEEPS LEEP FMC_A2 2 - DFSDM1 _CKIN2 I2S1_M CK - - - SPDIFR X1_IN3 SDMMC 2_CKIN ETH_MII _RXD0/ FMC_SD ETH_RM NE0 II_RXD0 - LCD_R7 EVENTO UT PC5 PWR_SLEEP SAI4_D3 SAI1_D3 DFSDM1 PSSI_D1 _DATIN2 5 - - - - SPDIFR X1_IN4 ETH_MII OCTOS _RXD1/ FMC_SD COMP1_ LCD_DE PIM_P1_ ETH_RM CKE0 OUT DQS II_RXD1 EVENTO UT PC6 - - TIM3_C H1 TIM8_C H1 DFSDM1 _CKIN3 I2S2_M CK - USART6 _TX SDMMC 1_D0DIR FMC_N WAIT SDMMC 2_D6 - SDMMC 1_D6 DCMI_D 0/PSSI_ D0 LCD_HS YNC EVENTO UT PC7 DBTRGIO - TIM3_C H2 TIM8_C H2 DFSDM1 _DATIN3 - I2S3_M CK USART6 _RX SDMMC 1_D123 DIR FMC_NE 1 SDMMC 2_D7 SWPMI_ TX SDMMC 1_D7 DCMI_D 1/PSSI_ D1 LCD_G6 EVENTO UT PC8 TRACED1 - TIM3_C H3 TIM8_C H3 - - - USART6 _CK UART5_ RTS/UA RT5_DE FMC_NE 2/FMC_ NCE FMC_IN T SWPMI_ RX SDMMC 1_D0 DCMI_D 2/PSSI_ D2 - EVENTO UT DFSDM1 _CKIN0 - - - SPI2_MI SO/I2S2 _SDI Pinouts, pin descriptions and alternate functions DS13312 Rev 3 Port C AF1 STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF10 AF11 AF12 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 UART5_ CTS OCTOS PIM_P1_ IO0 LCD_G3 SWPMI_ SUSPEN D SDMMC 1_D1 DCMI_D 3/PSSI_ D3 LCD_B2 EVENTO UT I2S_CKI N I2C5_SD A AF7 AF8 AF9 AF13 AF14 AF15 SYS DS13312 Rev 3 MCO2 - TIM3_C H4 PC10 - - - DFSDM1 I2C5_SD _CKIN5 A - SPI3_SC USART3 K/I2S3_ _TX CK UART4_ TX OCTOS PIM_P1_ IO1 LCD_B1 SWPMI_ RX SDMMC 1_D2 DCMI_D 8/PSSI_ D8 LCD_R2 EVENTO UT PC11 - - - DFSDM1 I2C5_SC _DATIN5 L - SPI3_MI SO/I2S3 _SDI USART3 _RX UART4_ RX OCTOS PIM_P1_ NCS - - SDMMC 1_D3 DCMI_D 4/PSSI_ D4 LCD_B4 EVENTO UT PC12 TRACED3 SPI6_SC SPI3_M K/I2S6_ OSI/I2S3 CK _SDO USART3 _CK UART5_ TX - - - SDMMC 1_CK DCMI_D 9/PSSI_ D9 LCD_R6 EVENTO UT PC13 - - PC14 - PC15 - FMC_D6 TIM15_C /FMC_A H1 D6 I2C3_SD A AF6 PC9 Port C TIM8_C H4 AF5 - - I2C5_S MBA - - - - - - - - - - - - - EVENTO UT - - - - - - - - - - - - - - EVENTO UT - - - - - - - - - - - - - - EVENTO UT Pinouts, pin descriptions and alternate functions 102/284 Table 9. STM32H735xG pin alternate functions (continued) STM32H735xG AF0 Port SYS AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS 103/284 PD0 - - - DFSDM1 _CKIN6 - - - - UART4_ RX FDCAN1 _RX - UART9_ CTS FMC_D2 /FMC_A D2 - LCD_B1 EVENTO UT PD1 - - - DFSDM1 _DATIN6 - - - - UART4_ TX FDCAN1 _TX - - FMC_D3 /FMC_A D3 - - EVENTO UT PD2 TRACED2 - TIM15_B KIN - - - UART5_ RX LCD_B7 - - SDMMC 1_CMD DCMI_D 11/PSSI_ D11 LCD_B2 EVENTO UT PD3 - - - DFSDM1 _CKOUT - SPI2_SC K/I2S2_ CK - USART2 _CTS/U SART2_ NSS - - - - FMC_CL K DCMI_D 5/PSSI_ D5 LCD_G7 EVENTO UT PD4 - - - - - - - USART2 _RTS/U SART2_ DE - - OCTOS PIM_P1_ IO4 - FMC_N OE - - EVENTO UT PD5 - - - - - - - USART2 _TX - - OCTOS PIM_P1_ IO5 - FMC_N WE - - EVENTO UT PD6 - SAI4_D1 SAI1_D1 SAI4_SD _A - OCTOS PIM_P1_ IO6 SDMMC 2_CK FMC_N WAIT DCMI_D 10/PSSI _D10 LCD_B2 EVENTO UT PD7 - - - DFSDM1 _DATIN4 - SPI1_M DFSDM1 USART2 OSI/I2S1 _CKIN1 _CK _SDO - SPDIFR X1_IN1 OCTOS PIM_P1_ IO7 SDMMC 2_CMD FMC_NE 1 - - EVENTO UT PD8 - - - DFSDM1 _CKIN3 - USART3 _TX - SPDIFR X1_IN2 - - FMC_D1 3/FMC_ AD13 - - EVENTO UT FMC_D7 TIM3_ET /FMC_A R D7 SPI3_M DFSDM1 DFSDM1 SAI1_SD USART2 OSI/I2S3 _CKIN4 _DATIN1 _A _RX _SDO - - Pinouts, pin descriptions and alternate functions DS13312 Rev 3 Port D AF1 STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS DS13312 Rev 3 Port D AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS PD9 - - - DFSDM1 _DATIN3 - - - USART3 _RX - - - - FMC_D1 4/FMC_ AD14 - - EVENTO UT PD10 - - - DFSDM1 _CKOUT - - - USART3 _CK - - - - FMC_D1 5/FMC_ AD15 - LCD_B3 EVENTO UT PD11 - - - LPTIM2_ IN2 I2C4_S MBA - - USART3 _CTS/U SART3_ NSS - OCTOS SAI4_SD PIM_P1_ _A IO0 - FMC_A1 6/FMC_ CLE - - EVENTO UT PD12 - LPTIM1_ IN1 TIM4_C H1 LPTIM2_ I2C4_SC FDCAN3 IN1 L _RX - USART3 _RTS/U SART3_ DE - OCTOS SAI4_FS PIM_P1_ _A IO1 - FMC_A1 7/FMC_ ALE DCMI_D 12/PSSI _D12 - EVENTO UT PD13 - LPTIM1_ OUT TIM4_C H2 - I2C4_SD FDCAN3 A _TX - - - OCTOS SAI4_SC PIM_P1_ K_A IO3 UART9_ RTS/UA RT9_DE FMC_A1 8 DCMI_D 13/PSSI _D13 - EVENTO UT PD14 - - TIM4_C H3 - - - - - UART8_ CTS - - UART9_ RX FMC_D0 /FMC_A D0 - - EVENTO UT PD15 - - TIM4_C H4 - - - - - UART8_ RTS/UA RT8_DE - - UART9_ TX FMC_D1 /FMC_A D1 - - EVENTO UT Pinouts, pin descriptions and alternate functions 104/284 Table 9. STM32H735xG pin alternate functions (continued) STM32H735xG AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 AF13 AF14 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - LPTIM1_ TIM4_ET ETR R - LPTIM2_ ETR - - - UART8_ RX - SAI4_M CLK_A - FMC_NB L0 DCMI_D 2/PSSI_ D2 LCD_R0 EVENTO UT PE1 - LPTIM1_ IN2 - - - - - - UART8_ TX - - - FMC_NB L1 DCMI_D 3/PSSI_ D3 LCD_R6 EVENTO UT PE2 TRACECLK - SAI1_CK 1 - USART1 SPI4_SC 0_RX K SAI1_M CLK_A - SAI4_M CLK_A OCTOS SAI4_CK ETH_MII PIM_P1_ 1 _TXD3 IO2 FMC_A2 3 - - EVENTO UT PE3 TRACED0 - - - TIM15_B KIN SAI1_SD _B - SAI4_SD _B - - USART1 0_TX FMC_A1 9 - - EVENTO UT PE4 TRACED1 - SAI1_D2 DFSDM1 TIM15_C SPI4_NS SAI1_FS _DATIN3 H1N S _A - SAI4_FS _A - SAI4_D2 - FMC_A2 0 DCMI_D 4/PSSI_ D4 LCD_B0 EVENTO UT PE5 TRACED2 - SAI1_CK DFSDM1 TIM15_C 2 _CKIN3 H1 SPI4_MI SO SAI1_SC K_A - SAI4_SC K_A - SAI4_CK 2 - FMC_A2 1 DCMI_D 6/PSSI_ D6 LCD_G0 EVENTO UT PE6 TRACED3 TIM1_B KIN2 SAI1_D1 - TIM15_C H2 SPI4_M OSI SAI1_SD _A - SAI4_SD SAI4_D1 _A SAI4_M CLK_B TIM1_B KIN2_C OMP12 FMC_A2 2 DCMI_D 7/PSSI_ D7 LCD_G1 EVENTO UT PE7 - TIM1_ET R - DFSDM1 _DATIN2 - - - UART7_ RX - - OCTOS PIM_P1_ IO4 - FMC_D4 /FMC_A D4 - - EVENTO UT PE8 - TIM1_C H1N - DFSDM1 _CKIN2 - - - UART7_ TX - - OCTOS PIM_P1_ IO5 - FMC_D5 COMP2_ /FMC_A OUT D5 - EVENTO UT PE9 - TIM1_C H1 - DFSDM1 _CKOUT - - - UART7_ RTS/UA RT7_DE - - OCTOS PIM_P1_ IO6 - FMC_D6 /FMC_A D6 - EVENTO UT Port E - 105/284 Pinouts, pin descriptions and alternate functions DS13312 Rev 3 PE0 - STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 - AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS DS13312 Rev 3 PE10 - TIM1_C H2N - DFSDM1 _DATIN4 - - - UART7_ CTS - - OCTOS PIM_P1_ IO7 FMC_D7 /FMC_A D7 - - EVENTO UT PE11 - TIM1_C H2 - DFSDM1 _CKIN4 - SPI4_NS S - - - - OCTOS FMC_D8 SAI4_SD PIM_P1_ /FMC_A _B NCS D8 - LCD_G3 EVENTO UT PE12 - TIM1_C H3N - DFSDM1 _DATIN5 - SPI4_SC K - - - - SAI4_SC K_B - FMC_D9 COMP1_ /FMC_A OUT D9 LCD_B4 EVENTO UT PE13 - TIM1_C H3 - DFSDM1 _CKIN5 - SPI4_MI SO - - - - SAI4_FS _B - FMC_D1 COMP2_ 0/FMC_ LCD_DE OUT AD10 EVENTO UT PE14 - TIM1_C H4 - - - SPI4_M OSI - - - - SAI4_M CLK_B - FMC_D1 1/FMC_ AD11 - LCD_CL K EVENTO UT PE15 - TIM1_B KIN - - - - - - - - - USART1 0_CK FMC_D1 2/FMC_ AD12 TIM1_B KIN_CO MP12 LCD_R7 EVENTO UT Port E Pinouts, pin descriptions and alternate functions 106/284 Table 9. STM32H735xG pin alternate functions (continued) STM32H735xG AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 AF13 AF14 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - - - - I2C2_SD A - I2C5_SD A - - OCTOS PIM_P2_ IO0 - - FMC_A0 TIM23_C H1 - EVENTO UT PF1 - - - - I2C2_SC L - I2C5_SC L - - OCTOS PIM_P2_ IO1 - - FMC_A1 TIM23_C H2 - EVENTO UT PF2 - - - - I2C2_S MBA - I2C5_S MBA - - OCTOS PIM_P2_ IO2 - - FMC_A2 TIM23_C H3 - EVENTO UT PF3 - - - - - - - - - OCTOS PIM_P2_ IO3 - - FMC_A3 TIM23_C H4 - EVENTO UT PF4 - - - - - - - - - OCTOS PIM_P2_ CLK - - FMC_A4 - - EVENTO UT PF5 - - - - - - - - - OCTOS PIM_P2_ NCLK - - FMC_A5 - - EVENTO UT PF6 - TIM16_C FDCAN3 H1 _RX - - SPI5_NS SAI1_SD S _B UART7_ RX SAI4_SD _B - OCTOS PIM_P1_ IO3 - - TIM23_C H1 - EVENTO UT PF7 - TIM17_C FDCAN3 _TX H1 - - SPI5_SC K SAI1_M CLK_B UART7_ TX SAI4_M CLK_B - OCTOS PIM_P1_ IO2 - - TIM23_C H2 - EVENTO UT PF8 - TIM16_C H1N - - - SPI5_MI SO SAI1_SC K_B UART7_ RTS/UA RT7_DE OCTOS SAI4_SC TIM13_C PIM_P1_ K_B H1 IO0 - - TIM23_C H3 - EVENTO UT PF9 - TIM17_C H1N - - - SPI5_M OSI SAI1_FS _B UART7_ CTS OCTOS SAI4_FS TIM14_C PIM_P1_ _B H1 IO1 - - TIM23_C H4 - EVENTO UT 107/284 Pinouts, pin descriptions and alternate functions DS13312 Rev 3 PF0 Port F STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS DS13312 Rev 3 Port F AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 AF13 AF14 AF15 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 SYS DCMI_D 11/PSSI_ LCD_DE D11 EVENTO UT - PSSI_D1 5 - - - - OCTOS PIM_P1_ SAI4_D3 CLK - - - - - SPI5_M OSI - - - OCTOS SAI4_SD PIM_P1_ _B NCLK - FMC_N RAS DCMI_D 12/PSSI _D12 TIM24_C EVENTO H1 UT - - - - - - - - OCTOS PIM_P2_ DQS - - FMC_A6 - TIM24_C EVENTO H2 UT - - - DFSDM1 _DATIN6 I2C4_S MBA - - - - - - - FMC_A7 - TIM24_C EVENTO H3 UT PF14 - - - DFSDM1 I2C4_SC _CKIN6 L - - - - - - - FMC_A8 - TIM24_C EVENTO H4 UT PF15 - - - I2C4_SD A - - - - - - - FMC_A9 - TIM16_B SAI1_D3 KIN PF10 - PF11 - - PF12 - PF13 - - Pinouts, pin descriptions and alternate functions 108/284 Table 9. STM32H735xG pin alternate functions (continued) EVENTO UT STM32H735xG AF0 Port SYS AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS PG0 - - - - - - - - - OCTOS PIM_P2_ IO4 - UART9_ RX FMC_A1 0 - - EVENTO UT PG1 - - - - - - - - - OCTOS PIM_P2_ IO5 - UART9_ TX FMC_A1 1 - - EVENTO UT PG2 - - - TIM8_B KIN - - - - - - - TIM8_B KIN_CO MP12 FMC_A1 2 - PG3 - - - TIM8_B KIN2 - - - - - - - TIM8_B KIN2_C OMP12 FMC_A1 3 TIM23_E TR - EVENTO UT PG4 - TIM1_B KIN2 - - - - - - - - - TIM1_B KIN2_C OMP12 FMC_A1 4/FMC_ BA0 - - EVENTO UT PG5 - TIM1_ET R - - - - - - - - - - FMC_A1 5/FMC_ BA1 - - EVENTO UT PG6 - TIM17_B KIN - - - - - - - - OCTOS PIM_P1_ NCS - FMC_NE 3 DCMI_D 12/PSSI _D12 LCD_R7 EVENTO UT PG7 - - - - - - SAI1_M CLK_A USART6 _CK - OCTOS PIM_P2_ DQS - - FMC_IN T DCMI_D 13/PSSI _D13 LCD_CL K EVENTO UT PG8 - - - TIM8_ET R - SPI6_NS S/I2S6_ WS - USART6 _RTS/U SART6_ DE SPDIFR X1_IN3 - - ETH_PP S_OUT FMC_SD CLK - LCD_G7 EVENTO UT TIM24_E EVENTO TR UT 109/284 Pinouts, pin descriptions and alternate functions DS13312 Rev 3 Port G AF1 STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS DS13312 Rev 3 Port G AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 OCTOS SAI4_FS PIM_P1_ _B IO6 SDMMC 2_D0 FMC_NE 2/FMC_ NCE DCMI_V SYNC/P SSI_RD Y - EVENTO UT FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF13 AF14 AF15 SYS SPI1_MI SO/I2S1 _SDI - USART6 _RX SPDIFR X1_IN4 - SPI1_NS S/I2S1_ WS - - - LCD_G3 SAI4_SD _B SDMMC 2_D1 FMC_NE 3 DCMI_D 2/PSSI_ D2 LCD_B2 EVENTO UT - USART1 0_RX SPI1_SC K/I2S1_ CK - - SPDIFR X1_IN1 OCTOS PIM_P2_ IO7 SDMMC 2_D2 ETH_MII _TX_EN/ ETH_RM II_TX_E N - DCMI_D 3/PSSI_ D3 LCD_B3 EVENTO UT - OCTOS PIM_P2_ NCS USART1 0_TX SPI6_MI SO/I2S6 _SDI - USART6 _RTS/U SART6_ DE SPDIFR X1_IN2 LCD_B4 SDMMC 2_D3 ETH_MII _TXD1/E FMC_NE TIM23_C TH_RMII 4 H1 _TXD1 LCD_B1 EVENTO UT LPTIM1_ OUT - - USART1 SPI6_SC 0_CTS/U K/I2S6_ SART10 CK _NSS - USART6 _CTS/U SART6_ NSS - - SDMMC 2_D6 ETH_MII _TXD0/E TH_RMII _TXD0 FMC_A2 TIM23_C 4 H2 LCD_R0 EVENTO UT TRACED1 LPTIM1_ ETR - - USART1 SPI6_M 0_RTS/U OSI/I2S6 SART10 _SDO _DE - USART6 _TX - OCTOS PIM_P1_ IO7 SDMMC 2_D7 ETH_MII _TXD1/E TH_RMII _TXD1 FMC_A2 TIM23_C 5 H3 LCD_B0 EVENTO UT - - - - - USART6 _CTS/U SART6_ NSS - OCTOS PIM_P2_ DQS - USART1 0_CK FMC_N CAS - EVENTO UT - - FDCAN3 _TX PG10 - - OCTOS FDCAN3 PIM_P2_ _RX IO6 PG11 - LPTIM1_ IN2 - PG12 - LPTIM1_ IN1 PG13 TRACED0 PG14 PG15 - - - DCMI_D 13/PSSI _D13 STM32H735xG - PG9 Pinouts, pin descriptions and alternate functions 110/284 Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS - - - - - - - - - - - - - - - EVENTO UT PH1 - - - - - - - - - - - - - - - EVENTO UT PH2 - LPTIM1_ IN2 - - - - - - - OCTOS SAI4_SC ETH_MII FMC_SD PIM_P1_ K_B _CRS CKE0 IO4 - LCD_R0 EVENTO UT PH3 - - - - - - - - - OCTOS PIM_P1_ IO5 SAI4_M CLK_B - LCD_R1 EVENTO UT PH4 - - - - I2C2_SC L - - - - LCD_G5 OTG_HS _ULPI_N XT - - PSSI_D1 4 LCD_G4 EVENTO UT PH5 - - - - I2C2_SD SPI5_NS A S - - - - - - FMC_SD NWE - - EVENTO UT PH6 - - TIM12_C H1 - I2C2_S MBA SPI5_SC K - - - - - ETH_MII FMC_SD _RXD2 NE1 DCMI_D 8/PSSI_ D8 - EVENTO UT PH7 - - - - I2C3_SC L SPI5_MI SO - - - - - ETH_MII FMC_SD _RXD3 CKE1 DCMI_D 9/PSSI_ D9 - EVENTO UT PH8 - - TIM5_ET R - I2C3_SD A - - - - - - - FMC_D1 6 DCMI_H SYNC/P SSI_DE LCD_R2 EVENTO UT PH9 - - TIM12_C H2 - I2C3_S MBA - - - - - - - FMC_D1 7 DCMI_D 0/PSSI_ D0 LCD_R3 EVENTO UT PH10 - - TIM5_C H1 - I2C4_S MBA - - - - - - - FMC_D1 8 DCMI_D 1/PSSI_ D1 LCD_R4 EVENTO UT Port H 111/284 Pinouts, pin descriptions and alternate functions DS13312 Rev 3 PH0 ETH_MII FMC_SD _COL NE0 STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) AF0 Port SYS DS13312 Rev 3 Port H AF1 AF2 AF3 AF4 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 AF5 AF6 AF7 AF8 AF9 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 AF13 AF14 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 SYS PH11 - - TIM5_C H2 - I2C4_SC L - - - - - - - FMC_D1 9 DCMI_D 2/PSSI_ D2 LCD_R5 EVENTO UT PH12 - - TIM5_C H3 - I2C4_SD A - - - - - - - FMC_D2 0 DCMI_D 3/PSSI_ D3 LCD_R6 EVENTO UT PH13 - - - TIM8_C H1N - - - - UART4_ TX FDCAN1 _TX - - FMC_D2 1 - LCD_G2 EVENTO UT PH14 - - - TIM8_C H2N - - - - UART4_ RX FDCAN1 _RX - - FMC_D2 2 DCMI_D 4/PSSI_ D4 LCD_G3 EVENTO UT PH15 - - - TIM8_C H3N - - - - - - - - DCMI_D FMC_D2 11/PSSI_ LCD_G4 3 D11 EVENTO UT PJ8 - TIM1_C H3N - TIM8_C H1 - - - - UART8_ TX - - - - - LCD_G1 EVENTO UT PJ9 - TIM1_C H3 - TIM8_C H1N - - - - UART8_ RX - - - - - LCD_G2 EVENTO UT PJ10 - TIM1_C H2N - TIM8_C H2 - SPI5_M OSI - - - - - - - - LCD_G3 EVENTO UT PJ11 - TIM1_C H2 - TIM8_C H2N - SPI5_MI SO - - - - - - - - LCD_G4 EVENTO UT Port J Pinouts, pin descriptions and alternate functions 112/284 Table 9. STM32H735xG pin alternate functions (continued) STM32H735xG AF0 Port SYS Port K AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 CEC/DC DFSDM1 MI/PSSI/ /LCD/LP DFSDM1 FMC/LP FDCAN3 TIM2/3/4 /I2C1/2/3 TIM1/SA /PDM_S /5/LPUA /4/5/LPTI I4/TIM16 AI1/TIM3 RT1/OC M2/OCT /17/TIM1 /4/5/12/1 TOSPIM OSPIM_ x/TIM2x 5 _P1/2/TI P1/TIM1 M8 5/USAR T1/10 FDCAN1 /2/FMC/ CEC/FD DFSDM1 SDMMC LPUART LCD/OC CAN3/S /I2C4/5/ 1/SPI2/I2 1/SAI4/S TOSPIM PI1/I2S1/ OCTOS S2/SPI3/ DMMC1/ _P1/2/S SPI2/I2S PIM_P1/ I2S3/SPI SPDIFR AI4/SDM 2/SPI3/I2 SAI1/SPI 6/UART X1/SPI6/ MC2/SP S3/SPI4/ 3/I2S3/U 7/USAR UART4/ DIFRX1/ 5/6 ART4 T1/2/3/6 5/8 TIM13/1 4 AF10 AF11 AF12 CRS/FM C/LCD/O CTOSPI M_P1/O TG1_FS/ OTG1_H S/SAI4/S DMMC2/ TIM8 DFSDM1 /ETH/I2C 4/LCD/M DIOS/O CTOSPI M_P1/S DMMC2/ SWPMI1 /TIM1x/T IM8/UAR T7/9/US ART10 FMC/LC D/MDIO S/OCTO SPIM_P 1/SDMM C1/TIM1 x/TIM8 AF13 AF14 COMP/D CMI/PSS LCD/TIM I/LCD/TI 24/UAR T5 M1x/TIM 23 AF15 STM32H735xG Table 9. STM32H735xG pin alternate functions (continued) SYS - TIM1_C H1N - TIM8_C H3 - SPI5_SC K - - - - - - - - LCD_G5 EVENTO UT PK1 - TIM1_C H1 - TIM8_C H3N - SPI5_NS S - - - - - - - - LCD_G6 EVENTO UT PK2 - TIM1_B KIN - TIM8_B KIN - - - - - - TIM8_B KIN_CO MP12 TIM1_B KIN_CO MP12 - - LCD_G7 EVENTO UT 113/284 Pinouts, pin descriptions and alternate functions DS13312 Rev 3 PK0 Electrical characteristics 6 STM32H735xG Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 12. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 13. Figure 12. Pin loading conditions Figure 13. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 114/284 DS13312 Rev 3 MS19010V2 STM32H735xG Power supply scheme Figure 14. Power supply scheme VDDSMPS VLXSMPS Step Down Converter VFBSMPS VSSSMPS VCAP IOs D3 domain (System logic, EXTI, IO logic Peripherals, RAM) Power switch VSS Power switch Core domain (VCORE) LDO voltage regulator VDDLDO Level shifter 6.1.6 Electrical characteristics D2 domain (peripherals, RAM) D1 domain (CPU, peripherals, RAM) Flash VSS VDD domain LSI, HSI, CSI, HSI48, HSE, PLLs VDD VBAT charging Backup domain Backup VBKP regulator VSW VBAT Power switch Power switch LSE, RTC, Wakeup logic, backup IO logic registers, Reset BKUP IOs VSS VDD50USB Backup RAM VSS USB regulator VSS VDD33USB USB FS IOs VDDA Analog domain REF_BUF VREF+ ADC, DAC VREF+ VREF- VREF- OPAMP, Comparator VSSA MSv63814V5 1. Refer to application note AN5419 “Getting started with STM32H723/733, STM32H725/735 and STM32H730 Value Line hardware development“ for the possible power scheme and connected capacitors. DS13312 Rev 3 115/284 252 Electrical characteristics 6.1.7 STM32H735xG Current consumption measurement Figure 15. Current consumption measurement scheme SMPS ON LDO ON IDD_VBAT IDD_VBAT VBAT VBAT IDD IDD VDD VDD VDDSMPS VDDLDO VDDA VDDA 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics, Table 11: Current characteristics, and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 10. Voltage characteristics Symbols Ratings Min Max Unit VDDX - VSS(1) External main supply voltage (including VDD, VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT) −0.3 4.0 V Input voltage on FT_xxx pins VSS−0.3 Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4) V Input voltage on TT_xx pins VSS−0.3 4.0 V Input voltage on BOOT0 pin VSS 9.0 V VSS-0.3 4.0 V Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins - 50 mV VIN(2) Input voltage on any other pins |∆VDDX| |VSSx-VSS| 1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 116/284 DS13312 Rev 3 STM32H735xG Electrical characteristics 4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled. Table 11. Current characteristics Symbols Ratings Max ΣIVDD (1) Total current into sum of all VDD power lines (source) 620 ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620 IVDD IVSS IIO ΣI(PIN) IINJ(PIN) (3)(4) ΣIINJ(PIN) Maximum current into each VDD power pin (source)(1) 100 (1) 100 Maximum current out of each VSS ground pin (sink) Output current sunk by any I/O and control pin, except Px_C 20 Output current sunk by Px_C pins 1 Total output current sunk by sum of all I/Os and control pins(2) Unit mA 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 −5/+0 Injected current on PA4, PA5 −0/0 Total injected current (sum of all I/Os and control pins)(5) ±25 1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN