STM32H743xI
32-bit Arm® Cortex®-M7 400MHz MCUs, up to 2MB Flash,
1MB RAM, 46 com. and analog interfaces
Datasheet - production data
Features
FBGA
Core
• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache allowing
one cache line to be filled in a single access
from the 256-bit embedded Flash memory;
frequency up to 400 MHz, MPU, 856 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
• Up to 2 Mbytes of Flash memory with readwhile-write support
TFBGA240+25 (14x14 mm)
TFBGA100 (8x8 mm)(1)
FBGA
UFBGA176+25 (10x10 mm)
UFBGA169 (7x7 mm)(1)
LQFP208
(28x28 mm)
LQFP176
(24x24 mm)
LQFP144
(20x20 mm)
LQFP100
(14x14 mm)
1. Package under development.
– D1: high-performance capabilities for high
bandwidth peripherals
– D2: communication peripherals and timers
– D3: reset/clock control/power management
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
• 1.62 to 3.6 V application supply and I/Os
• Dual mode Quad-SPI memory interface
running up to 133 MHz
• Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
• Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
clocked up to 133 MHz in synchronous mode
• Voltage scaling in Run and Stop mode (5
configurable ranges)
• CRC calculation unit
• Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Security
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/VREF+
Low-power consumption
• ROP, PC-ROP, active tamper
• Total current consumption down to 4 µA
General-purpose input/outputs
• Up to 168 I/O ports with interrupt capability
– Fast I/Os capable of up to 133 MHz
– Up to 164 5 V-tolerant I/Os
Clock management
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 40 kHz LSI
Reset and power management
• External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
• 3 separate power domains which can be
independently clock gated or switched off to
maximize power efficiency:
• 3× PLLs (1 for the system clock, 2 for kernel
clocks) with fractional mode
October 2017
This is information on a product in full production.
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STM32H743xI
Interconnect matrix
• 1× temperature sensor
•
3 bus matrices (1 AXI and 2 AHB)
• 2× 12-bit D/A converters (1 MHz)
•
Bridges (5× AHB2-APB, 2× AXI2-AHB)
• 2× ultra-low-power comparators
4 DMA controllers to unload the CPU
• 1× high-speed general-purpose master direct
memory access controller (MDMA) with linked
list support
• 2× dual-port DMAs with FIFO and request
router capabilities
• 2× operational amplifiers (8 MHz bandwidth)
• 1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
• LCD-TFT controller up to XGA resolution
• 1× basic DMA with request router capabilities
• Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
Up to 35 communication peripherals
• Hardware JPEG Codec
• 4× I2C FM+ interfaces (SMBus/PMBus)
Up to 22 timers and watchdogs
• 4× USART/4x UARTs (ISO7816 interface, LIN,
IrDA, modem control, up to 12.5 Mbit/s) and
1x LPUART
• 1× high-resolution timer (2.5 ns max
resolution)
• 6× SPIs, including 3 with muxed duplex I2S
audio class accuracy via internal audio PLL or
external clock, 1x I2S in LP domain (up to
133 MHz)
• 4x SAIs (serial audio interface)
• 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 200 MHz)
• 2× 16-bit advanced motor control timers (up to
200 MHz)
• SPDIFRX interface
• 10× 16-bit general-purpose timers (up to
200 MHz)
• SWPMI single-wire protocol master I/F
• 5× 16-bit low-power timers (up to 200 MHz)
• MDIO Slave interface
• 2× watchdogs (independent and window)
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 1× SysTick timer
• 2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
• RTC with sub-second accuracy & HW calendar
• 2× USB OTG interfaces (1FS, 1HS/FS)
Debug mode
• Ethernet MAC interface with DMA controller
• SWD & JTAG interfaces
• HDMI-CEC
• 4 Kbyte Embedded Trace Buffer
• 8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
• 3× ADCs with 16-bit max. resolution (14 bits
4 MSPS, 16 bits 3.6 MSPS)
True random number generators (3
oscillators each)
96-bit unique ID
All packages are ECOPACK®2 compliant
Table 1. Device summary
Reference
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Part number
STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI,
STM32H743AI
DocID030538 Rev 3
STM32H743xI
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
3.13
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 27
3.14
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 27
3.15
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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3.21
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.22
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.23
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 31
3.24
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.25
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.26
JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.27
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.28
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.28.1
High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.28.2
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.28.3
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.28.4
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 37
3.28.6
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28.7
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28.8
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.29
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 38
3.30
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.31
Universal synchronous/asynchronous receiver transmitter (USART) . . . 39
3.32
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 40
3.33
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 41
3.34
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.36
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 42
3.37
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 43
3.38
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 43
3.39
Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 43
3.40
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44
3.41
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 44
3.42
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.43
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Contents
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Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.2
VCAP1/VCAP2/VCAP3 external capacitor . . . . . . . . . . . . . . . . . . . . . . 99
6.3.3
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 99
6.3.4
Embedded reset and power control block characteristics . . . . . . . . . . 100
6.3.5
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.11
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.12
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.13
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 126
6.3.14
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.15
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.16
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.17
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.18
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.19
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.20
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.21
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.22
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.23
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.24
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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6.3.25
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.26
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.27
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 173
6.3.29
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 176
6.3.30
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 177
6.3.31
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.32
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.33
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.2
TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.3
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.4
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.5
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.6
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.7
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.8
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.9
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.9.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32H743xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM32H743xI pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VCAP1/VCAP2/VCAP3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 99
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 105
Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 106
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 107
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 114
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
DocID030538 Rev 3
7/226
9
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
8/226
STM32H743xI
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 124
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 137
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 137
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 138
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 139
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 142
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 147
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DocID030538 Rev 3
STM32H743xI
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
List of tables
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 188
Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 189
USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 192
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 193
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 194
Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 203
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 217
UFBGA 176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . 218
TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
TFBGA240+25, 265 pin recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . 222
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
STM32H743xI ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
DocID030538 Rev 3
9/226
9
List of figures
STM32H743xI
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
10/226
STM32H743xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32H743xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 138
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 139
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 147
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 150
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 151
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 162
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
DocID030538 Rev 3
STM32H743xI
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
List of figures
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 197
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 204
LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . . 209
LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 213
LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
TFBGA240+25 - 265 pin pin, 14x14 mm 0.8 mm pitch
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
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11
Introduction
1
STM32H743xI
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32H743xI microcontrollers.
This document should be read in conjunction with the STM32H743xI reference manual
(RM0433). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Arm® Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the www.arm.com website.
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STM32H743xI
2
Description
Description
STM32H743xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 400 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H743xI devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H743xI devices incorporate high-speed embedded memories with a dual-bank Flash
memory up to 2 Mbytes, 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, 864 Kbytes of
user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced
I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix
and a multi layer AXI interconnect supporting internal and external memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers and a true random number generator (RNG). The devices
support four digital filters for external sigma-delta modulators (DFSDM). They also feature
standard and advanced communication interfaces.
•
Standard peripherals
–
•
Four I2Cs
–
Four USARTs, four UARTs and one LPUART
–
Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
Four SAI serial audio interfaces
–
One SPDIFRX interface
–
One SWPMI (Single Wire Protocol Master Interface)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces
–
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
One FDCAN plus one TT-CAN interface
–
An Ethernet interface
–
Chrom-ART Accelerator™
–
HDMI-CEC
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
A Quad-SPI Flash memory interface
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
–
A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H743xI features and peripheral counts for the list of peripherals
available on each part number.
DocID030538 Rev 3
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46
Description
STM32H743xI
STM32H743xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H743xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H743xI microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smart watches.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32H743xI features and peripheral counts
Peripherals
STM32H
743VI
STM32H
743ZI
Flash memory in Kbytes
SRAM in
Kbytes
TCM RAM in
Kbytes
14/226
STM32H
743AI
2048
SRAM mapped onto
AXI bus
512
SRAM1 (D2 domain)
128
SRAM2 (D2 domain)
128
SRAM3 (D2 domain)
32
SRAM4 (D3 domain)
64
ITCM RAM
(instruction)
64
DTCM RAM (data)
128
Backup SRAM (Kbytes)
4
FMC
Yes
Quad-SPI
Yes
Ethernet
Yes
DocID030538 Rev 3
STM32H
743II
STM32H
743BI
STM32H
743XI
STM32H743xI
Description
Table 2. STM32H743xI features and peripheral counts (continued)
STM32H
743VI
Peripherals
Timers
STM32H
743ZI
STM32H
743AI
High-resolution
1
General-purpose
10
Advanced-control
(PWM)
2
Basic
2
Low-power
5
Random number generator
STM32H
743II
6/3(1)
SPI / I
I2C
4
USART/UART/
LPUART
4/4
/1
SAI
4
SPDIFRX
4 inputs
SWPMI
Yes
MDIO
Yes
SDMMC
2
FDCAN/TT-CAN
1/1
USB OTG_FS
Yes
USB OTG_HS
Yes
Ethernet and camera interface
Yes
LCD-TFT
Yes
JPEG Codec
Yes
Chrom-ART Accelerator™ (DMA2D)
Yes
GPIOs
82
114
131
140
168
3
8 to 16-bit ADCs
Number of channels
20
12-bit DAC
Number of channels
Yes
2
Comparators
2
Operational amplifiers
2
DFSDM
Yes
Maximum CPU frequency
400 MHz
Operating voltage
STM32H
743XI
Yes
2S
Communicati
on interfaces
STM32H
743BI
1.71 to
3.6 V(2)
DocID030538 Rev 3
1.62 to 3.6 V(3)
15/226
46
Description
STM32H743xI
Table 2. STM32H743xI features and peripheral counts (continued)
Peripherals
STM32H
743VI
STM32H
743AI
STM32H
743II
STM32H
743BI
STM32H
743XI
Ambient temperatures: –40 up to +85 °C(4)
Operating temperatures
Package
STM32H
743ZI
Junction temperature: –40 to + 125 °C
LQFP100
TFBGA100(5)
LQFP144
UFBGA
169(5)
LQFP176
UFBGA
176+25
LQFP208
TFBGA
240+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
3. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor)
and connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
4. The product junction temperature must be kept within the –40 to +125 °C temperature range.
5. This package is under development. Please contact STMicroelectronics for details.
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STM32H743xI
Description
Figure 1. STM32H743xI block diagram
MII / RMII
To APB1-2
peripherals
MDIO
as AF
AHB1
D-TCM
64KB
D-TCM
64KB
DMA1
AXIM
1 MB FLASH
D-Cache
16KB
LCD-TFT
WWDG
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
JPEG
FMC_signals
Quad-SPI
RNG
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
ADC1
CLK, CS,D[7:0]
32b
AXI/AHB34 (200MHz)
TIM6
16b
16b
TIM7
16b
16b
AHB/APB
SWPMI
32b
16b
Delay block
A P B 10 MHz
3
DAP
AHB4
TIM1/PWM
16b
16b
CRC
ADC3
RX, TX as AF
UART7
RX, TX as AF
RX, TX as AF
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SCL, SDA, SMBAL as AF
I2C2/SMBUS
I2C3/SMBUS
MDIOs
FDCAN2
4 KB BKP
RAM
SPIFRX
SPDIFRX[3:0] as AF
HDMI-CEC
Tamper monitor
VREF
AHB/APB
SAI4
HDMI_CEC as AF
LPTIM3
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
RX, TX, CK, CTS, RTS as AF
LPUART1
LPTIM2
DAC_OUT1, DAC_OUT2 as AF
16b
OPAMP1&2
@VDD33
VDD12 BBgen + POWER MNGT
Voltage
regulator
3.3 to 1.2V
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP1/2/3
@VSW
SYSCFG
XTAL 32 kHz
EXTI WKUP
LS
LPTIM3_OUT as AF
LPTIM1
PWRCTRL
RCC
Reset &
control
COMP1&2
LPTIM4
TX, RX
TX, RX
USBCR
64 KB SRAM
GPIO PORTK
LPTIM5
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MDC, MDIO
TT-FDCAN1
DAC
GPIO PORTA.. J
RX, TX, SCK
CTS, RTS as AF
RX, TX as AF
I2C1/SMBUS
RAM
I/F
32-bit AHB BUS-MATRIX
HSEM
APB1 100 MHz (max)
10 KB SRAM
AHB4
AHB4
AHB4
BDMA
SPI1/I2S1
LPTIM4_OUT as AF
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
AHB4
smcard
irDA USART6
smcard
irDA USART1
LPTIM5_OUT as AF
SCL, SDA, SMBAL as AF
APB2 100 MHz (max)
SPI4
DMA
Mux2
RX, TX, SCK, CTS,
RTS as AF
UART5
UART8
IWDG
Temperature
sensor
@VDD
CSI
HSI48
HSI
LSI
HS RC
LS RC
RTC
Backup registers
LS
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
TIM15
AHB4 (200MHz)
PK[7:0]
TIM17
TIM16
APB4
MHz
(max)
APB4
100100
MHz
(max)
PA..J[15:0]
SPI5
TIM8/PWM
irDA
UART4
AHB4 (200MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR,
BKIN as AF
Up to 17 analog inputs
common to ADC1 and 2
1 channel as AF
irDA
FIFO
RX, TX, SCK, CTS, RTS as AF
1 channel as AF
smcard
AHB4
RX, TX, SCK, CTS, RTS as AF
2 channels as AF
TIM13
Digital filter
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
4 channels
TIM12
USART3
SAI3
SAI1
MOSI, MISO, SCK, NSS as AF
4 channels, ETR as AF
TIM5
USART2
DFSDM
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
4 channels, ETR as AF
TIM4
smcard
SAI2
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
4 channels, ETR as AF
TIM14
HRTIM1
SD, SCK, FS, MCLK, CK[2:1] as AF
MOSI, MISO, SCK, NSS as AF
TIM2
TIM3
AHB/APB
FIFO FIFO FIFO
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM_CKOUT,
DFSDM_DATAIN[0:7],
DFSDM_CKIN[0:7]
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
16b
16b
APB4 100 MHz (max)
HSYNC, VSYNC, PIXCLK, D[13:0]
AHB2 (200MHz)
DCMI
Up to 20 analog inputs
common to ADC1 & 2
ADC2
FIFO
SDMMC1
DMA/
FIFO
AHB/APB
AHB3
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
FIFO
DMA
Mux1
FMC
64-bit AXI BUS-MATRIX
CHROM-ART
(DMA2D)
DMA/
FIFO
FIFO
32-bit AHB BUS-MATRIX
512 KB AXI
SRAM
AHBS
16 Streams
FIFO
MDMA
PHY
OTG_FS
1 MB FLASH
ETM
I-Cache
16KB
DMA/
FIFO
8 Stream 8 Stream
FIFOs
FIFOs
AXI/AHB12 (200MHz)
AHB2 (200MHz)
TRACECK
TRACED[3:0]
PHY
ETHER
SDMMC2 OTG_HS
MAC
AHBP
Arm CPU
Cortex-M7
400 MHz
JTAG/SW
AHB4 (200MHz)
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
DMA2
(200MHz)
AHB1 (200MHz)
I-TCM
64KB
DP, DM, STP,
SDMMC_
NXT,ULPI:CK DP, DM, ID,
D[7:0],
VBUS
, D[7:0], DIR,
CMD, CK as AF
ID, VBUS
AWU
OSC32_IN
OSC32_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VBAT = 1.8 to 3.6 V
@VDD
XTAL OSC
4- 48 MHz
PLL1+PLL2+PLL3
OSC_IN
OSC_OUT
WDG_LS_D1
@VDD
POR
reset
Int
SUPPLY SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[4:0]
MSv41922V8
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Functional overview
STM32H743xI
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•
64-bit AXI interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H743xI family.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H743xI devices embed up to 2 Mbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
One Flash word (8 words, 32 bytes or 256 bits)
•
10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
3.3.2
•
A 1 Mbyte user Flash memory block containing eight user sectors of
128 Kbytes(4 K Flash words)
•
128 Kbytes of System Flash memory from which the device can boot
•
2 Kbytes (64 Flash words) of user option bytes for user configuration
Embedded SRAM
All devices feature:
•
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
•
SRAM1 mapped on D2 domain: 128 Kbytes
•
SRAM2 mapped on D2 domain: 128 Kbytes
•
SRAM3 mapped on D2 domain: 32 Kbytes
•
SRAM4 mapped on D3 domain: 64 Kbytes
•
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the
CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the
CPU(AHBP).
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
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SRAM data are protected by ECC:
•
7 ECC bits are added per 32-bit word.
•
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single- and doubleerror correction.
3.4
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space
•
All RAM address space: ITCM, DTCM RAMs and SRAMs
•
The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•
VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
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•
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•
VCAP1/VCAP2/VCAP3: VCORE supplies, which values depend on voltage scaling (0.7 V,
0.9 V, 1.0 V, 1.1 V or 1.2 V). They are configured through VOS bits in PWR_D3CR
register. The VCORE domain is split into the following power domains that can be
independently switch off.
–
D1 domain containing some peripherals and the Cortex®-M7 core.
–
D2 domain containing a large part of the peripherals.
–
D3 domain containing some peripherals and the system control.
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3.5.2
Functional overview
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
3.5.3
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 5 power
supply levels:
•
•
Run mode (VOS1 to VOS3)
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.6
Low-power strategy
There are several ways to reduce power consumption on STM32H743xI:
•
Decrease dynamic power consumption by slowing down the system clocks even in
Run mode and individually clock gating the peripherals that are not used.
•
Save power consumption when the CPU is idle, by selecting among the available lowpower mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
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Functional overview
STM32H743xI
The devices feature several low-power modes:
•
CSleep (CPU clock stopped)
•
CStop (CPU sub-system clock stopped)
•
DStop (Domain bus matrix clock stopped)
•
Stop (System clock stopped)
•
DStandby (Domain powered down)
•
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
Table 3. System vs domain low-power mode
System power mode
Run
3.7
D1 domain power
mode
D2 domain power
mode
DRun/DStop/DStandby DRun/DStop/DStandby
D3 domain power
mode
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
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3.7.1
Functional overview
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
•
Internal oscillators:
–
64 MHz HSI clock (1% accuracy)
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
4-48 MHz HSE clock
–
32.768 kHz LSE clock
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
3.8
•
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Window watchdog
•
Independent watchdog
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in Analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
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Functional overview
3.9
STM32H743xI
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 2).
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Figure 2. STM32H743xI bus matrix
AHBS
CPU
ITCM
64 Kbyte
MDMA
DMA2D
DMA1_MEM
SDMMC1
LTDC
D1-to-D2 AHB
DMA2
DMA2_MEM
DMA1
Ethernet SDMMC2 USBHS1
MAC
USBHS2
DMA2_PERIPH
DTCM
128 Kbyte
AHBP
AXIM
I$
D$
16KB 16KB
DMA1_PERIPH
Cortex-M7
APB3
SRAM1 128
Kbyte
AHB3
SRAM2 128
Kbyte
SRAM3
32 Kbyte
DocID030538 Rev 3
Flash A
1 Mbyte
AHB1
Flash B
1 Mbyte
AHB2
AXI SRAM
512 Kbyte
APB1
QSPI
APB2
FMC
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
Legend
32-bit bus
AHB4
TCM AHB
AXI
APB
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64-bit bus
Master interface
Bus multiplexer
Slave interface
APB4
SRAM4
64 Kbyte
Backup
SRAM
4 Kbyte
MSv46613V1
Functional overview
BDMA
32-bit AHB bus matrix
D3 domain
Functional overview
3.10
STM32H743xI
DMA controllers
The devices feature four DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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3.12
Functional overview
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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Functional overview
3.15
STM32H743xI
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
3.16
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•
Direct mode through registers
•
External Flash status register polling mode
•
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H743xI devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H743xI devices embeds a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
ambient temperature ranging from − 40 to +125 °C with a precision of +-2%.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in read-only mode.
3.19
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VDD mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
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Functional overview
3.20
STM32H743xI
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
external triggers for conversion
•
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H743xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
An external I/O
•
A DAC output channel
•
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H743xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
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•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
One positive input connected to DAC
•
Output connected to internal ADC
•
Low input bias current down to 1 nA
•
Low input offset voltage down to 1.5 mV
•
Gain bandwidth up to 8 MHz
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Functional overview
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
up to 24-bit output data resolution, signed output data format
•
automatic data offset correction (offset stored in register by user)
•
continuous or single conversion
•
start-of-conversion triggered by:
•
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
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Functional overview
•
STM32H743xI
short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
•
break signal generation on analog watchdog event or on short circuit detector event
•
extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
•
DMA capability to read the final conversion data
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 4. DFSDM implementation
DFSDM features
3.24
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
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•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image
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3.25
Functional overview
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
3.26
•
2 display layers with dedicated FIFO (64x32-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
•
AXI master interface with burst of 16 words
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 109181 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
3.27
•
8-bit/channel pixel depths
•
Single clock per pixel encoding and decoding
•
Support for JPEG header generation and parsing
•
Up to four programmable quantization tables
•
Fully programmable Huffman tables (two AC and two DC)
•
Fully programmable minimum coded unit (MCU)
•
Encode/decode support (non simultaneous)
•
Single clock Huffman coding and decoding
•
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
•
Support for single greyscale component
•
Ability to enable/disable header processing
•
Fully synchronous design
•
Configuration for high-speed decode mode
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.28
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten generalpurpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
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All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison
Timer
type
Timer
Highresolution HRTIM1
timer
Advanced
-control
TIM1,
TIM8
TIM2,
TIM5
TIM3,
TIM4
TIM12
Counter Counter Prescaler
resolution
type
factor
TIM15
TIM16,
TIM17
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Complementary
output
Max
Max
interface timer
clock
clock
(MHz)
(MHz)(1)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes
10
Yes
400
400
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
Yes
100
200
32-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
100
200
16-bit
Any
integer
Up,
Down, between 1
and
Up/down
65536
Yes
4
No
100
200
16-bit
Up
Any
integer
between 1
and
65536
No
2
No
100
200
Up
Any
integer
between 1
and
65536
No
1
No
100
200
Up
Any
integer
between 1
and
65536
Yes
2
1
100
200
Up
Any
integer
between 1
and
65536
Yes
1
1
100
200
16-bit
Up
General
purpose
TIM13,
TIM14
DMA
Capture/
request
compare
generation channels
16-bit
16-bit
16-bit
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Functional overview
Table 5. Timer feature comparison (continued)
Timer
type
DMA
Capture/
request
compare
generation channels
Complementary
output
Max
Max
interface timer
clock
clock
(MHz)
(MHz)(1)
Timer
Counter Counter Prescaler
resolution
type
factor
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and
65536
Yes
0
No
100
200
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32, 64,
128
No
0
No
100
200
1. The maximum timer clock is up to 400 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
3.28.1
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 400 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, burst mode controller,
push-pull and resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
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3.28.2
STM32H743xI
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge- or center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.28.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H743xI
devices (see Table 5 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or one-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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Functional overview
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.28.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.28.6
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / one-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.28.7
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.28.8
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
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3.29
STM32H743xI
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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Functional overview
Inter-integrated circuit interface (I2C)
STM32H743xI devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
3.31
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H743xI devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode are programmable and can
be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 6. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
16
1. X = supported.
3.32
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.33
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 50 Mbits/s in master and slave modes, in half-duplex, full-duplex
and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is
configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability.
3.34
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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3.35
STM32H743xI
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.36
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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Functional overview
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
3.38
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from STOP mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.39
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event
synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10 Kbytes message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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3.40
STM32H743xI
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s). OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG-HS1 in HS mode, an external PHY
device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
3.41
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
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The devices include the following features:
3.42
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.43
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
Breakpoint debugging
•
Code execution tracing
•
Software instrumentation
•
JTAG debug port
•
Serial-wire debug port
•
Trigger input and output
•
Serial-wire trace port
•
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
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46
Memory mapping
4
STM32H743xI
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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5
Pin descriptions
Pin descriptions
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
Figure 3. LQFP100 pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1
75 VDD
PE3 2
74 VSS
PE4 3
73 VCAP2
PE5 4
72 PA13
PE6 5
71 PA12
VBAT 6
70 PA11
PC13 7
69 PA10
PC14-OSC32_IN 8
68 PA9
PC15-OSC32_OUT 9
67 PA8
VSS 10
66 PC9
VDD 11
65 PC8
PH0-OSC_IN 12
64 PC7
100-pins
PH1-OSC_OUT 13
63 PC6
NRST 14
62 PD15
PC0 15
61 PD14
PC1 16
60 PD13
PC2_C 17
59 PD12
PC3_C 18
58 PD11
VSSA 19
57 PD10
VREF+ 20
56 PD9
VDDA 21
55 PD8
PA0-WKUP 22
54 PB15
PA1 23
53 PB14
PA2 24
52 PB13
PA3 25
51 PB12
VDD
VSS
VCAP1
PB11
PB10
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PA7
PC4
PA6
PA5
PA4
VDD
VSS
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSv41918V3
1. The above figure shows the package top view.
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93
Pin descriptions
STM32H743xI
Figure 4. TFBGA100 pinout
1
2
3
5
6
7
8
9
10
PB9
PB7
PB4
(NJTRST)
PB3(JTDO/
TRACESWO)
PA15(JTDI)
PA14(JTCKSWCLK)
PA13(JTMSSWDIO)
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
VSS
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
VDD
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
NRST
PC2_C
PE6
VSS
VSS
VSS
VCAP2
PD1
PC9
PC7
F
PC0
PC1
PC3_C
VDDLDO3
VDD
VDD33USB
PDR_ON
VCAP1
PC8
PC6
G
VSSA
PA0WKUP(PA0)
PA4
PC4
PB2
PE10
PE14
PD15
PD11
PB15
H
VDDA
PA1
PA5
PC5
PE7
PE11
PE15
PD14
PD10
PB14
J
VSS
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDD
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
A
PC14OSC32_IN
(PC14)
PC13
PE2
B
PC15OSC32_OUT
(PC15)
VBAT
C
PH0OSC_IN(PH0)
D
PH1OSC_OUT
(PH1)
E
4
MSv46177V1
1. The above figure shows the package top view.
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Pin descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
144-pins
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP1
VDD
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0-WKUP
PA1
PA2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 5. LQFP144 pinout
MSv41917V3
1. The above figure shows the package top view.
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93
Pin descriptions
STM32H743xI
Figure 6. UFBGA169 ballout
A
B
C
1
2
3
4
5
6
PE4
PE2
VDD
PI6
PB6
PI2
VDD
PE3
VSS
VDDLDO3
PB8
PB4
PI3
PE6
PE5
PDR_ON
PB9
PB5
PC15OSC32_
OUT
PC14OSC32_
IN
7
8
9
10
PG10
PD5
VDD
PG11
PD6
VSS
PG14
PG9
PD4
11
PC12
12
13
PC10
PI0
PC11
PA14
PI1
PD1
PA15
VSS
VDD
D
VDD
VSS
PC13
PE1
PE0
PB7
PG13
PD7
PD3
PD0
PA13
VDDLDO2
VCAP2
E
PI11
PI7
VBAT
PF1
PF3
BOOT0
PG15
PG12
PD2
PA10
PA9
PA8
PA12
F
PI13
PI12
PF0
PF2
PF5
PF7
PB3
PG4
PC6
PC7
PC9
PC8
PA11
G
VDD
VSS
PF4
PF6
PF9
NRST
PF13
PE7
PG6
PG7
PG8
VDD50_
USB
VDD33_
USB
H
PH0OSCIN
PH1OSCOUT
PF10
PF8
PJ1
PA4
PF14
PE8
PG2
PG3
PG5
VSS
VDD
J
PC0
PC1
VSSA
PJ0
PA0WKUP
PA7
PF15
PE9
PE14
PD11
PD13
PD15
PD14
K
PC3_C
PC2_C
PH4
PA1
PA6
PC4
PG0
PE13
PH10
PH12
PD9
PD10
PD12
L
VDDA
VREF+
PH5
PA5
PB1
PB2
PG1
PE12
PB10
PH11
PB13
VSS
VDD
M
VDD
VSS
PH3
VSS
PB0
PF11
VSS
PE10
PB11
VDDLDO1
VSS
PD8
PB15
N
PA2
PH2
PA3
VDD
PC5
PF12
VDD
PE11
PE15
VCAP1
VDD
PB12
PB14
MSv45339V3
1. The above figure shows the package top view.
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Pin descriptions
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0-WKUP
PA1
PA2
PH2
PH3
134
133
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PINOUT UNDER DEVELOPMENT
169
170
171
172
173
174
175
176
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
Figure 7. LQFP176 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-pins
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
PH4
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP1
VDD
PH6
PH7
PH8
PH9
PH10
PH11
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv41916V4
1. The above figure shows the package top view.
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Pin descriptions
STM32H743xI
Figure 8. UFBGA176+25 ballout
1
2
3
5
6
10
11
A
PE3
PE2
PE1
PE0
PB8
PB5
PG14
PG13
PB4
PB3
PD7
B
PE4
PE5
PE6
PB9
PB7
PB6
PG15
PG12
PG11
PG10
C
VBAT
PI7
PI6
PI5
VDD
PDR_ON
VDD
VDD
VDD
D
PC13
PI8
PI9
PI4
VSS
BOOT0
VSS
VSS
VSS
PF0
PI10
PI11
VSS
VDD
PH2
VSS
VSS
VSS
VSS
E
F
PC14OSC32_
IN
PC15OSC32_
OUT
4
7
8
9
12
13
14
PC12
PA15
PA14
PA13
15
PD6
PD0
PC11
PC10
PA12
PG9
PD5
PD1
PI3
PI2
PA11
PD4
PD3
PD2
PH15
PI1
PA10
PH13
PH14
PI0
PA9
VSS
VSS
VCAP2
PC9
PA8
G
PH0OSC_IN
VSS
VDD
PH3
VSS
VSS
VSS
VSS
VSS
VSS
VDD
PC8
PC7
H
PH1OSC_
OUT
PF2
PF1
PH4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
33USB
PG8
PC6
J
NRST
PF3
PF4
PH5
VSS
VSS
VSS
VSS
VSS
VDD
VDD
PG7
PG6
K
PF7
PF6
PF5
VDD
VSS
VSS
VSS
VSS
VSS
PH12
PG5
PG4
PG3
L
PF10
PF9
PF8
VSS
PH11
PH10
PD15
PG2
M
VSSA
PC0
PC1
PC2_C
PC3_C
PB2
PG1
VSS
VSS
VCAP1
PH6
PH8
PH9
PD14
PD13
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
VDD
VDD
VDD
PE13
PH7
PD12
PD11
PD10
P
VREF+
PA2
PA6
PA5
PC5
PF12
PF15
PE8
PE9
PE11
PE14
PB12
PB13
PD9
PD8
R
VDDA
PA3
PA7
PB1
PB0
PF11
PF14
PE7
PE10
PE12
PE15
PB10
PB11
PB14
PB15
MSv41912V3
1. The above figure shows the package top view.
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Pin descriptions
208-pins
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PI2
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PK2
PK1
PK0
VSS
VDD
PJ11
PJ10
PJ9
PJ8
PJ7
PJ6
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PA4
PA5
PA6
PA7
PC4
PC5
VDD
VSS
PB0
PB1
PB2
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP1
VSS
VDD
PJ5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
VDD
PB12
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PI12
PI13
PI14
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0-WKUP
PA1
PA2
PH2
PH3
PH4
PH5
PA3
VSS
VDD
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PI7
PI6
PI5
PI4
VDD
PDR_ON
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
PK7
PK6
PK5
PK4
PK3
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PJ15
PJ14
PJ13
PJ12
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
PI3
Figure 9. LQFP208 pinout
MSv41915V2
1. The above figure shows the package top view.
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Pin descriptions
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Figure 10. TFBGA240+25 ballout
1
2
3
4
5
6
7
8
9
10
11
VCAP3
PK5
PG10
PG9
PD5
12
13
14
15
16
17
PC10
PA15
PI1
PI0
VSS
A
VSS
PI6
PI5
PI4
PB5
VDD
LDO3
B
VBAT
VSS
PI7
PE1
PB6
VSS
PB4
PK4
PG11
PJ15
PD6
PD3
PC11
PA14
PI2
PH15
PH14
PE2
PE0
PB7
PB3
PK6
PK3
PG12
VSS
PD7
PC12
VSS
PI3
PA13
VSS
VDD
LDO2
PB9
PB8
PG15
PK7
PG14
PG13
PJ14
PJ12
PD2
PD0
PA10
PA9
PH13
VCAP2
VDD
VDD
PJ13
VDD
PD1
PC8
PC9
PA8
PA12
PA11
PC6
PG8
PG7
VDD33
USB
PG5
PG6
VSS
VDD50
USB
C
D
PC15- PC14OSC32_ OSC32_
OUT
IN
PE5
PE4
PE3
E
NC
PI9
PC13
PI8
PE6
F
NC
NC
PI10
PI11
VDD
G
PF2
NC
PF1
PF0
VDD
PI13
PI14
PDR_
ON
BOO
T0
PD4
PC7
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
H
PI12
J
PH0PH0OSC_
OSC_IN
OUT
VSS
PF5
PF4
VSS
VSS
VSS
VSS
VSS
VDD
PK0
K
NRST
PF6
PF7
PF8
VDD
VSS
VSS
VSS
VSS
VSS
VDD
L
VDDA
PC0
PF10
PF9
VDD
VSS
VSS
VSS
VSS
VSS
M
VREF+
PC1
PC2
PC3
VDD
N
VREF-
PH2
PA2
PA1
PA0
PJ0
VDD
VDD
PE10
VDD
VDD
P
VSSA
PH3
PH4
PH5
PI15
PJ1
PF13
PF14
PE9
PE11
R
PC2_C
PC3_C
PA6
VSS
PA7
PB2
PF12
VSS
PF15
T
PA0_C
PA1_C
PA5
PC4
PB1
PJ2
PF11
PG0
U
VSS
PA3
PA4
PC5
PB0
PJ3
PJ4
PG1
PF3
VDD
PG4
PG3
PG2
PK2
PK1
VSS
VSS
PJ11
VSS
NC
NC
VDD
PJ10
VSS
NC
NC
VDD
PJ9
VSS
NC
NC
VDD
PJ8
PJ7
PJ6
VSS
NC
PB10
PB11
PH10
PH11
PD15
PD14
VDD
PE12
PE15
PJ5
PH9
PH12
PD11
PD12
PD13
PE8
PE13
PH6
VSS
PH8
PB12
PB15
PD10
PD9
PE7
PE14
VCAP1
VDD
LDO1
PH7
PB13
PB14
PD8
VSS
MSv41911V1
1. The above figure shows the package top view.
54/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 7. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
I/O structure
Notes
Pin functions
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High Speed Low Voltage
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DocID030538 Rev 3
55/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
1
A3
1
A2
A2
1
1
C3
PE2
I/O
FT_h
-
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
2
B3
2
B2
A1
2
2
D3
PE3
I/O
FT_h
-
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
FMC_A19, EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM_DATIN3,
TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM_CKIN3,
TIM15_CH1, SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
-
3
4
C3
D3
3
4
A1
C3
B1
B2
3
4
3
4
D2
D1
PE4
PE5
I/O
I/O
FT_h
FT_h
5
E3
5
C2
B3
5
5
E5
PE6
I/O
FT_h
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
-
-
M4
H10
-
-
A1
VSS
S
-
-
-
-
-
-
-
A3
-
-
-
-
VDD
S
-
-
-
-
6
B2
6
E3
C1
6
6
B1
VBAT
S
-
-
-
-
-
-
-
-
J6
-
-
B2
VSS
-
-
-
-
-
-
-
-
-
D2
7
7
E4
PI8
I/O
FT
-
EVENTOUT
RTC_TAMP_2/
RTC_TS/
WKUP3
7
A2
7
D3
D1
8
8
E3
PC13
I/O
FT
-
EVENTOUT
RTC_TAMP_1/
RTC_TS/
WKUP2
-
-
-
-
J7
-
-
B6
VSS
-
-
-
-
-
56/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
8
C1
E1
9
9
C2
PC14OSC32_
IN(PC14)
I/O
I/O
Notes
LQFP144
A1
I/O structure
TFBGA100
8
Pin name
(function
after
reset)
Pin type
LQFP100
Pin/ball name
Alternate functions
Additional
functions
FT
-
EVENTOUT
OSC32_IN
FT
-
EVENTOUT
OSC32_
OUT
-
9
B1
9
B1
F1
10
10
C1
PC15OSC32_
OUT(PC1
5)
-
-
-
-
D3
11
11
E2
PI9
I/O
FT_h
-
UART4_RX, CAN1_RX,
FMC_D30, LCD_VSYNC,
EVENTOUT
-
-
-
-
E3
12
12
F3
PI10
I/O
FT_h
-
CAN1_RXFD,
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
-
-
E1
E4
13
13
F4
PI11
I/O
FT
-
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
-
C2
-
D2
F2
14
14
A17
VSS
S
-
-
-
-
-
D2
-
D1
F3
15
15
E6
-
-
-
-
-
-
VDD
S
-
-
-
-
-
E1
(1)
NC
-
-
-
-
-
-
F1(2)
NC
-
-
-
-
-
(3)
NC
-
-
-
-
-
-
-
-
-
-
-
-
G2
-
-
10
F3
E2
16
16
G4
PF0
I/O
FT_f
-
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
11
E4
H3
17
17
G3
PF1
I/O
FT_f
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
-
12
F4
H2
18
18
G1
PF2
I/O
FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
F2
-
-
19
H1
PI12
I/O
FT
-
ETH_TX_ER,
LCD_HSYNC,
EVENTOUT
-
-
-
-
F1
-
-
20
H2
PI13
I/O
FT
-
LCD_VSYNC,
EVENTOUT
-
-
-
-
-
-
-
21
H3
PI14
I/O
FT_h
-
LCD_CLK, EVENTOUT
-
-
-
13
E5
J2
19
22
H4
PF3
I/O
FT_
ha
-
FMC_A3, EVENTOUT
ADC3_INP5
-
-
14
G3
J3
20
23
J5
PF4
I/O
FT_
ha
-
FMC_A4, EVENTOUT
ADC3_INN5,
ADC3_INP9
-
-
15
F5
K3
21
24
J4
PF5
I/O
FT_
ha
-
FMC_A5, EVENTOUT
ADC3_INP4
DocID030538 Rev 3
57/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
10
-
16
B10
G2
22
25
C10
VSS
S
-
-
-
-
11
-
17
G1
G3
23
26
E9
VDD
S
-
-
-
-
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_INN4,
ADC3_INP8
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_INP3
-
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS,
SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
ADC3_INP2
-
-
-
-
-
-
18
19
20
G4
F6
H4
K2
K1
L3
24
25
26
27
28
29
K2
K3
K4
PF6
PF7
PF8
I/O
I/O
I/O
FT_
ha
FT_
ha
FT_
ha
Notes
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
-
21
G5
L2
27
30
L4
PF9
I/O
FT_
ha
-
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
-
22
H3
L1
28
31
L3
PF10
I/O
FT_
ha
-
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
ADC3_INN2,
ADC3_INP6
12
C1
23
H1
G1
29
32
J2
PH0OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
13
D1
24
H2
H1
30
33
J1
PH1OSC_OUT
(PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
14
E1
25
G6
J1
31
34
K1
NRST
I/O
RST
-
-
-
-
DFSDM_CKIN0,
DFSDM_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
INP10
15
F1
58/226
26
J1
M2
32
35
L2
PC0
I/O
FT_a
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
F2
-
17
(5)
-
(5)
-
M3
-
33
-
36
-
-
-
-
-
-
-
F3(5) 29(5) K1(5) M5(5) 35(5) 38(5)
M2
M3
(4)
R1(4)
PC1
PC2
PC2_C
M4(4)
PC3
R2(4)
PC3_C
I/O structure
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
-
J2
E2(5) 28(5) K2(5) M4(5) 34(5) 37(5)
-
18
27
Pin name
(function
after
reset)
Notes
16
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TRACED0, SAI1_D1,
DFSDM_DATIN0,
DFSDM_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
MDIOS_MDC,
EVENTOUT
ADC123_
INN10,
ADC123_
INP11,
RTC_TAMP_3/
WKUP5
FT_a
-
DFSDM_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_
INN11,
ADC123_
INP12
ANA TT_a
-
-
ADC3_INN1,
ADC3_INP0
FT_a
-
DFSDM_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC12_INN12,
ADC12_INP13
ANA TT_a
-
-
ADC3_INP1
I/O
I/O
I/O
FT_
ha
-
F5
30
-
G3
36
39
E11
VDD
S
-
-
-
-
-
E6
-
B3
J10
-
-
C13
VSS
S
-
-
-
-
19
G1
31
J3
M1
37
40
P1
VSSA
S
-
-
-
-
-
-
-
-
N1
-
-
N1
VREF-
S
-
-
-
-
20
(6)
-
32
L2
P1
38
41
M1
VREF+
S
-
-
-
-
21
H1
33
L1
R1
39
42
L1
VDDA
S
-
-
-
-
FT_a
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS_NSS,
UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC1_INP16,
WKUP0
ANA TT_a
-
-
ADC12_INN1,
ADC12_INP0
22
G2
34
J5
N3
40
43
N5(4)
PA0WKUP
(PA0)
-
-
-
-
-
-
-
T1(4)
PA0_C
I/O
DocID030538 Rev 3
59/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
H2
35
K4
N2
41
44
N4(4)
PA1
-
-
-
-
-
-
-
T2(4)
PA1_C
24
J2
36
N1
P2
42
45
N3
PA2
Notes
23
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
FT_
ha
-
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ANA TT_a
-
-
ADC12_INP1
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX,
SAI2_SCK_B,
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP1
ADC3_INP13
I/O
I/O
FT_a
Additional
functions
ADC1_INN16,
ADC1_INP17
-
-
-
N2
F4
43
46
N2
PH2
I/O
FT_
ha
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
K1
-
M1
-
-
-
F5
VDD
S
-
-
-
-
-
J1
-
M7
J8
-
-
C16
VSS
S
-
-
-
-
-
QUADSPI_BK2_IO1,
SAI2_MCK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
ADC3_INN13,
ADC3_INP14
-
-
-
M3
G4
44
47
P2
PH3
I/O
FT_
ha
-
-
-
K3
H4
45
48
P3
PH4
I/O
FT_fa
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
ADC3_INN14,
ADC3_INP15
-
-
-
L3
J4
46
49
P4
PH5
I/O
FT_fa
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
ADC3_INN15,
ADC3_INP16
-
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC12_INP15
25
K2
60/226
37
N3
R2
47
50
U2
PA3
I/O
FT_
ha
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
26
-
38
G2
K6
-
51
F2(3)
VSS
S
-
-
-
-
-
-
-
-
L4
48
-
-
VSS
S
-
-
-
-
27
-
39
-
K4
49
52
G5
VDD
S
-
-
-
-
-
TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_INP18,
DAC1_OUT1
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_INP3
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
ADC12_INN3,
SPI6_MOSI, TIM14_CH1,
ADC12_INP7,
ETH_MII_RX_DV/ETH_R
OPAMP1_VINM
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
-
DFSDM_CKIN2,
I2S1_MCK,
SPDIFRX_IN2,
ETH_MII_RXD0/ETH_R
MII_RXD0, FMC_SDNE0,
EVENTOUT
28
29
30
31
32
G3
H3
J3
K3
G4
40
41
42
43
44
H6
L4
K5
J6
K6
N4
P4
P3
R3
N5
50
51
52
53
54
53
54
55
56
57
U3
T3
R3
R5
T4
PA4
PA5
PA6
PA7
PC4
I/O
I/O
I/O
I/O
I/O
TT_a
TT_
ha
FT_a
TT_a
TT_a
DocID030538 Rev 3
Additional
functions
ADC12_INP4,
OPAMP1_
VOUT,
COMP_1_INM
61/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
ADC12_INN4,
ADC12_INP8,
OPAMP1_
VINM
33
H4
45
N5
P5
55
58
U4
PC5
I/O
TT_a
-
SAI1_D3,
DFSDM_DATIN2,
SPDIFRX_IN3, SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
FMC_SDCKE0,
COMP_1_OUT,
EVENTOUT
-
-
-
N4
-
-
59
G13
VDD
S
-
-
-
-
-
-
-
H12
J9
-
60
G16
VSS
S
-
-
-
-
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP_1_INP
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP_1_INM
COMP_1_INP,
RTC_OUT
34
35
J4
K4
46
47
M5
L5
R5
R4
56
57
61
62
U5
T5
PB0
PB1
I/O
I/O
FT_a
TT_u
36
G5
48
L6
M6
58
63
R6
PB2
I/O
FT_
ha
-
SAI1_D1,
DFSDM_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, ETH_TX_ER,
EVENTOUT
-
-
-
-
-
-
64
P5
PI15
I/O
FT
-
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
J4
-
-
65
N6
PJ0
I/O
FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
H5
-
-
66
P6
PJ1
I/O
FT
-
LCD_R2, EVENTOUT
-
-
-
-
-
-
-
67
T6
PJ2
I/O
FT
-
LCD_R3, EVENTOUT
-
-
-
-
-
-
-
68
U6
PJ3
I/O
FT
-
LCD_R4, EVENTOUT
-
-
-
-
-
-
-
69
U7
PJ4
I/O
FT
-
LCD_R5, EVENTOUT
-
-
-
49
M6
R6
59
70
T7
PF11
I/O
FT_a
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
ADC1_INP2
62/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
50
N6
P6
60
71
R7
PF12
I/O
FT_
ha
-
FMC_A6, EVENTOUT
ADC1_INN2,
ADC1_INP6
-
-
51
M11
M8
61
72
J3
VSS
S
-
-
-
-
-
-
52
-
N8
62
73
H5
VDD
S
-
-
-
-
-
-
53
G7
N6
63
74
P7
PF13
I/O
FT_
ha
-
DFSDM_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
ADC2_INP2
-
-
54
H7
R7
64
75
P8
PF14
I/O
FT_
fha
-
DFSDM_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INN2,
ADC2_INP6
-
-
55
J7
P7
65
76
R9
PF15
I/O
FT_fh
-
I2C4_SDA, FMC_A9,
EVENTOUT
-
-
-
56
K7
N7
66
77
T8
PG0
I/O
FT_h
-
FMC_A10, EVENTOUT
-
-
-
-
M2
F6
-
-
J16
VSS
S
-
-
-
-
-
-
-
A10
-
-
-
H13
VDD
S
-
-
-
-
-
-
57
L7
M7
67
78
U8
PG1
I/O
TT_h
-
FMC_A11, EVENTOUT
OPAMP2_
VINM
-
TIM1_ETR,
DFSDM_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
OPAMP2_
VOUT,
COMP_2_INM
-
TIM1_CH1N,
DFSDM_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP_2_OUT,
EVENTOUT
OPAMP2_
VINM
OPAMP2_VINP,
COMP_2_INP
37
38
H5
J5
58
59
G8
H8
R8
P8
68
69
79
80
U9
T9
PE7
PE8
I/O
I/O
TT_
ha
TT_
ha
Additional
functions
39
K5
60
J8
P9
70
81
P9
PE9
I/O
TT_
ha
-
TIM1_CH1,
DFSDM_CKOUT,
UART7_RTS,
QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
-
-
61
C12
M9
71
82
J17
VSS
S
-
-
-
-
-
-
62
C13
N9
72
83
J13
VDD
S
-
-
-
-
DocID030538 Rev 3
63/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
41
42
G6
H6
J6
64
65
M8
N8
L8
R9
P10
R10
73
74
75
84
85
86
N9
P10
R10
PE10
PE11
PE12
I/O structure
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
63
Pin name
(function
after
reset)
I/O
FT_
ha
I/O
FT_
ha
I/O
FT_h
Notes
40
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2N,
DFSDM_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
COMP_2_INM
-
TIM1_CH2,
DFSDM_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP_2_INP
-
TIM1_CH3N,
DFSDM_DATIN5,
SPI4_SCK,
SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP_1_OUT, LCD_B4,
EVENTOUT
-
-
43
K6
66
K8
N11
76
87
T10
PE13
I/O
FT_h
-
TIM1_CH3,
DFSDM_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP_2_OUT, LCD_DE,
EVENTOUT
-
-
-
L12
F7
-
-
K15
VSS
S
-
-
-
-
-
-
-
H13
-
-
-
K13
VDD
S
-
-
-
-
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
-
-
TIM1_BKIN,
HDMI__TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
-
-
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
44
45
46
G7
H7
J7
64/226
67
68
69
J9
N9
L9
P11
R11
R12
77
78
79
88
89
90
U10
R11
P11
PE14
PE15
PB10
I/O
I/O
I/O
FT_h
FT_h
FT_f
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
47
K7
70
M9
R13
80
91
P12
PB11
I/O
FT_f
-
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
48
F8
71
N10
M10
81
92
U11
VCAP1
S
-
-
-
-
49
E4
-
-
K7
-
93
L15
VSS
S
-
-
-
-
-
-
-
M10
-
-
-
U12
VDDLDO1
S
-
-
-
-
50
-
72
M1
N10
82
94
L13
VDD
S
-
-
-
-
-
-
-
-
-
-
95
R12
PJ5
I/O
FT
-
LCD_R6, EVENTOUT
-
-
-
-
-
-
M11
83
96
T11
PH6
I/O
FT
-
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
-
-
N12
84
97
U13
PH7
I/O
FT_fa
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
-
-
-
-
M12
85
98
T13
PH8
I/O
FT_fh
a
-
-
-
-
F8
-
-
M15
VSS
S
-
-
-
-
-
-
-
L13
-
-
-
M13
VDD
S
-
-
-
-
-
-
-
-
M13
86
99
R13
PH9
I/O
FT_h
-
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
-
-
-
-
K9
L13
87
100
P13
PH10
I/O
FT_h
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
-
-
-
L10
L12
88
101
P14
PH11
I/O
FT_fh
-
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
DocID030538 Rev 3
65/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
-
-
-
K10
K12
89
102
R14
PH12
I/O
FT_fh
-
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
-
-
-
-
H12
90
-
N16
VSS
S
-
-
-
-
-
-
-
N11
J12
91
103
P17
VDD
S
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM_DATIN1,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
-
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM_CKIN1,
USART3_CTS_NSS,
CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, UART5_TX,
EVENTOUT
OTG_HS_
VBUS
-
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM_DATIN2,
USART3_RTS,
UART4_RTS,
SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
-
-
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
-
51
52
53
54
K8
J8
H10
G10
66/226
73
74
75
76
N12
L11
N13
M13
P12
P13
R14
R15
92
93
94
95
104
105
106
107
T14
U14
U15
T15
PB12
PB13
PB14
PB15
I/O
I/O
I/O
I/O
FT_u
FT_u
FT_u
FT_u
DocID030538 Rev 3
Notes
LQFP100
Pin/ball name
Alternate functions
Additional
functions
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
55
56
K9
J9
77
78
M12
K11
P15
P14
96
97
108
109
U16
T17
PD8
PD9
I/O
I/O
FT_h
FT_h
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
DFSDM_CKIN3,
SAI3_SCK_B,
USART3_TX,
SPDIFRX_IN1,
FMC_D13/FMC_DA13,
EVENTOUT
-
-
DFSDM_DATIN3,
SAI3_SD_B,
USART3_RX,
CAN2_RXFD,
FMC_D14/FMC_DA14,
EVENTOUT
-
-
57
H9
79
K12
N15
98
110
T16
PD10
I/O
FT_h
-
DFSDM_CKOUT,
SAI3_FS_B,
USART3_CK,
CAN2_TXFD,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
-
-
N7
-
-
-
N12
VDD
S
-
-
-
-
-
-
-
-
F9
-
-
U17
VSS
S
-
-
-
-
-
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS_NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
-
58
59
G9
K10
80
81
J10
K13
N14
N13
99
100
111
112
R15
R16
PD11
PD12
I/O
I/O
FT_h
FT_fh
60
J10
82
J11
M15
101
113
R17
PD13
I/O
FT_fh
-
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
-
83
-
K8
102
114
T12
VSS
S
-
-
-
-
-
-
84
-
J13
103
115
N11
VDD
S
-
-
-
-
-
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
-
61
H8
85
J13
M14
104
116
P16
PD14
I/O
FT_h
DocID030538 Rev 3
67/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
L14
105
117
P15
PD15
I/O
FT_h
-
-
-
-
-
-
-
118
N15
PJ6
I/O
FT
-
TIM8_CH2, LCD_R7,
EVENTOUT
-
-
-
-
-
-
-
119
N14
PJ7
I/O
FT
-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT
-
-
-
-
-
-
-
-
N10
VDD
S
-
-
-
-
-
-
F10
-
-
R8
VSS
S
-
-
-
-
-
-
-
-
120
N13
PJ8
I/O
FT
-
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
-
-
-
-
-
-
121
M14
PJ9
I/O
FT
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
-
-
-
-
-
-
122
L14
PJ10
I/O
FT
-
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
-
-
-
-
-
-
123
K14
PJ11
I/O
FT
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
-
-
-
-
-
124
N8
VDD
S
-
-
-
-
G6
-
125
U1
VSS
S
-
-
-
-
-
-
-
-
-
-
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
(1)
NC
-
-
-
-
-
-
-
-
-
-
-
-
L7
-
-
-
-
-
-
LQFP208
J12
LQFP176
86
UFBGA169
G8
LQFP144
62
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS,
FMC_D1/FMC_DA1,
EVENTOUT
TFBGA100
Alternate functions
LQFP100
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
UFBGA176+25
Pin/ball name
(1)
M16
(1)
M17
-
-
VSS
S
-
-
-
-
-
L16
(1)
NC
-
-
-
-
-
L17(1)
NC
-
-
-
-
-
NC
-
-
-
-
-
(1)
NC
-
-
-
-
-
L8
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
68/226
N17
-
Additional
functions
K16
(1)
K17
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin/ball name
-
-
-
-
-
-
126
J14
PK0
I/O
FT
-
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
-
-
-
-
-
-
127
J15
PK1
I/O
FT
-
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
-
Alternate functions
Additional
functions
-
-
-
-
-
-
128
H17
PK2
I/O
FT
-
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
-
87
H9
L15
106
129
H16
PG2
I/O
FT_h
-
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
-
-
-
88
H10
K15
107
130
H15
PG3
I/O
FT_h
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
-
-
-
-
G7
-
-
-
VSS
S
-
-
-
-
-
-
-
-
-
-
-
N7
VDD
S
-
-
-
-
-
-
89
F8
K14
108
131
H14
PG4
I/O
FT_h
-
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
-
-
-
90
H11
K13
109
132
G14
PG5
I/O
FT_h
-
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
-
-
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
-
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
-
-
-
-
-
91
92
G9
G10
J15
J14
110
111
133
134
G15
F16
PG6
PG7
I/O
I/O
FT_h
FT_h
-
-
93
G11
H14
112
135
F15
PG8
I/O
FT_h
-
TIM8_ETR, SPI6_NSS,
USART6_RTS,
SPDIFRX_IN2,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
-
94
-
G12
113
136
-
VSS
S
-
-
-
DocID030538 Rev 3
69/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin type
I/O structure
-
-
-
G12
-
-
-
G17
VDD50
USB
S
-
-
-
-
-
F6
95
G13
H13
114
137
F17
VDD33
USB
S
-
-
-
-
-
-
-
-
-
-
-
M5
VDD
S
-
-
-
-
-
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
SWPMI_IO
-
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS,
FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
63
64
65
F10
E10
F9
96
97
98
F9
F10
F12
H15
G15
G14
115
116
117
138
139
140
F14
F13
E13
Pin name
(function
after
reset)
PC6
PC7
PC8
I/O
I/O
I/O
FT_h
FT_h
FT_h
Notes
LQFP100
Pin/ball name
Alternate functions
Additional
functions
66
E9
99
F11
F14
118
141
E14
PC9
I/O
FT_fh
-
-
-
-
-
G8
-
-
-
VSS
S
-
-
-
-
-
-
-
-
-
-
L5
VDD
S
-
-
-
70/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
67
68
69
70
D9
C9
D10
C10
100
101
102
103
E12
E11
E10
F13
F15
E15
D15
C15
119
120
121
122
142
143
144
145
E15
D15
D14
E17
PA8
PA9
PA10
PA11
I/O
I/O
I/O
I/O
FT_
fha
FT_u
FT_u
FT_u
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
-
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
CAN1_RXFD,
ETH_TX_ER, DCMI_D0,
LCD_R5, EVENTOUT
OTG_FS_VBUS
-
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
CAN1_TXFD,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
-
-
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS_NSS,
CAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
-
-
-
71
B10
104
E13
B15
123
146
E16
PA12
I/O
FT_u
-
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
72
A10
105
D11
A15
124
147
C15
PA13(JTM
S-SWDIO)
I/O
FT
-
JTMS-SWDIO,
EVENTOUT
DocID030538 Rev 3
71/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
73
E7
106
D13
F13
125
148
D17
VCAP2
S
-
-
-
-
74
E5
107
-
F12
126
149
-
VSS
S
-
-
-
-
-
-
-
D12
-
-
-
C17
VDDLDO2
-
-
-
-
75
-
108
-
G13
127
150
K5
VDD
S
-
-
-
-
-
-
-
-
E12
128
151
D16
PH13
I/O
FT_h
-
TIM8_CH1N, UART4_TX,
CAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
Notes
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
-
-
-
E13
129
152
B17
PH14
I/O
FT_h
-
TIM8_CH2N,
UART4_RX, CAN1_RX,
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
-
-
-
-
D13
130
153
B16
PH15
I/O
FT_h
-
TIM8_CH3N,
CAN1_TXFD, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
-
-
-
-
A13
E14
131
154
A16
PI0
I/O
FT_h
-
TIM5_CH4,
SPI2_NSS/I2S2_WS,
CAN1_RXFD, FMC_D24,
DCMI_D13, LCD_G5,
EVENTOUT
-
-
-
-
G9
-
-
-
VSS
S
-
-
-
-
-
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
-
-
-
-
B13
D14
132
155
A15
PI1
I/O
FT_h
-
-
-
A6
C14
133
156
B15
PI2
I/O
FT_h
-
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
-
-
B7
C13
134
157
C14
PI3
I/O
FT_h
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
-
-
-
D9
135
-
-
VSS
S
-
-
-
-
-
-
-
-
C9
136
158
-
VDD
S
-
-
-
-
76
A9
109
B12
A14
137
159
B14
PA14
(JTCKSWCLK)
I/O
FT
-
JTCK-SWCLK,
EVENTOUT
-
72/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
78
79
A8
B9
B8
111
112
C11
A12
B11
A13
B14
B13
138
139
140
160
161
162
A14
A13
B13
PA15
(JTDI)
PC10
PC11
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
110
Pin name
(function
after
reset)
FT
FT_
ha
FT_h
Notes
77
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS, UART4_RTS,
UART7_TX, EVENTOUT
-
-
HRTIM_EEV1,
DFSDM_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
HRTIM_FLT2,
DFSDM_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
-
80
C8
113
A11
A12
141
163
C12
PC12
I/O
FT_h
-
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
-
-
-
-
G10
-
-
-
VSS
S
-
-
-
-
-
DFSDM_CKIN6,
SAI3_SCK_A,
UART4_RX, CAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
-
-
-
81
D8
114
D10
B12
142
164
D13
PD0
I/O
FT_h
82
E8
115
C10
C12
143
165
E12
PD1
I/O
FT_h
-
DFSDM_DATIN6,
SAI3_SD_A, UART4_TX,
CAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
83
B7
116
E9
D12
144
166
D12
PD2
I/O
FT_h
-
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
DocID030538 Rev 3
73/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
84
85
C7
D7
117
118
D9
C9
D11
D10
145
146
167
168
B12
A12
PD3
PD4
I/O
I/O
FT_h
FT_h
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
DFSDM_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS_NSS,
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
-
-
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS,
CAN1_RXFD,
FMC_NOE, EVENTOUT
-
-
86
B6
119
A9
C11
147
169
A11
PD5
I/O
FT_h
-
HRTIM_EEV3,
USART2_TX,
CAN1_TXFD,
FMC_NWE, EVENTOUT
-
-
120
-
D8
148
170
R4
VSS
S
-
-
-
-
-
-
121
-
C8
149
171
-
VDD
S
-
-
-
-
-
SAI1_D1,
DFSDM_CKIN4,
DFSDM_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
SAI4_SD_A,
CAN2_RXFD, SAI4_D1,
SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
-
-
87
C6
122
B9
B11
150
172
B11
PD6
I/O
FT_h
88
D6
123
D8
A11
151
173
C11
PD7
I/O
FT_h
-
DFSDM_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM_CKIN1,
USART2_CK,
SPDIFRX_IN0,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
-
-
-
-
-
174
D11
PJ12
I/O
FT
-
TRGOUT, LCD_G3,
LCD_B0, EVENTOUT
-
-
-
-
-
-
-
175
E10
PJ13
I/O
FT
-
LCD_B4, LCD_B1,
EVENTOUT
-
-
-
-
-
-
-
176
D10
PJ14
I/O
FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
-
-
177
B10
PJ15
I/O
FT
-
LCD_B3, EVENTOUT
-
-
-
-
-
H6
-
-
-
VSS
S
-
-
-
-
-
-
-
A7
-
-
-
-
VDD
S
-
-
-
-
74/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
-
-
-
-
-
-
-
-
-
-
124
125
126
127
128
C8
A8
B8
E8
D7
C10
B10
B9
B8
A8
152
153
154
155
156
178
179
180
181
182
A10
A9
B9
C9
D9
PG9
PG10
PG11
PG12
PG13
I/O
I/O
I/O
I/O
I/O
FT_h
FT_h
FT_h
FT_h
FT_h
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX_IN3,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
-
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
-
-
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX_IN0,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
-
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS,
SPDIFRX_IN1, LCD_B4,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
-
-
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS_NSS,
ETH_MII_TXD0/ETH_RM
II_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
-
-
-
129
C7
A7
157
183
D8
PG14
I/O
FT_h
-
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
-
130
-
D7
158
184
-
VSS
S
-
-
-
-
-
-
131
-
C7
159
185
-
VDD
S
-
-
-
-
DocID030538 Rev 3
75/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
-
-
-
-
186
C8
PK3
I/O
FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
-
-
187
B8
PK4
I/O
FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
-
-
188
A8
PK5
I/O
FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
-
-
189
C7
PK6
I/O
FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
-
-
190
D7
PK7
I/O
FT
-
LCD_DE, EVENTOUT
-
-
-
-
-
H7
-
-
-
VSS
S
-
-
-
-
-
-
132
E7
B7
160
191
D6
PG15
I/O
FT_h
-
USART6_CTS_NSS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
SDMMC2_D2,
UART7_RX, EVENTOUT
-
-
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
-
-
-
89
90
A7
A6
133
134
F7
B6
A10
A9
161
162
192
193
C6
B7
PB3(JTDO
/TRACES
WO)
PB4(NJTR
ST)
I/O
I/O
FT
FT
91
C5
135
C6
A6
163
194
A5
PB5
I/O
FT
-
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI, CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
-
-
-
H8
-
-
-
VSS
S
-
-
-
76/226
DocID030538 Rev 3
Additional
functions
STM32H743xI
Pin descriptions
Table 8. STM32H743xI pin/ball definition (continued)
92
B5
136
A5
B6
164
195
B5
PB6
I/O
FT_f
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, HDMI_CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX,
CAN2_TX,
QUADSPI_BK1_NCS,
DFSDM_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
-
PVD_IN
93
A5
137
D6
B5
165
196
C5
PB7
I/O
FT_fa
-
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
CAN2_TXFD,
DFSDM_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
94
D5
138
E6
D6
166
197
E8
BOOT0
I
B
-
-
VPP
-
TIM16_CH1, TIM4_CH3,
DFSDM_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX, CAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
TIM17_CH1, TIM4_CH4,
DFSDM_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX, CAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
95
96
B4
A4
139
140
B5
C5
A5
B4
167
168
198
199
D5
D4
PB8
PB9
I/O
I/O
FT_fh
FT_fh
DocID030538 Rev 3
77/226
93
Pin descriptions
STM32H743xI
Table 8. STM32H743xI pin/ball definition (continued)
97
D4
141
D5
A4
169
200
C4
PE0
I/O
FT_h
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
TFBGA240 +25
LQFP208
LQFP176
UFBGA176+25
UFBGA169
LQFP144
TFBGA100
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
CAN1_RXFD,
SAI2_MCK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
-
98
C4
142
D4
A3
170
201
B4
PE1
I/O
FT_h
-
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
CAN1_TXFD,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-
-
-
-
-
-
A7
VCAP3
S
-
-
-
-
99
-
-
-
D5
-
202
-
VSS
S
-
-
-
-
-
F7
143
C4
C6
171
203
E7
PDR_ON
S
-
-
-
-
-
F4
-
B4
-
-
-
A6
VDDLDO3
S
-
-
-
-
100
-
144
-
C5
172
204
-
VDD
S
-
-
-
-
-
TIM8_BKIN,
SAI2_MCK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
-
-
-
-
-
D4
173
205
A4
PI4
I/O
FT_h
-
-
-
-
C4
174
206
A3
PI5
I/O
FT_h
-
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
-
-
A4
C3
175
207
A2
PI6
I/O
FT_h
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
-
E2
C2
176
208
B3
PI7
I/O
FT_h
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
-
-
-
-
-
H9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
K9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
K10
-
-
-
VSS
S
-
-
-
-
1. This ball should remain floating.
2. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
78/226
DocID030538 Rev 3
STM32H743xI
Pin descriptions
3. This ball should be connected to VSS.
4. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
5. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
6. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package,
this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is
not available and must be kept disabled
DocID030538 Rev 3
79/226
93
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/S
PDIFRX
SAI4/
FDCAN1/2/
TIM13/14/Q
UADSPI/F
MC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PA0
-
TIM2_CH1/
TIM2_ETR
TIM5_CH1
TIM8_ETR
TIM15_BKIN
-
-
USART2_
CTS_NSS
UART4_TX
SDMMC2_
CMD
SAI2_SD_B
ETH_MII_
CRS
-
-
-
EVENTOUT
PA1
-
TIM2_CH2
TIM5_CH2
LPTIM3_
OUT
TIM15_
CH1N
-
-
USART2_
RTS
UART4_RX
QUADSPI_
BK1_IO3
SAI2_MCK_
B
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
-
-
LCD_R2
EVENTOUT
PA2
-
TIM2_CH3
TIM5_CH3
LPTIM4_
OUT
TIM15_CH1
-
-
USART2_
TX
SAI2_SCK_
B
-
-
ETH_MDIO
MDIOS_
MDIO
-
LCD_R1
EVENTOUT
PA3
-
TIM2_CH4
TIM5_CH4
LPTIM5_
OUT
TIM15_CH2
-
-
USART2_
RX
-
LCD_B2
OTG_HS_
ULPI_D0
ETH_MII_
COL
-
-
LCD_B5
EVENTOUT
PA4
-
-
TIM5_ETR
-
-
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART2_
CK
SPI6_NSS
-
-
-
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENTOUT
PA5
-
TIM2_CH1/
TIM2_ETR
-
TIM8_
CH1N
-
SPI1_SCK
/I2S1_CK
-
-
SPI6_SCK
-
OTG_HS_
ULPI_CK
-
-
-
LCD_R4
EVENTOUT
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_MISO
/I2S1_SDI
-
-
SPI6_MISO
TIM13_CH
1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
DCMI_PIX
CLK
LCD_G2
EVENTOUT
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_CH1
N
-
SPI1_MOSI
/I2S1_SDO
-
-
SPI6_MOSI
TIM14_CH
1
-
ETH_MII_
RX_DV/
ETH_RMII_
CRS_DV
FMC_SDN
WE
-
-
EVENTOUT
PA8
MCO1
TIM1_CH1
HRTIM_CH
B2
TIM8_BKIN
2
I2C3_SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
UART7_RX
TIM8_BKIN
2_COMP12
LCD_B3
LCD_R6
EVENTOUT
PA9
-
TIM1_CH2
HRTIM_CH
C1
LPUART1_
TX
I2C3_SMBA
SPI2_SCK/
I2S2_CK
-
USART1_
TX
-
CAN1_RXF
D
-
ETH_TX_
ER
-
DCMI_D0
LCD_R5
EVENTOUT
PA10
-
TIM1_CH3
HRTIM_CH
C2
LPUART1_
RX
-
-
-
USART1_
RX
-
CAN1_
TXFD
OTG_FS_ID
MDIOS_
MDIO
LCD_B4
DCMI_D1
LCD_B1
EVENTOUT
PA11
-
TIM1_CH4
HRTIM_CH
D1
LPUART1_
CTS
-
SPI2_NSS
/I2S2_WS
UART4_RX
USART1_
CTS_NSS
-
CAN1_RX
OTG_FS_
DM
-
-
-
LCD_R4
EVENTOUT
PA12
-
TIM1_ETR
HRTIM_CH
D2
LPUART1_
RTS
-
SPI2_SCK/
I2S2_CK
UART4_TX
USART1_
RTS
SAI2_FS_B
CAN1_TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENTOUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
DocID030538 Rev 3
STM32H743xI
SYS
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM
Port
Port A
AF1
Pin descriptions
80/226
Table 9. Port A alternate functions
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM
PA14
JTCKSWCLK
-
-
PA15
JTDI
TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1
Port A
Port
AF1
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/S
PDIFRX
SAI4/
FDCAN1/2/
TIM13/14/Q
UADSPI/F
MC/
SDMMC2/
LCD/
SPDIFRX
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
-
HDMI_CEC
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
SPI6_NSS
UART4_
RTS
-
-
UART7_TX
-
-
-
EVENTOUT
STM32H743xI
Table 9. Port A alternate functions (continued)
AF0
Table 10. Port B alternate functions
AF0
Port B
DocID030538 Rev 3
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCM
I/LCD/
COMP
UART5/
LCD
SYS
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2
N
-
-
DFSDM_CK
OUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
-
-
LCD_G1
EVENTOUT
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3
N
-
-
DFSDM_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
-
-
LCD_G0
EVENTOUT
PB2
-
-
SAI1_D1
-
DFSDM_
CKIN1
-
SAI1_SD_A
SPI3_
MOSI/I2S3_
SDO
SAI4_SD_
A
QUADSPI_
CLK
SAI4_D1
ETH_TX_
ER
-
-
-
EVENTOUT
PB3
JTDO/TRA
CESWO
TIM2_CH2
HRTIM_
FLT4
-
-
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
-
SPI6_SCK
SDMMC2_
D2
-
UART7_RX
-
-
-
EVENTOUT
PB4
NJTRST
TIM16_
BKIN
TIM3_CH1
HRTIM_EE
V6
-
SPI1_MISO/
I2S1_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/I
2S2_WS
SPI6_
MISO
SDMMC2_
D3
-
UART7_TX
-
-
-
EVENTOUT
PB5
-
TIM17_
BKIN
TIM3_CH2
HRTIM_
EEV7
I2C1_SMBA
SPI1_MOSI/
I2S1_SDO
I2C4_SMBA
SPI3_MOSI/
I2S3_SDO
SPI6_
MOSI
CAN2_RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_
SDCKE1
DCMI_D1
0
UART5_
RX
EVENTOUT
PB6
-
TIM16_CH1
N
TIM4_CH1
HRTIM_
EEV8
I2C1_SCL
HDMI_CEC
I2C4_SCL
USART1_
TX
LPUART1_
TX
CAN2_TX
QUADSPI_
BK1_NCS
DFSDM_
DATIN5
FMC_SDNE
1
DCMI_D5
UART5_
TX
EVENTOUT
PB7
-
TIM17_CH1
N
TIM4_CH2
HRTIM_
EEV9
I2C1_SDA
-
I2C4_SDA
USART1_
RX
LPUART1_
RX
CAN2_
TXFD
-
DFSDM_
CKIN5
FMC_NL
DCMI_
VSYNC
-
EVENTOUT
PB8
-
TIM16_CH1
TIM4_CH3
DFSDM_
CKIN7
I2C1_SCL
-
I2C4_SCL
SDMMC1_
CKIN
UART4_RX
CAN1_RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4
DCMI_D6
LCD_B6
EVENTOUT
81/226
Pin descriptions
AF5
Port
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCM
I/LCD/
COMP
UART5/
LCD
SYS
PB9
-
TIM17_CH1
TIM4_CH4
DFSDM_
DATIN7
I2C1_SDA
SPI2_NSS/
I2S2_WS
I2C4_SDA
SDMMC1_
CDIR
UART4_TX
CAN1_TX
SDMMC2_
D5
I2C4_SMB
A
SDMMC1_
D5
DCMI_D7
LCD_B7
EVENTOUT
PB10
-
TIM2_CH3
HRTIM_
SCOUT
LPTIM2_IN
1
I2C2_SCL
SPI2_SCK/
I2S2_CK
DFSDM_
DATIN7
USART3_
TX
-
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
-
-
LCD_G4
EVENTOUT
PB11
-
TIM2_CH4
HRTIM_
SCIN
LPTIM2_
ETR
I2C2_SDA
-
DFSDM_
CKIN7
USART3_
RX
-
-
OTG_HS_
ULPI_D4
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
-
LCD_G5
EVENTOUT
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS/
I2S2_WS
DFSDM_
DATIN1
USART3_
CK
-
CAN2_RX
OTG_HS_
ULPI_D5
ETH_MII_
TXD0/ETH_
RMII_TXD0
OTG_HS_
ID
TIM1_
BKIN_
COMP12
UART5_
RX
EVENTOUT
PB13
-
TIM1_CH1N
-
LPTIM2_
OUT
-
SPI2_SCK/
I2S2_CK
DFSDM_CK
IN1
USART3_
CTS_NSS
-
CAN2_TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/ETH_
RMII_TXD1
-
-
UART5_
TX
EVENTOUT
PB14
-
TIM1_CH2N
TIM12_CH
1
TIM8_
CH2N
USART1_TX
SPI2_MISO/
I2S2_SDI
DFSDM_
DATIN2
USART3_
RTS
UART4_
RTS
SDMMC2_
D0
-
-
OTG_HS_
DM
-
-
EVENTOUT
PB15
RTC_
REFIN
TIM1_CH3N
TIM12_CH
2
TIM8_CH3
N
USART1_RX
SPI2_MOSI/
I2S2_SDO
DFSDM_CK
IN2
-
UART4_
CTS
SDMMC2_
D1
-
-
OTG_HS_
DP
-
-
EVENTOUT
Port B
Port
AF1
Pin descriptions
82/226
Table 10. Port B alternate functions (continued)
AF0
DocID030538 Rev 3
STM32H743xI
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PC0
-
-
-
DFSDM_
CKIN0
-
-
DFSDM_
DATIN4
-
SAI2_FS_B
-
OTG_HS_
ULPI_STP
-
FMC_
SDNWE
-
LCD_R5
EVENTOUT
PC1
TRACED0
-
SAI1_D1
DFSDM_
DATIN0
DFSDM_
CKIN4
SPI2_
MOSI/I2S2
_SDO
SAI1_SD_A
-
SAI4_SD_
A
SDMMC2_
CK
SAI4_D1
ETH_MDC
MDIOS_
MDC
-
-
EVENTOUT
PC2
-
-
-
DFSDM_
CKIN1
-
SPI2_
MISO/I2S2
_SDI
DFSDM_CK
OUT
-
-
-
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDNE
0
-
-
EVENTOUT
PC3
-
-
-
DFSDM_
DATIN1
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SDCK
E0
-
-
EVENTOUT
PC4
-
-
-
DFSDM_
CKIN2
-
I2S1_MCK
-
-
-
SPDIFRX_
IN2
-
ETH_MII_
RXD0/ETH_
RMII_RXD0
FMC_SDNE
0
-
-
EVENTOUT
PC5
-
-
SAI1_D3
DFSDM_
DATIN2
-
-
-
-
SPDIFRX_
IN3
SAI4_D3
ETH_MII_
RXD1/ETH_
RMII_RXD1
FMC_SDCK
E0
COMP_1_
OUT
-
EVENTOUT
PC6
-
HRTIM_CH
A1
TIM3_CH1
TIM8_CH1
DFSDM_
CKIN3
I2S2_MCK
-
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1_
D6
DCMI_D0
LCD_
HSYNC
EVENTOUT
PC7
TRGIO
HRTIM_CH
A2
TIM3_CH2
TIM8_CH2
DFSDM_
DATIN3
-
I2S3_MCK
USART6_
RX
SDMMC1_
D123DIR
FMC_NE1
SDMMC2_
D7
SWPMI_TX
SDMMC1_
D7
DCMI_D1
LCD_G6
EVENTOUT
PC8
TRACED1
HRTIM_CH
B1
TIM3_CH3
TIM8_CH3
-
-
-
USART6_
CK
UART5_
RTS
FMC_NE2/
FMC_NCE
-
SWPMI_RX
SDMMC1_
D0
DCMI_D2
-
EVENTOUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
UART5_
CTS
QUADSPI_
BK1_IO0
LCD_G3
SWPMI_
SUSPEND
SDMMC1_
D1
DCMI_D3
LCD_B2
EVENTOUT
PC10
-
-
HRTIM_
EEV1
DFSDM_
CKIN5
-
-
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_TX
QUADSPI_
BK1_IO1
-
-
SDMMC1_
D2
DCMI_D8
LCD_R2
EVENTOUT
PC11
-
-
HRTIM_
FLT2
DFSDM_
DATIN5
-
-
SPI3_MISO/
I2S3_SDI
USART3_
RX
UART4_RX
QUADSPI_
BK2_NCS
-
-
SDMMC1_
D3
DCMI_D4
-
EVENTOUT
PC12
TRACED3
-
HRTIM_
EEV2
-
-
-
SPI3_MOSI/
I2S3_SDO
USART3_
CK
UART5_TX
-
-
-
SDMMC1_
CK
DCMI_D9
-
EVENTOUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
DocID030538 Rev 3
83/226
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port C
AF1
STM32H743xI
Table 11. Port C alternate functions
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PC14
-
-
-
PC15
-
-
-
Port C
Port
AF1
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
Pin descriptions
84/226
Table 11. Port C alternate functions (continued)
AF0
DocID030538 Rev 3
STM32H743xI
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PD0
-
-
-
DFSDM_
CKIN6
-
-
SAI3_SCK_
A
-
UART4_RX
CAN1_RX
-
-
FMC_D2/
FMC_DA2
-
-
EVENTOUT
PD1
-
-
-
DFSDM_
DATIN6
-
-
SAI3_SD_A
-
UART4_TX
CAN1_TX
-
-
FMC_D3/
FMC_DA3
-
-
EVENTOUT
PD2
TRACED2
-
TIM3_ETR
-
-
-
-
-
UART5_RX
-
-
-
SDMMC1_
CMD
DCMI_D11
-
EVENTOUT
PD3
-
-
-
DFSDM_
CKOUT
-
SPI2_SCK/
I2S2_CK
-
USART2_
CTS_NSS
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENTOUT
PD4
-
-
HRTIM_
FLT3
-
-
-
SAI3_FS_A
USART2_
RTS
-
CAN1_
RXFD
-
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
HRTIM_
EEV3
-
-
-
-
USART2_
TX
-
CAN1_
TXFD
-
-
FMC_NWE
-
-
EVENTOUT
PD6
-
-
SAI1_D1
DFSDM_
CKIN4
DFSDM_
DATIN1
SPI3_
MOSI/I2S3
_SDO
SAI1_SD_A
USART2_
RX
SAI4_SD_
A
CAN2_
RXFD
SAI4_D1
SDMMC2_
CK
FMC_
NWAIT
DCMI_D10
LCD_B2
EVENTOUT
PD7
-
-
-
DFSDM_
DATIN4
-
SPI1_
MOSI/I2S1
_SDO
DFSDM_CK
IN1
USART2_
CK
-
SPDIFRX_
IN0
-
SDMMC2_
CMD
FMC_NE1
-
-
EVENTOUT
PD8
-
-
-
DFSDM_
CKIN3
-
-
SAI3_SCK_
B
USART3_
TX
-
SPDIFRX_
IN1
-
-
FMC_D13/
FMC_DA13
-
-
EVENTOUT
PD9
-
-
-
DFSDM_
DATIN3
-
-
SAI3_SD_B
USART3_
RX
-
CAN2_
RXFD
-
-
FMC_D14/
FMC_DA14
-
-
EVENTOUT
PD10
-
-
-
DFSDM_
CKOUT
-
-
SAI3_FS_B
USART3_
CK
-
CAN2_
TXFD
-
-
FMC_D15/
FMC_DA15
-
LCD_B3
EVENTOUT
PD11
-
-
-
LPTIM2_IN
2
I2C4_SMBA
-
-
USART3_
CTS_NSS
-
QUADSPI_
BK1_IO0
SAI2_SD_A
-
FMC_A16
-
-
EVENTOUT
PD12
-
LPTIM1_IN1
TIM4_CH1
LPTIM2_IN
1
I2C4_SCL
-
-
USART3_
RTS
-
QUADSPI_
BK1_IO1
SAI2_FS_A
-
FMC_A17
-
-
EVENTOUT
PD13
-
LPTIM1_
OUT
TIM4_CH2
-
I2C4_SDA
-
-
-
QUADSPI_
BK1_IO3
SAI2_SCK_
A
-
FMC_A18
-
-
EVENTOUT
PD14
-
-
TIM4_CH3
-
-
-
SAI3_MCLK
_B
-
UART8_
CTS
-
-
-
FMC_D0/
FMC_DA0
-
-
EVENTOUT
PD15
-
-
TIM4_CH4
-
-
-
SAI3_MCLK
_A
-
UART8_
RTS
-
-
-
FMC_D1/
FMC_DA1
-
-
EVENTOUT
DocID030538 Rev 3
85/226
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port D
AF1
STM32H743xI
Table 12. Port D alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PE0
-
LPTIM1_
ETR
TIM4_ETR
HRTIM_
SCIN
LPTIM2_
ETR
-
-
-
UART8_RX
CAN1_
RXFD
SAI2_MCK
_A
-
FMC_NBL0
DCMI_D2
-
EVENTOUT
PE1
-
LPTIM1_IN2
-
HRTIM_
SCOUT
-
-
-
-
UART8_TX
CAN1_
TXFD
-
-
FMC_NBL1
DCMI_D3
-
EVENTOUT
PE2
TRACE
CLK
-
SAI1_CK1
-
-
SPI4_SCK
SAI1_MCLK
_A
-
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
SAI4_CK1
ETH_MII_
TXD3
FMC_A23
-
-
EVENTOUT
PE3
TRACED0
-
-
-
TIM15_BKIN
-
SAI1_SD_B
-
SAI4_SD_
B
-
-
-
FMC_A19
-
-
EVENTOUT
PE4
TRACED1
-
SAI1_D2
DFSDM_
DATIN3
TIM15_CH1
N
SPI4_NSS
SAI1_FS_A
-
SAI4_FS_A
-
SAI4_D2
-
FMC_A20
DCMI_D4
LCD_B0
EVENTOUT
PE5
TRACED2
-
SAI1_CK2
DFSDM_
CKIN3
TIM15_CH1
SPI4_
MISO
SAI1_SCK_
A
-
SAI4_SCK
_A
-
SAI4_CK2
-
FMC_A21
DCMI_D6
LCD_G0
EVENTOUT
PE6
TRACED3
TIM1_BKIN
2
SAI1_D1
-
TIM15_CH2
SPI4_
MOSI
SAI1_SD_A
-
SAI4_SD_
A
SAI4_D1
SAI2_MCK
_B
TIM1_BKIN
2_COMP12
FMC_A22
DCMI_D7
LCD_G1
EVENTOUT
PE7
-
TIM1_ETR
-
DFSDM_
DATIN2
-
-
-
UART7_RX
-
-
QUADSPI_
BK2_IO0
-
FMC_D4/
FMC_DA4
-
-
EVENTOUT
PE8
-
TIM1_CH1N
-
DFSDM_
CKIN2
-
-
-
UART7_TX
-
-
QUADSPI_
BK2_IO1
-
FMC_D5/
FMC_DA5
COMP_2_
OUT
-
EVENTOUT
PE9
-
TIM1_CH1
-
DFSDM_
CKOUT
-
-
-
UART7_
RTS
-
-
QUADSPI_
BK2_IO2
-
FMC_D6/
FMC_DA6
-
-
EVENTOUT
PE10
-
TIM1_CH2N
-
DFSDM_
DATIN4
-
-
-
UART7_
CTS
-
-
QUADSPI_
BK2_IO3
-
FMC_D7/
FMC_DA7
-
-
EVENTOUT
PE11
-
TIM1_CH2
-
DFSDM_
CKIN4
-
SPI4_NSS
-
-
-
-
SAI2_SD_B
-
FMC_D8/
FMC_DA8
-
LCD_G3
EVENTOUT
PE12
-
TIM1_CH3N
-
DFSDM_
DATIN5
-
SPI4_SCK
-
-
-
-
SAI2_SCK_
B
-
FMC_D9/
FMC_DA9
COMP_1_
OUT
LCD_B4
EVENTOUT
PE13
-
TIM1_CH3
-
DFSDM_
CKIN5
-
SPI4_
MISO
-
-
-
-
SAI2_FS_B
-
FMC_D10/
FMC_DA10
COMP_2_
OUT
LCD_DE
EVENTOUT
PE14
-
TIM1_CH4
-
-
-
SPI4_
MOSI
-
-
-
-
SAI2_MCK
_B
-
FMC_D11/
FMC_DA11
-
LCD_CLK
EVENTOUT
PE15
-
TIM1_BKIN
-
-
-
HDMI__
TIM1_BKIN
-
-
-
-
-
FMC_D12/
FMC_DA12
TIM1_BKIN
_COMP12
LCD_R7
EVENTOUT
DocID030538 Rev 3
STM32H743xI
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port E
AF1
Pin descriptions
86/226
Table 13. Port E alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENTOUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENTOUT
PF6
-
TIM16_CH1
-
-
-
SPI5_NSS
SAI1_SD_B
UART7_RX
SAI4_SD_
B
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENTOUT
PF7
-
TIM17_CH1
-
-
-
SPI5_SCK
SAI1_MCLK
_B
UART7_TX
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENTOUT
PF8
-
TIM16_
CH1N
-
-
-
SPI5_
MISO
SAI1_SCK_
B
UART7_
RTS
SAI4_SCK
_B
TIM13_
CH1
QUADSPI_
BK1_IO0
-
-
-
-
EVENTOUT
PF9
-
TIM17_
CH1N
-
-
-
SPI5_
MOSI
SAI1_FS_B
UART7_
CTS
SAI4_FS_B
TIM14_CH
1
QUADSPI_
BK1_IO1
-
-
-
-
EVENTOUT
PF10
-
TIM16_
BKIN
SAI1_D3
-
-
-
-
-
-
QUADSPI_
CLK
SAI4_D3
-
-
DCMI_D11
LCD_DE
EVENTOUT
PF11
-
-
-
-
-
SPI5_
MOSI
-
-
-
-
SAI2_SD_B
-
FMC_
SDNRAS
DCMI_D12
-
EVENTOUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENTOUT
PF13
-
-
-
DFSDM_
DATIN6
I2C4_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENTOUT
PF14
-
-
-
DFSDM_
CKIN6
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENTOUT
PF15
-
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENTOUT
DocID030538 Rev 3
87/226
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port F
AF1
STM32H743xI
Table 14. Port F alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
-OUT
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
-OUT
-
TIM8_BKIN
-
-
-
-
-
-
-
TIM8_BKIN_
COMP12
FMC_A12
-
-
EVENT
-OUT
-
-
TIM8_
BKIN2
-
-
-
-
-
-
-
TIM8_BKIN2
_COMP12
FMC_A13
-
-
EVENT
-OUT
-
TIM1_BKIN
2
-
-
-
-
-
-
-
-
-
TIM1_BKIN2
_COMP12
FMC_A14/
FMC_BA0
-
-
EVENT
-OUT
PG5
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
FMC_A15/
FMC_BA1
-
-
EVENT
-OUT
PG6
-
TIM17_
BKIN
HRTIM_
CHE1
-
-
-
-
-
-
-
QUADSPI_
BK1_NCS
-
FMC_NE3
DCMI_D1
2
LCD_R
7
EVENT
-OUT
PG7
-
-
HRTIM_
CHE2
-
-
-
SAI1_
MCLK_A
USART6_
CK
-
-
-
-
FMC_INT
DCMI_D1
3
LCD_
CLK
EVENT
-OUT
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
USART6_
RTS
SPDIFRX_
IN2
-
-
ETH_PPS_
OUT
FMC_
SDCLK
-
LCD_
G7
EVENT
-OUT
PG9
-
-
-
-
-
SPI1_
MISO/I2S1
_SDI
-
USART6_
RX
SPDIFRX_
IN3
QUADSPI_BK
2_IO2
SAI2_FS_B
-
FMC_NE2/
FMC_NCE
DCMI_
VSYNC
-
EVENT
-OUT
PG10
-
-
HRTIM_
FLT5
-
-
SPI1_NSS/
I2S1_WS
-
-
-
LCD_G3
SAI2_SD_B
-
FMC_NE3
DCMI_D2
LCD_B
2
EVENT
-OUT
PG11
-
-
HRTIM_
EEV4
-
-
SPI1_SCK/
I2S1_CK
-
-
SPDIFRX_
IN0
-
SDMMC2_D2
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
DCMI_D3
LCD_B
3
EVENT
-OUT
PG12
-
LPTIM1_IN1
HRTIM_
EEV5
-
-
SPI6_
MISO
USART6_
RTS
SPDIFRX_
IN1
LCD_B4
-
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_NE4
-
LCD_
B1
EVENT
-OUT
PG13
TRACED0
LPTIM1_
OUT
HRTIM_
EEV10
-
-
SPI6_SCK
USART6_
CTS_NSS
-
-
-
ETH_MII_
TXD0/ETH_
RMII_TXD0
FMC_A24
-
LCD_
R0
EVENT
-OUT
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
PG0
-
-
-
-
PG1
-
-
-
PG2
-
-
PG3
-
PG4
DocID030538 Rev 3
-
STM32H743xI
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/SPDIFRX
Port
Port G
AF1
Pin descriptions
88/226
Table 15. Port G alternate functions
AF1
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PG14
TRACED1
LPTIM1_
ETR
-
PG15
-
-
-
Port G
Port
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/SPDIFRX
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
-
-
SPI6_
MOSI
-
USART6_
TX
QUADSPI_
BK2_IO3
-
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_A25
-
LCD_
B0
EVENT
-OUT
-
-
-
-
USART6_
CTS_NSS
-
-
-
FMC_
SDNCAS
DCMI_
D13
-
EVENT
-OUT
-
STM32H743xI
Table 15. Port G alternate functions (continued)
AF0
DocID030538 Rev 3
Pin descriptions
89/226
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PH2
-
LPTIM1_IN2
-
-
-
-
-
-
-
QUADSPI_
BK2_IO0
SAI2_SCK_
B
ETH_MII_
CRS
FMC_
SDCKE0
-
LCD_R0
EVENTOUT
PH3
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO1
SAI2_MCK
_B
ETH_MII_
COL
FMC_
SDNE0
-
LCD_R1
EVENTOUT
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
OTG_HS_
ULPI_NXT
-
-
-
LCD_G4
EVENTOUT
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
-
-
-
-
-
FMC_
SDNWE
-
-
EVENTOUT
PH6
-
-
TIM12_
CH1
-
I2C2_SMBA
SPI5_SCK
-
-
-
-
-
ETH_MII_
RXD2
FMC_
SDNE1
DCMI_D8
-
EVENTOUT
PH7
-
-
-
-
I2C3_SCL
SPI5_
MISO
-
-
-
-
-
ETH_MII_
RXD3
FMC_
SDCKE1
DCMI_D9
-
EVENTOUT
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_
HSYNC
LCD_R2
EVENTOUT
PH9
-
-
TIM12_
CH2
-
I2C3_SMBA
-
-
-
-
-
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENTOUT
PH10
-
-
TIM5_CH1
-
I2C4_SMBA
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENTOUT
PH11
-
-
TIM5_CH2
-
I2C4_SCL
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENTOUT
PH12
-
-
TIM5_CH3
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENTOUT
PH13
-
-
-
TIM8_
CH1N
-
-
-
-
UART4_TX
CAN1_TX
-
-
FMC_D21
-
LCD_G2
EVENTOUT
PH14
-
-
-
TIM8_µCH
2N
-
-
-
-
UART4_RX
CAN1_RX
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENTOUT
PH15
-
-
-
TIM8_
CH3N
-
-
-
-
-
CAN1_
TXFD
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENTOUT
DocID030538 Rev 3
STM32H743xI
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port H
AF1
Pin descriptions
90/226
Table 16. Port H alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/
I2S2_WS
-
-
-
CAN1_
RXFD
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENTOUT
PI1
-
-
-
TIM8_BKIN
2
-
SPI2_SCK/
I2S2_CK
-
-
-
-
-
TIM8_BKIN
2_COMP12
FMC_D25
DCMI_D8
LCD_G6
EVENTOUT
PI2
-
-
-
TIM8_CH4
-
SPI2_
MISO/I2S2
_SDI
-
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENTOUT
PI3
-
-
-
TIM8_ETR
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
-
-
FMC_D27
DCMI_D10
-
EVENTOUT
PI4
-
-
-
TIM8_BKIN
-
-
-
-
-
-
SAI2_MCK
_A
TIM8_BKIN
_COMP12
FMC_NBL2
DCMI_D5
LCD_B4
EVENTOUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
SAI2_SCK_
A
-
FMC_NBL3
DCMI_
VSYNC
LCD_B5
EVENTOUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
SAI2_SD_A
-
FMC_D28
DCMI_D6
LCD_B6
EVENTOUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
SAI2_FS_A
-
FMC_D29
DCMI_D7
LCD_B7
EVENTOUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PI9
-
-
-
-
-
-
-
-
UART4_RX
CAN1_RX
-
-
FMC_D30
-
LCD_
VSYNC
EVENTOUT
PI10
-
-
-
-
-
-
-
-
-
CAN1_
RXFD
-
ETH_MII_
RX_ER
FMC_D31
-
LCD_
HSYNC
EVENTOUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS_
ULPI_DIR
-
-
-
-
EVENTOUT
PI12
-
-
-
-
-
-
-
-
-
-
-
ETH_TX_
ER
-
-
LCD_
HSYNC
EVENTOUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
VSYNC
EVENTOUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
EVENTOUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVENTOUT
DocID030538 Rev 3
91/226
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port I
AF1
STM32H743xI
Table 17. Port I alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVENTOUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVENTOUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R3
EVENTOUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVENTOUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVENTOUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENTOUT
PJ6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVENTOUT
PJ7
TRGIN
-
-
TIM8_
CH2N
-
-
-
-
-
-
-
-
-
-
LCD_G0
EVENTOUT
PJ8
-
TIM1_CH3N
-
TIM8_CH1
-
-
-
-
UART8_TX
-
-
-
-
-
LCD_G1
EVENTOUT
PJ9
-
TIM1_CH3
-
TIM8_
CH1N
-
-
-
-
UART8_RX
-
-
-
-
-
LCD_G2
EVENTOUT
PJ10
-
TIM1_CH2N
-
TIM8_CH2
-
SPI5_
MOSI
-
-
-
-
-
-
-
-
LCD_G3
EVENTOUT
PJ11
-
TIM1_CH2
-
TIM8_
CH2N
-
SPI5_
MISO
-
-
-
-
-
-
-
-
LCD_G4
EVENTOUT
PJ12
TRGOUT
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENTOUT
PJ13
-
-
-
-
-
-
-
-
-
LCD_B4
-
-
-
-
LCD_B1
EVENTOUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENTOUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENTOUT
DocID030538 Rev 3
STM32H743xI
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
Port
Port J
AF1
Pin descriptions
92/226
Table 18. Port J alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PK0
-
TIM1_CH1N
-
TIM8_CH3
-
SPI5_SCK
-
-
-
-
-
-
-
-
LCD_G5
EVENTOUT
PK1
-
TIM1_CH1
-
TIM8_
CH3N
-
SPI5_NSS
-
-
-
-
-
-
-
-
LCD_G6
EVENTOUT
PK2
-
TIM1_BKIN
-
TIM8_BKIN
-
-
-
-
-
-
TIM8_BKIN
_COMP12
TIM1_BKIN
_COMP12
-
-
LCD_G7
EVENTOUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENTOUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENTOUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENTOUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENTOUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENTOUT
Port
Port K
AF1
STM32H743xI
Table 19. Port K alternate functions
DocID030538 Rev 3
Pin descriptions
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Electrical characteristics
6
6.1
STM32H743xI
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
94/226
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MS19010V2
STM32H743xI
6.1.6
Electrical characteristics
Power supply scheme
VDD33USB
100 nF
100 nF
Figure 13. Power supply scheme
VDD33USB
USB
regulator
VDDLDO
VCAP
Core domain (VCORE)
Level shifter
VSS
IOs
N(1) x 100 nF
+ 1 x 4.7 μF
VDD
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
VDD domain
VBAT
charging
HSI, CSI,
HSI48,
HSE, PLLs
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
logic, backup
IO
registers,
logic
Reset
BKUP
IOs
VREF
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
VDDA
VDDA
Flash
VSS
VDD
VBAT
1.2 to 3.6V
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
Power
switch
Voltage
regulator
VSS
Power
switch
4..7μF
2 x 2.2μF
VDD50USB
USB
IOs
VSS
VDDLDO
VDD50USB
VSS
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
Backup
RAM
VSS
OPAMP,
Comparator
VSSA
MSv46116V3
1. N corresponds to the number of VDD pins available on the package..
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID030538 Rev 3
95/226
196
Electrical characteristics
6.1.7
STM32H743xI
Current consumption measurement
Figure 14. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics, and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 20. Voltage characteristics (1)
Symbols
VDDX - VSS
VIN(2)
Ratings
Min
Max
Unit
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS-0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
-
50
mV
-
50
mV
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)
Input voltage on any other pins
|∆VDDX|
Variations between different VDDX power pins
of the same domain
|VSSx-VSS| Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 57 for the maximum allowed injected current
values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
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STM32H743xI
Electrical characteristics
Table 21. Current characteristics
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
620
ΣIVSS
(1)
620
Total current out of sum of all VSS ground lines (sink)
IVDD
(1)
Maximum current into each VDD power pin (source)
100
IVSS
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk by any I/O and control pin
IIO
20
(2)
ΣI(PIN)
Total output current sunk by sum of all I/Os and control pins
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
IINJ(PIN)(3)(4) PA5
Injected current on PA4, PA5
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control
Unit
mA
−5/+0
−0/0
pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN