STM32H745xI/G
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs,
up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS
Datasheet - production data
Features
FBGA
Dual core
• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
®
®
• 32-bit Arm 32-bit Cortex -M4 core with FPU,
Adaptive real-time accelerator (ART
Accelerator™) for internal Flash memory and
external memories, frequency up to 240 MHz,
MPU, 300 DMIPS/1.25 DMIPS /MHz
(Dhrystone 2.1), and DSP instructions
LQFP144
(20x20 mm)
LQFP176
(24x24 mm)
LQFP208
(28x28 mm)
TFBGA240+25
(14x14 mm)
FBGA
UFBGA176+25
(10x10 mm)
Reset and power management
• 3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
• 1.62 to 3.6 V application supply and I/Os
Memories
• Up to 2 Mbytes of Flash memory with readwhile-write support
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
• Dual mode Quad-SPI memory interface
running up to 133 MHz
• Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 125 MHz in
Synchronous mode
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
• Embedded regulator (LDO) to supply the digital
circuitry
• High power-efficiency SMPS step-down
converter regulator to directly supply VCORE
and/or external circuitry
• Voltage scaling in Run and Stop mode (6
configurable ranges)
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/VREF+
• 1.2 to 3.6 V VBAT supply
• CRC calculation unit
• Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Security
Low-power consumption
• ROP, PC-ROP, active tamper
• VBAT battery operating mode with charging
capability
General-purpose input/outputs
• Up to 168 I/O ports with interrupt capability
May 2019
This is information on a product in full production.
• CPU and domain power state monitoring pins
• 2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
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STM32H745xI/G
Clock management
• 2× operational amplifiers (7.3 MHz bandwidth)
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
• 1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
• External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
Graphics
• 3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
• LCD-TFT controller up to XGA resolution
Interconnect matrix
• Hardware JPEG Codec
•
3 bus matrices (1 AXI and 2 AHB)
•
Bridges (5× AHB2-APB, 2× AXI2-AHB)
• Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
Up to 22 timers and watchdogs
• 1× high-resolution timer (2.1 ns max
resolution)
4 DMA controllers to unload the CPU
• 1× high-speed master direct memory access
controller (MDMA) with linked list support
• 2× dual-port DMAs with FIFO
• 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
• 1× basic DMA with request router capabilities
• 2× 16-bit advanced motor control timers (up to
240 MHz)
Up to 35 communication peripherals
• 10× 16-bit general-purpose timers (up to
240 MHz)
• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 5× 16-bit low-power timers (up to 240 MHz)
• 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
• 2× SysTick timers
• 4x SAIs (serial audio interface)
• 4× watchdogs (independent and window)
• RTC with sub-second accuracy and hardware
calendar
• SPDIFRX interface
Debug mode
• SWPMI single-wire protocol master I/F
• SWD & JTAG interfaces
• MDIO Slave interface
• 4-Kbyte Embedded Trace Buffer
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
• 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD
• Ethernet MAC interface with DMA controller
• HDMI-CEC
• 8- to 14-bit camera interface (up to 80 MHz)
• 3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
• 2× 12-bit D/A converters (1 MHz)
96-bit unique ID
Optional support of extended temperature
range up to 125 °C (specific part numbers)
All packages are ECOPACK®2 compliant
Table 1. Device summary
11 analog peripherals
• 1× temperature sensor
True random number generators (3
oscillators each)
Reference
STM32H745xI
STM32H745ZI, STM32H745II,
STM32H745BI, STM32H745XI
STM32H745xG
STM32H745ZG, STM32H745IG,
STM32H745BG, STM32H745XG
• 2× ultra-low-power comparators
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Part number
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STM32H745xI/G
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Dual Arm® Cortex® cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.2
Arm® Cortex®-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3
ART™ accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.3
Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 28
3.5.4
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34
3.13
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34
3.14
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34
3.15
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35
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3.17
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.18
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.21
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.23
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38
3.24
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.25
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.26
JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.27
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28.1
High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.28.2
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28.3
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28.4
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.28.6
Independent watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.7
Window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.8
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.30
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.31
Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.32
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.33
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.34
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.36
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.37
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.38
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.39
Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.40
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.41
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
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Contents
3.42
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.43
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.3
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.4
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
6.3.5
Embedded reset and power control block characteristics . . . . . . . . . . 115
6.3.6
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.12
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.13
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.14
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 150
6.3.15
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.16
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.17
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.18
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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6.3.19
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.20
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.3.21
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.22
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.23
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.24
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.25
Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.26
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.27
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.28
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.29
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 203
6.3.30
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 206
6.3.31
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 207
6.3.32
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.33
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.1
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.2
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.3
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.4
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.5
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32H745xI/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STM32H745xI/G pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 111
VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 113
SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 114
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 114
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
(ART accelerator ON), LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
ART accelerator OFF, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON . . . . . . . . . . . . . . . 120
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, SMPS regulator. . . . . . . . . . . . . . . . . 121
Typical and maximum current consumption in Run mode, code with data processing
DS12923 Rev 1
7/252
10
List of tables
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
8/252
STM32H745xI/G
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 124
Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 125
Typical and maximum current consumption in Sleep mode, LDO regulator ON . . . . . . . 126
Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 126
Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 127
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 147
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 154
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 155
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 163
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DS12923 Rev 1
STM32H745xI/G
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
List of tables
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 221
Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 222
Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 225
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 226
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 226
Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 243
DS12923 Rev 1
9/252
10
List of tables
Table 134.
Table 135.
Table 136.
Table 137.
10/252
STM32H745xI/G
TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 247
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
DS12923 Rev 1
STM32H745xI/G
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32H745xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TFBGA240+25 ball assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ART™ accelerator schematic and environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32H745xI/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 128
Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . 128
Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 °C . . . . . 129
Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 130
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 160
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 162
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 176
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 177
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 192
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 192
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DS12923 Rev 1
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12
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
12/252
STM32H745xI/G
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DS12923 Rev 1
STM32H745xI/G
1
Introduction
Introduction
This document provides information on STM32H745xI/G microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering information.
This document should be read in conjunction with the STM32H745xI/G reference manual
(RM0399), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core and Arm® Cortex®-M4 core, please refer to
the Cortex®-M7 Technical Reference Manual, available from the http://www.arm.com
website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12923 Rev 1
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54
Description
2
STM32H745xI/G
Description
STM32H745xI/G devices are based on the high-performance Arm® Cortex®-M7 and
Cortex®-M4 32-bit RISC cores. The Cortex®-M7 core operates at up to 480 MHz and the
Cortex®-M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which
supports Arm® single- and double-precision (Cortex®-M7 core) operations and conversions
(IEEE 754 compliant), including a full set of DSP instructions and a memory protection unit
(MPU) to enhance application security.
STM32H745xI/G devices incorporate high-speed embedded memories with a dual-bank
Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM,
up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG). The devices support
four digital filters for external sigma-delta modulators (DFSDM). They also feature standard
and advanced communication interfaces.
•
•
Standard peripherals
–
Four I2Cs
–
Four USARTs, four UARTs and one LPUART
–
Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
Four SAI serial audio interfaces
–
One SPDIFRX interface
–
One SWPMI (Single Wire Protocol Master Interface)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces
–
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
One FDCAN plus one TT-FDCAN interface
–
An Ethernet interface
–
Chrom-ART Accelerator™
–
HDMI-CEC
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
A Quad-SPI Flash memory interface
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
–
A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H745xI/G features and peripheral counts for the list of peripherals
available on each part number.
14/252
DS12923 Rev 1
STM32H745xI/G
Description
STM32H745xI/G devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to
allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H745xI/G devices are offered in 5 packages ranging from 144 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H745xI/G microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS12923 Rev 1
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54
Description
STM32H745xI/G
SRAM1
(D2 domain)
128
SRAM2
(D2 domain)
128
SRAM3
(D2 domain)
32
SRAM4
(D3 domain)
64
ITCM RAM
(instruction)
64
DTCM RAM
(data)
128
Backup SRAM (Kbytes)
4
FMC
Yes
148
168
97
Yes
Ethernet
Yes
Highresolution
1
Generalpurpose
10
Advancedcontrol
(PWM)
2
Basic
2
Low-power
5
Wakeup pins
Tamper pins
16/252
119/128
Quad-SPI
Timers
STM32H745II
STM32H745ZI
STM32H745XG
512
97
4
2
148
168
2 x 1 Mbyte
SRAM
mapped
onto AXI bus
General-purpose
input/outputs
STM32H745XI
TCM RAM in
Kbytes
2 x 512 Kbytes
STM32H745BI
Flash memory in Kbytes
SRAM in
Kbytes
STM32H745BG
STM32H745IG
Peripherals
STM32H745ZG
Table 2. STM32H745xI/G features and peripheral counts
6
3
DS12923 Rev 1
119/128
4
2
6
3
STM32H745xI/G
Description
STM32H745XI
STM32H745II
4
9
23
6/3(1)
SPI / I
I2C
4
USART/
UART/
LPUART
4/4
/1
SAI
4
SPDIFRX
4 inputs
SWPMI
Yes
MDIO
Yes
SDMMC
2
FDCAN/TTFDCAN
1/1
USB
OTG_FS
Yes
USB
OTG_HS
Yes
Ethernet and camera
interface
Yes
LCD-TFT
Yes
JPEG Codec
Yes
Chrom-ART Accelerator™
(DMA2D)
Yes
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
2
9
21
Yes
2S
Communicati
on interfaces
STM32H745BI
Random number generator
STM32H745ZI
STM32H745XG
STM32H745BG
Peripherals
STM32H745IG
STM32H745ZG
Table 2. STM32H745xI/G features and peripheral counts (continued)
3
2
6
15
2
9
17
4
9
23
2
9
21
4
9
23
2
6
15
12-bit DAC
Number of channels
Yes
2
Comparators
2
Operational amplifiers
2
DFSDM
Yes
DS12923 Rev 1
2
9
17
4
9
23
17/252
54
Description
STM32H745xI/G
STM32H745XI
STM32H745BI
STM32H745II
STM32H745ZI
STM32H745XG
STM32H745BG
STM32H745IG
Peripherals
STM32H745ZG
Table 2. STM32H745xI/G features and peripheral counts (continued)
480 MHz(2)
400 MHz(3)
Maximum CPU frequency
300 MHz(4)
Operating voltage
Operating
temperatures
Extended
operating
temperatures
1.62 to 3.6 V(5)
Ambient
temperature
–40 up to +85 °C(6)
Junction
temperature
–40 to + 125 °C
Ambient
temperature
–40 to + 125 °C(4)(7)
Junction
temperature
–40 to + 140 °C(8)
Package
LQFP LQFP UFBGA LQFP TFBGA LQFP
144
176 176+25
208 240+25 144
LQFP UFBGA LQFP TFBGA
176 176+25 208 240+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The product junction temperature must be kept within the –40 to +105 °C range.
3. The product junction temperature must be kept within the –40 to +125 °C range.
4. Up to 300 MHz for STM32H745xxx3 sales types (extended industrial temperature range).
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. Using appropriate cooling methods to guarantee that the maximum junction temperature (125 °C) is not exceeded, the
maximum ambient temperature (85°C) can be exceeded.
7. The product junction temperature must be kept within the –40 to +140 °C range.
8. It is mandatory to use the SMPS step-down converter when the maximum junction temperature is higher than 125 °C.
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DS12923 Rev 1
STM32H745xI/G
Description
Figure 1. STM32H745xI/G block diagram
MII / RMII
To APB1-2
peripherals
MDIO
as AF
AHB1
Up to 1 MB
FLASH
Up to 1 MB
FLASH
16 Streams
FIFO
CHROM-ART
(DMA2D)
FIFO
LCD-TFT
FIFO
JPEG
FMC
FMC_signals
Quad-SPI
CLK, CS,D[7:0]
AXI/AHB34 (200MHz)
RNG
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
ADC1
Up to 20 analog inputs
common to ADC1 & 2
ADC2
AHB/APB
32b
TIM6
16b
16b
TIM7
16b
16b
SWPMI
FIFO
32b
16b
ART
(instruction cache)
16b
AHB ART (200MHz)
TIM2
4 channels, ETR as AF
TIM3
4 channels, ETR as AF
TIM4
4 channels, ETR as AF
TIM5
4 channels
TIM12
2 channels as AF
TIM13
1 channel as AF
TIM14
16b
1 channel as AF
smcard
AHB2 (200MHz)
Delay block
DMA/
FIFO
32-bit AHB BUS-MATRIX
AHB/APB
SDMMC1
DMA/
FIFO
FIFO
DMA
DMA
Mux1
512 KB AXI
SRAM
AHBS
PHY
PHY
ETHER
SDMMC2 OTG_HS OTG_FS
MAC
AHB1 (200MHz)
D-Cache
16KB
(200MHz)
8 Stream 8 Stream
FIFOs
FIFOs
D- SIBus Bus Bus
AHB2 (200MHz)
I-Cache
16KB
WWDG1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
AXIM
ETM
MDMA
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE,
LCD_CLK
AXI/AHB12 (200MHz)
AHB4 (200MHz)
Arm
Cortex
M7
AHBP
DMA2
AHB ART(200MHz)
TRACECK
TRACED[3:0]
JTAG/SW
DMA1
Arm
Cortex
M4
64-bit AXI BUS-MATRIX
JTDO/SWD, JTDO
JTRST, JTDI,
JTCK/SWCLK
DTCM
64KB
AHB3
DTCM
64KB
ITCM
64KB
DP, DM, STP,
SDMMC_
NXT,ULPI:CK DP, DM, ID,
D[7:0],
VBUS
, D[7:0], DIR,
CMD, CK as AF
ID, VBUS
USART2
irDA
smcard
RX, TX as AF
RX, TX as AF
UART7
RX, TX as AF
UART8
RX, TX as AF
SPI/I2S1
16b
APB1 100 MHz (max)
A P B 10 MHz
3
IWDG2
DAP
16b
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
I2C2/SMBUS
I2C3/SMBUS
MDIOS
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MDC, MDIO
FDCAN1
FDCAN2
TX, RX
TX, RX
CRS
64 KB SRAM
SPDIFRX1
4 KB BKP
RAM
IN[1:4] as AF
HDMI-CEC
CEC as AF
DAC1&2
HSEM
TIM8/PWM
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SPI3/I2S3
I2C1/SMBUS
RAM
I/F
32-bit AHB BUS-MATRIX
IWDG1
smcard
irDA USART6
smcard
irDA USART1
TIM1/PWM
BDMA
SPI2/I2S2
FIFO
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
AHB4
DMA
Mux2
10 KB SRAM
TIM15
SPI4
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
APB2 100 MHz (max)
TIM16
MOSI, MISO, SCK, NSS as AF
RX, TX, SCK, CTS, RTS as AF
RX, TX, SCK
CTS, RTS as AF
UART5
Digital filter
SPI5
TIM17
AHB4
SAI1
AHB4
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
AHB4 (200MHz)
SAI2
RX, TX, SCK, CTS, RTS as AF
UART4
AHB4
SAI3
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
irDA
DFSDM1
SD, SCK, FS, MCLK as AF
MOSI, MISO, SCK, NSS as AF
AHB/APB
HRTIM1
SD, SCK, FS, MCLK as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
USART3
DCMI
AHB4
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
FIFO FIFO FIFO
HSYNC, VSYNC, PUIXCLK, D[13:0]
RX, TX, SCK, CTS,
RTS as AF
LPTIM1
CRC
DAC1_OUT, DAC2_OUT as AF
16b
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
@VSW
LPTIM4_OUT as AF
RX, TX, CK, CTS, RTS as AF
LS
XTAL 32 kHz
COMP1&2
LPTIM4
MISO, MOSI, SCK, NSS as AF
AHB/APB
Voltage regulator
3.3 to 1.2V
SMPS step-down
converter
SAI4
LPTIM5
LPTIM3_OUT as AF
VDD12 POWER MANAGEMENT
PWRCTRL
GPIO PORTK
LPTIM5_OUT as AF
SCL, SDA, SMBAL as AF
RCC
Reset &
control
LPTIM3
I2C4
SPI6
RTC
Backup registers
@VDD
VREF
SYSCFG
EXTI WKUP
CSI
RC48
4 MHz CSI
48 MHz HSI48 RC
HSI
64 MHz HSI RC
LSI
32 KHz LSI RC
PLL1+PLL2+PLL3
LS
PK[7:0]
SD, SCK, FS, MCLK,
PDM_DI/CK[4:1] as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
Tem. sensor
GPIO PORTA.. J
WWDG2
@VDD33
APB4 100 MHz (max)
PA..J[15:0]
AHB4
VDDREF_ADC
ADC3
APB4 100
100MHz
MHz(max)
(max)
APB4
Up to 17 analog inputs
common to ADC1 and 2
AHB4 (200MHz)
OPAMP1&2
AWU
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
VDD = 1.62 to 3.6V
VDD33USB = 3.0 to 3.6V
VSS
VCAP
VDDMMC33 = 1.8 to 3.6V
VDDSMPS, VSSSMPS
VLXSMP, VFBSMPS,
OSC32_IN
OSC32_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VBAT = 1.2 to 3.6 V
@VDD
XTAL OSC
4- 48 MHz
OSC_IN
OSC_OUT
IWDG1
LPUART1
IWDG2
LPTIM2_OUT as AF
LPTIM2
@VDD
POR
reset
Int
SUPPLY SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[5:0]
MSv43754V13
DS12923 Rev 1
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54
Description
STM32H745xI/G
Compatibility throughout the family
STM32H745xI/G devices are not pin-to-pin compatible with STM32H7x3 devices (single
core line):
•
The TFBGA240+25 ballout is compatible with STM32H7x3 devices, except for a few
I/O balls as shown in Figure 2.
•
LQFP208 and LQFP176 pinouts, as well as UFBGA176+25 ballout are not compatible
with STM32H7x3 devices.
Figure 2. TFBGA240+25 ball assignment differences
1
A
VSS
2
3
4
5
6
7
8
9
10
11
12
PK5
PG10
PG9
PD5
PI6
PI5
PI4
PB5
VDDLDO
VCAP
13
14
15
16
17
PD4
PC10
PA15
PI1
PI0
VSS
B
VBAT
VSS
PI7
PE1
PB6
VSS
PB4
PK4
PG11
PJ15
PD6
PD3
PC11
PA14
PI2
PH15
PH14
C
PC15OSC32_
OUT
PC14OSC32_
IN
PE2
PE0
PB7
PB3
PK6
PK3
PG12
VSS
PD7
PC12
VSS
PI3
PA13
VSS
VDDLDO
PE4
PE3
PB9
PB8
PG15
PK7
PG14
PG13
PJ14
PJ12
PD2
PD0
PA10
PA9
PH13
VCAP
PI9
PC13
PI8
PE6
VDD
PDR
_ON
BOOT0
VDD
PJ13
VDD
PD1
PC8
PC9
PA8
PA12
PA11
PI10
PI11
VDD
PC7
PC6
PG8
PG7
VDD33
USB
PF1
PF0
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PG5
PG6
VSS
VDD50
USB
D
PE5
E
F
G
PF2
H
PI12
PI14
PF3
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PG4
PG3
PG2
PK2
J
PH1PH0OSC_
OSC_IN
OUT
VSS
PF5
PF4
VSS
VSS
VSS
VSS
VSS
VDD
PK0
PK1
VSS
VSS
K
NRST
PF6
PF7
PF8
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PJ11
VSS
NC
NC
VSS
VSS
VSS
VSS
VSS
VDD
PJ10
VSS
NC
NC
VDD
PJ9
VSS
NC
NC
NC
PI13
L
VDDA
PC0
PF10
PF9
VDD
M
VREF+
PC1
PC2
PC3
VDD
N
VREF-
PH2
PA2
PA1
PA0
PJ0
VDD
VDD
PE10
VDD
VDD
VDD
PJ8
PJ7
PJ6
VSS
P
VSSA
PH3
PH4
PH5
PI15
PJ1
PF13
PF14
PE9
PE11
PB10
PB11
PH10
PH11
PD15
PD14
VDD
R
PC2_C
PC3_C
PA6
VSS
PA7
PB2
PF12
VSS
PF15
PE12
PE15
PJ5
PH9
PH12
PD11
PD12
PD13
T
PA0_C
PA1_C
PA5
PC4
PB1
PJ2
PF11
PG0
PE8
PE13
PH6
VSS
PH8
PB12
PB15
PD10
PD9
U
VSS
PA3
PA4
PC5
PB0
PJ3
PJ4
PG1
PE7
PE14
VCAP
VDDLDO
PH7
PB13
PB14
PD8
VSS
STM32H7x5
VLX
SMPS
STM32H7x3
PI9
VDD
VSS
SMPS
SMPS
NC
PI9
NC
NC
VFB
PF2
PF2
SMPS
NC
MSv48801V2
1. The balls highlighted in gray correspond to different signals on STM32H745xI/G and STM32H7x3 devices.
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DS12923 Rev 1
STM32H745xI/G
Functional overview
3
Functional overview
3.1
Dual Arm® Cortex® cores
The industrial STM32H745xI/G devices embed two Arm® cores, a Cortex®-M7 and a
Cortex®-M4. The Cortex®-M4 offers optimal performance for real-time applications while the
Cortex®-M7 core can execute high-performance tasks in parallel.
The two cores belong to separate power domains. This allows designing gradual highpower efficiency solutions in combination with the low-power modes already available on all
STM32 microcontrollers.
3.1.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•
64-bit AXI interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H745xI/G family.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
DS12923 Rev 1
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54
Functional overview
3.1.2
STM32H745xI/G
Arm® Cortex®-M4 with FPU
The Arm® Cortex®-M4 processor is a high-performance embedded processor which
supports DSP instructions. It was developed to provide an optimized power consumption
MCU, while delivering outstanding computational performance and low interrupt latency.
The Arm® Cortex®-M4 processor is a highly efficient MCU featuring:
•
3-stage pipeline with branch prediction
•
Harvard architecture
•
32-bit System (S-BUS) interface
•
32-bit I-BUS interface
•
32-bit D-BUS interface
The Arm® Cortex®-M4 processor also features a dedicated hardware adaptive real-time
accelerator (ART Accelerator™). This is an instruction cache memory composed of sixtyfour 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit
interface for non-cacheable accesses.
3.2
Memory protection unit (MPU)
The devices feature two memory protection units. Each MPU manages the CPU access
rights and the attributes of the system resources. It has to be programmed and enabled
before use. Its main purposes are to prevent an untrusted user program to accidentally
corrupt data used by the OS and/or by a privileged task, but also to protect data processes
or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H745xI/G devices embed up to 2 Mbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
One Flash word (8 words, 32 bytes or 256 bits)
•
10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
3.3.2
•
A user Flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI)
containing eight user sectors of 128 Kbytes (4 K Flash memory words)
•
128 Kbytes of System Flash memory from which the device can boot
•
2 Kbytes (64 Flash words) of user option bytes for user configuration
Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as
follows:
•
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
•
SRAM1 mapped on D2 domain: 128 Kbytes
•
SRAM2 mapped on D2 domain: 128 Kbytes
•
SRAM3 mapped on D2 domain: 32 Kbytes
•
SRAM4 mapped on D3 domain: 64 Kbytes
•
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the Arm® Cortex®-M7 CPU or the MDMA (even in Sleep mode) through a specific
AHB slave of the Cortex®-M7(AHBS):
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the Cortex®-M7.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
DS12923 Rev 1
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54
Functional overview
STM32H745xI/G
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
7 ECC bits are added per 32-bit word.
•
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.3.3
ART™ accelerator
The ART™ (adaptive real-time) accelerator block speeds up instruction fetch accesses of
the Cortex®-M4 core from D1-domain internal memories (Flash memory bank 1, Flash
memory bank 2, AXI SRAM) and from D1-domain external memories attached via QuadSPI controller and Flexible memory controller (FMC).
The ART™ accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit
AXI D1 domain. The acceleration is achieved by loading selected code into an embedded
cache and making it instantly available to Cortex®-M4 core, thus avoiding latency due to
memory wait states.
Figure 3. shows the block schematic and the environment of the ART accelerator.
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DS12923 Rev 1
STM32H745xI/G
Functional overview
Figure 3. ART™ accelerator schematic and environment
AHB from D2 domain
D1 domain
ART accelerator
Non-cacheable
access path
AHB switch
Cacheable
access path
control
Detect of
write to cacheable page
Cache
Cache buffer
noncacheable
access
instruction
fetch
cache cache
hit miss
1 x 256-bit
Cache memory
64 x 256-bit
Cache memory
Cache
manager
64 x 256-bit
cache
refill
AHB access
AXI access
Flash bank 1
Legend
Flash bank 2
Control
32-bit bus
AXI SRAM
64-bit bus
QSPI
Bus multiplexer
AXI AHB
Master interface
FMC
Slave interface
64-bit AXI bus matrix
MSv39757V2
3.4
Boot modes
By default, the boot codes are executed simultaneously by both cores. However, by
programming the appropriate Flash user option byte, it is possible to boot from one core
while clock-gating the other core.
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space
•
Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed
by the Cortex®-M4 core)
DS12923 Rev 1
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54
Functional overview
STM32H745xI/G
The bootloader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
STM32H745xI/G power supply voltages are the following:
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•
VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•
VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
•
–
D1 domain containing some peripherals and the Cortex®-M7 core.
–
D2 domain containing a large part of the peripherals and the Cortex®-M4 core.
–
D3 domain containing some peripherals and the system control.
VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply
VDDSMPS must be kept at the same voltage level as VDD.
•
VLXSMPS = SMPS step-down converter output coupled to an inductor.
•
VFBSMPS = VCORE, 1.8 V or 2.5 V external SMPS step-down converter feedback
voltage sense input.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 4):
•
When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•
When VDD is above 1 V, all power supplies are independent (except for VDDSMPS,
which must remain at the same level as VDD).
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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DS12923 Rev 1
STM32H745xI/G
Functional overview
Figure 4. Power-up/power-down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
VDDX independent from VDD
time
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
3.5.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
DS12923 Rev 1
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54
Functional overview
3.5.3
STM32H745xI/G
Voltage regulator (SMPS step-down converter and LDO)
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
Note:
Run mode (VOS0 to VOS3)
–
Scale 0: boosted performance (available only with LDO regulator)
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
For STM32H745xxx3 sales types (industrial temperature range) the voltage regulator output
can be set only to VOS2 or VOS3 in Run mode (VOS0 and VOS1 are not available for
industrial temperature range).
•
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.5.4
SMPS step-down converter
The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear
switching regulator that provides lower power consumption than a conventional voltage
regulator (LDO).
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DS12923 Rev 1
STM32H745xI/G
Functional overview
The SMPS step-down converter can be used for the following purposes:
•
•
Direct supply of the VCORE domain
–
the SMPS step-down converter operating modes follow the device system
operating modes (Run, Stop, Standby).
–
the SMPS step-down converter output voltage are set according to the selected
VOS and SVOS bits (voltage scaling)
Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO)
–
SMPS step-down converter operating modes
When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS stepdown converter follows the device system operating modes (Run, Stop and
Standby).
When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down
converter is forced to High-performance mode and does not follow the device
system operating modes (Run, Stop and Standby).
–
•
3.6
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
Delivery of an external supply
–
The SMPS step-down converter is forced to High-performance mode (provided
SDEXTHP bit is equal to 1 in PWR_CR3)
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
Low-power strategy
There are several ways to reduce power consumption on STM32H745xI/G:
•
Select the SMPS step-down converter as VCORE supply voltage source, as it allows to
enhance power efficiency.
•
Select the adequate voltage scaling
•
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode, and by individually clock gating the peripherals that are not used.
•
Save power consumption when one or both CPUs are idle, by selecting among the
available low-power mode according to the user application needs. This allows
achieving the best compromise between short startup time, low-power consumption, as
well as available wakeup sources.
The devices feature several low-power modes:
•
CSleep (CPU clock stopped)
•
CStop (CPU sub-system clock stopped)
•
DStop (Domain bus matrix clock stopped)
•
Stop (System clock stopped)
•
DStandby (Domain powered down)
•
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
DS12923 Rev 1
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54
Functional overview
STM32H745xI/G
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode. For instance
D1 or D2 domain enters DStop/DStandby mode when the CPU of the domain is in CStop
mode AND the other CPU has no peripheral allocated in that domain, or if it is in CStop
mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have
active peripherals in D3 domain, and D3 is not forced in Run mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
The clock system can be re-initialize by a master CPU (either the Cortex®-M4 or -M7) after
exiting Stop mode while the slave CPU is held in low-power mode. Once the master CPU
has re-initialized the system, the slave CPU can receive a wakeup interrupt and proceed
with the interrupt service routine.
Table 3. System vs domain low-power mode
D1 domain power
mode
System power mode
Run
3.7
D2 domain power
mode
DRun/DStop/DStandby DRun/DStop/DStandby
D3 domain power
mode
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
•
30/252
Internal oscillators:
–
64 MHz HSI clock
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
DS12923 Rev 1
STM32H745xI/G
Functional overview
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
3.8
•
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Independent watchdog 1 (from D1 domain)
•
Independent watchdog 2 (from D2 domain)
•
Window watchdog 1 (from D1 domain)
•
Window watchdog 2 (from D2 domain)
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 5).
DS12923 Rev 1
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54
AHBS
7
ITCM
64 Kbyte
LTDC
D1-to-D2 AHB
USBHS2
I-bus
DMA2D
Ethernet SDMMC2 USBHS1
MAC
S-bus
MDMA
DMA1_MEM
SDMMC1
DMA2
DMA2_MEM
DMA1
DMA2_PERIPH
DTCM
128 Kbyte
AHBP
AXIM
I$
D$
16KB 16KB
CPU
Cortex-M4
DMA1_PERIPH
Cortex-M7
D-bus
CPU
ART
Functional overview
32/252
Figure 5. STM32H745xI/G bus matrix
SRAM1 128
Kbyte
APB3
4
AHB3
SRAM2 128
Kbyte
SRAM3
32 Kbyte
Flash A
Up to 1 Mbyte
5
DS12923 Rev 1
AHB1
Flash B
Up to 1 Mbyte
AHB2
AXI SRAM
512 Kbyte
APB1
QSPI
APB2
FMC
1
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D2 domain
2
D2-to-D1 AHB
D2-to-D3 AHB
BDMA
D1-to-D3 AHB
3
32-bit bus
TCM AHB
AXI
APB
64-bit bus
Master interface
Bus multiplexer
Slave interface
6
AHB4
APB4
SRAM4
64 Kbyte
32-bit AHB bus matrix
D3 domain
Backup
SRAM
4 Kbyte
MSv39740V3
STM32H745xI/G
Legend
STM32H745xI/G
3.10
Functional overview
DMA controllers
The devices feature four DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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54
Functional overview
3.12
STM32H745xI/G
Nested vectored interrupt controller (NVIC)
Both Cortex®-M7 (CPU1) and Cortex®-M4 (CPU2) cores have their own nested vector
interrupt controller (respectively NVIC1 and NVIC2). Each NVIC instance is able to manage
16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt
lines of the Cortex®-M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processors, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events (including two interrupt lines for inter-core management).
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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STM32H745xI/G
3.15
Functional overview
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
3.16
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•
Direct mode through registers
•
External Flash status register polling mode
•
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H745xI/G devices embed three analog-to-digital converters, which resolution
can be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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54
Functional overview
STM32H745xI/G
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H745xI/G devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 up to +140 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
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STM32H745xI/G
3.20
Functional overview
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
external triggers for conversion
•
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H745xI/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
An external I/O
•
A DAC output channel
•
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H745xI/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
One positive input connected to DAC
•
Output connected to internal ADC
•
Low input bias current down to 1 nA
•
Low input offset voltage down to 1.5 mV
•
Gain bandwidth up to 7.3 MHz
DS12923 Rev 1
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54
Functional overview
STM32H745xI/G
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
up to 24-bit output data resolution, signed output data format
•
automatic data offset correction (offset stored in register by user)
•
continuous or single conversion
•
start-of-conversion triggered by:
•
38/252
internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
DS12923 Rev 1
STM32H745xI/G
•
Functional overview
short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
•
break signal generation on analog watchdog event or on short circuit detector event
•
extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
•
DMA capability to read the final conversion data
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 4. DFSDM implementation
DFSDM features
3.24
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 105 Mbyte/s using a 60 MHz pixel clock. It
features:
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports Continuous mode or Snapshot (a single frame) mode
•
Capability to automatically crop the image
DS12923 Rev 1
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54
Functional overview
3.25
STM32H745xI/G
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
3.26
•
2 display layers with dedicated FIFO (64x64-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
•
AXI master interface with burst of 16 words
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 109181 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
3.27
•
8-bit/channel pixel depths
•
Single clock per pixel encoding and decoding
•
Support for JPEG header generation and parsing
•
Up to four programmable quantization tables
•
Fully programmable Huffman tables (two AC and two DC)
•
Fully programmable minimum coded unit (MCU)
•
Encode/decode support (non simultaneous)
•
Single clock Huffman coding and decoding
•
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
•
Support for single greyscale component
•
Ability to enable/disable header processing
•
Fully synchronous design
•
Configuration for High-speed decode mode
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.28
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten generalpurpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
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Functional overview
All timer counters can be frozen in Debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison
Timer
type
Timer
Highresolution HRTIM1
timer
Advanced
-control
TIM1,
TIM8
TIM2,
TIM5
TIM3,
TIM4
TIM12
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
TIM15
TIM16,
TIM17
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)(2)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes
10
Yes
480(2)
480
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
Yes
120
240
32-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
120
240
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
120
240
16-bit
Up
Any
integer
between 1
and
65536
No
2
No
120
240
Up
Any
integer
between 1
and
65536
No
1
No
120
240
Up
Any
integer
between 1
and
65536
Yes
2
1
120
240
Up
Any
integer
between 1
and
65536
Yes
1
1
120
240
16-bit
Up
General
purpose
TIM13,
TIM14
Complementary
output
16-bit
16-bit
16-bit
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54
Functional overview
STM32H745xI/G
Table 5. Timer feature comparison (continued)
Timer
type
Timer
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and
65536
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32, 64,
128
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)(2)
Yes
0
No
120
240
No
0
No
120
240
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
2. On STM32H745xxx3 sales types (extended industrial temperature range), the maximum clock frequency is 300 MHz for the
high-resolution timer and 150 MHz for the other timers.
3.28.1
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz(a) The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
a. Up to 300 MHz for STM32H745xxx3 sales types (extended industrial temperature range).
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3.28.2
Functional overview
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (Edge- or Center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.28.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H745xI/G
devices (see Table 5 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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54
Functional overview
3.28.4
STM32H745xI/G
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.28.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.28.6
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / One-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdogs
There are two independent watchdogs, one per domain. Each independent watchdog is
based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32
kHz internal RC and as it operates independently from the main clock, it can operate in Stop
and Standby modes. It can be used either as a watchdog to reset the device when a
problem occurs, or as a free-running timer for application timeout management. It is
hardware- or software-configurable through the option bytes.
3.28.7
Window watchdogs
There are two window watchdogs, one per domain. Each window watchdog is based on a 7bit downcounter that can be set as free-running. It can be used as a watchdog to reset the
device or each respective domain (configurable in the RCC register), when a problem
occurs. It is clocked from the main clock. It has an early warning interrupt capability and the
counter can be frozen in Debug mode.
3.28.8
SysTick timer
The devices feature two SysTick timers, one per CPU. These timers are dedicated to realtime operating systems, but could also be used as a standard downcounter. It features:
44/252
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
DS12923 Rev 1
STM32H745xI/G
3.29
Functional overview
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
DS12923 Rev 1
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54
Functional overview
3.30
STM32H745xI/G
Inter-integrated circuit interface (I2C)
STM32H745xI/G devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
3.31
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H745xI/G devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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DS12923 Rev 1
STM32H745xI/G
Functional overview
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 6. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
16
1. X = supported.
3.32
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
DS12923 Rev 1
47/252
54
Functional overview
STM32H745xI/G
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.33
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in Master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability.
3.34
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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DS12923 Rev 1
STM32H745xI/G
3.35
Functional overview
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.36
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
Full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
DS12923 Rev 1
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54
Functional overview
3.37
STM32H745xI/G
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
3.38
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from Stop mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.39
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
50/252
DS12923 Rev 1
STM32H745xI/G
3.40
Functional overview
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
9 bidirectional endpoints (including EP0)
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
3.41
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
DS12923 Rev 1
51/252
54
Functional overview
STM32H745xI/G
The devices include the following features:
3.42
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.43
Debug infrastructure
The devices offer a comprehensive set of debug and trace features on both cores to support
software development and system integration.
•
Breakpoint debugging
•
Code execution tracing
•
Software instrumentation
•
JTAG debug port
•
Serial-wire debug port
•
Trigger input and output
•
Serial-wire trace port
•
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The debug infrastructure allows debugging one core at a time, or
both cores in parallel.
The trace port performs data capture for logging and analysis.
52/252
DS12923 Rev 1
STM32H745xI/G
Functional overview
A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com
port. In Trace mode, the trace is transferred by DMA to system RAM or to a high-speed
interface (such as SPI or USB). It can even be monitored by a software running on one of
the cores. Unlike hardware FIFO mode, this mode is invasive since it uses system
resources which are shared by the processors.
DS12923 Rev 1
53/252
54
Memory mapping
4
STM32H745xI/G
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
54/252
DS12923 Rev 1
STM32H745xI/G
5
Pin descriptions
Pin descriptions
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS
VDD
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS
VDD
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VCAP
VSS
PDR_ON
VDDLDO
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
Figure 6. LQFP144 pinout
PA15
PA14
VDD
VDDLDO
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VDD33USB
VDD50USB
VSS
PG8
PG7
PG6
PD15
PD14
PD13
PD12
PD11
VSS
VDD
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VDDLDO
VSS
VCAP
PB11
PB10
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
VDD
VSS
PF15
PF14
PF11
PB2
PB1
PB0
PC5
PC4
PA7
PA6
PA5
PA4
VDD
VSS
PA3
PA2
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
144-pins
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PA1
PE2
PE3
PE4
PE5
PE6
VSS
VDD
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSS
VSSA
VREF+
VDDA
MSv43750V3
DS12923 Rev 1
55/252
104
Pin descriptions
STM32H745xI/G
PE2
PE3
PE4
PE5
PE6
VSS
VDD
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PA1
PA2
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-pins
134
133
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VDD
VDDLDO
PDR_ON
VSS
VCAP
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VSS
VDD
VDDLDO
VSS
VCAP
Figure 7. LQFP176 pinout
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA13
PA12
PA11
PA10
PA9
PA8
VDD
PC9
PC8
PC7
PC6
VDD33USB
VDD50USB
VSS
PG8
PG7
PG6
PG5
PG4
VDD
VSS
PG3
PG2
PK2
PK1
PK0
VSS
VDD
PJ11
PJ10
PJ9
PJ8
VSS
VDD
PD15
PD14
PD13
PD12
PD11
VSS
VDD
PD10
PD9
PD8
VSS
PA3
VSS
NC
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
PF13
PF14
PF15
PG0
VSS
VDD
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDDLDO
VSS
VDD
PB12
PB13
PB14
PB15
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv43751V3
1. The above figure shows the package top view.
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DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Figure 8. UFBGA176+25 ballout
1
2
3
4
5
6
7
8
9
10
11
VCAP
PB6
PB3
PG11
PG9
PD3
PD1
PA15
12
13
14
PA14
VDD
LDO
15
VCAP
VSS
PA8
PA12
A
VSS
PB8
VDD
LDO
B
PE4
PE3
PB9
PE0
PB7
PB4
PG13
PD7
PD5
PD2
PC12
PH14
C
PC13
VSS
PE2
PE1
BOOT0
PB5
PG14
PG10
PD4
PD0
PC11
PC10
PH13
PA10
PA11
D
PC15OSC32
_OUT
PC14OSC32_
IN
PE5
PDR_
ON
VDD
VSS
PG15
PG12
PD6
VSS
VDD
PH15
PA9
PC8
PC7
E
VSS
VBAT
PE6
VDD
VDD
PC9
PC6
VDD50
USB
F
VLX
SMPS
VSS
SMPS
PF1
PF0
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
USB
PG6
PG5
G
VDD
SMPS
VFB
SMPS
PF2
VDD
VSS
VSS
VSS
VSS
VSS
PG8
PG7
PG4
PG2
H
PF6
PF4
PF5
PF3
VSS
VSS
VSS
VSS
VSS
VDD
PG3
PD14
PD13
J
PH0OSC_IN
PF8
PF7
PF9
VSS
VSS
VSS
VSS
VSS
PD15
PD11
VSS
PD12
K
PH1OSC_
OUT
VSS
PF10
VDD
VSS
VSS
VSS
VSS
VSS
VSS
PD9
PB15
PB14
L
NRST
PC0
PC1
VREF-
VDD
PD10
PD8
PB13
M
PC2
PC3
VREF+
VDDA
VDD
VSS
PC5
PB1
VDD
VSS
PH7
PE14
PH11
PH9
PB12
N
PC2_C
PC3_C
VSSA
PH2
PA3
PA7
PF11
PE8
PG1
PF15
PF13
PB10
PH8
PH10
PH12
PA1
PA1_C
PH4
PA4
PA5
PB2
PG0
PE7
PB11
PF12
PE12
PE13
PE15
PH6
PA2
PA0_C
PH3
PH5
PC4
PA6
PB0
PE10
PF14
PE9
PE11
VCAP
VDD
LDO
VSS
P
R
PA0
VSS
PA13
MSv43752V4
1. The above figure shows the package top view.
DS12923 Rev 1
57/252
104
Pin descriptions
STM32H745xI/G
PH14
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VDD
VSS
PI7
PI6
PI5
PI4
VDDLDO
PDR_ON
VSS
VCAP
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
PI3
PI2
PI1
VDD
VSS
PI0
PH15
Figure 9. LQFP208 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
208-pins
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PH13
VDD
VDDLDO
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VDD50USB
VSS
PG8
PG7
PG6
PG5
PG4
VDD
VSS
PG3
PG2
PK2
PK1
PK0
VSS
VDD
PJ11
PJ10
PJ9
PJ8
VSS
VDD
PJ7
PJ6
PD15
PD14
VDD
VSS
PD13
PD12
PD11
VSS
VDD
PD10
PD9
PD8
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PI15
PF11
PF12
PF13
PF14
PF15
PG0
VSS
VDD
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDDLDO
PH6
PH7
PH8
PH9
PH10
PH11
PH12
VSS
VDD
PB12
PB13
PB14
PB15
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PE2
PE3
PE4
PE5
PE6
VSS
VDD
VBAT
PI8
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
VDD
VSS
PH3
PH4
MSv43753V3
1. The above figure shows the package top view.
58/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Figure 10. TFBGA240+25 ballout
A
B
C
1
2
3
4
VSS
PI6
PI5
VBAT
VSS
PC15PC14OSC32_ OSC32
OUT
_IN
5
6
7
8
9
10
11
12
13
14
15
16
17
PI4
PB5
VDD
LDO
VCAP
PK5
PG10
PG9
PD5
PD4
PC10
PA15
PI1
PI0
VSS
PI7
PE1
PB6
VSS
PB4
PK4
PG11
PJ15
PD6
PD3
PC11
PA14
PI2
PH15
PH14
PE2
PE0
PB7
PB3
PK6
PK3
PG12
VSS
PD7
PC12
VSS
PI3
PA13
VSS
VDD
LDO
D
PE5
PE4
PE3
PB9
PB8
PG15
PK7
PG14
PG13
PJ14
PJ12
PD2
PD0
PA10
PA9
PH13
VCAP
E
VLX
SMPS
PI9
PC13
PI8
PE6
VDD
PDR
_ON
BOOT0
VDD
PJ13
VDD
PD1
PC8
PC9
PA8
PA12
PA11
F
VDD
SMPS
VSS
SMPS
PI10
PI11
VDD
PC7
PC6
PG8
PG7
VDD
33USB
G
PF2
VFB
SMPS
PF1
PF0
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PG5
PG6
VSS
VDD
50USB
H
PI12
PI13
PI14
PF3
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PG4
PG3
PG2
PK2
J
PH1OSC_
OUT
PH0OSC
_IN
VSS
PF5
PF4
VSS
VSS
VSS
VSS
VSS
VDD
PK0
PK1
VSS
VSS
K
NRST
PF6
PF7
PF8
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PJ11
VSS
NC
NC
L
VDDA
PC0
PF10
PF9
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PJ10
VSS
NC
NC
M
VREF+
PC1
PC2
PC3
VDD
VDD
PJ9
VSS
NC
NC
N
VREF-
PH2
PA2
PA1
PA0
PJ0
VDD
VDD
PE10
VDD
VDD
VDD
PJ8
PJ7
PJ6
VSS
NC
P
VSSA
PH3
PH4
PH5
PI15
PJ1
PF13
PF14
PE9
PE11
PB10
PB11
PH10
PH11
PD15
PD14
VDD
R
PC2_C
PC3_C
PA6
VSS
PA7
PB2
PF12
VSS
PF15
PE12
PE15
PJ5
PH9
PH12
PD11
PD12
PD13
T
PA0_C
PA1_C
PA5
PC4
PB1
PJ2
PF11
PG0
PE8
PE13
PH6
VSS
PH8
PB12
PB15
PD10
PD9
U
VSS
PA3
PA4
PC5
PB0
PJ3
PJ4
PG1
PE7
PE14
VCAP
VDD
LDO
PH7
PB13
PB14
PD8
VSS
MSv43744V3
1. The above figure shows the package top view.
DS12923 Rev 1
59/252
104
Pin descriptions
STM32H745xI/G
Table 7. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
I/O structure
Notes
Pin functions
60/252
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition
2
3
4
C3
B2
B1
D3
2
3
4
1
2
3
4
C3
D3
D2
D1
PE2
PE3
PE4
PE5
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
1
Pin name
(function
after reset)
I/O
FT_
h
I/O
FT_
h
I/O
I/O
Notes
1
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
-
TRACED0, TIM15_BKIN,
SAI1_SD_B,
SAI4_SD_B, FMC_A19,
EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A,
SAI4_CK2, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
-
-
FT_
h
FT_
h
5
E3
5
5
E5
PE6
I/O
FT_
h
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
6
A1
6
6
A1
VSS
S
-
-
-
-
7
D5
7
7
-
VDD
S
-
-
-
-
8
E2
8
8
B1
VBAT
S
-
-
-
-
-
A15
-
-
B2
VSS
S
-
-
-
-
DS12923 Rev 1
61/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
-
9
E4
PI8
I/O
FT
-
EVENTOUT
RTC_TAMP2/WK
UP3
9
C1
9
10
E3
PC13
I/O
FT
-
EVENTOUT
RTC_TAMP1/RTC
_TS/WKUP2
-
C2
-
-
-
VSS
S
-
-
-
-
I/O
FT
-
EVENTOUT
OSC32_IN
I/O
FT
-
EVENTOUT
OSC32_OUT
I/O
FT_
h
-
UART4_RX,
FDCAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
-
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
10
D2
10
11
C2
PC14OSC32_IN
(OSC32_IN)
Additional
functions
(1)
11
-
D1
-
11
-
12
13
C1
E2
PC15OSC32_OUT
(OSC32_
OUT)(1)
PI9
-
-
-
14
F3
PI10
I/O
FT_
h
-
-
-
15
F4
PI11
I/O
FT
-
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
12
D10
12
16
A17
VSS
S
-
-
-
-
13
D11
13
17
E6
VDD
S
-
-
-
-
14
F2
14
18
F2
VSSSMPS
S
-
-
-
-
15
F1
15
19
E1
VLXSMPS
S
-
-
-
-
16
G1
16
20
F1
VDDSMPS
S
-
-
-
-
17
G2
17
21
G2
VFBSMPS
S
-
-
-
-
-
F4
18
22
G4
PF0
I/O
FT_f
-
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
F3
19
23
G3
PF1
I/O
FT_f
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
G3
20
24
G1
PF2
I/O
FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
62/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
-
-
H1
PI12
I/O
FT
-
LCD_HSYNC,
EVENTOUT
-
-
-
-
-
H2
PI13
I/O
FT
-
LCD_VSYNC,
EVENTOUT
-
-
-
-
-
H3
PI14
I/O
FT_
h
-
LCD_CLK, EVENTOUT
-
-
H4
21
25
H4
PF3
I/O
FT_
ha
-
FMC_A3, EVENTOUT
ADC3_INP5
-
H2
22
26
J5
PF4
I/O
FT_
ha
-
FMC_A4, EVENTOUT
ADC3_INN5,
ADC3_INP9
-
H3
23
27
J4
PF5
I/O
FT_
ha
-
FMC_A5, EVENTOUT
ADC3_INP4
18
E1
24
28
C10
VSS
S
-
-
-
-
19
E4
25
29
E9
VDD
S
-
-
-
-
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_INN4,
ADC3_INP8
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_INP3
-
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE
, SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
-
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_INP2
20
21
22
23
H1
J3
J2
J4
26
27
28
29
30
31
32
33
K2
K3
K4
L4
PF6
PF7
PF8
PF9
I/O
I/O
I/O
I/O
FT_
ha
FT_
ha
FT_
ha
FT_
ha
DS12923 Rev 1
Additional
functions
63/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
PF10
I/O
25
J1
31
35
J2
PH0OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
26
K1
32
36
J1
PH1OSC_OUT
(PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
27
L1
33
37
K1
NRST
I/O
RST
-
-
-
-
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_INP10
-
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A,
SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
MDIOS_MDC,
EVENTOUT
ADC123_INN10,
ADC123_INP11,
RTC_TAMP3/WK
UP5
28
L2
34
38
L2
Pin name
(function
after reset)
PC0
I/O
Notes
I/O structure
L3
TFBGA240+25
34
LQFP208
30
LQFP176
K3
UFBGA176+25
24
FT_
ha
LQFP144
Pin type
Pin/ball name
Alternate functions
-
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
FT_
a
29
L3
35
39
M2
PC1
I/O
FT_
ha
-
M1
-
-
M3(2)
PC2
I/O
FT_
a
-
40(3)
R1(2)
PC2_C
ANA
TT_
a
-
-
M4(2)
PC3
I/O
FT_
a
-
41(3)
R2(2)
PC3_C
ANA
TT_
a
-
30(3) N1(3) 36(3)
-
M2
-
31(3) N2(3) 37(3)
64/252
DS12923 Rev 1
Additional
functions
ADC3_INN2,
ADC3_INP6
C1DSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_INN11,
ADC123_INP12
C1SLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC12_INN12,
ADC12_INP13
ADC3_INN1,
ADC3_INP0
ADC3_INP1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
32
E12
-
-
E11
VDD
S
-
-
-
-
33
F6
-
-
C13
VSS
S
-
-
-
-
34
N3
38
42
P1
VSSA
S
-
-
-
-
-
L4
-
-
N1
VREF-
S
-
-
-
-
35
M3
39
43
M1
VREF+
S
-
-
-
-
36
M4
40
44
L1
VDDA
S
-
-
-
-
37
P1
41
45
N5(2)
PA0
I/O
FT_
a
-
ADC1_INP16,
WKUP0
-
R3
-
-
T1(2)
PA0_C
ANA
TT_
a
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
38
P2
42
46
N4(2)
PA1
I/O
FT_
ha
-
-
P3
-
-
T2(2)
PA1_C
ANA
TT_
a
-
39
R2
43
47
N3
PA2
I/O
FT_
a
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC12_INN1,
ADC12_INP0
ADC1_INN16,
ADC1_INP17
ADC12_INP1
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX,
SAI2_SCK_B,
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP1
ADC3_INP13
-
-
N4
-
48
N2
PH2
I/O
FT_
ha
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
G4
44
49
F5
VDD
S
-
-
-
DS12923 Rev 1
Additional
functions
65/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP208
TFBGA240+25
F7
45
50
C16
VSS
S
Notes
LQFP176
-
I/O structure
UFBGA176+25
Pin name
(function
after reset)
Pin type
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
-
-
-
ADC3_INN13,
ADC3_INP14
-
R4
-
51
P2
PH3
I/O
FT_
ha
-
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
P4
-
52
P3
PH4
I/O
FT_f
a
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
ADC3_INN14,
ADC3_INP15
-
R5
-
53
P4
PH5
I/O
FT_f
a
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
ADC3_INN15,
ADC3_INP16
ADC12_INP15
40
N5
46
54
U2
PA3
I/O
FT_
ha
-
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
41
F8
47
55
-
VSS
S
-
-
-
-
42
H12
48
56
G5
VDD
S
-
-
-
-
-
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_INP18,
DAC1_OUT1
-
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
43
44
66/252
P5
P6
49
50
57
58
U3
T3
PA4
PA5
I/O
I/O
TT_
a
TT_
ha
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
46
47
R7
N6
R6
52
53
59
60
61
R3
R5
T4
PA6
PA7
PC4
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
51
Pin name
(function
after reset)
Notes
45
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO,
TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_INP3
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI,
TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
-
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_R
MII_RXD0,
FMC_SDNE0,
EVENTOUT
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
FT_
a
TT_
a
TT_
a
48
M7
54
62
U4
PC5
I/O
TT_
a
-
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
-
K4
-
-
G13
VDD
S
-
-
-
-
-
F9
-
-
R4
VSS
S
-
-
-
-
DS12923 Rev 1
67/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
50
R8
M8
56
63
64
U5
T5
PB0
PB1
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
55
Pin name
(function
after reset)
Notes
49
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
COMP1_INP
FT_
a
TT_
u
51
P7
57
65
R6
PB2
I/O
FT_
ha
-
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
-
-
-
66
P5
PI15
I/O
FT
-
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
-
N6
PJ0
I/O
FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
P6
PJ1
I/O
FT
-
LCD_R2, EVENTOUT
-
-
-
-
-
T6
PJ2
I/O
FT
-
LCD_R3, EVENTOUT
-
-
-
-
-
U6
PJ3
I/O
FT
-
LCD_R4, EVENTOUT
-
-
-
-
-
U7
PJ4
I/O
FT
-
LCD_R5, EVENTOUT
-
52
N7
58
67
T7
PF11
I/O
FT_
a
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
ADC1_INP2
-
P11
59
68
R7
PF12
I/O
FT_
ha
-
FMC_A6, EVENTOUT
ADC1_INN2,
ADC1_INP6
-
F10
-
-
J3
VSS
S
-
-
-
-
-
L12
-
-
H5
VDD
S
-
-
-
-
-
N11
60
69
P7
PF13
I/O
FT_
ha
-
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
ADC2_INP2
68/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
53
R10
61
70
P8
PF14
I/O
FT_f
ha
-
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INN2,
ADC2_INP6
54
N10
62
71
R9
PF15
I/O
FT_f
h
-
I2C4_SDA, FMC_A9,
EVENTOUT
-
-
P8
63
72
T8
PG0
I/O
FT_
h
-
FMC_A10, EVENTOUT
-
55
F12
64
73
J16
VSS
S
-
-
-
-
56
M5
65
74
H13
VDD
S
-
-
-
-
-
N9
66
75
U8
PG1
I/O
TT_
h
-
FMC_A11, EVENTOUT
OPAMP2_VINM
-
TIM1_ETR,
DFSDM1_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
OPAMP2_VOUT,
COMP2_INM
-
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
OPAMP2_VINM
OPAMP2_VINP,
COMP2_INP
57
58
P9
N8
67
68
76
77
U9
T9
PE7
PE8
I/O
I/O
TT_
ha
TT_
ha
Additional
functions
59
R11
69
78
P9
PE9
I/O
TT_
ha
-
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_DE
, QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
-
G6
70
79
J17
VSS
S
-
-
-
-
-
M9
71
80
J13
VDD
S
-
-
-
-
-
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
COMP2_INM
60
R9
72
81
N9
PE10
I/O
FT_
ha
DS12923 Rev 1
69/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
62
R12
P12
74
82
83
P10
R10
PE11
PE12
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
73
Pin name
(function
after reset)
Notes
61
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP2_INP
-
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
-
FT_
ha
FT_
h
63
P13
75
84
T10
PE13
I/O
FT_
h
-
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
G7
-
-
T12
VSS
S
-
-
-
-
-
-
-
-
K13
VDD
S
-
-
-
-
I/O
FT_
h
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
-
-
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/C
OMP_TIM1_BKIN,
LCD_R7, EVENTOUT
-
-
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
64
65
66
70/252
M12
P14
N12
76
77
78
85
86
87
U10
R11
P11
PE14
PE15
PB10
I/O
I/O
FT_
h
FT_f
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
P10
79
88
P12
PB11
I/O
FT_f
-
68
R13
80
89
U11
VCAP
S
-
-
-
-
69
M10
81
90
-
VSS
S
-
-
-
-
70
R14
82
91
U12
VDDLDO
S
-
-
-
-
71
-
-
-
L13
VDD
S
-
-
-
-
-
-
-
-
R12
PJ5
I/O
FT
-
LCD_R6, EVENTOUT
-
-
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-
-
-
P15
M11
-
-
LQFP208
67
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
LQFP176
Alternate functions
LQFP144
Notes
I/O structure
Pin name
(function
after reset)
Pin type
TFBGA240+25
UFBGA176+25
Pin/ball name
92
93
T11
U13
PH6
PH7
I/O
FT
I/O
FT_f
a
-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
Additional
functions
-
-
N13
-
94
T13
PH8
I/O
FT_f
ha
-
G9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
M13
VDD
S
-
-
-
-
-
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
-
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
-
M14
-
95
R13
PH9
I/O
FT_
h
-
N14
-
96
P13
PH10
I/O
FT_
h
DS12923 Rev 1
71/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
M13
-
97
P14
PH11
I/O
FT_f
h
-
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
-
N15
-
98
R14
PH12
I/O
FT_f
h
-
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
-
G10
83
99
N16
VSS
S
-
-
-
-
-
-
84
100
-
VDD
S
-
-
-
-
-
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FDCAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
-
-
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_
NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
OTG_HS_VBUS
-
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_
DE,
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
-
72
73
74
72/252
M15
L15
K15
85
86
87
101
102
103
T14
U14
U15
PB12
PB13
PB14
I/O
I/O
I/O
FT_
u
FT_
u
FT_
u
DS12923 Rev 1
Additional
functions
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
76
77
K14
L14
K13
89
90
104
105
106
T15
U16
T17
PB15
PD8
PD9
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
88
Pin name
(function
after reset)
Notes
75
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
-
-
DFSDM1_CKIN3,
SAI3_SCK_B,
USART3_TX,
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
-
-
DFSDM1_DATIN3,
SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
-
-
FT_
u
FT_
h
FT_
h
78
L13
91
107
T16
PD10
I/O
FT_
h
-
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
79
-
92
108
N12
VDD
S
-
-
-
-
80
H6
93
109
U17
VSS
S
-
-
-
-
-
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
81
J13
94
110
R15
PD11
I/O
FT_
h
DS12923 Rev 1
73/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
J15
111
R16
PD12
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
95
Pin name
(function
after reset)
Notes
82
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
-
FT_f
h
83
H15
96
112
R17
PD13
I/O
FT_f
h
-
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
R1
-
113
-
VSS
S
-
-
-
-
-
-
-
114
N11
VDD
S
-
-
-
-
-
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
-
-
84
H14
97
115
P16
PD14
I/O
FT_
h
85
J12
98
116
P15
PD15
I/O
FT_
h
-
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/UART8_DE
, FMC_D1/FMC_DA1,
EVENTOUT
-
-
-
117
N15
PJ6
I/O
FT
-
TIM8_CH2, LCD_R7,
EVENTOUT
-
-
-
-
118
N14
PJ7
I/O
FT
-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT
-
-
-
99
119
N10
VDD
S
-
-
-
-
-
D6
100
120
R8
VSS
S
-
-
-
-
-
-
101
121
N13
PJ8
I/O
FT
-
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
-
-
102
122
M14
PJ9
I/O
FT
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
-
-
103
123
L14
PJ10
I/O
FT
-
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
74/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
104
124
K14
PJ11
I/O
FT
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
-
105
125
N8
VDD
S
-
-
-
-
-
-
-
-
P17
VDD
S
-
-
-
-
-
R15
106
126
U1
VSS
S
-
-
-
-
-
-
-
-
N17
NC
-
-
-
-
-
-
-
-
-
M16
NC
-
-
-
-
-
-
-
-
-
M17
NC
-
-
-
-
-
-
-
-
-
K15
VSS
S
-
-
-
-
-
-
-
-
L16
NC
-
-
-
-
-
-
-
-
-
L17
NC
-
-
-
-
-
-
-
-
-
K16
NC
-
-
-
-
-
-
-
-
-
K17
NC
-
-
-
-
-
-
-
-
-
L15
VSS
S
-
-
-
-
-
-
107
127
J14
PK0
I/O
FT
-
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
-
-
108
128
J15
PK1
I/O
FT
-
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
-
Additional
functions
-
-
109
129
H17
PK2
I/O
FT
-
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
G15
110
130
H16
PG2
I/O
FT_
h
-
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
-
-
H13
111
131
H15
PG3
I/O
FT_
h
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
-
H10
112
132
-
VSS
S
-
-
-
-
-
-
113
133
N7
VDD
S
-
-
-
-
DS12923 Rev 1
75/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
PG4
I/O
-
F15
115
135
G14
PG5
I/O
FT_
h
86
87
F14
G13
116
117
136
137
G15
F16
Pin name
(function
after reset)
PG6
PG7
I/O
I/O
Notes
I/O structure
H14
TFBGA240+25
134
LQFP208
114
LQFP176
G14
UFBGA176+25
-
FT_
h
LQFP144
Pin type
Pin/ball name
Alternate functions
-
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
-
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
-
-
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
-
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
FT_
h
FT_
h
Additional
functions
-
88
G12
118
138
F15
PG8
I/O
FT_
h
-
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
89
J6
119
139
G16
VSS
S
-
-
-
-
90
E15
120
140
G17
VDD50USB
S
-
-
-
-
91
F13
121
141
F17
VDD33USB
S
-
-
-
-
92
-
-
-
M5
VDD
S
-
-
-
-
-
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
SWPMI_IO
93
76/252
E14
122
142
F14
PC6
I/O
FT_
h
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
95
D15
D14
124
143
144
F13
E13
PC7
PC8
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
123
Pin name
(function
after reset)
Notes
94
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE
, FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
-
FT_
h
FT_
h
96
E13
125
145
E14
PC9
I/O
FT_f
h
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
J7
-
-
-
VSS
S
-
-
-
-
-
-
126
-
L5
VDD
S
-
-
-
-
-
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
97
B14
127
146
E15
PA8
I/O
FT_f
ha
DS12923 Rev 1
77/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
99
100
D13
C14
C15
129
130
147
148
149
D15
D14
E17
PA9
PA10
PA11
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
128
Pin name
(function
after reset)
Notes
98
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
OTG_FS_VBUS
-
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
-
-
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
-
-
FT_
u
FT_
u
FT_
u
101
B15
131
150
E16
PA12
I/O
FT_
u
-
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/LPUART
1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
102
B13
132
151
C15
PA13(JTMS/
SWDIO)
I/O
FT
-
JTMS-SWDIO,
EVENTOUT
-
103
A14
133
152
D17
VCAP
S
-
-
-
-
104
M6
134
153
-
VSS
S
-
-
-
-
78/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
LQFP144
UFBGA176+25
LQFP176
LQFP208
TFBGA240+25
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
105
A13
135
154
C17
VDDLDO
-
-
-
-
-
106
-
136
155
K5
VDD
S
-
-
-
-
I/O
FT_
h
-
TIM8_CH1N,
UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
TIM8_CH2N,
UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
-
TIM8_CH3N,
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
-
-
-
-
-
C13
B12
D12
-
-
-
156
157
158
D16
B17
B16
PH13
PH14
PH15
I/O
FT_
h
I/O
FT_
h
Additional
functions
-
-
-
159
A16
PI0
I/O
FT_
h
-
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
J9
-
160
-
VSS
S
-
-
-
-
-
-
-
161
VDD
VDD
S
-
-
-
-
-
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
-
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
-
-
-
-
-
-
-
162
163
A15
B15
PI1
PI2
I/O
FT_
h
I/O
FT_
h
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
-
164
C14
PI3
I/O
FT_
h
-
J10
137
-
-
VSS
S
-
-
-
-
-
-
-
-
VDD
VDD
S
-
-
-
-
107
A12
138
165
B14
PA14(JTCK/
SWCLK)
I/O
FT
-
JTCK-SWCLK,
EVENTOUT
-
DS12923 Rev 1
79/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
109
110
A11
C12
C11
140
141
166
167
168
A14
A13
B13
PA15(JTDI)
PC10
PC11
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
139
Pin name
(function
after reset)
Notes
108
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
-
-
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
-
FT
FT_
ha
FT_
h
111
B11
142
169
C12
PC12
I/O
FT_
h
-
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
-
J14
-
-
-
VSS
S
-
-
-
-
-
-
-
-
VDD
VDD
S
-
-
-
-
-
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
-
112
80/252
C10
143
170
D13
PD0
I/O
FT_
h
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
114
115
116
A10
B10
A9
C9
145
146
147
171
172
173
174
E12
D12
B12
A12
PD1
PD2
PD3
PD4
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
144
Pin name
(function
after reset)
I/O
FT_
h
I/O
FT_
h
I/O
Notes
113
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
-
-
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
-
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
-
-
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS/USART2_
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
-
-
FT_
h
I/O
FT_
h
-
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
117
B9
148
175
A11
PD5
I/O
FT_
h
118
K2
-
-
-
VSS
S
-
-
-
-
119
-
-
-
VDD
VDD
S
-
-
-
-
-
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
-
120
D9
149
176
B11
PD6
I/O
FT_
h
DS12923 Rev 1
81/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
B8
150
177
C11
PD7
I/O
FT_
h
-
-
-
-
-
D11
PJ12
I/O
FT
-
TRGOUT, LCD_G3,
LCD_B0, EVENTOUT
-
-
-
-
-
E10
PJ13
I/O
FT
-
LCD_B4, LCD_B1,
EVENTOUT
-
-
-
-
-
D10
PJ14
I/O
FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
B10
PJ15
I/O
FT
-
LCD_B3, EVENTOUT
-
-
K6
151
178
-
VSS
S
-
-
-
-
-
-
152
179
VDD
VDD
S
-
-
-
-
-
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
-
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
-
-
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
122
123
124
82/252
A8
C8
A7
153
154
155
LQFP208
121
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
LQFP176
Alternate functions
LQFP144
Notes
I/O structure
Pin name
(function
after reset)
Pin type
TFBGA240+25
UFBGA176+25
Pin/ball name
180
181
182
A10
A9
B9
PG9
PG10
PG11
I/O
I/O
I/O
FT_
h
FT_
h
FT_
h
DS12923 Rev 1
Additional
functions
-
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
126
D8
B7
157
183
184
C9
D9
PG12
PG13
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
156
Pin name
(function
after reset)
Notes
125
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
DE, SPDIFRX1_IN2,
LCD_B4,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
-
-
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6_
NSS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
-
FT_
h
FT_
h
127
C7
158
185
D8
PG14
I/O
FT_
h
-
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
K7
159
186
-
VSS
S
-
-
-
-
-
-
160
187
VDD
VDD
S
-
-
-
-
-
-
-
-
C8
PK3
I/O
FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
B8
PK4
I/O
FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
A8
PK5
I/O
FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
C7
PK6
I/O
FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
D7
PK7
I/O
FT
-
LCD_DE, EVENTOUT
-
128
K8
-
-
-
VSS
S
-
-
-
-
129
-
-
-
VDD
VDD
S
-
-
-
-
-
D7
161
188
D6
PG15
I/O
FT_
h
-
USART6_CTS/USART6_
NSS, FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
DS12923 Rev 1
83/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
131
A6
B6
163
189
190
C6
B7
PB3(JTDO/T
RACESWO)
PB4(NJTRS
T)
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
162
Pin name
(function
after reset)
Notes
130
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
SDMMC2_D2,
CRS_SYNC,
UART7_RX, EVENTOUT
-
-
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
-
-
FT
FT
132
C6
164
191
A5
PB5
I/O
FT
-
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
K9
-
-
-
VSS
S
-
-
-
-
-
-
-
-
VDD
VDD
S
-
-
-
-
84/252
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
A5
192
B5
PB6
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
165
Pin name
(function
after reset)
Notes
133
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX,
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
-
PVD_IN
FT_f
134
B5
166
193
C5
PB7
I/O
FT_f
a
-
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
135
C5
167
194
E8
BOOT0
I
B
-
-
VPP
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
136
A2
168
195
D5
PB8
I/O
FT_f
h
DS12923 Rev 1
85/252
104
Pin descriptions
STM32H745xI/G
Table 8. STM32H745xI/G pin/ball definition (continued)
138
B3
B4
170
196
197
D4
C4
PB9
PE0
I/O
I/O
I/O structure
Pin type
TFBGA240+25
LQFP208
LQFP176
169
Pin name
(function
after reset)
Notes
137
UFBGA176+25
LQFP144
Pin/ball name
Alternate functions
Additional
functions
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
-
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
-
FT_f
h
FT_
h
139
C4
171
198
B4
PE1
I/O
FT_
h
-
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
140
A4
172
199
A7
VCAP
S
-
-
-
-
141
K10
173
200
B6
VSS
S
-
-
-
-
142
D4
174
201
E7
PDR_ON
I
FT
-
-
-
143
A3
175
202
A6
VDDLDO
S
-
-
-
-
-
-
-
-
VDD
VDD
S
-
-
-
-
-
TIM8_BKIN,
SAI2_MCLK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
-
86/252
-
-
203
A4
PI4
I/O
FT_
h
DS12923 Rev 1
STM32H745xI/G
Pin descriptions
Table 8. STM32H745xI/G pin/ball definition (continued)
-
-
204
A3
PI5
I/O
FT_
h
-
-
-
-
205
A2
PI6
I/O
FT_
h
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
-
206
B3
PI7
I/O
FT_
h
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
-
-
K12
-
207
-
VSS
S
-
-
-
-
144
-
176
208
VDD
VDD
S
-
-
-
-
-
-
-
-
M15
VSS
S
-
-
-
-
LQFP208
-
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
LQFP176
Alternate functions
LQFP144
Notes
I/O structure
Pin name
(function
after reset)
Pin type
TFBGA240+25
UFBGA176+25
Pin/ball name
Additional
functions
-
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
3. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
DS12923 Rev 1
87/252
104
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PA0
-
TIM2_CH1/
TIM2_ETR
TIM5_CH1
TIM8_ETR
TIM15_BKIN
-
-
USART2_
CTS/
USART2_
NSS
UART4_TX
SDMMC2_
CMD
SAI2_SD_B
ETH_MII_
CRS
-
-
-
EVENT
OUT
PA1
-
TIM2_CH2
TIM5_CH2
LPTIM3_
OUT
TIM15_
CH1N
-
-
USART2_
RTS/
USART2_
DE
UART4_RX
QUADSPI_
BK1_IO3
SAI2_
MCLK_B
ETH_MII_RX
_CLK/ETH_
RMII_REF_
CLK
-
-
LCD_R2
EVENT
OUT
PA2
-
TIM2_CH3
TIM5_CH3
LPTIM4_
OUT
TIM15_CH1
-
-
USART2_
TX
SAI2_SCK
_B
-
-
ETH_MDIO
MDIOS_
MDIO
-
LCD_R1
EVENT
OUT
PA3
-
TIM2_CH4
TIM5_CH4
LPTIM5_
OUT
TIM15_CH2
-
-
USART2_
RX
-
LCD_B2
OTG_HS_
ULPI_D0
ETH_MII_
COL
-
-
LCD_B5
EVENT
OUT
PA4
D1PWR
EN
-
TIM5_ETR
-
-
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART2_
CK
SPI6_NSS
-
-
-
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENT
OUT
PA5
D2PWR
EN
TIM2_CH1/
TIM2_ETR
-
TIM8_
CH1N
-
SPI1_SCK/
I2S1_CK
-
-
SPI6_SCK
-
OTG_HS_
ULPI_CK
-
-
-
LCD_R4
EVENT
OUT
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_
MISO/I2S1
_SDI
-
-
SPI6_
MISO
TIM13_CH1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
DCMI_PIX
CLK
LCD_G2
EVENT
OUT
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_
CH1N
-
SPI1_
MOSI/I2S1
_SDO
-
-
SPI6_
MOSI
TIM14_CH1
-
ETH_MII_RX
_DV/ETH_
RMII_CRS_
DV
FMC_SDN
WE
-
-
EVENT
OUT
PA8
MCO1
TIM1_CH1
HRTIM_
CHB2
TIM8_BKIN
2
I2C3_SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
UART7_RX
TIM8_BKIN
2_COMP12
LCD_B3
LCD_R6
EVENT
OUT
PA9
-
TIM1_CH2
HRTIM_
CHC1
LPUART1_
TX
I2C3_SMBA
SPI2_SCK/
I2S2_CK
-
USART1_
TX
-
FDCAN1_
RXFD_
MODE
-
-
-
DCMI_D0
LCD_R5
EVENT
OUT
PA10
-
TIM1_CH3
HRTIM_
CHC2
LPUART1_
RX
-
-
-
USART1_
RX
-
FDCAN1_
TXFD_MOD
E
OTG_FS_
ID
MDIOS_
MDIO
LCD_B4
DCMI_D1
LCD_B1
EVENT
OUT
PA11
-
TIM1_CH4
HRTIM_
CHD1
LPUART1_
CTS
-
SPI2_NSS/
I2S2_WS
UART4_RX
USART1_
CTS/
USART1_
NSS
-
FDCAN1_
RX
OTG_FS_
DM
-
-
-
LCD_R4
EVENT
OUT
Port A
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
88/252
Table 9. Port A alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PA12
-
TIM1_ETR
HRTIM_
CHD2
LPUART1_
RTS/
LPUART1_
DE
-
SPI2_SCK/
I2S2_CK
UART4_TX
USART1_
RTS/
USART1_D
E
SAI2_FS_B
FDCAN1_
TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENT
OUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1
-
CEC
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
SPI6_NSS
UART4_
RTS/UART
4_DE
-
-
UART7_TX
-
-
-
EVENT
OUT
Port
Port A
AF1
STM32H745xI/G
Table 9. Port A alternate functions (continued)
DS12923 Rev 1
Pin descriptions
89/252
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2
N
-
-
DFSDM1_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_RX
D2
-
-
LCD_G1
EVENT
OUT
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3
N
-
-
DFSDM1_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
ETH_MII_RX
D3
-
-
LCD_G0
EVENT
OUT
PB2
RTC_
OUT
-
SAI1_D1
-
DFSDM1_
CKIN1
-
SAI1_SD_A
SPI3_
MOSI/I2S3
_SDO
SAI4_SD_
A
QUADSPI_
CLK
SAI4_D1
-
-
-
-
EVENT
OUT
PB3
JTDO/
TRACE
SWO
TIM2_CH2
HRTIM_
FLT4
-
-
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
-
SPI6_SCK
SDMMC2_D
2
CRS_SYNC
UART7_RX
-
-
-
EVENT
OUT
PB4
NJTRST
TIM16_
BKIN
TIM3_CH1
HRTIM_
EEV6
-
SPI1_
MISO/I2S1
_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/
I2S2_WS
SPI6_
MISO
SDMMC2_D
3
-
UART7_TX
-
-
-
EVENT
OUT
PB5
-
TIM17_
BKIN
TIM3_CH2
HRTIM_
EEV7
I2C1_SMBA
SPI1_
MOSI/I2S1
_SDO
I2C4_SMBA
SPI3_
MOSI/I2S3
_SDO
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_SDCK
E1
DCMI_D10
UART5_
RX
EVENT
OUT
PB6
-
TIM16_CH1
N
TIM4_CH1
HRTIM_
EEV8
I2C1_SCL
CEC
I2C4_SCL
USART1_
TX
LPUART1_
TX
FDCAN2_
TX
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_SDNE
1
DCMI_D5
UART5_
TX
EVENT
OUT
PB7
-
TIM17_CH1
N
TIM4_CH2
HRTIM_
EEV9
I2C1_SDA
-
I2C4_SDA
USART1_
RX
LPUART1_
RX
FDCAN2_
TXFD_
MODE
-
DFSDM1_
CKIN5
FMC_NL
DCMI_
VSYNC
-
EVENT
OUT
PB8
-
TIM16_CH1
TIM4_CH3
DFSDM1_
CKIN7
I2C1_SCL
-
I2C4_SCL
SDMMC1_
CKIN
UART4_RX
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_TX
D3
SDMMC1_
D4
DCMI_D6
LCD_B6
EVENT
OUT
PB9
-
TIM17_CH1
TIM4_CH4
DFSDM1_
DATIN7
I2C1_SDA
SPI2_NSS/
I2S2_WS
I2C4_SDA
SDMMC1_
CDIR
UART4_TX
FDCAN1_
TX
SDMMC2_
D5
I2C4_SMBA
SDMMC1_
D5
DCMI_D7
LCD_B7
EVENT
OUT
PB10
-
TIM2_CH3
HRTIM_SC
OUT
LPTIM2_IN
1
I2C2_SCL
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
-
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_RX
_ER
-
-
LCD_G4
EVENT
OUT
PB11
-
TIM2_CH4
HRTIM_
SCIN
LPTIM2_
ETR
I2C2_SDA
-
DFSDM1_
CKIN7
USART3_
RX
-
-
OTG_HS_
ULPI_D4
ETH_MII_TX
_EN/ETH_
RMII_TX_EN
-
-
LCD_G5
EVENT
OUT
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
-
FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_TX
D0/ETH_
RMII_TXD0
OTG_HS_
ID
TIM1_BKIN
_COMP12
UART5_
RX
EVENT
OUT
PB13
-
TIM1_CH1N
-
LPTIM2_
OUT
-
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
USART3_
CTS/
USART3_
NSS
-
FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/ETH_
RMII_TXD1
-
-
UART5_
TX
EVENT
OUT
Port B
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
90/252
Table 10. Port B alternate functions
AF0
AF1
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PB14
-
TIM1_CH2N
TIM12_CH
1
TIM8_CH2
N
USART1_TX
SPI2_
MISO/I2S2
_SDI
DFSDM1_
DATIN2
USART3_
RTS/USAR
T3_DE
UART4_
RTS/UART
4_DE
SDMMC2_
D0
-
-
OTG_HS_
DM
-
-
EVENT
OUT
PB15
RTC_
REFIN
TIM1_CH3N
TIM12_CH
2
TIM8_CH3
N
USART1_RX
SPI2_
MOSI/I2S2
_SDO
DFSDM1_
CKIN2
-
UART4_
CTS
SDMMC2_D
1
-
-
OTG_HS_
DP
-
-
EVENT
OUT
Port B
Port
STM32H745xI/G
Table 10. Port B alternate functions (continued)
DS12923 Rev 1
Pin descriptions
91/252
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PC0
-
-
-
DFSDM1_
CKIN0
-
-
DFSDM1_
DATIN4
-
SAI2_FS_B
-
OTG_HS_
ULPI_STP
-
FMC_SDN
WE
-
LCD_R5
EVENT
OUT
PC1
TRACE
D0
-
SAI1_D1
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SPI2_
MOSI/I2S2
_SDO
SAI1_SD_A
-
SAI4_SD_
A
SDMMC2_
CK
SAI4_D1
ETH_MDC
MDIOS_
MDC
-
-
EVENT
OUT
PC2
C1DSLE
EP
-
-
DFSDM1_
CKIN1
-
SPI2_
MISO/I2S2
_SDI
DFSDM1_
CKOUT
-
-
-
OTG_HS_
ULPI_DIR
ETH_MII_TX
D2
FMC_SDNE
0
-
-
EVENT
OUT
PC3
C1
SLEEP
-
-
DFSDM1_
DATIN1
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
OTG_HS_
ULPI_NXT
ETH_MII_TX
_CLK
FMC_SDCK
E0
-
-
EVENT
OUT
PC4
C2
DSLEE
P
-
-
DFSDM1_
CKIN2
-
I2S1_MCK
-
-
-
SPDIFRX1_
IN3
-
ETH_MII_RX
D0/ETH_
RMII_RXD0
FMC_SDNE
0
-
-
EVENT
OUT
PC5
C2
SLEEP
-
SAI1_D3
DFSDM1_
DATIN2
-
-
-
-
-
SPDIFRX1_
IN4
SAI4_D3
ETH_MII_RX
D1/ETH_
RMII_RXD1
FMC_SDCK
E0
COMP1_
OUT
-
EVENT
OUT
PC6
-
HRTIM_CH
A1
TIM3_CH1
TIM8_CH1
DFSDM1_
CKIN3
I2S2_MCK
-
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1_
D6
DCMI_D0
LCD_
HSYNC
EVENT
OUT
PC7
TRGIO
HRTIM_CH
A2
TIM3_CH2
TIM8_CH2
DFSDM1_
DATIN3
-
I2S3_MCK
USART6_
RX
SDMMC1_
D123DIR
FMC_NE1
SDMMC2_
D7
SWPMI_TX
SDMMC1_
D7
DCMI_D1
LCD_G6
EVENT
OUT
PC8
TRACE
D1
HRTIM_CH
B1
TIM3_CH3
TIM8_CH3
-
-
-
USART6_
CK
UART5_
RTS/UART
5_DE
FMC_NE2/
FMC_NCE
-
SWPMI_RX
SDMMC1_
D0
DCMI_D2
-
EVENT
OUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
UART5_
CTS
QUADSPI_
BK1_IO0
LCD_G3
SWPMI_
SUSPEND
SDMMC1_
D1
DCMI_D3
LCD_B2
EVENT
OUT
PC10
-
-
HRTIM_EE
V1
DFSDM1_
CKIN5
-
-
SPI3_SCK/I
2S3_CK
USART3_
TX
UART4_TX
QUADSPI_
BK1_IO1
-
-
SDMMC1_
D2
DCMI_D8
LCD_R2
EVENT
OUT
PC11
-
-
HRTIM_
FLT2
DFSDM1_
DATIN5
-
-
SPI3_MISO/
I2S3_SDI
USART3_
RX
UART4_RX
QUADSPI_
BK2_NCS
-
-
SDMMC1_
D3
DCMI_D4
-
EVENT
OUT
PC12
TRACE
D3
-
HRTIM_EE
V2
-
-
-
SPI3_MOSI/
I2S3_SDO
USART3_
CK
UART5_TX
-
-
-
SDMMC1_
CK
DCMI_D9
-
EVENT
OUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Port C
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
92/252
Table 11. Port C alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Port
Port C
AF1
STM32H745xI/G
Table 11. Port C alternate functions (continued)
DS12923 Rev 1
Pin descriptions
93/252
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PD0
-
-
-
DFSDM1_
CKIN6
-
-
SAI3_SCK_
A
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D2/
FMC_DA2
-
-
EVENT
OUT
PD1
-
-
-
DFSDM1_
DATIN6
-
-
SAI3_SD_A
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D3/
FMC_DA3
-
-
EVENT
OUT
PD2
TRACE
D2
-
TIM3_ETR
-
-
-
-
-
UART5_RX
-
-
-
SDMMC1_
CMD
DCMI_D11
-
EVENT
OUT
PD3
-
-
-
DFSDM1_
CKOUT
-
SPI2_SCK/
I2S2_CK
-
USART2_
CTS/
USART2_
NSS
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENT
OUT
PD4
-
-
HRTIM_
FLT3
-
-
-
SAI3_FS_A
USART2_
RTS/USART2
_DE
-
FDCAN1_
RXFD_
MODE
-
-
FMC_NOE
-
-
EVENT
OUT
PD5
-
-
HRTIM_EE
V3
-
-
-
-
USART2_
TX
-
FDCAN1_
TXFD_
MODE
-
-
FMC_NWE
-
-
EVENT
OUT
PD6
-
-
SAI1_D1
DFSDM1_
CKIN4
DFSDM1_
DATIN1
SPI3_
MOSI/I2S3
_SDO
SAI1_SD_A
USART2_
RX
SAI4_SD_
A
FDCAN2_
RXFD_
MODE
SAI4_D1
SDMMC2_
CK
FMC_
NWAIT
DCMI_D10
LCD_B2
EVENT
OUT
PD7
-
-
-
DFSDM1_
DATIN4
-
SPI1_
MOSI/I2S1
_SDO
DFSDM1_
CKIN1
USART2_
CK
-
SPDIFRX1_
IN1
-
SDMMC2_
CMD
FMC_NE1
-
-
EVENT
OUT
PD8
-
-
-
DFSDM1_
CKIN3
-
-
SAI3_SCK_
B
USART3_
TX
-
SPDIFRX1_
IN2
-
-
FMC_D13/
FMC_DA13
-
-
EVENT
OUT
PD9
-
-
-
DFSDM1_
DATIN3
-
-
SAI3_SD_B
USART3_
RX
-
FDCAN2_
RXFD_
MODE
-
-
FMC_D14/
FMC_DA14
-
-
EVENT
OUT
PD10
-
-
-
DFSDM1_
CKOUT
-
-
SAI3_FS_B
USART3_
CK
-
FDCAN2_
TXFD_
MODE
-
-
FMC_D15/
FMC_DA15
-
LCD_B3
EVENT
OUT
PD11
-
-
-
LPTIM2_
IN2
I2C4_SMBA
-
-
USART3_
CTS/
USART3_
NSS
-
QUADSPI_
BK1_IO0
SAI2_SD_A
-
FMC_A16
-
-
EVENT
OUT
PD12
-
LPTIM1_IN1
TIM4_CH1
LPTIM2_IN
1
I2C4_SCL
-
-
USART3_
RTS/
USART3_
DE
-
QUADSPI_
BK1_IO1
SAI2_FS_A
-
FMC_A17
-
-
EVENT
OUT
Port D
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
94/252
Table 12. Port D alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PD13
-
LPTIM1_
OUT
TIM4_CH2
-
I2C4_SDA
-
-
-
-
QUADSPI_
BK1_IO3
SAI2_SCK_
A
-
FMC_A18
-
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
SAI3_MCLK
_B
-
UART8_
CTS
-
-
-
FMC_D0/
FMC_DA0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
SAI3_MCLK
_A
-
UART8_
RTS/
UART8_DE
-
-
-
FMC_D1/
FMC_DA1
-
-
EVENT
OUT
Port
Prot D
AF1
STM32H745xI/G
Table 12. Port D alternate functions (continued)
DS12923 Rev 1
Pin descriptions
95/252
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PE0
-
LPTIM1_
ETR
TIM4_ETR
HRTIM_
SCIN
LPTIM2_
ETR
-
-
-
UART8_RX
FDCAN1_
RXFD_
MODE
SAI2_
MCLK_A
-
FMC_NBL0
DCMI_D2
-
EVENT
OUT
PE1
-
LPTIM1_IN2
-
HRTIM_
SCOUT
-
-
-
-
UART8_TX
FDCAN1_
TXFD_
MODE
-
-
FMC_NBL1
DCMI_D3
-
EVENT
OUT
PE2
TRACE
CLK
-
SAI1_CK1
-
-
SPI4_SCK
SAI1_MCLK
_A
-
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
SAI4_CK1
ETH_MII_TX
D3
FMC_A23
-
-
EVENT
OUT
PE3
TRACE
D0
-
-
-
TIM15_BKIN
-
SAI1_SD_B
-
SAI4_SD_
B
-
-
-
FMC_A19
-
-
EVENT
OUT
PE4
TRACE
D1
-
SAI1_D2
DFSDM1_
DATIN3
TIM15_CH1
N
SPI4_NSS
SAI1_FS_A
-
SAI4_FS_A
-
SAI4_D2
-
FMC_A20
DCMI_D4
LCD_B0
EVENT
OUT
PE5
TRACE
D2
-
SAI1_CK2
DFSDM1_
CKIN3
TIM15_CH1
SPI4_
MISO
SAI1_SCK_
A
-
SAI4_SCK
_A
-
SAI4_CK2
-
FMC_A21
DCMI_D6
LCD_G0
EVENT
OUT
PE6
TRACE
D3
TIM1_BKIN
2
SAI1_D1
-
TIM15_CH2
SPI4_
MOSI
SAI1_SD_A
-
SAI4_SD_
A
SAI4_D1
SAI2_
MCLK_B
TIM1_BKIN2
_COMP12
FMC_A22
DCMI_D7
LCD_G1
EVENT
OUT
PE7
-
TIM1_ETR
-
DFSDM1_
DATIN2
-
-
-
UART7_RX
-
-
QUADSPI_
BK2_IO0
-
FMC_D4/
FMC_DA4
-
-
EVENT
OUT
PE8
-
TIM1_CH1N
-
DFSDM1_
CKIN2
-
-
-
UART7_TX
-
-
QUADSPI_
BK2_IO1
-
FMC_D5/
FMC_DA5
COMP2_
OUT
-
EVENT
OUT
PE9
-
TIM1_CH1
-
DFSDM1_
CKOUT
-
-
-
UART7_
RTS/
UART7_DE
-
-
QUADSPI_
BK2_IO2
-
FMC_D6/
FMC_DA6
-
-
EVENT
OUT
PE10
-
TIM1_CH2N
-
DFSDM1_
DATIN4
-
-
-
UART7_
CTS
-
-
QUADSPI_
BK2_IO3
-
FMC_D7/
FMC_DA7
-
-
EVENT
OUT
PE11
-
TIM1_CH2
-
DFSDM1_
CKIN4
-
SPI4_NSS
-
-
-
-
SAI2_SD_B
-
FMC_D8/
FMC_DA8
-
LCD_G3
EVENT
OUT
PE12
-
TIM1_CH3N
-
DFSDM1_
DATIN5
-
SPI4_SCK
-
-
-
-
SAI2_SCK_
B
-
FMC_D9/
FMC_DA9
COMP1_
OUT
LCD_B4
EVENT
OUT
PE13
-
TIM1_CH3
-
DFSDM1_
CKIN5
-
SPI4_
MISO
-
-
-
-
SAI2_FS_B
-
FMC_D10/
FMC_DA10
COMP2_
OUT
LCD_DE
EVENT
OUT
Port E
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
96/252
Table 13. Port E alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PE14
-
TIM1_CH4
-
-
-
SPI4_
MOSI
-
-
-
-
SAI2_MCL
K_B
-
FMC_D11/
FMC_DA11
-
LCD_CL
K
EVENT
OUT
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
FMC_D12/
FMC_DA12
TIM1_BKIN
_COMP12/
COMP_
TIM1_BKIN
LCD_R7
EVENT
OUT
Port
Prot E
AF1
STM32H745xI/G
Table 13. Port E alternate functions (continued)
DS12923 Rev 1
Pin descriptions
97/252
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENT
OUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENT
OUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
TIM16_CH1
-
-
-
SPI5_NSS
SAI1_SD_B
UART7_RX
SAI4_SD_
B
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENT
OUT
PF7
-
TIM17_CH1
-
-
-
SPI5_SCK
SAI1_MCLK
_B
UART7_TX
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENT
OUT
PF8
-
TIM16_CH1
N
-
-
-
SPI5_
MISO
SAI1_SCK_
B
UART7_
RTS/
UART7_DE
SAI4_SCK
_B
TIM13_CH1
QUADSPI_
BK1_IO0
-
-
-
-
EVENT
OUT
PF9
-
TIM17_CH1
N
-
-
-
SPI5_
MOSI
SAI1_FS_B
UART7_
CTS
SAI4_FS_B
TIM14_CH1
QUADSPI_
BK1_IO1
-
-
-
-
EVENT
OUT
PF10
-
TIM16_BKI
N
SAI1_D3
-
-
-
-
-
-
QUADSPI_
CLK
SAI4_D3
-
-
DCMI_D11
LCD_DE
EVENT
OUT
PF11
-
-
-
-
-
SPI5_
MOSI
-
-
-
-
SAI2_SD_B
-
FMC_
SDNRAS
DCMI_D12
-
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
PF13
-
-
-
DFSDM1_
DATIN6
I2C4_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
PF14
-
-
-
DFSDM1_
CKIN6
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
PF15
-
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
Port F
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
98/252
Table 14. Port F alternate functions
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PG0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
TIM8_BKIN
-
-
-
-
-
-
-
TIM8_BKIN_
COMP12
FMC_A12
-
-
EVENT
OUT
PG3
-
-
-
TIM8_BKIN
2
-
-
-
-
-
-
-
TIM8_BKIN2
_COMP12
FMC_A13
-
-
EVENT
OUT
PG4
-
TIM1_BKIN
2
-
-
-
-
-
-
-
-
-
TIM1_BKIN2
_COMP12
FMC_A14/
FMC_BA0
-
-
EVENT
OUT
PG5
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
FMC_A15/
FMC_BA1
-
-
EVENT
OUT
PG6
-
TIM17_
BKIN
HRTIM_
CHE1
-
-
-
-
-
-
-
QUADSPI_
BK1_NCS
-
FMC_NE3
DCMI_D12
LCD_R7
EVENT
OUT
PG7
-
-
HRTIM_
CHE2
-
-
-
SAI1_MCLK
_A
USART6_
CK
-
-
-
-
FMC_INT
DCMI_D13
LCD_CL
K
EVENT
OUT
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
USART6_
RTS/
USART6_
DE
-
-
ETH_PPS_
OUT
FMC_
SDCLK
-
LCD_G7
EVENT
OUT
PG9
-
-
-
-
-
SPI1_
MISO/I2S1
_SDI
-
USART6_
RX
SPDIFRX1
_
IN4
QUADSPI_
BK2_IO2
SAI2_FS_B
-
FMC_NE2/
FMC_NCE
DCMI_
VSYNC
-
EVENT
OUT
PG10
-
-
HRTIM_
FLT5
-
-
SPI1_NSS/
I2S1_WS
-
-
-
LCD_G3
SAI2_SD_B
-
FMC_NE3
DCMI_D2
LCD_B2
EVENT
OUT
PG11
-
LPTIM1_IN2
HRTIM_
EEV4
-
-
SPI1_SCK/
I2S1_CK
-
-
-
SDMMC2_
D2
ETH_MII_
TX_EN/ETH
_RMII_TX_
EN
-
DCMI_D3
LCD_B3
EVENT
OUT
PG12
-
LPTIM1_IN1
HRTIM_
EEV5
-
-
SPI6_
MISO
-
USART6_
RTS/
USART6_
DE
LCD_B4
-
ETH_MII_TX
D1/ETH_
RMII_TXD1
FMC_NE4
-
LCD_B1
EVENT
OUT
Port G
DS12923 Rev 1
SPDIFRX1
_
IN3
SPDIFRX1
_
IN1
SPDIFRX1
_IN2
99/252
Pin descriptions
AF5
Port
AF1
STM32H745xI/G
Table 15. Port G alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PG13
TRACE
D0
LPTIM1_
OUT
HRTIM_
EEV10
-
-
SPI6_SCK
-
USART6_
CTS/
USART6_
NSS
-
-
-
ETH_MII_TX
D0/ETH_
RMII_TXD0
FMC_A24
-
LCD_R0
EVENT
OUT
PG14
TRACE
D1
LPTIM1_
ETR
-
-
-
SPI6_
MOSI
-
USART6_
TX
-
QUADSPI_
BK2_IO3
-
ETH_MII_TX
D1/ETH_
RMII_TXD1
FMC_A25
-
LCD_B0
EVENT
OUT
PG15
-
-
-
-
-
-
-
USART6_
CTS/
USART6_
NSS
-
-
-
-
FMC_
SDNCAS
DCMI_D13
-
EVENT
OUT
Port
Prot G
AF1
Pin descriptions
100/252
Table 15. Port G alternate functions (continued)
DS12923 Rev 1
STM32H745xI/G
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH2
-
LPTIM1_IN2
-
-
-
-
-
-
-
QUADSPI_
BK2_IO0
SAI2_SCK_
B
ETH_MII_
CRS
FMC_
SDCKE0
-
LCD_R0
EVENT
OUT
PH3
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_SDNE
0
-
LCD_R1
EVENT
OUT
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
OTG_HS_U
LPI_NXT
-
-
-
LCD_G4
EVENT
OUT
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
-
-
-
-
-
FMC_SDN
WE
-
-
EVENT
OUT
PH6
-
-
TIM12_CH
1
-
I2C2_SMBA
SPI5_SCK
-
-
-
-
-
ETH_MII_RX
D2
FMC_SDNE
1
DCMI_D8
-
EVENT
OUT
PH7
-
-
-
-
I2C3_SCL
SPI5_
MISO
-
-
-
-
-
ETH_MII_RX
D3
FMC_
SDCKE1
DCMI_D9
-
EVENT
OUT
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_HSY
NC
LCD_R2
EVENT
OUT
PH9
-
-
TIM12_CH
2
-
I2C3_SMBA
-
-
-
-
-
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENT
OUT
PH10
-
-
TIM5_CH1
-
I2C4_SMBA
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENT
OUT
PH11
-
-
TIM5_CH2
-
I2C4_SCL
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENT
OUT
PH12
-
-
TIM5_CH3
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENT
OUT
PH13
-
-
-
TIM8_CH1
N
-
-
-
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D21
-
LCD_G2
EVENT
OUT
PH14
-
-
-
TIM8_CH2
N
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENT
OUT
PH15
-
-
-
TIM8_CH3
N
-
-
-
-
-
FDCAN1_
TXFD_
MODE
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENT
OUT
Port H
DS12923 Rev 1
101/252
Pin descriptions
AF5
Port
AF1
STM32H745xI/G
Table 16. Port H alternate functions
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/
I2S2_WS
-
-
-
FDCAN1_
RXFD_MODE
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENT
OUT
PI1
-
-
-
TIM8_BKIN
2
-
SPI2_SCK/
I2S2_CK
-
-
-
-
-
TIM8_BKIN2
_COMP12
FMC_D25
DCMI_D8
LCD_G6
EVENT
OUT
PI2
-
-
-
TIM8_CH4
-
SPI2_MIS
O/I2S2_SD
I
-
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENT
OUT
PI3
-
-
-
TIM8_ETR
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
-
-
FMC_D27
DCMI_D10
-
EVENT
OUT
PI4
-
-
-
TIM8_BKIN
-
-
-
-
-
-
SAI2_
MCLK_A
TIM8_BKIN_
COMP12
FMC_NBL2
DCMI_D5
LCD_B4
EVENT
OUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
SAI2_SCK_
A
-
FMC_NBL3
DCMI_
VSYNC
LCD_B5
EVENT
OUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
SAI2_SD_A
-
FMC_D28
DCMI_D6
LCD_B6
EVENT
OUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
SAI2_FS_A
-
FMC_D29
DCMI_D7
LCD_B7
EVENT
OUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PI9
-
-
-
-
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D30
-
LCD_VS
YNC
EVENT
OUT
PI10
-
-
-
-
-
-
-
-
-
FDCAN1_
RXFD_MODE
-
ETH_MII_RX
_ER
FMC_D31
-
LCD_HS
YNC
EVENT
OUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS_
ULPI_DIR
-
-
-
-
EVENT
OUT
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_HS
YNC
EVENT
OUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VS
YNC
EVENT
OUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CL
K
EVENT
OUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVENT
OUT
Port I
DS12923 Rev 1
STM32H745xI/G
AF5
Port
AF1
Pin descriptions
102/252
Table 17. Port I alternate functions
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVENT
OUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVENT
OUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R3
EVENT
OUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVENT
OUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVENT
OUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENT
OUT
PJ6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVENT
OUT
PJ7
TRGIN
-
-
TIM8_CH2
N
-
-
-
-
-
-
-
-
-
-
LCD_G0
EVENT
OUT
PJ8
-
TIM1_CH3N
-
TIM8_CH1
-
-
-
-
UART8_TX
-
-
-
-
-
LCD_G1
EVENT
OUT
PJ9
-
TIM1_CH3
-
TIM8_CH1
N
-
-
-
-
UART8_RX
-
-
-
-
-
LCD_G2
EVENT
OUT
PJ10
-
TIM1_CH2N
-
TIM8_CH2
-
SPI5_
MOSI
-
-
-
-
-
-
-
-
LCD_G3
EVENT
OUT
PJ11
-
TIM1_CH2
-
TIM8_CH2
N
-
SPI5_µ
MISO
-
-
-
-
-
-
-
-
LCD_G4
EVENT
OUT
PJ12
TRGOU
T
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENT
OUT
PJ13
-
-
-
-
-
-
-
-
-
LCD_B4
-
-
-
-
LCD_B1
EVENT
OUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENT
OUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENT
OUT
Port J
DS12923 Rev 1
103/252
Pin descriptions
AF5
Port
AF1
STM32H745xI/G
Table 18. Port J alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PK0
-
TIM1_CH1N
-
TIM8_CH3
-
SPI5_SCK
-
-
-
-
-
-
-
-
LCD_G5
EVENT
OUT
PK1
-
TIM1_CH1
-
TIM8_CH3
N
-
SPI5_NSS
-
-
-
-
-
-
-
-
LCD_G6
EVENT
OUT
PK2
-
TIM1_BKIN
-
TIM8_BKIN
-
-
-
-
-
-
TIM8_BKIN
_COMP12
TIM1_BKIN_
COMP12
-
-
LCD_G7
EVENT
OUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENT
OUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENT
OUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENT
OUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENT
OUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENT
OUT
Port K
Port
AF1
Pin descriptions
104/252
Table 19. Port K alternate functions
DS12923 Rev 1
STM32H745xI/G
STM32H745xI/G
6
6.1
Electrical characteristics
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
DS12923 Rev 1
MS19010V2
105/252
228
Electrical characteristics
6.1.6
STM32H745xI/G
Power supply scheme
VDD33USB
Step
Down
Coverter
(SMPS)
VLXSMPS
VFBSMPS
VSSSMPS
USB
regulator
VDDLDO
VCAP
Core domain (VCORE)
Level shifter
IOs
N(1) x 100 nF
+ 1 x 4.7 μF
VDD
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
Power
switch
Power
switch
VSS
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
VDD domain
VBAT
charging
HSI, CSI,
HSI48,
HSE, PLLs
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
logic, backup
IO
registers,
logic
Reset
BKUP
IOs
VREF
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
VDDA
VDDA
Flash
VSS
VDD
VBAT
1.2 to 3.6V
VSS
Voltage
regulator
VDDLDO
4..7μF
2 x 2.2μF
VDD50USB
USB
IOs
VSS
VDDSMPS
VDD50USB
100 nF
VDD33USB
100 nF
Figure 13. Power supply scheme
VSS
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
Backup
RAM
VSS
OPAMP,
Comparator
VSSA
MSv62410V1
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
106/252
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
DS12923 Rev 1
STM32H745xI/G
Electrical characteristics
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics, and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 20. Voltage characteristics (1)
Symbols
VDDX - VSS
VIN(2)
Ratings
Min
Max
Unit
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS-0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
-
50
mV
-
50
mV
External main supply voltage (including VDD,
VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT)
Input voltage on any other pins
|∆VDDX|
Variations between different VDDX power pins
of the same domain
|VSSx-VSS| Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 68: I/O current injection susceptibility for the
maximum allowed injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
DS12923 Rev 1
107/252
228
Electrical characteristics
STM32H745xI/G
Table 21. Current characteristics
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
620
ΣIVSS
(1)
620
Total current out of sum of all VSS ground lines (sink)
IVDD
(1)
Maximum current into each VDD power pin (source)
100
IVSS
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk by any I/O and control pin
IIO
20
(2)
ΣI(PIN)
Total output current sunk by sum of all I/Os and control pins
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
IINJ(PIN)(3)(4) PA5
Injected current on PA4, PA5
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control
Unit
mA
−5/+0
−0/0
pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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