STM32H7B0xB
Datasheet
32-bit Arm® Cortex®-M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte
RAM, 46 com. and analog interfaces, SMPS, crypto
Features
FBGA
Includes ST state-of-the-art patented technology
Core
LQFP64
(10 x 10 mm)
LQFP100
(14 x 14 mm)
LQFP144
(20x20 mm)
LQFP176
(24 x 24 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10x10 mm)
Product summary
STM32H7B0xB
STM32H7B0AB,
STM32H7B0IB,
STM32H7B0RB,
STM32H7B0ZB,
STM32H7B0VB
32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache:
16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache
line in a single access from the 128-bit embedded flash memory; frequency up
to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
•
128 Kbytes of flash memory plus 1 Kbyte of OTP memory
•
~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM +
128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM,
and 4 Kbytes of SRAM in Backup domain
•
2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and
support for serial PSRAM/NOR, Hyper RAM/flash frame formats, running up to
140 MHz in SRD mode and up to 110 MHz in DTR mode
•
Flexible external memory controller with up to 32-bit data bus:
–
SRAM, PSRAM, NOR flash memory clocked up to 125 MHz in
Synchronous mode
–
SDRAM/LPSDR SDRAM
–
8/16-bit NAND flash memories
•
CRC calculation unit
Security
•
ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access
mode
General-purpose input/outputs
•
Up to 138 I/O ports with interrupt capability
–
Fast I/Os capable of up to 133 MHz
–
Up to 164 5-V-tolerant I/Os
Low-power consumption
•
Stop: down to 32 µA with full RAM retention
•
Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)
•
VBAT: 0.8 µA (RTC and LSE ON)
•
Clock management
•
Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
•
External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
•
3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
DS13196 - Rev 7 - May 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
STM32H7B0xB
Reset and power management
•
2 separate power domains, which can be independently clock gated to maximize power efficiency:
•
•
•
•
•
CPU domain (CD) for Arm® Cortex® core and its peripherals, which can be independently switched in
Retention mode
–
Smart run domain (SRD) for reset and clock control, power management and some peripherals
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Dedicated SDMMC power supply
High power efficiency SMPS step-down converter regulator to directly supply VCORE or an external circuitry
•
•
•
•
•
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode
Backup regulator (~0.9 V)
Low-power modes: Sleep, Stop and Standby
VBAT battery operating mode with charging capability
–
•
CPU and domain power state monitoring pins
Interconnect matrix
•
3 bus matrices (1 AXI and 2 AHB)
•
Bridges (5× AHB2APB, 3× AXI2AHB)
5 DMA controllers to unload the CPU
•
1× high-speed general-purpose master direct memory access controller (MDMA)
•
2× dual-port DMAs with FIFO and request router capabilities
•
1× basic DMA with request router capabilities
•
1x basic DMA dedicated to DFSDM
Up to 35 communication peripherals
•
4× I2C FM+ interfaces (SMBus/PMBus)
•
5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART
•
6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock
and 1 x SPI/I2S in LP domain (up to 125 MHz)
•
2x SAIs (serial audio interface)
•
SPDIFRX interface
•
SWPMI single-wire protocol master interface
•
MDIO Slave interface
•
2× SD/SDIO/MMC interfaces (up to 133 MHz)
•
2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
•
1× USB OTG interfaces (1HS/FS)
•
HDMI-CEC
•
8- to 14-bit camera interface up to 80 MHz
•
8-/16-bit parallel synchronous data input/output slave interface (PSSI)
11 analog peripherals
•
2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS)
•
1× analog and 1x digital temperature sensors
•
1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC
•
2× ultra-low-power comparators
•
2× operational amplifiers (8 MHz bandwidth)
•
2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2
channels/1 filter
DS13196 - Rev 7
page 2/205
STM32H7B0xB
Graphics
•
LCD-TFT controller up to XGA resolution
•
Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
•
Hardware JPEG Codec
•
Chrom-GRC™ (GFXMMU)
Up to 19 timers and 2 watchdogs
•
2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to
280 MHz)
•
2× 16-bit advanced motor control timers (up to 280 MHz)
•
10× 16-bit general-purpose timers (up to 280 MHz)
•
3× 16-bit low-power timers (up to 280 MHz)
•
2× watchdogs (independent and window)
•
1× SysTick timer
•
RTC with sub-second accuracy and hardware calendar
Cryptographic acceleration
•
AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256
•
HASH (MD5, SHA-1, SHA-2), HMAC
•
2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption
•
1x 32-bit, NIST SP 800-90B compliant, true random generator
Debug mode
•
SWD and JTAG interfaces
•
4 KB Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK2 compliant
DS13196 - Rev 7
page 3/205
STM32H7B0xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32H7B0xB
microcontrollers.
This document should be read in conjunction with the STM32H7B0xB reference manual (RM0455). The reference
manual is available from the STMicroelectronics website .
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32H7B0xB errata sheet (ES0478), available on the STMicroelectronics website .
For information on the Arm® Cortex®-M7 core, refer to the Cortex®-M7 Technical Reference Manual, available
from the www.arm.com website
Note:
DS13196 - Rev 7
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
page 4/205
STM32H7B0xB
Description
2
Description
STM32H7B0xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up
to 280 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision
(IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H7B0xB devices
support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H7B0xB devices incorporate high-speed embedded memories with a flash memory of 128 Kbytes, around
1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of backup
SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses, three AHB
buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory
access.
All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a
low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers,
a true random number generator (RNG), and a cryptographic acceleration cell and a HASH processor. The
devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and
advanced communication interfaces.
•
Standard peripherals
–
–
Four I2Cs
Five USARTs, five UARTs and one LPUART
Six SPIs, four I2Ss in full-duplex mode. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
–
Two SAI serial audio interfaces, out of which one with PDM
–
One SPDIFRX interface
–
One single wire protocol master interface (SWPMI)
–
One 16-bit parallel synchronous slave interface (PSSI) sharing the same interface as the digital
camera)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces (one can be supplied from a supply voltage separate from that of all other I/Os)
–
A USB OTG high-speed with full-speed capability (with the ULPI)
–
One FDCAN plus one TT-CAN interface
–
Chrom-ART Accelerator
–
HDMI-CEC
Advanced peripherals including
–
•
–
–
–
–
–
–
A flexible memory control (FMC) interface
Two octo-SPI memory interface with on-the-fly decryption (OTFDEC)
A digital camera interface for CMOS sensors (DCMI)
A graphic memory management unit (GFXMMU)
An LCD-TFT display controller (LTDC)
A JPEG hardware compressor/decompressor
Refer to Table 1. STM32H7B0xB features and peripheral counts for the list of peripherals available on each part
number.
STM32H7B0xB devices operate in the –40 to +85 °C ambient temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see
Section 3.5.2 Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage
must stay above 1.71 V with the embedded power voltage detector enabled.
The USB OTG_HS/FS interfaces can be supplied either by the integrated USB regulator or through a separate
supply input.
A dedicated supply input is available for one of the SDMMC interface for package with more than 100 pins. It
allows running from a different voltage level than all other I/Os.
A comprehensive set of power-saving mode allows the design of low-power applications.
The CPU and domain states can be directly monitored on some GPIOs configured as alternate functions.
STM32H7B0xB devices are offers in several packages ranging from 64 pins to 225 pins/balls. The set of included
peripherals changes with the device chosen.
DS13196 - Rev 7
page 5/205
STM32H7B0xB
Description
These features make the STM32H7B0xB microcontrollers suitable for a wide range of applications:
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1. STM32H7B0xB block diagram shows the general block diagram of the device family.
DS13196 - Rev 7
page 6/205
DS13196 - Rev 7
Table 1. STM32H7B0xB features and peripheral counts
Flash memory (Kbytes)
SRAM in Kbytes
TCM RAM in Kbytes
1024
SRAM on AHB (CD domain)
128
SRAM on AHB (SRD domain)
32
ITCM RAM (instruction)
64
DTCM RAM (data)
128
1
NOR Flash memory/RAM
controller
x (2)
Multiplexed I/O NOR Flash
memory
x
x
x(2)
-
16-bit NAND Flash memory
x
x
x(2)
-
SDRAM controller
x(2)
x
x(2)
2(4)
2
2(4)
Octo-SPI interfaces(3)
x(2)
x
General-purpose
10
Advanced-control (PWM)
2
Basic
2
Low-power
3
Window watchdog / independent watchdog
1 Octo-SPI
1 Quad-SPI
1
2
3
2
Active
1
2
1
page 7/205
1
Cryptographic accelerator
1
Hash processor (HASH)
1
for external Octo-SPI memory
2
2
2
2(2)
STM32H7B0xB
Passive
Random number generator
On-the-fly decryption
-
1/1
Real-time Clock (RTC)
Tamper pins (5)
STM32H7B0RBT
4
Interface
Timers
STM32H7B0VBT
128
SRAM on AXI
Backup SRAM (Kbytes)
FMC
STM32H7B0ZBT
STM32H7B0IBT
Peripherals
no-SMPS
STM32H7B0ABI
STM32H7B0IBK
SMPS (1)
DS13196 - Rev 7
Communi-cation interfaces
STM32H7B0RBT
4/4
4(2)/3(2)
3
USART/UART
5/5
5/5
5(2)/5
/LPUART
/1
/1
/1
/1
SAI/PDM
2/1
2/1
2(2)/1
1(2)/-
SPDIFRX
4 inputs
4 inputs
SWPMI
1
MDIOS
1
2
USB OTG_HS ULPI, OTG_FS
PHY
1/1(2)
1/1
1
1
Digital camera interface/PSSI (10)
1 (8)
1
1/1
1
JPEG Codec
1
Chrom-ART Accelerator (DMA2D)
1
Graphic memory management unit (GFXMMU)
1
HDMI CEC
1
DFSDM
2
Number of filters for DFSDM1/DFSDM2
8/1
8/1
8 to 16 bits
24
20(11)
24
16(11)
2
3 (1 single channel + 1 dual-channel interfaces)
Comparators
2
Operational amplifier
2
2
page 8/205
128
2
121
4
1
138
6
112
1
80
4
49
STM32H7B0xB
12 bits
Wakeup pins
7/1
2
Number of channels
GPIOs
1 (9)
1/1
LCD-TFT display controller
Number of channels
2(7)
2
FDCAN/TT-CAN
DACs
5/4
4
SDMMC
ADCs
6/4
STM32H7B0ZBT
6/4
I2C
STM32H7B0VBT
SPI/I2S (6)
STM32H7B0IBT
Peripherals
no-SMPS
STM32H7B0ABI
STM32H7B0IBK
SMPS (1)
Maximum CPU frequency (MHz)
STM32H7B0RBT
STM32H7B0VBT
STM32H7B0ZBT
STM32H7B0IBT
STM32H7B0ABI
Peripherals
no-SMPS
STM32H7B0IBK
DS13196 - Rev 7
SMPS (1)
280
SMPS step-down converter
1
USB internal regulator
1
-
USB separate supply pad
1
-
VDDMMC separate supply pad
1
-
VREF+ separate pad and internal buffer
1
1
Operating voltage
1.62 to 3.6 V
1
-
LQFP100
LQFP64
(12)
Ambient temperature range: −40 to 85 °C
Operating temperatures
Junction temperature range: −40 to 130 °C(13)
Packages
UFBGA176+25
UFBGA169
LQFP176
Bootloader
USART, I2C, SPI, USBDFU, FDCAN
USART, I2C, SPI,
USB-DFU, FDCAN
USART, I2C, SPI,
USB-DFU, FDCAN
LQFP144
USART, I2C, SPI, USB-DFU
1. The devices with SMPS correspond to commercial code STM32H7B0xIxxQ.
2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7. STM32H7B0xB pin/ball definition.
3. To maximize the performance, the I/O high-speed at low-voltage feature (HSLV) must be activated when VDD < 2.7 V. This feature is not available on all I/Os (see
Table 88. OCTOSPI characteristics in SDR mode, and Table 89. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus).
4. The I/O high-speed at low-voltage feature (HSLV) at VDD < 2.7 V is not available for OCTOSPIM_P2.
5. A tamper pin can be configured either as passive or active (not both).
6. SPI1, SPI2, SPI3 and SPI6 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode.
7. Dedicated I/O supply pad (VDDMMC) or external level shifter are not supported.
8. The ULPI interface is supported. PC2 and PC3 are available on PC2_C and PC3_C, respectively, by closing the internal analog switch (see Table 7. STM32H7B0xB pin/ball
definition).
9. The ULPI interface is not supported.
10. DCMI and PSSI cannot be used simultaneously since they share the same circuitry.
11. For limitations on fast pads or channels depending on packages, check to the available pins/balls in Table 7. STM32H7B0xB pin/ball definition.
13. The junction temperature is limited to 105 °C in VOS0 voltage range.
page 9/205
STM32H7B0xB
12. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2 Power supply supervisor) and connecting PDR_ON pin to VSS. Otherwise the supply
voltage must stay above 1.71 V with the embedded power voltage detector enabled.
STM32H7B0xB
Figure 1. STM32H7B0xB block diagram
SDMMC_
D[7:0],
CMD, CK as AF
DP, DM, ID,
VBUS
To APB1-2
peripherals
AHB1
DMA1
AXI/AHB12 (280 MHz)
D-Cache
16KB
AHBS
AXI/AHB34 (280 MHz)
DCMI
PSSI
32b
16b
AHB3 (280 MHz)
16b
smcard
irDA USART10
TIM15
16b
16b
TIM7
16b
32-bit AHB BUS-MATRIX
16b
16b
32 KB
SRD_SRAM
RX, TX as AF
I2C3/SMBUS
FDCAN2
Tamper monitor
AHB/
APB
DAC1_OUT1 as AF
DAC1_OUT2 as AF
SYSCFG
LPUART1
EXTI WKUP
@VDD
CSI
CSI RC 4MHz
HSI48
LSI
LSE XTAL 32 kHz
RTC
Backup registers
AWU
HSE XTAL OSC
4 - 48MHz
HSI RC 64MHz
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
VDD
VDDMMC
VSS
VCAP, VDDLDO
VDDSMPS, VSSSMPS
VLXSMPS, VFBSMPS
VDD50USB
VDD33USB
VBAT
OSC32_IN
OSC32_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
OSC_IN
OSC_OUT
WDG_LS_D1
HSI48 RC 48MHz
LSI RC 32kHz
VDD
LPTIM1_IN1, LPTIM1_IN2,
LPTIM2_OUT as AF
@VDD
PLL1+PLL2+PLL3
VREF
16b
Temp USB regulator
Monitor Vbat charging
LS
I2C4
Vref internal
HDMI_CEC as AF
DAC
DAC
BBgen + POWER MNGT
@VSW
TX, RX
SYNC
Voltage
SMPS
regulator Step-down
3.3 to 1.2V converter
APB4
APB4 140 MHz (max)
16b
TX, RX
SPDIFRX[3:0] as AF
OPAMP1&2
DAC2
SPI6/I2S6
MDC, MDIO
@VDD33
VDD12
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
HDMI-CEC
DAC1
AHB4
RCC
Reset &
Clock
Control
Digital Temp Sensor
RX, TX, CK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SPIF-RX1
4 KB
BKP_SRAM
COMP1&2
16b
MOSI, MISO, SCK, SS /
SDO, SDI, CK, WS, MCK, as AF
MOSI, MISO, SCK, SS /
SDO, SDI, CK, WS, MCK, as AF
MDIOS
LPTIM1
HSI
DS13196 - Rev 7
RX, TX as AF
UART8
CRS
IWDG
LPTIM3
RX, TX as AF
UART7
TT-FDCAN1
PWRCTRL
DFSDM2 1ftr
LPTIM2
RX, TX as AF
I2C2/SMBUS
RAM
I/F
RX, TX, SCK
CTS, RTS as AF
UART5
I2C1/SMBUS
AHB4 280 MHz (max)
GPIO PORTA.. I
irDA
RX, TX, SCK, CTS,
RTS as AF
UART4
16b
MOSI, MISO, SCK, SS /
SDO, SDI, CK, WS, MCK, as AF
VREF+
1 channel as AF
irDA
SPI3/I2S3
LS
SCL, SDA, SMBAL as AF
1 channel as AF
SPI2/I2S2
AHB4
LPTIM3_OUT as AF
2 channels as AF
TIM13
TIM14
A P B 10 MHz
3
SWPMI
DAP
BDMA2
16b
TIM17
TIM6
DMA
Mux2
APB4
LPTIM2_OUT as AF
4 channels
TIM12
FIFO
TIM16
TIM1/PWM
DAC2_OUT1 as AF
4 channels, ETR as AF
TIM5
Digital filter
UART9
TIM8/PWM
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
4 channels, ETR as AF
TIM4
smcard
SPI5
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
DFSDM_CKOUT,
DFSDM_DATAIN[1:0],
DFSDM_CKIN[1:0]
4 channels, ETR as AF
smcard
SPI4
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
PA..I[15:0]
16b
TIM2
TIM3
USART2
SPI/I2S1
smcard
irDA USART6
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
16b
APB1 140 MHz (max)
SAI2
RX, TX, SCK, CTS, RTS as AF
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
DB-SDMMC2
Up to 20 analog inputs
USART3
SAI1/PDM
smcard
irDA USART1
RX, TX, SCK, CTS, RTS as AF
32b
3DES/AES
Up to 20 analog inputs
Some inputs are
common to ADC1&2
Analog Temp Sensor
DFSDM1 8ftrs
RX, TX, SCK, CTS, RTS as AF
RX, TX as AF
RNG
HSEM
HASH
AHB3
AHB4 280 MHz (max)
MOSI, MISO, SCK, SS as AF
ADC2
AHB/APB
CRC
16b
AHB4
MOSI, MISO, SCK, SS as AF
ADC1
AHB2 280 MHz (max)
AHB4
MOSI, MISO, SCK, SS /
SDO, SDI, CK, WS, MCK, as AF
DMA
Mux1
AHB_SRAM1 AHB_SRAM2
64 KB
64 KB
AHB1 280 MHz (max)
FIFO FIFO
SD, SCK, FS, MCLK, AF
OCTOSPI1
FIFO
SDMMC1
OCTOSPI2_signals
DB-SDMMC1
DB-OCTOSPI1
DB-OCTOSPI2
APB2 140 MHz (max)
SD, SCK, FS, MCLK, PDM_D[3:1],
PDM_CK[2:1] as AF
OTFDEC1
AHB3 (280 MHz)
AHB/APB
OCTOSPI2
JPEG
OTFDEC2
WWDG
FIFO
AHB/APB
DFSDM_CKOUT,
DFSDM_DATAIN[7:0],
DFSDM_CKIN[7:0]
64-bit AXI BUS-MATRIX
LCD-TFT
OCTOSPI1_signals
10 KB SRAM
HSYNC, VSYNC, PIXCLK, D[13:0]
PDCK, DE, RDY, D[15:0]
FIFO
FMC_signals
AHB4 280 MHz (max)
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
APB3 (140 MHz)
CHROM-ART
(DMA2D)
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
FIFO
FMC
16 Streams
FIFO
MDMA
SDMMC2 BDMA1 8ch
for DFSDM
DMA/
FIFO
32-bit AHB BUS-MATRIX
AHB2 (280 MHz)
I-Cache
16KB
DMA2
AHB1 (280 MHz)
ETM
TRACED[3:0]
PHY
OTG_FS
8 Stream 8 Stream
FIFOs
FIFOs
256 KB
AXI_SRAM1
384 KB
AXI_SRAM2
384 KB
AXI_SRAM3
AXIM
OCTOSPIM
TRACECK
JTAG/SW
AHB4
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
128 KB
FLASH
AHBP
ARM CPU
Cortex-M7
280 MHz
AHB2
CPU_AHBP
D-TCM
64KB
AHB4 (280 MHz)
D-TCM
64KB
AHB1 280 MHz (max)
I-TCM
64KB
MCO1
MCO2
@VDD
POR
reset
Int
SUPPLY
SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[6:1]
page 10/205
STM32H7B0xB
Functional overview
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors
for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and optimized power consumption, while delivering outstanding
computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
•
•
•
•
•
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
64-bit AXI4 interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
•
•
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm
execution.
It also supports single and double precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
Refer to Figure 1. STM32H7B0xB block diagram for the general block diagram of the STM32H7B0xB family.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources.
It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program
to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or
read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16
protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and
attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is generated.
3.3
Memories
3.3.1
Embedded flash memory
The STM32H7B0xB devices embed up to 128 Kbytes of flash memory that can be used for storing programs and
data.
The flash memory is organized as 137-bit flash words memory that can be used for storing both code and data
constants. Each word consists of:
•
•
One flash word (4 words, 16 bytes or 128 bits)
9 ECC bits.
The Flash memory is organized as follows:
•
•
•
DS13196 - Rev 7
128 Kbytes of user Flash memory, containing 16 user sectors of 8 Kbytes each
128 Kbytes of System Flash memory from which the device can boot.
1 Kbyte of OTP (one-time programmable) memory containing option bytes for user configuration.
page 11/205
STM32H7B0xB
Boot modes
3.3.2
Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H7B0xB devices embed the
Secure access mode, an enhanced security feature. This mode allows developing user-defined secure services
by ensuring, on the one hand code and data protection and on the other hand code safe execution.
Two types of secure services are available:
•
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for firmware and third-party
modules installation. These services rely on cryptographic algorithms based on a device unique private key.
•
User-defined secure services:
These services are embedded in user flash memory. Examples of user secure services are proprietary user
firmware update solution, secure flash integrity check or any other sensitive applications that require a high level
of protection.
The secure firmware is embedded in specific user flash memory areas configured through option bytes.
Secure services are executed just after a reset and preempt all other applications to guarantee protected and safe
execution. Once executed, the corresponding code and data are no more accessible.
The above secure services are available only for Cortex®-M7 core operating in Secure access mode. The other
masters cannot access the option bytes involved in Secure access mode settings or the flash secured areas.
3.3.3
Embedded SRAM
All devices feature:
•
1 Mbyte of AXI-SRAM mapped onto AXI bus matrix in CPU domain (CD) split into:
•
–
AXI-SRAM1: 256 Kbytes
–
AXI-SRAM2: 384 Kbytes
–
AXI-SRAM3: 384 Kbytes
128 Kbytes of AHB-RAM mapped onto AHB bus matrix in CPU domain (CD) split into:
•
•
–
AHB-SRAM1: 64 Kbytes
–
AHB-SRAM2: 64 Kbytes
32 Kbytes of SRD-SRAM mapped in Smart Run Domain (SRD)
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and is retained in Standby or
VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the CPU or the MDMA (even in
Sleep mode) through a specific AHB slave of the CPU(AHBP).
•
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU.
•
128 Kbytes of DTCM-RAM (2x 64 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap
memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex®-M7 dual
issue capability.
3.4
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to
program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
•
•
•
All flash address space
All RAM address space: ITCM, DTCM RAMs and SRAMs
The system memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the flash memory through a serial
interface (USART, I2C, SPI, USB-DFU, FDCAN). Refer to STM32 microcontroller system memory boot mode
application note (AN2606) for details.
DS13196 - Rev 7
page 12/205
STM32H7B0xB
Power supply management
3.5
Power supply management
3.5.1
Power supply scheme
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL.
•
VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the USB internal regulator. This
allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•
•
•
Note:
VDDMMC = 1.62 to 3.6 V external power supply for independent I/Os. VDDMMC can be higher than VDD.
VDDMMC pin should be tied to VDD when it is not used.
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
VCAP: VCORE supply, which value depends on voltage scaling (0.74 V, 0.9 V, 1.0 V, 1.1 V, 1.2 V or 1.3 V). It
is configured through VOS bits in PWR_CR3 register. The VCORE domain is split into two domains the CPU
domain (CD) and the Smart Run Domain (SRD).
•
–
CD domain containing most of the peripherals and the Arm® Cortex®-M7 core
–
SRD domain containing some peripherals and the system control.
VDDSMPS = 1.62 to 3.6 V: step-down converter power supply
•
VLXSMPS = VCORE or 1.8 to 2.5 V: external regulated step-down converter output
•
VFBSMPS = VCORE or 1.8 to 2.5 V: external step-down converter feedback voltage sense input
For I/O speed optimization at low VDD supply, refer to Section 3.8 General-purpose input/outputs (GPIOs).
The features available on the device depend on the package (refer to Table 1. STM32H7B0xB features and
peripheral counts).
During power-up and power-down phases, the following power sequence requirements must be respected (see
Figure 2. Power-up/power-down sequence):
•
•
When VDD is below 1 V, other power supplies (VDDA, VDD33USB and VDD50USB) must remain below VDD +
300 mV.
When VDD is above 1 V, all power supplies are independent (except for VDDSMPS, which must remain at the
same level as VDD).
During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided
to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with
different time constants during the power-down transient phase.
DS13196 - Rev 7
page 13/205
STM32H7B0xB
Power supply management
Figure 2. Power-up/power-down sequence
V
3.6
VDDX(1)
VDD
VPOR
VPDR
1
0.3
Power-on
Invalid supply area
3.5.2
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
1.
VDDx refers to any power supply among VDDA, VDD33USB and VDD50USB.
2.
VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a
Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in
reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed
threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be
configured through option bytes. A reset is generated when VDD drops below this threshold.
•
Programmable voltage detector (PVD)
The PVD monitors the VDD power supply by comparing it with a threshold selected from a set of predefined
values.
It can also monitor the voltage level of the PVD_IN pin by comparing it with an internal VREFINT voltage
reference level.
•
Analog voltage detector (AVD)
The AVD monitors the VDDA power supply by comparing it with a threshold selected from a set of predefined
values.
•
VBAT threshold
•
Temperature threshold
A dedicated temperature sensor monitors the junction temperature and compare it with two threshold levels.
The VBAT battery voltage level can be monitored by comparing it with two thresholds levels.
DS13196 - Rev 7
page 14/205
STM32H7B0xB
Low-power modes
3.5.3
Voltage regulator
The same voltage regulator supplies the two power domains (CD and SRD). The CD domain can be
independently switched off.
Voltage regulator output can be adjusted according to application needs through six power supply levels:
•
Run mode (VOS0 to VOS3)
•
–
Scale 0 and scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
–
Scale 3: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C, LPTIM) are operational
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or
asynchronous interrupt.
3.5.4
SMPS step-down converter
The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear switching regulator that
provides lower power consumption than a conventional voltage regulator (LDO).
The step-down converter can be used to:
•
Directly supply the VCORE domain
–
•
the SMPS step-down converter operating modes follow the device system operating modes (Run,
Stop, Standby).
–
the SMPS step-down converter output voltage are set according to the selected VOS and SVOS bits
(voltage scaling)
Provide intermediate voltage level to supply the internal voltage regulator (LDO)
–
•
The SMPS step-down converter operating modes follow the device system operating modes (Run,
Stop, Standby).
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level
Provide an external supply
–
–
The SMPS step-down converter is forced to external operating mode
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level
The 1.8 V or 2.5 V SMPS step-down converter output voltage imposes a minimum VDDSMPS supply of 2.5 V or
3.3 V, respectively. It defines indirectly the minimum VDD supply and I/O level.
3.6
Low-power modes
There are several ways to reduce power consumption on STM32H7B0xB:
•
•
Decrease dynamic power consumption by slowing down the system clocks even in Run mode and
individually clock gating the peripherals that are not used.
Save power consumption when the CPU is idle, by selecting among the available low-power mode
according to the user application needs. This allows achieving the best compromise between short startup
time, low-power consumption, as well as available wakeup sources.
The devices feature several low-power modes:
•
•
•
•
•
•
DS13196 - Rev 7
System Run with CSleep (CPU clock stopped)
Autonomous with CD domain in DStop (CPU and CPU Domain bus matrix clocks stopped)
Autonomous with CD domain in DStop2 (CPU and CPU Domain bus matrix clocks stopped, CPU domain in
retention mode)
System Stop (SRD domain clocks stopped) and CD domain in DStop (CPU and CPU Domain bus matrix
clocks stopped)
System Stop (SRD domain clocks stopped) and CD domain in DStop2 (CPU and CPU Domain bus matrix
clocks stopped, CPU domain in retention mode)
Standby (System, CD and SRD domains powered down)
page 15/205
STM32H7B0xB
Reset and clock controller (RCC)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE
(Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-M7 core is set after returning from an
interrupt service routine.
The CPU domain can enter low-power mode (DStop or DStop2) when the processor, its subsystem and the
peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains
are in DStop or DStop2 mode.
Table 2. System vs domain low-power mode
System power mode
CD domain power mode
SRD domain power mode
Run
DRun/DStop/DStop2
DRun
Stop
DStop/DStop2
DStop
Standby
Standby
Standby
Some GPIO pins can be used to monitor CPU and domain power states:
Table 3. Overview of low-power mode monitoring pins
3.7
Power state monitoring pins
Description
PWR_CSLEEP
CPU clock OFF
PWR_CSTOP
CPU domain in low-power mode
PWR_NDSTOP2
CPU domain retention mode selection
Reset and clock controller (RCC)
The clock and reset controller is located in the SRD domain. The RCC manages the generation of all the clocks,
as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the
choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some
communication peripherals that are capable to work with two different clock domains (either a bus interface clock
or a kernel peripheral clock), the system frequency can be changed without modifying the baud rate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal
oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
Internal oscillators:
•
–
64 MHz HSI clock (1% accuracy)
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
–
4-50 MHz HSE clock
32.768 kHz LSE clock
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock configuration.
A high precision can be achieved for the 48 MHz clock by using the embedded clock recovery system (CRS). It
uses the USB SOF signal, the LSE or an external signal (SYNC) to fine tune the oscillator frequency on-the- fly.
DS13196 - Rev 7
page 16/205
STM32H7B0xB
General-purpose input/outputs (GPIOs)
3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the
RCC and power controller status registers, as well as the backup power domain.
A system reset is generated in the following cases:
•
•
•
•
•
•
•
•
3.8
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Window watchdog
Independent watchdog
Software reset
Low-power mode security reset
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up
or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of
the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have
speed selection to better manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in Analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing
to the I/Os registers.
To maximize the performance, the I/O high-speed feature, HSLV, must be activated at low device supply voltage.
This is needed to achieve the performance required for peripherals such as the SDMMC, FMC and OCTOSPI.
The GPIOs are divided into four groups which can be optimized separately (refer to the description of HSLVx bits
of SYSCFG_CCCSR register in RM0455).
The I/O high-speed feature must be used only when VDD is lower than 2.7 V, and both the HSLV user option bits
(VDDIO_HSLV and VDDMMC_HSLV) and HSLVx bits must be set to enable it (refer to RM0455 for details).
DS13196 - Rev 7
page 17/205
DS13196 - Rev 7
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see
Figure 3. STM32H7B0xB bus matrix).
Figure 3. STM32H7B0xB bus matrix
AHBS
CPU
ITCM
64 Kbytes
Cortex-M7
I$
D$
16KB 16KB
DTCM
128 Kbytes
LTDC
AXI to AHB
SDMMC2 USBHS1
BDMA1
DMA2_PERIPH
DMA2D
DMA2
DMA2_MEM
MDMA
DMA1_PERIPH
SDMMC1
DMA1_MEM
AHBP
AXIM
DMA1
AHB SRAM1
64 Kbytes
GFX-MMU
AHB3
AHB SRAM2 64
Kbytes
APB3
AHB1
Flash
memory
128 Kbytes
AHB2
FMC
APB2
APB1
OTFDEC1
OCTOSPI1
OTFDEC2
OCTOSPI2
AXI SRAM1
256 Kbytes
AXI SRAM2
384 Kbytes
AXI SRAM3
384 Kbytes
32-bit AHB bus matrix
CD domain
64-bit AXI bus matrix
CD domain
CD-to-SRD AHB
BDMA2
Legend
AHB4
64-bit bus
Master interface
Bus multiplexer
Slave interface
SRD SRAM
32 Kbytes
page 18/205
32-bit AHB bus matrix
SRD domain
Backup
SRAM
4 Kbytes
APB4
STM32H7B0xB
TCM AHB
AXI
APB
Bus-interconnect matrix
32-bit bus
STM32H7B0xB
DMA controllers
3.10
DMA controllers
The devices feature five DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to
memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface
and a dedicated AHB interface to access Cortex®-M7 TCM memories.
The MDMA is located in the CD domain. It is able to interface with the other DMA controllers located in this
domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers.
•
•
•
Two dual-port DMAs (DMA1, DMA2) located in the CD domain and connected to the AHB matrix, with FIFO
and request router capabilities.
One basic DMA (BDMA1) located in the CD domain and connected to the AHB matrix. This DMA is
dedicated to the DFSDM (see Section 3.26 Digital filter for sigma-delta modulators (DFSDM))
One basic DMA (BDMA2) located in the SRD domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral
requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing
the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output
trigger or DMA event.
3.11
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data copy
and pixel format conversion. It supports the following functions:
•
•
•
•
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds
dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG
decoder output.
An interrupt can be generated when an operation is complete or at a programmed watermark.
All the operations are fully automatized and are running independently from the CPU or the DMAs.
3.12
Chrom-GRC™ (GFXMMU)
The Chrom-GRC™ is a graphical oriented memory management unit aimed at:
•
•
•
Optimizing memory usage according to the display shape
Manage cache linear accesses to the frame buffer
Prefetch data
The display shape is programmable to store only the visible image pixels.
A virtual memory space is provided which is seen by all system masters and can be physically mapped to any
system memory.
An interrupt can be generated in case of buffer overflow or memory transfer error.
3.13
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle
up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core.
•
•
•
•
•
•
DS13196 - Rev 7
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved
page 19/205
STM32H7B0xB
Extended interrupt and event controller (EXTI)
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt latency.
3.14
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power
domains and/or SRD domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split into 28 configurable events and 61 direct
events.
Configurable events have dedicated pending flags, active edge selection, and software trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.15
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In
the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC
calculation unit helps compute a signature of the software during runtime, to be compared with a reference
signature generated at link-time and stored at a given memory location.
3.16
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
•
•
•
•
•
•
•
3.17
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR flash memory/OneNAND flash memory
–
PSRAM (4 memory banks)
–
NAND flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock
divided by 2.
Octo-SPI memory interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal SPI memories.
The STM32H7B0xB embeds two separate Octo-SPI interfaces.
Each OCTOSPI instance supports single/dual/quad/octal SPI formats.
Multiplex of single/dual/quad/octal SPI over the same bus can be achieved using the integrated I/O manager.
The OCTOSPI can operate in any of the three following modes:
•
•
•
Indirect mode: all the operations are performed using the OCTOSPI registers
Status-polling mode: the external memory status register is periodically read and an interrupt can be
generated in case of flag setting
Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an
internal memory supporting both read and write operations.
The OCTOSPI support two frame formats supported by most external serial memories such as serial PSRAMs,
serial NOR flash memories, Hyper RAMs and Hyper flash memories:
•
The classical frame format with the command, address, alternate byte, dummy cycles and data phase
•
The HyperBus™ frame format.
Multichip package (MCP) combining any of the above mentioned memory types can also be supported.
DS13196 - Rev 7
page 20/205
STM32H7B0xB
Analog-to-digital converters (ADCs)
3.18
Analog-to-digital converters (ADCs)
The STM32H7B0xB devices embed two analog-to-digital converters, whose resolution can be configured to 16,
14, 12, 10 or 8 bits. Each ADC shares up to 24 external channels, performing conversions in the single-shot or
scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to a
destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected
channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6,
TIM8, TIM15, and LPTIM1 timers.
3.19
Analog temperature sensor
The STM32H7B0xB embeds an analog temperature sensor that generates a voltage (VTS) that varies linearly
with the temperature. This temperature sensor is internally connected to ADC2_IN18. The conversion range is
between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from −40 to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the
temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation,
the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated
by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is
accessible in read-only mode.
3.20
Digital temperature sensor (DTS)
The STM32H7B0xB embeds a sensor that converts the temperature into a square wave which frequency
is proportional to the temperature. The PCLK or the LSE clock can be used as reference clock for the
measurements. A formula given in the product reference manual (RM0455) allows to calculate the temperature
according to the measured frequency stored in the DTS_DR register.
3.21
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on
VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped
below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in
which case, the VDD mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
The devices embed an internal VBAT battery charging circuitry that can be activated when VDD is present.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from
VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and
VBAT pin should be connected to VDD.
3.22
Digital-to-analog converters (DAC)
The devices features one dual-channel DAC (DAC1), located in the CD domain, plus one single-channel DAC
(DAC2), located in the SRD domain.
The three 12-bit buffered DAC channels can be used to convert three digital signals into three analog voltage
signal outputs.
The following feature are supported:
DS13196 - Rev 7
page 21/205
STM32H7B0xB
Voltage reference buffer (VREFBUF)
•
•
•
•
•
•
•
•
•
•
three DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
Triple DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected to different DMA
streams.
3.23
Voltage reference buffer (VREFBUF)
The built-in voltage reference buffer can be used as voltage reference for ADCs and DACs, as well as voltage
reference for external components through the VREF+ pin.
Five different voltages are supported (refer to the reference manual for details).
3.24
Ultra-low-power comparators (COMP)
The STM32H7B0xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature
programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as
selectable output polarity.
The reference voltage can be one of the following:
•
•
•
•
•
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4)
The analog temperature sensor
The VBAT/4 supply.
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined
into a window comparator.
3.25
Operational amplifiers (OPAMP)
The STM32H7B0xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external
or internal follower routing and PGA capability, and two inputs and one output each. These three I/Os can be
connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers
can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
The operational amplifier main features are:
•
•
•
•
•
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15
Up to two positive inputs connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 8 MHz
The devices embed two operational amplifiers (OPMAP1 and OPAMP2) with two inputs and one output each.
These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The
operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging
from 2 to 16 or with inverting gain ranging from -1 to -15.
3.26
Digital filter for sigma-delta modulators (DFSDM)
The device embeds two DFSDM interfaces:
DS13196 - Rev 7
page 22/205
STM32H7B0xB
Digital filter for sigma-delta modulators (DFSDM)
•
•
DSFDM1
It is located in the CD domain and features eight external digital serial interfaces (channels) and eight digital
filters, or alternately eight internal parallel inputs.
DSFDM2
It is located in the SRD domain. DFSDM2 is a lite version including two external digital serial interfaces
(channels) and one digital filters.
The DFSDM peripherals interface the external Σ∆ modulators to microcontroller and then perform digital filtering
of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDMs can also interface
PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware.
The DFSDMs feature optional parallel data stream inputs from internal ADC peripherals or microcontroller
memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital
filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC
resolution.
The DFSDM peripherals support:
DS13196 - Rev 7
•
Multiplexed input digital serial channels:
•
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
Alternative inputs from eight internal digital parallel channels (up to 16 bit input resolution):
•
–
internal sources: ADC data or memory data streams (DMA)
Digital filter modules with adjustable digital signal processing:
•
•
•
•
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
Up to 24-bit output data resolution, signed output data format
Automatic data offset correction (offset stored in register by user)
Continuous or single conversion
Start-of-conversion triggered by:
•
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
Analog watchdog feature:
•
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
Short circuit detector to detect saturated analog input values (bottom and top range):
•
•
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
Break signal generation on analog watchdog event or on short circuit detector event
Extremes detector:
•
•
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
DMA capability to read the final conversion data
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence
page 23/205
STM32H7B0xB
Digital camera interface (DCMI)
•
“Regular” or “injected” conversions:
–
–
3.27
“regular” conversions can be requested at any time or even in continuous mode without having any
impact on the timing of “injected” conversions
“injected” conversions for precise timing and with high conversion priority
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS sensors through an
8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to
140 Mbyte/s using a 80 MHz pixel clock. It features:
•
•
•
•
•
3.28
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB
565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
Parallel synchronous slave interface (PSSI)
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It allows the transmitter
to send a data valid signal to indicate when the data is valid, and the receiver to output a flow control signal to
indicate when it is ready to sample the data.
The PSSI main features are:
•
•
•
•
Slave mode operation
8- or 16-bit parallel data input or output
8-word (32-byte) FIFO
Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data is valid or the receiver to
indicate when it is ready to sample the data, or both.
The PSSI shares most of the circuitry with the digital camera interface (DCMI). It thus cannot be used
simultaneously with the DCMI.
3.29
LCD-TFT display controller (LTDC)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals
to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following
features:
•
•
•
•
•
•
•
•
3.30
2 display layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
JPEG codec (JPEG)
The JPEG codec can encode and decode a JPEG stream as defined in the
ISO/IEC10918-1 specification. It provides an fast and simple hardware compressor and decompressor of JPEG
images with full management of JPEG headers.
The JPEG codec main features are as follows:
•
•
•
DS13196 - Rev 7
8-bit/channel pixel depths
Single clock per pixel encoding and decoding
Support for JPEG header generation and parsing
page 24/205
STM32H7B0xB
True random number generator (RNG)
•
•
•
•
•
•
•
•
•
•
•
•
3.31
Up to four programmable quantization tables
Fully programmable Huffman tables (two AC and two DC)
Fully programmable minimum coded unit (MCU)
Encode/decode support (non simultaneous)
Single clock Huffman coding and decoding
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
Stallable design
Support for single greyscale component
Ability to enable/disable header processing
Internal register interface
Fully synchronous design
Configuration for high-speed decode mode
True random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. The
RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It
is composed of a live entropy source (analog) and an internal conditioning component.
3.32
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic algorithms usually
required to ensure confidentiality, authentication, data integrity and non-repudiation when exchanging messages
with a peer:
•
Encryption/Decryption
–
•
DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and
CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining
algorithms, 128, 192 or 256-bit key
Universal HASH
–
–
–
SHA-1 and SHA-2 (secure HASH algorithms)
MD5
HMAC
The cryptographic accelerator supports DMA request generation.
3.33
On-the-fly decryption engine (OTFDEC)
The embedded OTFDEC decrypts in real-time the encrypted content stored in the external Octo-SPI memories
used in Memory-mapped mode.
The OTFDEC uses the AES-128 algorithm in counter mode (CTR).
Code execution on external Octo-SPI memories can be protected against fault injection thanks to
STMicroelectronics enhanced encryption mode (refer to RM0455 for details).
The OTFDEC main features are as follow:
•
On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or multiple).
•
–
AES-CTR algorithm with keystream FIFO (depth= 4)
–
Support for any read size
Up to four independent encrypted regions
•
•
–
Region definition granularity: 4096 bytes
–
Region configuration write locking mechanism
–
Two optional decryption modes: execute-only and execute-never
128-bit key for each region, two-byte firmware version, and eight-byte application-defined nonce
Encryption keys confidentiality and integrity protection
–
–
DS13196 - Rev 7
Write only registers with software locking mechanism
Availability of 8-bit CRC as public key information
page 25/205
STM32H7B0xB
Timers and watchdogs
•
•
3.34
Support for STM32 Octo-SPI prefetching mechanism.
Encryption mode
Timers and watchdogs
The devices include two advanced-control timers, ten general-purpose timers, two basic timers, three low-power
timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4. Timer feature comparison compares the features of the advanced-control, general-purpose and basic
timers.
Table 4. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
TIM1,
TIM8
16-bit
Up, Down,
Up/down
Any integer
between 1 and
65536
Yes
4
Yes
140
280
TIM2,
TIM5
32-bit
Up, Down,
Up/down
Any integer
between 1 and
65536
Yes
4
No
140
280
TIM3,
TIM4
16-bit
Up, Down,
Up/down
Any integer
between 1 and
65536
Yes
4
No
140
280
TIM12
16-bit
Up
Any integer
between 1 and
65536
No
2
No
140
280
TIM13,
TIM14
16-bit
Up
Any integer
between 1 and
65536
No
1
No
140
280
TIM15
16-bit
Up
Any integer
between 1 and
65536
Yes
2
1
140
280
TIM16,
TIM17
16-bit
Up
Any integer
between 1 and
65536
Yes
1
1
140
280
Basic
TIM6,
TIM7
16-bit
Up
Any integer
between 1 and
65536
Yes
0
No
140
280
Low-power
timer
LPTIM1,
LPTIM2,
LPTIM3
16-bit
Up
1, 2, 4, 8, 16, 32,
64, 128
No
0
No
140
280
Advancedcontrol
General
purpose
1. The maximum timer clock is up to 280 MHz depending on TIMPRE bit in the RCC_CFGR register and CDPRE1/2 bits in RCC_CDCFGR
register.
3.34.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead times. They can also be
considered as complete general-purpose timers. Their 4 independent channels can be used for:
•
•
•
•
DS13196 - Rev 7
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
page 26/205
STM32H7B0xB
Timers and watchdogs
If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If
configured as 16-bit PWM generators, they have full modulation capability (0-100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization
or event chaining.
The advanced-control timers support independent DMA request generation.
3.34.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H7B0xB devices (see
Table 4. Timer feature comparison for differences).
3.34.3
•
TIM2, TIM3, TIM4 and TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5
are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels
for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose
timers and the advanced-control timers (TIM1, TIM8) via the Timer Link feature for synchronization or event
chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4 and TIM5 all have independent DMA request generation. They are capable of handling
quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and
TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for
input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2,
TIM3, TIM4 and TIM5 full-featured general-purpose timers or used as simple time bases.
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic
16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.34.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3)
The low-power timers feature an independent clock and are running also in Stop mode if they are clocked by LSE,
LSI or an external clock. The low-power timers are able to wakeup the devices from Stop mode.
The low-power timers support the following features:
•
•
•
•
•
•
•
•
•
•
3.34.5
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source running, used by the
Pulse Counter Application)
Programmable digital glitch filter
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an
independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop
and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a
free-running timer for application timeout management. It is hardware- or software-configurable through the option
bytes.
DS13196 - Rev 7
page 27/205
STM32H7B0xB
Real-time clock (RTC)
3.34.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a
watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning
interrupt capability and the counter can be frozen in debug mode.
3.34.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It
features:
•
•
•
•
3.35
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
Real-time clock (RTC)
The RTC is an independent BCD timer/counter. It supports the following features:
•
•
•
•
•
•
•
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD
(binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master
clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the
calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.
Timestamp feature which can be used to save the calendar content. This function can be triggered by an
event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.
The RTC is supplied through a switch that takes power either from the VDD supply when present or from the VBAT
pin.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by
the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device
from the low-power modes.
3.36
Tamper and backup registers (TAMP)
The TAMP main features are the following:
•
32 backup registers:
–
•
•
•
•
DS13196 - Rev 7
The backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on
by VBAT when the VDD power is switched off.
Three external tamper detection events
–
Each external event can be configured to be active or passive
–
External passive tampers with configurable filter and internal pull-up
Seven internal tamper events
Any tamper detection can generate an RTC timestamp event
Any tamper detection can erase the RTC backup registers, the backup SRAM and the memory regions
protected by the on-the-fly decryption engine (OTFDEC)
page 28/205
STM32H7B0xB
Inter-integrated circuit interface (I2C)
•
3.37
Monotonic counter
Inter-integrated circuit interface (I2C)
The STM32H7B0xB embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all
I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
•
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bit rate up to 100 kbit/s
–
Fast-mode (Fm), with a bit rate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System management bus (SMBus) specification rev 2.0 compatibility:
–
–
–
•
•
•
•
•
3.38
Hardware PEC (packet error checking) generation and verification with ACK control
Address resolution protocol (ARP) support
SMBus alert
Power system management protocol (PMBus®) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming.
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter (USART)
The STM32H7B0xB devices have five embedded universal synchronous receiver transmitters (USART1,
USART2, USART3, USART6 and USART10) and five universal asynchronous receiver transmitters (UART4,
UART5, UART7, UART8 and UART9). Refer to the table below for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor
communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They
provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to
communicate at speeds of up to 10Mbit/s.
USART1, USART2, USART3, USART6 and USART10 also provide Smartcard mode (ISO 7816 compliant) and
SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by
software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU
from Stop mode.The wakeup from Stop mode are programmable and can be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
X = supported.
DS13196 - Rev 7
USART modes/features
USART1/2/3/6/10
UART4/5/7/8/9
Hardware flow control for modem
X
X
page 29/205
STM32H7B0xB
Low-power universal asynchronous receiver transmitter (LPUART)
USART modes/features
USART1/2/3/6/10
UART4/5/7/8/9
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
Tx/Rx FIFO
Tx/Rx FIFO size
3.39
7, 8 and 9 bits
X
X
16
Low-power universal asynchronous receiver transmitter (LPUART)
The device embeds one Low-power UART (LPUART1). The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
The LPUART embeds a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by
software and is disabled by default.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode.
The wakeup from Stop mode are programmable and can be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even
in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption.
Higher speed clock can be used to reach higher baud rates.
LPUART interface can be served by the DMA controller.
3.40
Serial peripheral interfaces (SPI)/integrated interchip sound interfaces (I2S)
The devices feature up to six SPIs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3, SPI6/I2S6 and SPI4, SPI5) that allow
communicating up to 125 Mbits/s in master and slave modes, in half-duplex, full-duplex and simplex modes. The
3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 32 bits for SPI1/I2S1,
SPI2/I2S2, SPI3/I2S3, from 4 to 16 bits for the others. All SPI interfaces support SS pulse mode, TI mode,
Hardware CRC calculation, and 16x 8-bit embedded Rx and Tx FIFOs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3) or 8x
8-bit embedded Rx and Tx FIFOs (SPI4, SPI5, SPI6/I2S6), all with DMA capability. .
Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3, SPI6) are available. They can be operated in
master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit
resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported.
When one or all I2S interfaces is/are configured in master mode, the master clock can be output to the external
DAC/codec at 256 times the sampling frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs
with DMA capability.
DS13196 - Rev 7
page 30/205
STM32H7B0xB
Serial audio interfaces (SAI)
3.41
Serial audio interfaces (SAI)
The devices embed two SAIs (SAI1, SAI2) that allow designing many stereo or mono audio protocols such as
I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is
configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent
audio sub-blocks. Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
One of the SAI supports up to 8 microphones thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and
can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other
SAIs to work synchronously.
3.42
SPDIFRX receiver interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These
standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound,
such as those defined by Dolby or DTS (up to 5.1).
The main SPDIFRX features are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming
data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX
will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks
elements. It delivers to the CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will
be used to compute the exact sample rate for clock drift algorithms.
3.43
Single wire protocol master interface (SWPMI)
The single wire protocol master interface (SWPMI) is the master interface corresponding to the contactless
frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:
•
•
•
•
full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bit rate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
3.44
Management data input/output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
32 MDIO register addresses, each of which is managed using separate input and output data registers:
•
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
DS13196 - Rev 7
MDIO register write
MDIO register read
MDIO protocol error
page 31/205
STM32H7B0xB
SD/SDIO/MMC card host interfaces (SDMMC)
•
3.45
Able to operate in and wake up from STOP mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System Specification version 4.51 in
three different databus modes: 1 bit (default), 4 bits and 8 bits.
One of the SDMMC interface can be supplied through a separate VDDMMC supply. If required, it can thus operate
at a different voltage level than all other I/Os.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version
4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version
4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the
interface and the SRAM.
3.46
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory
and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version
2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized
time-triggered communication, global system time, and clock drift compensation. FDCAN1 contains additional
registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and
time-triggered CAN communication.
A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs,
transmit buffers (and triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2
modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and
FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.
3.47
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral that supports both
full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and a
UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG_HS interface in
HS mode, an external PHY device connected to the ULPI is required.
The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification.
It features software-configurable endpoint setting and supports suspend/resume. The USB OTG_HS controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
The main features are:
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the
60 MHz output.
•
•
•
DS13196 - Rev 7
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are connected
page 32/205
STM32H7B0xB
High-definition multimedia interface (HDMI) - consumer electronics control (CEC)
3.48
High-definition multimedia interface (HDMI) - consumer electronics control
(CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the consumer electronics control
(CEC) protocol (supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an environment. It is
specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain
independent from the CPU clock, allowing the HDMI-CEC controller to wake up the MCU from Stop mode on data
reception.
3.49
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software development and system
integration.
•
•
•
•
•
•
•
•
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools.
The trace port performs data capture for logging and analysis.
DS13196 - Rev 7
page 33/205
STM32H7B0xB
Memory mapping
4
Memory mapping
Refer to the product line reference manual (RM0455) for details on the memory mapping as well as the boundary
addresses for all peripherals.
DS13196 - Rev 7
page 34/205
STM32H7B0xB
Pin descriptions
5
Pin descriptions
1.
DS13196 - Rev 7
PC12
PC11
PC10
PA15
PA14
51
50
49
PB5
57
52
PB6
58
53
PB7
59
54
BOOT0
60
PB4
PB8
61
PB3
PD2
PB9
62
55
VSS
63
56
VDD
64
Figure 4. LQFP64 (STM32H7B0xB without SMPS) pinout
VBAT
1
48
VDD
PC13
2
47
VSS
PC14-OSC32_IN
3
46
VCAP
PC15-OSC32_OUT
4
45
PA13
PH0-OSC_IN
5
44
PA12
PH1-OSC_OUT
6
43
PA11
NRST
7
42
PA10
PC0
8
41
PA9
PC1
9
40
PA8
PC2
10
39
PC9
PC3
11
38
PC7
VSSA
12
37
PC6
VDDA
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
LQFP64
The above figure shows the package top view.
page 35/205
STM32H7B0xB
Pin descriptions
PA15
PA14
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
Figure 5. LQFP100 (STM32H7B0xB without SMPS) pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1.
DS13196 - Rev 7
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
VCAP
PB11
PB10
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PC4
PA7
PA6
PA5
PA4
75
74
73
72
71
70
69
68
67
66
65
64
LQFP100
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
NRST
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PA1
PA2
PA3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_ON
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PH1-OSC_OUT
The above figure shows the package top view.
page 36/205
STM32H7B0xB
Pin descriptions
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDDMMC
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 6. LQFP144 (STM32H7B0xB without SMPS) pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQPF144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
1.
DS13196 - Rev 7
The above figure shows the package top view.
page 37/205
STM32H7B0xB
Pin descriptions
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDDMMC
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
Figure 7. LQFP176 (STM32H7B0xB without SMPS) pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LQFP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
PH4
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PH11
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
PH3
1.
DS13196 - Rev 7
The above figure shows the package top view.
page 38/205
STM32H7B0xB
Pin descriptions
Figure 8. UFBGA169 (STM32H7B0xB with SMPS) ballout
1
2
3
4
5
A
PE4
PE2
VDD
VCAP
PB6
B
PC15OSC32_
OUT
PE3
VSS
VDDLDO
PB8
C
PC14OSC32_IN
PE6
PE5
PDR_ON
PB9
VSS
PC13
PE1
D
VDD
6
7
8
9
10
11
12
13
VDDMMC
VDD
PG10
PD5
VDD
PC12
PC10
PH14
PB4
VSS
PG11
PD6
VSS
PC11
PA14
PH13
PB5
PG14
PG9
PD4
PD1
PA15
VSS
VDD
PE0
PB7
PG13
PD7
PD3
PD0
PA13
VDDLDO
VCAP
PG15
PG12
PD2
PA10
PA9
PA8
PA12
PB3
PG4
PC6
PC7
PC9
PC8
PA11
E
VLXSMPS
VSSSMPS
VBAT
PF1
PF3
BOOT0
F
VDDSMPS
VFBSMPS
PF0
PF2
PF5
PF7
VSS
PF4
PF6
PF9
NRST
PF13
PE7
PG6
PG7
PG8
PF10
PF8
PC2
PA4
PF14
PE8
PG2
PG3
PG5
VSS
VDD
G
VDD
PH1OSC_OUT
VDD50USB VDD33USB
H
PH0OSC_IN
J
PC0
PC1
VSSA
PC3
PA0
PA7
PF15
PE9
PE14
PD11
PD13
PD15
PD14
K
PC3_C
PC2_C
PA0_C
PA1
PA6
PC4
PG0
PE13
PH10
PH12
PD9
PD10
PD12
L
VDDA
VREF+
PA1_C
PA5
PB1
PB2
PG1
PE12
PB10
PH11
PB13
VSS
VDD
M
VDD
VSS
PH3
VSS
PB0
PF11
VSS
PE10
PB11
VDDLDO
VSS
PD8
PB15
N
PA2
PH2
PA3
VDD
PC5
PF12
VDD
PE11
PE15
VCAP
VDD
PB12
PB14
1.
DS13196 - Rev 7
The above figure shows the package top view.
page 39/205
STM32H7B0xB
Pin descriptions
Figure 9. UFBGA176+25 (STM32H7B0xB with SMPS) ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PA14
VDDLDO
VCAP
VSS
A
VSS
PB8
VDDLDO
VCAP
PB6
PB3
PG11
PG9
PD3
PD1
PA15
B
PE4
PE3
PB9
PE0
PB7
PB4
PG13
PD7
PD5
PD2
PC12
PH14
PA13
PA8
PA12
C
PC13
VSS
PE2
PE1
BOOT0
PB5
PG14
PG10
PD4
PD0
PC11
PC10
PH13
PA10
PA11
PC14OSC32_IN
PE5
PDR_ON
VDD
MMC
VSS
PG15
PG12
PD6
VSS
VDD
PH15
PA9
PC8
PC7
VDD
PC9
PC6
VDD50
USB
D
PC15OSC32_
OUT
E
VSS
VBAT
PE6
VDD
F
VLX
SMPS
VSS
SMPS
PF1
PF0
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
USB
PG6
PG5
G
VDD
SMPS
VFB
SMPS
PF2
VDD
VSS
VSS
VSS
VSS
VSS
PG8
PG7
PG4
PG2
H
PF6
PF4
PF5
PF3
VSS
VSS
VSS
VSS
VSS
VDD
PG3
PD14
PD13
J
PH0OSC_IN
PF8
PF7
PF9
VSS
VSS
VSS
VSS
VSS
PD15
PD11
VSS
PD12
K
PH1OSC_
OUT
VSS
PF10
VDD
VSS
VSS
VSS
VSS
VSS
VSS
PD9
PB15
PB14
L
NRST
PC0
PC1
VREF−
VDD
PD10
PD8
PB13
M
PC2
PC3
VREF+
VDDA
VDD
VSS
PC5
PB1
VDD
VSS
PH7
PE14
PH11
PH9
PB12
N
PC2_C
PC3_C
VSSA
PH2
PA3
PA7
PF11
PE8
PG1
PF15
PF13
PB10
PH8
PH10
PH12
P
PA0
PA1
PA1_C
PH4
PA4
PA5
PB2
PG0
PE7
PB11
PF12
PE12
PE13
PE15
PH6
R
VSS
PA2
PA0_C
PH3
PH5
PC4
PA6
PB0
PE10
PF14
PE9
PE11
VCAP
VDDLDO
VSS
1.
2.
The above figure shows the package top view.
The devices with SMPS correspond to commercial code STM32H7B0IIK6Q.
Table 6. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin
function during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with
embedded weak pull-up resistor
Option for TT and FT I/Os
_f
DS13196 - Rev 7
I2C FM+ option
page 40/205
STM32H7B0xB
Pin descriptions
Name
Abbreviation
Definition
_a
analog option (supplied by VDDA)
_u
USB option (supplied by
VDD33USB)
_h0 (1)
High-speed low voltage (mainly
SDMMC2 on VDDMMC power rail)
_h1(1)
High-speed low voltage (mainly
for OCTOSPI)
_h2(1)
High-speed low voltage (mainly
for FMC)
_h3(1)
High-speed low voltage
_s
Secondary supply (supplied by
VDDMMC) (2)
I/O structure
Unless otherwise specified by a note, all I/Os are set as floating inputs
during and after reset.
Notes
Pin functions
Alternate functions
Functions selected through GPIOx_AFR registers
Additional functions
Functions directly selected/enabled through peripheral registers
1. Refer to SYSCFG_CCCSR register in the device reference manual for how to set a group of I/Os in High-speed low-voltage mode.
Depending on the chosen I/Os (for example OCTOSPI), it can belong to several groups of I/Os and several HSLVx bits need to be set (refer
to Table Pin/ball definition). Take care that the VDDIO_HSLV and/or VDDMMC_HSLV option bits must also be set.
2. Refer to the table Features and peripheral counts for the list of packages featuring a VDDMMC separate supply pad.
Table 7. STM32H7B0xB pin/ball definition
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
A2
C3
-
1
1
1
PE2
I/O
FT_h2
TRACECLK, SAI1_CK1, SPI4_SCK,
SAI1_MCLK_A, OCTOSPIM_P1_IO2,
USART10_RX, FMC_A23, EVENTOUT
-
B2
B2
-
2
2
2
PE3
I/O
FT_h2
TRACED0, TIM15_BKIN, SAI1_SD_B,
USART10_TX, FMC_A19, EVENTOUT
-
A1
B1
-
3
3
3
PE4
I/O
FT_h2
TRACED1, SAI1_D2, DFSDM1_DATIN3,
TIM15_CH1N, SPI4_SS, SAI1_FS_A,
FMC_A20, DCMI_D4/PSSI_D4,
LCD_B0, EVENTOUT
-
FT_h2
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A, FMC_A21,
DCMI_D6/PSSI_D6, LCD_G0,
EVENTOUT
-
-
C3
D3
-
4
4
4
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
PE5
I/O
C2
E3
-
5
5
5
PE6
I/O
FT_h2
TRACED3, TIM1_BKIN2, SAI1_D1,
TIM15_CH2, SPI4_MOSI, SAI1_SD_A,
SAI2_MCK_B, TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7/PSSI_D7,
LCD_G1, EVENTOUT
B3
A1
-
-
-
-
VSS
S
-
-
-
A3
-
-
-
-
-
VDD
S
-
-
-
E3
E2
1
6
6
6
VBAT
S
-
-
-
D2
A15
-
-
-
-
VSS
S
-
-
-
DS13196 - Rev 7
page 41/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
-
-
-
-
-
7
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
PI8
I/O
FT
EVENTOUT
TAMP_IN2/
TAMP_OUT3,
RTC_OUT2, WKUP4
PC13
I/O
FT
EVENTOUT
TAMP_IN1/
TAMP_OUT2/
TAMP_OUT3,
RTC_OUT1/RTC_TS,
WKUP3
-
VSS
S
-
-
-
I/O
FT
EVENTOUT
OSC32_IN
D3
C1
2
7
7
8
-
C2
-
-
-
C1
D2
3
8
8
9
PC14-OSC32_IN
(OSC32_IN)
B1
D1
4
9
9
10
PC15OSC32_OUT
(OSC32_OUT)
I/O
FT
EVENTOUT
OSC32_OUT
-
-
-
-
-
11
PI9
I/O
FT_h2
OCTOSPIM_P2_IO0, UART4_RX,
FDCAN1_RX, FMC_D30, LCD_VSYNC,
EVENTOUT
-
-
-
-
-
-
12
PI10
I/O
FT_h2
OCTOSPIM_P2_IO1, FMC_D31,
PSSI_D14, LCD_HSYNC, EVENTOUT
-
-
-
-
-
-
13
PI11
I/O
FT
OCTOSPIM_P2_IO2, LCD_G6,
OTG_HS_ULPI_DIR, PSSI_D15,
EVENTOUT
WKUP5
-
D10
-
-
-
14
VSS
S
-
-
-
D1
D11
-
-
-
15
VDD
S
-
-
-
E2
F2
-
-
-
-
VSSSMPS
S
-
-
-
E1
F1
-
-
-
-
VLXSMPS
S
-
-
-
F1
G1
-
-
-
-
VDDSMPS
S
-
-
-
F2
G2
-
-
-
-
VFBSMPS
S
-
-
-
F3
F4
-
-
10
16
PF0
I/O
FT_f
I2C2_SDA, OCTOSPIM_P2_IO0,
FMC_A0, EVENTOUT
-
E4
F3
-
-
11
17
PF1
I/O
FT_f
I2C2_SCL, OCTOSPIM_P2_IO1,
FMC_A1, EVENTOUT
-
F4
G3
-
-
12
18
PF2
I/O
FT_h2
I2C2_SMBA, OCTOSPIM_P2_IO2,
FMC_A2, EVENTOUT
-
E5
H4
-
-
13
19
PF3
I/O
FT_h2
OCTOSPIM_P2_IO3, FMC_A3,
EVENTOUT
-
G3
H2
-
-
14
20
PF4
I/O
FT_h2
OCTOSPIM_P2_CLK, FMC_A4,
EVENTOUT
-
F5
H3
-
-
15
21
PF5
I/O
FT_h2
OCTOSPIM_P2_NCLK, FMC_A5,
EVENTOUT
-
B7
E1
-
10
16
22
VSS
S
-
-
-
A7
E4
-
11
17
23
VDD
S
-
-
-
G4
H1
-
-
18
24
PF6
I/O
FT_h1
TIM16_CH1, SPI5_SS, SAI1_SD_B,
UART7_Rx, OCTOSPIM_P1_IO3,
EVENTOUT
F6
J3
-
-
19
25
PF7
I/O
FT_h1
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_Tx,
OCTOSPIM_P1_IO2, EVENTOUT
-
H4
J2
-
-
20
26
PF8
I/O
FT_h1
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B, UART7_RTS,
TIM13_CH1, OCTOSPIM_P1_IO0,
EVENTOUT
-
DS13196 - Rev 7
page 42/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
G5
J4
-
-
21
27
PF9
I/O
FT_h1
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS, TIM14_CH1,
OCTOSPIM_P1_IO1, EVENTOUT
-
H3
K3
-
-
22
28
PF10
I/O
FT_h1
TIM16_BKIN, SAI1_D3, PSSI_D15,
OCTOSPIM_P1_CLK, DCMI_D11/
PSSI_D11, LCD_DE, EVENTOUT
-
H1
J1
5
12
23
29
PH0OSC_IN(PH0)
I/O
FT
EVENTOUT
OSC_IN
H2
K1
6
13
24
30
PH1-OSC_OUT
(PH1)
I/O
FT
EVENTOUT
OSC_OUT
G6
L1
7
14
25
31
NRST
I/O
RST
-
-
FT_a
DFSDM1_CKIN0, DFSDM1_DATIN4,
SAI2_FS_B, FMC_A25,
OTG_HS_ULPI_STP, LCD_G2,
FMC_SDNWE, LCD_R5, EVENTOUT
ADC12_INP10
FT_ah0
TRACED0, SAI1_D1,
DFSDM1_DATIN0, DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, SAI1_SD_A,
SDMMC2_CK, OCTOSPIM_P1_IO4,
MDIOS_MDC, LCD_G5, EVENTOUT
ADC12_INP11,
ADC12_INN10,
TAMP_IN3, WKUP6
ADC12_INP12,
ADC12_INN11
J1
J2
H5
L2
L3
(3)
M1 (3)
K2
N1
(3)
(3)
8
9
15
16
26
27
32
33
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
PC0
PC1
I/O
I/O
10
-
-
-
PC2
I/O
FT_a
PWR_CSTOP, DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT, OCTOSPIM_P1_IO2,
OTG_HS_ULPI_DIR,
OCTOSPIM_P1_IO5, FMC_SDNE0,
EVENTOUT
-
17(4)
28(4)
34(4)
PC2_C
ANA
TT_a
-
ADC2_INP0,
ADC2_INN1
ADC12_INP13,
ADC12_INN12
J4(3)
M2(3)
11
-
-
-
PC3
I/O
FT_a
PWR_CSLEEP, DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OCTOSPIM_P1_IO0,
OTG_HS_ULPI_NXT,
OCTOSPIM_P1_IO6, FMC_SDCKE0,
EVENTOUT
K1(3)
N2(3)
-
18(4)
29(4)
35(4)
PC3_C
ANA
TT_a
-
ADC2_INP1
G1
E12
-
-
30
36
VDD
S
-
-
G2
F6
-
-
-
-
VSS
S
-
-
J3
N3
12
19
31
37
VSSA
S
-
-
-
L4
-
-
-
-
VREF-
S
-
-
L2
M3
-
20
32
38
VREF+
S
-
-
L1
M4
13
21
33
39
VDDA
S
-
-
ADC1_INP16,
WKUP1
J5(3)
P1(3)
14
22
34
40
PA0
I/O
FT_a
TIM2_CH1/TIM2_ETR, TIM5_CH1,
TIM8_ETR, TIM15_BKIN,
SPI6_SS/I2S6_WS, USART2_CTS/
USART2_NSS, UART4_TX,
SDMMC2_CMD, SAI2_SD_B,
EVENTOUT
K3(3)
R3(3)
-
-
-
-
PA0_C
ANA
TT_a
-
ADC1_INP0,
ADC1_INN1
ADC1_INP17,
ADC1_INN16
ADC1_INP1
K4(3)
P2(3)
15
23
35
41
PA1
I/O
FT_ah1
TIM2_CH2, TIM5_CH2, LPTIM3_OUT,
TIM15_CH1N, USART2_RTS,
UART4_RX, OCTOSPIM_P1_IO3,
SAI2_MCK_B, OCTOSPIM_P1_DQS,
LCD_R2, EVENTOUT
L3(3)
P3(3)
-
-
-
-
PA1_C
ANA
TT_a
-
DS13196 - Rev 7
page 43/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
N1
R2
16
24
36
42
PA2
I/O
FT_a
TIM2_CH3, TIM5_CH3, TIM15_CH1,
DFSDM2_CKIN1, USART2_TX,
SAI2_SCK_B, MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC1_INP14,
WKUP2
N2
N4
-
-
-
43
PH2
I/O
FT_h2
LPTIM1_IN2, OCTOSPIM_P1_IO4,
SAI2_SCK_B, FMC_SDCKE0, LCD_R0,
EVENTOUT
-
M1
G4
-
-
-
-
VDD
S
-
-
-
M2
F7
-
-
-
-
VSS
S
-
-
-
M3
R4
-
-
-
44
PH3
I/O
FT_ah2
OCTOSPIM_P1_IO5, SAI2_MCK_B,
FMC_SDNE0, LCD_R1, EVENTOUT
-
-
P4
-
-
-
45
PH4
I/O
FT_fa
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT, PSSI_D14,
LCD_G4, EVENTOUT
-
-
R5
-
-
-
46
PH5
I/O
FT_fa
I2C2_SDA, SPI5_SS, FMC_SDNWE,
EVENTOUT
-
ADC1_INP15
N3
48
VSS
S
-
-
-
49
VDD
S
-
-
-
50
PA4
I/O
TT_a
TIM5_ETR, SPI1_SS/I2S1_WS,
SPI3_SS/I2S3_WS, USART2_CK,
SPI6_SS/I2S6_WS, DCMI_HSYNC/
PSSI_DE, LCD_VSYNC, EVENTOUT
ADC1_INP18,
DAC1_OUT1
TT_ah0
PWR_NDSTOP2, TIM2_CH1/
TIM2_ETR, TIM8_CH1N, SPI1_SCK/
I2S1_CK, SPI6_SCK/I2S6_CK,
OTG_HS_ULPI_CK, PSSI_D14,
LCD_R4, EVENTOUT
ADC1_INP19,
ADC1_INN18,
DAC1_OUT2
TT_ah1
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO/I2S1_SDI,
OCTOSPIM_P1_IO3, SPI6_MISO/
I2S6_SDI, TIM13_CH1,
TIM8_BKIN_COMP12, MDIOS_MDC,
TIM1_BKIN_COMP12, DCMI_PIXCLK/
PSSI_PDCK, LCD_G2, EVENTOUT
ADC12_INP3,
DAC2_OUT1
ADC12_INP7,
ADC12_INN3,
OPAMP1_VINM
47
M4
F8
18
26
38
N4
H12
19
27
39
H6
P5
20
28
40
K5
R7
22
30
41
42
Additional functions
FT_ah1
37
29
Alternate functions
I/O
25
21
I/O
structure
PA3
17
P6
Pin type
TIM2_CH4, TIM5_CH4,
OCTOSPIM_P1_CLK, TIM15_CH2,
I2S6_MCK, USART2_RX, LCD_B2,
OTG_HS_ULPI_D0, LCD_B5,
EVENTOUT
N5
L4
Pin name
(function after
reset)
51
52
PA5
PA6
I/O
I/O
J6
N6
23
31
43
53
PA7
I/O
FT_ah1
TIM1_CH1N, TIM3_CH2, TIM8_CH1N,
DFSDM2_DATIN1, SPI1_MOSI/
I2S1_SDO, SPI6_MOSI/I2S6_SDO,
TIM14_CH1, OCTOSPIM_P1_IO2,
FMC_SDNWE, LCD_VSYNC,
EVENTOUT
K6
R6
24
32
44
54
PC4
I/O
FT_a
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX1_IN2, FMC_SDNE0,
LCD_R7, EVENTOUT
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
N5
M7
25
33
45
55
PC5
I/O
FT_ah1
SAI1_D3, DFSDM1_DATIN2, PSSI_D15,
SPDIFRX1_IN3, OCTOSPIM_P1_DQS,
FMC_SDCKE0, COMP1_OUT, LCD_DE,
EVENTOUT
ADC12_INP8,
ADC12_INN4,
OPAMP1_VINM
N7
K4
-
-
-
-
VDD
S
-
-
-
M7
F9
-
-
-
-
VSS
S
-
-
-
DS13196 - Rev 7
page 44/205
STM32H7B0xB
Pin descriptions
M5
L5
R8
M8
26
27
34
35
46
47
LQFP176
LQFP144
LQFP100
LQFP64
UFBGA176+25 with SMPS
UFBGA169 with SMPS
Pin/ball name(1) (2)
56
57
Pin name
(function after
reset)
PB0
PB1
Pin type
I/O
I/O
I/O
structure
Alternate functions
Additional functions
FT_ah0
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, DFSDM2_CKOUT,
DFSDM1_CKOUT, UART4_CTS,
LCD_R3, OTG_HS_ULPI_D1,
OCTOSPIM_P1_IO1, LCD_G1,
EVENTOUT
ADC12_INP9,
ADC12_INN5,
OPAMP1_VINP,
COMP1_INP
FT_ah0
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, DFSDM1_DATIN1,
LCD_R6, OTG_HS_ULPI_D2,
OCTOSPIM_P1_IO0, LCD_G0,
EVENTOUT
ADC12_INP5,
COMP1_INM
COMP1_INP
L6
P7
28
36
48
58
PB2
I/O
FT_ah1
RTC_OUT2, SAI1_D1,
DFSDM1_CKIN1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
OCTOSPIM_P1_CLK,
OCTOSPIM_P1_DQS, EVENTOUT
M6
N7
-
-
49
59
PF11
I/O
FT_ah1
SPI5_MOSI, OCTOSPIM_P1_NCLK,
SAI2_SD_B, FMC_SDNRAS,
DCMI_D12/PSSI_D12, EVENTOUT
ADC1_INP2
N6
P11
-
-
50
60
PF12
I/O
FT_ah2
OCTOSPIM_P2_DQS, FMC_A6,
EVENTOUT
ADC1_INP6,
ADC1_INN2
-
F10
-
-
51
61
VSS
S
-
-
-
-
L12
-
-
52
62
VDD
S
-
-
ADC2_INP2
G7
N11
-
-
53
63
PF13
I/O
FT_ah2
DFSDM1_DATIN6, I2C4_SMBA,
FMC_A7, EVENTOUT
H7
R10
-
-
54
64
PF14
I/O
FT_fah2
DFSDM1_CKIN6, I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INP6,
ADC2_INN2
J7
N10
-
-
55
65
PF15
I/O
FT_fh2
I2C4_SDA, FMC_A9, EVENTOUT
-
PG0
I/O
FT_h2
OCTOSPIM_P2_IO4, UART9_RX,
FMC_A10, EVENTOUT
-
VSS
S
-
-
-
-
VDD
S
-
-
-
57
67
PG1
I/O
FT_h2
OCTOSPIM_P2_IO5, UART9_TX,
FMC_A11, EVENTOUT
OPAMP2_VINM
37
58
68
PE7
I/O
FT_ah2
TIM1_ETR, DFSDM1_DATIN2,
UART7_Rx, OCTOSPIM_P1_IO4,
FMC_D4/FMC_DA4, EVENTOUT
OPAMP2_VOUT,
COMP2_INM
-
38
59
69
PE8
I/O
FT_ah2
TIM1_CH1N, DFSDM1_CKIN2,
UART7_Tx, OCTOSPIM_P1_IO5,
FMC_D5/FMC_DA5, COMP2_OUT,
EVENTOUT
OPAMP2_VINM
R11
-
39
60
70
PE9
I/O
FT_ah2
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS, OCTOSPIM_P1_IO6,
FMC_D6/FMC_DA6, EVENTOUT
OPAMP2_VINP,
COMP2_INP
M11
G6
-
-
61
71
VSS
S
-
-
-
N11
M9
-
-
62
72
VDD
S
-
-
COMP2_INM
COMP2_INP
K7
P8
-
-
56
66
-
F12
-
-
-
-
M5
-
-
-
L7
N9
-
-
G8
P9
-
H8
N8
J8
M8
R9
-
40
63
73
PE10
I/O
FT_ah2
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS, OCTOSPIM_P1_IO7,
FMC_D7/FMC_DA7, EVENTOUT
N8
R12
-
41
64
74
PE11
I/O
FT_ah2
TIM1_CH2, DFSDM1_CKIN4, SPI4_SS,
SAI2_SD_B, OCTOSPIM_P1_NCS,
FMC_D8/FMC_DA8, LCD_G3,
EVENTOUT
DS13196 - Rev 7
page 45/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
L8
P12
-
42
65
75
PE12
I/O
FT_h2
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK, SAI2_SCK_B, FMC_D9/
FMC_DA9, COMP1_OUT, LCD_B4,
EVENTOUT
-
K8
P13
-
43
66
76
PE13
I/O
FT_h2
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B, FMC_D10/
FMC_DA10, COMP2_OUT, LCD_DE,
EVENTOUT
-
J9
M12
-
44
67
77
PE14
I/O
FT_h2
TIM1_CH4, SPI4_MOSI, SAI2_MCK_B,
FMC_D11/FMC_DA11, LCD_CLK,
EVENTOUT
-
N9
P14
-
45
68
78
PE15
I/O
FT_h2
TIM1_BKIN, USART10_CK, FMC_D12/
FMC_DA12, TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
-
-
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
L9
N12
29
46
69
79
PB10
I/O
FT_f
TIM2_CH3, LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK, DFSDM1_DATIN7,
USART3_TX, OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3, LCD_G4,
EVENTOUT
M9
P10
-
47
70
80
PB11
I/O
FT_f
TIM2_CH4, LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX,
OTG_HS_ULPI_D4, LCD_G5,
EVENTOUT
-
N10
R13
30
48
71
81
VCAP
S
-
-
-
-
M10
31
49
-
-
VSS
S
-
-
-
M10
R14
-
-
-
-
VDDLDO
S
-
-
-
-
-
32
50
72
82
VDD
S
-
-
-
-
P15
-
-
-
83
PH6
I/O
FT
TIM12_CH1, I2C2_SMBA, SPI5_SCK,
FMC_SDNE1, DCMI_D8/PSSI_D8,
EVENTOUT
-
-
M11
-
-
-
84
PH7
I/O
FT_f
I2C3_SCL, SPI5_MISO, FMC_SDCKE1,
DCMI_D9/PSSI_D9, EVENTOUT
-
-
N13
-
-
-
85
PH8
I/O
FT_fh2
TIM5_ETR, I2C3_SDA, FMC_D16,
DCMI_HSYNC/PSSI_DE, LCD_R2,
EVENTOUT
-
-
M14
-
-
-
86
PH9
I/O
FT_h2
TIM12_CH2, I2C3_SMBA, FMC_D17,
DCMI_D0/PSSI_D0, LCD_R3,
EVENTOUT
-
K9
N14
-
-
-
87
PH10
I/O
FT_h2
TIM5_CH1, I2C4_SMBA, FMC_D18,
DCMI_D1/PSSI_D1, LCD_R4,
EVENTOUT
-
L10
M13
-
-
-
88
PH11
I/O
FT_fh2
TIM5_CH2, I2C4_SCL, FMC_D19,
DCMI_D2/PSSI_D2, LCD_R5,
EVENTOUT
-
K10
N15
-
-
-
89
PH12
I/O
FT_fh2
TIM5_CH3, I2C4_SDA, FMC_D20,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
-
L12
G10
-
-
-
90
VSS
S
-
-
-
L13
-
-
-
-
91
VDD
S
-
-
-
FT_h1
TIM1_BKIN, OCTOSPIM_P1_NCLK,
I2C2_SMBA, SPI2_SS/
I2S2_WS, DFSDM1_DATIN1,
USART3_CK, FDCAN2_RX,
OTG_HS_ULPI_D5, DFSDM2_DATIN1,
TIM1_BKIN_COMP12, UART5_RX,
EVENTOUT
-
N12
M15
DS13196 - Rev 7
33
51
73
92
PB12
I/O
page 46/205
STM32H7B0xB
Pin descriptions
L11
N13
L15
K15
34
35
52
53
74
75
LQFP176
LQFP144
LQFP100
LQFP64
UFBGA176+25 with SMPS
UFBGA169 with SMPS
Pin/ball name(1) (2)
93
94
Pin name
(function after
reset)
PB13
PB14
Pin type
I/O
I/O
I/O
structure
Alternate functions
Additional functions
FT_h0
TIM1_CH1N, LPTIM2_OUT,
DFSDM2_CKIN1, SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1, USART3_CTS/
USART3_NSS, FDCAN2_TX,
OTG_HS_ULPI_D6, SDMMC1_D0,
DCMI_D2/PSSI_D2, UART5_TX,
EVENTOUT
-
FT_h0
TIM1_CH2N, TIM12_CH1, TIM8_CH2N,
USART1_TX, SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2, USART3_RTS,
UART4_RTS, SDMMC2_D0, LCD_CLK,
EVENTOUT
-
-
M13
K14
36
54
76
95
PB15
I/O
FT_h0
RTC_REFIN, TIM1_CH3N, TIM12_CH2,
TIM8_CH3N, USART1_RX, SPI2_MOSI/
I2S2_SDO, DFSDM1_CKIN2,
UART4_CTS, SDMMC2_D1, LCD_G7,
EVENTOUT
M12
L14
-
55
77
96
PD8
I/O
FT_h2
DFSDM1_CKIN3, USART3_TX,
SPDIFRX1_IN1, FMC_D13/FMC_DA13,
EVENTOUT
-
K11
K13
-
56
78
97
PD9
I/O
FT_h2
DFSDM1_DATIN3, USART3_RX,
FMC_D14/FMC_DA14, EVENTOUT
-
K12
L13
-
57
79
98
PD10
I/O
FT_h2
DFSDM1_CKOUT, DFSDM2_CKOUT,
USART3_CK, FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
-
H6
-
-
-
-
VSS
S
-
-
-
J10
J13
-
58
80
99
PD11
I/O
FT_h2
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
OCTOSPIM_P1_IO0, SAI2_SD_A,
FMC_A16/FMC_CLE, EVENTOUT
-
-
K13
J15
-
59
81
100
PD12
I/O
FT_fh2
LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,
I2C4_SCL, USART3_RTS,
OCTOSPIM_P1_IO1, SAI2_FS_A,
FMC_A17/FMC_ALE, DCMI_D12/
PSSI_D12, EVENTOUT
J11
H15
-
60
82
101
PD13
I/O
FT_fh2
LPTIM1_OUT, TIM4_CH2, I2C4_SDA,
OCTOSPIM_P1_IO3, SAI2_SCK_A,
UART9_RTS, FMC_A18, DCMI_D13/
PSSI_D13, EVENTOUT
-
H12
R1
-
-
83
102
VSS
S
-
-
-
H13
-
-
-
84
103
VDD
S
-
-
-
J13
H14
-
61
85
104
PD14
I/O
FT_h2
TIM4_CH3, UART8_CTS, UART9_RX,
FMC_D0/FMC_DA0, EVENTOUT
-
J12
J12
-
62
86
105
PD15
I/O
FT_h2
TIM4_CH4, UART8_RTS, UART9_TX,
FMC_D1/FMC_DA1, EVENTOUT
-
-
D6
-
-
-
-
VSS
S
-
-
-
-
G7
-
-
-
-
VSS
S
-
-
-
H9
G15
-
-
87
106
PG2
I/O
FT_h2
TIM8_BKIN, TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
H10
H13
-
-
88
107
PG3
I/O
FT_h2
TIM8_BKIN2, TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
C12
H10
-
-
-
-
VSS
S
-
-
-
C13
-
-
-
-
-
VDD
S
-
-
-
FT_h2
TIM1_BKIN2, TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0, EVENTOUT
-
F8
G14
DS13196 - Rev 7
-
-
89
108
PG4
I/O
page 47/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
H11
F15
-
-
90
109
PG5
I/O
FT_h2
TIM1_ETR, FMC_A15/FMC_BA1,
EVENTOUT
-
G9
F14
-
-
91
110
PG6
I/O
FT_h2
TIM17_BKIN, OCTOSPIM_P1_NCS,
FMC_NE3, DCMI_D12/PSSI_D12,
LCD_R7, EVENTOUT
-
G10
G13
-
-
92
111
PG7
I/O
FT_h2
SAI1_MCLK_A, USART6_CK,
OCTOSPIM_P2_DQS, FMC_INT,
DCMI_D13/PSSI_D13, LCD_CLK,
EVENTOUT
-
G11
G12
-
-
93
112
PG8
I/O
FT_h2
TIM8_ETR, SPI6_SS/I2S6_WS,
USART6_RTS, SPDIFRX1_IN2,
FMC_SDCLK, LCD_G7, EVENTOUT
-
-
J6
-
-
94
113
VSS
S
-
-
-
G12
E15
-
-
-
-
VDD50USB
S
-
-
-
G13
F13
-
-
95
114
VDD33USB
S
-
-
-
FT_h0
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX, SDMMC1_D0DIR,
FMC_NWAIT, SDMMC2_D6,
SDMMC1_D6, DCMI_D0/PSSI_D0,
LCD_HSYNC, EVENTOUT
SWPMI_IO
FT_h0
TRGIO, TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX, SDMMC1_D123DIR,
FMC_NE1, SDMMC2_D7, SWPMI_TX,
SDMMC1_D7, DCMI_D1/PSSI_D1,
LCD_G6, EVENTOUT
-
FT_h0
TRACED1, TIM3_CH3, TIM8_CH3,
USART6_CK, UART5_RTS, FMC_NE2/
FMC_NCE, FMC_INT, SWPMI_RX,
SDMMC1_D0, DCMI_D2/PSSI_D2,
EVENTOUT
-
-
F9
F10
F12
E14
D15
D14
37
38
-
63
64
65
96
97
98
115
116
117
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
PC6
PC7
PC8
I/O
I/O
I/O
F11
E13
39
66
99
118
PC9
I/O
FT_fh0
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN, UART5_CTS,
OCTOSPIM_P1_IO0, LCD_G3,
SWPMI_SUSPEND, SDMMC1_D1,
DCMI_D3/PSSI_D3, LCD_B2,
EVENTOUT
-
J7
-
-
-
-
VSS
S
-
-
-
-
E12
B14
40
67
100
119
PA8
I/O
FT_fh0
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL, USART1_CK,
OTG_HS_SOF, UART7_RX,
TIM8_BKIN2_COMP12, LCD_B3,
LCD_R6, EVENTOUT
E11
D13
41
68
101
120
PA9
I/O
FT_u
TIM1_CH2, LPUART1_TX, I2C3_SMBA,
SPI2_SCK/I2S2_CK, USART1_TX,
DCMI_D0/PSSI_D0, LCD_R5,
EVENTOUT
OTG_HS_VBUS
E10
C14
42
69
102
121
PA10
I/O
FT_u
TIM1_CH3, LPUART1_RX,
USART1_RX, OTG_HS_ID,
MDIOS_MDIO, LCD_B4, DCMI_D1/
PSSI_D1, LCD_B1, EVENTOUT
-
F13
C15
43
70
103
122
PA11
I/O
FT_u
TIM1_CH4, LPUART1_CTS, SPI2_SS/
I2S2_WS, UART4_RX, USART1_CTS/
USART1_NSS, FDCAN1_RX, LCD_R4,
EVENTOUT
OTG_HS_DM
DS13196 - Rev 7
page 48/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
E13
B15
44
71
104
123
PA12
I/O
FT_u
TIM1_ETR, LPUART1_RTS, SPI2_SCK/
I2S2_CK, UART4_TX, USART1_RTS,
SAI2_FS_B, FDCAN1_TX, LCD_R5,
EVENTOUT
OTG_HS_DP
D11
B13
45
72
105
124
PA13(JTMS/
SWDIO)
I/O
FT
JTMS/SWDIO, EVENTOUT
-
D13
A14
46
73
106
125
VCAP
S
-
-
-
B10
M6
47
74
107
126
VSS
S
-
-
-
D12
A13
-
-
-
-
VDDLDO
S
-
-
-
A10
-
48
75
108
127
VDD
S
-
-
-
B13
C13
-
-
-
128
PH13
I/O
FT_h2
TIM8_CH1N, UART4_TX, FDCAN1_TX,
FMC_D21, LCD_G2, EVENTOUT
-
A13
B12
-
-
-
129
PH14
I/O
FT_h2
TIM8_CH2N, UART4_RX, FDCAN1_RX,
FMC_D22, DCMI_D4/PSSI_D4,
LCD_G3, EVENTOUT
-
-
D12
-
-
-
130
PH15
I/O
FT_h2
TIM8_CH3N, FMC_D23, DCMI_D11/
PSSI_D11, LCD_G4, EVENTOUT
-
-
-
-
-
-
131
PI0
I/O
FT_h2
TIM5_CH4, SPI2_SS/I2S2_WS,
FMC_D24, DCMI_D13/PSSI_D13,
LCD_G5, EVENTOUT
-
-
J9
-
-
-
-
VSS
S
-
-
-
-
-
-
-
-
132
PI1
I/O
FT_h2
TIM8_BKIN2, SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12, FMC_D25,
DCMI_D8/PSSI_D8, LCD_G6,
EVENTOUT
-
-
-
-
-
-
133
PI2
I/O
FT_h2
TIM8_CH4, SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9/PSSI_D9,
LCD_G7, EVENTOUT
-
-
-
-
-
-
134
PI3
I/O
FT_h2
TIM8_ETR, SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10/PSSI_D10,
EVENTOUT
-
-
J10
-
-
-
135
VSS
S
-
-
-
-
-
-
-
-
136
VDD
S
-
-
-
137
PA14(JTCK/
SWCLK)
I/O
FT
JTCK/SWCLK, EVENTOUT
-
FT
JTDI, TIM2_CH1/TIM2_ETR,
HDMI_CEC, SPI1_SS/I2S1_WS,
SPI3_SS/I2S3_WS, SPI6_SS/I2S6_WS,
UART4_RTS, LCD_R3, UART7_TX,
LCD_B6, EVENTOUT
-
FT_h0
DFSDM1_CKIN5, DFSDM2_CKIN0,
SPI3_SCK/I2S3_CK, USART3_TX,
UART4_TX, OCTOSPIM_P1_IO1,
LCD_B1, SWPMI_RX, SDMMC1_D2,
DCMI_D8/PSSI_D8, LCD_R2,
EVENTOUT
-
FT_h0
DFSDM1_DATIN5, DFSDM2_DATIN0,
SPI3_MISO/I2S3_SDI, USART3_RX,
UART4_RX, OCTOSPIM_P1_NCS,
SDMMC1_D3, DCMI_D4/PSSI_D4,
LCD_B4, EVENTOUT
-
FT_h0
TRACED3, TIM15_CH1,
DFSDM2_CKOUT, SPI6_SCK/I2S6_CK,
SPI3_MOSI/I2S3_SDO, USART3_CK,
UART5_TX, SDMMC1_CK, DCMI_D9/
PSSI_D9, LCD_R6, EVENTOUT
-
B12
C11
A12
B11
A11
A12
A11
C12
C11
B11
DS13196 - Rev 7
49
50
51
52
53
76
77
78
79
80
109
110
111
112
113
138
139
140
141
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
PA15(JTDI)
PC10
PC11
PC12
I/O
I/O
I/O
I/O
page 49/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
-
J14
-
-
-
-
VSS
S
-
-
-
D10
C10
-
81
114
142
PD0
I/O
FT_h2
DFSDM1_CKIN6, UART4_RX,
FDCAN1_RX, UART9_CTS, FMC_D2/
FMC_DA2, LCD_B1, EVENTOUT
-
C10
A10
-
82
115
143
PD1
I/O
FT_h2
DFSDM1_DATIN6, UART4_TX,
FDCAN1_TX, FMC_D3/FMC_DA3,
EVENTOUT
-
E9
B10
54
83
116
144
PD2
I/O
FT_h0
TRACED2, TIM3_ETR, TIM15_BKIN,
UART5_RX, LCD_B7, SDMMC1_CMD,
DCMI_D11/PSSI_D11, LCD_B2,
EVENTOUT
-
D9
A9
-
84
117
145
PD3
I/O
FT_h2
DFSDM1_CKOUT, SPI2_SCK/
I2S2_CK, USART2_CTS/USART2_NSS,
FMC_CLK, DCMI_D5/PSSI_D5,
LCD_G7, EVENTOUT
-
C9
C9
-
85
118
146
PD4
I/O
FT_h1
USART2_RTS, OCTOSPIM_P1_IO4,
FMC_NOE, EVENTOUT
-
A9
B9
-
86
119
147
PD5
I/O
FT_h1
USART2_TX, OCTOSPIM_P1_IO5,
FMC_NWE, EVENTOUT
-
-
K2
-
-
120
148
VSS
S
-
-
-
-
-
-
-
121
149
VDDMMC
S
-
-
-
-
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
B9
D9
-
87
122
150
PD6
I/O
FT_sh3
SAI1_D1, DFSDM1_CKIN4,
DFSDM1_DATIN1, SPI3_MOSI/
I2S3_SDO, SAI1_SD_A, USART2_RX,
OCTOSPIM_P1_IO6, SDMMC2_CK,
FMC_NWAIT, DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
D8
B8
-
88
123
151
PD7
I/O
FT_sh3
DFSDM1_DATIN4, SPI1_MOSI/
I2S1_SDO, DFSDM1_CKIN1,
USART2_CK, SPDIFRX1_IN0,
OCTOSPIM_P1_IO7, SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
-
K6
-
-
-
-
VSS
S
-
-
-
A6
D5
-
-
-
-
VDDMMC
S
-
-
-
-
C8
A8
-
-
124
152
PG9
I/O
FT_sh3
SPI1_MISO/I2S1_SDI, USART6_RX,
SPDIFRX1_IN3, OCTOSPIM_P1_IO6,
SAI2_FS_B, SDMMC2_D0, FMC_NE2/
FMC_NCE, DCMI_VSYNC/PSSI_RDY,
EVENTOUT
A8
C8
-
-
125
153
PG10
I/O
FT_sh3
OCTOSPIM_P2_IO6, SPI1_SS/
I2S1_WS, LCD_G3, SAI2_SD_B,
SDMMC2_D1, FMC_NE3, DCMI_D2/
PSSI_D2, LCD_B2, EVENTOUT
-
FT_sh3
LPTIM1_IN2, SPI1_SCK/I2S1_CK,
SPDIFRX1_IN0, OCTOSPIM_P2_IO7,
SDMMC2_D2, USART10_RX,
DCMI_D3/PSSI_D3, LCD_B3,
EVENTOUT
-
-
-
B8
A7
-
-
126
154
PG11
I/O
E8
D8
-
-
127
155
PG12
I/O
FT_sh3
LPTIM1_IN1, OCTOSPIM_P2_NCS,
SPI6_MISO/I2S6_SDI, USART6_RTS,
SPDIFRX1_IN1, LCD_B4,
SDMMC2_D3, USART10_TX,
FMC_NE4, LCD_B1, EVENTOUT
D7
B7
-
-
128
156
PG13
I/O
FT_sh3
TRACED0, LPTIM1_OUT,
SPI6_SCK/I2S6_CK, USART6_CTS/
USART6_NSS, SDMMC2_D6,
USART10_CTS/USART10_NSS,
FMC_A24, LCD_R0, EVENTOUT
DS13196 - Rev 7
page 50/205
STM32H7B0xB
Pin descriptions
LQFP176
LQFP144
LQFP100
LQFP64
UFBGA176+25 with SMPS
UFBGA169 with SMPS
Pin/ball name(1) (2)
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
-
C7
C7
-
-
129
157
PG14
I/O
FT_sh3
TRACED1, LPTIM1_ETR,
SPI6_MOSI/I2S6_SDO, USART6_TX,
OCTOSPIM_P1_IO7, SDMMC2_D7,
USART10_RTS, FMC_A25, LCD_B0,
EVENTOUT
-
K7
-
-
130
158
VSS
S
-
-
-
-
-
-
-
131
159
VDD
S
-
-
-
-
K8
-
-
-
-
VSS
S
-
-
-
E7
D7
-
-
132
160
PG15
I/O
FT_h1
USART6_CTS/USART6_NSS,
OCTOSPIM_P2_DQS, USART10_CK,
FMC_SDNCAS, DCMI_D13/PSSI_D13,
EVENTOUT
-
161
PB3(JTDO/
TRACESWO)
FT_h0
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK/I2S1_CK, SPI3_SCK/
I2S3_CK, SPI6_SCK/I2S6_CK,
SDMMC2_D2, CRS_SYNC, UART7_RX,
EVENTOUT
-
FT_h0
NJTRST, TIM16_BKIN, TIM3_CH1,
SPI1_MISO/I2S1_SDI, SPI3_MISO/
I2S3_SDI, SPI2_SS/I2S2_WS,
SPI6_MISO/I2S6_SDI, SDMMC2_D3,
UART7_TX, EVENTOUT
-
FT_h0
TIM17_BKIN, TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO, I2C4_SMBA,
SPI3_MOSI/I2S3_SDO, SPI6_MOSI/
I2S6_SDO, FDCAN2_RX,
OTG_HS_ULPI_D7, LCD_B5,
FMC_SDCKE1, DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT
-
FT_f
TIM16_CH1N, TIM4_CH1,
I2C1_SCL, HDMI_CEC, I2C4_SCL,
USART1_TX, LPUART1_TX,
FDCAN2_TX, OCTOSPIM_P1_NCS,
DFSDM1_DATIN5, FMC_SDNE1,
DCMI_D5/PSSI_D5, UART5_TX,
EVENTOUT
-
PVD_IN
F7
B6
C6
A5
A6
B6
C6
A5
55
56
57
58
89
90
91
92
133
134
135
136
162
163
164
PB4(NJTRST)
PB5
PB6
I/O
I/O
I/O
I/O
D6
B5
59
93
137
165
PB7
I/O
FT_fa
TIM17_CH1N, TIM4_CH2,
I2C1_SDA, I2C4_SDA, USART1_RX,
LPUART1_RX, DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC/PSSI_RDY,
EVENTOUT
E6
C5
60
94
138
166
BOOT0
I
B
-
VPP
FT_fsh3
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4, SDMMC1_D4, DCMI_D6/
PSSI_D6, LCD_B6, EVENTOUT
-
-
-
B5
A2
61
95
139
167
PB8
I/O
C5
B3
62
96
140
168
PB9
I/O
FT_fsh3
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA,
SPI2_SS/I2S2_WS, I2C4_SDA,
SDMMC1_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5, DCMI_D7/
PSSI_D7, LCD_B7, EVENTOUT
D5
B4
-
97
141
169
PE0
I/O
FT_h2
LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
SAI2_MCK_A, FMC_NBL0, DCMI_D2/
PSSI_D2, LCD_R0, EVENTOUT
DS13196 - Rev 7
page 51/205
STM32H7B0xB
Pin descriptions
UFBGA169 with SMPS
UFBGA176+25 with SMPS
LQFP64
LQFP100
LQFP144
LQFP176
Pin/ball name(1) (2)
D4
C4
-
98
142
170
PE1
I/O
FT_h2
LPTIM1_IN2, UART8_TX, FMC_NBL1,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
-
A4
A4
-
-
-
-
VCAP
S
-
-
-
Pin name
(function after
reset)
Pin type
I/O
structure
Alternate functions
Additional functions
-
K10
63
99
-
-
VSS
S
-
-
-
C4
D4
-
-
143
171
PDR_ON
S
-
-
-
B4
A3
-
-
-
-
VDDLDO
S
-
-
-
-
-
64
100
144
172
VDD
S
-
-
-
-
-
-
-
-
173
PI4
I/O
FT_h2
TIM8_BKIN, SAI2_MCK_A,
TIM8_BKIN_COMP12, FMC_NBL2,
DCMI_D5/PSSI_D5, LCD_B4,
EVENTOUT
-
-
-
-
-
-
174
PI5
I/O
FT_h2
TIM8_CH1, SAI2_SCK_A, FMC_NBL3,
DCMI_VSYNC/PSSI_RDY, LCD_B5,
EVENTOUT
-
-
-
-
-
-
175
PI6
I/O
FT_h2
TIM8_CH2, SAI2_SD_A, FMC_D28,
DCMI_D6/PSSI_D6, LCD_B6,
EVENTOUT
-
-
-
-
-
-
176
PI7
I/O
FT_h2
TIM8_CH3, SAI2_FS_A, FMC_D29,
DCMI_D7/PSSI_D7, LCD_B7,
EVENTOUT
-
-
K12
-
-
-
-
VSS
S
-
-
-
-
G8
-
-
-
-
VSS
S
-
-
-
-
G9
-
-
-
-
VSS
S
-
-
-
-
H7
-
-
-
-
VSS
S
-
-
-
-
H8
-
-
-
-
VSS
S
-
-
-
-
H9
-
-
-
-
VSS
S
-
-
-
-
J8
-
-
-
-
VSS
S
-
-
-
-
K9
-
-
-
-
VSS
S
-
-
-
-
R15
-
-
-
-
VSS
S
-
-
-
1. The devices with SMPS correspond to commercial code STM32H7B0xIxxQ.
2. A non-connected I/O in a given package is configured as an output tied to VSS. Any analog peripheral connected to such a pad (such as
OPAMP, VREF+) must be disabled.
3. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer
to the product reference manual for a detailed description of the switch configuration bits.
4. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when
the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a
detailed description of the switch configuration bits.
DS13196 - Rev 7
page 52/205
DS13196 - Rev 7
Table 8. Port A alternate functions
AF0
Port
SYS
AF1
LPTIM1/
TIM1/2/16/17
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
DFSDM1/2/
I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/
SPI2/I2S2/
SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/
LCD/
OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/
TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/OTG1_HS/
SAI2/SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/
TIM1/8/
UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/
TIM1
LCD/UART5
SYS
UART4_TX
SDMMC2_CMD
SAI2_SD_B
-
-
-
-
EVENTOUT
-
-
LCD_R2
EVENTOUT
-
MDIOS_MDIO
-
LCD_R1
EVENTOUT
-
-
-
LCD_B5
EVENTOUT
-
-
DCMI_HSYNC/
PSSI_DE
USART2_
PA0
TIM2_CH1/
-
SPI6_SS/
TIM5_CH1
TIM8_ETR
TIM15_BKIN
TIM2_ETR
CTS/
-
I2S6_WS
USART2_
NSS
USART2_
PA1
-
TIM2_CH2
TIM5_CH2
LPTIM3_OUT
TIM15_CH1N
-
-
OCTOSPIM_
UART4_RX
RTS
PA2
-
TIM2_CH3
TIM5_CH3
-
TIM15_CH1
DFSDM2_
USART2_
CKIN1
TX
-
OCTOSPIM_
PA3
-
TIM2_CH4
TIM5_CH4
PA4
-
-
TIM5_ETR
-
PWR_NDSTOP2
I2S6_MCK
-
TIM8_CH1N
-
TIM1_BKIN
TIM8_BKIN
-
Port A
DFSDM2_
PA7
-
TIM1_CH1N
USART2_
SPI6_SS/
I2S3_WS
CK
I2S6_WS
-
-
-
SPI6_SCK/
TIM3_CH2
TIM8_CH1N
DATIN1
P1_IO3
SPI1_MOSI/
I2S1_SDO
-
-
-
-
MCO1
TIM1_CH1
-
TIM8_BKIN2
I2C3_SCL
SPI2_SCK/
-
TIM1_CH2
-
LPUART1_TX
I2C3_SMBA
SPI6_MISO/
I2S6_SDI
TIM13_CH1
SPI6_MOSI/
I2S6_SDO
TIM14_CH1
-
-
-
TIM1_CH3
-
LPUART1_RX
-
-
TIM8_BKIN_COMP12
-
PSSI_D14
TIM1_BKIN_
DCMI_PIXCLK/
COMP12
PSSI_PDCK
OCTOSPIM_P1_IO2
-
FMC_SDNWE
EVENTOUT
LCD_G2
EVENTOUT
-
LCD_VSYNC
EVENTOUT
LCD_B3
LCD_R6
EVENTOUT
LCD_R5
EVENTOUT
LCD_B1
EVENTOUT
TIM8_BKIN2_
UART7_RX
SOF
COMP12
DCMI_D0/
-
-
-
-
-
TX
-
LCD_R4
MDIOS_MDC
OTG_HS_
PSSI_D0
USART1_
PA10
-
USART1_
-
I2S2_CK
EVENTOUT
ULPI_CK
CK
PA9
LCD_
VSYNC
OTG_HS_
USART1_
PA8
-
I2S6_CK
OCTOSPIM_
-
ULPI_D0
SPI3_SS/
SPI1_MISO/
I2S1_SDI
P1_DQS
OTG_HS_
I2S1_WS
I2S1_CK
TIM3_CH1
LCD_B2
SPI1_SS/
-
TIM2_ETR
PA6
-
-
SPI1_SCK/
-
-
RX
TIM2_CH1/
PA5
SAI2_SCK_B
USART2_
TIM15_CH2
P1_CLK
OCTOSPIM_
SAI2_MCK_B
P1_IO3
OTG_HS_
-
-
RX
DCMI_D1/
MDIOS_MDIO
LCD_B4
ID
PSSI_D1
USART1_
SPI2_SS/
PA11
-
TIM1_CH4
-
LPUART1_CTS
-
FDCAN1_
UART4_RX
CTS/
-
I2S2_WS
-
-
-
-
LCD_R4
EVENTOUT
-
-
-
-
LCD_R5
EVENTOUT
RX
USART1_NSS
SPI2_SCK/
PA12
-
TIM1_ETR
-
LPUART1_RTS
-
USART1_
UART4_TX
FDCAN1_
SAI2_FS_B
RTS
TX
JTMS/
PA13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
SPI1_SS/
SPI3_SS/
SPI6_SS/
UART4_
-
-
HDMI_CEC
LCD_R3
-
UART7_TX
-
-
LCD_B6
EVENTOUT
I2S1_WS
I2S3_WS
I2S6_WS
RTS
SWDIO
JTCK/
PA14
page 53/205
SWCLK
TIM2_CH1/
PA15
JTDI
TIM2_ETR
STM32H7B0xB
I2S2_CK
DS13196 - Rev 7
Table 9. Port B alternate functions
AF0
AF2
AF3
AF4
AF5
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/TIM15/
USART1
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
DFSDM2_CKOUT
-
Port
PB0
AF1
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/SPI2/
I2S2/SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/LC
D/OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/
SAI2/SDMMC2/
TIM8
DFSDM1/2/
I2C4/LCD/MDIOS/
OCTOSPIM_P1/
SDMMC2/SWPMI1/
TIM1/8/UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/TIM1
LCD/
UART5
SYS
DFSDM1_CKOUT
-
UART4_CTS
LCD_R3
OCTOSPIM_P1_IO1
-
-
LCD_G1
EVENTOUT
-
-
LCD_G0
EVENTOUT
-
-
-
-
EVENTOUT
OTG_HS_
ULPI_D1
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
-
-
DFSDM1_DATIN1
-
-
SPI3_MOSI/
PB2
RTC_OUT2
-
SAI1_D1
-
DFSDM1_CKIN1
-
SAI1_SD_A
JTDO/
SPI1_SCK/
TIM2_CH2
-
-
OCTOSPIM_P1_CLK
PB4
NJTRST
TIM16_BKIN
TIM3_CH1
-
SPI1_MISO/
SPI3_MISO/
SPI2_SS/
SPI6_MISO/
I2S1_SDI
I2S3_SDI
I2S2_WS
I2S6_SDI
-
TIM17_BKIN
TIM3_CH2
-
SPI3_MOSI/
SPI6_MOSI/
I2S3_SDO
I2S6_SDO
USART1_TX
LPUART1_TX
I2C1_SMBA
I2C4_SMBA
I2S1_SDO
SDMMC2_D2
CRS_SYNC
UART7_RX
-
-
-
EVENTOUT
SDMMC2_D3
-
UART7_TX
-
-
-
EVENTOUT
LCD_B5
FMC_SDCKE1
DCMI_D10/
PSSI_D10
UART5_RX
EVENTOUT
DFSDM1_DATIN5
FMC_SDNE1
DCMI_D5/PSSI_D5
UART5_TX
EVENTOUT
I2S6_CK
-
SPI1_MOSI/
PB5
SPI6_SCK/
-
I2S1_CK
P1_IO0
P1_DQS
SPI3_SCK/
I2S3_CK
-
TRACESWO
OCTOSPIM_
ULPI_D2
OCTOSPIM_
I2S3_SDO
PB3
OTG_HS_
LCD_R6
OTG_HS_
FDCAN2_RX
ULPI_D7
OCTOSPIM_
PB6
-
TIM16_CH1N
TIM4_CH1
-
I2C1_SCL
HDMI_CEC
I2C4_SCL
FDCAN2_TX
Port B
P1_NCS
PB7
-
TIM17_CH1N
TIM4_CH2
-
I2C1_SDA
PB8
-
TIM16_CH1
TIM4_CH3
DFSDM1_CKIN7
I2C1_SCL
-
I2C4_SDA
USART1_RX
LPUART1_RX
-
-
DFSDM1_CKIN5
FMC_NL
DCMI_VSYNC/
PSSI_RDY
-
EVENTOUT
-
I2C4_SCL
SDMMC1_CKIN
UART4_RX
FDCAN1_RX
SDMMC2_D4
-
SDMMC1_D4
DCMI_D6/PSSI_D6
LCD_B6
EVENTOUT
I2C4_SDA
SDMMC1_CDIR
UART4_TX
FDCAN1_TX
SDMMC2_D5
I2C4_SMBA
SDMMC1_D5
DCMI_D7/PSSI_D7
LCD_B7
EVENTOUT
OCTOSPIM_
OTG_HS_
DFSDM1_DATIN7
USART3_TX
-
-
-
-
LCD_G4
EVENTOUT
P1_NCS
ULPI_D3
-
-
-
LCD_G5
EVENTOUT
DFSDM2_DATIN1
-
TIM1_BKIN_COMP12
UART5_RX
EVENTOUT
-
SDMMC1_D0
DCMI_D2/PSSI_D2
UART5_TX
EVENTOUT
SPI2_SS/
PB9
-
TIM17_CH1
TIM4_CH4
DFSDM1_DATIN7
I2C1_SDA
I2S2_WS
SPI2_SCK/
PB10
-
TIM2_CH3
-
LPTIM2_IN1
I2C2_SCL
I2S2_CK
OTG_HS_
PB11
-
TIM2_CH4
-
LPTIM2_ETR
I2C2_SDA
-
DFSDM1_CKIN7
USART3_RX
-
ULPI_D4
OCTOSPIM_
PB12
-
TIM1_BKIN
-
I2C2_SMBA
P1_NCLK
SPI2_SS/
I2S2_WS
OTG_HS_
DFSDM1_DATIN1
-
TIM1_CH1N
-
LPTIM2_OUT
DFSDM2_CKIN1
-
FDCAN2_RX
ULPI_D5
SPI2_SCK/
PB13
USART3_CK
USART3_CTS/
DFSDM1_CKIN1
I2S2_CK
OTG_HS_
-
FDCAN2_TX
USART3_NSS
ULPI_D6
SPI2_MISO/
PB14
-
TIM1_CH2N
TIM12_CH1
TIM8_CH2N
USART1_TX
DFSDM1_DATIN2
USART3_RTS
UART4_RTS
SDMMC2_D0
-
-
-
-
LCD_CLK
EVENTOUT
DFSDM1_CKIN2
-
UART4_CTS
SDMMC2_D1
-
-
-
-
LCD_G7
EVENTOUT
I2S2_SDI
SPI2_MOSI/
PB15
RTC_REFIN
TIM1_CH3N
TIM12_CH2
TIM8_CH3N
USART1_RX
I2S2_SDO
STM32H7B0xB
page 54/205
DS13196 - Rev 7
Table 10. Port C alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/TIM15/
USART1
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/
SPI2/I2S2/
SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/SDMMC1/
SPDIFRX1/SPI6/
I2S6/UART4/5/8
FDCAN1/2/FMC/LCD
/OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/TIM13/14
-
-
-
DFSDM1_CKIN0
-
-
DFSDM1_DATIN4
-
SAI2_FS_B
FMC_A25
Port
PC0
AF1
AF10
AF11
AF12
AF13
AF14
AF15
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/
SAI2/SDMMC2/
TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/
TIM1/8/
UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/
TIM1
LCD/UART5
SYS
LCD_G2
FMC_SDNWE
-
LCD_R5
EVENTOUT
-
MDIOS_MDC
-
LCD_G5
EVENTOUT
FMC_SDNE0
-
-
EVENTOUT
FMC_SDCKE0
-
-
EVENTOUT
OTG_HS_
ULPI_STP
PC1
PC2
PC3
PC4
TRACED0
PWR_CSTOP
PWR_CSLEEP
-
-
-
-
-
SAI1_D1
-
-
-
DFSDM1_DATIN0
DFSDM1_CKIN1
DFSDM1_DATIN1
DFSDM1_CKIN2
DFSDM1_CKIN4
-
-
-
OCTOSPIM_
SPI2_MOSI/
I2S2_SDO
SAI1_SD_A
SPI2_MISO/
I2S2_SDI
DFSDM1_CKOUT
SPI2_MOSI/
I2S2_SDO
-
I2S1_MCK
-
-
-
SDMMC2_CK
P1_IO4
-
-
-
-
-
-
OTG_HS_
OCTOSPIM_
ULPI_DIR
P1_IO5
OCTOSPIM_P1_IO2
OTG_HS_
OCTOSPIM_
ULPI_NXT
P1_IO6
-
-
FMC_SDNE0
-
LCD_R7
EVENTOUT
-
FMC_SDCKE0
COMP1_OUT
LCD_DE
EVENTOUT
-
SDMMC1_D6
LCD_HSYNC
EVENTOUT
LCD_G6
EVENTOUT
-
EVENTOUT
LCD_B2
EVENTOUT
LCD_R2
EVENTOUT
LCD_B4
EVENTOUT
LCD_R6
EVENTOUT
OCTOSPIM_P1_IO0
SPDIFRX1_IN2
OCTOSPIM_
PC5
-
-
SAI1_D3
DFSDM1_DATIN2
PSSI_D15
-
-
-
-
SPDIFRX1_IN3
P1_DQS
DCMI_D0/
PC6
-
-
TIM3_CH1
TIM8_CH1
DFSDM1_CKIN3
I2S2_MCK
-
USART6_TX
SDMMC1_D0DIR
FMC_NWAIT
SDMMC2_D6
Port C
PSSI_D0
DCMI_D1/
PC7
TRGIO
-
TIM3_CH2
TIM8_CH2
DFSDM1_DATIN3
-
I2S3_MCK
USART6_RX
SDMMC1_D123DIR
FMC_NE1
SDMMC2_D7
SWPMI_TX
SDMMC1_D7
PSSI_D1
FMC_NE2/
PC8
TRACED1
-
TIM3_CH3
TIM8_CH3
-
-
-
USART6_CK
UART5_RTS
DCMI_D2/
FMC_INT
SWPMI_RX
SDMMC1_D0
FMC_NCE
PSSI_D2
SWPMI_
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
UART5_CTS
OCTOSPIM_P1_IO0
LCD_G3
DCMI_D3/
SDMMC1_D1
SUSPEND
PSSI_D3
SPI3_SCK/
PC10
-
-
-
DFSDM1_CKIN5
DFSDM2_CKIN0
-
DCMI_D8/
USART3_TX
UART4_TX
OCTOSPIM_P1_IO1
LCD_B1
SWPMI_RX
SDMMC1_D2
I2S3_CK
PSSI_D8
SPI3_MISO/
PC11
-
-
-
DFSDM1_DATIN5
DFSDM2_DATIN0
-
DCMI_D4/
USART3_RX
UART4_RX
OCTOSPIM_P1_NCS
-
-
SDMMC1_D3
I2S3_SDI
PC12
TRACED3
-
TIM15_CH1
-
SPI6_SCK/
SPI3_MOSI/
I2S6_CK
I2S3_SDO
DFSDM2_CKOUT
PSSI_D4
DCMI_D9/
USART3_CK
UART5_TX
-
-
-
SDMMC1_CK
PSSI_D9
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
STM32H7B0xB
page 55/205
DS13196 - Rev 7
Table 11. Port D alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/
DCMI/
PSSI/LCD/
TIM1
LCDUART5
SYS
-
LCD_B1
EVENTOUT
-
-
EVENTOUT
LCD_B2
EVENTOUT
LCD_G7
EVENTOUT
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/TIM15/
USART1
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/
SPI2/I2S2/
SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/LC
D/OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/
TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/SAI2/
SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/
TIM1/8/
UART7/9/
USART10
-
-
-
DFSDM1_CKIN6
-
-
-
-
UART4_RX
FDCAN1_RX
-
UART9_CTS
Port
PD0
AF1
FMC_D2/
FMC_DA2
FMC_D3/
PD1
-
-
-
DFSDM1_DATIN6
-
-
-
-
UART4_TX
FDCAN1_TX
-
FMC_DA3
DCMI_D11/
PD2
TRACED2
-
TIM3_ETR
-
TIM15_BKIN
-
-
-
UART5_RX
LCD_B7
-
-
SDMMC1_CMD
PSSI_D11
SPI2_SCK/
PD3
-
-
-
DFSDM1_CKOUT
-
USART2_CTS/
-
I2S2_CK
DCMI_D5/
-
-
-
-
FMC_CLK
USART2_NSS
PSSI_D5
PD4
-
-
-
-
-
-
-
USART2_RTS
-
-
OCTOSPIM_P1_IO4
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
-
-
-
-
-
USART2_TX
-
-
OCTOSPIM_P1_IO5
-
FMC_NWE
-
-
EVENTOUT
PD6
-
-
SAI1_D1
DFSDM1_CKIN4
DFSDM1_DATIN1
SAI1_SD_A
USART2_RX
-
-
OCTOSPIM_P1_IO6
SDMMC2_CK
FMC_NWAIT
LCD_B2
EVENTOUT
-
-
EVENTOUT
-
-
EVENTOUT
-
-
EVENTOUT
-
LCD_B3
EVENTOUT
-
-
EVENTOUT
-
EVENTOUT
-
EVENTOUT
-
-
EVENTOUT
-
-
EVENTOUT
SPI3_MOSI/
DCMI_D10/
I2S3_SDO
PSSI_D10
SPI1_MOSI/
PD7
-
-
-
DFSDM1_DATIN4
-
DFSDM1_CKIN1
USART2_CK
-
SPDIFRX1_IN0
OCTOSPIM_P1_IO7
SDMMC2_CMD
-
USART3_TX
-
SPDIFRX1_IN1
-
-
FMC_NE1
Port D
I2S1_SDO
FMC_D13/
PD8
-
-
-
DFSDM1_CKIN3
-
-
FMC_DA13
FMC_D14/
PD9
-
-
-
DFSDM1_DATIN3
-
-
-
USART3_RX
-
-
-
FMC_DA14
FMC_D15/
PD10
-
-
-
DFSDM1_CKOUT
DFSDM2_CKOUT
-
-
USART3_CK
-
-
-
FMC_DA15
PD11
PD12
-
-
-
LPTIM1_IN1
-
TIM4_CH1
LPTIM2_IN2
LPTIM2_IN1
I2C4_SMBA
I2C4_SCL
-
-
-
-
FMC_A16/
USART3_CTS/
USART3_NSS
-
USART3_RTS
-
OCTOSPIM_P1_IO0
SAI2_SD_A
FMC_CLE
OCTOSPIM_P1_IO1
SAI2_FS_A
FMC_A17/
DCMI_D12/
FMC_ALE
PSSI_D12
-
DCMI_D13/
PD13
-
LPTIM1_OUT
TIM4_CH2
-
I2C4_SDA
-
-
-
-
OCTOSPIM_P1_IO3
SAI2_SCK_A
UART9_RTS
FMC_A18
PSSI_D13
FMC_D0/
PD14
-
-
TIM4_CH3
-
-
-
-
-
UART8_CTS
-
-
UART9_RX
FMC_DA0
FMC_D1/
PD15
-
-
TIM4_CH4
-
-
-
-
-
UART8_RTS
-
-
UART9_TX
page 56/205
STM32H7B0xB
FMC_DA1
DS13196 - Rev 7
Table 12. Port E alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
DFSDM1/2/
I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/
SPI2/I2S2/
SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/LC
D/OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/
TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/SAI2/
SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/MDIOS/
OCTOSPIM_P1/
SDMMC2/SWPMI1/
TIM1/8/UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/TIM1
LCD/
UART5
SYS
-
-
-
UART8_Rx
-
SAI2_MCK_A
-
FMC_NBL0
LCD_R0
EVENTOUT
LCD_R6
EVENTOUT
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
-
LPTIM1_ETR
TIM4_ETR
-
LPTIM2_ETR
Port
PE0
AF1
DCMI_D2/
PSSI_D2
DCMI_D3/
PE1
-
LPTIM1_IN2
-
-
-
-
-
-
UART8_Tx
-
-
-
FMC_NBL1
PSSI_D3
PE2
TRACECLK
-
SAI1_CK1
-
-
SPI4_SCK
SAI1_MCLK_A
-
-
OCTOSPIM_P1_IO2
-
USART10_RX
FMC_A23
-
-
EVENTOUT
PE3
TRACED0
-
-
-
TIM15_BKIN
-
SAI1_SD_B
-
-
-
-
USART10_TX
FMC_A19
-
-
EVENTOUT
PE4
TRACED1
-
SAI1_D2
DFSDM1_DATIN3
TIM15_CH1N
SPI4_SS
SAI1_FS_A
-
-
-
-
-
FMC_A20
LCD_B0
EVENTOUT
LCD_G0
EVENTOUT
LCD_G1
EVENTOUT
-
-
EVENTOUT
COMP2_OUT
-
EVENTOUT
-
-
EVENTOUT
-
-
EVENTOUT
-
LCD_G3
EVENTOUT
LCD_B4
EVENTOUT
COMP2_OUT
LCD_DE
EVENTOUT
-
LCD_CLK
EVENTOUT
TIM1_BKIN_COMP12
LCD_R7
EVENTOUT
DCMI_D4/
PSSI_D4
DCMI_D6/
PE5
TRACED2
-
SAI1_CK2
DFSDM1_CKIN3
TIM15_CH1
SPI4_MISO
SAI1_SCK_A
-
-
-
-
-
FMC_A21
PSSI_D6
TIM1_BKIN2_
PE6
TRACED3
TIM1_BKIN2
SAI1_D1
-
TIM15_CH2
SPI4_MOSI
SAI1_SD_A
-
-
-
SAI2_MCK_B
DCMI_D7/
FMC_A22
COMP12
PSSI_D7
FMC_D4/
PE7
-
TIM1_ETR
-
DFSDM1_DATIN2
-
-
-
UART7_RX
-
-
OCTOSPIM_P1_IO4
-
Port E
FMC_DA4
FMC_D5/
PE8
-
TIM1_CH1N
-
DFSDM1_CKIN2
-
-
-
UART7_TX
-
-
OCTOSPIM_P1_IO5
FMC_DA5
FMC_D6/
PE9
-
TIM1_CH1
-
DFSDM1_CKOUT
-
-
-
UART7_RTS
-
-
OCTOSPIM_P1_IO6
FMC_DA6
FMC_D7/
PE10
-
TIM1_CH2N
-
DFSDM1_DATIN4
-
-
-
UART7_CTS
-
-
OCTOSPIM_P1_IO7
FMC_DA7
FMC_D8/
PE11
-
TIM1_CH2
-
DFSDM1_CKIN4
-
SPI4_SS
-
-
-
-
SAI2_SD_B
OCTOSPIM_P1_NCS
FMC_DA8
PE12
-
TIM1_CH3N
-
DFSDM1_DATIN5
-
SPI4_SCK
-
-
-
-
SAI2_SCK_B
FMC_D9/
COMP1_
FMC_DA9
OUT
-
FMC_D10/
PE13
-
TIM1_CH3
-
DFSDM1_CKIN5
-
SPI4_MISO
-
-
-
-
SAI2_FS_B
FMC_DA10
FMC_D11/
PE14
-
TIM1_CH4
-
-
SPI4_MOSI
-
-
-
-
SAI2_MCK_B
FMC_DA11
FMC_D12/
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
USART10_CK
FMC_DA12
STM32H7B0xB
page 57/205
DS13196 - Rev 7
Table 13. Port F alternate functions
AF0
Port
SYS
AF1
LPTIM1/
TIM1/2/16/17
AF2
PDM_SAI1/
TIM3/4/5/12/15
AF3
AF4
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
AF5
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/SPI4/5/
SPI6/I2S6
AF6
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
AF7
SDMMC1/SPI2/
I2S2/SPI3/
I2S3/SPI6/
I2S6/UART7/
USART1/2/3/6
AF8
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
AF9
FDCAN1/2/FMC/LCD/
OCTOSPIM_P1/2/
SDMMC2/SPDIFRX1/
TIM13/14
AF10
AF11
AF12
AF13
AF14
AF15
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/OTG1_HS/
SAI2/SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/TIM1/8/
UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/
DCMI/
PSSI/LCD/
TIM1
LCD/
UART5
SYS
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
OCTOSPIM_P2_IO0
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
OCTOSPIM_P2_IO1
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
OCTOSPIM_P2_IO2
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO3
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_CLK
-
-
FMC_A4
-
-
EVENTOUT
-
-
FMC_A5
-
-
EVENTOUT
OCTOSPIM_
PF5
-
-
-
-
-
-
-
-
-
Port F
P2_NCLK
PF6
-
TIM16_CH1
-
-
-
SPI5_SS
SAI1_SD_B
UART7_Rx
-
-
OCTOSPIM_P1_IO3
-
-
-
-
EVENTOUT
PF7
-
TIM17_CH1
-
-
-
SPI5_SCK
SAI1_MCLK_B
UART7_Tx
-
-
OCTOSPIM_P1_IO2
-
-
-
-
EVENTOUT
PF8
-
TIM16_CH1N
-
-
-
SPI5_MISO
SAI1_SCK_B
UART7_RTS
-
TIM13_CH1
OCTOSPIM_P1_IO0
-
-
-
-
EVENTOUT
PF9
-
TIM17_CH1N
-
-
-
SPI5_MOSI
SAI1_FS_B
UART7_CTS
-
TIM14_CH1
OCTOSPIM_P1_IO1
-
-
-
-
EVENTOUT
PF10
-
TIM16_BKIN
SAI1_D3
-
PSSI_D15
-
-
-
-
OCTOSPIM_P1_CLK
-
-
-
LCD_DE
EVENTOUT
-
EVENTOUT
-
EVENTOUT
DCMI_D11/
PSSI_D11
OCTOSPIM_
PF11
-
-
-
-
-
SPI5_MOSI
-
-
-
DCMI_D12/
SAI2_SD_B
-
FMC_SDNRAS
P1_NCLK
PSSI_D12
OCTOSPIM_
PF12
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
P2_DQS
PF13
-
-
-
DFSDM1_DATIN6
I2C4_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENTOUT
PF14
-
-
-
DFSDM1_CKIN6
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENTOUT
PF15
-
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENTOUT
STM32H7B0xB
page 58/205
DS13196 - Rev 7
Table 14. Port G alternate functions
AF0
Port
SYS
AF1
LPTIM1/
TIM1/2/16/17
AF2
PDM_SAI1/
TIM3/4/5/12/15
AF3
DFSDM1/LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
AF4
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
AF5
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/
SPI4/5/
SPI6/I2S6
AF6
DFSDM1/2/
I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
AF7
SDMMC1/
SPI2/I2S2/
SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
AF8
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
AF9
FDCAN1/2/FMC/LCD
/OCTOSPIM_P1/2/
SDMMC2/SPDIFRX1/
TIM13/14
AF10
AF11
AF12
AF13
AF14
AF15
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/SAI2/
SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/
TIM1/8/
UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/
TIM1
LCD/
UART5
SYS
PG0
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO4
-
UART9_RX
FMC_A10
-
-
EVENTOUT
PG1
-
-
-
-
-
-
-
-
-
OCTOSPIM_P2_IO5
-
UART9_TX
FMC_A11
-
-
EVENTOUT
PG2
-
-
-
TIM8_BKIN
-
-
-
-
-
-
-
FMC_A12
-
-
EVENTOUT
FMC_A13
-
-
EVENTOUT
-
-
EVENTOUT
-
-
EVENTOUT
LCD_R7
EVENTOUT
LCD_CLK
EVENTOUT
LCD_G7
EVENTOUT
-
EVENTOUT
LCD_B2
EVENTOUT
LCD_B3
EVENTOUT
TIM8_BKIN_
COMP12
TIM8_BKIN2_
PG3
-
-
-
TIM8_BKIN2
-
-
-
-
-
-
COMP12
PG4
-
TIM1_BKIN2
-
-
-
-
-
-
-
-
TIM1_BKIN2_
FMC_A14/
COMP12
FMC_BA0
-
FMC_A15/
PG5
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
FMC_BA1
DCMI_D12/
PG6
-
TIM17_BKIN
-
-
-
-
-
-
-
-
OCTOSPIM_P1_NCS
-
FMC_NE3
PSSI_D12
DCMI_D13/
PG7
-
-
-
-
-
-
SAI1_MCLK_A
USART6_CK
-
OCTOSPIM_P2_DQS
-
-
FMC_INT
Port G
PSSI_D13
SPI6_SS/
PG8
-
-
-
TIM8_ETR
-
-
USART6_RTS
SPDIFRX1_IN2
-
-
-
-
USART6_RX
SPDIFRX1_IN3
OCTOSPIM_P1_IO6
SAI2_FS_B
SDMMC2_D0
FMC_SDCLK
-
FMC_NE2/
DCMI_VSYNC/
FMC_NCE
PSSI_RDY
I2S6_WS
SPI1_MISO/
PG9
-
-
-
-
I2S1_SDI
SPI1_SS/
PG10
-
-
-
OCTOSPIM_P2_IO6
-
DCMI_D2/
-
-
-
LCD_G3
SAI2_SD_B
SDMMC2_D1
FMC_NE3
I2S1_WS
PSSI_D2
SPI1_SCK/
PG11
-
LPTIM1_IN2
-
-
-
DCMI_D3/
-
-
SPDIFRX1_IN0
OCTOSPIM_P2_IO7
SDMMC2_D2
USART10_RX
-
I2S1_CK
PG12
-
LPTIM1_IN1
-
OCTOSPIM_P2_NCS
-
SPI6_MISO/
I2S6_SDI
PSSI_D3
-
SPI6_SCK/
PG13
TRACED0
LPTIM1_OUT
-
-
-
USART6_RTS
SPDIFRX1_IN1
LCD_B4
SDMMC2_D3
USART6_CTS/
-
I2S6_CK
USART10_TX
-
-
LCD_B1
EVENTOUT
-
-
LCD_R0
EVENTOUT
USART10_CTS/
-
-
SDMMC2_D6
USART6_NSS
USART10_NSS
SPI6_MOSI/
PG14
TRACED1
LPTIM1_ETR
-
-
-
-
USART6_TX
-
OCTOSPIM_P1_IO7
SDMMC2_D7
USART10_RTS
-
-
LCD_B0
EVENTOUT
-
OCTOSPIM_P2_DQS
-
-
-
DCMI_D13/
PSSI_D13
-
EVENTOUT
I2S6_SDO
USART6_CTS/
PG15
-
-
-
-
-
-
USART6_NSS
STM32H7B0xB
page 59/205
DS13196 - Rev 7
Table 15. Port H alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/TIM1
LCD/
UART5
SYS
EVENTOUT
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/SPI4/5/
SPI6/I2S6
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/SPI2/
I2S2/SPI3/I2S3/
SPI6/I2S6/
UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/LCD
/OCTOSPIM_P1/2/
SDMMC2/SPDIFRX1/
TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/SAI2/
SDMMC2/TIM8
DFSDM1/2/
I2C4/LCD/
MDIOS/
OCTOSPIM_P1/
SDMMC2/
SWPMI1/TIM1/8/
UART7/9/
USART10
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/
LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PH2
-
LPTIM1_IN2
-
-
-
-
-
-
-
OCTOSPIM_P1_IO4
SAI2_SCK_B
-
FMC_SDCKE0
-
LCD_R0
EVENTOUT
PH3
-
-
-
-
-
-
-
-
-
OCTOSPIM_P1_IO5
SAI2_MCK_B
-
FMC_SDNE0
-
LCD_R1
EVENTOUT
-
-
PSSI_D14
LCD_G4
EVENTOUT
-
FMC_SDNWE
-
-
EVENTOUT
-
EVENTOUT
-
EVENTOUT
LCD_R2
EVENTOUT
LCD_R3
EVENTOUT
LCD_R4
EVENTOUT
LCD_R5
EVENTOUT
LCD_R6
EVENTOUT
LCD_G2
EVENTOUT
LCD_G3
EVENTOUT
LCD_G4
EVENTOUT
Port
OTG_HS_
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
ULPI_NXT
PH5
-
-
-
-
I2C2_SDA
SPI5_SS
-
-
-
-
-
DCMI_D8/
PH6
-
-
TIM12_CH1
-
I2C2_SMBA
SPI5_SCK
-
-
-
-
-
-
FMC_SDNE1
PSSI_D8
DCMI_D9/
PH7
-
-
-
-
I2C3_SCL
SPI5_MISO
-
-
-
-
-
-
FMC_SDCKE1
PSSI_D9
Port H
DCMI_HSYNC/
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
PSSI_DE
DCMI_D0/
PH9
-
-
TIM12_CH2
-
I2C3_SMBA
-
-
-
-
-
-
-
FMC_D17
PSSI_D0
DCMI_D1/
PH10
-
-
TIM5_CH1
-
I2C4_SMBA
-
-
-
-
-
-
-
FMC_D18
PSSI_D1
DCMI_D2/
PH11
-
-
TIM5_CH2
-
I2C4_SCL
-
-
-
-
-
-
-
FMC_D19
PSSI_D2
DCMI_D3/
PH12
-
-
TIM5_CH3
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_D20
PSSI_D3
PH13
-
-
-
TIM8_CH1N
-
-
-
-
UART4_TX
FDCAN1_TX
-
-
FMC_D21
DCMI_D4/
PH14
-
-
-
TIM8_CH2N
-
-
-
-
UART4_RX
FDCAN1_RX
-
-
FMC_D22
PSSI_D4
PH15
-
-
-
TIM8_CH3N
-
-
-
-
-
-
-
-
FMC_D23
DCMI_D11/
PSSI_D11
STM32H7B0xB
page 60/205
DS13196 - Rev 7
Table 16. Port I alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/SPI1/
I2S1/SPI2/
I2S2/SPI3/
I2S3/SPI4/5/
SPI6/I2S6
DFSDM1/2/I2C4/
OCTOSPIM_P1/
SAI1/SPI3/I2S3/
UART4
SDMMC1/SPI2/
I2S2/SPI3/
I2S3/SPI6/
I2S6/UART7/
USART1/2/3/6
LPUART1/
SAI2/
SDMMC1/
SPDIFRX1/
SPI6/I2S6/
UART4/5/8
FDCAN1/2/FMC/L
CD/
OCTOSPIM_P1/2/
SDMMC2/
SPDIFRX1/
TIM13/14
CRS/FMC/LCD/
OCTOSPIM_P1/
OTG1_FS/
OTG1_HS/SAI2/
SDMMC2/TIM8
DFSDM1/2/I2C4/LCD/
MDIOS/OCTOSPIM_P1/
SDMMC2/SWPMI1/
TIM1/8/UART7/9/
USART10
FMC/LCD/
MDIOS/
SDMMC1/
TIM1/8
COMP/DCMI/
PSSI/LCD/TIM1
LCD/
UART5
SYS
-
-
-
-
-
-
FMC_D24
DCMI_D13/
PSSI_D13
LCD_G5
EVENTOUT
-
-
-
-
-
TIM8_BKIN2_COMP12
FMC_D25
LCD_G6
EVENTOUT
LCD_G7
EVENTOUT
-
EVENTOUT
LCD_B4
EVENTOUT
LCD_B5
EVENTOUT
LCD_B6
EVENTOUT
LCD_B7
EVENTOUT
-
EVENTOUT
SYS
LPTIM1/
TIM1/2/16/17
PDM_SAI1/
TIM3/4/5/12/15
DFSDM1/LPTIM2/3/
LPUART1/
OCTOSPIM_P1/2/
TIM8
CEC/DCMI/
PSSI/
DFSDM1/2/
I2C1/2/3/4/
LPTIM2/
TIM15/
USART1
-
-
TIM5_CH4
-
-
Port
PI0
AF1
SPI2_SS/
I2S2_WS
SPI2_SCK/
PI1
-
-
-
TIM8_BKIN2
-
DCMI_D8/
I2S2_CK
PI2
PI3
-
-
-
-
-
-
TIM8_CH4
TIM8_ETR
-
-
PSSI_D8
DCMI_D9/
SPI2_MISO/
I2S2_SDI
-
SPI2_MOSI/
I2S2_SDO
-
-
-
-
-
-
FMC_D26
PSSI_D9
-
-
-
-
-
FMC_D27
DCMI_D10/
PSSI_D10
DCMI_D5/
PI4
-
-
-
TIM8_BKIN
-
-
-
-
-
-
SAI2_MCK_A
TIM8_BKIN_COMP12
FMC_NBL2
PSSI_D5
-
-
-
TIM8_CH1
-
-
-
-
-
-
SAI2_SCK_A
-
FMC_NBL3
Port I
PI5
DCMI_VSYNC/
PSSI_
RDY
DCMI_D6/
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
SAI2_SD_A
-
FMC_D28
PSSI_D6
DCMI_D7/
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
SAI2_FS_A
-
FMC_D29
PSSI_D7
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
PI9
-
-
-
OCTOSPIM_P2_IO0
-
-
-
-
UART4_RX
FDCAN1_RX
-
-
FMC_D30
-
EVENTOUT
VSYNC
LCD_
PI10
-
-
-
OCTOSPIM_P2_IO1
-
-
-
-
-
-
-
-
FMC_D31
PSSI_D14
EVENTOUT
HSYNC
OTG_HS_
PI11
-
-
-
OCTOSPIM_P2_IO2
-
-
-
-
-
LCD_G6
-
-
PSSI_D15
-
EVENTOUT
ULPI_DIR
STM32H7B0xB
page 61/205
STM32H7B0xB
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction
temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction
temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in
the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and
represent the mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 1.62 V ≤ VDD ≤ 3.6 V
voltage range). They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10. Pin loading conditions.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11. Pin input voltage.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
MCU pin
MCU pin
C = 50 pF
DS13196 - Rev 7
V IN
page 62/205
STM32H7B0xB
Parameter conditions
6.1.6
Power supply scheme
Figure 12. Power supply scheme
VDDSMPS
VDDSMPS
10 μF
4.7 μ F
4.7 μF
4.7 μF
2.2 μH
SMPS
Switched Mode
Power Supply
step down
converter
VLXSMPS
100 pF or 200 pF
VFBSMPS
VSSSMPS
SMPS disabled
SMPS enabled
VCAP1/2
100 nF(1)
2.2 μF
LDO enabled
LDO disabled
LDO
Voltage
regulator
VCAP3
VDDLDO
Core domain
100nF
VDD
Two different possible use cases
PDR_ON
POR/PDR
VDDMMC
VDDMMC
100
nF
1 μF
VDDMMC
IOs
100 nF
Two different possible use cases
VDD
100 nF(1)
VDD
IOs
VDD
VDD
4.7 μF
VDD
domain
100 nF(1)
VSS
Two different possible use cases
Battery
Power switch
VBAT
1 μF
Backup
domain
100 nF
BKUP
IOs
VDD50USB
5V
3.3V
4.7 μF
USB regulator
VDD33USB
1 μF
1 μF
100 nF
USB FS
IOs
Two different possible use cases
VDDA
VREF+
VDDA
1 μF
47W
Analog domain
100 nF
VREF+
1 μF
1 μF
100 nF
VREFVSSA
Three different possible use cases
Defines different use case options
Define power domaines
DS13196 - Rev 7
page 63/205
STM32H7B0xB
Absolute maximum ratings
1.
2.
100 nF filtering capacitor on each package pin.
A tolerance of +/- 20% is acceptable on decoupling capacitors.
Note:
Refer to Getting started with STM32H7A3/7B3 and STM32H7B0 hardware development(AN5307) for more
details.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown
above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside
of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to
reduce PCB size or cost. This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 13. Current consumption measurement scheme
SMPS ON
LDO ON
IDD_VBAT
IDD_VBAT
VBAT
VBAT
VDDMMC
VDDMMC
IDD
IDD
VDD
VDD
VDDSMPS
VDDLDO
VDDA
VDDA
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 17. Voltage characteristics, Table 18. Current
characteristics, and Table 19. Thermal characteristics may cause permanent damage to the device. These are
stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability. Device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on
demand.
Table 17. Voltage characteristics
All main power (VDD, VDDA, VDD33USB, VDDMMC, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
Symbols
VDDX − VSS
VIN(1)
Ratings
Min
Max
Unit
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VDDMMC,
VBAT) +4.0(2)(3)
V
Input voltage on TT_xx pins
VSS−0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS−0.3
4.0
V
-
50
mV
External main supply voltage (including VDD, VDDLDO, VDDSMPS,
VDDA, VDD33USB, VDDMMC, VBAT, VREF+)
Input voltage on any other pins
|ΔVDDX|
DS13196 - Rev 7
Variations between different VDDX power pins of the same domain
page 64/205
STM32H7B0xB
Absolute maximum ratings
Symbols
Ratings
Min
Max
Unit
-
50
mV
|VSSx−VSS| Variations between all the different ground pins
1. VIN maximum value must always be respected. Refer to Table 62. I/O current injection susceptibility for the maximum
allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.
Table 18. Current characteristics
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines
(source)(1)
620
ΣIVSS
Total current out of sum of all VSS ground lines (sink)(1)
620
IVDD
Maximum current into each VDD power pin
(source)(1)
100
IVSS
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk or sourced by any I/O and control pin
20
Output current sunk or sourced by Pxy_C pin
1
IIO
ΣI(PIN)
IINJ(PIN)(3)(4)
ΣIINJ(PIN)
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control
Unit
mA
140
pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDDSMPS, VDDLDO, VDD33USB, VDDMMC) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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