STM32L010F4
STM32L010K4
Value line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+,
16-Kbyte Flash memory, 2-Kbyte SRAM, 128-byte EEPROM, ADC
Datasheet - production data
Features
•
Ultra-low-power platform
– 1.8 V to 3.6 V power supply
– –40 to 85 °C temperature range
– 0.23 µA Standby mode (2 wakeup pins)
– 0.29 µA Stop mode (16 wakeup lines)
– 0.54 µA Stop mode + RTC + 2-Kbyte RAM
retention
– Down to 76 µA/MHz in Run mode
– 5 µs wakeup time (from Flash memory)
– 41 µA 12-bit ADC conversion at 10 ksps
• Core: Arm® 32-bit Cortex®-M0+
– From 32 kHz to 32 MHz
– 0.95 DMIPS/MHz
• Reset and supply management
– Ultra-low-power BOR (brownout reset) with
5 selectable thresholds
– Ultra-low-power POR/PDR
• Clock sources
– 0 to 32 MHz external clock
– 32 kHz oscillator for RTC with calibration
– High-speed internal 16 MHz factory-trimmed RC
(±1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– PLL for CPU clock
• Pre-programmed bootloader
– USART, SPI supported
• Development support
– Serial wire debug supported
• Up to 26 fast I/Os (23 I/Os 5-Volt tolerant)
•
LQFP32
7 x 7 mm
•
•
TSSOP20
169 mils
Analog peripherals
– 12-bit ADC 1.14 Msps up to 10 channels (down
to 1.8 V)
5-channel DMA controller, supporting ADC, SPI,
I2C, USART and timers
•
4x peripherals communication interface
•
1x USART, 1x LPUART (low power)
•
1x SPI 16 Mbit/s
•
1x I2C (SMBus/PMBus)
•
7x timers: 1x 16-bit with up to 4 channels,
1x 16-bit with up to 2 channels, 1x 16-bit ultra-lowpower timer, 1x SysTick, 1x RTC and 2x watchdogs
(independent/window)
•
CRC calculation unit, 96-bit unique ID
•
All packages are ECOPACK2 compliant.
Memories
– 16-Kbyte Flash memory
– 2-Kbyte RAM
– 128 bytes of data EEPROM
– 20-byte backup register
– Sector protection against R/W operation
August 2019
This is information on a product in full production.
DS12323 Rev 3
1/91
www.st.com
Contents
STM32L010F4/K4
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Arm® Cortex®-M0+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 21
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12
System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14
2/91
3.4.1
3.13.1
General-purpose timers (TIM2, TIM21) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13.2
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13.3
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.1
I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 26
3.14.3
Low-power universal asynchronous receiver transmitter (LPUART) . . . 27
DS12323 Rev 3
STM32L010F4/K4
Contents
3.14.4
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15
Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 27
3.16
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.15
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.16
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DS12323 Rev 3
3/91
4
Contents
7
STM32L010F4/K4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.1
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4/91
DS12323 Rev 3
STM32L010F4/K4
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
STM32L010F4/K4 features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 14
Functionalities depending on the working mode
(from Run/active down to Standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32L010F4/K4 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Features of general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Current consumption in Run mode vs code type, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Current consumption in Run mode, code with data processing running from RAM . . . . . . 45
Current consumption in Run mode vs code type, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 50
Average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral current consumption in run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 53
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 63
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DS12323 Rev 3
5/91
6
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
6/91
STM32L010F4/K4
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . 86
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DS12323 Rev 3
STM32L010F4/K4
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
STM32L010F4/K4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32L010F4/K4 TSSOP20 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32L010F4/K4 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IDD vs VDD, Run mode, code running from Flash memory, Range 2, HSI, 1 ws . . . . . . . . 44
IDD vs VDD, Run mode, code running from Flash memory, Range 2, HSE bypass, 1 ws . 45
IDD vs VDD, Low-power run mode executed from RAM, Range 3, MSI at 65 KHz, 0 ws . . 48
IDD vs VDD, Stop mode with RTC enabled and running from LSE on low drive . . . . . . . . . 49
IDD vs VDD, Stop mode with RTC disabled, all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . 50
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 59
VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DS12323 Rev 3
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7
Introduction
1
STM32L010F4/K4
Introduction
The STM32L010F4/K4 ultra-low-power microcontrollers are part of the STM32L010 value
line.
The STM32L010F4/K4 features make these ultra-low-power microcontrollers suitable for a
wide range of applications:
•
gas/water meters and industrial sensors
•
healthcare and fitness equipment
•
remote control and user interfaces
•
PC peripherals, gaming, GPS equipment
•
alarm systems, wired and wireless sensors, video intercom
This datasheet must be read in conjunction with the STM32L010 value line reference
manual (RM0451).
For information on the Arm®(a) Cortex®-M0+ core, refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the STM32L010F4/K4.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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STM32L010F4/K4
2
Description
Description
The ultra-low-power STM32L010F4/K4 microcontrollers incorporate the high-performance
Arm® Cortex®-M0+ 32-bit RISC core operating at 32 MHz, high-speed embedded memories
(16 Kbytes of Flash program memory, 128 bytes of data EEPROM and 2 Kbytes of RAM)
plus an extensive range of enhanced I/Os and peripherals.
The STM32L010F4/K4 provide high power efficiency over a wide performance range. This
is achieved with a large choice of internal and external clock sources, internal voltage
adaptation, and several low-power modes.
The STM32L010F4/K4 offer several analog features: one 12-bit ADC with hardware
oversampling, several timers, one low-power timer (LPTIM), two general-purpose 16-bit
timers, one RTC and one SysTick that can be used as timebases. The STM32L010F4/K4
also feature two watchdogs, one watchdog with independent clock and window capability,
and one window watchdog based on the bus clock.
Moreover, the STM32L010F4/K4 embed standard and advanced communication interfaces:
one I2C, one SPI, one USART, and a low-power UART (LPUART).
The STM32L010F4/K4 also include a real-time clock and a set of backup registers that
remain powered in Standby mode.
The ultra-low-power STM32L010F4/K4 operate from a 1.8 to 3.6 V power supply and in the
–40 to + 85 °C temperature range. A comprehensive set of power-saving modes allows the
design of low-power applications.
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28
Description
2.1
STM32L010F4/K4
Device overview
Table 1. STM32L010F4/K4 features and peripheral counts
Feature and peripheral count
STM32L010F4
Flash memory (Kbytes)
16
Data EEPROM (bytes)
128
RAM (Kbytes)
2
Timers
General-purpose
2
LPTIM
1
RTC / SYSTICK / IWDG / WWDG
Communication
interfaces
1/1/1/1
SPI
1
I2C
1
USART
1
LPUART
1
GPIOs
Clocks:
16
HSE(1)
/ LSE / HSI / MSI / LSI
12-bit synchronized ADC / Number of
channels
26
1/1/1/1/1
1/7
Maximum CPU frequency
1/10
32 MHz
Operating voltage range
1.8 to 3.6 V
Operating temperatures
Ambient temperature: –40 to +85 °C
Junction temperature: –40 to +105 °C
Package
TSSOP20
1. HSE available only as external clock input (HSE bypass).
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DS12323 Rev 3
LQFP32
STM32L010F4/K4
Description
Figure 1. STM32L010F4/K4 block diagram
SWD
SWD
FLASH
EEPROM
BOOT
CORTEX M0+ CPU
Fmax:32MHz
RAM
DBG
DMA1
NVIC
A
P
B
2
ADC1
AINx
SPI1
MISO, MOSI,
SCK, NSS
TIM21
2ch
EXTI
BRIDGE
CRC
BRIDGE
GPIO PORT A
PB[0:15]
GPIO PORT B
PC[14:15]
GPIO PORT C
CK_IN
HSE
LPTIM1
AHB: Fmax 32MHz
PA[0:15]
WWDG
I2C1
A
P
B
1
IN1, IN2,
ETR, OUT
SCL, SDA,
SMBA
USART2
RX, TX, RTS,
CTS, CK
LPUART1
RX, TX,
RTS, CTS
HSI 16M
LSI
IWDG
PLL
MSI
TIM2
4ch
RTC
BCKP REG
RESET & CLK
WKUPx
OSC32_IN,
OSC32_OUT
LSE
VREF_OUT
PMU
NRST
VDDA
VDD
REGULATOR
MSv48124V1
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Description
2.2
STM32L010F4/K4
Ultra-low-power device continuum
The ultra-low-power microcontrollers’ family offers a large choice of core and features, from
8-bit proprietary core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and
Arm® Cortex®-M0+. The STM32Lx series are the best choice to answer application needs in
terms of ultra-low-power features and the best solution for applications such as gas/water
meter, keyboard/mouse or fitness and healthcare applications.
Several built-in features, like LCD drivers, dual-bank memory, low-power Run mode,
operational amplifiers, 128-bit AES, DAC, crystal-less USB and many others, definitely help
building a highly cost optimized application by reducing BOM cost. STMicroelectronics, as a
reliable and long-term manufacturer, ensures as much as possible pin-to-pin compatibility
between all STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx
on the other hand.
Thanks to this scalability, any legacy application can be upgraded to respond to the latest
market feature and efficiency requirements.
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Functional overview
3
Functional overview
3.1
Low-power modes
The STM32L010F4/K4 support dynamic voltage scaling to optimize its power consumption
in Run mode. The voltage from the internal low-drop regulator that supplies the logic, can be
adjusted according to the maximum operating frequency of the system.
There are three power consumption ranges:
•
Range 1 with the CPU running at up to 32 MHz
•
Range 2 with a maximum CPU frequency of 16 MHz
•
Range 3 with a maximum CPU frequency limited to 4.2 MHz
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. The power consumption in this
mode, at 16 MHz, is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize its operating current. In Low-power run mode,
the clock frequency and the number of enabled peripherals are both limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize its operating current. In Low-power sleep mode, both the
clock frequency and the number of enabled peripherals are limited; a typical example is
to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
•
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, HSE input, MSI and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in Low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line. In 3.5 µs, the
processor serves the interrupt or resume the code. The EXTI line source can be any
GPIO, the RTC alarm/tamper/timestamp/wakeup events, or the
USART/I2C/LPUART/LPTIM wakeup events.
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28
Functional overview
•
STM32L010F4/K4
Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped. The PLL, MSI RC, HSI and LSI RC, HSE
bypass input and LSE crystal oscillator are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in Low-power mode. The device can be woken up from Stop
mode by any of the EXTI line. In 3.5 µs, the processor serves the interrupt or resume
the code. The EXTI line source can be any GPIO. It can also be wakened by the
USART/I2C/LPUART/LPTIM wakeup events.
•
Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSE bypass and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 kHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC wakeup event occurs.
•
Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire VCORE domain is powered off. The
PLL, MSI RC, HSI and LSI RC, HSE bypass and LSE crystal oscillator are also
switched off. After entering Standby mode, the RAM and register contents are lost
except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE
Crystal 32 kHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
For power supply voltage range 1.8 V-2.0 V, CPU frequency changes from initial to final
must respect the condition: fCPU initial < 4fCPU initial. It must also respect 5 µs delay between
two changes. For example, switch from 4.2 MHz to 32 MHz can be split in switch from
4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.
Table 2. CPU frequency range depending on dynamic voltage scaling
CPU frequency range (number of wait state)
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws) - 32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws) - 32 kHz to 8 MHz (0ws)
Range 2
32 kHz to 4.2 MHz (0ws)
Range 3
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STM32L010F4/K4
Functional overview
Table 3. Functionalities depending on the working mode
(from Run/active down to Standby)(1)(2)
Run/active
mode
Sleep
mode
Lowpower
run
mode
Lowpower
sleep
mode
CPU
Y
-
Y
-
-
-
-
-
Flash memory
O
O
O
O
-
-
-
-
RAM
Y
Y
Y
Y
Y
-
-
-
Backup registers
Y
Y
Y
Y
Y
-
Y
-
EEPROM
O
O
O
O
-
-
-
-
Brownout reset (BOR)
O
O
O
O
O
O
O
O
DMA
O
O
O
O
-
-
-
-
Power-on/down reset
(POR/PDR)
Y
Y
Y
Y
Y
Y
Y
Y
High speed internal (HSI)
O
O
-
-
(3)
-
-
-
High speed external (HSE)
O
O
O
O
-
-
-
-
Low speed internal (LSI)
O
O
O
O
O
-
O
-
Low speed external (LSE)
O
O
O
O
O
-
O
-
Multispeed internal (MSI)
O
O
Y
Y
-
-
-
-
Interconnect controller
Y
Y
Y
Y
Y
-
-
-
RTC
O
O
O
O
O
O
O
-
RTC tamper
O
O
O
O
O
O
O
O
Auto wakeup (AWU)
O
O
O
O
O
IP
USART
O
O
O
O
Stop mode
Standby mode
Wakeup
capability
Wakeup
capability
-
O
O
O
(4)
O
-
-
(4)
O
-
-
LPUART
O
O
O
O
O
SPI
O
O
O
O
-
-
-
-
O
-
-
I2C
O
O
-
-
O(5)
ADC
O
O
-
-
-
-
-
-
16-bit timers
O
O
O
O
-
-
-
-
LPTIM
O
O
O
O
O
O
-
-
IWDG
O
O
O
O
O
O
O
O
WWDG
O
O
O
O
-
-
-
-
SysTick timer
O
O
O
O
-
-
-
-
GPIOs
O
O
O
O
O
O
-
2 pins
0 µs
6 CPU
cycles
3 µs
7 CPU
cycles
Wakeup time to Run mode
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5 µs
65 µs
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28
Functional overview
STM32L010F4/K4
Table 3. Functionalities depending on the working mode
(from Run/active down to Standby)(1)(2) (continued)
Run/active
mode
IP
Sleep
mode
Lowpower
run
mode
Down to
Down to
140 µA/MHz 37 µA/MHz Down
(from Flash (from Flash to 8 µA
memory)
memory)
Consumption
VDD=1.8 to 3.6 V (typ)
Lowpower
sleep
mode
Stop mode
Standby mode
Wakeup
capability
Wakeup
capability
0.29 µA (no
RTC) VDD=1.8 V
0.1 µA (no RTC)
VDD=1.8 V
0.41 µA (with RTC)
0.54 µA (with
VDD=1.8 V
RTC) VDD=1.8 V
Down
to
4.5 µA
0.34 µA (no
RTC) VDD=3.0 V
0.23 µA (no RTC)
VDD=3.0 V
0.53 µA (with RTC)
0.67 µA (with
VDD=3.0 V
RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional (can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. USART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the USART has to wake up or keep
running the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It wakes up the
HSI during reception.
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Table 4. STM32L010F4/K4 peripherals interconnect matrix
Interconnect
source
TIMx
RTC
All clocks
16/91
Interconnect
destination
TIMx
TIM21
LPTIM1
TIMx
Run
Sleep
Lowpower
run
Lowpower
sleep
Stop
Timer triggered by other timer
Y
Y
Y
Y
-
Timer triggered by auto wakeup
Y
Y
Y
Y
-
Timer triggered by RTC event
Y
Y
Y
Y
Y
Clock source used as input channel
for RC measurement and trimming
Y
Y
Y
Y
-
Interconnect action
DS12323 Rev 3
STM32L010F4/K4
Functional overview
Table 4. STM32L010F4/K4 peripherals interconnect matrix (continued)
Interconnect
source
GPIO
Interconnect
destination
Run
Sleep
Lowpower
run
Lowpower
sleep
Stop
TIMx
Timer input channel and trigger
Y
Y
Y
Y
-
LPTIM1
Timer input channel and trigger
Y
Y
Y
Y
Y
Conversion trigger
Y
Y
Y
Y
-
ADC
3.3
Interconnect action
Arm® Cortex®-M0+ core
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
•
a simple architecture that is easy to learn and program
•
ultra-low power, energy-efficient operation
•
excellent code density
•
deterministic, high-performance interrupt handling
•
upward compatibility with Cortex-M processor family
•
platform security robustness
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L010F4/K4 are compatible with all Arm tools
and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L010F4/K4 embed a nested vectored interrupt controller, able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable nested vectored interrupt
controller (NVIC), to deliver industry-leading interrupt performance.
The NVIC includes a non-maskable interrupt (NMI) and provides zero jitter interrupt option
plus four interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to abandon and restart load-multiple and
store-multiple operations. Interrupt handlers do not require any assembler wrapper code,
removing any code overhead from the ISRs. Tail-chaining optimization also significantly
reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates sleep modes, such as a deep-sleep
function that enables the entire device to enter rapidly Stop or Standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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Functional overview
STM32L010F4/K4
3.4
Reset and supply management
3.4.1
Power supply schemes
3.4.2
•
VDD (1.8 to 3.6 V): external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•
VSSA, VDDA (1.8 to 3.6 V): external analog power supplies for ADC, reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The STM32L010F4/K4 feature an integrated zeropower power-on reset (POR)/power-down
reset (PDR) that can be coupled with a brownout reset (BOR) circuitry.
After the VDD threshold is reached, the option byte loading process starts, either to confirm
or modify default thresholds, or to disable the BOR permanently.
The BOR is active at power-on, and ensures proper operation starting from 1.8 V, whatever
the power ramp-up phase before it reaches 1.8 V.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
3.4.4
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 kHz oscillator, RCC_CSR).
Boot modes
At startup, BOOT0 pin and nBOOT0, nBOOT1 and nBOOT_SEL option bits are used to
select one of the three following boot options:
•
Boot from Flash memory
•
Boot from system memory
•
Boot from embedded RAM
The bootloader is located in system memory. It is used to reprogram the Flash memory by
using SPI1 (PA4, PA5, PA6 and PA7) or USART2 (PA2, PA3).
If the bootloader is activated (the bootloader is active on all empty devices due to the empty
check mechanism), then the above mentioned bits are configured depending on whether
SPI1 or USART2 functionality is used.
See the application note STM32 microcontroller system memory boot mode (AN2606) for
more details.
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DS12323 Rev 3
STM32L010F4/K4
3.5
Functional overview
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. Its associated features are the listed below:
•
Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
•
Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
•
Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
•
System clock source
Three different clock sources are available to drive the master clock SYSCLK:
•
–
0-32 MHz high-speed external (HSE bypass), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
multispeed internal RC oscillator (MSI), trimmable by software, able to generate
seven frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz
and 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source
Two ultra-low-power clock sources can be used to drive the real-time clock:
•
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
RTC clock sources
The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system
clock.
•
Startup clock
After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
•
Clock security system (CSS)
This feature can be enabled by software. If an LSE clock failure occurs, it provides an
interrupt or wakeup event that is generated assuming it has been previously enabled.
This feature is not available on the HSE clock.
•
Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz.
See Figure 2 for details on the clock tree.
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28
Functional overview
STM32L010F4/K4
Figure 2. Clock tree
@V33
LSI RC
Enable Watchdog
Watchdog LS
LSI tempo
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal
RTCSEL
RTC2 enable
LSE OSC
RTC
LSE tempo
LSU
LSD
LSD
@V18
@V33
MSI RC
LSI
LSE
MSI
MCOSEL
ADC enable
ADCCLK
Level shifters
@V18
MCO
/ 1,2,4,8,16
not deepsleep
/ 2,4,8,16
@V33
HSI16 RC
ck_rchs
Level shifters
@V18
/ 1,4
HSI16
System
Clock
4 MHz
Level shifters
@V18
PLLSRC
@V33
LSU
1 MHz Clock
Detector
/ 1,2,…, 512
X
3,4,6,8,12,16,
24,32,48
HCLK
PCLK1 to APB1
peripherals
APB1
PRESC
/ 1,2,4,8,16
Peripheral
clock enable
to TIMx
If (APB1 presc=1) x1
else x2)
/ 2,3,4
LSD
not (sleep or
deepsleep)
TIMxCLK
PLLCLK
Level shifters
@VDDCORE
HSE present or not
FCLK
AHB
PRESC
ck_pllin PLL
@V33
not (sleep or
deepsleep)
/8
MSI
HSI16
HSE
@V33
HSE OSC
CK_PWR
not deepsleep
Clock
Source
Control
APB2
PRESC
/ 1,2,4,8,16
Peripheral
clock enable
PCLK2 to APB2
32 MHz
peripherals
max.
Peripheral
clock enable
If (APB2 presc=1) x1
else x2)
LSI
LSE
HSI16
SYSCLK
PCLK
to TIMx
Peripherals
enable
Peripherals
enable
Peripherals
enable
LPTIMCLK
LPUART/
UARTCLK
I2C1CLK
MSv34747V2
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STM32L010F4/K4
3.6
Functional overview
Low-power real-time clock and backup registers
The real time clock (RTC) and the 5 backup registers are supplied in all modes including
Standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD (binary-coded decimal) timer/counter. Its main features
are the following:
•
•
•
•
•
•
•
•
•
Calendar with subsecond, second, minute, hour (12 or 24 format), week, day, date,
month and year, in BCD format
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
Two programmable alarms with wakeup capability from Stop and Standby modes
Periodic wakeup from Stop and Standby modes, with programmable resolution and
period
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize with a master clock.
Reference clock detection: a more precise second-source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes, on tamper event detection.
Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The possible RTC clock sources are listed below:
•
•
•
•
3.7
a 32.768 kHz external crystal
a resonator or oscillator
the internal low-power RC oscillator (typical frequency of 37 kHz)
the high-speed external clock
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIOs are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
I/O bus with a toggling speed of up to 32 MHz.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 23 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI detects an external line with a pulse
width shorter than the Internal APB2 clock period. Up to 26 GPIOs can be connected to the
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Functional overview
STM32L010F4/K4
16 configurable interrupt/event lines. The 7 other lines are connected to RTC, USART, I2C,
LPUART or LPTIM events.
3.8
Memories
The STM32L010F4/K4 integrate the following memories:
•
2 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
state. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
the non-volatile memory divided into three arrays:
–
16 Kbytes of embedded Flash program memory
–
128 bytes of data EEPROM
–
information block containing 32 user and factory options bytes, plus 4 Kbytes of
system memory
The user options bytes are used to write-protect or read-out protect the memory (4-Kbyte
granularity) and/or readout-protect the whole memory with the following options:
•
Level 0: no protection
•
Level 1: memory readout protected
The Flash memory cannot be read or written if either debug features are connected or
boot in RAM is selected.
•
3.9
Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
Direct memory access (DMA)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, LPUART,
general-purpose timers, and ADC.
3.10
Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into the STM32L010F4/K4. The ADC has up to 10 external channels
and one internal channel (voltage reference). Three channels (PA0, PA4 and PA5) are fast
channels, while the others are standard channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 Msps even with a low CPU speed. The ADC consumption is low at all
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Functional overview
frequencies (~25 µA at 10 ksps, ~200 µA at 1 Msps). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits. See the application note Improving STM32F1x and STM32L1x ADC resolution by
oversampling (AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
3.11
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate
monitoring of the VDD value (since no external voltage, VREF+, is available for ADC). The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area (see Table 17: Embedded internal reference
voltage calibration values). It is accessible in read-only mode.
Reference voltage
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.12
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21 and LPTIM1 timer input captures. The system
configuration controller also controls the routing of internal analog signals to the ADC and
the internal reference voltage VREFINT.
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Functional overview
3.13
STM32L010F4/K4
Timers and watchdogs
The ultra-low-power STM32L010F4/K4 include two general-purpose timers, one low- power
timer (LPTIM1), two watchdog timers and the SysTick timer.
3.13.1
General-purpose timers (TIM2, TIM21)
Table 5 compares the features of the general-purpose timers.
Table 5. Features of general purpose timers
Timer
Counter Counter
resolution
type
Prescaler factor
DMA
request
generation
Capture/compare Complementary
channels
outputs
TIM2
16-bit
Up,
down,
up/down
Any integer
between 1 and 65536
Yes
4
No
TIM21
16-bit
Up,
down,
up/down
Any integer
between 1 and 65536
No
2
No
TIM2
This timer is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler and
four independent channels for input capture/output compare, PWM or one-pulse mode
output.
TIM2 can work together and be synchronized with the TIM21 timer via the Timer Link
feature for synchronization or event chaining. The TIM2 counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs.
TIM2 has independent DMA request generation.
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
TIM21
This timer is based on a 16-bit auto-reload up/down counter. It includes a 16-bit prescaler
and two independent channels for input capture/output compare, PWM or one-pulse mode
output. TIM21 can work together and be synchronized with TIM2.
TIM21 can also be used as a simple timebase and be clocked by the LSE (32.768 kHz) to
provide independent timebase from the main CPU clock.
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3.13.2
Functional overview
Low-power timer (LPTIM)
LPTIM1 has an independent clock and is running also in Stop mode if it is clocked by LSE,
LSI or an external clock. This timer is able to wakeup the STM32L010F4/K4 from Stop
mode.
LPTIM1 supports the following features:
3.13.3
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / one shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source
–
Internal clock source: LSE, LSI, HSI or APB clock
–
External clock source over LPTIM1 input (working even with no internal clock
source running, used by the pulse counter application)
•
Programmable digital glitch filter
•
Encoder mode
SysTick timer
This timer is dedicated to the OS, but can also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
3.13.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. IWDG can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for
application timeout management. It is hardware- or software-configurable through the option
bytes. The counter can be frozen in debug mode.
3.13.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.14
Communication interfaces
3.14.1
I2C bus
One I2C interface (I2C1) can operate in multimaster or slave mode. The I2C interface can
support Standard mode up to 100 kbit/s and Fast mode (Fm) up to 400 kbit/s.
The I2C interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask).
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Functional overview
STM32L010F4/K4
In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. I2C1 also has a clock domain independent from the CPU
clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interface can be served by the DMA controller.
Refer to Table 6 for the supported modes and features of I2C interface.
Table 6. I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast mode plus with 20 mA output drive I/Os (up to 1 Mbit/s)
-
Independent clock
X
SMBus
X
Wakeup from Stop
X
1. X = supported.
3.14.2
Universal synchronous/asynchronous receiver transmitter (USART)
The USART interface (USART2) is able to communicate at speeds of up to 4 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 driver enable (DE) signals,
multiprocessor communication mode and single-wire half-duplex communication mode.
The UART2 interface can be served by the DMA controller.
Table 7 for the supported modes and features of the USART interface.
Table 7. USART implementation
USART modes/features(1)
26/91
USART2
Hardware flow control for modem
X
Continuous communication using DMA
X
Multiprocessor communication
X
Synchronous mode
-
Smartcard mode
-
Single-wire half-duplex communication
X
IrDA SIR ENDEC block
-
LIN mode
-
Dual clock domain and wakeup from Stop mode
-
Receiver timeout interrupt
-
Modbus communication
-
DS12323 Rev 3
STM32L010F4/K4
Functional overview
Table 7. USART implementation (continued)
USART modes/features(1)
USART2
Auto baud rate detection (4 modes)
-
Driver enable
X
1. X = supported.
3.14.3
Low-power universal asynchronous receiver transmitter (LPUART)
The STM32L010F4/K4 embed one low-power UART. The LPUART supports asynchronous
serial communication with minimum power consumption. It supports half-duplex single-wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wake up the
system from Stop mode, using baudrates up to 46 kbauds. The wakeup events from Stop
mode are programmable and can be one of the following:
•
start bit detection
•
any received data frame
•
a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 bauds. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.14.4
Serial peripheral interface (SPI)
The SPI is able to communicate at up to 16 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card / MMC modes.
The SPI can be served by the DMA controller.
Refer to Table 8 for the supported modes and features of SPI interface.
Table 8. SPI implementation
SPI features(1)
SPI1
Hardware CRC calculation
X
I2S mode
-
TI mode
X
1. X = supported.
3.15
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
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Functional overview
STM32L010F4/K4
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.16
Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
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STM32L010F4/K4
4
Pin descriptions
Pin descriptions
Figure 3. STM32L010F4/K4 TSSOP20 pinout
PB9-BOOT0
1
20
PC14-OSC32_IN
PC15-OSC32_OUT
2
19
3
18
PA10
NRST
4
17
PA9
VDDA
5
16
VDD
PA0-CK_IN
6
15
VSS
PA1
PA2
PA3
7
14
PB1
8
13
PA7
9
12
PA4
10
11
PA6
PA5
PA14
PA13
MSv37875V1
1. The above figure shows the package top view.
PA15
PB3
PB4
PB5
PB6
PB7
PB9-BOOT0
VSS
Figure 4. STM32L010F4/K4 LQFP32 pinout
VDD
1
32 31 30 29 28 27 26 25
24
PA14
PC14-OSC32_IN
2
23
PA13
PC15-OSC32_OUT
3
22
PA12
NRST
4
21
PA11
VDDA
5
20
PA10
PA0-CK_IN
6
19
PA9
PA1
7
18
PA8
PA2
8
17
9 10 11 12 1 3 14 15 16
VDD
VSS
PB1
PB0
PA7
PA6
PA5
PA4
PA3
LQFP32
MSv37870V1
1. The above figure shows the package top view.
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34
Pin descriptions
STM32L010F4/K4
Table 9. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
Supply pin
I
Input only pin
Pin type
I/O structure
Notes
I/O
Input/output pin
FT
5 V tolerant I/O
TTa
3.3 V tolerant I/O directly connected to the ADC
TC
Standard 3.3 V I/O
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions
Table 10. Pin definitions
Pin
number
Pin functions
Not
es
LQFP32
Pin
type
TSSOP20
Pin name (function
after reset)
I/O
struct
ure
-
1
VDD
S
-
(1)
-
-
2
2
PC14-OSC32_IN
I/O
FT
-
-
OSC32_IN
3
3
PC15-OSC32_OUT
I/O
TC
-
-
OSC32_OUT
4
4
NRST
I/O
RST
(2)
-
-
5
5
VDDA
S
-
(3)
-
-
6
6
PA0-CK_IN
I/O
TTa
-
USART2_RX, LPTIM1_IN1,
TIM2_CH1, USART2_CTS,
TIM2_ETR, LPUART1_RX
ADC_IN0,
RTC_TAMP2/WKUP1/
CK_IN
ADC_IN1
Alternate functions
Additional functions
7
7
PA1
I/O
FT
-
EVENTOUT, LPTIM1_IN2,
TIM2_CH2, I2C1_SMBA,
USART2_RTS, TIM21_ETR,
LPUART1_TX
8
8
PA2
I/O
TTa
-
TIM21_CH1, TIM2_CH3,
USART2_TX, LPUART1_TX
ADC_IN2,
RTC_TAMP3/RTC_TS/
RTC_OUT/WKUP3
9
9
PA3
I/O
FT
-
TIM21_CH2, TIM2_CH4,
USART2_RX, LPUART1_RX
ADC_IN3
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Pin descriptions
Table 10. Pin definitions (continued)
LQFP32
TSSOP20
Pin
number
Pin functions
Pin name (function
after reset)
Pin
type
I/O
struct
ure
Not
es
Alternate functions
Additional functions
ADC_IN4
10
10
PA4
I/O
TTa
-
SPI1_NSS, LPTIM1_IN1,
LPTIM1_ETR, I2C1_SCL,
USART2_CK, TIM2_ETR,
LPUART1_TX
11
11
PA5
I/O
TTa
-
SPI1_SCK, LPTIM1_IN2,
TIM2_ETR, TIM2_CH1
ADC_IN5
12
12
PA6
I/O
FT
-
SPI1_MISO, LPTIM1_ETR,
LPUART1_CTS, EVENTOUT
ADC_IN6
13
13
PA7
I/O
FT
-
SPI1_MOSI, LPTIM1_OUT,
USART2_CTS, TIM21_ETR,
EVENTOUT
ADC_IN7
-
14
PB0
I/O
FT
-
EVENTOUT, SPI1_MISO,
TIM2_CH2, USART2_RTS,
TIM2_CH3
ADC_IN8, VREF_OUT
14
15
PB1
I/O
FT
-
USART2_CK, SPI1_MOSI,
LPTIM1_IN1, LPUART1_RTS,
TIM2_CH4
ADC_IN9, VREF_OUT
15
16
VSS
S
-
(4)
-
-
-
-
16
17
VDD
S
-
(1)
-
18
PA8
I/O
FT
-
MCO, LPTIM1_IN1, EVENTOUT,
USART2_CK, TIM2_CH1
-
17
19
PA9
I/O
FT
-
MCO, I2C1_SCL, LPTIM1_OUT,
USART2_TX, TIM21_CH2
-
18
20
PA10
I/O
FT
-
TIM21_CH1, I2C1_SDA,
RTC_REFIN, USART2_RX,
TIM2_CH3
-
-
21
PA11
I/O
FT
-
SPI1_MISO, LPTIM1_OUT,
EVENTOUT, USART2_CTS,
TIM21_CH2
-
-
22
PA12
I/O
FT
-
SPI1_MOSI, EVENTOUT,
USART2_RTS
-
19
23
PA13
I/O
FT
-
SWDIO, LPTIM1_ETR,
I2C1_SDA, SPI1_SCK,
LPUART1_RX
-
20
24
PA14
I/O
FT
-
SWCLK, LPTIM1_OUT,
I2C1_SMBA, USART2_TX,
SPI1_MISO, LPUART1_TX
-
-
25
PA15
I/O
FT
-
SPI1_NSS, TIM2_ETR,
EVENTOUT, USART2_RX,
TIM2_CH1
-
DS12323 Rev 3
31/91
34
Pin descriptions
STM32L010F4/K4
Table 10. Pin definitions (continued)
Pin
number
Pin functions
I/O
struct
ure
Not
es
LQFP32
Pin
type
TSSOP20
Pin name (function
after reset)
-
26
PB3
I/O
FT
-
SPI1_SCK, TIM2_CH2,
EVENTOUT
-
-
27
PB4
I/O
FT
-
SPI1_MISO, EVENTOUT
-
-
28
PB5
I/O
FT
-
SPI1_MOSI, LPTIM1_IN1,
I2C1_SMBA, TIM21_CH1
-
-
29
PB6
I/O
FT
-
USART2_TX, I2C1_SCL,
LPTIM1_ETR, TIM2_CH3,
LPUART1_TX
-
-
30
PB7
I/O
FT
-
USART2_RX, I2C1_SDA,
LPTIM1_IN2, TIM2_CH4,
LPUART1_RX
VREF_PVD_IN
1
31
PB9-BOOT0
I
B
-
-
-
-
(4)
-
-
-
32
VSS
S
Alternate functions
Additional functions
1. Digital power supply.
2. Device reset input/internal reset output (active low).
3. Analog power supply.
4. Digital and analog ground.
32/91
DS12323 Rev 3
AF0
AF1
AF2
AF3
AF4
AF5
AF6
SPI1/USART2/
TIM21/
EVENOUT/
SYS_AF
SPI1/I2C1/
LPTIM
LPUART1/
LPTIM/TIM2/E
VENOUT/
SYS_AF
I2C1/EVENOUT
I2C1/
USART2/
LPUART1/
EVENOUT
SPI1/TIM2/
TIM21
LPUART1/
EVENOUT
PA0
USART2_RX
LPTIM1_IN1
TIM2_CH1
-
USART2_CTS
TIM2_ETR
LPUART1_RX
PA1
EVENTOUT
LPTIM1_IN2
TIM2_CH2
I2C1_SMBA
USART2_RTS
TIM21_ETR
LPUART1_TX
PA2
TIM21_CH1
-
TIM2_CH3
-
USART2_TX
-
LPUART1_TX
PA3
TIM21_CH2
-
TIM2_CH4
-
USART2_RX
-
LPUART1_RX
PA4
SPI1_NSS
LPTIM1_IN1
LPTIM1_ETR
I2C1_SCL
USART2_CK
TIM2_ETR
LPUART1_TX
PA5
SPI1_SCK
LPTIM1_IN2
TIM2_ETR
-
-
TIM2_CH1
-
PA6
SPI1_MISO
LPTIM1_ETR
-
LPUART1_CTS
-
EVENTOUT
PA7
SPI1_MOSI
LPTIM1_OUT
-
USART2_CTS
TIM21_ETR
EVENTOUT
PA8
MCO
-
LPTIM1_IN1
EVENTOUT
USART2_CK
TIM2_CH1
-
PA9
MCO
I2C1_SCL
LPTIM1_OUT
-
USART2_TX
TIM21_CH2
-
PA10
TIM21_CH1
I2C1_SDA
RTC_REFIN
-
USART2_RX
TIM2_CH3
-
PA11
SPI1_MISO
LPTIM1_OUT
EVENTOUT
-
USART2_CTS
TIM21_CH2
-
PA12
SPI1_MOSI
-
EVENTOUT
-
USART2_RTS
-
-
PA13
SWDIO
LPTIM1_ETR
-
I2C1_SDA
-
SPI1_SCK
LPUART1_RX
PA14
SWCLK
LPTIM1_OUT
-
I2C1_SMBA
USART2_TX
SPI1_MISO
LPUART1_TX
PA15
SPI1_NSS
-
TIM2_ETR
EVENTOUT
USART2_RX
TIM2_CH1
-
Port
DS12323 Rev 3
Port A
STM32L010F4/K4
Table 11. Alternate functions
Pin descriptions
33/91
AF0
AF1
AF2
AF3
AF4
AF5
AF6
SPI1/USART2/
TIM21/
EVENOUT/
SYS_AF
SPI1/I2C1/
LPTIM
LPUART1/
LPTIM/TIM2/E
VENOUT/
SYS_AF
I2C1/EVENOUT
I2C1/
USART2/
LPUART1/
EVENOUT
SPI1/TIM2/
TIM21
LPUART1/
EVENOUT
PB0
EVENTOUT
SPI1_MISO
TIM2_CH2
-
USART2_RTS
TIM2_CH3
-
PB1
USART2_CK
SPI1_MOSI
LPTIM1_IN1
-
LPUART1_RTS
TIM2_CH4
-
PB3
SPI1_SCK
-
TIM2_CH2
-
EVENTOUT
-
-
PB4
SPI1_MISO
-
EVENTOUT
-
-
-
-
PB5
SPI1_MOSI
-
LPTIM1_IN1
I2C1_SMBA
-
TIM21_CH1
-
PB6
USART2_TX
I2C1_SCL
LPTIM1_ETR
-
-
TIM2_CH3
LPUART1_TX
PB7
USART2_RX
I2C1_SDA
LPTIM1_IN2
-
-
TIM2_CH4
LPUART1_RX
Port
Port B
Pin descriptions
34/91
Table 11. Alternate functions (continued)
DS12323 Rev 3
STM32L010F4/K4
STM32L010F4/K4
5
Memory mapping
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
DS12323 Rev 3
35/91
35
Electrical characteristics
STM32L010F4/K4
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 5.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 6.
Figure 5. Pin loading conditions
Figure 6. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
ai17851c
36/91
DS12323 Rev 3
ai17852c
STM32L010F4/K4
6.1.6
Electrical characteristics
Power supply scheme
Figure 7. Power supply scheme
OUT
GP I/Os
IN
Level shifter
Standby-power circuitry
(OSC32,RTC,Wake-up
logic, RTC backup
registers)
IO
Logic
Kernel logic
(CPU,
Digital &
Memories)
VDD
VDD
Regulator
N × 100 nF
+ 1 × 10 μF
VSS
VDDA
VDDA
100 nF
+ 1 μF
ADC
Analog:
RC,PLL,….
VSSA
MSv48106V1
1. VSSA is internally connected to VSS on all packages.
6.1.7
Current consumption measurement
Figure 8. Current consumption measurement scheme
VDDA
IDD
NxVDD
N × 100 nF
+ 1 × 10 μF
NxVSS
MSv34711V1
DS12323 Rev 3
37/91
81
Electrical characteristics
6.2
STM32L010F4/K4
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics, and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.
Table 12. Voltage characteristics
Symbol
VDD -VSS
VIN(2)
Ratings
Min
Max
–0.3
4.0
Input voltage on FT pin
VSS - 0.3
VDD + 4.0
Input voltage on TC pins
VSS - 0.3
4.0
Input voltage on BOOT0
VSS
VDD + 4.0
VSS - 0.3
4.0
-
50
-
300
Variations between all different ground pins
-
50
Electrostatic discharge voltage (human body model)
see Section 6.3.11
External main supply voltage
(including VDDA, VDD)(1)
Input voltage on any other pin
|∆VDD|
|VDDA-VDDx|
|∆VSS|
VESD(HBM)
Variations between different VDDx power pins
Variations between any VDDx and VDDA power
pins(3)
Unit
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2.
VIN maximum must always be respected. Refer to Table 13 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and device operation. its value does not need to respect this rule.
38/91
DS12323 Rev 3
V
mV
V
STM32L010F4/K4
Electrical characteristics
Table 13. Current characteristics
Symbol
Ratings
Max.
ΣIVDD(2)
Total current into sum of all VDD power lines (source)(1)
105
ΣIVSS(2)
Total current out of sum of all VSS ground lines (sink)
(1)
105
ΣIVDDIO2
Total current into sum of all VDDIO2 power lines (source)
25
IVDD(PIN)
Maximum current into each VDD power pin (source)(1)
100
IVSS(PIN)
IIO
ΣIIO(PIN)
IINJ(PIN)
ΣIINJ(PIN)
Maximum current out of each VSS ground pin (sink)
(1)
Unit
100
Output current sunk by any I/O and control pin
16
Output current sourced by any I/O and control pin
-16
Total output current sunk by sum of all I/Os and control pins(2)
mA
90
(2)
-90
Total output current sourced by sum of all I/Os and control pins
−5/+0(3)
Injected current on FT, RST and B pins
Injected current on TC pin
±5(4)
Total injected current (sum of all I/O and control pins)(5)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 12 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 12 for the maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DS12323 Rev 3
Value
Unit
–65 to +150
°C
150
°C
39/91
81
Electrical characteristics
STM32L010F4/K4
6.3
Operating conditions
6.3.1
General operating conditions
Table 15. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
VDD
Standard operating voltage
-
1.8
3.6
V
VDDA
Analog operating voltage
(all features)
Must be the same voltage as VDD(1)
1.8
3.6
V
2.0 V ≤ VDD ≤ 3.6 V
–0.3
5.5
1.8 V ≤ VDD ≤ 2.0 V
–0.3
5.2
Input voltage on FT and RST pins(2)
VIN
Input voltage on BOOT0 pin
-
0
5.5
Input voltage on TC pin
-
–0.3
VDD+ 0.3
PD
Power dissipation at TA = 85 °C(3)
TSSOP20/
LQFP32
-
270/
333
TA
Temperature range
-
–40
85
TJ
Junction temperature range (range 6)
–40 °C ≤ TA ≤ 85 °
–40
105
MHz
V
mW
°C
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and normal operation.
2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 14: Thermal characteristics
on page 39).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 15.
Table 16. Embedded reset and power control block characteristics
Symbol
Parameter
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1)
40/91
Reset temporization
Conditions
Min
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
DS12323 Rev 3
Unit
µs/V
ms
STM32L010F4/K4
Electrical characteristics
Table 16. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brownout reset threshold 0
VBOR1
Brownout reset threshold 1
VBOR2
Brownout reset threshold 2
VBOR3
Brownout reset threshold 3
VBOR4
Brownout reset threshold 4
Vhyst
Hysteresis voltage
Conditions
Min
Typ
Max
Falling edge
1
1.5
1.8
Rising edge
1.3
1.5
1.8
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
BOR0 threshold
-
40
-
All BOR thresholds excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results, not tested in production.
6.3.3
Embedded internal reference voltage
The parameters given in Table 18 are based on characterization results, unless otherwise
specified.
Table 17. Embedded internal reference voltage calibration values
Calibration value name
VREFINT_CAL
Description
Memory address
Raw data acquired at temperature of 25°C, VDDA= 3 V
0x1FF8 0078 - 0x1FF8 0079
Table 18. Embedded internal reference voltage(1)
Symbol
VREFINT out(2)
Parameter
Internal reference voltage
Conditions
–40 °C < TJ < +85 °C
Min
Typ
Max
Unit
1.202
1.224
1.242
V
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA voltage during VREFINT
factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Accuracy of factory-measured
VREFINT value(3)
Including uncertainties
due to ADC and VDDA
values
-
-
±5
mV
–40 °C < TJ < +85 °C
-
25
100
0 °C < TJ < +50 °C
-
-
20
1000 hours, T= 25 °C
-
-
1000
TCoeff(4)
Temperature coefficient
ACoeff(4)
Long-term stability
DS12323 Rev 3
ppm/°C
ppm
41/91
81
Electrical characteristics
STM32L010F4/K4
Table 18. Embedded internal reference voltage(1) (continued)
Symbol
Parameter
VDDCoeff(4)
Voltage coefficient
Conditions
3.0 V < VDDA < 3.6 V
Min
Typ
Max
Unit
-
-
2000
ppm/V
TS_vrefint(4)(5)
ADC sampling time when
reading the internal reference
voltage
-
5
10
-
µs
TADC_BUF(4)
Startup time of reference
voltage buffer for ADC
-
-
-
10
µs
IBUF_ADC(4)
Consumption of reference
voltage buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(4)
VREF_OUT output current(6)
-
-
-
1
µA
CVREF_OUT(4)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference
voltage buffer for VREF_OUT
-
-
730
1200
nA
VREFINT_DIV1(4)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(4)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(4)
3/4 reference voltage
-
74
75
76
ILPBUF(4)
%
VREFINT
1. Refer to Table 30: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
4. Guaranteed by design, not tested in production.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 8: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 15: General operating
conditions unless otherwise specified.
42/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
The MCU is placed under the following conditions:
•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time and prefetch is adjusted depending on fHCLK frequency
and voltage range to provide the best CPU performance unless otherwise specified.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAPB
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass is used)
•
The HSE user clock is applied to CK_IN. It follows the characteristic specified in
Table 32: High-speed external user clock characteristics
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise
Table 19. Current consumption in Run mode, code with data processing
running from Flash memory
Symbol
Parameter
Conditions
Typ
Max
1
140
180
2
245
290
4
460
540
4
0.56
0.65
8
1.1
1.3
16
2.1
2.4
8
1.3
1.6
16
2.6
3
32
5.3
6.5
0.065
34.5
54
0.524
86
120
4.2
505
560
Range 2,
VCORE = 1.5 V
VOS[1:0] = 10,
16
2.2
2.6
Range 1,
VCORE = 1.8 V
VOS[1:0] = 01
32
Range 3,
VCORE = 1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to 16 MHz
included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(1)
Range 2,
VCORE = 1.5 V
VOS[1:0] = 10,
Range 1,
VCORE = 1.8 V
VOS[1:0] = 01
Supply current
IDD (Run in Run mode,
from Flash code executed
memory)
from Flash
memory
Range 3,
VCORE = 1.2 V
VOS[1:0] = 11
MSI clock
HSI clock
fHCLK
(MHz)
Unit
µA
mA
µA
mA
5.4
5.9
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
DS12323 Rev 3
43/91
81
Electrical characteristics
STM32L010F4/K4
Table 20. Current consumption in Run mode vs code type, code with data processing
running from Flash memory
Symbol
IDD
(Run
from
Flash
memory)
Parameter
Supply
current in
Run mode,
code
executed
from Flash
memory
Conditions
fHCLK
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(1)
Typ
Dhrystone
460
CoreMark
440
Fibonacci
4 MHz
330
while(1)
305
while(1), prefetch OFF
320
Dhrystone
5.4
CoreMark
4.9
Range 1,
VCORE = 1.8 V
VOS[1:0] = 01
Fibonacci
32 MHz
5
Unit
µA
mA
while(1)
4.35
while(1), prefetch OFF
3.7
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Figure 9. IDD vs VDD, Run mode, code running from Flash memory, Range 2, HSI, 1 ws
MSv48132V1
44/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Figure 10. IDD vs VDD, Run mode, code running from Flash memory, Range 2, HSE bypass, 1 ws
MSv48133V1
Table 21. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
fHCLK
Typ
Max(1)
1
115
140
2
205
240
4
385
420
4
0.48
0.55
8
0.935
1.1
16
1.8
2
8
1.1
1.4
16
2.1
2.5
32
4.5
4.9
0.065
22
38
0.524
67
91
4.2
415
450
Range 2,
VCORE = 1.5 V,
VOS[1:0] = 10
16
1.95
2.2
Range 1,
VCORE = 1.8 V,
VOS[1:0] = 01
32
Conditions
(MHz)
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
fHSE = fHCLK up to 16 MHz,
Range 2,
included
Supply current in
VCORE = 1.5 ,V,
Run mode, code fHSE = fHCLK/2 above 16 MHz VOS[1:0] = 10
(2)
IDD (Run
executed from (PLL ON)
from
RAM, Flash
RAM)
Range 1,
memory
VCORE = 1.8 V,
switched OFF
VOS[1:0] = 01
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
MSI clock
Supply current in
Run mode, code
IDD (Run
executed from
from
HSI16 clock source (16 MHz)
RAM, Flash
RAM)
memory
switched OFF
Unit
µA
mA
µA
mA
4.7
5.2
1. Guaranteed by characterization results at 85 °C, not tested in production, unless otherwise specified.
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 22. Current consumption in Run mode vs code type, code with data processing
running from RAM(1)
Symbol
Parameter
Conditions
fHCLK
Typ
Dhrystone
Supply current in
Run mode, code
IDD (Run
executed from
from
RAM, Flash
RAM)
memory switched
OFF
fHSE = fHCLK up to 16 MHz,
included,
fHSE = fHCLK/2 above 16 MHz
(PLL ON)(2)
385
Range 3
CoreMark
VCORE = 1.2 V
VOS[1:0] = 11 Fibonacci
-(3)
4 MHz
350
while(1)
340
Dhrystone
4.5
Range 1
CoreMark
VCORE = 1.8 V
VOS[1:0] = 01 Fibonacci
Unit
-(3)
32 MHz
4.2
while(1)
µA
mA
3
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. CoreMark code is unable to run from RAM since the RAM size is only 2 Kbytes.
Table 23. Current consumption in Sleep mode
Symbol
Parameter
fHCLK
Typ
Max(1)
1
36.5
70
2
58
95
4
100
150
4
125
170
8
230
300
16
450
540
8
275
350
16
555
650
32
1350
1600
0.065
15.5
32
0.524
26.5
55
4.2
115
160
Range 2,
VCORE = 1.5 V,
VOS[1:0] = 10
16
585
670
Range 1,
VCORE = 1.8 V,
VOS[1:0] = 01
32
1500
1700
Conditions
(MHz)
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
fHSE = fHCLK up to 16 MHz
included,
fHSE = fHCLK/2 above 16
MHz (PLL ON)(2)
IDD
(Sleep)
Range 1,
VCORE = 1.8 V,
VOS[1:0] = 01
Supply current
in Sleep
mode, Flash
memory OFF
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
MSI clock
HSI16 clock source (16
MHz)
46/91
Range 2,
VCORE = 1.5 V,
VOS[1:0] = 10
DS12323 Rev 3
Unit
µA
STM32L010F4/K4
Electrical characteristics
Table 23. Current consumption in Sleep mode (continued)
Symbol
Parameter
fHCLK
Typ
Max(1)
1
49
88
2
69
120
4
115
190
4
135
200
8
240
340
16
460
650
8
290
400
16
565
750
32
1350
1900
0.065
26.5
46
0.524
38.5
70
4.2
125
190
Range 2,
VCORE = 1.5 V,
VOS[1:0] = 10
16
600
760
Range 1,
VCORE = 1.8 V,
VOS[1:0] = 01
32
1500
1850
Conditions
(MHz)
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
fHSE = fHCLK up to 16 MHz
included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(2)
IDD
(Sleep)
Range 2,
CORE = 1.5 V,
VOS[1:0] = 10
Range 1,
VCORE = 1.8 V,
VOS[1:0] = 01
Supply current
in Sleep
mode, Flash
memory ON
Range 3,
VCORE = 1.2 V,
VOS[1:0] = 11
MSI clock
HSI16 clock source (16
MHz)
Unit
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Table 24. Current consumption in Low-power run mode
Symbol
Parameter
Conditions
MSI clock = 65 KHz
fHCLK = 32 KHz
IDD
(LP run)
Supply
current in
Low-power
run mode
All peripherals OFF,
code executed from MSI clock = 65 KHz
RAM, Flash memory fHCLK = 65 KHz
switched OFF, VDD
from 1.8 V to 3.6 V MSI
clock = 131 KHz
fHCLK = 131 KHz
MSI clock = 65 KHz
fHCLK = 32 KHz
All peripherals OFF,
code executed from
Flash memory, VDD
from 1.8 V to 3.6 V
MSI clock = 65 KHz
fHCLK = 65 KHz
MSI
clock = 131 KHz
fHCLK = 131 KHz
Typ
Max(1) Unit
TA = -40 °C to 25 °C
5.7
8.1
TA = 85 °C
6.5
9
TA =-40 °C to 25 °C
8.7
11
TA = 85 °C
9.5
12
TA = -40 °C to 25 °C
17
19
TA = 55 °C
17
19.5
TA = 85 °C
17.5
20
TA = -40 °C to 25 °C
18
22
TA = 85 °C
20
24
TA = -40 °C to 25 °C
22
25
TA = 85 °C
24
27
TA = -40 °C to 25 °C
32
35
TA = 55 °C
32.5
35
TA = 85 °C
34
37
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
Figure 11. IDD vs VDD, Low-power run mode executed from RAM, Range 3, MSI at 65 KHz, 0 ws
MSv48134V1
48/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 25. Current consumption in Low-power sleep mode
Symbol
Parameter
Typ
Max(1)
TA = -40 °C to 25 °C
2.5(2)
-
MSI clock = 65 KHz
fHCLK = 32 KHz
Flash ON
TA = -40 °C to 25 °C
13
19
TA = 85 °C
15.5
20
MSI clock = 65 KHz
fHCLK = 65 KHz
Flash ON
TA = -40 °C to 25 °C
13.5
19
16
20
MSI
clock = 131 KHz
fHCLK = 131 KHz
Flash ON
TA = -40 °C to 25 °C
15.5
21
TA = 55 °C
17
22
TA = 85 °C
18
23
Conditions
MSI clock = 65 KHz
fHCLK = 32 KHz
Flash OFF
IDD
(LP Sleep)
Supply
All peripherals
current in
OFF, VDD from
Low-power
1.8 V to 3.6 V
sleep mode
TA = 85 °C
Unit
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. In low-power modes, only the static Flash memory power consumption applies (~13 µA) when Flash is ON (independent of
clock speed).
Figure 12. IDD vs VDD, Stop mode with RTC enabled and running from LSE on low drive
MSv48135V1
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Figure 13. IDD vs VDD, Stop mode with RTC disabled, all clocks off
MSv48136V1
Table 26. Typical and maximum current consumptions in Stop mode
Symbol
IDD (Stop)
Typ
Max(1)
TA = –40°C to 25°C
0.34
0.99
TA = 55°C
0.43
1.9
TA= 85°C
0.94
4.2
Parameter
Conditions
Supply current in Stop mode
Unit
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
Table 27. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
TA = –40 °C to 25 °C
0.8
1.6
TA = 55 °C
0.9
1.8
TA= 85 °C
1
2
TA = -40 °C to 25 °C
0.23
0.6
TA = 55 °C
0.25
0.7
TA = 85 °C
0.36
1.7
Conditions
Independent watchdog
and LSI enabled
Supply current in Standby
IDD
(Standby)
mode
Independent watchdog
and LSI OFF
1. Guaranteed by characterization results, not tested in production, unless otherwise specified
50/91
DS12323 Rev 3
Unit
µA
STM32L010F4/K4
Electrical characteristics
Table 28. Average current consumption during wakeup
System
frequency
Current
consumption
during wakeup
HSI
1
HSI/4
0,7
MSI 4,2 MHz
0,7
MSI 1,05 MHz
0,4
MSI 65 KHz
0,1
Reset pin pulled down
-
0,21
BOR ON
-
0,23
With fast wakeup set
MSI 2,1 MHz
0,5
With fast wakeup disabled
MSI 2,1 MHz
0,12
Symbol
Parameter
IDD (wakeup from Stop)
IDD (Reset)
IDD (Power up)
IDD (wakeup from Standby)
Supply current during wakeup from
Stop mode
Unit
mA
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked OFF
–
with only one peripheral clocked ON
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Table 29. Peripheral current consumption in run or Sleep mode(1)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE = 1.8 V
VOS[1:0] = 01
Range 2,
VCORE = 1.5 V
VOS[1:0] = 10
Range 3,
VCORE = 1.2 V
VOS[1:0] = 11
Low-power
sleep and run
WWDG
2.5
2
1.6
2
LPUART1
8.3
7.2
5.4
7.2
I2C1
11
8.2
6.8
8.9
LPTIM1
14
11
8.7
11
10.5
8.5
6.4
8.5
8.5
6.8
5.4
7.1
5
3.9
3.3
4
SPI1
4.5
3.5
2.9
3.6
TIM21
6.8
6.1
4.5
5.6
DBGMCU
1.7
1.7
1.1
1.4
SYSCFG
2.5
2.4
1.6
2.3
GPIOA
7.6
6.3
4.9
6.5
GPIOB
Cortex-M0+
GPIOC
I/O port
CRC
5.1
4.1
3.2
4
1.1
0.7
0.6
0.8
Peripheral
APB1
TIM2
USART2
ADC1
APB2
(2)
1.5
(3)
0
0
0
5.3
4.2
3.5
4.8
All enabled
96
80
62
88
PWR
2.5
2
2
1
FLASH
DMA1
µA/MHz
(fHCLK)
1
0
AHB
Unit
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the
following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64 KHz (Lowpower run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in
both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. These values correspond to the Flash memory configuration interface consumption, which is negligible. To assess true
Flash memory consumption, compare relevant figures, like for example Table 19 and Table 21.
52/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 30. Peripheral current consumption in Stop and Standby mode
Symbol
Typical consumption, TA = 25 °C
Peripheral
IDD(BOR)
-
IREFINT
-
-
LSE low drive(1)
-
LPTIM1(2), input 100 Hz
VDD = 1.8 V
VDD = 3.0 V
0.6
1
Unit
3
0.01
µA
-
LPTIM1, input 1 MHz
8
9
-
LPUART1
0.025
0.03
-
RTC
0.1
0.19
1. LSE low drive consumption is the difference between an external clock on OSC32_IN and a quartz between
OSC32_IN and OSC32_OUT.
2. LPTIM peripheral cannot operate in Standby mode.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 15.
Table 31. Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP
Wakeup from Sleep mode
Conditions
Wakeup from Low-power sleep mode,
tWUSLEEP_LP
fHCLK = 262 KHz
Typ
Max
fHCLK = 32 MHz
7
8
fHCLK = 262 KHz
Flash enabled
7
8
fHCLK = 262 KHz
Flash switched OFF
9
10
DS12323 Rev 3
Unit
CPU
cycles
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81
Electrical characteristics
STM32L010F4/K4
Table 31. Low-power mode wakeup timings (continued)
Symbol
Parameter
Conditions
Typ
Max
fHCLK = fMSI = 4.2 MHz
5.1
8
fHCLK = fHSI = 16 MHz
5.1
7
fHCLK = fHSI/4 = 4 MHz
8.1
11
fHCLK = fMSI = 4.2 MHz
Voltage Range 1
5
8
fHCLK = fMSI = 4.2 MHz
Voltage Range 2
5
8
fHCLK = fMSI = 4.2 MHz
Voltage Range 3
5
8
fHCLK = fMSI = 2.1 MHz
7.4
13
fHCLK = fMSI = 1.05 MHz
14
23
fHCLK = fMSI = 524 KHz
28
38
fHCLK = fMSI = 262 KHz
51
65
fHCLK = fMSI = 131 KHz
99
120
fHCLK = fMSI = 65 KHz
196
260
fHCLK = fHSI = 16 MHz
5.1
7
fHCLK = fHSI/4 = 4 MHz
8.2
11
fHCLK = fHSI = 16 MHz
3.25
-
fHCLK = fHSI = 16 MHz
4.9
7
fHCLK = fHSI/4 = 4 MHz
7.9
10
fHCLK = fMSI = 4.2 MHz
4.8
8
Wakeup from Standby mode, FWU bit = 1 fHCLK = fMSI = 2.1 MHz
65
130
Wakeup from Standby mode, FWU bit = 0 fHCLK = fMSI = 2.1 MHz
2.2
3
Wakeup from Stop mode, regulator in
Run mode
Wakeup from Stop mode, regulator in
Low-power mode
tWUSTOP
Wakeup from Stop mode, regulator in
Low-power mode, HSI kept running in
Stop mode
Wakeup from Stop mode, regulator in
Low-power mode, code running from
RAM
tWUSTDBY
54/91
DS12323 Rev 3
Unit
µs
ms
STM32L010F4/K4
6.3.6
Electrical characteristics
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the input pin is a standard GPIO.The external clock signal has to respect
the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform
is shown in Figure 14.
Table 32. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min
Typ
Max
Unit
CSS is ON or
PLL used
1
8
32
MHz
CSS is OFF,
PLL not used
0
8
32
MHz
VHSEH
CK_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
CK_IN input pin low level voltage
VSS
-
0.3VDD
tw(HSE)
tw(HSE)
CK_IN high or low time
12
-
-
tr(HSE)
tf(HSE)
CK_IN rise or fall time
-
-
20
CK_IN input capacitance
-
2.6
-
pF
45
-
55
%
-
-
±1
µA
Cin(HSE)
ns
-
DuCy(HSE) Duty cycle
IL
CK_IN input leakage current
V
VSS ≤ VIN ≤ VDD
1. Guaranteed by design, not tested in production.
Figure 14. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
CK_IN
IL
tW(HSE)
t
THSE
EXTERNAL
CLOCK SOURCE
fHSE_ext
STM32L010
MSv48107V1
DS12323 Rev 3
55/91
81
Electrical characteristics
STM32L010F4/K4
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 15.
Table 33. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSE)
tw(LSE)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
CIN(LSE)
Typ
Max
Unit
-
32.768
1000
KHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
-
-
10
-
-
0.6
-
pF
-
45
-
55
%
VSS ≤ VIN ≤ VDD
-
-
±1
µA
OSC32_IN input capacitance
DuCy(LSE) Duty cycle
IL
Min
OSC32_IN input leakage current
1. Guaranteed by design, not tested in production.
Figure 15. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
tW(LSE)
t
TLSE
EXTER NAL
CLOCK SOURC E
fLSE_ext
OSC32_IN
IL
STM32Lxx
ai18233c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 34. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
56/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 34. HSE oscillator characteristics(1)
Symbol
Conditions
Min
Typ
Max
Unit
Oscillator frequency
-
1
-
25
MHz
RF
Feedback resistor
-
-
200
-
kΩ
Gm
Maximum critical crystal
transconductance
Startup
-
-
700
µA/V
VDD is stabilized
-
2
-
s
fOSC_IN
tSU(HSE)(2)
Parameter
Startup time
1. Guaranteed by design, not tested in production.
2. Guaranteed by characterization results. tSU(HSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (seeFigure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note Oscillator design guide for STM8AF/AL/S and
STM32 microcontrollers (AN2867) available from the ST website www.st.com.
Figure 16. HSE oscillator circuit diagram
fHSE to core
Rm
Lm
RF
CO
CL1
OSC_IN
Cm
gm
Resonator
Resonator
Consumption
control
STM32
OSC_OUT
CL2
ai18235b
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 KHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 35. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 35. LSE oscillator characteristics(1)
Symbol
fLSE
Gm
tSU(LSE)
(3)
Conditions(2)
Min(2)
Typ
Max
Unit
-
-
32.768
-
KHz
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
LSEDRV[1:0]= 01
medium low driving capability
-
-
0.75
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.7
LSEDRV[1:0]=11
higher driving capability
-
-
2.7
VDD is stabilized
-
2
-
Parameter
LSE oscillator
frequency
Maximum critical crystal
transconductance
Startup time
µA/V
s
1. Guaranteed by design, not tested in production.
2. Refer to the note and caution paragraphs below the table.
3. Guaranteed by characterization results, not tested in production. tSU(LSE) is the startup time measured from
the moment it is enabled (by software) to a stabilized 32.768 KHz oscillation is reached. This value is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. To
increase speed, address a lower-drive quartz with a high- driver mode.
Note:
For information on selecting the crystal, refer to the application note Oscillator design guide
for STM8AF/AL/S and STM32 microcontrollers (AN2867) available from the ST website
www.st.com.
Figure 17. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
programmable
amplifier
32.768 kHz
resonator
OSC32_OUT
CL2
MS30253V2
Note:
58/91
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS12323 Rev 3
STM32L010F4/K4
6.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 36 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 15.
High-speed internal 16 MHz (HSI16) RC oscillator
Table 36. 16 MHz HSI16 oscillator characteristics
Symbol
Parameter
fHSI16
TRIM
Frequency
(1)(2)
ACCHSI16
(2)
Conditions
Min
Typ
Max
Unit
-
16
-
MHz
-
±0.4
0.7
-
-
±1.5
VDDA = 3.0 V, TA = 25 °C
–1(3)
-
1(3)
VDDA = 3.0 V, TA = 0 to 55 °C
–1.5
-
1.5
VDDA = 3.0 V, TA = –10 to 70 °C
–2
-
2
VDDA = 3.0 V, TA = –10 to 85 °C
–2.5
-
2
VDDA = 1.8 V to 3.6 V
TA = -40 to 85 °C
–5.45
-
3.25
VDD = 3.0 V
Trimming code is not a multiple
HSI16 userof 16
trimmed resolution
Trimming code is a multiple of 16
Accuracy of the
factory-calibrated
HSI16 oscillator
%
HSI16 oscillator
startup time
-
-
3.7
6
µs
HSI16 oscillator
IDD(HSI16)(2) power
consumption
-
-
100
140
µA
tSU(HSI16)(2)
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
Figure 18. HSI16 minimum and maximum value versus temperature
DS12323 Rev 3
59/91
81
Electrical characteristics
STM32L010F4/K4
Low-speed internal (LSI) RC oscillator
Table 37. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI(1)
LSI frequency
26
38
56
KHz
DLSI(2)
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
–10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
tsu(LSI)(3)
IDD(LSI)
(3)
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
Multi-speed internal (MSI) RC oscillator
Table 38. MSI oscillator characteristics
Symbol
Typ
Max
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.8 V ≤ VDD ≤ 3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
Frequency after factory calibration, done
at VDD = 3.3 V and TA = 25 °C
fMSI
ACCMSI
IDD(MSI)
60/91
Parameter
(2)
MSI oscillator power consumption
DS12323 Rev 3
Condition
Unit
KHz
MHz
µA
STM32L010F4/K4
Electrical characteristics
Table 38. MSI oscillator characteristics (continued)
Symbol
tSU(MSI)
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
Condition
MSI oscillator startup time
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Typ
Max
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
6
Unit
µs
µs
MHz
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results, not tested in production.
6.3.8
PLL characteristics
The parameters given in Table 39 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 15.
Table 39. PLL characteristics
Value
Symbol
fPLL_IN
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Table 39. PLL characteristics (continued)
Value
Symbol
Parameter
Min
Typ
Max(1)
Unit
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
µA
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
RAM memory
Table 40. RAM and hardware registers
Symbol
VRM
Parameter
Data retention mode(1)
Conditions
Min
Typ
Max
Unit
Stop mode (or reset)
1.8
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
Flash memory and data EEPROM
Table 41. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.8
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
500
700
µA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming time for
word or half-page
IDD
1. Guaranteed by design, not tested in production.
62/91
DS12323 Rev 3
ms
STM32L010F4/K4
Electrical characteristics
Table 42. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC(2)
tRET(2)
Parameter
Cycling (erase / write)
Program memory
Conditions
Min(1)
Unit
10
TA = –40°C to 85 °C
Cycling (erase / write)
EEPROM data memory
kcycles
100
Data retention (program memory) after
10 kcycles at TA = 85 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 85 °C
30
TRET = +85 °C
years
30
1. Guaranteed by characterization results, not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 43. They are based on the EMS levels and classes
defined in application note AN1709.
Table 43. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin to induce
fHCLK = 32 MHz
a functional disturbance
conforms to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
DS12323 Rev 3
63/91
81
Electrical characteristics
STM32L010F4/K4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note Software techniques for
improving microcontrollers EMC performance (AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 44. EMI characteristics
Symbol Parameter
SEMI
6.3.11
Conditions
VDD = 3.3 V,
TA = 25 °C,
Peak level
compliant with
IEC 61967-2
Monitored
frequency band
Max vs. frequency range
(32 MHz voltage range 1)
0.1 to 30 MHz
–22
30 to 130 MHz
–7
130 MHz to 1GHz
–12
SAE EMI Level
1
Unit
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
64/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 45. ESD absolute maximum ratings
Conditions
Class
Maximum
value(1)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming
to ANSI/JEDEC JS-001
2
2000
Electrostatic discharge voltage
VESD(CDM)
(charge device model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1
C4
Symbol
VESD(HBM)
Ratings
Unit
V
500
1. Guaranteed by characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin.
•
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 46. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
TA = +85 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 47.
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Table 47. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
IINJ
Negative
injection
Positive
injection
Injected current on BOOT0
–0
NA(1)
Injected current on PA0, PA4, PA5,
PA11, PA12, PC15, PH0 and PH1
–5
0
Injected current on all FT pins
–5(2)
NA(1)
Injected current on any other pin
–5(2)
+5
Unit
mA
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under the conditions summarized in Table 15. All I/Os are CMOS and TTL
compliant.
Table 48. I/O static characteristics
Symbol
VIL
Input low level voltage
VIH
Input high level voltage
Vhys
I/O Schmitt trigger
voltage hysteresis (2)
Ilkg
RPU
66/91
Parameter
Input leakage current
(4)
Weak pull-up
equivalent resistor(5)
Conditions
Min
Typ
Max
TC, FT, RST I/Os
-
-
0.3VDD
BOOT0 pin
-
-
0.14VDD(1)
All I/Os except
BOOT0 pin
0.7 VDD
-
-
Standard I/Os
-
10% VDD
(3)
-
BOOT0 pin
-
0.01
-
VSS ≤ VIN ≤ VDD
All I/Os except
PA11, PA12 and
BOOT0 pins
-
-
±50
VSS ≤ VIN ≤ VDD
PA11, PA12 pins
-
-
–50/+250
VDD ≤ VIN ≤ 5 V All
I/Os except PA11,
PA12 and BOOT0
pins
-
-
200
VDD ≤ VIN ≤ 5 V
PA11, PA12 and
BOOT0 pins
-
-
10
µA
VIN = VSS
25
45
65
kΩ
DS12323 Rev 3
Unit
V
nA
STM32L010F4/K4
Electrical characteristics
Table 48. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
25
45
65
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by characterization, not tested in production
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not
tested in production.
3. With a minimum of 200 mV. Guaranteed by characterization results, not tested in production.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
Figure 19. VIH/VIL versus VDD (CMOS I/Os)
VIL/VIH (V)
in =
pins
9 (all
+0.5 , PH0/1
DD
V
9
5
1
= 0.3
, PC
V IHmin t BOOT0 0.38 for
+
p
exce = 0.45V DD H0/1
,P
V IHmin 0, PC15
T
BOO
0.7V D
D
irem
qu
d re
ndar
sta
MOS
V IHm
ents
C
VIHmin 2.0
V DD
V ILmax
1.3
= 0.3
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MSv34789V1
Figure 20. VIH/VIL versus VDD (TTL I/Os)
VIL/VIH (V)
pins
9 (all 0/1
+0.5
9V DD C15, PH
.3
0
=
,P
V IHmin t BOOT0 0.38 for
+
p
exce = 0.45V DD PH0/1
,
V IHmin 0, PC15
T
O
BO
TTL standard requirements VIHmin = 2 V
VIHmin 2.0
V DD
V ILmax
1.3
= 0.3
Input range not
guaranteed
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MSv34790V1
DS12323 Rev 3
67/91
81
Electrical characteristics
STM32L010F4/K4
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard VOL/VOH specifications given in Table 49.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 13).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 13).
Output voltage levels
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15. All I/Os are CMOS and TTL compliant.
Table 49. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
CMOS port(2),
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
-
0.4
VDD - 0.4
-
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL (1)
Output low level voltage for an I/O pin
TTL port(2),
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
-
0.4
Output high level voltage for an I/O pin
TTL port(2),
IIO = –6mA
2.7 V ≤ VDD ≤ 3.6 V
2.4
-
VOL(1)(4)
Output low level voltage for an I/O pin
IIO = +15 mA
2.7 V ≤ VDD ≤ 3.6 V
-
1.3
VOH(3)(4)
Output high level voltage for an I/O pin
IIO = –15 mA
2.7 V ≤ VDD ≤ 3.6 V
VDD - 1.3
-
VOL(1)(4)
Output low level voltage for an I/O pin
IIO = +4 mA
1.8 V ≤ VDD ≤ 3.6 V
-
0.45
VOH(3)(4)
Output high level voltage for an I/O pin
IIO = –4 mA
V - 0.45
1.8 V ≤ VDD ≤ 3.6 V DD
VOH
(3)(4)
Unit
V
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 13. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN).
4. Guaranteed by characterization results, not tested in production.
68/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 21 and
Table 50, respectively.
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15.
Table 50. I/O AC characteristics(1)(2)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(4)
00
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out Maximum frequency(4)
01
tf(IO)out
tr(IO)out
Output rise and fall time
Fmax(IO)out Maximum frequency(4)
10
tf(IO)out
tr(IO)out
Output rise and fall time
DS12323 Rev 3
Conditions
Min Max(3) Unit
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
100
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
320
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
0.6
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
30
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
65
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
2
CL = 50 pF,
VDD = 2.7 V to 3.6 V
-
13
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
400
KHz
ns
MHz
ns
MHz
ns
28
69/91
81
Electrical characteristics
STM32L010F4/K4
Table 50. I/O AC characteristics(1)(2) (continued)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
Conditions
(4)
Fmax(IO)out Maximum frequency
11
-
tf(IO)out
tr(IO)out
Output rise and fall time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
Min Max(3) Unit
CL = 30 pF,
VDD = 2.7 V to 3.6 V
-
35
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
10
CL = 30 pF,
VDD = 2.7 V to 3.6 V
-
6
CL = 50 pF,
VDD = 1.8 V to 2.7 V
-
17
8
-
-
MHz
ns
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a
description of GPIO Port configuration register.
2. BOOT0/PB9 maximum input frequency is 10 KHz (1.8 V < VDD < 2.7 V) and 5 MHz (2.7 V < VDD < 3.6 V).
3. Guaranteed by design. Not tested in production.
4. The maximum frequency is defined in Figure 21.
Figure 21. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON CL
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.
ai14131d
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU , except when it is internally driven low (see Table 51).
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15.
70/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 51. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)(1)
NRST input low
level voltage
-
-
-
0.3VDD
VIH(NRST)(1)
NRST input high
level voltage
-
0.39VDD+ 0.59
-
-
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
-
IOL = 1.5 mA
1.8 V < VDD < 2.7 V
-
-
-
-
10%VDD(2)
-
mV
VOL(NRST)(1)
NRST output low
level voltage
NRST Schmitt
Vhys(NRST)(1) trigger voltage
hysteresis
V
0.4
RPU
Weak pull-up
equivalent
resistor(3)
VIN = VSS
25
45
65
kΩ
VF(NRST)(1)
NRST input
filtered pulse
-
-
-
50
ns
VNF(NRST)(1)
NRST input not
filtered pulse
-
350
-
-
ns
1. Guaranteed by design, not tested in production.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
Figure 22. Recommended NRST pin protection
External reset circuit(1)
NRST(2)
VDD
RPU
Internal reset
Filter
0.1 μF
STM32Lxx
ai17854c
1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 51. Otherwise the reset will not be taken into account by the device.
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 52 are values derived from tests
performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions
summarized in Table 15: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
DS12323 Rev 3
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81
Electrical characteristics
STM32L010F4/K4
Table 52. ADC characteristics
Symbol
VDDA
IDDA (ADC)
fADC
fS(3)
fTRIG(3)
Parameter
Analog supply voltage for
ADC ON
Conditions
Min
Typ
Max
-
-
-
3.6
-
3.6
-
(1)
1.8
Unit
V
Current consumption of the
ADC on VDDA
1.14 Msps
-
200
-
10 ksps
-
40
-
Current consumption of the
ADC on VDD(2)
1.14 Msps
-
70
-
10 ksps
-
1
-
Voltage scaling Range 1
0.14
-
16
Voltage scaling Range 2
0.14
-
8
Voltage scaling Range 3
0.14
-
4
-
0.01
-
1.14
MHz
fADC = 16 MHz,
16-bit resolution
-
-
941
KHz
-
-
-
17
1/fADC
ADC clock frequency
Sampling rate
External trigger frequency
µA
MHz
VAIN
Conversion voltage range
-
0
-
VDDA
V
RAIN(3)
External input impedance
See Equation 1 and
Table 53 for details
-
-
50
kΩ
-
-
-
1
kΩ
-
-
-
8
pF
RADC(3)(4) Sampling switch resistance
CADC(3)
tCAL(3)
WLATENCY
tlatr(3)
JitterADC
tS(3)
72/91
Internal sample and hold
capacitor
Calibration time
ADC_DR register write
latency
Trigger conversion latency
ADC jitter on trigger
conversion
Sampling time
fADC = 16 MHz
5.2
µs
-
83
1/fADC
ADC clock = HSI16
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
fADC = fPCLK/2 = 16 MHz
0.266
µs
fADC = fPCLK/2
8.5
1/fPCLK
fADC = fPCLK/4 = 8 MHz
0.516
µs
fADC = fPCLK/4
16.5
1/fPCLK
fADC = fHSI16 = 16 MHz
0.252
-
0.260
µs
fADC = fHSI16
-
1
-
1/fHSI16
fADC = 16 MHz
0.093
-
10.03
µs
-
1.5
-
239.5
1/fADC
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 52. ADC characteristics (continued)
Symbol
Parameter
tSTAB(3)
Power-up time
tConV(3)
Total conversion time
(including sampling time)
Conditions
Min
Typ
Max
Unit
-
0
0
1
µs
fADC = 16 MHz
0.875
-
10.81
µs
14 to 173 (tS for sampling +12.5 for
successive approximation)
-
1/fADC
1. VDDA minimum value can be decreased in specific temperature conditions.
Refer to Table 53: RAIN max for fADC = 16 MHz.
2. A current consumption proportional to the APB clock frequency has to be added
Refer to Table 29: Peripheral current consumption in run or Sleep mode.
3. Guaranteed by design, not tested in production.
4. Standard channels have an extra protection resistance which depends on supply voltage.
Refer to Table 53: RAIN max for fADC = 16 MHz.
Equation 1: RAIN max formula
TS
- – R ADC
R AIN < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The presented formula above (Equation 1) is a representation of an hypothetical ideal ADC
and illustrates how the parameters influence each other. It is not to be used for computation
of actual values.
Table 53. RAIN max for fADC = 16 MHz(1)
Ts (cycles)
tS (µs)
RAIN max for fast
channels (kΩ)
1.5
0.09
3.5
RAIN max for standard channels (kΩ)
VDD > 2.7 V
VDD > 2.4 V
VDD > 2.0 V
VDD > 1.8 V
0.5
< 0.1
NA
NA
NA
0.22
1
0.2
< 0.1
NA
NA
7.5
0.47
2.5
1.7
1.5
< 0.1
NA
12.5
0.78
4
3.2
3
1
NA
19.5
1.22
6.5
5.7
5.5
3.5
NA
39.5
2.47
13
12.2
12
10
NA
79.5
4.97
27
26.2
26
24
< 0.1
160.5
10.03
50
49.2
49
47
32
1. Guaranteed by design.
DS12323 Rev 3
73/91
81
Electrical characteristics
STM32L010F4/K4
Table 54. ADC accuracy(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
ET
Total unadjusted error
-
2
4
EO
Offset error
-
1
2.5
EG
Gain error
-
1
2
EL
Integral linearity error
-
1.5
2.5
ED
Differential linearity error
-
1
1.5
10.2
11
-
11.3
12.1
-
Effective number of bits
1.8 V < VDDA < 3.6 V,
Range 1, 2 and 3
ENOB
Effective number of bits (16-bit mode
oversampling with ratio =256)(4)
SINAD
Signal-to-noise distortion
62
67.8
-
Signal-to-noise ratio
63
68
-
SNR
Signal-to-noise ratio (16-bit mode
oversampling with ratio =256)(4)
70
76
-
THD
Total harmonic distortion
-
-81
-68.5
Unit
LSB
bits
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative current injection: Injecting negative current on any of the standard (non-robust) analog input
pins must be avoided as it significantly reduces the accuracy of the conversion being performed on another analog input. It
is recommended to add a Schottky diode (pin to ground) to standard analog pins that may potentially inject negative
current.
Any positive current injection within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.
Figure 23. ADC accuracy characteristics
VSSA
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
ET
(3)
7
(1)
6
5
EO
EL
4
3
ED
2
1 LSB IDEAL
1
0
1
2
3
4
5
6
7
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
4093 4094 4095 4096
VDDA
MS19880V2
74/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Figure 24. Typical connection diagram using the ADC
VDDA
VT
RAIN(1)
VAIN
AINx
Cparasitic
VT
Sample and hold ADC
converter
RADC
12-bit
converter
IL±50nA
CADC
MSv34712V1
1. Refer to Table 52: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC must be reduced.
6.3.16
Timer characteristics
TIM timer characteristics
The parameters given in the Table 55 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 55. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
31.25
-
ns
fTIMxCLK = 32 MHz
Timer external clock frequency on
CH1 to CH4
fTIMxCLK = 32 MHz
0
fTIMxCLK/2
MHz
0
16
MHz
Timer resolution
-
-
16
bit
16-bit counter clock period when
internal clock is selected (timer’s
prescaler disabled)
-
1
65536
tTIMxCLK
0.0312
2048
µs
-
65536 × 65536
tTIMxCLK
-
134.2
s
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz
fTIMxCLK = 32 MHz
1. TIMx is used as a general term to refer to the TIM2, TIM21 and TIM22 timers.
DS12323 Rev 3
75/91
81
Electrical characteristics
6.3.17
STM32L010F4/K4
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for standard-mode (Sm) with a bit rate up to 100 kbit/s.
The I2C timing requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual for details) and when the I2CCLK frequency is
greater than 2 MHz. The SDA and SCL I/O requirements are met with the following
restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as opendrain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present.
All I2C SDA and SCL I/Os embed an analog filter (see Table 56 for the analog filter
characteristics).
Table 56. I2C analog filter characteristics(1)
Symbol
Parameter
Conditions
Min
Maximum pulse width of spikes that are
suppressed by the analog filter
Range 2
Range 3
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
76/91
DS12323 Rev 3
Unit
100(3)
Range 1
tAF
Max
50(2)
-
ns
STM32L010F4/K4
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 15.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 57. SPI characteristics in voltage Range 1 (1)
Symbol
Parameter
Conditions
Min
Typ
-
-
Slave mode transmitter
1.71 < VDD < 3.6V
-
-
12(2)
Slave mode transmitter
2.7 < VDD < 3.6V
-
-
16(2)
Master mode
Slave mode receiver
fSCK
1/tc(SCK)
SPI clock frequency
Max
16
16
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
Tpclk - 2 Tpclk
Master mode
3
-
-
Slave mode
3
-
-
Master mode
3.5
-
-
Slave mode
0
-
-
Data output access time
Slave mode
15
-
36
tdis(SO)
Data output disable time
Slave mode
10
-
30
Slave mode, 1.71 < VDD < 3.6V
-
14
35
Slave mode, 2.7 < VDD < 3.6V
-
14
20
Master mode
-
4
6
Slave mode
10
-
-
Master mode
3
-
-
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
MHz
%
Tpclk + 2
ta(SO
tv(SO)
Unit
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
DS12323 Rev 3
77/91
81
Electrical characteristics
STM32L010F4/K4
Table 58. SPI characteristics in voltage Range 2 (1)
Symbol
Parameter
Conditions
Min
Typ
Master mode
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode transmitter
1.8 V < VDD < 3.6 V
Max
8
-
-
Slave mode transmitter
2.7 V < VDD < 3.6 V
8
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk - 2
Tpclk
Tpclk + 2
Master mode
3
-
-
Slave mode
3
-
-
Master mode
6
-
-
Slave mode
2
-
-
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO
Data output access time
Slave mode
18
-
52
tdis(SO)
Data output disable time
Slave mode
12
-
42
tv(SO)
Data output valid time
Slave mode
-
16
33
Master mode
-
4
6
Slave mode
11
-
-
Master mode
3
-
-
tv(MO)
th(SO)
Data output hold time
MHz
8(2)
Duty(SCK)
tsu(MI)
Unit
%
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
78/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Table 59. SPI characteristics in voltage Range 3 (1)
Symbol
Parameter
fSCK
1/tc(SCK)
SPI clock frequency
Duty(SCK)
Duty cycle of SPI clock
frequency
tsu(NSS)
Min
Typ
-
-
Slave mode
30
50
70
NSS setup time
Slave mode, SPI presc = 2
4Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk - 2
Tpclk
Tpclk + 2
Master mode
3
-
-
Slave mode
3
-
-
Master mode
16
-
-
Slave mode
14
-
-
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
Conditions
Master mode
Slave mode
Max
2
2(2)
ta(SO
Data output access time
Slave mode
30
-
70
tdis(SO)
Data output disable time
Slave mode
40
-
80
tv(SO)
Data output valid time
Slave mode
-
26.5
47
Master mode
-
4
6
Slave mode
20
-
-
Master mode
3
-
-
tv(MO)
th(SO)
Data output hold time
Unit
MHz
%
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
DS12323 Rev 3
79/91
81
Electrical characteristics
STM32L010F4/K4
Figure 25. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
SCK input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
First bit OUT
MISO output
tf(SCK)
Next bits OUT
tdis(SO)
Last bit OUT
th(SI)
tsu(SI)
First bit IN
MOSI input
Next bits IN
Last bit IN
MSv41658V1
Figure 26. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
ta(SO)
tw(SCKL)
tf(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
tv(SO)
First bit OUT
tsu(SI)
MOSI input
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
Last bit OUT
th(SI)
First bit IN
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
80/91
DS12323 Rev 3
STM32L010F4/K4
Electrical characteristics
Figure 27. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MSB IN
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MI)
MOSI
OUTPUT
MSB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136d
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DS12323 Rev 3
81/91
81
Package information
7
STM32L010F4/K4
Package information
In order to meet environmental requirements, ST offers the STM32L010F4/K4 in different
grades of ECOPACK packages, depending on their level of environmental compliance.
ECOPACK specifications, grade definitions and product status are available at www.st.com.
ECOPACK is an ST trademark.
7.1
TSSOP20 package information
Figure 28. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
D
20
11
c
E1 E
1
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
10
PIN 1
IDENTIFICATION
k
aaa C
A1
A
A2
b
L
L1
e
YA_ME_V3
1. Drawing is not to scale.
Table 60. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
inches(1)
millimeters
Symbol
82/91
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.200
-
-
0.0472
A1
0.050
-
0.150
0.0020
-
0.0059
A2
0.800
1.000
1.050
0.0315
0.0394
0.0413
b
0.190
-
0.300
0.0075
-
0.0118
c
0.090
-
0.200
0.0035
-
0.0079
D(2)
6.400
6.500
6.600
0.2520
0.2559
0.2598
E
6.200
6.400
6.600
0.2441
0.2520
0.2598
E1(3)
4.300
4.400
4.500
0.1693
0.1732
0.1772
e
-
0.650
-
-
0.0256
-
DS12323 Rev 3
STM32L010F4/K4
Package information
Table 60. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
-
8°
0°
-
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 29. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
0.25
6.25
20
11
1.35
0.25
7.10 4.40
1.35
1
10
0.40
0.65
YA_FP_V1
1. Dimensions are expressed in millimeters.
DS12323 Rev 3
83/91
89
Package information
STM32L010F4/K4
Device marking for TSSOP20
Figure 30 gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks depending on supply-chain operations, are not
indicated below.
Figure 30. TSSOP20 marking example (package top view)
Product identification(1)
32L010F4P6
Pin 1
indentifier
Date code
Y
WW
Revision code
R
MSv48142V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
84/91
DS12323 Rev 3
STM32L010F4/K4
LQFP32 package information
Figure 31. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
c
A2
A1
A
SEATING
PLANE
C
0.25 mm
ccc
GAUGE PLANE
C
K
D
A1
L
D1
L1
D3
24
17
25
16
32
9
PIN 1
IDENTIFICATION
1
E
E1
E3
b
7.2
Package information
8
e
5V_ME_V2
1. Drawing is not to scale.
DS12323 Rev 3
85/91
89
Package information
STM32L010F4/K4
Table 61. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 32. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
1. Dimensions are expressed in millimeters.
86/91
DS12323 Rev 3
5V_FP_V2
STM32L010F4/K4
Package information
Device marking for LQFP32
Figure 33 gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks depending on supply-chain operations, are not
indicated below.
Figure 33. LQFP32 marking example (package top view)
Product identification(1)
STM32L
010K4T6
Date code
Y WW
Revision code
Pin 1
indentifier
R
MSv48143V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
7.3
Thermal characteristics
The maximum chip-junction temperature, TJ max, in °C, may be calculated using the
following equation:
TJ max = TA max + (PD max × ϴJA)
Where:
•
TA max is the maximum ambient temperature in °C
•
ϴJA is the package junction-to-ambient thermal resistance in °C/W
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max= Σ(VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
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Package information
STM32L010F4/K4
Table 62. Thermal characteristics
symbol
ϴJA
Thermal resistance junction-ambient
Value
TSSOP20 - 169 mils
74
LQFP32 - 7 x 7 mm / 0.8 mm pitch
60
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Ordering information
Ordering information
Example:
STM32 L 010
F
4
P
6
xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
010 = Value line
Pin count
F = 20 pins
K = 32 pins
Flash memory size
4 = 16 Kbytes
Package
P = TSSOP
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (such as speed, package) or for further information on any
aspect of this device, contact the nearest ST sales office.
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Revision history
9
STM32L010F4/K4
Revision history
Table 63. Document revision history
Date
Revision
8-Dec-2017
1
Initial release.
3-Sep-2018
2
Updated Introduction.
TSSOP14 removed in the whole document.
3
Updated:
– Table 3: Functionalities depending on the working
mode (from Run/active down to Standby)
– Table 29: Peripheral current consumption in run or
Sleep mode
– Device marking sections
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Changes
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