STM32L151VD-X
STM32L152VD-X
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3 with 384KB
Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 290 nA Standby mode (3 wakeup pins)
– 1.11 µA Standby mode + RTC
– 560 nA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 11 µA Low-power run mode down to 4.6 µA
in Low-power sleep mode
– 195 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
• Core: ARM® Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
LQFP100 (14 × 14 mm)
WLCSP104
(0.4 mm pitch)
• Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
• Memories
– 384 Kbytes of Flash memory with ECC
(with 2 banks of 192 Kbytes enabling RWW
capability)
– 80 Kbytes of RAM
– 16 Kbytes of true EEPROM with ECC
– 128-byte backup register
• LCD driver (except STM32L151VD-X) up to
8x40 segments, contrast adjustment, blinking
mode, step-up converter
• Up to 23 capacitive sensing channels
• CRC calculation unit, 96-bit unique ID
• Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 16 MHz oscillator factory trimmed
RC(+/-1%) with PLL option
– Internal low-power 37 kHz oscillator
– Internal multispeed low-power 65 kHz to
4.2 MHz oscillator
– PLL for CPU clock and USB (48 MHz)
• Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power comparators
(window mode and wakeup capability)
• DMA controller 12x channels
• 11x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USARTs
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
– 2x I2Cs (SMBus/PMBus)
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
• Development support: serial wire debug, JTAG
and trace
• Pre-programmed bootloader
– USB and USART supported
August 2017
This is information on a product in full production.
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Contents
STM32L151VD-X STM32L152VD-X
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2/119
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3
Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22
3.6
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9
LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26
3.14
System configuration controller and routing interface . . . . . . . . . . . . . . . 26
3.15
Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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3.17
Contents
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.2
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.3
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 28
3.17.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.4
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.5
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.1.7
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.8
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 55
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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STM32L151VD-X STM32L152VD-X
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.17
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.19
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.21
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.22
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.1
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2
WLCSP104, 0.4 mm pitch wafer level chip scale package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.3.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Ultra-low-power STM32L151VD-X and STM32L152VD-X device features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15
Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L151VD-X and STM32L152VD-X pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current consumption in Run mode, code with data processing running from Flash. . . . . . 59
Current consumption in Run mode, code with data processing running from RAM . . . . . . 60
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 66
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 79
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
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STM32L151VD-X STM32L152VD-X
SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 89
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 108
WLCSP104, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . 112
WLCSP104, 0.4 mm pitch recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . 113
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
STM32L151VD-X and STM32L152VD-X Ordering information scheme . . . . . . . . . . . . . 116
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DocID027267 Rev 4
STM32L151VD-X STM32L152VD-X
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Ultra-low-power STM32L151VD-X and STM32L152VD-X block diagram . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32L152VD-X LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32L151VD-X WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 108
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 110
WLCSP104, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . 111
WLCSP104, 0.4 mm pitch wafer level chip scale package recommended footprint. . . . . 112
WLCSP104, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . 113
Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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7
Introduction
1
STM32L151VD-X STM32L152VD-X
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151VD-X and STM32L152VD-X ultra-low-power ARM® Cortex®-M3 based
microcontroller product line. The STM32L151VD-X and STM32L152VD-X devices are
microcontrollers with a Flash memory density of 384 Kbytes.
The ultra-low-power STM32L151VD-X and STM32L152VD-X family includes devices in 2
different package types: from 100 pins to 104 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151VD-X and STM32L152VD-X
microcontroller family suitable for a wide range of applications:
•
Medical and handheld equipment
•
Application control and user interface
•
PC peripherals, gaming, GPS and sport equipment
•
Alarm systems, wired and wireless sensors, video intercom
•
Utility metering
This STM32L151VD-X and STM32L152VD-X datasheet should be read in conjunction with
the STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device family.
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STM32L151VD-X STM32L152VD-X
2
Description
Description
The ultra-low-power STM32L151VD-X and STM32L152VD-X devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance ARM®
Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes
and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
The STM32L151VD-X and STM32L152VD-X devices offer two operational amplifiers, one
12-bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer,
six general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151VD-X and STM32L152VD-X devices contain standard and
advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs,
two UARTs and an USB. The STM32L151VD-X and STM32L152VD-X devices offer up to
23 capacitive sensing channels to simply add a touch sensing functionality to any
application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151VD-X) has a built-in LCD voltage
generator that allows to drive up to 8 multiplexed LCDs with the contrast independent of the
supply voltage.
The ultra-low-power STM32L151VD-X and STM32L152VD-X devices operate from a 1.8 to
3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V
power supply without BOR option. They are available in the -40 to +85 °C and -40 to +105
°C temperature ranges. A comprehensive set of power-saving modes allows the design of
low-power applications.
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49
Description
2.1
STM32L151VD-X STM32L152VD-X
Device overview
Table 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X device features
and peripheral counts
Peripheral
STM32L151VD-X STM32L152VD-X
Flash (Kbytes)
384
Data EEPROM (Kbytes)
16
RAM (Kbytes)
80
Timers
32 bit
1
Generalpurpose
6
Basic
2
SPI
8(3)(1)
I2S
2
Communication 2
I C
interfaces
2
USART
5
USB
1
GPIOs
83
Operational amplifiers
2
12-bit synchronized ADC
Number of channels
1
25
12-bit DAC
Number of channels
2
2
LCD (2)
COM x SEG
1
4x44 or 8x40
Comparators
2
Capacitive sensing channels
23
Max. CPU frequency
Operating voltage
Operating temperatures
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
LQFP100,
WLCSP104
Packages
1. 5 SPIs are USART configured in synchronous mode emulating SPI master.
2. STM32L152VD-X device only.
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STM32L151VD-X STM32L152VD-X
Description
Note:
There is no FSMC and SDIO peripheral.
2.2
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow to build very cost-optimized applications by reducing BOM.
Note:
STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.
2.2.1
Performance
All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
2.2.3
•
Analog peripherals: ADC, DAC and comparators
•
Digital peripherals: RTC and some communication interfaces
Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
2.2.4
•
Same power supply range from 1.65 V to 3.6 V
•
Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•
Fast startup strategy from low-power modes
•
Flexible system clock
•
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
Features
ST ultra-low-power continuum also lies in feature compatibility:
•
More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•
Memory density ranging from 2 to 512 Kbytes
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49
Functional overview
3
STM32L151VD-X STM32L152VD-X
Functional overview
Figure 1. Ultra-low-power STM32L151VD-X and STM32L152VD-X block diagram
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DocID027267 Rev 4
06Y9
STM32L151VD-X STM32L152VD-X
3.1
Functional overview
Low-power modes
The ultra-low-power STM32L151VD-X and STM32L152VD-X devices support dynamic
voltage scaling to optimize its power consumption in run mode. The voltage from the internal
low-drop regulator that supplies the logic can be adjusted according to the system’s
maximum operating frequency and the external voltage supply.
There are three power consumption ranges:
•
Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
•
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•
Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI
range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or
Flash memory, and internal regulator in low-power mode to minimize the regulator's
operating current. In low-power run mode, the clock frequency and the number of
enabled peripherals are both limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
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49
Functional overview
•
STM32L151VD-X STM32L152VD-X
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 2. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply
range(1)
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage scaling
range
VDD= VDDA = 1.65 to 1.71 V
Not functional
Not functional
Range 2 or Range 3
Not functional
Not functional
Range 1, Range 2 or
Range 3
Conversion time up
to 500 Ksps
Not functional
Range 1, Range 2 or
Range 3
VDD=VDDA= 1.71 to 1.8 V(2)
VDD=VDDA= 1.8 to 2.0 V
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STM32L151VD-X STM32L152VD-X
Functional overview
Table 2. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply
range(1)
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage scaling
range
VDD=VDDA = 2.0 to 2.4 V
Conversion time up
to 500 Ksps
Functional(3)
Range 1, Range 2 or
Range 3
VDD=VDDA = 2.4 to 3.6 V
Conversion time up
to 1 Msps
Functional(3)
Range 1, Range 2 or
Range 3
1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 43: I/O AC
characteristics for more information about I/O speed.
2. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop
due to current consumption peak when frequency increases. It must also respect 5 µs delay between two
changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz,
wait 5 µs, then switch from 16 MHz to 32 MHz.
3. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 3. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
Range 3
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Functional overview
STM32L151VD-X STM32L152VD-X
Table 4. Functionalities depending on the working mode (from Run/active down to
standby)
Standby
Run/Active
Sleep
CPU
Y
--
Y
--
--
--
--
--
Flash
Y
Y
Y
Y
--
--
--
--
RAM
Y
Y
Y
Y
Y
--
--
--
Backup Registers
Y
Y
Y
Y
Y
--
Y
--
EEPROM
Y
Y
Y
Y
Y
--
--
--
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
--
DMA
Y
Y
Y
Y
--
--
--
--
Programmable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
--
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
--
Power Down Rest
(PDR)
Y
Y
Y
Y
Y
--
Y
--
High Speed
Internal (HSI)
Y
Y
--
--
--
--
--
--
High Speed
External (HSE)
Y
Y
--
--
--
--
--
--
Low Speed Internal
(LSI)
Y
Y
Y
Y
Y
--
Y
--
Low Speed
External (LSE)
Y
Y
Y
Y
Y
--
Y
--
Multi-Speed
Internal (MSI)
Y
Y
Y
Y
--
--
--
--
Inter-Connect
Controller
Y
Y
Y
Y
--
--
--
--
RTC
Y
Y
Y
Y
Y
Y
Y
--
RTC Tamper
Y
Y
Y
Y
Y
Y
Y
Y
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
Y
Y
LCD
Y
Y
Y
Y
Y
--
--
--
USB
Y
Y
--
--
--
Y
--
--
--
--
Ips
Lowpower
Sleep
Stop
Lowpower
Run
Wakeup
capability
Wakeup
capability
USART
Y
Y
Y
Y
Y
(1)
SPI
Y
Y
Y
Y
--
--
--
--
I2C
Y
Y
--
--
--
(1)
--
--
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Functional overview
Table 4. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Standby
Run/Active
Sleep
ADC
Y
Y
--
--
--
--
--
--
DAC
Y
Y
Y
Y
Y
--
--
--
Tempsensor
Y
Y
Y
Y
Y
--
--
--
OP amp
Y
Y
Y
Y
Y
--
--
--
Comparators
Y
Y
Y
Y
Y
Y
--
--
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
WWDG
Y
Y
Y
Y
--
--
--
--
Touch sensing
Y
Y
--
--
--
--
--
--
Systic Timer
Y
Y
Y
Y
--
--
--
GPIOs
Y
Y
Y
Y
Y
--
3 pins
0 µs
0.4 µs
3 µs
46 µs
Ips
Wakeup time to
Run mode
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 195
µA/MHz (from
Flash)
Down to 38
µA/MHz (from
Flash)
Down to
11 µA
Lowpower
Sleep
Stop
Lowpower
Run
Down to
4.6 µA
Wakeup
capability
Y
Wakeup
capability
< 8 µs
58 µs
0.53 µA
(no RTC)
VDD=1.8V
0.285 µA
(no RTC)
VDD=1.8V
1.2 µA
(with RTC)
VDD=1.8V
0.97 µA
(with RTC)
VDD=1.8V
0.56 µA
(no RTC)
VDD=3.0V
0.29 µA
(no RTC)
VDD=3.0V
1.4 µA
(with RTC)
VDD=3.0V
1.11 µA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
ARM® Cortex®-M3 core with MPU
The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
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Functional overview
STM32L151VD-X STM32L152VD-X
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L151VD-X and STM32L152VD-X devices are
compatible with all ARM tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151VD-X and STM32L152VD-X devices embed a nested
vectored interrupt controller able to handle up to 56 maskable interrupt channels (not
including the 16 interrupt lines of ARM® Cortex®-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
3.3.2
•
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
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Functional overview
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
3.3.4
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.
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Functional overview
3.4
STM32L151VD-X STM32L152VD-X
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
•
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
•
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
•
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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Functional overview
Figure 2. Clock tree
3TANDBYSUPPLIEDVOLTAGEDOMAIN
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IF!0"PRESC X
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APBPERIPHENANDNOTDEEPSLEEP
-36
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Functional overview
3.5
STM32L151VD-X STM32L152VD-X
Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
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3.7
Functional overview
Memories
The STM32L151VD-X and STM32L152VD-X devices have the following features:
•
80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
384 Kbytes of embedded Flash program memory
–
16 Kbytes of data EEPROM
–
Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
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Functional overview
3.9
STM32L151VD-X STM32L152VD-X
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
3.10
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
•
Supports static, 1/2, 1/3 and 1/4 bias
•
Phase inversion to reduce power consumption and EMI
•
Up to 8 pixels can be programmed to blink
•
Unneeded segments and common pins can be used as general I/O pins
•
LCD RAM can be updated at any time owing to a double-buffer
•
The LCD controller can operate in Stop mode
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151VD-X and
STM32L152VD-X devices with up to 40 external channels, performing conversions in
single-shot or scan mode. In scan mode, automatic conversion is performed on a selected
group of analog inputs with up to 28 external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
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Functional overview
stored by ST in the system memory area, accessible in read-only mode. See Table 59:
Temperature sensor calibration values.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 14: Embedded internal reference voltage calibration values.
3.11
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
•
Two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channels, independent or simultaneous conversions
•
DMA capability for each channel (including the underrun interrupt)
•
External triggers for conversion
•
Input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L151VD-X and STM32L152VD-X devices.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.12
Operational amplifier
The STM32L151VD-X and STM32L152VD-X devices embed two operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.
The operational amplifiers feature:
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
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Functional overview
3.13
STM32L151VD-X STM32L152VD-X
Ultra-low-power comparators and reference voltage
The STM32L151VD-X and STM32L152VD-X devices embed two comparators sharing the
same current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).
•
One comparator with fixed threshold
•
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
DAC output
–
External I/O
–
Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4)
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.14
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
VREFINT.
3.15
Touch sensing
The STM32L151VD-X and STM32L152VD-X devices provide a simple solution for adding
capacitive sensing functionality to any application. These devices offer up to 23 capacitive
sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see Section 3.14: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
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3.16
Functional overview
Timers and watchdogs
The ultra-low-power STM32L151VD-X and STM32L152VD-X devices include seven
general-purpose timers, two basic timers, and two watchdog timers.
Table 5 compares the features of the general-purpose and basic timers.
Table 5. Timer feature comparison
DMA
Capture/compare Complementary
request
channels
outputs
generation
Timer
Counter
resolution
Counter type
Prescaler factor
TIM2,
TIM3,
TIM4
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM5
32-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM9
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM10,
TIM11
16-bit
Up
Any integer between
1 and 65536
No
1
No
TIM6,
TIM7
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L151VD-X
and STM32L152VD-X devices (see Table 5 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
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Functional overview
STM32L151VD-X STM32L152VD-X
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.16.2
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.16.3
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.16.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.16.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17
Communication interfaces
3.17.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three
USARTs provide hardware management of the CTS and RTS signals and are ISO 7816
compliant.
All USART/UART interfaces can be served by the DMA controller.
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3.17.3
Functional overview
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
3.17.4
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.17.5
Universal serial bus (USB)
The STM32L151VD-X and STM32L152VD-X devices embed a USB device peripheral
compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed
(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the
clock source must use a HSE crystal oscillator).
3.18
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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Functional overview
STM32L151VD-X STM32L152VD-X
3.19
Development support
3.19.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
3.19.2
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151VD-X and STM32L152VD-X device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.
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Pin descriptions
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Pin descriptions
AIC
1. This figure shows the package top view.
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Pin descriptions
STM32L151VD-X STM32L152VD-X
Figure 4. STM32L151VD-X WLCSP104 ballout
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t VDDA
-
Electrostatic discharge voltage
(human body model)
see Section 6.3.11
VESD(HBM)
Unit
V
mV
V
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. VIN maximum must always be respected. Refer to Table 10 for maximum allowed injected current values.
3. Include VREF- pin.
Table 10. Current characteristics
Symbol
IVDD(Σ)
IVSS(Σ)
(2)
Ratings
Max.
Total current into sum of all VDD_x power lines (source)(1)
100
(sink)(1)
100
Total current out of sum of all VSS_x ground lines
IVDD(PIN)
Maximum current into each VDD_x power pin (source)(1)
70
IVSS(PIN)
(sink)(1)
-70
IIO
ΣIIO(PIN)
IINJ(PIN) (3)
ΣIINJ(PIN)
Maximum current out of each VSS_x ground pin
Output current sunk by any I/O and control pin
25
Output current sourced by any I/O and control pin
- 25
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins
Injected current on five-volt tolerant
Injected current on any other pin
mA
60
(2)
I/O(4),
Unit
RST and B pins
(5)
Total injected current (sum of all I/O and control pins)(6)
-60
-5/+0
±5
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.
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STM32L151VD-X STM32L152VD-X
4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 9: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 11. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Value
Unit
–65 to +150
°C
150
°C
Table 12. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled, at
power on
1.8
3.6
BOR detector disabled, after
power on
1.65
3.6
1.65
3.6
1.8
3.6
FT pins; 2.0 V ≤VDD
-0.3
5.5(3)
FT pins; VDD < 2.0 V
-0.3
5.25(3)
0
5.5
-0.3
VDD+0.3
LQFP100 package
-
465
WLCSP104 package
-
435
Ambient temperature for 6 suffix version Maximum power dissipation(5)
–40
85
Ambient temperature for 7 suffix version Maximum power dissipation
–40
105
6 suffix version
–40
105
7 suffix version
–40
110
VDD
(1)
VDDA
VIN
Standard operating voltage
Analog operating voltage
(ADC and DAC not used)
Analog operating voltage
(ADC or DAC used)
I/O input voltage
Must be the same voltage as
VDD(2)
BOOT0 pin
Any other pin
PD
TA
TJ
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
Junction temperature range
1. When the ADC is used, refer to Table 54: ADC characteristics.
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V
V
V
mW
°C
°C
STM32L151VD-X STM32L152VD-X
Electrical characteristics
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up .
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 67: Thermal characteristics
on page 114).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 67: Thermal characteristics on page 114).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
conditions summarized in Table 12.
Table 13. Embedded reset and power control block characteristics
Symbol
Parameter
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1)
Reset temporization
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
Conditions
Min
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
VDD rising, BOR disabled(2)
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Table 13. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst
Hysteresis voltage
Min
Typ
Max
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD
thresholds excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details.
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6.3.3
Electrical characteristics
Embedded internal reference voltage
The parameters given in Table 15 are based on characterization results, unless otherwise
specified.
Table 14. Embedded internal reference voltage calibration values
Calibration value name
Description
Raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
VREFINT_CAL
Memory address
0x1FF8 00F8 - 0x1FF8 00F9
Table 15. Embedded internal reference voltage
Symbol
VREFINT out
Parameter
(1)
Conditions
Internal reference voltage
Min
Typ
– 40 °C < TJ < +110 °C 1.202 1.224
Max
Unit
1.242
V
Internal reference current
consumption
-
-
1.4
2.3
µA
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Including uncertainties
Accuracy of factory-measured VREF
due to ADC and
(2)
value
VDDA/VREF+ values
-
-
±5
mV
TCoeff(3)
Temperature coefficient
–40 °C < TJ < +110 °C
-
25
100
ppm/°C
ACoeff(3)
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
VDDCoeff(3)
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
TS_vrefint(3)
ADC sampling time when reading
the internal reference voltage
-
4
-
-
µs
TADC_BUF(3)
Startup time of reference voltage
buffer for ADC
-
-
-
10
µs
IBUF_ADC(3)
Consumption of reference voltage
buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(3)
VREF_OUT output current (4)
-
-
-
1
µA
CVREF_OUT(3)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference voltage
buffer for VREF_OUT and COMP
-
-
730
1200
nA
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
IREFINT
ILPBUF(3)
%
VREFINT
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results.
4. To guarantee less than 1% VREF_OUT deviation.
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6.3.4
STM32L151VD-X STM32L152VD-X
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature TA = 25 °C and VDD supply voltage conditions summarized in
Table 12: General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
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•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAHB.
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 25: High-speed external user clock characteristics.
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins.
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise.
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STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 16. Current consumption in Run mode, code with data processing running from
Flash
Symbol Parameter
fHCLK
Typ
Max(1)
1 MHz
225
500
2 MHz
420
750
4 MHz
780
1200
4 MHz
0.98
1.6
8 MHz
1.85
2.9
16 MHz
3.6
5.2
8 MHz
2.2
3.5
16 MHz
4.4
6.5
32 MHz
8.6
12
Range 2, VCORE=1.5
V VOS[1:0] = 10
16 MHz
3.6
5.2
Range 1, VCORE=1.8
V VOS[1:0] = 01
32 MHz
8.7
12.3
65 kHz
42
145
524 kHz
135
250
4.2 MHz
820
1200
Conditions
Range 3, VCORE=1.2
V VOS[1:0] = 11
IDD
(Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK up to
16 MHz included,
Range 2, VCORE=1.5
fHSE = fHCLK/2
V VOS[1:0] = 10
above 16 MHz (PLL
(2)
ON)
Range 1, VCORE=1.8
V VOS[1:0] = 01
HSI clock source
(16 MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
Range 3, VCORE=1.2
V VOS[1:0] = 11
MSI clock, 4.2 MHz
Unit
µA
mA
µA
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Table 17. Current consumption in Run mode, code with data processing running from
RAM
Symbol
Parameter
Conditions
Typ
1 MHz
200
470
2 MHz
360
780
4 MHz
685
1200
4 MHz
0.80
1.5
8 MHz
1.6
3
16 MHz
3.1
5
8 MHz
1.9
3.5
16 MHz
3.7
5.55
32 MHz
7.55
10.9
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
3.15
4.8
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
7.75
11.7
65 kHz
40
130
524 kHz
115
215
4.2 MHz
715
1100
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
IDD
(Run
from
RAM)
Supply current
in Run mode,
code executed
from RAM,
Flash switched
off
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
HSI clock source
(16 MHz)
MSI clock, 65 kHz
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Max(1) Unit
fHCLK
DocID027267 Rev 4
µA
mA
µA
STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 18. Current consumption in Sleep mode
Symbol
Parameter
Conditions
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
Range 2,
fHSE = fHCLK/2
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
ON)(2)
Supply current
in Sleep
mode, Flash
OFF
HSI clock source
(16 MHz)
Typ
Max(1)
1 MHz
51
220
2 MHz
81
300
4 MHz
140
380
4 MHz
175
500
8 MHz
330
700
16 MHz
625
1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz
395
800
16 MHz
760
1250
32 MHz
1700
2700
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
670
1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1750
2700
65 kHz
19
92
524 kHz
33
110
4.2 MHz
150
273
1 MHz
63
250
2 MHz
93
300
4 MHz
155
380
4 MHz
190
500
MSI clock, 65 kHz
IDD (Sleep)
fHCLK
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
Range 2,
fHSE = fHCLK/2
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
Supply current ON)(2)
in Sleep
Range 1,
mode, Flash
VCORE=1.8 V
ON
VOS[1:0] = 01
8 MHz
340
700
16 MHz
640
1120
8 MHz
410
800
16 MHz
770
1300
32 MHz
1750
2700
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
690
1160
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1750
2800
65 kHz
31
105
524 kHz
45
125
4.2 MHz
160
290
HSI clock source
(16 MHz)
Supply current MSI clock, 65 kHz
Range 3,
in Sleep
MSI clock, 524 kHz VCORE=1.2V
mode, Flash
VOS[1:0] = 11
ON
MSI clock, 4.2 MHz
Unit
µA
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
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107
Electrical characteristics
STM32L151VD-X STM32L152VD-X
Table 19. Current consumption in Low-power run mode
Symbol
Parameter
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
IDD (LP
Run)
Typ
Max(1)
11
16
TA = 85 °C
36.2
40
TA = 105 °C
65.4
102
TA =-40 °C to 25 °C
16.5
23
TA = 85 °C
41.9
48
TA = 105 °C
72.1
108
30
45
TA = 55 °C
36.1
48
TA = 85 °C
55.7
66
TA = 105 °C
86.6
125
26
40.5
TA = 85 °C
53.2
67
TA = 105 °C
92.1
120
33
49
TA = 85 °C
60.2
75
TA = 105 °C
95.6
130
TA = -40 °C to 25 °C
48.5
71
TA = 55 °C
54.7
75
TA = 85 °C
76.1
95
TA = 105 °C
112
140
-
200
Conditions
Supply
current in
Low-power
run mode
MSI clock, 65 kHz
fHCLK = 32 kHz
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C
MSI clock, 131 kHz
fHCLK = 131 kHz
MSI clock, 65 kHz
fHCLK = 32 kHz
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
Max allowed
VDD from
IDD max current in
1.65 V to
(LP Run) Low-power
3.6 V
run mode
TA = -40 °C to 25 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C
TA = -40 °C to 25 °C
-
1. Guaranteed by characterization results, unless otherwise specified.
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Unit
µA
STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 20. Current consumption in Low-power sleep mode
Symbol
Parameter
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
All peripherals
OFF, VDD from
1.65 V to 3.6 V
IDD
(LP Sleep)
Typ
Max(1)
TA = -40 °C to 25 °C
5.5
-
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
26.8
29
TA = 105 °C
37
47
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
27.2
29
TA = 105 °C
37.3
47
TA = -40 °C to 25 °C
21.5
25
23.7
26
29.8
32
TA = 105 °C
39.7
50
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
26.8
29
TA = 105 °C
38.3
47
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
27.2
29
TA = 105 °C
38.5
47
TA = -40 °C to 25 °C
21.5
25
23.7
26
29.8
32
41.2
50
-
200
Conditions
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
MSI clock, 131 kHz T = 55 °C
A
fHCLK = 131 kHz,
TA = 85 °C
Flash ON
Supply
current in
Low-power
sleep mode
MSI clock, 65 kHz
fHCLK = 32 kHz
TIM9 and
USART1
enabled, Flash
ON, VDD from
1.65 V to 3.6 V
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz TA = 55 °C
fHCLK = 131 kHz
TA = 85 °C
TA = 105 °C
IDD max
(LP Sleep)
Max
allowed
VDD from 1.65 V
current in
to 3.6 V
Low-power
sleep mode
-
-
Unit
µA
1. Guaranteed by characterization results, unless otherwise specified.
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Electrical characteristics
STM32L151VD-X STM32L152VD-X
Table 21. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
LCD
OFF
RTC clocked by LSI
or LSE external clock
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
Typ
TA = -40°C to 25°C
VDD = 1.8 V
1.18
-
TA = -40°C to 25°C
1.4
4
TA = 55°C
3.02
6
TA= 85°C
7.44
11
TA = 105°C
15.5
27
1.5
6
4.65
7
9.07
13
15.6
31
3.9
10
5.19
11
9.8
17
TA = 105°C
18.4
48
TA = -40°C to 25°C
1.65
-
TA = 55°C
3.32
-
TA= 85°C
7.83
-
16
-
1.75
-
4.9
-
9.41
-
15.8
-
4.1
-
5.53
-
10
-
TA = 105°C
18.5
-
TA = -40°C to 25°C
VDD = 1.8V
1.33
-
TA = -40°C to 25°C
VDD = 3.0V
1.62
-
TA = -40°C to 25°C
VDD = 3.6V
1.87
-
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
TA = -40°C to 25°C
LCD
TA = 55°C
ON (1/8
duty)(3) TA= 85°C
IDD (Stop
with RTC)
Supply current in
Stop mode with RTC
enabled
LCD
OFF
TA = 105°C
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
RTC clocked by LSE
external quartz
(32.768kHz),
regulator in LP mode,
TA = -40°C to 25°C
HSI and HSE OFF
LCD
TA = 55°C
(no independent
ON
(1/8
watchdog(4)
duty)(3) TA= 85°C
LCD
OFF
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µA
STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 21. Typical and maximum current consumptions in Stop mode (continued)
Symbol
Parameter
Conditions
Regulator in LP mode, HSI and
HSE OFF, independent
watchdog and LSI enabled
IDD (Stop)
Supply current in
Stop mode (RTC
disabled)
Typ
TA = -40°C to 25°C
1.8
2.2
TA = -40°C to 25°C
0.560
1.5
2.18
4
6.6
12
14.9
26
2
-
1.45
-
1.45
-
Regulator in LP mode, LSI, HSI T = 55°C
A
and HSE OFF (no independent
TA= 85°C
watchdog)
TA = 105°C
IDD
(WU from
Stop)
MSI = 4.2 MHz
Supply current during
wakeup from Stop
MSI = 1.05 MHz
mode
MSI = 65 kHz(5)
Max(1) Unit
TA = -40°C to 25°C
µA
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
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107
Electrical characteristics
STM32L151VD-X STM32L152VD-X
Table 22. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
0.865
-
1.11
1.9
1.72
2.2
TA= 85 °C
2.12
4
TA = 105 °C
2.54
8.3(2)
TA = -40 °C to 25 °C
VDD = 1.8 V
0.97
-
TA = -40 °C to 25 °C
1.28
-
TA = 55 °C
2.01
-
TA= 85 °C
2.5
-
TA = 105 °C
2.98
-
1
1.7
0.29
1
0.96
1.3
1.38
3
1.98
7(2)
1
-
Conditions
TA = -40 °C to 25 °C
VDD = 1.8 V
T = -40 °C to 25 °C
RTC clocked by LSI (no A
independent watchdog) TA = 55 °C
IDD
(Standby
with RTC)
Supply current in
Standby mode with RTC
enabled
RTC clocked by LSE
external quartz (no
independent
watchdog)(3)
Independent watchdog
TA = -40 °C to 25 °C
and LSI enabled
IDD
(Standby)
Supply current in
Standby mode (RTC
disabled)
TA = -40 °C to 25 °C
Independent watchdog TA = 55 °C
and LSI OFF
TA = 85 °C
TA = 105 °C
IDD
(WU from
Standby)
Supply current during
wakeup time from
Standby mode
-
TA = -40 °C to 25 °C
Unit
µA
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
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•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
DocID027267 Rev 4
STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 23. Peripheral current consumption(1)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
APB1
Range 1,
Range 2,
Range 3,
VCORE=
VCORE=
VCORE=
Low-power
1.8 V
1.5 V
1.2 V
sleep and run
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
TIM2
12.0
10.0
8.0
10.0
TIM3
10.5
8.8
7.0
8.8
TIM4
10.4
8.8
7.0
8.8
TIM5
13.8
11.5
9.1
11.5
TIM6
3.9
3.0
2.5
3.0
TIM7
3.8
3.3
2.6
3.3
LCD
4.2
3.6
2.8
3.6
WWDG
2.9
2.5
2.1
2.5
SPI2
5.4
4.4
3.5
4.4
SPI3
5.5
4.6
3.7
4.6
USART2
7.6
6.2
4.9
6.2
USART3
7.6
6.2
5.0
6.2
USART4
7.3
6.1
4.8
6.1
USART5
7.6
6.3
5.0
6.3
I2C1
7.3
6.1
4.8
6.1
I2C2
7.2
5.9
4.7
5.9
USB
13.0
11.2
8.9
11.2
PWR
2.6
2.3
1.9
2.3
DAC
5.9
5.0
4.0
5.0
COMP
3.9
3.3
2.6
3.3
DocID027267 Rev 4
Unit
µA/MHz
(fHCLK)
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107
Electrical characteristics
STM32L151VD-X STM32L152VD-X
Table 23. Peripheral current consumption(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
APB2
AHB
Range 1,
Range 2,
Range 3,
VCORE=
VCORE=
VCORE=
Low-power
1.8 V
1.5 V
1.2 V
sleep and run
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
SYSCFG & RI
2.9
2.4
2.0
2.4
TIM9
8.2
6.9
5.5
6.9
TIM10
6.2
5.1
4.1
5.1
TIM11
6.2
5.1
4.1
5.1
ADC
9.5
7.9
6.2
7.9
SPI1
4.8
3.9
3.2
3.9
USART1
8.2
6.9
5.4
6.9
GPIOA
6.3
5.3
4.1
5.3
GPIOB
6.3
5.3
4.1
5.3
GPIOC
6.3
5.2
4.1
5.2
GPIOD
8.1
6.8
5.4
6.8
GPIOE
6.7
5.7
4.5
5.7
GPIOF
5.9
4.9
3.9
4.9
GPIOG
7.2
6.1
4.9
6.1
GPIOH
1.7
1.4
1.1
1.4
CRC
0.8
0.7
0.5
0.7
FLASH
21.6
18.1
16.0
- (3)
DMA1
16.8
14.5
11.5
14.5
DMA2
15.7
13.6
10.8
13.6
222
184
160
165.9
(2)
All enabled
IDD (RTC)
0.4
IDD (LCD)
3.1
IDD (ADC)(4)
1450
IDD (DAC)(5)
340
IDD (COMP1)
0.16
IDD (COMP2)
Slow mode
2
Fast mode
5
IDD (PVD / BOR)(6)
2.6
IDD (IWDG)
0.25
Unit
µA/MHz
(fHCLK)
µA
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the
following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Lowpower run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in
both cases. No I/O pins toggling.
2. HSI oscillator is OFF for this measure.
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STM32L151VD-X STM32L152VD-X
Electrical characteristics
3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI
consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under the conditions summarized in Table 12.
Table 24. Low-power mode wakeup timings
Symbol
tWUSLEEP
tWUSLEEP_LP
Parameter
Wakeup from Sleep mode
tWUSTDBY
Typ
Max(1) Unit
fHCLK = 32 MHz
0.4
-
fHCLK = 262 kHz
Flash enabled
46
-
fHCLK = 262 kHz
Flash switched OFF
46
-
fHCLK = fMSI = 4.2 MHz
8.2
-
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
7.7
8.9
fHCLK = fMSI = 4.2 MHz
Voltage range 3
8.2
13.1
fHCLK = fMSI = 2.1 MHz
10.2
13.4
fHCLK = fMSI = 1.05 MHz
16
20
fHCLK = fMSI = 524 kHz
31
37
fHCLK = fMSI = 262 kHz
57
66
fHCLK = fMSI = 131 kHz
112
123
fHCLK = MSI = 65 kHz
221
236
Wakeup from Standby mode
ULP bit = 1 and FWU bit = 1
fHCLK = MSI = 2.1 MHz
58
104
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
2.6
3.25
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
Wakeup from Stop mode,
regulator in Run mode
ULP bit = 1 and FWU bit = 1
tWUSTOP
Conditions
Wakeup from Stop mode,
regulator in low-power mode
ULP bit = 1 and FWU bit = 1
µs
ms
1. Guaranteed by characterization, unless otherwise specified
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Electrical characteristics
6.3.6
STM32L151VD-X STM32L152VD-X
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 11.
Table 25. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min
Typ
Max
Unit
CSS is on or
PLL is used
1
8
32
MHz
CSS is off, PLL
not used
0
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
12
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance
-
2.6
-
Cin(HSE)
-
V
ns
pF
1. Guaranteed by design.
Figure 11. High-speed external clock source AC timing diagram
WZ +6(+
9+6(+
9+6(/
WU +6(
WI +6(
WZ +6(/
W
7+6(
06 9
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Electrical characteristics
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under the conditions summarized in Table 12.
Table 26. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
CIN(LSE)
Min
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
OSC32_IN input capacitance
-
-
-
10
-
0.6
-
pF
1. Guaranteed by design.
Figure 12. Low-speed external clock source AC timing diagram
WZ /6(+
9/6(+
9/6(/
WU /6(
WI /6(
W
WZ /6(/
7/6(
06 9
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 27. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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107
Electrical characteristics
STM32L151VD-X STM32L152VD-X
Table 27. HSE oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Min Typ
Max
Unit
24
MHz
Oscillator frequency
-
1
RF
Feedback resistor
-
-
200
-
kΩ
C
Recommended load
capacitance versus
equivalent serial
resistance of the crystal
(RS)(3)
RS = 30 Ω
-
20
-
pF
VDD= 3.3 V,
VIN = VSS with 30 pF
load
-
-
3
mA
C = 20 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.7 (stabilized)
C = 10 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.46 (stabilized)
Startup
3.5
-
-
mA /V
VDD is stabilized
-
1
-
ms
IHSE
IDD(HSE)
gm
tSU(HSE)(4)
HSE driving current
HSE oscillator power
consumption
Oscillator
transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 13. HSE oscillator circuit diagram
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 28. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 28. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE
Low speed external oscillator
frequency
-
-
32.768
-
kHz
RF
Feedback resistor
-
-
1.2
-
MΩ
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 kΩ
-
8
-
pF
ILSE
LSE driving current
VDD = 3.3 V, VIN = VSS
-
-
1.1
µA
VDD = 1.8 V
-
450
-
VDD = 3.0 V
-
600
-
VDD = 3.6V
-
750
-
-
3
-
-
µA/V
VDD is stabilized
-
1
-
s
IDD (LSE)
Oscillator transconductance
gm
tSU(LSE)
LSE oscillator current
consumption
(4)
Startup time
nA
1. Guaranteed by characterization results.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
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STM32L151VD-X STM32L152VD-X
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 14).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and
Cstray = 2 pF, then CL1 = CL2 = 8 pF.
Figure 14. Typical application with a 32.768 kHz crystal
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6.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 29 are derived from tests performed under the conditions
summarized in Table 12.
High-speed internal (HSI) RC oscillator
Table 29. HSI oscillator characteristics
Symbol
fHSI
TRIM
(1)(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI user-trimmed
resolution
Trimming code is not a multiple of 16
-
± 0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
ACCHSI(2) factory-calibrated
HSI oscillator
-
± 1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C
-4
-
3
%
tSU(HSI)(2)
HSI oscillator
startup time
-
-
3.7
6
µs
IDD(HSI)(2)
HSI oscillator
power consumption
-
-
100
140
µA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
Low-speed internal (LSI) RC oscillator
Table 30. LSI oscillator characteristics
Symbol
fLSI(1)
DLSI(2)
tsu(LSI)(3)
IDD(LSI)
(3)
Parameter
Min
Typ
Max
Unit
LSI frequency
26
38
56
kHz
LSI oscillator frequency drift
0°C ≤TA ≤ 105°C
-10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
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STM32L151VD-X STM32L152VD-X
Multi-speed internal (MSI) RC oscillator
Table 31. MSI oscillator characteristics
Symbol
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0 °C ≤TA ≤105 °C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.65 V ≤VDD ≤3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
fMSI
ACCMSI
IDD(MSI)(2)
tSU(MSI)
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Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI oscillator power consumption
MSI oscillator startup time
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µs
STM32L151VD-X STM32L152VD-X
Electrical characteristics
Table 31. MSI oscillator characteristics (continued)
Symbol
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
Typ
Max Unit
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
µs
MHz
6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
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6.3.8
STM32L151VD-X STM32L152VD-X
PLL characteristics
The parameters given in Table 32 are derived from tests performed under the conditions
summarized in Table 12.
Table 32. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
PLL lock time
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
µA
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 33. RAM and hardware registers
Symbol
VRM
Parameter
Conditions
Data retention mode(1)
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Flash memory and data EEPROM
Table 34. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
600
-
µA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming/ erasing
time for byte / word /
double word / half-page
IDD
ms
1. Guaranteed by design.
Table 35. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC(2)
Parameter
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
tRET
(2)
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
Conditions
TA = -40°C to
105 °C
Min(1) Typ Max
10
-
-
300
-
-
30
-
-
30
-
-
10
-
-
10
-
-
Unit
kcycles
TRET = +85 °C
years
TRET = +105 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.
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6.3.10
STM32L151VD-X STM32L152VD-X
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 36. They are based on the EMS levels and classes
defined in application note AN1709.
Table 36. EMS characteristics
Symbol
Parameter
Conditions
VFESD
VDD = 3.3 V, LQFP100, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
Level/
Class
VDD = 3.3 V, LQFP100, TA = +25
°C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 37. EMI characteristics
Max vs. frequency range
Symbol Parameter
SEMI
6.3.11
Conditions
VDD = 3.6 V,
TA = 25 °C,
Peak level LQFP100 package
compliant with IEC
61967-2
Monitored
frequency band
4 MHz
16 MHz 32 MHz
voltage voltage voltage
range 3 range 2 range 1
0.1 to 30 MHz
-14
-6
-4
30 to 130 MHz
-11
0
9
130 MHz to 1GHz
-7
-1
9
SAE EMI Level
1
2
2.5
Unit
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.
Table 38. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Electrostatic
VESD(HBM) discharge voltage
(human body model)
Class
TA = +25 °C, conforming
to JESD22-A114
Electrostatic
TA = +25 °C, conforming
VESD(CDM) discharge voltage
to ANSI/ESD STM5.3.1.
(charge device model)
Maximum
Unit
value(1)
2
2000
LQFP100
C4
500
WLCSP104
C3
250
V
V
1. Guaranteed by characterization results.
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STM32L151VD-X STM32L152VD-X
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 39. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 40.
Table 40. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Injected current on all 5 V tolerant (FT) pins
IINJ
Injected current on BOOT0
Injected current on any other pin
Negative
injection
Positive
injection
-5 (1)
NA(2)
-0
NA(2)
-5
(1)
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
2. Injection is not possible.
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6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL
compliant.
Table 41. I/O static characteristics
Symbol
VIL
VIH
Parameter
Conditions
Input low level voltage
Input high level voltage
Ilkg
I/O Schmitt trigger voltage
hysteresis(2)
Input leakage current
(4)
Typ
Max
0.3
Unit
VDD(1)(2)
TC and FT I/O
-
-
BOOT0
-
-
0.14 VDD(2)
TC I/O
0.45 VDD+0.38(2)
-
-
FT I/O
0.39
VDD+0.59(2)
-
-
0.15
VDD+0.56(2)
-
-
BOOT0
Vhys
Min
V
TC and FT I/O
-
10% VDD(3)
-
BOOT0
-
0.01
-
VSS ≤VIN ≤VDD
I/Os with LCD
-
-
±50
VSS ≤VIN ≤VDD
I/Os with analog
switches
-
-
±50
VSS ≤VIN ≤VDD
I/Os with analog
switches and LCD
-
-
±50
VSS ≤VIN ≤VDD
I/Os with USB
-
-
±250
VSS ≤VIN ≤VDD
TC and FT I/Os
-
-
±50
FT I/O
VDD ≤VIN ≤5V
-
-
±10
µA
nA
RPU
Weak pull-up equivalent
resistor(5)(1)
VIN = VSS
25
45
65
kΩ
RPD
Weak pull-down equivalent
resistor(5)
VIN = VDD
25
45
65
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by test in production.
2. Guaranteed by design.
3. With a minimum of 200 mV.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 42.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 10).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 10).
Output voltage levels
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL
compliant.
Table 42. Output voltage characteristics
Symbol
VOL(1)(2)
Parameter
Output low level voltage for an I/O pin
VOH
(2)(3)
Output high level voltage for an I/O pin
VOL
(3)(4)
Output low level voltage for an I/O pin
VOH (3)(4) Output high level voltage for an I/O pin
VOL(1)(4)
VOH
(3)(4)
Conditions
Min
Max
IIO = 8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD-0.4
-
IIO = 4 mA
1.65 V < VDD < 3.6 V V -0.45
DD
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
IIO = 20 mA
2.7 V < VDD < 3.6 V
Unit
0.45
-
-
1.3
VDD-1.3
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 10
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Guaranteed by test in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 10 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Guaranteed by characterization results.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 15 and
Table 43, respectively.
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 12.
Table 43. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
-
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
Conditions
fmax(IO)out
tf(IO)out
tr(IO)out
Min
Parameter
tf(IO)out
tr(IO)out
Output rise and fall time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-
Unit
kHz
ns
MHz
ns
MHz
ns
MHz
ns
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 15.
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Electrical characteristics
STM32L151VD-X STM32L152VD-X
Figure 15. I/O AC characteristics definition
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6.3.14
AIC
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 44)
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 12.
Table 44. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL(NRST)(1)
NRST input low level
voltage
-
-
-
0.3 VDD
VIH(NRST)(1)
NRST input high
level voltage
-
0.39VDD+0.59
-
-
VOL(NRST)(1)
NRST output low
level voltage
Unit
V
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
0.4
Vhys(NRST)(1)
NRST Schmitt trigger
voltage hysteresis
-
-
10%VDD(2)
-
mV
RPU
Weak pull-up
equivalent resistor(3)
VIN = VSS
25
45
65
kΩ
VF(NRST)(1)
NRST input filtered
pulse
-
-
-
50
ns
VNF(NRST)(3)
NRST input not
filtered pulse
-
350
-
-
ns
1. Guaranteed by design.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
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Electrical characteristics
Figure 16. Recommended NRST pin protection
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DLE
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 44. Otherwise the reset will not be taken into account by the device.
6.3.15
TIM timer characteristics
The parameters given in the Table 45 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).
Table 45. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 32 MHz
31.25
-
ns
0
fTIMxCLK/2
MHz
0
16
MHz
16
bit
65536
tTIMxCLK
2048
µs
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz
Timer resolution
-
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
-
tMAX_COUNT Maximum possible count
1
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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Electrical characteristics
6.3.16
STM32L151VD-X STM32L152VD-X
Communications interfaces
I2C interface characteristics
The device I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 46. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output ction characteristics (SDA and SCL).
Table 46. I2C characteristics
Symbol
Parameter
Standard mode
I2C(1)(2)
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
-
3450(3)
-
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
tSP
Pulse width of spikes that
are suppressed by the
analog filter
0
50(4)
0
50(4)
ns
µs
ns
µs
1. Guaranteed by design.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
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Electrical characteristics
Figure 17. I2C bus AC waveforms and measurement circuit
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100
-
-
300
-
-
50
-
Normal mode
55
100
-
Low-power mode
65
110
-
4
-
-
20
-
-
-
-
50
VDD100
-
-
VDD-50
-
-
-
-
100
-
-
50
Low-power mode
Open loop gain
VDD>2.4 V
Typ
Normal mode
Normal mode
AO
DC
Min(2)
Normal mode
Low-power mode
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STM32L151VD-X STM32L152VD-X
Package information
Figure 35. Thermal resistance suffix 7
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Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Ordering information
8
STM32L151VD-X STM32L152VD-X
Ordering information
Table 68. STM32L151VD-X and STM32L152VD-X Ordering information scheme
Example:
STM32
L
151 V
D
Y
6
X
D
TR
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low-power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
V = 100/104 pins
Flash memory size
D=384 Kbytes of Flash memory
Package
T = LQFP
Y = WLCSP104
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
X = device generation X
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact the nearest ST sales office.
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9
Revision History
Revision History
Table 69. Document revision history
Date
Revision
22-Jan-2015
1
Initial release.
2
Updated Section 7: Package information structure: paragraph titles
and paragraph heading level.
Updated Section 7.1: LQFP100, 14 x 14 mm, 100-pin low-profile quad
flat package information removing gate mark in Figure 30.
Updated Section 7: Package information for LQFP100 & WLCSP104
package device marking adding text in for device orientation versus pin
1 / ball A1 identifier.
Updated Figure 31: WLCSP104, 0.4 mm pitch wafer level chip scale
package outline.
Updated Table 65: WLCSP104, 0.4 mm pitch wafer level chip scale
package mechanical data.
Added Figure 32: WLCSP104, 0.4 mm pitch wafer level chip scale
package recommended footprint.
Added Table 66: WLCSP104, 0.4 mm pitch recommended PCB design
rules.
Updated Table 7: STM32L151VD-X and STM32L152VD-X pin
definitions ADC inputs.
Updated Table 15: Embedded internal reference voltage temperature
coefficient at 100ppm/°C and table footnote 3: “guaranteed by design”
changed by “guaranteed by characterization results”.
Updated Table 62: Comparator 2 characteristics new maximum
threshold voltage temperature coefficient at 100ppm/°C.
28-Apr-2015
Changes
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Revision History
STM32L151VD-X STM32L152VD-X
Table 69. Document revision history (continued)
Date
12-Feb-2016
28-Aug-2017
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Revision
Changes
3
Updated cover page putting eight SPIs in the peripheral
communication interface list.
Updated Table 1: Ultra-low-power STM32L151VD-X and
STM32L152VD-X device features and peripheral counts SPI and I2S
lines.
Updated Table 38: ESD absolute maximum ratings CDM class.
Updated all the notes, removing ‘not tested in production’.
Updated Table 9: Voltage characteristics adding note about VREF- pin.
Updated Table 4: Functionalities depending on the working mode (from
Run/active down to standby) LSI and LSE functionalities putting “Y” in
Standby mode.
4
Updated Table 41: I/O static characteristics pull-up and pull-down
values.
Updated Table 44: NRST pin characteristics pull-up values.
Updated Section 7: Package information adding information about
other optional marking or inset/upset marks.
Updated note 1 below all the package device marking figures.
Updated Section 7: Package information replacing “Marking of
engineering samples” by “device marking”.
Updated Nested vectored interrupt controller (NVIC) in Section 3.2:
ARM® Cortex®-M3 core with MPU about process state automatically
saved.
Updated Table 2: Functionalities depending on the operating power
supply range removing I/O operation column and adding note about
GPIO speed.
Updated Table 40: I/O current injection susceptibility note by ‘injection
is not possible’.
Updated Figure 16: Recommended NRST pin protection note about
the 0.1uF capacitor.
Updated Table 57: DAC characteristics resistive load.
Updated Section 3.1: Low-power modes Low-power run mode (MSI)
RC oscillator clock.
Updated Table 4: Functionalities depending on the working mode
(from Run/active down to standby) disabling I2C functionality in Lowpower Run and Low-power Sleep modes.
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STM32L151VD-X STM32L152VD-X
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