STM32L151xE STM32L152xE
Ultra-low-power 32-bit MCU Arm®-based Cortex®-M3 with 512KB
Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 290 nA Standby mode (3 wakeup pins)
– 1.11 µA Standby mode + RTC
– 560 nA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 11 µA Low-power run mode down to 4.6 µA
in Low-power sleep mode
– 195 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
• Core: Arm® Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
• CRC calculation unit, 96-bit unique ID
• Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 16 MHz oscillator factory trimmed
RC(+/-1%) with PLL option
– Internal low-power 37 kHz oscillator
– Internal multispeed low-power 65 kHz to
4.2 MHz oscillator
– PLL for CPU clock and USB (48 MHz)
April 2021
This is information on a product in full production.
UFBGA132
(7 × 7 mm)
WLCSP104
(0.4 mm pitch)
– USB and USART supported
• Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
• Memories
– 512 Kbytes of Flash memory with ECC
(with 2 banks of 256 Kbytes enabling RWW
capability)
– 80 Kbytes of RAM
– 16 Kbytes of true EEPROM with ECC
– 128-byte backup register
• LCD driver (except STM32L151xE devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter
• Up to 34 capacitive sensing channels
• Pre-programmed bootloader
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
• Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power comparators
(window mode and wake up capability)
• DMA controller 12x channels
• 11x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USARTs
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
– 2x I2Cs (SMBus/PMBus)
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
• Development support: serial wire debug, JTAG
and trace
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STM32L151xE STM32L152xE
Table 1. Device summary
Reference
Part number
STM32L151xE
STM32L151QE, STM32L151RE, STM32L151VE, STM32L151ZE
STM32L152xE
STM32L152QE, STM32L152RE, STM32L152VE, STM32L152ZE
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Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3
Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Arm® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
3.6
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9
LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14
System configuration controller and routing interface . . . . . . . . . . . . . . . 27
3.15
Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STM32L151xE STM32L152xE
3.16
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.2
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.3
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.17.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.4
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.5
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1
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Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.7
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.8
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 62
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.17
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.18
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.19
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.21
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.22
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.2
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.3
WLCSP104 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4
UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.5
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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List of tables
STM32L151xE STM32L152xE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32L151xE and STM32L152xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 62
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Current consumption in Run mode, code with data processing running from Flash. . . . . . 66
Current consumption in Run mode, code with data processing running from RAM . . . . . . 67
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 73
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 86
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DS10002 Rev 10
STM32L151xE STM32L152xE
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
List of tables
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 96
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
WLCSP104 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
WLCSP104 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
STM32L151xE and STM32L152xE Ordering information scheme . . . . . . . . . . . . . . . . . . 132
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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7
List of figures
STM32L151xE STM32L152xE
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
8/136
Ultra-low-power STM32L151xE and STM32L152xE block diagram. . . . . . . . . . . . . . . . . . 13
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32L15xRE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32L15xVE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L15xVEY WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L15xQE UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L15xZE LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
WLCSP104 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
WLCSP104 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
WLCSP104 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
UFBGA132 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
DS10002 Rev 10
STM32L151xE STM32L152xE
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xE and STM32L152xE ultra-low-power Arm® Cortex®-M3 based
microcontroller product line. STM32L151xE and STM32L152xE devices are
microcontrollers with a Flash memory density of 512 Kbytes.
The ultra-low-power STM32L151xE and STM32L152xE family includes devices in 5
different package types: from 64 pins to 144 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151xE and STM32L152xE
microcontroller family suitable for a wide range of applications:
•
Medical and handheld equipment
•
Application control and user interface
•
PC peripherals, gaming, GPS and sport equipment
•
Alarm systems, wired and wireless sensors, video intercom
•
Utility metering
This STM32L151xE and STM32L152xE datasheet must be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M3 core, refer to the Arm® Cortex®-M3 technical
reference manual, available from the www.arm.com website. Figure 1 shows the general
block diagram of the device family.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L15xE errata sheet (ES0235), available on the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS10002 Rev 10
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56
Description
2
STM32L151xE STM32L152xE
Description
The ultra-low-power STM32L151xE and STM32L152xE devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance Arm®
Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 512 Kbytes
and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
The STM32L151xE and STM32L152xE devices offer two operational amplifiers, one 12-bit
ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151xE and STM32L152xE devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, two UARTs
and an USB. The STM32L151xE and STM32L152xE devices offer up to 34 capacitive
sensing channels to simply add a touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151xE devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.
The ultra-low-power STM32L151xE and STM32L152xE devices operate from a 1.8 to 3.6 V
power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of lowpower applications.
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DS10002 Rev 10
STM32L151xE STM32L152xE
2.1
Description
Device overview
Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
counts
Peripheral
STM32L15xRE
STM32L15xVE
STM32L15xQE
Flash (Kbytes)
512
Data EEPROM (Kbytes)
16
RAM (Kbytes)
80
Timers
Communication
interfaces
32 bit
1
General-purpose
6
Basic
2
SPI
8(3)(1)
I2S
2
I2C
2
USART
5
USB
1
GPIOs
51
83
Operational amplifiers
12-bit synchronized ADC
Number of channels
1
21
1
25
1
1
40
4x44 or 8x40
2
23
33
Max. CPU frequency
Packages
1
40
1
4x32 or 8x28
Capacitive sensing channels
Operating temperatures
115
2
2
Comparators
Operating voltage
109
2
12-bit DAC
Number of channels
LCD (2)
COM x SEG
STM32L15xZE
34
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
LQFP64
LQFP100,
WLCSP104
UFBGA132
LQFP144
1. 5 SPIs are USART configured in synchronous mode emulating SPI master.
2. STM32L152xx devices only.
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56
Description
2.2
STM32L151xE STM32L152xE
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others clearly allow very cost-optimized applications to be built by reducing BOM.
Note:
STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.
2.2.1
Performance
All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and Arm Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
2.2.3
•
Analog peripherals: ADC, DAC and comparators
•
Digital peripherals: RTC and some communication interfaces
Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
2.2.4
•
Same power supply range from 1.65 V to 3.6 V
•
Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•
Fast startup strategy from low-power modes
•
Flexible system clock
•
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
Features
ST ultra-low-power continuum also lies in feature compatibility:
12/136
•
More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•
Memory density ranging from 2 to 512 Kbytes
DS10002 Rev 10
STM32L151xE STM32L152xE
Functional overview
Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram
TRACECK, TRACED0, TRACED1, TRACED2, TRACED4
Fmax: 32 MHz
MPU
Dbus
System
NVIC
GP DMA 7 channels
EEPROM ob l
M3 CPU
VOLT. REG.
ibus
Bus Matrix 5M / 5S
NJTRST
JTDI
JTCK / SWCLK
JTMS / SWDAT
JTDO
as AF
512 KB PROGRAM
16 KB DATA
8KB BOOT
DUAL BANK
SRAM 80K
BOR
PB[15:0]
GPIO PORT B
PC[15:0]
GPIO PORT C
PD[15:0]
GPIO PORT D
PE[15:0]
GPIO PORT E
PH[2:0]
GPIO PORT H
PF[15:0]
GPIO PORT F
115 AF
MOSI, MISO,
SCK, NSS as AF
RX, TX, CTS, RTS,
SmartCard as AF
AHB/APB2
12bit ADC
VSSREF_ADC*
Temp sensor
IF
USB SRAM 512 B
WinWATCHDOG
TIMER6
TIMER7
4 channels
TIMER3
4 channels
TIMER4
4 channels
TIMERS (32 bits)
4 channels
USART2
RX, TX, CTS, RTS,
SmartCard as AF
USART3
RX, TX, CTS, RTS,
SmartCard as AF
USART4
RX, TX as AF
USART5
RX, TX as AF
SPI2/I2S
2x(8x16bit)
MOSI, MISO, SCK,NSS,WS, CK
MCK, SD as AF
SPI3/I2S
2x(8x16bit)
MOSI, MISO, SCK,NSS,WS, CK
MCK, SD as AF
I2C1
SCL, SDA
As AF
I2C2
SCL, SDA, SMBus, PMBus
As AF
USB2.0 FS device
Cap. sensing
General purpose
timers
2 channels
TIMER9
1 channel
TIMER10
1 channel
TIMER11
VLCD = 2.5V to 3.6V
TIMER2
AHB/APB1
USART1
40 AF
VDDREF_ADC*
LCD Booster
SPI1
@VDDA
TAMPER
@VDD33
GPIO PORT G
EXT.IT
WKUP
Backup
Reg 128
Backup interface
APB1: Fmax = 32 MHz
PG[15:0]
@VDDA
OSC32_IN
OSC32_OUT
RTC_OUT
RTC V2
AWU
VLCD
GPIO PORT A
OSC_OUT
XTAL 32 kHz
AHB: Fmax = 32 MHz
PA[15:0]
OSC_IN
XTAL OSC
1-24 MHz
RC LSIA
@VDD
GP Comp
PU / PD
@ VDD33
Standby
interface
RC MSI
Int
NRST
WDG 32K
RC HSI
Cap. sens
COMPx_INx
PDR
PLL &
Clock
Mgmt
FCLK
PVD
Vref
PDR
AHBPCLK
APBPCLK
HCLK
BOR / Bgap
Vss
Supply monitoring
@VDDA
Supply
monitoring
VDD33=1.65V to 3.6V
EEPROM 64 bit
GP DMA2 5 channels
VDDA /
VSSA
@ VDD 33
POWER
VDD CORE
Trace Controller ETM
pbus
Interface
JTAG & SW
APB2: Fmax = 32 MHz
3
Functional overview
LCD 8x40
OPAMP1
USB_DP
USB_DM
Px
SEGx
COMx
@VDDA
OPAMP2
12bit DAC1
DAC_OUT1 as AF
12bit DAC2
DAC_OUT2 as AF
IF
IIF
F
VINP
a
VOUT
VINP
VINM
VOUT
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56
Functional overview
3.1
STM32L151xE STM32L152xE
Low-power modes
The ultra-low-power STM32L151xE and STM32L152xE devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal lowdrop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.
There are three power consumption ranges:
•
Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
•
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•
Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI
range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or
Flash memory, and internal regulator in low-power mode to minimize the regulator's
operating current. In low-power run mode, the clock frequency and the number of
enabled peripherals are both limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
14/136
DS10002 Rev 10
STM32L151xE STM32L152xE
•
Functional overview
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
-
Functionalities depending on the operating power supply
range(1)
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage scaling
range
VDD= VDDA = 1.65 to 1.71 V
Not functional
Not functional
Range 2 or Range 3
Not functional
Not functional
Range 1, Range 2 or
Range 3
Conversion time up
to 500 Ksps
Not functional
Range 1, Range 2 or
Range 3
VDD=VDDA= 1.71 to 1.8 V(2)
VDD=VDDA= 1.8 to 2.0 V(2)
DS10002 Rev 10
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Functional overview
STM32L151xE STM32L152xE
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply
range(1)
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage scaling
range
VDD=VDDA = 2.0 to 2.4 V
Conversion time up
to 500 Ksps
Functional(3)
Range 1, Range 2 or
Range 3
VDD=VDDA = 2.4 to 3.6 V
Conversion time up
to 1 Msps
Functional(3)
Range 1, Range 2 or
Range 3
1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 44: I/O AC
characteristics for more information about I/O speed.
2. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop
due to current consumption peak when frequency increases. It must also respect 5 µs delay between two
changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz,
wait 5 µs, then switch from 16 MHz to 32 MHz.
3. Must be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
16/136
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
Range 3
DS10002 Rev 10
STM32L151xE STM32L152xE
Functional overview
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Ips
Run/Active
Sleep
Stop
Standby
Lowpower
Run
Lowpower
Sleep
-
Wakeup
capability
-
Wakeup
capability
CPU
Y
--
Y
--
--
--
--
--
Flash
Y
Y
Y
Y
--
--
--
--
RAM
Y
Y
Y
Y
Y
--
--
--
Backup Registers
Y
Y
Y
Y
Y
--
Y
--
EEPROM
Y
Y
Y
Y
Y
--
--
--
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
--
DMA
Y
Y
Y
Y
--
--
--
--
Programmable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
--
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
--
Power Down Rest
(PDR)
Y
Y
Y
Y
Y
--
Y
--
High Speed
Internal (HSI)
Y
Y
--
--
--
--
--
--
High Speed
External (HSE)
Y
Y
--
--
--
--
--
--
Low Speed Internal
(LSI)
Y
Y
Y
Y
Y
--
Y
--
Low Speed
External (LSE)
Y
Y
Y
Y
Y
--
Y
--
Multi-Speed
Internal (MSI)
Y
Y
Y
Y
--
--
--
--
Inter-Connect
Controller
Y
Y
Y
Y
--
--
--
--
RTC
Y
Y
Y
Y
Y
Y
Y
--
RTC Tamper
Y
Y
Y
Y
Y
Y
Y
Y
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
Y
Y
LCD
Y
Y
Y
Y
Y
--
--
--
USB
Y
Y
--
--
--
Y
--
--
--
--
USART
Y
Y
Y
Y
Y
(1)
SPI
Y
Y
Y
Y
--
--
--
--
I2C
Y
Y
--
--
--
(1)
--
--
DS10002 Rev 10
17/136
56
Functional overview
STM32L151xE STM32L152xE
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Ips
Run/Active
Sleep
Stop
Standby
Lowpower
Run
Lowpower
Sleep
-
Wakeup
capability
-
Wakeup
capability
ADC
Y
Y
--
--
--
--
--
--
DAC
Y
Y
Y
Y
Y
--
--
--
Tempsensor
Y
Y
Y
Y
Y
--
--
--
OP amp
Y
Y
Y
Y
Y
--
--
--
Comparators
Y
Y
Y
Y
Y
Y
--
--
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
WWDG
Y
Y
Y
Y
--
--
--
--
Touch sensing
Y
Y
--
--
--
--
--
--
Systic Timer
Y
Y
Y
Y
-
--
--
--
GPIOs
Y
Y
Y
Y
Y
Y
--
3 pins
0 µs
0.4 µs
3 µs
46 µs
Wakeup time to
Run mode
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 195
µA/MHz (from
Flash)
Down to 38
µA/MHz (from
Flash)
Down to
11 µA
Down to
4.6 µA
< 8 µs
58 µs
0.53 µA
(no RTC)
VDD=1.8V
0.285 µA
(no RTC)
VDD=1.8V
1.2 µA
(with RTC)
VDD=1.8V
0.97 µA
(with RTC)
VDD=1.8V
0.56 µA
(no RTC)
VDD=3.0V
0.29 µA
(no RTC)
VDD=3.0V
1.4 µA
(with RTC)
VDD=3.0V
1.11 µA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
Arm® Cortex®-M3 core with MPU
The Arm® Cortex®-M3 processor is the industry leading processor for embedded systems. It
has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an Arm core in the memory size usually
associated with 8- and 16-bit devices.
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DS10002 Rev 10
STM32L151xE STM32L152xE
Functional overview
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded Arm core, the STM32L151xE and STM32L152xE devices are
compatible with all Arm tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xE and STM32L152xE devices embed a nested vectored
interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16
interrupt lines of Arm® Cortex®-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
3.3.2
•
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up must guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the
POR area.
DS10002 Rev 10
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56
Functional overview
STM32L151xE STM32L152xE
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
3.3.4
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.
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DS10002 Rev 10
STM32L151xE STM32L152xE
3.4
Functional overview
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
•
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
•
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
•
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
DS10002 Rev 10
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56
Functional overview
STM32L151xE STM32L152xE
Figure 2. Clock tree
Standby supplied voltage domain
enable
Watchdog
LSI RC
LSI tempo
LSE OSC
LSE tempo
Watchdog
LS
RTC enable
RTC
Radio Sleep Timer
Radio Sleep Timer enable
LS
LS LS
LS
@VDDCORE
1 MHz
LCD enable
@V33
MSI RC
level shifters
@VDDCORE
CK_ADC
ADC enable
ck_lsi
ck_lse
CK_LCD
MCO
/ 1,2,4,8,16
not deepsleep
/ 2,4,8,16
CK_PWR
@V33
not deepsleep
HSI RC
CK_FCLK
not (sleep or
deepsleep
level shifters
@VDDCORE
System
clock
@V33
HSE
OSC
ck_msi
ck_hsi
ck_hse
level shifters
@VDDCORE
AHB
prescaler
/ 1,2,..512
@V33 ck_pll
PLL
ck_pllin X 3,4,6,8,12
16,24,32,48
LS
@V33
1 MHz clock
detector
not (sleep or
deepsleep)
/8
CK_CPU
CK_TIMSYS
APB1
APB2
prescaler prescaler
/ 1,2,4,8,16 / 1,2,4,8,16
/ 2, 3, 4
HSE present or not
LS
level shifters
@VDDCORE
Clock
source
control
usben and (not deepsleep)
CK_USB48
ck_usb = Vco / 2 (Vco must be atz)
96 MH
CK_TIMTGO
CK_APB1
timer9en and (not deepsleep)
apb1 periphen and (not deepsleep)
if (APB1 presc = 1)x1
x2
else
apb2 periphen and (not deepsleep)
CK_APB2
MS18583V1
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DS10002 Rev 10
STM32L151xE STM32L152xE
3.5
Functional overview
Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
DS10002 Rev 10
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56
Functional overview
3.7
STM32L151xE STM32L152xE
Memories
The STM32L151xE and STM32L152xE devices have the following features:
•
80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
512 Kbytes of embedded Flash program memory
–
16 Kbytes of data EEPROM
–
Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Arm Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
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DS10002 Rev 10
STM32L151xE STM32L152xE
3.9
Functional overview
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
3.10
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
•
Supports static, 1/2, 1/3 and 1/4 bias
•
Phase inversion to reduce power consumption and EMI
•
Up to 8 pixels can be programmed to blink
•
Unneeded segments and common pins can be used as general I/O pins
•
LCD RAM can be updated at any time owing to a double-buffer
•
The LCD controller can operate in Stop mode
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151xE and STM32L152xE
devices with up to 40 external channels, performing conversions in single-shot or scan
mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs with up to 28 external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
DS10002 Rev 10
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56
Functional overview
STM32L151xE STM32L152xE
stored by ST in the system memory area, accessible in read-only mode. See Table 60:
Temperature sensor calibration values.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 15: Embedded internal reference voltage calibration values.
3.11
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
•
Two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channels, independent or simultaneous conversions
•
DMA capability for each channel (including the underrun interrupt)
•
External triggers for conversion
•
Input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L151xE and STM32L152xE devices. The
DAC channels are triggered through the timer update outputs that are also connected to
different DMA channels.
3.12
Operational amplifier
The STM32L151xE and STM32L152xE devices embed two operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.
The operational amplifiers feature:
26/136
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
DS10002 Rev 10
STM32L151xE STM32L152xE
3.13
Functional overview
Ultra-low-power comparators and reference voltage
The STM32L151xE and STM32L152xE devices embed two comparators sharing the same
current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).
•
One comparator with fixed threshold
•
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
DAC output
–
External I/O
–
Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4)
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.14
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
VREFINT.
3.15
Touch sensing
The STM32L151xE and STM32L152xE devices provide a simple solution for adding
capacitive sensing functionality to any application. Thesedevices offer up to 34 capacitive
sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see Section 3.14: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
DS10002 Rev 10
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56
Functional overview
3.16
STM32L151xE STM32L152xE
Timers and watchdogs
The ultra-low-power STM32L151xE and STM32L152xE devices include seven generalpurpose timers, two basic timers, and two watchdog timers.
Table 6 compares the features of the general-purpose and basic timers.
Table 6. Timer feature comparison
DMA
Capture/compare Complementary
request
channels
outputs
generation
Timer
Counter
resolution
Counter type
Prescaler factor
TIM2,
TIM3,
TIM4
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM5
32-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM9
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM10,
TIM11
16-bit
Up
Any integer between
1 and 65536
No
1
No
TIM6,
TIM7
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L151xE
and STM32L152xE devices (see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
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DS10002 Rev 10
STM32L151xE STM32L152xE
Functional overview
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.16.2
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.16.3
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.16.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.16.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17
Communication interfaces
3.17.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three
USARTs provide hardware management of the CTS and RTS signals and are ISO 7816
compliant.
All USART/UART interfaces can be served by the DMA controller.
DS10002 Rev 10
29/136
56
Functional overview
3.17.3
STM32L151xE STM32L152xE
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
3.17.4
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.17.5
Universal serial bus (USB)
The STM32L151xE and STM32L152xE devices embed a USB device peripheral compatible
with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s)
function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the
clock source must use a HSE crystal oscillator).
3.18
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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DS10002 Rev 10
STM32L151xE STM32L152xE
Functional overview
3.19
Development support
3.19.1
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
3.19.2
Embedded Trace Macrocell™
The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151xE and STM32L152xE device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.
DS10002 Rev 10
31/136
56
Pin descriptions
4
STM32L151xE STM32L152xE
Pin descriptions
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 3. STM32L15xRE LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_ 2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
PH0 -OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP1
PA1
PA2
ai15693c
1. This figure shows the package top view.
32/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 4. STM32L15xVE LQFP100 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
PH2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE2
PE3
PE4
PE5
PE6-WKUP3
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP1
PA1
PA2
ai15692c
1. This figure shows the package top view.
DS10002 Rev 10
33/136
56
Pin descriptions
STM32L151xE STM32L152xE
Figure 5. STM32L15xVEY WLCSP104 ballout
1
2
3
4
5
6
7
8
9
A
VSS_2
PD0
PD4
PD7
PB4
PB5
BOOT0
PE1
VDD_3
B
PA15
PC12
PD5
PD6
PB3
PB7
PE0
VDD_3
PE5
C
VDD_2
PC11
PD2
PD3
PB6
PB9
VSS_3
PE4
D
PH2
VSS_2
PA14
PD1
PB8
PE2
PE3
PC14
OSC32IN
E
PA11
PA12
PA13
PC10
PE6
WKUP3
VLCD
VSS_5
F
PA9
PA10
PA8
PC9
PC0
NRST
PH0
OSCIN
PH1
OSCOUT
G
PC7
PC8
PD15
PD11
VDDA
VREF+
PC3
PC2
H
PC6
PD13
PD12
PD8
PA6
PA3
VREF-
PC1
J
PD14
PD9
PB13
PB12
PE10
PB0
PA4
PA2
VSSA
K
PD10
PB15
VDD_1
PE15
PE13
PB1
PA7
VSS_4
PA0
WKUP1
L
PB14
VSS_1
PB11
PE14
PE11
PE7
PC4
VDD_4
PA1
M
VSS_1
PB10
PE12
PE9
PE8
PB2
PC5
PA5
VDD_4
PC13
WKUP2
PC15
OSC32OUT
VDD_5
MSv41009V1
1. This figure shows the package top view.
34/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
Figure 6. STM32L15xQE UFBGA132 ballout
1
2
3
4
5
6
7
8
9
10
11
12
A
PE3
PE1
PB8
BOOT0
PD7
PD5
PB4
PB3
PA15
PA14
PA13
PA12
B
PE4
PE2
PB9
PB7
PB6
PD6
PD4
PD3
PD1
PC12
PC10
PA11
PE0
VDD_3
PB5
PG14
PG13
PD2
PD0
PC11
PH2
PA10
PF1
PF0
PG12
PG10
PG9
PA9
PA8
PC9
PG5
PC8
PC7
PC6
C
PC13WKUP2
PE5
D
PC14OSC32
_IN
PE6WKUP3
VSS_3
PF2
E
PC15OSC32
_OUT
VLCD
VSS_6
PF3
F
PH0
OSC_IN
VSS_5
PF4
PF5
VSS_9
VSS_10
PG3
PG4
VSS_2
VSS_1
G
PH1
OSC_
OUT
VDD_5
PF6
PF7
VDD_9
VDD_10
PG1
PG2
VDD_2
VDD_1
VDD_6
PF8
PG0
PD15
PD14
PD13
H
PC0
NRST
J
VSSA
PC1
PC2
PA4
PA7
PF9
PF12
PF14
PF15
PD12
PD11
PD10
K
NC
PC3
PA2
PA5
PC4
PF11
PF13
PD9
PD8
PB15
PB14
PB13
L
VREF+
PA0WKUP1
PA3
PA6
PC5
PB2
PE8
PE10
PE12
PB10
PB11
PB12
M
VDDA
PA1
PB0
PB1
PE7
PE9
PE11
PE13
PE14
PE15
OPAMP1 OPAMP2
_VINM _VINM
MS33002V1
1. This figure shows the package top view.
DS10002 Rev 10
35/136
56
Pin descriptions
STM32L151xE STM32L152xE
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD_11
VSS_11
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD_10
VSS_10
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 7. STM32L15xZE LQFP144 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_2
VSS_2
PH2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD_9
VSS_9
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD_8
VSS_8
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6-WKUP3
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS_5
VDD_5
PF6
PF7
PF8
PF9
PF10
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0 -WKUP1
PA1
PA2
MS18581V2
1. This figure shows the package top view.
36/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
Table 7. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
Pin type
I/O structure
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TC
Standard 3.3 V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 8. STM32L151xE and STM32L152xE pin definitions
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
1
B2
1
-
D6
PE2
I/O
FT
PE2
TIM3_ETR/LCD_SEG38/
TRACECLK
-
2
A1
2
-
D7
PE3
I/O
FT
PE3
TIM3_CH1/LCD_SEG39/
TRACED0
-
3
B1
3
-
C8
PE4
I/O
FT
PE4
TIM3_CH2/TRACED1
-
4
C2
4
-
B9
PE5
I/O
FT
PE5
TIM9_CH1/TRACED2
-
5
D2
5
-
E6
PE6WKUP3
I/O
FT
PE6
TIM9_CH2/TRACED3
WKUP3/
RTC_TAMP3
6
E2
6
1
E7
VLCD(3)
S
-
VLCD
-
-
7
C1
7
2
C9
PC13-WKUP2
I/O
FT
PC13
-
WKUP2/RTC_TA
MP1/RTC_TS/
RTC_OUT
Pin name
DS10002 Rev 10
Alternate functions
Additional
functions
37/136
56
Pin descriptions
STM32L151xE STM32L152xE
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
8
D1
8
3
D8
PC14OSC32_IN(4)
I/O
TC
PC14
-
OSC32_IN
9
E1
9
4
D9
PC15OSC32_OUT
I/O
TC
PC15
-
OSC32_OUT
10
D6
-
-
-
PF0
I/O
FT
PF0
-
-
11
D5
-
-
-
PF1
I/O
FT
PF1
-
-
12
D4
-
-
-
PF2
I/O
FT
PF2
-
-
13
E4
-
-
-
PF3
I/O
FT
PF3
-
-
14
F3
-
-
-
PF4
I/O
FT
PF4
-
-
15
F4
-
-
-
PF5
I/O
FT
PF5
-
-
16
F2
10
-
E8
VSS_5
S
-
VSS_5
-
-
17
G2
11
-
E9
VDD_5
S
-
VDD_5
-
-
18
G3
-
-
-
PF6
I/O
FT
PF6
TIM5_CH1/TIM5_ETR
ADC_IN27
19
G4
-
-
-
PF7
I/O
FT
PF7
TIM5_CH2
ADC_IN28/
COMP1_INP
20
H4
-
-
-
PF8
I/O
FT
PF8
TIM5_CH3
ADC_IN29/
COMP1_INP
21
J6
-
-
-
PF9
I/O
FT
PF9
TIM5_CH4
ADC_IN30/
COMP1_INP
22
-
-
-
-
PF10
I/O
FT
PF10
-
ADC_IN31/
COMP1_INP
23
F1
12
5
F8
PH0-OSC_IN(5) I/O
TC
PH0
-
OSC_IN
24
G1
13
6
F9
PH1OSC_OUT(5)
TC
PH1
-
OSC_OUT
25
H2
14
7
F7
NRST
NRST
-
-
26
H1
15
8
F6
PC0
I/O
FT
PC0
LCD_SEG18
ADC_IN10/
COMP1_INP
27
J2
16
9
H9
PC1
I/O
FT
PC1
LCD_SEG19
ADC_IN11/
COMP1_INP
28
-
17
10 G9
PC2
I/O
FT
PC2
LCD_SEG20
ADC_IN12/
COMP1_INP
38/136
Pin name
I/O
I/O RST
DS10002 Rev 10
Alternate functions
Additional
functions
STM32L151xE STM32L152xE
Pin descriptions
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
-
J3
-
-
-
PC2
I/O
FT
PC2
LCD_SEG20
ADC_IN12/
COMP1_INP
-
K1
-
-
-
NC
I
-
NC
-
-
29
K2
18
11
G8
PC3
I/O
TC
PC3
LCD_SEG21
ADC_IN13/
COMP1_INP
30
J1
19
12
J9
VSSA
S
-
VSSA
-
-
31
-
20
-
H8
VREF-
S
-
VREF-
-
-
32
L1
21
-
G7
VREF+
S
-
VREF+
-
-
33
M1
22
13 G6
VDDA
S
-
VDDA
-
-
34
L2
23
14
K9
PA0-WKUP1
I/O
FT
PA0
TIM2_CH1_ETR/
TIM5_CH1/
USART2_CTS
WKUP1/RTC_TA
MP2/ADC_IN0/
COMP1_INP
35
M2
24
15
L9
PA1
I/O
FT
PA1
TIM2_CH2/TIM5_CH2/
USART2_RTS/
LCD_SEG0
ADC_IN1/
COMP1_INP/
OPAMP1_VINP
36
-
25
16
J8
PA2
I/O
FT
PA2
TIM2_CH3/TIM5_CH3/
TIM9_CH1/
USART2_TX/LCD_SEG1
ADC_IN2/
COMP1_INP/
OPAMP1_VINM
-
K3
-
-
-
PA2
I/O
FT
PA2
TIM2_CH3/TIM5_CH3/
TIM9_CH1/
USART2_TX/LCD_SEG1
ADC_IN2/
COMP1_INP
-
M3
-
-
-
OPAMP1_VINM
I
TC
OPAMP1_
VINM
-
-
37
L3
26
17
H7
PA3
I/O
TC
PA3
TIM2_CH4/TIM5_CH4/
TIM9_CH2/
USART2_RX/LCD_SEG2
ADC_IN3/
COMP1_INP/
OPAMP1_VOUT
38
-
27
18
K8
VSS_4
S
-
VSS_4
-
-
39
-
28
19
L8,
M9
VDD_4
S
-
VDD_4
-
-
40
J4
29
20
J7
PA4
I/O
TC
PA4
SPI1_NSS/SPI3_NSS/
I2S3_WS/
USART2_CK
ADC_IN4/
DAC_OUT1/
COMP1_INP
Pin name
DS10002 Rev 10
Alternate functions
Additional
functions
39/136
56
Pin descriptions
STM32L151xE STM32L152xE
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
UFBGA132
LQFP100
LQFP64
Pin Type(1)
I / O structure
Main
function(2)
(after
reset)
41
K4
30
21 M8
PA5
I/O
TC
PA5
TIM2_CH1_ETR/
SPI1_SCK
ADC_IN5/
DAC_OUT2/
COMP1_INP
42
L4
31
22
H6
PA6
I/O
FT
PA6
TIM3_CH1/TIM10_CH1/S
PI1_MISO/
LCD_SEG3
ADC_IN6/
COMP1_INP/
OPAMP2_VINP
43
-
32
23
K7
PA7
I/O
FT
PA7
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/
LCD_SEG4
ADC_IN7/
COMP1_INP/
OPAMP2_VINM
-
J5
-
-
-
PA7
I/O
FT
PA7
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/
LCD_SEG4
ADC_IN7/
COMP1_INP
-
M4
-
-
-
OPAMP2_VINM
I
TC
OPAMP2_
VINM
-
-
44
K5
33
24
L7
PC4
I/O
FT
PC4
LCD_SEG22
ADC_IN14/
COMP1_INP
45
L5
34
25 M7
PC5
I/O
FT
PC5
LCD_SEG23
ADC_IN15/
COMP1_INP
WLCSP104
LQFP144
Pin functions
Pin name
Alternate functions
Additional
functions
46
M5
35
26
J6
PB0
I/O
TC
PB0
TIM3_CH3/LCD_SEG5
ADC_IN8/
COMP1_INP/
OPAMP2_VOUT/
VREF_OUT
47
M6
36
27
K6
PB1
I/O
FT
PB1
TIM3_CH4/LCD_SEG6
ADC_IN9/
COMP1_INP/
VREF_OUT
48
L6
37
28 M6
PB2
I/O
FT
PB2/
BOOT1
BOOT1
ADC_IN0b
49
K6
-
-
-
PF11
I/O
FT
PF11
-
ADC_IN1b
50
J7
-
-
-
PF12
I/O
FT
PF12
-
ADC_IN2b
51
E3
-
-
-
VSS_6
S
-
VSS_6
-
-
52
H3
-
-
-
VDD_6
S
-
VDD_6
-
-
53
K7
-
-
-
PF13
I/O
FT
PF13
-
ADC_IN3b
54
J8
-
-
-
PF14
I/O
FT
PF14
-
ADC_IN6b
55
J9
-
-
-
PF15
I/O
FT
PF15
-
ADC_IN7b
40/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
56
H9
-
-
-
PG0
I/O
FT
PG0
-
ADC_IN8b
57
G9
-
-
-
PG1
I/O
FT
PG1
-
ADC_IN9b
58
M7
38
-
L6
PE7
I/O
TC
PE7
-
ADC_IN22/
COMP1_INP
59
L7
39
-
M5
PE8
I/O
TC
PE8
-
ADC_IN23/
COMP1_INP
60
M8
40
-
M4
PE9
I/O
TC
PE9
TIM2_CH1_ETR
ADC_IN24/
COMP1_INP
61
-
-
-
-
VSS_7
S
-
VSS_7
-
-
62
-
-
-
-
VDD_7
S
-
VDD_7
-
-
63
L8
41
-
J5
PE10
I/O
TC
PE10
TIM2_CH2
ADC_IN25/
COMP1_INP
64
M9
42
-
L5
PE11
I/O
FT
PE11
TIM2_CH3
-
65
L9
43
-
M3
PE12
I/O
FT
PE12
TIM2_CH4/SPI1_NSS
-
66
M10
44
-
K5
PE13
I/O
FT
PE13
SPI1_SCK
-
67
M11
45
-
L4
PE14
I/O
FT
PE14
SPI1_MISO
-
68
M12
46
-
K4
PE15
I/O
FT
PE15
SPI1_MOSI
-
69
L10
47
29 M2
PB10
I/O
FT
PB10
TIM2_CH3/I2C2_SCL/
USART3_TX/
LCD_SEG10
-
70
L11
48
30
L3
PB11
I/O
FT
PB11
TIM2_CH4/I2C2_SDA/
USART3_RX/
LCD_SEG11
-
71
F12
49
31
L2,
M1
VSS_1
S
-
VSS_1
-
-
72
G12
50
32
K3
VDD_1
S
-
VDD_1
-
-
PB12
TIM10_CH1/I2C2_SMBA/
SPI2_NSS/I2S2_WS/
USART3_CK/
LCD_SEG12
ADC_IN18/
COMP1_INP
73
L12
51
33
J4
Pin name
PB12
I/O
FT
DS10002 Rev 10
Alternate functions
Additional
functions
41/136
56
Pin descriptions
STM32L151xE STM32L152xE
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
I / O structure
Pin name
Pin Type(1)
WLCSP104
Pin functions
LQFP64
LQFP100
LQFP144
UFBGA132
Pins
Main
function(2)
(after
reset)
Alternate functions
Additional
functions
ADC_IN19/
COMP1_INP
74
K12
52
34
J3
PB13
I/O
FT
PB13
TIM9_CH1/SPI2_SCK/
I2S2_CK/
USART3_CTS/
LCD_SEG13
75
K11
53
35
L1
PB14
I/O
FT
PB14
TIM9_CH2/SPI2_MISO/
USART3_RTS/
LCD_SEG14
ADC_IN20/
COMP1_INP
76
K10
54
36
K2
PB15
I/O
FT
PB15
TIM11_CH1/SPI2_MOSI/
I2S2_SD/
LCD_SEG15
ADC_IN21/
COMP1_INP/
RTC_REFIN
77
K9
55
-
H4
PD8
I/O
FT
PD8
USART3_TX/
LCD_SEG28
-
78
K8
56
-
J2
PD9
I/O
FT
PD9
USART3_RX/
LCD_SEG29
-
79
J12
57
-
K1
PD10
I/O
FT
PD10
USART3_CK/
LCD_SEG30
-
80
J11
58
-
G4
PD11
I/O
FT
PD11
USART3_CTS/
LCD_SEG31
-
81
J10
59
-
H3
PD12
I/O
FT
PD12
TIM4_CH1/
USART3_RTS/
LCD_SEG32
-
82
H12
60
-
H2
PD13
I/O
FT
PD13
TIM4_CH2/LCD_SEG33
-
83
-
-
-
-
VSS_8
S
-
VSS_8
-
-
84
-
-
-
-
VDD_8
S
-
VDD_8
-
-
85
H11
61
-
J1
PD14
I/O
FT
PD14
TIM4_CH3/LCD_SEG34
-
86
H10
62
-
G3
PD15
I/O
FT
PD15
TIM4_CH4/LCD_SEG35
-
87
G10
-
-
-
PG2
I/O
FT
PG2
-
ADC_IN10b
88
F9
-
-
-
PG3
I/O
FT
PG3
-
ADC_IN11b
89
F10
-
-
-
PG4
I/O
FT
PG4
-
ADC_IN12b
90
E9
-
-
-
PG5
I/O
FT
PG5
-
-
91
-
-
-
-
PG6
I/O
FT
PG6
-
-
92
-
-
-
-
PG7
I/O
FT
PG7
-
-
93
-
-
-
-
PG8
I/O
FT
PG8
-
-
42/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
94
F6
-
-
-
VSS_9
S
-
VSS_9
-
-
95
G6
-
-
-
VDD_9
S
-
VDD_9
-
-
96
E12
63
37
H1
PC6
I/O
FT
PC6
TIM3_CH1/I2S2_MCK/
LCD_SEG24
-
97
E11
64
38 G1
PC7
I/O
FT
PC7
TIM3_CH2/I2S3_MCK/
LCD_SEG25
-
98
E10
65
39 G2
PC8
I/O
FT
PC8
TIM3_CH3/LCD_SEG26
-
99
D12
66
40
F4
PC9
I/O
FT
PC9
TIM3_CH4/LCD_SEG27
-
100 D11
67
41
F3
PA8
I/O
FT
PA8
USART1_CK/MCO/
LCD_COM0
-
101 D10
68
42
F1
PA9
I/O
FT
PA9
USART1_TX /
LCD_COM1
-
102 C12
69
43
F2
PA10
I/O
FT
PA10
USART1_RX /
LCD_COM2
-
103 B12
70
44
E1
PA11
I/O
FT
PA11
USART1_CTS/
SPI1_MISO
USB_DM
104 A12
71
45
E2
PA12
I/O
FT
PA12
USART1_RTS/
SPI1_MOSI
USB_DP
105 A11
72
46
E3
PA13
I/O
FT
JTMSSWDIO
JTMS-SWDIO
-
106 C11
73
-
D1
PH2
I/O
FT
PH2
-
-
107 F11
74
47
D2,
A1
VSS_2
S
-
VSS_2
-
-
108 G11
75
48
C1
VDD_2
S
-
VDD_2
-
-
109 A10
76
49
D3
PA14
I/O
FT
JTCKSWCLK
JTCK-SWCLK
-
JTDI
TIM2_CH1_ETR/
SPI1_NSS/SPI3_NSS/
I2S3_WS/LCD_SEG17/
JTDI
-
PC10
SPI3_SCK/I2S3_CK/
USART3_TX/ UART4_TX/
LCD_SEG28/
LCD_SEG40/LCD_COM4
-
110
111
A9
B11
77
78
50
51
B1
E4
Pin name
PA15
PC10
I/O
I/O
FT
FT
DS10002 Rev 10
Alternate functions
Additional
functions
43/136
56
Pin descriptions
STM32L151xE STM32L152xE
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
112 C10
79
52
C2
PC11
I/O
I / O structure
Pin name
Pin Type(1)
WLCSP104
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
Pins
FT
Main
function(2)
(after
reset)
Alternate functions
Additional
functions
PC11
SPI3_MISO/USART3_RX/
UART4_RX/
LCD_SEG29/
LCD_SEG41/LCD_COM5
-
-
113 B10
80
53
B2
PC12
I/O
FT
PC12
SPI3_MOSI/I2S3_SD/
USART3_CK/
UART5_TX/LCD_SEG30/
LCD_SEG42/
LCD_COM6
114
C9
81
-
A2
PD0
I/O
FT
PD0
TIM9_CH1/SPI2_NSS/
I2S2_WS
-
115
B9
82
-
D4
PD1
I/O
FT
PD1
SPI2_SCK/I2S2_CK
-
116
C8
83
54
C3
PD2
I/O
FT
PD2
TIM3_ETR/UART5_RX/
LCD_SEG31/
LCD_SEG43/LCD_COM7
-
117
B8
84
-
C4
PD3
I/O
FT
PD3
SPI2_MISO/
USART2_CTS
-
118
B7
85
-
A3
PD4
I/O
FT
PD4
SPI2_MOSI/I2S2_SD/
USART2_RTS
-
119
A6
86
-
B3
PD5
I/O
FT
PD5
USART2_TX
-
120
F7
-
-
-
VSS_10
S
-
VSS_10
-
-
121
G7
-
-
-
VDD_10
S
-
VDD_10
-
-
122
B6
87
-
B4
PD6
I/O
FT
PD6
USART2_RX
-
123
A5
88
-
A4
PD7
I/O
FT
PD7
TIM9_CH2/USART2_CK
-
124
D9
-
-
-
PG9
I/O
FT
PG9
-
-
125
D8
-
-
-
PG10
I/O
FT
PG10
-
-
126
-
-
-
-
PG11
I/O
FT
PG11
-
-
127
D7
-
-
-
PG12
I/O
FT
PG12
-
-
128
C7
-
-
-
PG13
I/O
FT
PG13
-
-
129
C6
-
-
-
PG14
I/O
FT
PG14
-
-
130
-
-
-
-
VSS_11
S
-
VSS_11
-
-
131
-
-
-
-
VDD_11
S
-
VDD_11
-
-
44/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Pin descriptions
Table 8. STM32L151xE and STM32L152xE pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP104
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after
reset)
132
-
-
-
-
PG15
I/O
FT
PG15
-
-
133
A8
89
55
B5
PB3
I/O
FT
JTDO
TIM2_CH2/SPI1_SCK/
SPI3_SCK/ I2S3_CK/
LCD_SEG7/JTDO
COMP2_INM
134
A7
90
56
A5
PB4
I/O
FT
NJTRST
TIM3_CH1/SPI1_MISO/
SPI3_MISO/
LCD_SEG8/NJTRST
COMP2_INP
COMP2_INP
Pin name
Alternate functions
Additional
functions
135
C5
91
57
A6
PB5
I/O
FT
PB5
TIM3_CH2/I2C1_SMBA/
SPI1_MOSI/
SPI3_MOSI/I2S3_SD/
LCD_SEG9
136
B5
92
58
C5
PB6
I/O
FT
PB6
TIM4_CH1/I2C1_SCL/
USART1_TX
COMP2_INP
137
B4
93
59
B6
PB7
I/O
FT
PB7
TIM4_CH2/I2C1_SDA/
USART1_RX
COMP2_INP/
PVD_IN
138
A4
94
60
A7
BOOT0
I
B
BOOT0
-
-
139
A3
95
61
D5
PB8
I/O
FT
PB8
TIM4_CH3/TIM10_CH1/
I2C1_SCL/
LCD_SEG16
-
140
B3
96
62
C6
PB9
I/O
FT
PB9
TIM4_CH4/
TIM11_CH1/I2C1_SDA/
LCD_COM3
-
141
C3
97
-
B7
PE0
I/O
FT
PE0
TIM4_ETR/TIM10_CH1/
LCD_SEG36
-
142
A2
98
-
A8
PE1
I/O
FT
PE1
TIM11_CH1/LCD_SEG37
-
143
D3
99
63
C7
VSS_3
S
-
VSS_3
-
-
144
C4
100 64
B8,
A9
VDD_3
S
-
VDD_3
-
-
1. I = input, O = output, S = supply.
2. Function availability depends on the chosen device.
3. Applicable to STM32L152xE devices only. In STM32L151xE devices, this pin should be connected to VDD.
4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section
in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).
DS10002 Rev 10
45/136
56
Pin descriptions
STM32L151xE STM32L152xE
5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off). The HSE has priority over the GPIO
function.
46/136
DS10002 Rev 10
Table 9. Alternate function input/output
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
LCD
-
CPRI
SYSTEM
EVENT
OUT
DS10002 Rev 10
BOOT0
BOOT0
-
-
-
-
-
-
-
-
-
-
-
-
NRST
NRST
-
-
-
-
-
-
-
-
-
-
-
-
-
- TIMx_IC1
EVENT
OUT
-
-
TIM2_CH1_
ETR
TIM5_CH1
-
-
-
-
USART2_CTS
-
-
PA1
-
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_RTS
-
- SEG0
-
TIMx_IC2
EVENT
OUT
PA2
-
TIM2_CH3
TIM5_CH3
TIM9_CH1
-
-
-
USART2_TX
-
- SEG1
- TIMx_IC3
EVENT
OUT
PA3
-
TIM2_CH4
TIM5_CH4
TIM9_CH2
-
-
-
USART2_RX
-
- SEG2
- TIMx_IC4
EVENT
OUT
PA4
-
-
-
-
-
SPI1_NSS
USART2_CK
-
-
-
- TIMx_IC1
EVENT
OUT
PA5
-
TIM2_CH1_
ETR
-
-
-
SPI1_SCK
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
PA6
-
-
TIM3_CH1
TIM10_CH1
-
SPI1_MISO
-
-
-
- SEG3
- TIMx_IC3
EVENT
OUT
PA7
-
-
TIM3_CH2
TIM11_CH1
-
SPI1_MOSI
-
-
-
- SEG4
- TIMx_IC4
EVENT
OUT
-
-
-
-
-
-
USART1_CK
-
- COM0
- TIMx_IC1
EVENT
OUT
PA8
MCO
47/136
PA9
-
-
-
-
-
-
-
USART1_TX
-
- COM1
- TIMx_IC2
EVENT
OUT
PA10
-
-
-
-
-
-
-
USART1_RX
-
- COM2
- TIMx_IC3
EVENT
OUT
Pin descriptions
PA0-WKUP1
SPI3_NSS
I2S3_WS
STM32L151xE STM32L152xE
Alternate functions
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
PA11
-
-
-
-
-
SPI1_MISO
-
USART1_CTS
-
-
-
- TIMx_IC4
EVENT
OUT
PA12
-
-
-
-
-
SPI1_MOSI
-
USART1_RTS
-
-
-
- TIMx_IC1
EVENT
OUT
LCD
-
CPRI
SYSTEM
DS10002 Rev 10
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
- TIMx_IC3
EVEN
TOUT
PA15
JTDI
TIM2_CH1_
ETR
-
-
-
SPI1_NSS
-
-
- SEG17
- TIMx_IC4
EVEN
TOUT
SPI3_NSS
I2S3_WS
-
-
TIM3_CH3
-
-
-
-
-
-
- SEG5
-
-
EVEN
TOUT
PB1
-
-
TIM3_CH4
-
-
-
-
-
-
- SEG6
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
SPI1_SCK
-
-
- SEG7
-
-
EVENT
OUT
-
TIM3_CH1
-
-
SPI1_MISO SPI3_MISO
-
-
- SEG8
-
-
EVENT
OUT
SPI1_MOSI
SPI3_MOSI
I2S3_SD
-
-
- SEG9
-
-
EVENT
OUT
-
EVENT
OUT
BOOT1
PB3
JTDO
PB4
NJTRST
TIM2_CH2
SPI3_SCK
I2S3_CK
PB5
-
-
TIM3_CH2
-
I2C1_
SMBA
PB6
-
-
TIM4_CH1
-
I2C1_SCL
-
-
USART1_TX
-
-
-
-
PB7
-
-
TIM4_CH2
-
I2C1_SDA
-
-
USART1_RX
-
-
-
-
PB8
-
-
TIM4_CH3
TIM10_CH1
I2C1_SCL
-
-
-
- SEG16
-
-
EVENT
OUT
-
EVENT
OUT
STM32L151xE STM32L152xE
PB0
PB2
Pin descriptions
48/136
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PB9
-
-
TIM4_CH4
TIM11_CH1
I2C1_SDA
-
-
PB10
-
TIM2_CH3
-
-
I2C2_SCL
-
-
PB11
-
TIM2_CH4
-
-
I2C2_SDA
-
PB12
-
-
-
TIM10_CH1
I2C2_SM
BA
PB13
-
-
-
TIM9_CH1
PB14
-
-
-
PB15
-
-
PC0
-
PC1
USART1/2/ UART4/
3
5
LCD
-
CPRI
SYSTEM
- COM3
-
-
EVENT
OUT
USART3_TX
-
- SEG10
-
-
EVENT
OUT
-
USART3_RX
-
- SEG11
-
-
EVENT
OUT
SPI2_NSS
I2S2_WS
-
USART3_CK
-
- SEG12
-
-
EVENT
OUT
-
SPI2_SCK
I2S2_CK
-
USART3_CTS
-
- SEG13
-
-
EVENT
OUT
TIM9_CH2
-
SPI2_MISO
-
USART3_RTS
-
- SEG14
-
-
EVENT
OUT
-
TIM11_CH1
-
SPI2_MOSI
I2S2_SD
-
-
-
- SEG15
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
- SEG18
- TIMx_IC1
EVENT
OUT
-
-
-
-
-
-
-
-
-
- SEG19
- TIMx_IC2
EVENT
OUT
PC2
-
-
-
-
-
-
-
-
-
- SEG20
- TIMx_IC3
EVENT
OUT
PC3
-
-
-
-
-
-
-
-
-
- SEG21
- TIMx_IC4
EVENT
OUT
PC4
-
-
-
-
-
-
-
-
-
- SEG22
- TIMx_IC1
EVENT
OUT
PC5
-
-
-
-
-
-
-
-
-
- SEG23
- TIMx_IC2
EVENT
OUT
PC6
-
-
TIM3_CH1
-
-
I2S2_MCK
-
-
-
- SEG24
- TIMx_IC3
EVENT
OUT
Pin descriptions
49/136
-
-
STM32L151xE STM32L152xE
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
PC7
-
-
TIM3_CH2
-
-
-
PC8
-
-
TIM3_CH3
-
-
-
PC9
-
-
TIM3_CH4
-
-
-
PC10
-
-
-
-
-
-
SPI3_SCK
I2S3_CK
PC11
-
-
-
-
-
-
PC12
-
-
-
-
-
PC13-WKUP2
-
-
-
-
PC14
OSC32_IN
-
-
-
PC15
OSC32_OUT
-
-
-
PD0
-
-
-
PD1
-
-
-
PD2
-
-
PD3
-
-
SPI3
USART1/2/ UART4/
3
5
LCD
-
CPRI
SYSTEM
-
-
- SEG25
- TIMx_IC4
EVENT
OUT
-
-
-
- SEG26
- TIMx_IC1
EVENT
OUT
-
-
-
- SEG27
- TIMx_IC2
EVENT
OUT
USART3_TX
UART4_TX
COM4/
- SEG28/
SEG40
- TIMx_IC3
EVENT
OUT
SPI3_MISO
USART3_RX
COM5/
UART4_RX - SEG29
/SEG41
- TIMx_IC4
EVENT
OUT
-
SPI3_MOSI
I2S3_SD
USART3_CK
UART5_TX
COM6/
- SEG30/
SEG42
- TIMx_IC1
EVENT
OUT
-
-
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
-
-
-
-
-
-
-
-
- TIMx_IC3
EVENT
OUT
-
-
-
-
-
-
-
-
- TIMx_IC4
EVENT
OUT
-
SPI2_NSS
I2S2_WS
-
-
-
-
-
- TIMx_IC1
EVENT
OUT
-
-
SPI2 SCK
I2S2_CK
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
TIM3_ETR
-
-
-
-
-
- TIMx_IC3
EVENT
OUT
-
-
-
SPI2_MISO
-
USART2_CTS
- TIMx_IC4
EVENT
OUT
TIM9_CH1
I2S3_MCK
COM7/
UART5_RX - SEG31/
SEG43
-
-
-
STM32L151xE STM32L152xE
SYSTEM
Pin descriptions
50/136
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PD4
-
-
-
-
-
SPI2_MOSI
I2S2_SD
-
USART2_RTS
-
-
-
- TIMx_IC1
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2_TX
-
-
-
- TIMx_IC2
EVENT
OUT
PD6
-
-
-
-
-
-
-
USART2_RX
-
-
-
- TIMx_IC3
EVENT
OUT
PD7
-
-
-
-
-
-
USART2_CK
-
-
-
- TIMx_IC4
EVENT
OUT
PD8
-
-
-
-
-
-
-
USART3_TX
-
- SEG28
- TIMx_IC1
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_RX
-
- SEG29
- TIMx_IC2
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_CK
-
- SEG30
- TIMx_IC3
EVENT
OUT
PD11
-
-
-
-
-
-
-
USART3_CTS
-
- SEG31
- TIMx_IC4
EVENT
OUT
PD12
-
-
TIM4_CH1
-
-
-
-
USART3_RTS
-
- SEG32
- TIMx_IC1
EVENT
OUT
PD13
-
-
TIM4_CH2
-
-
-
-
-
-
- SEG33
- TIMx_IC2
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
-
- SEG34
- TIMx_IC3
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
-
-
-
- SEG35
- TIMx_IC4
EVENT
OUT
PE0
-
-
TIM4_ETR
TIM10_CH1
-
-
-
-
-
- SEG36
- TIMx_IC1
EVENT
OUT
PE1
-
-
-
TIM11_CH1
-
-
-
-
-
- SEG37
- TIMx_IC2
EVENT
OUT
TIM9_CH2
USART1/2/ UART4/
3
5
LCD
-
CPRI
SYSTEM
Pin descriptions
51/136
SYSTEM
STM32L151xE STM32L152xE
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
LCD
-
CPRI
Pin descriptions
52/136
Table 9. Alternate function input/output (continued)
SYSTEM
DS10002 Rev 10
PE2
TRACECK
-
TIM3_ETR
-
-
-
-
-
-
- SEG 38
- TIMx_IC3
EVENT
OUT
PE3
TRACED0
-
TIM3_CH1
-
-
-
-
-
-
- SEG 39
- TIMx_IC4
EVENT
OUT
PE4
TRACED1
-
TIM3_CH2
-
-
-
-
-
-
-
-
- TIMx_IC1
EVENT
OUT
PE5
TRACED2
-
-
TIM9_CH1
-
-
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
PE6WKUP3
TRACED3
-
-
TIM9_CH2
-
-
-
-
-
-
-
- TIMx_IC3
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
- TIMx_IC4
EVENT
OUT
PE8
-
-
-
-
-
-
-
-
-
-
-
- TIMx_IC1
EVENT
OUT
PE9
-
TIM2_CH1_
ETR
-
-
-
-
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
PE10
-
TIM2_CH2
-
-
-
-
-
-
-
-
-
- TIMx_IC3
EVENT
OUT
PE11
-
TIM2_CH3
-
-
-
-
-
-
-
-
-
- TIMx_IC4
EVENT
OUT
PE12
-
TIM2_CH4
-
-
-
SPI1_NSS
-
-
-
-
-
- TIMx_IC1
EVENT
OUT
PE13
-
-
-
-
-
SPI1_SCK
-
-
-
-
-
- TIMx_IC2
EVENT
OUT
PE14
-
-
-
-
-
SPI1_MISO
-
-
-
-
-
- TIMx_IC3
EVENT
OUT
PE15
-
-
-
-
-
SPI1_MOSI
-
-
-
-
-
- TIMx_IC4
EVENT
OUT
STM32L151xE STM32L152xE
PE7
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
PF0
-
-
-
-
-
-
-
-
-
PF1
-
-
-
-
-
-
-
-
PF2
-
-
-
-
-
-
-
PF3
-
-
-
-
-
-
PF4
-
-
-
-
-
PF5
-
-
-
-
PF6
-
-
TIM5_ETR
PF7
-
-
PF8
-
PF9
-
CPRI
SYSTEM
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
TIM5_CH2
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
TIM5_CH3
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
TIM5_CH4
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF10
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF11
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF13
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Pin descriptions
53/136
LCD
STM32L151xE STM32L152xE
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
PF14
-
-
-
-
-
-
-
-
-
PF15
-
-
-
-
-
-
-
-
PG0
-
-
-
-
-
-
-
PG1
-
-
-
-
-
-
PG2
-
-
-
-
-
PG3
-
-
-
-
PG4
-
-
-
PG5
-
-
PG6
-
PG7
LCD
-
CPRI
SYSTEM
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG8
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG9
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG10
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG11
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
STM32L151xE STM32L152xE
SYSTEM
Pin descriptions
54/136
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO8
.
.
AFIO11
AFIO14
.
.
AFIO15
Port name
Alternate function
DS10002 Rev 10
SYSTEM
TIM2
TIM3/4/
5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/ UART4/
3
5
PG12
-
-
-
-
-
-
-
-
-
PG13
-
-
-
-
-
-
-
-
PG14
-
-
-
-
-
-
-
PG15
-
-
-
-
-
-
PH0OSC_IN
-
-
-
-
-
PH1OSC_OUT
-
-
-
-
PH2
-
-
-
-
LCD
-
CPRI
SYSTEM
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STM32L151xE STM32L152xE
Table 9. Alternate function input/output (continued)
Pin descriptions
55/136
Memory mapping
5
STM32L151xE STM32L152xE
Memory mapping
Figure 8. Memory map
APB memory space
0x4002 67FF
0x4002 6400
0x4002 6000
0x4002 4000
0x4002 3C00
0x4002 3800
0xFFFF FFFF
0x4002 3400
0x4002 3000
7
0xE010 0000
0xE000 0000
0x4002 2000
0x4002 1C00
Cortex-M3 Internal
Peripherals
0x4002 1800
0x4002 1400
0x4002 1000
0x4002 0C00
0x4002 0800
0x4002 0400
0x4002 0000
6
0xC000 0000
0x4001 3C00
0x4001 3800
5
0x4001 3400
0x4001 3000
0xA000 0000
0x4001 2C00
DMA2
DMA1
reserved
Flash Interface
RCC
reserved
CRC
reserved
Port G
Port F
Port H
Port E
Port D
Port C
Port B
Port A
reserved
USART1
reserved
SPI1
reserved
0x4001 2800
0x4001 2400
4
0x4001 1400
0x4001 1000
0x8000 0000
0x1FF8 009F
0x1FF8 0080
3
0x1FF8 0020
0x1FF8 0000
Option Bytes
Bank 2
reserved
Option Bytes
Bank 1
0x6000 0000
reserved
0x4000 0000
0x1FF0 1000
Peripherals
0x1FF0 0000
0
0x4001 0000
0x4000 8000
0x4000 7800
0x4000 7400
System memory
Bank 1
0x4000 7000
0x4000 6400
0x4000 6000
0x4000 5C00
reserved
0x4000 5800
0x4000 5400
SRAM
0x0808 4000
Nonvolatile
memory
0x0000 0000
0x4000 5000
Data EEPROM
Bank 2
0x0808 2000
Data EEPROM
Bank 1
0x0808 0000
Reserved
0x0800 0000
0x0000 0000
0x4000 4C00
0x4000 4800
0x4000 4400
0x4000 4000
0x4000 3C00
0x0804 0000
56/136
0x4001 0400
System
memory
reserved
Bank 2
1
0x2000 0000
0x4001 0800
0x4001 7C00
0x1FF0 2000
2
0x4001 0C00
Flash memory
Bank 2
0x4000 3800
0x4000 3400
Flash memory
Bank 1
0x4000 3000
Aliased to Flash or system
memory depending on
BOOT pins
DS10002 Rev 10
0x4000 2C00
0x4000 2800
0x4000 2400
0x4000 1C00
0x4000 1400
0x4000 1000
0x4000 0C00
0x4000 0800
0x4000 0400
0x4000 0000
ADC
reserved
TIM11
TIM10
TIM9
EXTI
SYSCFG
reserved
COMP + RI
reserved
DAC1 & 2
PWR
reserved
512 byte USB
USB Registers
I2C2
I2C1
UART5
UART4
USART3
USART2
reserved
SPI3
SPI2
reserved
IWDG
WWDG
RTC
LCD
reserved
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
MS33003V4
STM32L151xE STM32L152xE
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean ±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
ai17851c
ai17852d
DS10002 Rev 10
57/136
114
Electrical characteristics
6.1.6
STM32L151xE STM32L152xE
Power supply scheme
Figure 11. Power supply scheme
OUT
GP I/Os
IN
VDD
VDD
Level shifter
Standby-power circuitry
(LSE,RTC,Wake-up
logic, RTC backup
registers)
IO
Logic
Kernel logic
(CPU,
Digital &
Memories)
Regulator
N × 100 nF +
1 × 4.7 μF
VSS
VDDA
VDDA
VREF
100 nF
+ 1 μF
100 nF
+ 1 μF
VREF+
VREF-
ADC/
DAC
Analog:
OSC,PLL,COMP,
….
VSSA
N – number of
VDD/VSS pairs
58/136
MS32461V3
DS10002 Rev 10
STM32L151xE STM32L152xE
6.1.7
Electrical characteristics
Optional LCD power supply scheme
Figure 12. Optional LCD power supply scheme
VSEL
VDD
N x 100 nF
+ 1 x 10 μF
Option 1
VDD1/2/.../N
Step-up
Converter
VLCD
100 nF
LCD
VLCD
Option 2
CEXT
VSS1/2/.../N
MS32462V2
1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
6.1.8
Current consumption measurement
Figure 13. Current consumption measurement scheme
A
+
-
N x 100 nF
+1 x 10 μF
N x VDD
N x VSS
VLCD
VDDA
100 nF
+1 μF
VREF+
VREFVSSA
MS33028V1
DS10002 Rev 10
59/136
114
Electrical characteristics
6.2
STM32L151xE STM32L152xE
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,
Table 11: Current characteristics, and Table 12: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 10. Voltage characteristics
Symbol
VDD–VSS
VIN(2)
|ΔVDDx|
Ratings
Min
Max
–0.3
4.0
Input voltage on five-volt tolerant pin
VSS − 0.3
VDD+4.0
Input voltage on any other pin
VSS − 0.3
4.0
-
50
-
50
External main supply voltage
(including VDDA and VDD)(1)
Variations between different VDD power pins
pins(3)
Unit
V
mV
|VSSX − VSS|
Variations between all different ground
VREF+ –VDDA
Allowed voltage difference for VREF+ > VDDA
-
0.4
V
Electrostatic discharge voltage
(human body model)
see Section 6.3.11
-
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. VIN maximum must always be respected. Refer to Table 11 for maximum allowed injected current values.
3. Include VREF- pin.
Table 11. Current characteristics
Symbol
IVDD(Σ)
IVSS(Σ)
(2)
Ratings
Max.
Total current into sum of all VDD_x power lines (source)(1)
100
(sink)(1)
100
Total current out of sum of all VSS_x ground lines
IVDD(PIN)
Maximum current into each VDD_x power pin (source)(1)
70
IVSS(PIN)
(sink)(1)
-70
IIO
ΣIIO(PIN)
IINJ(PIN) (3)
ΣIINJ(PIN)
Maximum current out of each VSS_x ground pin
Output current sunk by any I/O and control pin
25
Output current sourced by any I/O and control pin
- 25
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins
Injected current on five-volt tolerant
Injected current on any other pin
I/O(4),
Unit
mA
60
(2)
RST and B pins
(5)
Total injected current (sum of all I/O and control pins)(6)
-60
-5/+0
±5
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.
60/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 12. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Value
Unit
–65 to +150
°C
150
°C
Table 13. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled, at
power on
1.8
3.6
BOR detector disabled, after
power on
1.65
3.6
1.65
3.6
1.8
3.6
FT pins; 2.0 V ≤ VDD
-0.3
5.5(3)
FT pins; VDD < 2.0 V
-0.3
5.25(3)
0
5.5
-0.3
VDD+0.3
UFBGA132 package
-
333
LQFP144 package
-
500
LQFP100 package
-
465
LQFP64 package
-
435
WLCSP104 package
-
435
–40
85
–40
105
VDD
VDDA(1)
VIN
Standard operating voltage
Analog operating voltage
(ADC and DAC not used)
Analog operating voltage
(ADC or DAC used)
I/O input voltage
Must be the same voltage as
VDD(2)
BOOT0 pin
Any other pin
PD
TA
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
Ambient temperature for 6 suffix version Maximum power
dissipation(5)
Ambient temperature for 7 suffix version Maximum power dissipation
DS10002 Rev 10
Unit
MHz
V
V
V
mW
°C
61/136
114
Electrical characteristics
STM32L151xE STM32L152xE
Table 13. General operating conditions (continued)
Symbol
TJ
Parameter
Junction temperature range
Conditions
Min
Max
6 suffix version
–40
105
7 suffix version
–40
110
Unit
°C
1. When the ADC is used, refer to Table 55: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up .
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 71: Thermal characteristics
on page 130).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 71: Thermal characteristics on page 130).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
conditions summarized in Table 13.
Table 14. Embedded reset and power control block characteristics
Symbol
Parameter
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1)
Reset temporization
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
62/136
Conditions
Min
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
VDD rising, BOR disabled(2)
DS10002 Rev 10
Unit
µs/V
ms
V
STM32L151xE STM32L152xE
Electrical characteristics
Table 14. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst
Hysteresis voltage
Min
Typ
Max
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD
thresholds excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. See option “D” in Ordering information scheme for more details.
DS10002 Rev 10
63/136
114
Electrical characteristics
6.3.3
STM32L151xE STM32L152xE
Embedded internal reference voltage
The parameters given in Table 16 are based on characterization results, unless otherwise
specified.
Table 15. Embedded internal reference voltage calibration values
Calibration value name
Description
Raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
VREFINT_CAL
Memory address
0x1FF8 00F8 - 0x1FF8 00F9
Table 16. Embedded internal reference voltage
Symbol
VREFINT out
Parameter
(1)
Conditions
Min
Typ
Unit
1.242
V
Internal reference voltage
– 40 °C < TJ < +110 °C
Internal reference current
consumption
-
-
1.4
2.3
µA
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Including uncertainties
Accuracy of factory-measured VREF
due to ADC and
(2)
value
VDDA/VREF+ values
-
-
±5
mV
TCoeff(3)
Temperature coefficient
–40 °C < TJ < +110 °C
-
25
100
ppm/°C
ACoeff(3)
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
VDDCoeff(3)
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
TS_vrefint(3)
ADC sampling time when reading
the internal reference voltage
-
4
-
-
µs
TADC_BUF(3)
Startup time of reference voltage
buffer for ADC
-
-
-
10
µs
IBUF_ADC(3)
Consumption of reference voltage
buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(3)
VREF_OUT output current (4)
-
-
-
1
µA
CVREF_OUT(3)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference voltage
buffer for VREF_OUT and COMP
-
-
730
1200
nA
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
IREFINT
ILPBUF(3)
1.202 1.224
Max
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results.
4. To guarantee less than 1% VREF_OUT deviation.
64/136
DS10002 Rev 10
%
VREFINT
STM32L151xE STM32L152xE
6.3.4
Electrical characteristics
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature TA = 25 °C and VDD supply voltage conditions summarized in
Table 13: General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAHB.
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 26: High-speed external user clock characteristics.
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins.
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise.
DS10002 Rev 10
65/136
114
Electrical characteristics
STM32L151xE STM32L152xE
Table 17. Current consumption in Run mode, code with data processing running from
Flash
Symbol Parameter
fHCLK
Typ
Max(1)
1 MHz
225
500
2 MHz
420
750
4 MHz
780
1200
4 MHz
0.98
1.6
8 MHz
1.85
2.9
16 MHz
3.6
5.2
8 MHz
2.2
3.5
16 MHz
4.4
6.5
32 MHz
8.6
12
Range 2, VCORE=1.5
V VOS[1:0] = 10
16 MHz
3.6
5.2
Range 1, VCORE=1.8
V VOS[1:0] = 01
32 MHz
8.7
12.3
65 kHz
42
145
524 kHz
135
250
4.2 MHz
820
1200
Conditions
Range 3, VCORE=1.2
V VOS[1:0] = 11
IDD
(Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK up to
16 MHz included,
Range 2, VCORE=1.5
fHSE = fHCLK/2
V VOS[1:0] = 10
above 16 MHz (PLL
(2)
ON)
Range 1, VCORE=1.8
V VOS[1:0] = 01
HSI clock source
(16 MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
Range 3, VCORE=1.2
V VOS[1:0] = 11
MSI clock, 4.2 MHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
66/136
DS10002 Rev 10
Unit
µA
mA
µA
STM32L151xE STM32L152xE
Electrical characteristics
Table 18. Current consumption in Run mode, code with data processing running from
RAM
Symbol
Parameter
Conditions
Typ
1 MHz
200
470
2 MHz
360
780
4 MHz
685
1200
4 MHz
0.80
1.5
8 MHz
1.6
3
16 MHz
3.1
5
8 MHz
1.9
3.5
16 MHz
3.7
5.55
32 MHz
7.55
10.9
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
3.15
4.8
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
7.75
11.7
65 kHz
40
130
524 kHz
115
215
4.2 MHz
715
1100
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
IDD
(Run
from
RAM)
Supply current
in Run mode,
code executed
from RAM,
Flash switched
off
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
HSI clock source
(16 MHz)
Max(1) Unit
fHCLK
MSI clock, 65 kHz
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
µA
mA
µA
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
DS10002 Rev 10
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Electrical characteristics
STM32L151xE STM32L152xE
Table 19. Current consumption in Sleep mode
Symbol
Parameter
Conditions
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
Range 2,
fHSE = fHCLK/2
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
ON)(2)
Supply current
in Sleep
mode, Flash
OFF
HSI clock source
(16 MHz)
Max(1)
1 MHz
51
220
2 MHz
81
300
4 MHz
140
380
4 MHz
175
500
8 MHz
330
700
16 MHz
625
1100
8 MHz
395
800
16 MHz
760
1250
32 MHz
1700
2700
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
670
1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1750
2700
65 kHz
19
92
524 kHz
33
110
4.2 MHz
150
273
1 MHz
63
250
2 MHz
93
300
4 MHz
155
380
4 MHz
190
500
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
Range 2,
fHSE = fHCLK/2
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
Supply current ON)(2)
in Sleep
Range 1,
mode, Flash
VCORE=1.8 V
ON
VOS[1:0] = 01
8 MHz
340
700
16 MHz
640
1120
8 MHz
410
800
16 MHz
770
1300
32 MHz
1750
2700
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
690
1160
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1750
2800
65 kHz
31
105
524 kHz
45
125
4.2 MHz
160
290
HSI clock source
(16 MHz)
Supply current MSI clock, 65 kHz
Range 3,
in Sleep
MSI clock, 524 kHz VCORE=1.2V
mode, Flash
VOS[1:0] = 11
ON
MSI clock, 4.2 MHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
68/136
Typ
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
MSI clock, 65 kHz
IDD (Sleep)
fHCLK
DS10002 Rev 10
Unit
µA
STM32L151xE STM32L152xE
Electrical characteristics
Table 20. Current consumption in Low-power run mode
Symbol
Parameter
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
IDD (LP
Run)
Typ
Max(1)
11
16
TA = 85 °C
36.2
40
TA = 105 °C
65.4
102
TA =-40 °C to 25 °C
16.5
23
TA = 85 °C
41.9
48
TA = 105 °C
72.1
108
30
45
TA = 55 °C
36.1
48
TA = 85 °C
55.7
66
TA = 105 °C
86.6
125
26
40.5
TA = 85 °C
53.2
67
TA = 105 °C
92.1
120
33
49
TA = 85 °C
60.2
75
TA = 105 °C
95.6
130
TA = -40 °C to 25 °C
48.5
71
TA = 55 °C
54.7
75
TA = 85 °C
76.1
95
TA = 105 °C
112
140
-
200
Conditions
Supply
current in
Low-power
run mode
MSI clock, 65 kHz
fHCLK = 32 kHz
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C
MSI clock, 131 kHz
fHCLK = 131 kHz
MSI clock, 65 kHz
fHCLK = 32 kHz
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
Max allowed
VDD from
IDD max current in
1.65 V to
(LP Run) Low-power
3.6 V
run mode
TA = -40 °C to 25 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C
TA = -40 °C to 25 °C
-
-
Unit
µA
1. Guaranteed by characterization results, unless otherwise specified.
DS10002 Rev 10
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Electrical characteristics
STM32L151xE STM32L152xE
Table 21. Current consumption in Low-power sleep mode
Symbol
Parameter
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
All peripherals
OFF, VDD from
1.65 V to 3.6 V
IDD
(LP Sleep)
Typ
Max(1)
TA = -40 °C to 25 °C
5.5
-
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
26.8
29
TA = 105 °C
37
47
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
27.2
29
TA = 105 °C
37.3
47
TA = -40 °C to 25 °C
21.5
25
23.7
26
29.8
32
TA = 105 °C
39.7
50
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
26.8
29
TA = 105 °C
38.3
47
TA = -40 °C to 25 °C
18.5
21
TA = 85 °C
27.2
29
TA = 105 °C
38.5
47
TA = -40 °C to 25 °C
21.5
25
23.7
26
29.8
32
41.2
50
-
200
Conditions
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
MSI clock, 131 kHz T = 55 °C
A
fHCLK = 131 kHz,
TA = 85 °C
Flash ON
Supply
current in
Low-power
sleep mode
MSI clock, 65 kHz
fHCLK = 32 kHz
TIM9 and
USART1
enabled, Flash
ON, VDD from
1.65 V to 3.6 V
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz TA = 55 °C
fHCLK = 131 kHz
TA = 85 °C
TA = 105 °C
IDD max
(LP Sleep)
Max
allowed
VDD from 1.65 V
current in
to 3.6 V
Low-power
sleep mode
-
1. Guaranteed by characterization results, unless otherwise specified.
70/136
DS10002 Rev 10
-
Unit
µA
STM32L151xE STM32L152xE
Electrical characteristics
Table 22. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
LCD
OFF
RTC clocked by LSI
or LSE external clock
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
Typ
TA = -40°C to 25°C
VDD = 1.8 V
1.18
-
TA = -40°C to 25°C
1.4
4
TA = 55°C
3.02
6
TA= 85°C
7.44
11
TA = 105°C
15.5
27
1.5
6
4.65
7
9.07
13
15.6
31
3.9
10
5.19
11
9.8
17
TA = 105°C
18.4
48
TA = -40°C to 25°C
1.65
-
TA = 55°C
3.32
-
TA= 85°C
7.83
-
16
-
1.75
-
4.9
-
9.41
-
15.8
-
4.1
-
5.53
-
10
-
TA = 105°C
18.5
-
TA = -40°C to 25°C
VDD = 1.8V
1.33
-
TA = -40°C to 25°C
VDD = 3.0V
1.62
-
TA = -40°C to 25°C
VDD = 3.6V
1.87
-
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
TA = -40°C to 25°C
LCD
TA = 55°C
ON (1/8
duty)(3) TA= 85°C
IDD (Stop
with RTC)
Supply current in
Stop mode with RTC
enabled
LCD
OFF
TA = 105°C
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
RTC clocked by LSE
external quartz
(32.768kHz),
regulator in LP mode,
TA = -40°C to 25°C
HSI and HSE OFF
LCD
TA = 55°C
(no independent
ON
(1/8
watchdog(4)
duty)(3) TA= 85°C
LCD
OFF
DS10002 Rev 10
Max(1) Unit
µA
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Electrical characteristics
STM32L151xE STM32L152xE
Table 22. Typical and maximum current consumptions in Stop mode (continued)
Symbol
Parameter
Conditions
Regulator in LP mode, HSI and
HSE OFF, independent
watchdog and LSI enabled
IDD (Stop)
Supply current in
Stop mode (RTC
disabled)
Typ
TA = -40°C to 25°C
1.8
2.2
TA = -40°C to 25°C
0.560
1.5
2.18
4
6.6
12
14.9
26
2
-
1.45
-
1.45
-
Regulator in LP mode, LSI, HSI T = 55°C
A
and HSE OFF (no independent
TA= 85°C
watchdog)
TA = 105°C
IDD
(WU from
Stop)
MSI = 4.2 MHz
Supply current during
wakeup from Stop
MSI = 1.05 MHz
mode
MSI = 65 kHz(5)
Max(1) Unit
TA = -40°C to 25°C
µA
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
72/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
Table 23. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
0.865
-
1.11
1.9
1.72
2.2
TA= 85 °C
2.12
4
TA = 105 °C
2.54
8.3(2)
TA = -40 °C to 25 °C
VDD = 1.8 V
0.97
-
TA = -40 °C to 25 °C
1.28
-
TA = 55 °C
2.01
-
TA= 85 °C
2.5
-
TA = 105 °C
2.98
-
1
1.7
0.29
1
0.96
1.3
1.38
3
1.98
7(2)
1
-
Conditions
TA = -40 °C to 25 °C
VDD = 1.8 V
T = -40 °C to 25 °C
RTC clocked by LSI (no A
independent watchdog) TA = 55 °C
IDD
(Standby
with RTC)
Supply current in
Standby mode with RTC
enabled
RTC clocked by LSE
external quartz (no
independent
watchdog)(3)
Independent watchdog
TA = -40 °C to 25 °C
and LSI enabled
IDD
(Standby)
Supply current in
Standby mode (RTC
disabled)
TA = -40 °C to 25 °C
Independent watchdog TA = 55 °C
and LSI OFF
TA = 85 °C
TA = 105 °C
IDD
(WU from
Standby)
Supply current during
wakeup time from
Standby mode
-
TA = -40 °C to 25 °C
Unit
µA
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
DS10002 Rev 10
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Electrical characteristics
STM32L151xE STM32L152xE
Table 24. Peripheral current consumption(1)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
APB1
74/136
Range 1,
Range 2,
Range 3,
VCORE=
VCORE=
VCORE=
Low-power
1.8 V
1.5 V
1.2 V
sleep and run
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
TIM2
12.0
10.0
8.0
10.0
TIM3
10.5
8.8
7.0
8.8
TIM4
10.4
8.8
7.0
8.8
TIM5
13.8
11.5
9.1
11.5
TIM6
3.9
3.0
2.5
3.0
TIM7
3.8
3.3
2.6
3.3
LCD
4.2
3.6
2.8
3.6
WWDG
2.9
2.5
2.1
2.5
SPI2
5.4
4.4
3.5
4.4
SPI3
5.5
4.6
3.7
4.6
USART2
7.6
6.2
4.9
6.2
USART3
7.6
6.2
5.0
6.2
USART4
7.3
6.1
4.8
6.1
USART5
7.6
6.3
5.0
6.3
I2C1
7.3
6.1
4.8
6.1
I2C2
7.2
5.9
4.7
5.9
USB
13.0
11.2
8.9
11.2
PWR
2.6
2.3
1.9
2.3
DAC
5.9
5.0
4.0
5.0
COMP
3.9
3.3
2.6
3.3
DS10002 Rev 10
Unit
µA/MHz
(fHCLK)
STM32L151xE STM32L152xE
Electrical characteristics
Table 24. Peripheral current consumption(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
APB2
AHB
Range 1,
Range 2,
Range 3,
VCORE=
VCORE=
VCORE=
Low-power
1.8 V
1.5 V
1.2 V
sleep and run
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
SYSCFG & RI
2.9
2.4
2.0
2.4
TIM9
8.2
6.9
5.5
6.9
TIM10
6.2
5.1
4.1
5.1
TIM11
6.2
5.1
4.1
5.1
ADC
9.5
7.9
6.2
7.9
SPI1
4.8
3.9
3.2
3.9
USART1
8.2
6.9
5.4
6.9
GPIOA
6.3
5.3
4.1
5.3
GPIOB
6.3
5.3
4.1
5.3
GPIOC
6.3
5.2
4.1
5.2
GPIOD
8.1
6.8
5.4
6.8
GPIOE
6.7
5.7
4.5
5.7
GPIOF
5.9
4.9
3.9
4.9
GPIOG
7.2
6.1
4.9
6.1
GPIOH
1.7
1.4
1.1
1.4
CRC
0.8
0.7
0.5
0.7
FLASH
21.6
18.1
16.0
- (3)
DMA1
16.8
14.5
11.5
14.5
DMA2
15.7
13.6
10.8
13.6
222
184
160
165.9
(2)
All enabled
IDD (RTC)
0.4
IDD (LCD)
3.1
IDD (ADC)(4)
1450
IDD (DAC)(5)
340
IDD (COMP1)
0.16
IDD (COMP2)
Slow mode
2
Fast mode
5
IDD (PVD / BOR)(6)
2.6
IDD (IWDG)
0.25
Unit
µA/MHz
(fHCLK)
µA
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the
following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Lowpower run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in
both cases. No I/O pins toggling.
2. HSI oscillator is OFF for this measure.
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI
consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under the conditions summarized in Table 13.
Table 25. Low-power mode wakeup timings
Symbol
tWUSLEEP
tWUSLEEP_LP
Parameter
Wakeup from Sleep mode
tWUSTDBY
Max(1) Unit
0.4
-
fHCLK = 262 kHz
Flash enabled
46
-
fHCLK = 262 kHz
Flash switched OFF
46
-
fHCLK = fMSI = 4.2 MHz
8.2
-
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
7.7
8.9
fHCLK = fMSI = 4.2 MHz
Voltage range 3
8.2
13.1
fHCLK = fMSI = 2.1 MHz
10.2
13.4
fHCLK = fMSI = 1.05 MHz
16
20
fHCLK = fMSI = 524 kHz
31
37
fHCLK = fMSI = 262 kHz
57
66
fHCLK = fMSI = 131 kHz
112
123
fHCLK = MSI = 65 kHz
221
236
Wakeup from Standby mode
ULP bit = 1 and FWU bit = 1
fHCLK = MSI = 2.1 MHz
58
104
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
2.6
3.25
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
Wakeup from Stop mode,
regulator in low-power mode
ULP bit = 1 and FWU bit = 1
1. Guaranteed by characterization, unless otherwise specified
76/136
Typ
fHCLK = 32 MHz
Wakeup from Stop mode,
regulator in Run mode
ULP bit = 1 and FWU bit = 1
tWUSTOP
Conditions
DS10002 Rev 10
µs
ms
STM32L151xE STM32L152xE
6.3.6
Electrical characteristics
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 14.
Table 26. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min
Typ
Max
Unit
CSS is on or
PLL is used
1
8
32
MHz
CSS is off, PLL
not used
0
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
12
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance
-
2.6
-
Cin(HSE)
-
V
ns
pF
1. Guaranteed by design.
Figure 14. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tw(HSEL)
t
THSE
MS19214V2
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under the conditions summarized in Table 13.
Table 27. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
CIN(LSE)
Min
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
OSC32_IN input capacitance
-
-
-
10
-
0.6
-
pF
1. Guaranteed by design.
Figure 15. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
t
tw(LSEL)
TLSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 28. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
78/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
Table 28. HSE oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Min Typ
Max
Unit
Oscillator frequency
-
1
-
24
MHz
RF
Feedback resistor
-
-
200
-
kΩ
C
Recommended load
capacitance versus
equivalent serial
resistance of the crystal
(RS)(3)
RS = 30 Ω
-
20
-
pF
VDD= 3.3 V,
VIN = VSS with 30 pF
load
-
-
3
mA
C = 20 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.7 (stabilized)
C = 10 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.46 (stabilized)
Startup
3.5
-
-
mA /V
VDD is stabilized
-
1
-
ms
IHSE
IDD(HSE)
gm
tSU(HSE)(4)
HSE driving current
HSE oscillator power
consumption
Oscillator
transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
Figure 16. HSE oscillator circuit diagram
fHSE to core
Rm
RF
CO
Lm
CL1
OSC_IN
Cm
gm
Resonator
Consumption
control
Resonator
STM32
OSC_OUT
CL2
ai18235b
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 29. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE
Low speed external oscillator
frequency
-
-
32.768
-
kHz
RF
Feedback resistor
-
-
1.2
-
MΩ
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 kΩ
-
8
-
pF
ILSE
LSE driving current
VDD = 3.3 V, VIN = VSS
-
-
1.1
µA
VDD = 1.8 V
-
450
-
VDD = 3.0 V
-
600
-
VDD = 3.6V
-
750
-
-
3
-
-
µA/V
VDD is stabilized
-
1
-
s
IDD (LSE)
Oscillator transconductance
gm
tSU(LSE)
LSE oscillator current
consumption
(4)
Startup time
nA
1. Guaranteed by characterization results.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
4.
80/136
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 17).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and
Cstray = 2 pF, then CL1 = CL2 = 8 pF.
Figure 17. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 kHz
resonator
RF
OSC32_OUT
Bias
controlled
gain
STM32L1xx
CL2
ai17853b
DS10002 Rev 10
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114
Electrical characteristics
6.3.7
STM32L151xE STM32L152xE
Internal clock source characteristics
The parameters given in Table 30 are derived from tests performed under the conditions
summarized in Table 13.
High-speed internal (HSI) RC oscillator
Table 30. HSI oscillator characteristics
Symbol
fHSI
TRIM
(1)(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI user-trimmed
resolution
Trimming code is not a multiple of 16
-
± 0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
ACCHSI(2) factory-calibrated
HSI oscillator
-
± 1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C
-4
-
3
%
tSU(HSI)(2)
HSI oscillator
startup time
-
-
3.7
6
µs
IDD(HSI)(2)
HSI oscillator
power consumption
-
-
100
140
µA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
Low-speed internal (LSI) RC oscillator
Table 31. LSI oscillator characteristics
Symbol
fLSI(1)
DLSI(2)
tsu(LSI)(3)
IDD(LSI)
(3)
Parameter
Min
Typ
Max
Unit
LSI frequency
26
38
56
kHz
LSI oscillator frequency drift
0°C ≤ TA ≤ 105°C
-10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
82/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
Multi-speed internal (MSI) RC oscillator
Table 32. MSI oscillator characteristics
Symbol
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0 °C ≤ TA ≤ 105 °C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
fMSI
ACCMSI
IDD(MSI)(2)
tSU(MSI)
Parameter
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI oscillator power consumption
MSI oscillator startup time
DS10002 Rev 10
Max Unit
kHz
MHz
µA
µs
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Electrical characteristics
STM32L151xE STM32L152xE
Table 32. MSI oscillator characteristics (continued)
Symbol
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
84/136
DS10002 Rev 10
Max Unit
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
Typ
µs
MHz
6
STM32L151xE STM32L152xE
6.3.8
Electrical characteristics
PLL characteristics
The parameters given in Table 33 are derived from tests performed under the conditions
summarized in Table 13.
Table 33. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
PLL lock time
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
µA
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 34. RAM and hardware registers
Symbol
VRM
Parameter
Data retention mode(1)
Conditions
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
Flash memory and data EEPROM
Table 35. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
600
-
µA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming/ erasing
time for byte / word /
double word / half-page
IDD
ms
1. Guaranteed by design.
Table 36. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC(2)
Parameter
Cycling (erase / write)
Program memory
TA = -40°C to
105 °C
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
tRET(2)
Conditions
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
-
-
300
-
-
30
-
-
30
-
-
10
-
-
10
-
-
kcycles
years
TRET = +105 °C
2. Characterization is done according to JEDEC JESD22-A117.
DS10002 Rev 10
10
Unit
TRET = +85 °C
1. Guaranteed by characterization results.
86/136
Min(1) Typ Max
STM32L151xE STM32L152xE
6.3.10
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 37. They are based on the EMS levels and classes
defined in application note AN1709.
Table 37. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, LQFP144, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
4B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It must be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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114
Electrical characteristics
STM32L151xE STM32L152xE
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 38. EMI characteristics
Max vs. frequency range
Symbol Parameter
SEMI
6.3.11
Conditions
VDD = 3.6 V,
TA = 25 °C,
Peak level LQFP144 package
compliant with IEC
61967-2
Monitored
frequency band
4 MHz
16 MHz 32 MHz
voltage voltage voltage
range 3 range 2 range 1
0.1 to 30 MHz
-14
-6
-4
30 to 130 MHz
-11
0
9
130 MHz to 1GHz
-7
-1
9
SAE EMI Level
1
2
2.5
Unit
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.
Table 39. ESD absolute maximum ratings
Symbol
Ratings
Electrostatic
VESD(HBM) discharge voltage
(human body model)
Conditions
TA = +25 °C, conforming
to JESD22-A114
Electrostatic
TA = +25 °C, conforming
VESD(CDM) discharge voltage
to ANSI/ESD STM5.3.1.
(charge device model)
1. Guaranteed by characterization results.
88/136
Class
DS10002 Rev 10
LQFP144
and
WLCSP104
packages
packages
except
LQFP144
and
WLCSP104
Maximum
Unit
value(1)
2
2000
C3
250
V
V
C4
500
STM32L151xE STM32L152xE
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 40. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) must be avoided during normal product operation. However,
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 41.
Table 41. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Injected current on all 5 V tolerant (FT) pins
IINJ
Injected current on BOOT0
Injected current on any other pin
Negative
injection
Positive
injection
-5 (1)
NA(2)
-0
NA(2)
-5
(1)
Unit
mA
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
2. Injection is not possible.
DS10002 Rev 10
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114
Electrical characteristics
6.3.13
STM32L151xE STM32L152xE
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.
Table 42. I/O static characteristics
Symbol
VIL
VIH
Parameter
Conditions
Input low level voltage
Input high level voltage
Ilkg
I/O Schmitt trigger voltage
hysteresis(2)
Input leakage current
(4)
Typ
Max
Unit
VDD(1)(2)
TC and FT I/O
-
-
0.3
BOOT0
-
-
0.14 VDD(2)
TC I/O
0.45 VDD+0.38(2)
-
-
FT I/O
0.39
VDD+0.59(2)
-
-
0.15
VDD+0.56(2)
-
-
BOOT0
Vhys
Min
V
TC and FT I/O
-
10% VDD(3)
-
BOOT0
-
0.01
-
VSS ≤ VIN ≤ VDD
I/Os with LCD
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches and LCD
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with USB
-
-
±250
VSS ≤ VIN ≤ VDD
TC and FT I/Os
-
-
±50
FT I/O
VDD ≤ VIN ≤ 5V
-
-
±10
µA
nA
RPU
Weak pull-up equivalent
resistor(5)(1)
VIN = VSS
25
45
65
kΩ
RPD
Weak pull-down equivalent
resistor(5)
VIN = VDD
25
45
65
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by test in production.
2. Guaranteed by design.
3. With a minimum of 200 mV.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
90/136
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 43.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 11).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 11).
Output voltage levels
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.
Table 43. Output voltage characteristics
Symbol
VOL(1)(2)
Parameter
Output low level voltage for an I/O pin
VOH
(2)(3)
Output high level voltage for an I/O pin
VOL
(3)(4)
Output low level voltage for an I/O pin
VOH (3)(4) Output high level voltage for an I/O pin
VOL(1)(4)
VOH
(3)(4)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Conditions
Min
Max
IIO = 8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD-0.4
-
IIO = 4 mA
1.65 V < VDD < 3.6 V V -0.45
DD
IIO = 20 mA
2.7 V < VDD < 3.6 V
Unit
0.45
V
-
-
1.3
VDD-1.3
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 11
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Guaranteed by test in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Guaranteed by characterization results.
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Table 44, respectively.
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 13.
Table 44. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
-
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
Conditions
fmax(IO)out
tf(IO)out
tr(IO)out
Min
Parameter
tf(IO)out
tr(IO)out
Output rise and fall time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-
Unit
kHz
ns
MHz
ns
MHz
ns
MHz
ns
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 18.
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Electrical characteristics
Figure 18. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON 50pF
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131c
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 45)
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 13.
Table 45. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL(NRST)(1)
NRST input low level
voltage
-
-
-
0.3 VDD
VIH(NRST)(1)
NRST input high
level voltage
-
0.39VDD+0.59
-
-
VOL(NRST)(1)
NRST output low
level voltage
Unit
V
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
0.4
Vhys(NRST)(1)
NRST Schmitt trigger
voltage hysteresis
-
-
10%VDD(2)
-
mV
RPU
Weak pull-up
equivalent resistor(3)
VIN = VSS
25
45
65
kΩ
VF(NRST)(1)
NRST input filtered
pulse
-
-
-
50
ns
VNF(NRST)(3)
NRST input not
filtered pulse
-
350
-
-
ns
1. Guaranteed by design.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
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STM32L151xE STM32L152xE
Figure 19. Recommended NRST pin protection
External reset circuit(1)
NRST(2)
VDD
RPU
Internal reset
Filter
0.1 μF
STM32L1xx
ai17854b
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 45. Otherwise the reset is not taken into account by the device.
6.3.15
TIM timer characteristics
The parameters given in the Table 46 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).
Table 46. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 32 MHz
31.25
-
ns
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz
0
fTIMxCLK/2
MHz
0
16
MHz
Timer resolution
-
-
16
bit
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
-
1
65536
tTIMxCLK
2048
µs
Timer resolution time
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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6.3.16
Electrical characteristics
Communications interfaces
I2C interface characteristics
The device I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 47. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output ction characteristics (SDA and SCL).
Table 47. I2C characteristics
Symbol
Standard mode
I2C(1)(2)
Parameter
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
-
3450(3)
-
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
tSP
Pulse width of spikes that
are suppressed by the
analog filter
0
50(4)
0
50(4)
ns
µs
ns
µs
1. Guaranteed by design.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
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STM32L151xE STM32L152xE
Figure 20. I2C bus AC waveforms and measurement circuit
VDD_I2C
VDD_I2C
RP
RP
STM32L1xx
RS
SDA
I2C bus
RS
SCL
S TART REPEATED
S TART
S TART
tsu(STA)
SDA
tf(SDA)
tr(SDA)
tsu(SDA)
th(STA)
tw(SCKL)
th(SDA)
tsu(STA:STO)
S TOP
SCL
tr(SCK)
tw(SCKH)
tf(SCK)
tsu(STO)
ai17855c
1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
0x801B
300
0x8024
200
0x8035
100
0x00A0
50
0x0140
20
0x0320
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
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STM32L151xE STM32L152xE
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the conditions summarized in Table 13.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 49. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)(2)
tf(SCK)(2)
SPI clock rise and fall time
DuCy(SCK)
Min
Max(2)
Master mode
-
16
Slave mode
-
16
Slave transmitter
-
12(3)
Capacitive load: C = 30 pF
-
6
ns
30
70
%
Parameter
Conditions
SPI slave input clock duty cycle Slave mode
tsu(NSS)
NSS setup time
Slave mode
4tHCLK
-
th(NSS)
NSS hold time
Slave mode
2tHCLK
-
SCK high and low time
Master mode
tw(SCKH)(2)
tw(SCKL)(2)
tsu(MI)(2)
tsu(SI)(2)
th(MI)
th(SI)
Data input setup time
(2)
(2)
Data input hold time
Master mode
5
-
Slave mode
6
-
Master mode
5
-
Slave mode
5
-
Data output access time
Slave mode
0
3tHCLK
tv(SO) (2)
Data output valid time
Slave mode
-
33
(2)
Data output valid time
Master mode
-
6.5
Slave mode
17
-
Master mode
0.5
-
th(SO)
(2)
th(MO)(2)
Data output hold time
MHz
tSCK/2 − 5 tSCK/2 +3
ta(SO)(4)
tv(MO)
Unit
ns
1. The characteristics above are given for voltage range 1.
2. Guaranteed by characterization results.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
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Figure 21. SPI timing diagram - slave mode and CPHA = 0
SCK input
NSS input
MISO
OUTPUT
MSB OUT
BIT6 OUT
MSB IN
BIT1 IN
LSB OUT
(SI)
MOSI
INPUT
LSB IN
(SI)
Figure 22. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
th(SO)
tv(SO)
ta(SO)
MISO
OUTPUT
MSB OUT
BIT6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
tsu(SI)
MOSI
INPUT
th(NSS)
tc(SCK)
MSB IN
BIT 1 IN
LSB IN
ai14135b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
Figure 23. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MSB IN
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MI)
MOSI
OUTPUT
MSB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DS10002 Rev 10
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Electrical characteristics
STM32L151xE STM32L152xE
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 50. USB startup time
Symbol
Parameter
tSTARTUP(1)
USB transceiver startup time
Max
Unit
1
µs
1. Guaranteed by design.
Table 51. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
-
3.0
3.6
V
0.2
-
Input levels
VDD
USB operating voltage
VDI(2)
Differential input sensitivity
VCM(2)
Differential common mode range Includes VDI range
0.8
2.5
VSE(2)
Single ended receiver threshold
1.3
2.0
-
0.3
2.8
3.6
I(USB_DP, USB_DM)
-
V
Output levels
VOL(3)
VOH
(3)
RL of 1.5 kΩ to 3.6 V(4)
Static output level low
Static output level high
RL of 15 kΩ to
VSS(4)
V
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
4. RL is the load connected on the USB drivers.
Figure 24. USB timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
Table 52. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Conditions
Min
Max
Unit
tr
Rise time(2)
CL = 50 pF
4
20
ns
tf
Time(2)
CL = 50 pF
4
20
ns
tr/tf
90
110
%
-
1.3
2.0
V
trfm
VCRS
100/136
Parameter
Fall
Rise/ fall time matching
Output signal crossover voltage
DS10002 Rev 10
STM32L151xE STM32L152xE
Electrical characteristics
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification Chapter 7 (version 2.0).
I2S characteristics
Table 53. I2S characteristics
Symbol
fMCK
Parameter
Conditions
Min
Max
256 x 8K 256xFs (1)
I2S Main Clock Output
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
30
70
fCK
I2S clock frequency
DCK
I2S clock frequency duty cycle Slave receiver, 48KHz
tr(CK)
I2S clock rise time
tf(CK)
I2S clock fall time
tv(WS)
-
WS valid time
Master mode
4
24
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
15
-
th(WS)
WS hold time
Slave mode
0
-
tsu(SD_MR) Data input setup time
Master receiver
8
-
tsu(SD_SR) Data input setup time
Slave receiver
9
-
th(SD_MR)
Master receiver
5
-
Slave receiver
4
-
th(SD_SR)
MHz
MHz
%
8
Capacitive load CL=30pF
Data input hold time
Unit
8
tv(SD_ST)
Data output valid time
Slave transmitter
(after enable edge)
-
64
th(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
22
-
tv(SD_MT) Data output valid time
Master transmitter
(after enable edge)
-
12
th(SD_MT) Data output hold time
Master transmitter
(after enable edge)
8
-
ns
1. The maximum for 256xFs is 8 MHz
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Electrical characteristics
STM32L151xE STM32L152xE
Figure 25. I2S slave timing diagram (Philips protocol)(1)
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 26. I2S master timing diagram (Philips protocol)(1)
1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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STM32L151xE STM32L152xE
6.3.17
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 55 are guaranteed by design.
Table 54. ADC clock frequency
Symbol
fADC
Parameter
ADC clock
frequency
Conditions
2.4 V ≤ VDDA ≤ 3.6 V
Voltage
range 1 & 2
Min
VREF+ = VDDA
16
VREF+ < VDDA
VREF+ > 2.4 V
8
VREF+ < VDDA
VREF+ ≤ 2.4 V
1.8 V ≤ VDDA ≤ 2.4 V
Max
0.480
4
VREF+ = VDDA
8
VREF+ < VDDA
4
Voltage range 3
Unit
MHz
4
Table 55. ADC characteristics
Symbol
VDDA
Parameter
Power supply
Conditions
Min
Typ
Max
-
1.8
-
3.6
-
VDDA
VREF+
Positive reference voltage
-
1.8(1)
VREF-
Negative reference voltage
-
-
VSSA
-
IVDDA
Current on the VDDA input pin
-
-
1000
1450
IVREF(2)
Current on the VREF input pin
Peak
-
Average
--
-
0(4)
-
VREF+
Direct channels
-
-
1
Multiplexed channels
-
-
0.76
Direct channels
-
-
1.07
Multiplexed channels
-
-
0.8
Direct channels
-
-
1.23
Multiplexed channels
-
-
0.89
Direct channels
-
-
1.45
Multiplexed channels
-
-
1
VAIN
Conversion voltage range(3)
12-bit sampling rate
10-bit sampling rate
fS
8-bit sampling rate
6-bit sampling rate
DS10002 Rev 10
400
700
Unit
V
µA
450
V
Msps
Msps
Msps
Msps
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Electrical characteristics
STM32L151xE STM32L152xE
Table 55. ADC characteristics (continued)
Symbol
tS(5)
Parameter
Sampling time
tCONV
Total conversion time
(including sampling time)
CADC
Internal sample and hold
capacitor
fTRIG
External trigger frequency
Regular sequencer
fTRIG
External trigger frequency
Injected sequencer
RAIN(6)
Signal source impedance
Conditions
Min
Typ
Max
Direct channels
2.4 V ≤ VDDA ≤ 3.6 V
0.25
-
-
Multiplexed channels
2.4 V ≤ VDDA ≤ 3.6 V
0.56
-
-
Direct channels
1.8 V ≤ VDDA ≤ 2.4 V
0.56
-
-
Multiplexed channels
1.8 V ≤ VDDA ≤ 2.4 V
1
-
-
-
4
-
384
1/fADC
fADC = 16 MHz
1
-
24.75
µs
-
Unit
µs
4 to 384 (sampling phase) +12
(successive approximation)
1/fADC
Direct channels
-
Multiplexed channels
-
12-bit conversions
-
-
6/8/10-bit conversions
-
-
12-bit conversions
-
-
Tconv+2 1/fADC
6/8/10-bit conversions
-
-
Tconv+1 1/fADC
-
-
-
50
kΩ
16
-
pF
-
Tconv+1 1/fADC
Tconv
1/fADC
tlat
Injection trigger conversion
latency
fADC = 16 MHz
219
-
281
ns
-
3.5
-
4.5
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 16 MHz
156
-
219
ns
-
2.5
-
3.5
1/fADC
-
-
-
3.5
µs
tSTAB
Power-up time
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 57: Maximum
source impedance RAIN max.
6. External impedance has another high value limitation when using short sampling time as defined in Table 57: Maximum
source impedance RAIN max.
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STM32L151xE STM32L152xE
Electrical characteristics
Table 56. ADC accuracy(1)(2)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
Test conditions
2.4 V ≤ VDDA ≤ 3.6 V
2.4 V ≤ VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
2.4 V ≤ VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
1.8 V ≤ VDDA ≤ 2.4 V
VDDA = VREF+
fADC = 8 MHz or 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
Min(3)
Typ
Max(3)
-
2.5
4
-
1
2
-
1.5
3.5
-
1
2
-
2.2
3
9.2
10
-
57.5
62
-
57.5
62
-
-
-70
-65
9.2
10
-
57.5
62
-
57.5
62
-
-
-70
-65
-
4
6.5
-
1.5
4
-
3.5
6
-
1
2
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
-
2.5
3
ET
Total unadjusted error
-
2
3
EO
Offset error
-
1
1.5
EG
Gain error
-
1.5
2
ED
Differential linearity error
-
1
2
EL
Integral linearity error
-
2.2
3
2.4 V ≤ VDDA ≤ 3.6 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
1.8 V ≤ VDDA ≤ 2.4 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Unit
LSB
bits
dB
bits
dB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Guaranteed by characterization results.
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
Figure 27. ADC accuracy characteristics
Output code
EG
(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End-point correlation line
2n-1
2n-2
2n-3
n = ADC resolution
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves
EO = offset error: maximum deviation between the
first actual transition and the first ideal one
EG = gain error: deviation between the last ideal
transition and the last actual one
ED = differential linearity error: maximum deviation
between actual steps and the ideal one
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line
(2)
ET
(3)
7
(1)
6
5
EO
EL
4
3
ED
2
1 LSB IDEAL
1
0
1
2
3
4
5
6
7
2n-3
2n-2 2n-1
2n
VREF+ (or VDDA)
MS19880V4
Figure 28. Typical connection diagram using the ADC
VDDA
STM32Lxx
Sample and hold
ADC converter
RAIN(1)
VAIN
AINx
Cparasitic
IL± 50 nA
12-bit
converter
CADC(1)
ai17856e
1. Refer to Table 57: Maximum source impedance RAIN max for the value of RAIN and Table 55: ADC
characteristics for the value of CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC must be reduced.
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STM32L151xE STM32L152xE
Electrical characteristics
Figure 29. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
Iref+
700µA
300µA
MS36686V1
Table 57. Maximum source impedance RAIN max(1)
RAIN max (kΩ)
Ts
(µs)
Multiplexed channels
Ts (cycles)
Direct channels
fADC=16 MHz(2)
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V
0.25
Not allowed
Not allowed
0.7
Not allowed
4
0.5625
0.8
Not allowed
2.0
1.0
9
1
2.0
0.8
4.0
3.0
16
1.5
3.0
1.8
6.0
4.5
24
3
6.8
4.0
15.0
10.0
48
6
15.0
10.0
30.0
20.0
96
12
32.0
25.0
50.0
40.0
192
24
50.0
50.0
50.0
50.0
384
1. Guaranteed by design.
2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced
with respect to the minimum sampling time Ts (µs),
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 11. The applicable
procedure depends on whether VREF+ is connected to VDDA or not. The 100 nF capacitors
must be ceramic (good quality). They must be placed as close as possible to the chip.
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114
Electrical characteristics
6.3.18
STM32L151xE STM32L152xE
DAC electrical specifications
Data guaranteed by design, unless otherwise specified.
Table 58. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
-
1.8
-
3.6
1.8
-
3.6
VDDA
Analog supply voltage
VREF+
Reference supply
voltage
VREF-
Lower reference voltage
IDDVREF+(1)
Current consumption on No load, middle code (0x800)
VREF+ supply
No load, worst code (0x000)
VREF+ = 3.3 V
-
130
220
-
220
350
IDDA(1)
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
-
210
320
-
320
520
5
-
-
25
-
-
RL
Resistive load
VREF+ must always be below
VDDA
-
Connected to
DAC output VSSA
buffer ON
Conected to
VDDA
Unit
V
VSSA
µA
kΩ
CL(2)
Capacitive load
DAC output buffer ON
-
-
50
pF
RO
Output impedance
DAC output buffer OFF
12
16
20
kΩ
DAC output buffer ON
0.2
-
VDDA – 0.2
V
DAC output buffer OFF
0.5
-
VREF+ –
1LSB
mV
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
1.5
3
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
1.5
3
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
2
4
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
±10
±25
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±5
±8
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±1.5
±5
VDAC_OUT
DNL(1)
INL(1)
Offset(1)
Offset1(1)
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Voltage on DAC_OUT
output
Differential non
linearity(3)
Integral non linearity(4)
Offset error at code
0x800 (5)
Offset error at code
0x001(6)
DS10002 Rev 10
LSB
STM32L151xE STM32L152xE
Electrical characteristics
Table 58. DAC characteristics (continued)
Symbol
Parameter
Conditions
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
Offset
error
temperature
dOffset/dT(1)
coefficient (code 0x800) V
= 3.3V
Min
Typ
Max
-20
-10
0
Unit
µV/°C
DDA
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
0
20
50
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
+0 / -0.2%
+0 / -0.4%
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
-10
-2
0
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
-40
-8
0
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
12
30
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
8
12
tSETTLING
Settling time (full scale:
for a 12-bit code
transition between the
lowest and the highest
CL ≤ 50 pF, RL ≥ 5 kΩ
input codes till
DAC_OUT reaches final
value ±1LSB
-
7
12
µs
Update rate
Max frequency for a
correct DAC_OUT
change (95% of final
value) with 1 LSB
variation in the input
code
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
tWAKEUP
Wakeup time from off
state (setting the ENx bit
CL ≤ 50 pF, RL ≥ 5 kΩ
in the DAC Control
(8)
register)
-
9
15
µs
PSRR+
VDDA supply rejection
ratio (static DC
measurement)
-
-60
-35
dB
Gain(1)
dGain/dT(1)
TUE(1)
Gain error(7)
Gain error temperature
coefficient
Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
+0.1 / -0.2% +0.2 / -0.5%
%
µV/°C
LSB
1. Data based on characterization results.
2. Connected between DAC_OUT and VSSA.
3. Difference between two consecutive codes - 1 LSB.
DS10002 Rev 10
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114
Electrical characteristics
STM32L151xE STM32L152xE
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 30. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
DAC_OUTx
12-bit
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.19
Operational amplifier characteristics
Table 59. Operational amplifier characteristics
Symbol
CMIR
VIOFFSET
Condition(1)
Min(2)
Typ
Max(2)
Unit
-
0
-
VDD
-
Maximum
calibration range
-
-
-
±15
After offset
calibration
-
-
-
±1.5
-
-
-
±40
µV/°C
-
-
-
±80
-
-
-
1
-
-
10
Parameter
Common mode input range
Input offset voltage
ΔVIOFFSET
Input offset voltage Normal mode
drift
Low-power mode
IIB
Input current bias
ILOAD
Drive current
IDD
Consumption
CMRR
Common mode
rejection ration
mV
Dedicated input
110/136
General purpose
input
75 °C
Normal mode
-
-
-
500
Low-power mode
-
-
-
100
-
100
220
-
30
60
Normal mode
Low-power mode
No load,
quiescent mode
Normal mode
-
-
-85
-
Low-power mode
-
-
-90
-
DS10002 Rev 10
nA
µA
µA
dB
STM32L151xE STM32L152xE
Electrical characteristics
Table 59. Operational amplifier characteristics (continued)
Symbol
PSRR
Condition(1)
Parameter
Power supply
rejection ratio
Normal mode
Low-power mode
Normal mode
GBW
Bandwidth
Low-power mode
Normal mode
Low-power mode
SR
Slew rate
RL
Resistive load
CL
Capacitive load
VOHSAT
High saturation
voltage
VDD2.4 V
(between 0.1 V and
VDD-0.1 V)
-
700
-
Low-power mode
VDD>2.4 V
-
100
-
-
300
-
-
50
-
Low-power mode
Open loop gain
VDD>2.4 V
Typ
Normal mode
Normal mode
AO
DC
Min(2)
VDD TJ max
2000.00
PD (mW)
LQFP64 10x10 mm / WLCSP104
1500.00
UFBGA132 7x7 mm
LQFP144 20x20 mm
LQFP 100 14x14 mm
1000.00
500.00
0.00
105
75
50
25
0
Temperature (°C)
MSv34185V1
7.6.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DS10002 Rev 10
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135
Ordering information
8
STM32L151xE STM32L152xE
Ordering information
Table 72. STM32L151xE and STM32L152xE Ordering information scheme
Example:
STM32
L 151 R
E
T
6
D TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
L = Low-power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
R = 64 pins
V = 100/104 pins
Z = 144 pins
Q = 132 pins
Flash memory size
E= 512 Kbytes of Flash memory
Package
H = BGA
T = LQFP
Y = WLCSP104
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, contact the nearest ST sales office.
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DS10002 Rev 10
STM32L151xE STM32L152xE
9
Revision History
Revision History
Table 73. Document revision history
Date
Revision
31-Oct-2013
1
Initial release.
19-Feb-2014
2
Added Input Voltage in Table 13: General operating conditions.
Updated: Section 2.2: Ultra-low-power device continuum, Table 21:
Current consumption in Low-power sleep mode, Table 20: Current
consumption in Low-power run mode, Table 36: Flash memory and
data EEPROM endurance and retention,
Updated Ultra-Low-power Feature inside Cover Page
Updated Table 56: ADC accuracy, Table 37: EMS characteristics,
Table 38: EMI characteristics, Table 39: ESD absolute maximum
ratings, Table 42: I/O static characteristics, Table 45: NRST pin
characteristics. Added WLCSP104 recommended footprint for
package WLCSP104, removed figures “Power supply and reference
decoupling (VREF+ not connected to VDDA) and “Power supply and
reference decoupling (VREF+ connected to VDDA). Updated current
consumption values.
21-Feb-2014
3
Ultra low power features modification inside Cover page. Updated
Table 5: Functionalities depending on the working mode (from
Run/active down to standby), Table 58: DAC characteristics
4
Updated IIO in Table 11: Current characteristics.
Removed note 4 in Table 61: Temperature sensor characteristics.
Added Table 41: UFBGA132 recommended footprint..
Modified pins F9 for WLCSP104 package inside Table 8:
STM32L151xE and STM32L152xE pin definitions
13-Oct-2014
5
Updated Section 3.17: Communication interfaces putting I2S
characteristics inside.
Updated DMIPS features in cover page and Section 2: Description.
Updated max temperature at 105°C instead of 85°C in the whole
datasheet.
Updated current consumption in Table 19: Current consumption in
Sleep mode.
Updated Table 24: Peripheral current consumption with new measured
current values.
Updated Table 57: Maximum source impedance RAIN max adding note
2.
10-Feb-2015
6
Updated Section 7: Package information with new package device
marking.
Updated Figure 8: Memory map.
16-May-2014
Changes
DS10002 Rev 10
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135
Revision History
STM32L151xE STM32L152xE
Table 73. Document revision history (continued)
Date
27-Apr-2015
09-Feb-2016
134/136
Revision
Changes
7
Updated Section 7: Package information structure: Paragraph titles
and paragraph heading level.
Updated Section : LQFP144 is a 144-pin 20 x 20 mm, low-profile quad
flat package. removing gate mark in Figure 45 and adding text for
device orientation versus pin1 identifier.
Updated Section : LQFP100 is a 100-pin, 14 x 14 mm, low-profile quad
flat package. removing gate mark in Figure 36 and adding note for
device orientation versus pin 1 identifier.
Updated Section 7: Package information for all other package device
marking adding text in for device orientation versus pin 1 or ball A1
identifier.
Added Figure 38: WLCSP104 recommended footprint and Table 68:
WLCSP104 recommended PCB design rules.
Updated Table 8: STM32L151xE and STM32L152xE pin definitions
ADC inputs.
Updated Table 16: Embedded internal reference voltage temperature
coefficient at 100ppm/°C.
and table footnote 3: “guaranteed by design” changed by “guaranteed
by characterization results”.
Updated Table 63: Comparator 2 characteristics new maximum
threshold voltage temperature coefficient at 100ppm/°C.
8
Updated cover page putting eight SPIs in the peripheral
communication interface list.
Updated Table 2: Ultra-low-power STM32L151xE and STM32L152xE
device features and peripheral counts SPI and I2S lines.
Updated Table 39: ESD absolute maximum ratings CDM class II by
class C3 and C4 depending of the package.
Updated all the notes, removing ‘not tested in production’.
Updated Table 10: Voltage characteristics adding note about VREFpin.
Updated Table 5: Functionalities depending on the working mode (from
Run/active down to standby) LSI and LSE functionalities putting “Y” in
Standby mode.
DS10002 Rev 10
STM32L151xE STM32L152xE
Revision History
Table 73. Document revision history (continued)
Date
25-Aug-2017
20-Apr-2021
Revision
Changes
9
Updated Table 42: I/O static characteristics pull-up and pull-down
values.
Updated Table 45: NRST pin characteristics pull-up values.
Updated Section 7: Package information adding information about
other optional marking or inset/upset marks.
Updated note 1 below all the package device marking figures.
Updated Section 7: Package information replacing “Marking of
engineering samples” by “device marking”.
Updated Nested vectored interrupt controller (NVIC) in Section 3.2:
Arm® Cortex®-M3 core with MPU about process state automatically
saved.
Updated Table 3: Functionalities depending on the operating power
supply range removing I/O operation column and adding note about
GPIO speed.
Updated Table 41: I/O current injection susceptibility note by ‘injection
is not possible’.
Updated Figure 19: Recommended NRST pin protection note about
the 0.1uF capacitor.
Updated Table 58: DAC characteristics resistive load.
Updated Section 3.1: Low-power modes Low-power run mode (MSI)
RC oscillator clock.
Updated Table 5: Functionalities depending on the working mode
(from Run/active down to standby) disabling I2C functionality in Lowpower Run and Low-power Sleep modes.
10
Updated:
– Cover features.
– Section 1: Introduction adding reference to errata sheet.
– Section 4: Pin descriptions.
– Figure 8: Memory map.
– Figure 27: ADC accuracy characteristics.
– Section 7: Package information.
DS10002 Rev 10
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STM32L151xE STM32L152xE
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