STM32L412KBU6

STM32L412xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 16 nA Shutdown mode (4 wakeup pins) – 32 nA Standby mode (4 wakeup pins) – 245 nA Standby mode with RTC – 0.7 µA Stop 2 mode, 0.95 µA with RTC – 79 µA/MHz run mode (LDO Mode) – 28 μA/MHz run mode (@3.3 V SMPS Mode) – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) • Energy benchmark – 442 ULPMark-CP® – 165 ULPMark-PP® • Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – Internal 48 MHz with clock recovery November 2020 This is information on a product in full production. LQFP32 (7x7 mm) UFBGA64 (5x5 mm) UFQFPN32 (5x5 mm) LQFP48 (7x7 mm) UFQFPN48 (7x7 mm) LQFP64 (10x10 mm) WLCSP36 (2.6x3.1 mm) – PLL for system clock • Up to 52 fast I/Os, most 5 V-tolerant • RTC with HW calendar, alarms and calibration • Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors • 10x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 1x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer • Memories – 128 KB single bank Flash, proprietary code readout protection – 40 KB of SRAM including 8 KB with hardware parity check – Quad SPI memory interface with XIP capability • Rich analog peripherals (independent supply) – 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x operational amplifiers with built-in PGA – 1x ultra-low-power comparator – Accurate 2.5 V or 2.048 V reference voltage buffered output • 12x communication interfaces – USB 2.0 full-speed crystal less solution with LPM and BCD – 3x I2C FM+(1 Mbit/s), SMBus/PMBus – 3x USARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART (Stop 2 wake-up) – 2x SPIs (and 1x Quad SPI) – IRTIM (Infrared interface) • 14-channel DMA controller • True random number generator DS12469 Rev 8 1/192 www.st.com STM32L412xx • CRC calculation unit, 96-bit unique ID • All packages are ECOPACK2 compliant • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ Table 1. Device summary Reference STM32L412xx 2/192 Part numbers STM32L412CB, STM32L412KB, STM32L412RB, STM32L412TB STM32L412C8, STM32L412K8, STM32L412R8, STM32L412T8 DS12469 Rev 8 STM32L412xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19 3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.15 3.16 3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 36 3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 36 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DS12469 Rev 8 3/192 6 Contents STM32L412xx 3.17 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.19 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 41 3.20.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.20.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.20.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.20.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 43 3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 45 3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46 3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.26 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.27 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.28 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.29 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.29.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.29.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1 4/192 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DS12469 Rev 8 STM32L412xx Contents 6.1.7 7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 79 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 79 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 137 6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 138 6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.20 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 157 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.2 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.5 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.6 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 DS12469 Rev 8 5/192 6 Contents STM32L412xx 7.7 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 187 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6/192 DS12469 Rev 8 STM32L412xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L412xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17 STM32L412xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32L412xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32L412xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32L412xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L412xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 70 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 79 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 85 Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . 88 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . 90 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 91 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Typical current consumption in Run modes, with different codes running from DS12469 Rev 8 7/192 9 List of tables Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/192 STM32L412xx Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . 93 Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V) . . . . . . . . . 94 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . 95 Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . 95 Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 96 Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . . 97 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 DS12469 Rev 8 STM32L412xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. List of tables OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFBGA64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . 170 LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 WLCSP36 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 WLCSP36 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LQFP32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 STM32L412xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DS12469 Rev 8 9/192 9 List of figures STM32L412xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 10/192 STM32L412xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L412Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32L412Rx, external SMPS, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32L412Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32L412Rx UFBGA64, external SMPS, ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32L412Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32L412Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32L412Tx WLCSP36 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32L412Tx, external SMPS, WLCSP36 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32L412Kx LQFP32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32L412Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32L412xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Current consumption measurement scheme with and without external SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 LQFP64 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . . 168 UFBGA64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 UFBGA64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQFP48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DS12469 Rev 8 STM32L412xx Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. List of figures LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 WLCSP36 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 WLCSP36 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 WLCSP36 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LQFP32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LQFP32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 LQFP32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 DS12469 Rev 8 11/192 11 Introduction 1 STM32L412xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L412xx microcontrollers. This document should be read in conjunction with the STM32L41x, STM32L42x, STM32L43x, STM32L44x, STM32L45x, STM32L46x reference manual (RM0394), available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/192 DS12469 Rev 8 STM32L412xx 2 Description Description The STM32L412xx devices are ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L412xx devices embed high-speed memories (Flash memory up to 128 Kbyte,40 Kbyte of SRAM), a Quad SPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L412xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer two fast 12-bit ADC (5 Msps), two comparators, one operational amplifier, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers. In addition, up to 12 capacitive sensing channels are available. They also feature standard and advanced communication interfaces, namely three I2Cs, two SPIs, three USARTs and one Low-Power UART, one USB full-speed device crystal less. The STM32L412xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.00 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes makes possible the design of lowpower applications. Some independent power supplies are supported: analog independent supply input for ADC, OPAMP and comparator. A VBAT input makes it possible to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. The STM32L412xx family offers six packages from 32 to 64-pin packages. STM32L412CB STM32L412C8 STM32L412TB STM32L412T8 STM32L412KB STM32L412K8 Flash memory STM32L412R8 Peripheral STM32L412RB Table 2. STM32L412xx family device features and peripheral counts 128KB 64KB 128KB 64KB 128KB 64KB 128KB 64KB SRAM Quad SPI 40KB Yes DS12469 Rev 8 13/192 49 Description STM32L412xx Timers Comm. interfac es Advanced control 1 (16-bit) General purpose 2 (16-bit) 1 (32-bit) Basic 1 (16-bit) Low -power 2 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 SPI 2 1 2C 3 2 3 1 2 1 I USART LPUART USB FS Yes RTC Tamper pins Yes 2 2 1 Random generator Yes GPIOs(1) Wakeup pins 52 4 38 3 Capacitive sensing Number of channels 12 6 12-bit ADC Number of channels 2 16 2 10 30 2 2 10 2 10 No Analog comparator 1 Operational amplifiers 1 Max. CPU frequency 80 MHz Operating voltage (VDD) 1.71 to 3.6 V Operating voltage (VDD12) 1.00 to 1.32 V Packages 26 2 2 Internal voltage reference buffer Operating temperature STM32L412K8 STM32L412KB STM32L412T8 STM32L412TB STM32L412C8 STM32L412CB STM32L412R8 Peripheral STM32L412RB Table 2. STM32L412xx family device features and peripheral counts (continued) Ambient operating temperature: -40 to 85 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 130 °C LQFP64 UFBGA64 LQFP48 UFQFPN48 WLCSP36 UFQFPN32 LQFP32 1. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2. 14/192 DS12469 Rev 8 STM32L412xx Description Figure 1. STM32L412xx block diagram D0[3:0], D1[3:0], CLK0, CLK1 CS NJTRST, JTDI, JTCK/SWCLK Quad SPI memory interface JTAG & SW MPU ETM NVIC JTDO/SWD, JTDO TRACECLK D-BUS TRACED[3:0] ARM Cortex-M4 80 MHz FPU I-BUS ART ACCEL/ CACHE RNG Flash up to 128 KB AHB bus-matrix S-BUS SRAM2 8 KB SRAM1 32 KB VDD AHB2 80 MHz DMA2 Power management Voltage regulator 3.3 to 1.2 V VDD = 1.71 to 3.6 V VSS DMA1 @ VDD @ VDD 7 Groups of 4 channels max as AF supervision RC HSI Touch sensing controller Supply reset MSI VDDUSB Int BOR VDDA, VSSA RC LSI PA[15:0] VDD, VSS, NRST GPIO PORT A GPIO PORT B GPIO PORT C PLL 1&2 AHB1 80 MHz PB[15:0] PC[15:0] PVD, PVM @VDD HSI48 OSC_IN XTAL OSC OSC_OUT 4- 16MHz IWDG PD2 GPIO PORT D PH[1:0], PH[3] GPIO PORT H VBAT = 1.55 to 3.6 V Standby interface Reset & clock M AN AGT control @VBAT XTAL 32 kHz PCLKx HCLKx FCLK RTC U STemperature AR T 2 M sensor Bps RTC_TS AWU Backup register RTC_TAMPx RTC_OUT TIM2 32b CRC @ VDDA 4 channels, ETR as AF FIFO ITF USB FS PHY @ VDDUSB ADC1 16 external analog inputs OSC32_IN OSC32_OUT @ VDD DP DM NOE ADC2 16 external analog inputs CRS_SYNC CRS @ VDDA USART2 VREF+ VREF Buffer 83 AF AHB/APB2 AHB/APB1 USART3 EXT IT. WKUP 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1 / PWM smcard IrDA smcard RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF IrDA 16b SPI2 MOSI, MISO, SCK, NSS as AF WWDG 1 channel, 1 compl. channel, BKIN as AF TIM16 RX, TX, CK,CTS, RTS as AF smcard 16b USART1 IrDA MOSI, MISO, SCK, NSS as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF 16b TIM6 A 60PM B Hz 2 SPI1 16b A P B(max) 1 3 0 M Hz APB1 80 MHz TIM15 APB2 80MHz 2 channels, 1 compl. channel, BKIN as AF @VDDA OpAmp1 VOUT, VINM, VINP LPUART1 RX, TX, CTS, RTS as AF LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF @ VDDA INP, INM, OUT COMP1 FIREWALL MSv45999V2 Note: AF: alternate function on I/O pins. DS12469 Rev 8 15/192 49 Functional overview STM32L412xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems, developed to provide a low-cost platform that meets the needs of MCU implementation with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions enabling efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32L412xx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L412xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 16/192 DS12469 Rev 8 STM32L412xx 3.4 Functional overview Embedded Flash memory STM32L412xx devices feature 128Kbyte of embedded Flash memory available for storing programs and data in single bank architecture.The Flash memory contains 64 pages of 2 Kbyte Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 (1) 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP) allows the user to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. The whole non-volatile memory embeds the error correction code (ECC) feature supporting: • single error detection and correction • double error detection. DS12469 Rev 8 17/192 49 Functional overview STM32L412xx The address of the ECC fail can be read in the ECC register. 3.5 Embedded SRAM STM32L412xx devices feature 40 Kbyte of embedded SRAM, split into two blocks: • 32 Kbyte mapped at address 0x2000 0000 (SRAM1) • 8 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2000 8000, offering a contiguous address space with the SRAM1 (8 Kbyte aliased by bit band) This block is accessed through the ICode/DCode buses for maximum performance. These 8 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. 3.7 Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: 18/192 • Boot from user Flash • Boot from system memory • Boot from embedded SRAM DS12469 Rev 8 STM32L412xx Functional overview BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI or USB FS in Device mode through DFU (device firmware upgrade). 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDD12 = 1.00 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load. • VDDA = 1.62 V (ADC/COMP) / 1.8 (OPAMP) to 3.6 V: external analog power supply for ADC, OPAMP, Comparator. The VDDA voltage level is independent from the VDD voltage. • VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant. Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with VDDIO1 = VDD. DS12469 Rev 8 19/192 49 Functional overview STM32L412xx Figure 2. Power supply overview VDDA domain VDDA VSSA A/D converters Comparators Operational amplifiers Voltage reference buffer VDDUSB VSS USB transceivers VDD domain VDD VDDIO1 I/O ring Reset block Temp. sensor PLL, HSI, MSI, HSI48 VSS Standby circuitry (Wakeup logic, IWDG) Voltage regulator VCORE VCORE domain Core Memories Digital peripherals VDD12 Low voltage detector Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MS49685V1 During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDAVDDUSB) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. 20/192 DS12469 Rev 8 STM32L412xx Functional overview Figure 3. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage VDDA with a fixed threshold in order to ensure that the peripheral is in its functional supply range. DS12469 Rev 8 21/192 49 Functional overview 3.9.3 STM32L412xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 8 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L412xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • 3.9.4 Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. Low-power modes The ultra-low-power STM32L412xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. 22/192 DS12469 Rev 8 Mode Regulator(1) CPU Flash SRAM Clocks MR range 1 Run SMPS range 2 high MR range2 LPR Yes ON(4) ON Any Yes ON(4) ON Any except PLL SMPS range 2 high MR range2 No ON(4) ON(5) DS12469 Rev 8 LPR No ON(4) ON(5) No ON 79 µA/MHz N/A 83 µA/MHz to Range 1: 4 µs to Range 2: 64 µs 7.5 µA/MHz 20 µA/MHz 6 cycles 7 µA/MHz Any except PLL All except USB_FS, RNG Any interrupt or event 83 µA/MHz 6 cycles LSE LSI BOR, PVD, PVM RTC, IWDG COMP1, OPAMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) USB_FS(8) 105 µA 2.47 µs in SRAM 4.1 µs in Flash 23/192 Functional overview MR Range 2 OFF 34 µA/MHz 21 µA/MHz All except USB_FS, RNG MR Range 1 Stop 0 N/A Any interrupt or event Any Wakeup time 28 µA/MHz All SMPS range 2 low LPSleep N/A All except USB_FS, RNG Consumption(3) 91 µA/MHz All except USB_FS, RNG MR range 1 Sleep Wakeup source All SMPS range 2 low LPRun DMA and Peripherals(2) STM32L412xx Table 4. STM32L412xx modes overview Mode Stop 1 DS12469 Rev 8 Stop 2 Regulator LPR LPR CPU No No DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time LSE LSI BOR, PVD, PVM RTC, IWDG COMP1, OPAMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) USB_FS(8) 3.25 µA w/o RTC 3.65 µA w RTC 5.7 µs in SRAM 7 µs in Flash LSE LSI BOR, PVD, PVM RTC, IWDG COMP1 I2C3(7) LPUART1(6) LPTIMx (x = 1, 2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMP1 I2C3(7) LPUART1(6) LPTIMx (x = 1, 2) 710 nA w/o RTC 950 nA w RTC 5.8 µs in SRAM 8.3 µs in Flash Flash SRAM Clocks Off Off ON ON Functional overview 24/192 Table 4. STM32L412xx modes overview (continued) (1) STM32L412xx Mode Regulator CPU Flash SRAM Clocks SRAM 2 ON LPR Standby OFF Shutdown OFF Power ed Off Power ed Off Off Off Power ed Off Power ed Off DMA and Peripherals(2) Wakeup source DS12469 Rev 8 LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(9) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(10) Reset pin 5 I/Os (WKUPx)(9) RTC Consumption(3) Wakeup time 195 nA STM32L412xx Table 4. STM32L412xx modes overview (continued) (1) 16.1 µs 105 nA 18 nA 256 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. The SRAM1 and SRAM2 clocks can be gated on or off independently. 6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. USB_FS wakeup by resume from suspend and attach detection protocol event. 9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PA2, PC5. 25/192 Functional overview 10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Functional overview STM32L412xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. 26/192 DS12469 Rev 8 STM32L412xx • Functional overview Shutdown mode The Shutdown mode permits to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. DS12469 Rev 8 27/192 49 Functional overview STM32L412xx Table 5. Functionalities depending on the working mode(1) - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (32 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (8 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - Quad SPI O O O O - - - - - - - - - Backup registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable voltage detector (PVD) O O O O O O O O - - - - - Peripheral voltage monitor (PVMx; x=1,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - High speed Internal (HSI16) O O O O (5) - (5) - - - - - - Oscillator RC48 O O - - - - - - - - - - - High speed external (HSE) O O O O - - - - - - - - - Low speed internal (LSI) O O O O O - O - O - - - - Low speed external (LSE) O O O O O - O - O - O - O Multi-Speed internal (MSI) O O O O - - - - - - - - - Clock security system (CSS) O O O O - - - - - - - - - Clock security system on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 2 2 2 2 2 O 2 O 2 O 2 O 2 USARTx (x=1,2,3) O O O O - - - - - - - Peripheral CPU Flash memory (up to 128 KB) 28/192 Run Sleep Lowpower run Lowpower sleep - O(6) O(6) DS12469 Rev 8 Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT STM32L412xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - - O(7) O(7) O(7) - - - - - Sleep Lowpower run Lowpower sleep - - - Wakeup capability Wakeup capability Standby Shutdown Low-power UART (LPUART) Run Wakeup capability Stop 2 - Peripheral Wakeup capability Stop 0/1 VBAT I2C3 O O O O O(7) SPIx (x=1,2) O O O O - - - - - - - - - ADCx (x=1,2) O O O O - - - - - - - - - OPAMPx (x=1) O O O O O - - - - - - - - COMP1 O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O O O - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 4 pins (11) 4 pins - (10) (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. DS12469 Rev 8 29/192 49 Functional overview STM32L412xx 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.9.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 VBAT operation The VBAT pin permits to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Two anti-tamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.10 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6. STM32L412xx peripherals interconnect matrix Timers synchronization or chaining Y Y Y Y - - Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - Interconnect destination TIMx ADCx TIMx 30/192 Interconnect action DS12469 Rev 8 STM32L412xx Functional overview Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L412xx peripherals interconnect matrix (continued) IRTIM Infrared interface output generation Y Y Y Y - - TIM1 TIM2 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y Y TIM1 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y Y All clocks sources (internal TIM2 and external) TIM15, 16 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - CSS CPU (hard fault) RAM (parity error) TIM1 Flash memory (ECC error) TIM15,16 COMPx PVD Timer break Y Y Y Y - - TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y Y ADCx Conversion external trigger Y Y Y Y - - Interconnect source TIM15/TIM16 COMPx ADCx RTC Interconnect destination Interconnect action GPIO DS12469 Rev 8 31/192 49 Functional overview 3.11 STM32L412xx Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: 32/192 • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. • RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be used to drive the USB or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (RNG, USARTs, I2Cs, LPTimers) have their own independent clock whatever the system clock. PLL having three independent outputs allowing the highest flexibility, can generate independent clocks for the RNG. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS12469 Rev 8 STM32L412xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. DS12469 Rev 8 33/192 49 Functional overview STM32L412xx Figure 4. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN LSE LSI HSE MCO / 1→16 to PWR SYSCLK HSI16 OSC_OUT HSE OSC 4-48 MHz OSC_IN Clock detector to AHB bus, core, memory and DMA Clock source control HSI48 MSI PLLCLK AHB PRESC / 1,2,..512 HCLK FCLK Cortex free running clock to Cortex system timer HSE /8 MSI SYSCLK HSI16 APB1 PRESC / 1,2,4,8,16 PCLK1 to APB1 peripherals x1 or x2 HSI RC 16 MHz LSE HSI16 SYSCLK to USARTx x=2..3 to LPUART1 HSI16 SYSCLK MSI RC 100 kHz – 48 MHz to I2Cx x=1,2,3 LSI LSE HSI16 MSI PLL /M /Q /R PLLCLK to LPTIMx x=1,2 PCLK2 HSI16 APB2 PRESC / 1,2,4,8,16 HSE /P PLL48M1CLK to TIMx x=2,6,7 to APB2 peripherals x1 or x2 LSE HSI16 SYSCLK MSI HSI RC 48 MHz to TIMx x=1,15,16 to USART1 48 MHz clock to USB, RNG SYSCLK to ADCx, x=1,2 CRS MSv46900V3 34/192 DS12469 Rev 8 STM32L412xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.13 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (example: request 1 has priority over request 2) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 DS12469 Rev 8 35/192 49 Functional overview STM32L412xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 37 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 52 GPIOs can be connected to the 16 external interrupt lines. 36/192 DS12469 Rev 8 STM32L412xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds 2 successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution – Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels, some of them shared between ADC1 and ADC2. • 3 internal channels: internal reference voltage, temperature sensor, VBAT/3. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design – • 3.15.1 Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes) – Each ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into 2 data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. DS12469 Rev 8 37/192 49 Functional overview STM32L412xx Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.15.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.16 Comparators (COMP) The STM32L412xx devices embed one rail-to-rail comparator with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.17 Operational amplifier (OPAMP) The STM32L412xx embeds one operational amplifier with external or internal follower routing and PGA capability. 38/192 DS12469 Rev 8 STM32L412xx Functional overview The operational amplifier features: 3.18 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (such as glass or plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 12 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. 3.19 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. DS12469 Rev 8 39/192 49 Functional overview 3.20 STM32L412xx Timers and watchdogs The STM32L412xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.20.1 Advanced-control timer (TIM1) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.20.2) using the same architecture, so the advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 40/192 DS12469 Rev 8 STM32L412xx 3.20.2 Functional overview General-purpose timers (TIM2, TIM15, TIM16) There are up to three synchronizable general-purpose timers embedded in the STM32L412xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 It is a full-featured general-purpose timers: – TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler. This timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoder. • TIM15 and 16 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 has 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.20.3 Basic timer (TIM6) The basic timer can be used as generic 16-bit timebase. 3.20.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. Both LPTIM1 and LPTIM2 are active in Stop 0, Stop 1 and Stop 2 modes. This low-power timer supports the following features: • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) DS12469 Rev 8 41/192 49 Functional overview 3.20.5 STM32L412xx Infrared interface (IRTIM) The STM32L412xx includes one infrared interface (IRTIM), which can be used with an infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels to generate output signal waveforms on IR_OUT pin. 3.20.6 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.20.7 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.8 SysTick timer This timer is dedicated to real-time operating systems, but can also be used as a standard down counter. It features: 42/192 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source DS12469 Rev 8 STM32L412xx 3.21 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Two anti-tamper detection pins with programmable filter. • Timestamp feature, which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. DS12469 Rev 8 43/192 49 Functional overview 3.22 STM32L412xx Inter-integrated circuit interface (I2C) The device embeds three I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 4: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X Wakeup from Stop 1 mode on address match X X X Wakeup from Stop 2 mode on address match - - X 1. X: supported 44/192 DS12469 Rev 8 STM32L412xx 3.23 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L412xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable, and are able to communicate at speeds of up to 10 Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 12. STM32L412xx USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 LPUART1 Hardware flow control for modem X X X X Continuous communication using DMA X X X X Multiprocessor communication X X X X Synchronous mode X X X - Smartcard mode X X X - Single-wire half-duplex communication X X X X IrDA SIR ENDEC block X X X - LIN mode X X X - Dual clock domain X X X X Wakeup from Stop 0 / Stop 1 modes X X X X Wakeup from Stop 2 mode - - - X Receiver timeout interrupt X X X - Modbus communication X X X - Auto baud rate detection X (4 modes) Driver Enable X LPUART/USART data length X X X 7, 8 and 9 bits 1. X = supported. DS12469 Rev 8 45/192 49 Functional overview 3.24 STM32L412xx Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 46/192 DS12469 Rev 8 STM32L412xx 3.25 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.26 Universal serial bus (USB) The STM32L412xx devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 KB and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.27 Clock recovery system (CRS) The STM32L412xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.28 Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad SPI flash memories are accessed simultaneously. DS12469 Rev 8 47/192 49 Functional overview STM32L412xx The Quad SPI interface supports: 48/192 • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS12469 Rev 8 STM32L412xx Functional overview 3.29 Development support 3.29.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.29.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L412xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell™ operates with third party debugger software tools. DS12469 Rev 8 49/192 49 Pinouts and pin description 4 STM32L412xx Pinouts and pin description VDD VSS PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 5. STM32L412Rx LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP64 MSv46920V1 1. The above figure shows the package top view. VDD VSS VDD12 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 6. STM32L412Rx, external SMPS, LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PB10 PB11 VDD12 VSS VDD LQFP64 1. The above figure shows the package top view. 50/192 DS12469 Rev 8 MS46959V1 STM32L412xx Pinouts and pin description Figure 7. STM32L412Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 A PC14OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 PH3-BOOT0 PD2 PC11 PC10 PA12 C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11 D PH1OSC_OUT VDD PB6 VSS VSS VSS PA8 PC9 E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8 F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14 G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13 H VDDA/VREF+ PA1 PA4 PA7 PC4 PC5 PB11 PB12 MSv46919V1 1. The above figure shows the package top view. Figure 8. STM32L412Rx UFBGA64, external SMPS, ballout(1) 1 2 3 4 5 6 7 8 A PC14OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 PH3-BOOT0 VDD12 PC11 PC10 PA12 C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11 D PH1OSC_OUT VDD PB6 VSS VSS VSS PA8 PC9 E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8 F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14 G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13 H VDDA/VREF+ PA1 PA4 PA7 PC4 VDD12 PB11 PB12 MS53656V1 1. The above figure shows the package top view. DS12469 Rev 8 51/192 72 Pinouts and pin description STM32L412xx VDD VSS PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 9. STM32L412Cx LQFP48 pinout(1) VBAT 1 36 VDDUSB PC13 2 35 VSS PC14/OSC32_IN 3 34 PA13 PC15/OSC32_OUT 4 33 PA12 PH0/OSC_IN 5 32 PA11 PH1/OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA 8 29 PA8 VDDA 9 28 PB15 PA0/CK_IN 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP48 MSv46916V1 1. The above figure shows the package top view. VDD VSS PB9 PB8 PH3/BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Figure 10. STM32L412Cx UFQFPN48 pinout(1) VBAT 1 36 VDDUSB PC13 2 35 VSS PC14/OSC32_IN 3 34 PA13 PC15/OSC32_OUT 4 33 PA12 PH0/OSC_IN 5 32 PA11 PH1/OSC_OUT 6 31 PA10 NRST 7 30 PA9 VSSA 8 29 PA8 VDDA 9 28 PB15 PA0/CK_IN 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 13 14 15 16 17 18 19 20 21 22 23 24 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD UFQFPN48 MSv46917V1 1. The above figure shows the package top view. 52/192 DS12469 Rev 8 STM32L412xx Pinouts and pin description Figure 11. STM32L412Tx WLCSP36 ballout(1) 1 2 3 4 5 6 A PA12 PA14 PB4 PB7 VSS VDD B PA11 PA13 PB3 PB6 PB8 PC14 C PA9 PA10 PA15 PB5 D PA8 PB1 PA6 PA1 PA0 NRST E VDD PB2 PA7 PA5 PA2 VREF+ F VSS PB10 PB0 PA4 PA3 VDDA PH3 PC15 BOOT0 MS49688V1 1. The above figure shows the package top view. Figure 12. STM32L412Tx, external SMPS, WLCSP36 ballout(1) 1 2 3 4 5 6 A PA12 PA14 PB4 PB7 VSS VDD B PA11 PA13 PB3 PB6 VDD12 PC14 C PA9 PA10 PA15 PB5 PH3 PC15 D PA8 PB1 PA6 PA2 PA1 NRST E VDD PB10 PB0 PA5 PA3 VDDA/ VREF+ F VSS VDD12 PB2 PA7 PA4 PA0 MS51459V1 1. The above figure shows the package top view. DS12469 Rev 8 53/192 72 Pinouts and pin description STM32L412xx VSS PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 32 31 30 29 28 27 26 25 Figure 13. STM32L412Kx LQFP32 pinout(1) VDD 1 24 PA14 PC14-OSC32_IN 2 23 PA13 PC15-OSC32_OUT 3 22 PA12 NRST 4 21 PA11 VDDA/VREF+ 5 20 PA10 PA0-CK_IN 6 19 PA9 PA1 7 18 PA8 PA2 8 17 VDD 9 10 11 12 13 14 15 16 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS LQFP32 MSv46914V1 1. The above figure shows the package top view. VSS PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 32 31 30 29 28 27 26 25 Figure 14. STM32L412Kx UFQFPN32 pinout(1) VDD 1 24 PA14 PC14-OSC32_IN 2 23 PA13 PC15-OSC32_OUT 3 22 PA12 NRST 4 21 PA11 VDDA/VREF+ 5 20 PA10 PA0-CK_IN 6 19 PA9 PA1 7 18 PA8 PA2 8 17 VDD 9 10 11 12 13 14 15 16 PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS UFQFPN32 MSv46915V1 1. The above figure shows the package top view. 54/192 DS12469 Rev 8 STM32L412xx Pinouts and pin description Table 13. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor I/O structure Option for TT or FT I/Os _f (1) _u I/O, Fm+ capable (2) I/O, with USB function supplied by VDDUSB _a (3) Notes I/O, with Analog switch function supplied by VDDA Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 14 are: FT_f, FT_fa. 2. The related I/O structures in Table 14 are: FT_u, FT_fu. 3. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a. DS12469 Rev 8 55/192 72 WLCSP36 SMPS WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS Pin type I/O structure Notes Alternate functions - - - - 1 1 1 1 B2 B2 VBAT S - - - - - - - - 2 2 2 2 A2 A2 PC13 I/O FT - EVENTOUT RTC_TAMP1/RTC_TS/RT C_OUT1/WKUP2 2 2 B6 B6 3 3 3 3 A1 A1 PC14-OSC32_IN (PC14) I/O FT - EVENTOUT OSC32_IN 3 3 C6 C6 4 4 4 4 B1 B1 PC15OSC32_OUT (PC15) I/O FT - EVENTOUT OSC32_OUT - - - - 5 5 5 5 C1 C1 PH0-OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN - - - - 6 6 6 6 D1 D1 PH1-OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT 4 4 D6 D6 7 7 7 7 E1 E1 NRST I/O RST - - - - - - - - - 8 8 E3 E3 PC0 I/O FT_fa - TRACECK, LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LPTIM2_IN1, EVENTOUT ADC12_IN1 - - - - - - 9 9 E2 E2 PC1 I/O FT_fa - TRACED0, LPTIM1_OUT, I2C3_SDA, LPUART1_TX, EVENTOUT ADC12_IN2 - - - - - - 10 10 F2 F2 PC2 I/O FT_a - LPTIM1_IN2, SPI2_MISO, EVENTOUT ADC12_IN3 - - - - - - 11 11 G1 G1 PC3 I/O FT_a - LPTIM1_ETR, SPI2_MOSI, LPTIM2_ETR, EVENTOUT ADC12_IN4 - - - - 8 8 12 12 F1 F1 VSSA/VREF- S - - - - - - E6 E6 - - - - - - VREF+ S - - - - Pin name (function after reset) Additional functions STM32L412xx UFQFPN32 DS12469 Rev 8 LQFP32 Pin Number Pinouts and pin description 56/192 Table 14. STM32L412xx pin definitions LQFP32 UFQFPN32 WLCSP36 SMPS WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS Pin type I/O structure Notes Pin Number Alternate functions - - - F6 - - - - - - VDDA S - - - 5 5 E6 - 9 9 13 13 H1 H1 VDDA/VREF+ S - - - DS12469 Rev 8 6 7 8 - 6 7 8 - F6 D5 D4 - D5 D4 E5 10 - 11 12 10 - 11 12 14 - 15 16 14 - 15 16 G2 - H2 F3 G2 - H2 F3 Pin name (function after reset) PA0 PA0-CK_IN PA1 PA2 I/O I/O I/O I/O FT_a FT_a FT_a FT_a TT_a - - - - TIM2_CH1, USART2_CTS, OPAMP1_VINP, COMP1_OUT, TIM2_ETR, COMP1_INM, ADC1_IN5, EVENTOUT RTC_TAMP2/WKUP1 - OPAMP1_VINP, TIM2_CH1, USART2_CTS, COMP1_INM, ADC1_IN5, COMP1_OUT, TIM2_ETR, RTC_TAMP2/WKUP1, EVENTOUT CK_IN - TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, TIM15_CH1N, EVENTOUT OPAMP1_VINM, COMP1_INP, ADC1_IN6 - TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, TIM15_CH1, EVENTOUT ADC12_IN7, WKUP4/LSCO - TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, TIM15_CH2, EVENTOUT OPAMP1_VOUT, ADC12_IN8 9 9 F5 F5 13 13 17 17 G3 G3 - - - - - - 18 18 C2 C2 VSS S - - - - - - - - - - 19 19 D2 D2 VDD S - - - - 10 10 F5 F4 14 14 20 20 H3 H3 PA4 I/O TT_a SPI1_NSS, USART2_CK, COMP1_INM, ADC12_IN9 LPTIM2_OUT, EVENTOUT 57/192 Pinouts and pin description PA3 I/O Additional functions STM32L412xx Table 14. STM32L412xx pin definitions (continued) WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS E4 E4 15 15 21 21 F4 F4 12 12 D3 D3 16 16 22 22 G4 G4 PA5 PA6 DS12469 Rev 8 Alternate functions Additional functions I/O TT_a TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, EVENTOUT COMP1_INM, ADC12_IN10 FT_a TIM1_BKIN, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, TIM16_CH1, EVENTOUT ADC12_IN11 ADC12_IN12 I/O Notes WLCSP36 SMPS 11 I/O structure UFQFPN32 11 Pin name (function after reset) Pin type LQFP32 Pin Number 13 F4 E3 17 17 23 23 H4 H4 PA7 I/O FT_fa - - - - - - 24 24 H5 H5 PC4 I/O FT_a USART3_TX, EVENTOUT COMP1_INM, ADC12_IN13 - - - - - - - 25 H6 - PC5 I/O FT_a USART3_RX, EVENTOUT COMP1_INP, ADC12_IN14, WKUP5 FT_a TRACED0, TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, EVENTOUT ADC12_IN15 TRACED1, TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LPTIM2_IN1, EVENTOUT COMP1_INM, ADC12_IN16 14 14 E3 F3 18 18 25 26 F5 F5 PB0 I/O 15 15 D2 D2 19 19 26 27 G5 G5 PB1 I/O FT_a - - F3 E2 20 20 27 28 G6 G6 PB2 I/O FT_a LPTIM1_OUT, I2C3_SMBA, COMP1_INP, RTC_OUT2 EVENTOUT STM32L412xx 13 TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, EVENTOUT Pinouts and pin description 58/192 Table 14. STM32L412xx pin definitions (continued) - - - - E2 - F2 - 21 22 21 28 22 29 29 30 G7 G7 PB10 H7 H7 PB11 I/O I/O Notes I/O structure Pin name (function after reset) Pin type UFBGA64 SMPS UFBGA64 LQFP64 LQFP64 SMPS UFQFPN48 LQFP48 WLCSP36 WLCSP36 SMPS UFQFPN32 LQFP32 Pin Number DS12469 Rev 8 Alternate functions Additional functions FT_f TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, COMP1_OUT, EVENTOUT - FT_f TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, EVENTOUT - - F2 - - - 30 - - H6 VDD12 S - - - - 16 F1 F1 23 23 31 31 D6 D6 VSS S - - - - 17 17 E1 E1 24 24 32 32 E6 E6 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, TIM15_BKIN, EVENTOUT - FT_f TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, TIM15_CH1N, EVENTOUT - FT_f TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE, TSC_G1_IO3, TIM15_CH1, EVENTOUT - - - - - - - - - - - - - 25 26 27 25 26 27 33 34 35 33 34 35 H8 G8 F8 H8 G8 F8 PB12 PB13 PB14 I/O I/O I/O FT - 59/192 Pinouts and pin description 16 STM32L412xx Table 14. STM32L412xx pin definitions (continued) UFQFPN32 WLCSP36 SMPS WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS Pin type I/O structure Notes DS12469 Rev 8 LQFP32 Pin Number Alternate functions - - - - 28 28 36 36 F7 F7 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, TIM15_CH2, EVENTOUT - - - - - - - 37 37 F6 F6 PC6 I/O FT - TSC_G4_IO1, EVENTOUT - - - - - - - 38 38 E7 E7 PC7 I/O FT - TSC_G4_IO2, EVENTOUT - - - - - - - 39 39 E8 E8 PC8 I/O FT - TSC_G4_IO3, EVENTOUT - TSC_G4_IO4, USB_NOE, EVENTOUT - Pin name (function after reset) Additional functions - - - - - 40 40 D8 D8 PC9 I/O FT - 18 18 D1 D1 29 29 41 41 D7 D7 PA8 I/O FT MCO, TIM1_CH1, - USART1_CK, LPTIM2_OUT, EVENTOUT - 19 19 C1 C1 30 30 42 42 C7 C7 PA9 I/O FT_f - TIM1_CH2, I2C1_SCL, USART1_TX, TIM15_BKIN, EVENTOUT - - TIM1_CH3, I2C1_SDA, USART1_RX, USB_CRS_SYNC, EVENTOUT - - - 20 20 C2 C2 31 31 43 43 C6 C6 PA10 I/O FT_f 21 21 B1 B1 32 32 44 44 C8 C8 PA11 I/O FT_u - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, USB_DM, TIM1_BKIN2_COMP1, EVENTOUT 22 22 A1 A1 33 33 45 45 B8 B8 PA12 I/O FT_u - TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, USB_DP, EVENTOUT STM32L412xx - Pinouts and pin description 60/192 Table 14. STM32L412xx pin definitions (continued) UFQFPN32 WLCSP36 SMPS WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS Pin type I/O structure Notes DS12469 Rev 8 LQFP32 Pin Number Alternate functions 23 23 B2 B2 34 34 46 46 A8 A8 PA13 (JTMS/SWDIO) I/O FT - JTMS/SWDIO, IR_OUT, USB_NOE, EVENTOUT - - - - - 35 35 47 47 D5 D5 VSS S - - - - - - - - 36 36 48 48 E5 E5 VDDUSB S - - - - 24 24 A2 A2 37 37 49 49 A7 A7 PA14 (JTCK/SWCLK) I/O FT - JTCK/SWCLK, LPTIM1_OUT, I2C1_SMBA, EVENTOUT - - Pin name (function after reset) Additional functions 25 C3 C3 38 38 50 50 A6 A6 PA15 (JTDI) I/O FT - - - - - - - 51 51 B7 B7 PC10 I/O FT - TRACED1, USART3_TX, TSC_G3_IO2, EVENTOUT - - - - - - - 52 52 B6 B6 PC11 I/O FT - USART3_RX, TSC_G3_IO3, EVENTOUT - - - - - - - 53 53 C5 C5 PC12 I/O FT - TRACED3, USART3_CK, TSC_G3_IO4, EVENTOUT - - - - - - - - 54 B5 - PD2 I/O FT - TRACED2, USART3_RTS_DE, TSC_SYNC, EVENTOUT - A5 PB3 (JTDO/TRACESW O) - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, USART1_RTS_DE, EVENTOUT - 26 26 B3 B3 39 39 54 55 A5 I/O FT_a 61/192 Pinouts and pin description 25 JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, USART3_RTS_DE, TSC_G3_IO1, EVENTOUT STM32L412xx Table 14. STM32L412xx pin definitions (continued) WLCSP36 LQFP48 UFQFPN48 LQFP64 SMPS LQFP64 UFBGA64 UFBGA64 SMPS A3 A3 40 40 55 56 A4 A4 28 28 C4 C4 41 41 56 57 C4 C4 PB4 (NJTRST) I/O FT_fa PB5 I/O DS12469 Rev 8 Notes WLCSP36 SMPS 27 I/O structure UFQFPN32 27 Pin name (function after reset) Pin type LQFP32 Pin Number Alternate functions Additional functions - NJTRST, I2C3_SDA, SPI1_MISO, USART1_CTS, TSC_G2_IO1, EVENTOUT - FT TRACED2, LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, USART1_CK, TSC_G2_IO2, TIM16_BKIN, EVENTOUT - - 29 B4 B4 42 42 57 58 D3 D3 PB6 I/O FT_fa 30 30 A4 A4 43 43 58 59 C3 C3 PB7 I/O FT_fa - TRACECK, LPTIM1_IN2, I2C1_SDA, USART1_RX, TSC_G2_IO4, EVENTOUT PVD_IN 31 31 C5 C5 44 44 59 60 B4 B4 PH3-BOOT0 (BOOT0) I/O FT - EVENTOUT - - - - B5 45 45 60 61 B3 B3 PB8 I/O FT_f - I2C1_SCL, TIM16_CH1, EVENTOUT - - - - - 46 46 61 62 A3 A3 PB9 I/O FT_f - IR_OUT, I2C1_SDA, SPI2_NSS, EVENTOUT - - - B5 - - - 62 - - B5 VDD12 S - - - 32 32 A5 A5 47 47 63 63 D4 D4 VSS S - - - 1 1 A6 A6 48 48 64 64 E4 E4 VDD S - - - STM32L412xx 29 TRACED3, LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, TIM16_CH1N, EVENTOUT Pinouts and pin description 62/192 Table 14. STM32L412xx pin definitions (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/LPT IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA RT2/USART3 PA0 - TIM2_CH1 - - - - - USART2_CTS PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - USART2_RTS_ DE PA2 - TIM2_CH3 - - - - - USART2_TX PA3 - TIM2_CH4 - - - - - USART2_RX PA4 - - - - - SPI1_NSS - USART2_CK PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - PA6 - TIM1_BKIN - - SPI1_MISO COMP1_OUT USART3_CTS PA7 - TIM1_CH1N - - SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - USART1_CK PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_ DE PA13 JTMS/SWDAT IR_OUT - - - - - - PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA - - - PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS - USART3_RTS_ DE Port DS12469 Rev 8 Port A I2C3_SCL 63/192 Pinouts and pin description AF0 STM32L412xx Table 15. Alternate function AF0 to AF7(1) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/LPT IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA RT2/USART3 PB0 TRACED0 TIM1_CH2N - - - SPI1_NSS - USART3_CK PB1 TRACED1 TIM1_CH3N - - - - - USART3_RTS_ DE PB2 - LPTIM1_OUT - - I2C3_SMBA - - - PB3 JTDO/TRACES WO TIM2_CH2 - - - SPI1_SCK - USART1_RTS_ DE PB4 NJTRST - - - I2C3_SDA SPI1_MISO - USART1_CTS PB5 TRACED2 LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI - USART1_CK PB6 TRACED3 LPTIM1_ETR - - I2C1_SCL - - USART1_TX PB7 TRACECK LPTIM1_IN2 - - I2C1_SDA - - USART1_RX PB8 - - - - I2C1_SCL - - - PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX PB11 - TIM2_CH4 - - I2C2_SDA - USART3_RX PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS - USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO - USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - - Port DS12469 Rev 8 Port B Pinouts and pin description 64/192 Table 15. Alternate function AF0 to AF7(1) (continued) STM32L412xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/LPT IM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1 USART1/USA RT2/USART3 PC0 TRACECK LPTIM1_IN1 - - I2C3_SCL - - - PC1 TRACED0 LPTIM1_OUT - - I2C3_SDA - - - PC2 - LPTIM1_IN2 - - - SPI2_MISO - - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - - - - - - - PC7 - - - - - - - - PC8 - - - - - - - - PC9 - - - - - - - - PC10 TRACED1 - - - - - - USART3_TX PC11 - - - - - - - USART3_RX PC12 TRACED3 - - - - - - USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - PD2 TRACED2 - - - - - - USART3_RTS_ DE PH0 - - - - - - - - PH1 - - - - - - - - PH3 - - - - - - - - Port DS12469 Rev 8 Port C Port D Port H 1. Refer to Table 16 for AF8 to AF15. 65/192 Pinouts and pin description AF0 STM32L412xx Table 15. Alternate function AF0 to AF7(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 LPUART1 TSC QUADSPI - COMP1 - TIM2/TIM15/ TIM16/LPTIM2 EVENOUT PA0 - - - - - TIM2_ETR EVENTOUT PA1 - - - - - - TIM15_CH1N EVENTOUT Port DS12469 Rev 8 Port A COMP1_OUT PA2 LPUART1_TX - QUADSPI_BK1 _NCS - - - TIM15_CH1 EVENTOUT PA3 LPUART1_RX - QUADSPI_CLK - - - TIM15_CH2 EVENTOUT PA4 - - - - - - LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 LPUART1_CTS - QUADSPI_BK1 _IO3 - - - TIM16_CH1 EVENTOUT PA7 - - QUADSPI_BK1 _IO2 - - - PA8 - - - - - - LPTIM2_OUT EVENTOUT PA9 - - - - - - TIM15_BKIN EVENTOUT PA10 - - USB_CRS_SY NC - - - - EVENTOUT PA11 - - USB_DM - TIM1_BKIN2_C OMP1 - - EVENTOUT PA12 - - USB_DP - - - - EVENTOUT PA13 - - USB_NOE - - - - EVENTOUT PA14 - - - - - - - EVENTOUT PA15 - - - - - - EVENTOUT TSC_G3_IO1 - Pinouts and pin description 66/192 Table 16. Alternate function AF8 to AF15(1) EVENTOUT STM32L412xx AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 LPUART1 TSC QUADSPI - COMP1 - TIM2/TIM15/ TIM16/LPTIM2 EVENOUT PB0 - - QUADSPI_BK1 _IO1 - - - - PB1 LPUART1_RTS _DE - QUADSPI_BK1 _IO0 - PB2 - - - - - - - EVENTOUT PB3 - - - - - - - EVENTOUT PB4 - TSC_G2_IO1 - - - - - EVENTOUT PB5 - TSC_G2_IO2 - - - - TIM16_BKIN EVENTOUT PB6 - TSC_G2_IO3 - - - - TIM16_CH1N EVENTOUT PB7 - TSC_G2_IO4 - - - - PB8 - - - - - - PB9 - - - - - - - EVENTOUT - QUADSPI_CLK - - - - EVENTOUT QUADSPI_BK1 _NCS - - - EVENTOUT Port DS12469 Rev 8 Port B PB10 LPUART1_RX TSC_SYNC COMP1_OUT COMP1_OUT - LPTIM2_IN1 TIM16_CH1 STM32L412xx Table 16. Alternate function AF8 to AF15(1) (continued) EVENTOUT EVENTOUT EVENTOUT EVENTOUT LPUART1_TX PB12 LPUART1_RTS TSC_G1_IO1 _DE - - - - TIM15_BKIN EVENTOUT PB13 LPUART1_CTS TSC_G1_IO2 - - - - TIM15_CH1N EVENTOUT PB14 - TSC_G1_IO3 - - - - TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - - - - TIM15_CH2 EVENTOUT 67/192 Pinouts and pin description PB11 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 LPUART1 TSC QUADSPI - COMP1 - TIM2/TIM15/ TIM16/LPTIM2 EVENOUT LPTIM2_IN1 Port DS12469 Rev 8 Port C Port D Port H PC0 LPUART1_RX - - - - - EVENTOUT PC1 LPUART1_TX - - - - - - EVENTOUT - EVENTOUT PC2 - - - - - - PC3 - - - - - - PC4 - - - - - - - EVENTOUT PC5 - - - - - - - EVENTOUT PC6 - TSC_G4_IO1 - - - - - EVENTOUT PC7 - TSC_G4_IO2 - - - - - EVENTOUT PC8 - TSC_G4_IO3 - - - - - EVENTOUT PC9 - TSC_G4_IO4 - - - - EVENTOUT PC10 - TSC_G3_IO2 - - - - - EVENTOUT PC11 - TSC_G3_IO3 - - - - - EVENTOUT PC12 - TSC_G3_IO4 - - - - - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT PD2 - - - - - - EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - PH3 - - - - - - - EVENTOUT EVENTOUT STM32L412xx 1. Refer to Table 15 for AF0 to AF7. TSC_SYNC USB_NOE LPTIM2_ETR Pinouts and pin description 68/192 Table 16. Alternate function AF8 to AF15(1) (continued) STM32L412xx 5 Memory mapping Memory mapping Figure 15. STM32L412xx memory map 0xFFFF FFFF 0xBFFF FFFF Cortex™-M4 with FPU Internal Peripherals 7 Reserved 0xA000 1400 QUADSPI registers 0xA000 1000 0xE000 0000 0x5FFF FFFF Reserved 6 0x5006 0C00 AHB2 0x4800 0000 Reserved 0xC000 0000 QUADSPI registers 5 0x4002 4400 AHB1 0x4002 0000 0xA000 1000 0x4001 5800 0xA000 0000 QUADSPI Flash bank 4 0x9000 0000 Reserved APB2 0x4001 0000 Reserved 0x4000 9800 APB1 0x4000 0000 0x1FFF FFFF 0x8000 0000 3 Reserved 0x6000 0000 0x1FFF 7810 Options Bytes 2 0x1FFF 7800 Reserved 0x1FFF 7400 Peripherals 0x4000 0000 OTP area 0x1FFF 7000 System memory 1 0x2000 A000 0x2000 8000 SRAM2 SRAM1 0x2000 0000 0x1FFF 0000 Reserved 0x1000 2000 SRAM2 0x1000 0000 Reserved 0 CODE 0x0802 0000 Flash memory 0x0800 0000 0x0000 0000 0x0002 0000 Reserved 0x0000 0000 Reserved Flash, system memory or SRAM, depending on BOOT configuration MSv45997V1 DS12469 Rev 8 69/192 72 Memory mapping STM32L412xx Table 17. STM32L412xx memory map and peripheral register boundary addresses(1) Bus Boundary address - AHB1 70/192 Peripheral 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5006 0400 - 0x5006 07FF 1 KB Reserved 128 KB Reserved 0x5004 0400 - 5006 07FF AHB2 Size(bytes) 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB Reserved 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1000 - 0x4800 1BFF 3 KB Reserved 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~127 MB 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 0x4002 0000 - 0x4002 03FF 1 KB DMA1 DS12469 Rev 8 Reserved STM32L412xx Memory mapping Table 17. STM32L412xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 APB1 Boundary address Size(bytes) Peripheral 0x4001 4800 - 0x4001 FFFF 46 KB Reserved 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2000 - 0x4001 2BFF 3 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 1 KB COMP 0x4001 0030 - 0x4001 01FF 1 KB Reserved 0x4001 0000 - 0x4001 002F 1 KB SYSCFG 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8400 - 0x4000 93FF 4 KB Reserved 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP 0x4000 7400 - 0x4000 77FF 1 KB Reserved 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM 0x4000 6800 - 0x4000 6BFF 1 KB USB FS 0x4000 6400 - 0x4000 67FF 1 KB Reserved 0x4000 6000 - 0x4000 63FF 1 KB CRS 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 4C00 - 0x4000 53FF 2 KB Reserved 0x4000 4800 - 0x4000 4BFF 1 KB USART3 0x4000 4400 - 0x4000 47FF 1 KB USART2 0x4000 4000 - 0x4000 43FF 1 KB Reserved DS12469 Rev 8 71/192 72 Memory mapping STM32L412xx Table 17. STM32L412xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Peripheral 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 1400 - 0x4000 27FF 5 KB Reserved 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0400- 0x4000 0FFF 3 KB Reserved 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. 72/192 Size(bytes) DS12469 Rev 8 STM32L412xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 16. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 16. Pin loading conditions Figure 17. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 DS12469 Rev 8 MS19211V1 73/192 164 Electrical characteristics 6.1.6 STM32L412xx Power supply scheme Figure 18. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch VDD VCORE n x VDD Regulator OUT n x 100 nF GPIOs IN +1 x 4.7 μF Level shifter VDDIO1 IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDA VDDA VREF 10 nF +1 μF 100 nF +1 μF VREF+ VREF- ADCs/ OPAMPs/ COMPs/ VSSA MS49692V1 Caution: 74/192 Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS12469 Rev 8 STM32L412xx 6.1.7 Electrical characteristics Current consumption measurement Figure 19. Current consumption measurement scheme with and without external SMPS power supply IDD_USB IDD_USB VDDUSB VDDUSB IDD_VBAT IDD_VBAT VBAT VBAT IDD IDD IDDA SMPS VDD VDD12 VDD IDDA VDDA VDDA MSv45729V1 The IDD_ALL parameters given in Table 25 to Table 47 represent the total MCU consumption including the current supplying VDD, VDDA, VDDUSB and VBAT. 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 18. Voltage characteristics(1) Symbol Ratings Min Max Unit VDDX - VSS External main supply voltage (including VDD, VDDA, VDDUSB, VBAT) -0.3 4.0 V VDD12 - VSS External SMPS supply voltage -0.3 1.32 V Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDUSB) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on any other pins VSS-0.3 4.0 VIN(2) DS12469 Rev 8 V 75/192 164 Electrical characteristics STM32L412xx Table 18. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 19. Current characteristics Symbol ∑IVDD Ratings Max Total current into sum of all VDD power lines (source)(1)(2) 140 (1) ∑IVSS Total current out of sum of all VSS ground lines (sink) IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100 IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(4) ∑|IINJ(PIN)| Unit 140 Total output current sunk by sum of all I/Os and control pins(3) mA 100 (3) Total output current sourced by sum of all I/Os and control pins Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 100 -5/+0(5) Injected current on PA4, PA5 -5/0 Total injected current (sum of all I/Os and control pins)(6) 25 1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. Valid also for VDD12 on SMPS packages. 3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). 76/192 DS12469 Rev 8 STM32L412xx Electrical characteristics Table 20. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS12469 Rev 8 Value Unit –65 to +150 °C 150 °C 77/192 164 Electrical characteristics STM32L412xx 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDA Analog supply voltage Standard operating voltage VBAT Backup operating voltage VDDUSB USB supply voltage VIN PD PD 78/192 I/O input voltage Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(4) Power dissipation at TA = 125 °C for suffix 3(4) MHz 3.6 V 3.6 V 1.32 V 1.55 3.6 V 3.0 3.6 0 3.6 TT_xx I/O -0.3 VDDIOx+0.3 All I/O except TT_xx -0.3 Min(Min(VDD, VDDA, VDDUSB)+3.6 V, 5.5 V)(2)(3) LQFP64 - 303 UFBGA64 - 317 LQFP48 - 294 UFQFPN48 - 667 (1) ADC or COMP used 1.62 OPAMP used 1.8 ADC, OPAMP, COMP not used VDD12 1.71 Unit 0 Full frequency range 1.08 Up to 26 MHz 1.00 - USB used USB not used WLCSP36 235 LQFP32 294 UFQFPN32 541 LQFP64 - 76 UFBGA64 - 79 LQFP48 - 75 UFQFPN48 - 167 WLCSP36 - 59 LQFP32 - 75 UFQFPN32 - 135 DS12469 Rev 8 V V mW mW STM32L412xx Electrical characteristics Table 21. General operating conditions (continued) Symbol Parameter Conditions Max Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 Low-power dissipation(5) –40 105 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(5) –40 130 Suffix 6 version –40 105 Suffix 3 version –40 130 TA TJ Min Junction temperature range Unit °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Max - 0 ∞ ULPEN = 0 10 ∞ ULPEN = 1 100 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ VDD rise time rate tVDD VDD fall time rate VDDA rise time rate tVDDA VDDA fall time rate VDDUSB rise time rate tVDDUSB 6.3.3 - - VDDUSB fall time rate Unit µs/V ms/V µs/V Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions. Table 23. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) VBOR0(2) Parameter Reset temporization after BOR0 is detected Brown-out reset threshold 0 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 VDD rising DS12469 Rev 8 V 79/192 164 Electrical characteristics STM32L412xx Table 23. Embedded reset and power control block characteristics (continued) Symbol Min Typ Max Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Vhyst_BOR_PVD 80/192 Conditions(1) Parameter Unit V V V V V V V V V V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and PVD consumption from VDD - - 1.1 1.6 µA IDD (3) (BOR_PVD)(2) BOR (except BOR0) and PVD average consumption from VDD with ENULP = 1 - - 55 1000 nA VPVM1 VDDUSB peripheral voltage monitoring - 1.18 1.22 1.26 V VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 DS12469 Rev 8 V STM32L412xx Electrical characteristics Table 23. Embedded reset and power control block characteristics (continued) Symbol VPVM4 Parameter VDDA peripheral voltage monitoring Conditions(1) Min Typ Max Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 Unit V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV PVM1 consumption from VDD - - 0.2 - µA - - 2 - µA IDD (PVM1) (2) IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS12469 Rev 8 81/192 164 Electrical characteristics 6.3.4 STM32L412xx Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs - - 12.5 20(2) µA VREFINT buffer consumption from VDD when converted by IDD(VREFINTBUF) ADC ∆VREFINT TCoeff Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C ppm ppm/V ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) 24 25 26 49 50 51 74 75 76 VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage - 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 82/192 DS12469 Rev 8 % VREFINT STM32L412xx Electrical characteristics Figure 20. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 DS12469 Rev 8 83/192 164 Electrical characteristics 6.3.5 STM32L412xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 19: Current consumption measurement scheme with and without external SMPS power supply. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0394 reference manual). • When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 25 to Table 48 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. 84/192 DS12469 Rev 8 running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol Parameter - Voltage scaling DS12469 Rev 8 85 °C 2.20 2.25 2.30 2.40 2.60 1.60 1.40 1.45 1.50 1.60 1.80 0.855 1.00 0.76 0.78 0.84 0.96 1.25 0.475 0.555 0.710 0.45 0.50 0.55 0.70 0.90 0.28 0.325 0.400 0.555 0.30 0.30 0.40 0.50 0.80 0.190 0.205 0.250 0.325 0.480 0.20 0.25 0.30 0.44 0.70 100 kHz 0.120 0.135 0.180 0.255 0.410 0.15 0.20 0.25 0.40 0.60 80 MHz 7.30 7.35 7.40 7.55 7.70 7.75 7.80 7.80 7.90 8.10 72 MHz 6.60 6.65 6.70 6.80 7.00 7.00 7.00 7.10 7.20 7.40 64 MHz 5.90 5.90 6.00 6.10 6.30 6.25 6.30 6.35 6.40 6.65 Range 1 48 MHz 4.40 4.40 4.50 4.60 4.80 4.70 4.75 4.80 4.90 5.10 32 MHz 3.00 3.00 3.05 3.15 3.35 3.20 3.25 3.30 3.40 3.60 24 MHz 2.30 2.30 2.35 2.45 2.65 2.40 2.40 2.50 2.60 2.90 16 MHz 1.55 1.60 1.65 1.75 1.90 1.70 1.75 1.80 1.90 2.20 2 MHz 190 205 255 335 505 235 230 315 455 725 1 MHz 110 120 165 250 415 135 145 230 370 645 400 kHz 55.0 65.5 115 195 360 75.0 90.5 180 325 590 100 kHz 26.0 40.0 87.5 170 335 45.0 65.5 160 290 550 fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI Low-power all peripherals disable run mode 25 °C 55 °C 85 °C 26 MHz 2.05 2.10 2.10 2.20 2.35 16 MHz 1.30 1.35 1.40 1.45 8 MHz 0.715 0.730 0.780 4 MHz 0.415 0.430 2 MHz 0.265 1 MHz fHCLK 1. Guaranteed by characterization results, unless otherwise specified. 105 °C 125 °C 25 °C 105 °C 125 °C mA µA 85/192 Electrical characteristics IDD_ALL (LPRun) Unit 55 °C Range 2 IDD_ALL (Run) MAX(1) TYP STM32L412xx Table 25. Current consumption in Run and Low-power run modes, code with data processing Conditions(1) Symbol Unit - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS12469 Rev 8 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 2.62 2.64 2.66 2.71 2.77 72 MHz 2.37 2.39 2.41 2.44 2.52 64 MHz 2.12 2.12 2.16 2.19 2.26 48 MHz 1.58 1.58 1.62 1.65 1.73 32 MHz 1.08 1.08 1.10 1.13 1.20 24 MHz 0.83 0.83 0.84 0.88 0.95 16 MHz 0.56 0.58 0.59 0.63 0.68 8 MHz 0.26 0.26 0.28 0.31 0.36 4 MHz 0.15 0.15 0.17 0.20 0.26 2 MHz 9.53 0.10 0.12 0.14 0.20 1 MHz 0.07 0.07 0.09 0.12 0.17 100 kHz 0.01 0.01 0.03 0.06 0.12 Electrical characteristics 86/192 Table 26. Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L412xx running from Flash, ART disable Conditions Symbol Parameter - Voltage scaling Unit 25 °C 55 °C 85 °C 2.40 2.45 2.50 2.55 16 MHz 1.70 1.75 1.80 1.85 2.05 1.85 1.90 1.95 2.05 2.30 8 MHz 0.970 0.985 1.05 1.10 1.25 1.05 1.10 1.15 1.25 1.50 4 MHz 0.570 0.585 0.630 0.710 0.865 0.61 0.63 0.70 0.80 1.10 fHCLK 26 MHz Range 2 IDD_ALL (Run) DS12469 Rev 8 IDD_ALL (LPRun) MAX(1) TYP 105 °C 125 °C 25 °C 2.75 2.60 55 °C 85 °C 2.65 2.70 105 °C 125 °C 2.80 3.00 2 MHz 0.340 0.355 0.400 0.475 0.635 0.40 0.40 0.50 0.60 0.80 1 MHz 0.230 0.240 0.285 0.365 0.52 0.25 0.30 0.34 0.50 0.70 100 kHz 0.125 0.140 0.185 0.260 0.415 0.14 0.20 0.25 0.40 0.60 80 MHz 7.65 7.70 7.85 8.00 8.20 8.20 8.30 8.40 8.50 8.80 72 MHz 6.95 6.95 7.05 7.15 7.35 7.40 7.45 7.50 7.60 7.80 64 MHz 6.90 6.95 7.05 7.20 7.40 7.40 7.45 7.50 7.60 7.80 Range 1 48 MHz 5.85 5.90 6.00 6.15 6.35 6.30 6.35 6.50 6.65 6.90 32 MHz 4.20 4.20 4.30 4.45 4.65 4.50 4.55 4.70 4.80 5.10 24 MHz 3.15 3.20 3.25 3.35 3.55 3.40 3.40 3.50 3.60 3.90 16 MHz 2.25 2.30 2.35 2.50 2.65 2.50 2.50 2.60 2.70 3.00 2 MHz 275 290 340 425 590 325 360 425 565 840 1 MHz 155 165 210 295 460 185 195 275 420 690 400 kHz 69.0 83.0 130 215 280 90.5 108 195 340 600 100 kHz 32.0 45.5 92.0 175 340 48.0 69 155 300 570 fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI Low-power all peripherals disable run mA µA 87/192 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L412xx Table 27. Current consumption in Run and Low-power run modes, code with data processing Conditions(1) Symbol - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS12469 Rev 8 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 2.75 2.77 2.82 2.88 2.95 72 MHz 2.50 2.50 2.53 2.57 2.64 64 MHz 2.48 2.50 2.53 2.59 2.66 48 MHz 2.10 2.12 2.16 2.21 2.28 32 MHz 1.51 1.51 1.55 1.60 1.67 24 MHz 1.13 1.15 1.17 1.20 1.28 16 MHz 0.81 0.83 0.84 0.90 0.95 8 MHz 0.35 0.35 0.38 0.40 0.45 4 MHz 0.20 0.21 0.23 0.26 0.31 2 MHz 12.22 0.13 0.14 0.17 0.23 1 MHz 0.08 0.09 0.10 0.13 0.19 100 kHz 0.01 0.02 0.03 0.06 0.12 Uni t Electrical characteristics 88/192 Table 28. Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L412xx Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Run) Supply current in Run mode DS12469 Rev 8 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 IDD_ALL (LPRun) Supply current in low-power run mode fHCLK = fMSI all peripherals disable FLASH in power-down MAX(1) TYP fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 26 MHz 2.00 2.05 2.10 2.15 2.35 2.20 2.20 2.25 2.35 2.55 16 MHz 1.30 1.30 1.35 1.45 1.60 1.40 1.45 1.45 1.55 1.80 8 MHz 0.705 0.720 0.765 0.845 1.00 0.75 0.77 0.83 0.94 1.20 4 MHz 0.410 0.425 0.470 0.550 0.700 0.44 0.46 0.52 0.64 0.90 2 MHz 0.265 0.275 0.320 0.395 0.555 0.28 0.30 0.37 0.49 0.75 1 MHz 0.190 0.200 0.245 0.325 0.475 0.21 0.22 0.29 0.42 0.67 100 kHz 0.120 0.135 0.180 0.255 0.410 0.14 0.15 0.23 0.35 0.61 80 MHz 7.15 7.20 7.25 7.45 7.55 7.65 7.65 7.75 7.75 8.00 72 MHz 6.45 6.50 6.55 6.75 6.85 6.90 6.95 7.00 7.05 7.25 64 MHz 5.75 5.80 5.85 6.05 6.15 6.15 6.20 6.25 6.30 6.50 48 MHz 4.20 4.35 4.40 4.50 7.70 4.65 4.65 4.70 4.80 5.00 32 MHz 2.95 2.95 3.00 3.10 3.30 3.15 3.15 3.20 3.30 3.55 24 MHz 2.25 2.25 2.30 2.40 2.60 2.40 2.40 2.50 2.60 2.85 16 MHz 1.55 1.55 1.60 1.70 1.85 1.65 1.70 1.75 1.85 2.10 2 MHz 180 190 240 320 485 215 225 300 450 720 1 MHz 90.5 110 155 235 400 120 135 220 360 640 400 kHz 40.5 56.0 105 185 350 60.0 76.5 165 315 565 100 kHz 17.5 32.0 78.5 160 325 33.5 53.5 140 285 555 mA µA 89/192 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. Unit STM32L412xx Table 29. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 Conditions(1) Symbol TYP Parameter Unit - fHCLK = fHSE up to 48MHz included, bypass mode IDD_ALL(Run) Supply current in Run mode PLL ON above 48 MHz all peripherals disable DS12469 Rev 8 25 °C 55 °C 85 °C 80 MHz 2.57 2.59 2.61 2.68 2.71 72 MHz 2.32 2.34 2.35 2.43 2.46 64 MHz 2.07 2.08 2.10 2.17 2.21 48 MHz 1.55 1.56 1.58 1.62 1.69 32 MHz 1.06 1.06 1.08 1.11 1.19 24 MHz 0.81 0.81 0.83 0.86 0.93 16 MHz 0.56 0.56 0.58 0.61 0.67 8 MHz 0.25 0.26 0.28 0.30 0.36 4 MHz 0.15 0.15 0.17 0.20 0.25 2 MHz 9.53 0.10 0.12 0.15 0.20 1 MHz 0.07 0.07 0.09 0.14 0.17 100 kHz 0.01 0.01 0.03 0.06 0.12 fHCLK 105 °C 125 °C Electrical characteristics 90/192 Table 30. Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L412xx STM32L412xx Electrical characteristics Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Parameter Supply current in Run mode Range 2 fHCLK = 26 MHz IDD_ALL (Run) fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Code 25 °C Reduced code(1) 2.05 79 Coremark 2.30 88 Dhrystone 2.1 2.35 Fibonacci 2.25 87 1.95 75 Reduced code 7.30 91 Coremark 8.15 102 Dhrystone 2.1 8.35 Fibonacci 8.10 101 7.20 90 Reduced code 190 95 Coremark 205 103 Dhrystone 2.1 220 Fibonacci 205 103 While(1) 225 113 While(1) (1) Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run Unit 25 °C While(1) (1) IDD_ALL (LPRun) TYP Unit Voltage scaling - Range 1 fHCLK = 80 MHz Symbol TYP mA mA µA 90 104 110 µA/MHz µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. Table 32. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz IDD_ALL (Run) Parameter fHCLK = 80 MHz Symbol TYP Code 25 °C Reduced code(2) 0.88 TYP Unit 25 °C 34 Coremark 0.99 38 Dhrystone 2.1 1.01 39 Fibonacci 0.97 37 While(1) 0.84 Reduced code(2) 3.15 mA 32 39 Coremark 3.52 44 Dhrystone 2.1 3.60 45 Fibonacci 3.49 44 While(1) 3.11 39 DS12469 Rev 8 Unit µA/MHz 91/192 164 Electrical characteristics STM32L412xx 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. Table 33. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.00 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 0.73 28 Coremark 0.82 32 Dhrystone 2.1 0.84 Fibonacci 0.80 31 While(1) 0.70 27 mA Unit 25 °C 32 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. 92/192 DS12469 Rev 8 STM32L412xx Electrical characteristics Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable Conditions Parameter IDD_ALL (Run) IDD_ALL (LPRun) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit Voltage scaling - Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Unit 25 °C Reduced code(1) 2.40 92 Coremark 2.15 83 Dhrystone 2.1 2.20 mA 85 Fibonacci 2.05 79 While(1) 1.90 73 (1) Reduced code 7.65 96 Coremark 6.95 87 Dhrystone 2.1 7.00 Fibonacci 6.60 While(1) 6.85 86 Reduced code(1) 275 138 mA 88 µA/MHz µA/MHz 83 Coremark 300 Dhrystone 2.1 315 150 Fibonacci 305 153 While(1) 385 193 µA 158 µA/MHz 1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. Table 35. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.04 40 Coremark 0.93 36 Dhrystone 2.1 0.95 37 Fibonacci 0.88 34 While(1) 0.82 Reduced code(2) 3.30 mA 25 °C 32 41 Coremark 3.00 37 Dhrystone 2.1 3.02 38 Fibonacci 2.85 36 While(1) 2.95 37 Unit µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. DS12469 Rev 8 93/192 164 Electrical characteristics STM32L412xx Table 36. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode TYP Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 0.86 TYP Unit 25 °C Unit 33 Coremark 0.77 Dhrystone 2.1 0.78 29 Fibonacci 0.73 28 While(1) 0.68 26 mA 30 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. Table 37. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions Parameter - IDD_ALL (Run) IDD_ALL (LPRun) fHCLK = fHSE up to 48 MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit Code 25 °C Unit 25 °C Reduced code(1) 2.00 77 Coremark 2.00 77 Dhrystone 2.1 2.05 mA 79 Fibonacci 2.00 77 While(1) 1.85 71 Reduced code(1) 7.15 89 Coremark 7.00 88 Dhrystone 2.1 7.15 Fibonacci 7.10 89 While(1) 6.60 83 Reduced code(1) 180 90 mA 89 Coremark 180 Dhrystone 2.1 185 Fibonacci 170 85 While(1) 170 85 1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. 94/192 TYP DS12469 Rev 8 µA/MHz µA/MHz 90 µA 93 µA/MHz STM32L412xx Electrical characteristics Table 38. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode TYP Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 0.86 TYP Unit 25 °C Unit 33 Coremark 0.86 33 Dhrystone 2.1 0.88 34 Fibonacci 0.86 33 While(1) 0.80 Reduced code(2) 3.08 mA 31 39 Coremark 3.02 38 Dhrystone 2.1 3.08 39 Fibonacci 3.06 38 While(1) 2.85 36 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. Table 39. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 0.71 TYP Unit 25 °C Unit 27 Coremark 0.71 Dhrystone 2.1 0.73 27 Fibonacci 0.71 27 While(1) 0.66 25 mA 28 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V 2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29. DS12469 Rev 8 95/192 164 Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Sleep) Supply current in sleep mode, DS12469 Rev 8 fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 26 MHz 0.535 0.550 0.600 0.680 0.835 0.58 0.60 0.66 0.79 1.05 16 MHz 0.375 0.390 0.435 0.515 0.670 0.41 0.43 0.50 0.62 0.88 8 MHz 0.245 0.260 0.305 0.385 0.540 0.27 0.29 0.36 0.49 0.74 4 MHz 0.180 0.195 0.240 0.315 0.470 0.20 0.22 0.29 0.42 0.67 2 MHz 0.150 0.160 0.205 0.285 0.435 0.17 0.18 0.25 0.38 0.63 1 MHz 0.130 0.145 0.190 0.265 0.420 0.15 0.16 0.24 0.36 0.62 100 kHz 0.115 0.130 0.175 0.250 0.405 0.13 0.15 0.22 0.35 0.60 80 MHz 1.65 1.70 1.75 1.85 2.00 1.80 1.80 1.85 1.95 2.25 72 MHz 1.50 1.55 1.60 1.70 1.85 1.60 1.65 1.70 1.80 2.10 64 MHz 1.35 1.40 1.45 1.55 1.70 1.45 1.50 1.55 1.65 1.95 1.00 Range 1 48 MHz IDD_ALL (LPSleep) Supply current in =f f low-power HCLK MSI all peripherals disable sleep mode MAX(1) TYP 105 °C 125 °C 1.05 1.10 1.2 1.35 1.10 1.15 1.20 1.35 1.65 32 MHz 0.725 0.740 0.795 0.885 1.05 0.78 0.80 0.87 1.05 1.35 24 MHz 0.575 0.595 0.650 0.740 0.910 0.62 0.64 0.72 0.86 1.15 16 MHz 0.425 0.440 0.495 0.585 0.760 0.47 0.48 0.56 0.71 1.00 2 MHz 52.5 66.5 115 195 360 71.0 91.5 175 315 600 1 MHz 37.0 51.5 97.5 180 345 55.0 73.0 165 295 575 400 kHz 25.5 39.0 85.0 170 330 41.0 63.0 150 280 565 100 kHz 18.5 33.5 80.5 165 325 36.0 57.5 145 280 560 Electrical characteristics 96/192 Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L412xx Conditions(1) Symbol TYP Parameter Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 0.59 0.61 0.63 0.67 0.72 72 MHz 0.54 0.56 0.58 0.61 0.67 64 MHz 0.49 0.50 0.52 0.56 0.61 48 MHz 0.36 0.38 0.40 0.43 0.49 32 MHz 0.26 0.27 0.29 0.32 0.38 24 MHz 0.21 0.21 0.23 0.27 0.33 16 MHz 0.15 0.16 0.18 0.21 0.27 8 MHz 0.09 0.09 0.11 0.14 0.19 4 MHz 0.06 0.07 0.09 0.11 0.17 2 MHz 5.39 0.06 0.07 0.10 0.15 1 MHz 0.05 0.05 0.07 0.10 0.15 100 kHz 0.01 0.01 0.03 0.06 0.12 - IDD_ALL(Sleep) Supply current in sleep mode, fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable STM32L412xx Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) mA DS12469 Rev 8 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V Table 42. Current consumption in Low-power sleep modes, Flash in power-down Conditions Symbol Parameter - fHCLK = fMSI all peripherals disable Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 2 MHz 50 60 105 185 350 63 83 170 300 585 1 MHz 35 45 89.0 170 335 46 65 150 285 570 400 kHz 20 32 76.5 155 320 32 51 135 270 560 100 kHz 15 25 71.5 150 315 25 46 135 270 555 1. Guaranteed by characterization results, unless otherwise specified. µA 97/192 Electrical characteristics IDD_ALL (LPSleep) Supply current in low-power sleep mode Voltage scaling MAX(1) TYP Symbol Conditions Parameter - IDD_ALL (Stop 2) Supply current in Stop 2 mode, RTC disabled ENULP = 1 DS12469 Rev 8 RTC clocked by LSI IDD_ALL (Stop 2 with RTC) Supply current in RTC clocked by LSI Stop 2 mode, ENULP = 1 RTC enabled LPCAL = 1 RTC clocked by LSI ENULP = 1 LPCAL = 1 LSIPREDIV = 1 MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 0.77 2.35 8.60 20.5 46.0 2.0 5.6 21.5 51.0 115 2.4 V 0.78 2.35 8.75 21.0 3V 0.79 2.40 9.00 21.5 47.0 2.1 5.8 22.0 52.5 120 49.0 2.1 5.9 22.5 54.0 125 3.6 V 0.84 2.55 9.40 22.5 51.5 2.3 6.1 23.0 56.0 130 1.8 V 0.72 2.35 9.35 21.0 46.5 - - - - - 2.4 V 0.74 2.35 9.65 22.0 48.0 - - - - - 3V 0.75 2.65 10.0 22.5 50.0 - - - - - 3.6 V 0.79 2.90 10.5 24.0 52.5 - - - - - 1.8 V 1.05 2.70 9.00 21.0 46.0 2.5 6.2 22.0 51.5 120 2.4 V 1.10 2.90 9.30 21.5 47.5 2.8 6.4 22.5 53.0 120 3V 1.20 3.10 9.65 22.5 49.5 3.0 6.8 23.0 54.5 125 3.6 V 1.30 3.35 10.0 23.5 52.0 3.3 7.2 24.5 57.0 130 1.8 V 1.00 2.65 9.55 21.5 46.5 - - - - - 2.4 V 1.05 2.90 10.0 22.0 48.5 - - - - - 3V 1.10 3.15 10.5 23.0 50.5 - - - - - 3.6 V 1.20 3.55 11.5 24.5 53.0 - - - - - 1.8 V 0.86 2.45 9.35 21.5 46.5 - - - - - 2.4 V 0.88 2.60 9.70 22.0 48.0 - - - - - 3V 0.93 2.75 10.0 23.0 50.0 - - - - - 3.6 V 0.98 3.05 11.0 24.0 52.5 - - - - - Unit µA Electrical characteristics 98/192 Table 43. Current consumption in Stop 2 mode µA STM32L412xx Symbol Parameter Conditions VDD 25 °C 55 °C 85 °C 1.8 V 1.35 2.85 9.15 2.4 V 1.60 3.15 9.60 22.0 48.0 - - - - - 3V 2.00 3.85 11.0 24.0 51.5 - - - - - 3.6 V 3.90 6.60 15.0 29.5 58.5 - - - - - 1.8 V RTC clocked by LSE bypassed at 32768 Hz, 2.4 V ENULP = 1, 3V Supply current in LPCAL = 1 3.6 V Stop 2 mode, 1.8 V RTC enabled RTC clocked by LSE 2.4 V quartz in low drive 3V mode 3.6 V 1.20 2.80 9.70 21.5 46.5 - - - - - 1.35 3.10 10.5 22.5 48.5 - - - - - 1.80 3.90 11.5 25.0 52.5 - - - - - 3.65 6.75 16.0 30.5 59.5 - - - - - 1.20 2.65 8.85 20.5 47.5 - - - - - - RTC clocked by LSE bypassed at 32768 Hz IDD_ALL (Stop 2 with RTC) MAX(1) TYP 21.0 46.0 - 55 °C 85 °C - - 105 °C 125 °C - DS12469 Rev 8 2.75 9.10 21.0 49.0 - - - - - 2.90 9.45 22.0 51.0 - - - - - 1.50 3.10 9.95 23.0 53.0 - - - - - 1.8 V 1.00 2.55 9.50 21.0 48.0 - - - - - 2.4 V 1.10 2.75 9.90 22.0 49.5 - - - - - 3V 1.15 3.00 10.5 23.0 52.0 - - - - - 3.6 V 1.25 3.25 11.0 25.0 54.5 - - - - - Wakeup clock is MSI = 48 MHz, voltage Range 1. See (3). 3V 185 - - - - - - - - - Wakeup clock is MSI = 4 MHz, voltage Range 2. See (3). 3V 155 - - - - - - - - - Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (3). 3V 152 - - - - - - - - - µA mA Electrical characteristics 99/192 1.25 1. Guaranteed by characterization results, unless otherwise specified. Unit - 1.35 RTC clocked by LSE quartz(2) in low drive mode, ENULP = 1, LPCAL = 1 Supply current IDD_ALL during wakeup (wakeup from from Stop 2 Stop2) mode 105 °C 125 °C 25 °C STM32L412xx Table 43. Current consumption in Stop 2 mode (continued) 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings. Electrical characteristics 100/192 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. DS12469 Rev 8 STM32L412xx Symbol Parameter IDD_ALL (Stop 1) Supply current in Stop 1 mode, RTC disabled Conditions - - - RTC clocked by LSI DS12469 Rev 8 Supply current IDD_ALL in stop 1 RTC clocked by LSE (Stop 1 with mode, bypassed at 32768 Hz RTC) RTC enabled RTC clocked by LSE in low drive mode quartz(2) Wakeup clock MSI = 48 MHz, voltage Range 1. See (3). VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 3.95 13.0 47.5 110 230 7.40 24.5 87.0 190 395 2.4 V 3.95 13.0 48.0 110 230 7.50 24.5 86.0 190 395 3V 4.00 13.5 48.0 110 235 7.30 24.5 87.0 195 400 3.6 V 4.10 13.5 48.5 110 240 7.85 25.0 90.0 195 405 1.8 V 4.40 13.5 48.0 110 230 8.05 24.5 86.5 190 395 2.4 V 4.60 14.0 48.5 110 235 8.10 25.0 90.0 195 395 3V 4.75 14.0 48.5 110 235 8.20 25.5 89.0 195 400 3.6 V 5.05 14.5 49.5 115 240 8.55 27.0 89.5 195 405 1.8 V 4.50 13.5 48.5 110 230 11.5 26.5 86.0 190 395 2.4 V 4.70 14.0 49.0 110 230 29.0 31.5 90.0 190 395 3V 5.35 14.5 50.0 115 240 36.0 31.5 87.5 195 400 3.6 V 7.20 17.5 54.5 120 245 26.0 28.0 88.0 195 405 1.8 V 4.25 13.5 47.5 110 - - - - - - 2.4 V 4.35 13.5 48.0 110 - - - - - - 3V 4.40 13.5 48.0 110 - - - - - - 3.6 V 4.50 14.0 49.0 125 - - - - - - 3V 1.15 - - - - - - - - - 3V 1.25 - - - - - - - - - 3V 1.20 - - - - - - - - - 1. Guaranteed by characterization results, unless otherwise specified. 101/192 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings. Unit µA µA mA Electrical characteristics Supply current Wakeup clock MSI = 4 MHz, IDD_ALL voltage Range 2. during (wakeup wakeup from See (3). from Stop1) Stop 1 Wakeup clock HSI16 = 16 MHz, voltage Range 1. See (3). MAX(1) TYP STM32L412xx Table 44. Current consumption in Stop 1 mode Symbol Parameter IDD_ALL (Stop 0) Supply current in Stop 0 mode, RTC disabled Conditions MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 110 125 165 240 380 130 145 215 340 585 2.4 V 110 125 170 240 385 130 145 215 340 585 3V 115 125 170 245 385 130 145 220 345 590 3.6 V 115 130 175 250 390 135 150 220 345 595 1. Guaranteed by characterization results, unless otherwise specified. Unit µA Electrical characteristics 102/192 Table 45. Current consumption in Stop 0 DS12469 Rev 8 STM32L412xx Symbol Parameter Conditions - No independent watchdog IDD_ALL (Standby) DS12469 Rev 8 Supply current in Standby mode (backup registers retained), RTC disabled No independent watchdog ENULP = 1 With independent watchdog With independent watchdog ENULP = 1 MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 95 255 1150 3200 8350 115 405 2750 7150 19500 2.4 V 105 290 1300 3600 9500 175 540 3250 8350 23000 3V 120 354 1550 4350 11500 215 650 3750 9600 26000 3.6 V 150 410 1850 5050 13000 280 835 4450 11500 29500 1.8 V 32 225 1400 3850 9000 115 405 2750 7250 19500 2.4 V 46 315 1800 4500 10500 175 540 3250 8350 23000 3V 66 430 2400 5450 12500 215 650 3750 9600 26000 3.6 V 115 570 3050 6350 14500 280 835 4450 11500 29500 1.8 V 295 450 1300 3250 8250 - - - - - 2.4 V 350 530 1500 3750 9450 - - - - - 3V 415 635 1800 4450 11500 - - - - - 3.6 V 505 775 2200 5350 13500 - - - - - 1.8 V 230 415 1450 3900 8850 - - - - - 2.4 V 290 540 1950 4600 10550 - - - - - 3V 365 710 2550 5500 12500 - - - - - 3.6 V 460 915 3300 6600 14500 - - - - - Unit STM32L412xx Table 46. Current consumption in Standby mode nA Electrical characteristics 103/192 Symbol Parameter Conditions - RTC clocked by LSI, no independent watchdog IDD_ALL (Standby with RTC) DS12469 Rev 8 Supply current in Standby mode (backup registers retained), RTC enabled RTC clocked by LSI, no independent watchdog ENULP = 1 RTC clocked by LSI, with independent watchdog RTC clocked by LSI, with independent watchdog ENULP = 1 MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 1.8 V 480 635 1500 3450 2.4 V 615 800 1800 3V 775 995 2150 3.6 V 970 1250 1.8 V 330 2.4 V 3V 55 °C 85 °C 8400 560 900 3180 4050 9700 770 1200 4850 11500 975 1450 2650 5850 14000 1250 515 1600 4000 9000 435 690 2100 4750 565 915 2750 5750 3.6 V 725 1200 3600 1.8 V 530 680 2.4 V 675 3V 850 3.6 V 1050 1.8 V 105 °C 125 °C 7500 19500 3850 880 23000 4450 10500 26000 1850 5300 12000 29500 560 900 3180 7500 19500 10500 770 1200 3850 8800 23000 12500 975 1450 4450 10500 26000 6900 1500 1250 1850 5300 12000 29500 1550 3500 8450 - - - - - 855 1850 4100 9850 - - - - - 1050 2250 4900 11500 - - - - - 1350 2750 4900 11500 - - - - - 370 560 1600 4050 9050 - - - - - 2.4 V 495 755 2150 4800 10500 - - - - - 3V 645 985 2850 5800 12500 - - - - - 3.6 V 825 1300 3700 6950 15000 - - - - - Unit Electrical characteristics 104/192 Table 46. Current consumption in Standby mode (continued) nA STM32L412xx Symbol Parameter Conditions - DS12469 Rev 8 IDD_ALL (SRAM2)(3) 85 °C 105 °C 125 °C 25 °C 640 1500 3450 2.4 V 615 800 1800 3V 775 995 2150 3.6 V 960 1250 1.8 V 330 2.4 V 3V 105 °C 125 °C - - - 4000 9300 - - - - - 4800 11000 - - - - - 2650 5800 13000 - - - - - 510 1600 4000 8800 - - - - - 435 695 2100 4750 10000 - - - - - 565 910 2750 5700 12000 - - - - - 3.6 V 730 1200 3600 6900 14500 - - - - - 1.8 V 415 575 1450 3400 - - - - - - 2.4 V 485 670 1650 3900 - - - - - - 3V 550 800 1950 4600 - - - - - - 3.6 V 690 985 2400 - - - - - - - 1.8 V RTC clocked by LSE (2) in low drive mode 2.4 V quartz ENULP = 1 3V LPCAL = 1 3.6 V 245 450 1600 4000 - - - - - - 290 565 2050 4650 - - - - - - 355 705 2650 5500 - - - - - - 450 915 3400 - - - - - - - 1.8 V 100 230 750 1600 3500 - - - - - 2.4 V 100 230 750 1650 3500 - - - - - 3V 100 235 750 1700 3500 - - - - - 3.6 V 100 240 750 1700 3500 - - - - - 3V 1.25 - - - - - - - - - Wakeup clock is MSI = 4 MHz. See (4). 480 85 °C - - 1.8 V 55 °C Unit nA nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 105/192 3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby + RTC) + IDD_ALL(SRAM2). 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings. Electrical characteristics IDD_ALL (wakeup from Standby) 25 °C 55 °C - RTC clocked by LSE Supply current bypassed at 32768 Hz in Standby ENULP = 1 mode (backup registers retained), RTC enabled RTC clocked by LSE (cont.) quartz (2) in low drive mode Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode VDD 8100 RTC clocked by LSE bypassed at 32768 Hz IDD_ALL (Standby with RTC) (cont.) MAX(1) TYP STM32L412xx Table 46. Current consumption in Standby mode (continued) Symbol IDD_ALL (Shutdown) Parameter Supply current in Shutdown mode (backup registers retained) RTC disabled Conditions - - RTC clocked by LSE bypassed at 32768 Hz DS12469 Rev 8 IDD_ALL (Shutdown with RTC) Supply current in Shutdown mode (backup registers retained) RTC enabled RTC clocked by LSE bypassed at 32768 Hz ENULP = 1 RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE quartz (2) in low drive mode ENULP = 1 Wakeup clock is MSI = 4 MHz. See (3). VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 16 100 600 1850 5450 56 310 1200 3350 9550 2.4 V 22 120 705 2150 6250 65 365 1350 3800 11000 3V 31 155 870 2650 7700 97 600 1700 4750 12500 3.6 V 52 220 1150 3350 9350 95 440 1850 5050 14500 1.8 V 210 300 820 2050 5750 - - - - - 2.4 V 315 445 1100 2650 6950 - - - - - 3V 625 1000 2200 44000 10000 - - - - - 3.6 V 820 1650 3500 5600 14500 - - - - - 1.8 V 210 300 820 2050 5750 - - - - - 2.4 V 315 445 1100 2650 6950 - - - - - 3V 625 1000 2200 44000 10000 - - - - - 3.6 V 820 1650 3500 5600 14500 - - - - - 1.8 V 325 425 930 2200 - - - - - - 2.4 V 400 515 1100 2550 - - - - - - 3V 475 630 1350 3100 - - - - - - 3.6 V 595 795 1750 - - - - - - - 1.8 V 230 325 830 2050 - - - - - - 2.4 V 270 380 975 2400 - - - - - - 3V 320 455 1200 1950 - - - - - - 3.6 V 400 575 1500 - - - - - - - 3V 0.78 - - - - - - - - - 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Unit nA nA mA STM32L412xx Supply current IDD_ALL during wakeup (wakeup from from Shutdown Shutdown) mode MAX(1) TYP Electrical characteristics 106/192 Table 47. Current consumption in Shutdown mode Table 48. Current consumption in VBAT mode Symbol Parameter Conditions - RTC disabled IDD_VBAT (VBAT) Backup domain supply current RTC enabled and clocked by LSE quartz(2) MAX(1) TYP VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 2 12 66 195 540 - - - - - 2.4 V 3 14 73 215 600 - - - - - 3V 5 16 92 265 730 - - - - - 3.6 V 6 30 161 460 1250 - - - - - 1.8 V 300 455 460 990 1750 - - - - - 2.4 V 380 515 575 1050 1950 - - - - - 3V 445 550 595 1200 2550 - - - - - 3.6 V 495 630 820 1500 2950 - - - - - Unit STM32L412xx 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings. nA DS12469 Rev 8 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Electrical characteristics 107/192 Electrical characteristics STM32L412xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 69: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 49: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 108/192 DS12469 Rev 8 STM32L412xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 49. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 18: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 49. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 49. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus Matrix(1) 3.0 2.9 2.8 ADC clock domain 2.2 1.8 1.8 CRC 0.5 0.3 0.2 DMA1 1.3 1.2 1.1 DMA2 1.3 1.2 1.1 5.9 4.9 5.6 GPIOA 1.6 1.5 1.3 GPIOB(2)) 1.5 1.4 1.3 GPIOC(2) 1.7 1.6 1.5 (2) GPIOH 0.6 0.5 0.6 QSPI 6.9 7.0 5.6 RNG independent clock domain 2.2 NA NA RNG clock domain 0.5 NA NA SRAM1 0.7 0.6 0.7 SRAM2 0.9 0.7 0.8 TSC 1.5 1.3 1.3 21.9 19.2 20.5 0.8 0.6 0.8 RTCA 1.7 1.1 2.1 CRS 0.3 0.3 0.5 USB FS independent clock domain 2.8 NA NA USB FS clock domain 2.2 NA NA Peripheral FLASH (2) AHB All AHB Peripherals AHB to APB1 APB1 bridge(3) DS12469 Rev 8 Unit µA/MHz 109/192 164 Electrical characteristics STM32L412xx Table 49. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep I2C1 independent clock domain 3.4 2.8 3.3 I2C1 clock domain 1.0 0.9 0.9 I2C2 independent clock domain 3.4 2.8 3.3 I2C2 clock domain 1.0 0.9 0.9 I2C3 independent clock domain 2.8 2.3 2.4 I2C3 clock domain 0.9 0.4 0.7 LPUART1 independent clock domain 1.8 1.6 1.7 LPUART1 clock domain 0.6 0.6 1.7 LPTIM1 independent clock domain 2.8 2.3 2.7 LPTIM1 clock domain 0.8 0.4 0.7 LPTIM2 independent clock domain 2.9 2.6 3.8 LPTIM2 clock domain 0.8 0.7 0.8 OPAMP 0.4 0.2 0.4 PWR 0.4 0.1 0.4 SPI2 1.7 1.5 1.5 SPI3 1.7 1.4 1.5 TIM2 6.2 5.0 5.8 TIM6 1.0 0.6 0.9 USART2 independent clock domain 4.0 3.5 3.7 USART2 clock domain 1.3 0.8 1.1 USART3 independent clock domain 4.2 3.4 4.1 USART3 clock domain 1.5 1.1 1.3 WWDG 0.5 0.5 0.5 All APB1 on 41.4 28.5 38.9 Peripheral APB1 110/192 DS12469 Rev 8 Unit µA/MHz STM32L412xx Electrical characteristics Table 49. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep AHB to APB2(4) 1.0 0.9 0.9 FW 0.2 0.2 0.2 SPI1 1.7 1.6 1.7 SYSCFG/COMP 0.6 0.5 0.6 TIM1 8.1 6.4 7.6 TIM15 3.7 3.0 3.4 TIM16 2.6 2.1 2.5 USART1 independent clock domain 4.1 4.1 4.4 USART1 clock domain 1.5 1.2 1.6 All APB2 on 19.2 16.1 17.8 82.5 63.8 77.2 Peripheral APB2 ALL Unit µA/MHz 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes). 3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1. 4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2. The consumption for the peripherals when using SMPS can be found using STM32CubeMX PCC tool. 6.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 50 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 50. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Conditions Typ Max - 6 6 Wakeup time from Sleep mode to Run mode Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz DS12469 Rev 8 6 8.3 Unit Nb of CPU cycles 111/192 164 Electrical characteristics STM32L412xx Table 50. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 0 mode to Run mode in Flash Range 2 tWUSTOP0 Range 1 Wake up time from Stop 0 mode to Run mode in SRAM1 Range 2 Range 1 Wake up time from Stop 1 mode to Run in Flash Range 2 Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Run mode in SRAM1 Wake up time from Stop 1 mode to Low-power run mode in Flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 112/192 Range 2 Regulator in low-power mode (LPR=1 in PWR_CR1) Typ Max Wakeup clock MSI = 48 MHz 3.8 5.7 Wakeup clock HSI16 = 16 MHz 4.1 6.9 Wakeup clock MSI = 24 MHz 4.07 6.2 Wakeup clock HSI16 = 16 MHz 4.1 6.8 Wakeup clock MSI = 4 MHz 8.45 11.8 Wakeup clock MSI = 48 MHz 1.5 2.9 Wakeup clock HSI16 = 16 MHz 2.4 2.76 Wakeup clock MSI = 24 MHz 2.4 3.48 Wakeup clock HSI16 = 16 MHz 2.4 2.76 Wakeup clock MSI = 4 MHz 8.16 10.94 Wakeup clock MSI = 48 MHz 6.34 7.86 Wakeup clock HSI16 = 16 MHz 6.84 8.23 Wakeup clock MSI = 24 MHz 6.74 8.1 Wakeup clock HSI16 = 16 MHz 6.89 8.21 Wakeup clock MSI = 4 MHz 10.47 12.1 Wakeup clock MSI = 48 MHz 4.7 5.97 Wakeup clock HSI16 = 16 MHz 5.9 6.92 Wakeup clock MSI = 24 MHz 5.4 6.51 Wakeup clock HSI16 = 16 MHz 5.9 6.92 Wakeup clock MSI = 4 MHz 11.1 12.2 16.4 17.73 Wakeup clock MSI = 2 MHz DS12469 Rev 8 17.3 18.82 Unit µs µs STM32L412xx Electrical characteristics Table 50. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 8.02 9.24 Wakeup clock HSI16 = 16 MHz 7.66 8.95 Wakeup clock MSI = 24 MHz 8.5 9.54 Wakeup clock HSI16 = 16 MHz 7.75 8.95 Wakeup clock MSI = 4 MHz 12.06 13.16 Wakeup clock MSI = 48 MHz 5.45 6.79 Wakeup clock HSI16 = 16 MHz 6.9 7.98 Wakeup clock MSI = 24 MHz 6.3 7.36 Wakeup clock HSI16 = 16 MHz 6.9 7.9 Wakeup clock MSI = 4 MHz 13.1 13.31 Wakeup time from Standby Range 1 mode to Run mode Wakeup clock MSI = 8 MHz 12.2 18.35 Wakeup clock MSI = 4 MHz 19.14 25.8 Wakeup time from Standby Range 1 with SRAM2 to Run mode Wakeup clock MSI = 8 MHz 12.1 Wakeup clock MSI = 4 MHz 19.2 25.87 Wakeup clock MSI = 4 MHz 261.5 315.7 Range 1 Wake up time from Stop 2 mode to Run mode in Flash Range 2 tWUSTOP2 Range 1 Wake up time from Stop 2 mode to Run mode in SRAM1 tWUSTBY tWUSTBY SRAM2 tWUSHDN Wakeup time from Shutdown mode to Run mode Range 2 Range 1 18.3 Unit µs µs µs µs 1. Guaranteed by characterization results. Table 51. Regulator modes transition times(1) Symbol tWULPRUN tVOST Parameter Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Code run with MSI 24 MHz Unit µs 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. Table 52. Wakeup time using USART/LPUART(1) Symbol tWUUSART tWULPUART Parameter Conditions Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is HSI Unit µs 1. Guaranteed by design. DS12469 Rev 8 113/192 164 Electrical characteristics 6.3.7 STM32L412xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 21: High-speed external clock source AC timing diagram. Table 53. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 Unit MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 tw(HSEH) OSC_IN high or low time tw(HSEL) V ns - - 1. Guaranteed by design. Figure 21. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tw(HSEL) t THSE MS19214V2 114/192 DS12469 Rev 8 STM32L412xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 22. Table 54. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 22. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 DS12469 Rev 8 115/192 164 Electrical characteristics STM32L412xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 55. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 55. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 116/192 DS12469 Rev 8 STM32L412xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 23. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 56. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - DS12469 Rev 8 Unit nA µA/V s 117/192 164 Electrical characteristics STM32L412xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 24. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: 118/192 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS12469 Rev 8 STM32L412xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 57 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 57. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step DuCy(HSI16)(2) Duty Cycle Conditions Min Typ Max Unit 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % VDD=3.0 V, TA=30 °C - % ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA 1. Guaranteed by characterization results. 2. Guaranteed by design. DS12469 Rev 8 119/192 164 Electrical characteristics STM32L412xx Figure 25. HSI16 frequency versus temperature MHz 16.4 +2% 16.3 +1.5% 16.2 +1% 16.1 16 15.9 -1% 15.8 -1.5% 15.7 -2% 15.6 -40 -20 0 20 min 40 mean 60 80 100 120 °C max MSv39299V1 120/192 DS12469 Rev 8 STM32L412xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 58. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode fMSI ∆TEMP(MSI)(2) MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature MSI mode TA= -0 to 85 °C TA= -40 to 125 °C DS12469 Rev 8 Unit kHz MHz kHz MHz % 121/192 164 Electrical characteristics STM32L412xx Table 58. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI) (2) MSI oscillator frequency drift MSI mode over VDD (reference is 3 V) Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(6) Frequency variation in MSI mode sampling mode(3) P_USB Jitter(MSI)(6) Period jitter for USB clock(4) MT_USB Jitter(MSI)(6) Medium term jitter PLL mode for USB clock(5) Range 11 CC jitter(MSI)(6) P jitter(MSI)(6) tSU(MSI)(6) tSTAB(MSI)(6) 122/192 PLL mode Range 11 Max Unit 0.5 0.7 % 1 for next transition - - - 3.458 for paired transition - - - 3.916 for next transition - - - 2 for paired transition - - - 1 % ns ns RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - ps RMS Period jitter PLL mode Range 11 - - 50 - ps Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 0.5 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator stabilization time PLL mode Range 11 DS12469 Rev 8 us ms STM32L412xx Electrical characteristics Table 58. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock. 5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles. For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles. For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over 56 cycles. 6. Guaranteed by design. DS12469 Rev 8 123/192 164 Electrical characteristics STM32L412xx Figure 26. Typical current consumption versus MSI frequency High-speed internal 48 MHz (HSI48) RC oscillator Table 59. HSI48 oscillator characteristics(1) Symbol Parameter fHSI48 HSI48 Frequency TRIM HSI48 user trimming step USER TRIM COVERAGE HSI48 user trimming coverage DuCy(HSI48) Duty Cycle Accuracy of the HSI48 oscillator ACCHSI48_REL over temperature (factory calibrated) DVDD(HSI48) HSI48 oscillator frequency drift with VDD Conditions VDD=3.0V, TA=30°C ±32 steps VDD = 3.0 V to 3.6 V, TA = –15 to 85 °C Min Typ Max Unit - 48 - MHz - 0.11(2) 0.18(2) % ±3(3) ±3.5(3) - % 45(2) - 55(2) % - - ±3(3) % VDD = 1.65 V to 3.6 V, TA = –40 to 125 °C - - ±4.5(3) VDD = 3 V to 3.6 V - 0.025(3) 0.05(3) VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3) % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA 124/192 DS12469 Rev 8 STM32L412xx Electrical characteristics Table 59. HSI48 oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. Figure 27. HSI48 frequency versus temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 Avg 10 30 50 70 90 min 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 60. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Parameter LSI Frequency LSI oscillator startup time LSI oscillator stabilization time LSI oscillator power consumption Conditions Min Typ Max Unit VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 μs 5% of final frequency - 125 180 μs - - 110 180 nA kHz 1. Guaranteed by characterization results. 2. Guaranteed by design. DS12469 Rev 8 125/192 164 Electrical characteristics 6.3.9 STM32L412xx PLL characteristics The parameters given in Table 61 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions. Table 61. PLL characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.0968 - 26 Voltage scaling Range 1 12 - 80 Voltage scaling Range 2 12 - 26 Voltage scaling Range 1 12 - 80 Voltage scaling Range 2 12 - 26 Voltage scaling Range 1 96 - 344 Voltage scaling Range 2 96 - 128 - 15 40 - 40 - - 30 - VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 80 MHz MHz MHz MHz MHz μs ±ps 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs. 126/192 DS12469 Rev 8 μA STM32L412xx 6.3.10 Electrical characteristics Flash memory characteristics Table 62. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.95 fast programming 3.91 4.35 22.13 24.59 Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - tERASE tprog_bank tME IDD Page (2 KB) erase time one bank (512 Kbyte) programming time - Mass erase time (one or two banks) - Average consumption from VDD Maximum current (peak) ms s ms mA 1. Guaranteed by design. Table 63. Flash memory endurance and data retention Symbol NEND tRET Min(1) Unit TA = –40 to +105 °C 10 kcycles 1 kcycle(2) at TA = 85 °C 30 Parameter Endurance Data retention Conditions 1 kcycle (2) 1 kcycle (2) at TA = 105 °C 15 at TA = 125 °C 7 (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles (2) at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS12469 Rev 8 127/192 164 Electrical characteristics 6.3.11 STM32L412xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 64. They are based on the EMS levels and classes defined in application note AN1709. Table 64. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 128/192 • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) DS12469 Rev 8 STM32L412xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 65. EMI characteristics Symbol Parameter Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8 MHz/ 80 MHz SEMI Peak level 0.1 MHz to 30 MHz 3 VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz LQFP64 package 130 MHz to 1 GHz compliant with IEC 61967-2 1 GHz to 2 GHz 3 8 EMI Level 6.3.12 dBµV 4 2.5 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 66. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) T = +25 °C, conforming Electrostatic discharge voltage A to ANSI/ESDA/JEDEC (human body model) JS-001 VESD T = +25 °C, Electrostatic discharge voltage A conforming to (charge device model) ANSI/ESDA/JEDEC-002 Package Class Maximum value(1) All 2 2000 BGA64 C2a 500 All others C1 250 Unit V 1. Guaranteed by characterization results. DS12469 Rev 8 129/192 164 Electrical characteristics STM32L412xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 67. Electrical sensitivities Symbol LU 6.3.13 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 68. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 68. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Positive injection Injected current on all pins except PA4, PA5 -5 N/A(2) Injected current on PA4, PA5 pins -5 0 1. Guaranteed by characterization results. 2. Injection is not possible. 130/192 Unit Negative injection DS12469 Rev 8 mA STM32L412xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 69. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Conditions Min Typ Max Unit I/O input low level voltage 1.62 V