STM32L431xx
Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
up to 256KB Flash, 64KB SRAM, analog, audio
Datasheet - production data
Features
• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 200 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
– 8 nA Shutdown mode (5 wakeup pins)
– 28 nA Standby mode (5 wakeup pins)
– 280 nA Standby mode with RTC
– 1.0 µA Stop 2 mode, 1.28 µA Stop 2 with
RTC
– 84 µA/MHz run mode
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR) in all modes except
shutdown
– Interconnect matrix
• Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS/1.25DMIPS/MHz (Dhrystone
2.1), and DSP instructions
• Performance Benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 Coremark® (3.42 Coremark/MHz @
80 MHz)
• Energy Benchmark
– 176.7 ULPBench® score
• Clock Sources
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– Internal 48 MHz with clock recovery
May 2016
This is information on a product in full production.
LQFP100 (14x14)
LQFP64 (10x10) UFQFPN32 (5x5) UFBGA100 (7×7) WLCSP64
LQFP48 (7x7)
UFQFPN48 (7x7) UFBGA64 (5x5) WLCSP49
– 2 PLLs for system clock, audio, ADC
• RTC with HW calendar, alarms and calibration
• Up to 21 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
• 11x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
• Up to 83 fast I/Os, most 5 V-tolerant
• Memories
– Up to 256 KB single bank Flash,
proprietary code readout protection
– 64 KB of SRAM including 16 KB with
hardware parity check
– Quad SPI memory interface
• Rich analog peripherals (independent supply)
– 1× 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC, low-power sample and hold
– 1x operational amplifier with built-in PGA
– 2x ultra-low-power comparators
• 15x communication interfaces
– 1x SAI (serial audio interface)
– 3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 4x USARTs (ISO 7816, LIN, IrDA, modem)
– 3x SPIs (4x SPIs with the Quad SPI)
– CAN (2.0B Active) and SDMMC interface
– SWPMI single wire protocol master I/F
– IRTIM (Infrared interface)
• 14-channel DMA controller
• True random number generator
• CRC calculation unit, 96-bit unique ID
DocID028800 Rev 1
1/200
www.st.com
STM32L431xx
•
Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
Table 1. Device summary
Reference
STM32L431xx
2/200
Part numbers
STM32L431CC, STM32L431KC, STM32L431RC, STM32L431VC, STM32L431CB,
STM32L431KB, STM32L431RB
DocID028800 Rev 1
STM32L431xx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16
3.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19
3.9
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.6
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.13
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.14
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.15
3.16
3.14.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 32
3.14.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 32
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.15.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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STM32L431xx
3.17
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.18
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.19
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22.2
General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 38
3.22.3
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.22.4
Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 38
3.22.5
Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22.6
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22.7
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22.8
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.23
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 40
3.24
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.25
Universal synchronous/asynchronous receiver transmitter (USART) . . . 42
3.26
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 43
3.27
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 45
3.30
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.31
Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 46
3.32
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.33
Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.34.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.34.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1
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Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Contents
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 83
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 83
6.3.4
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.16
Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.17
Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 132
6.3.18
Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 145
6.3.19
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.20
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.21
Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.24
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.25
Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 157
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
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7.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.2
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.3
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.4
UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5
WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.6
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.7
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.8
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.9
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.10
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.10.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.10.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 196
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L431xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32L431xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STM32L431xx USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32L431xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) . . . . . . . . . . . . . . . . . . . . . 64
Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) . . . . . . . . . . . . . . . . . . . . . 69
STM32L431xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 75
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83
Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 88
Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 91
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 93
Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . . 94
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DocID028800 Rev 1
7/200
9
List of tables
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
8/200
STM32L431xx
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 166
eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 173
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
DocID028800 Rev 1
STM32L431xx
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
List of tables
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 179
WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
WLCSP64 recommended PCB design rules (0.35 mm pitch) . . . . . . . . . . . . . . . . . . . . . 182
WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 186
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
STM32L431xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DocID028800 Rev 1
9/200
9
List of figures
STM32L431xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
10/200
STM32L431xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L431Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32L431Vx UFBGA100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32L431Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32L431Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32L431Rx WLCSP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32L431Cx WLCSP49 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32L431Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32L431Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32L431Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32L431xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 169
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
DocID028800 Rev 1
STM32L431xx
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
List of figures
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 175
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 187
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DocID028800 Rev 1
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11
Introduction
1
STM32L431xx
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L431xx microcontrollers.
This document should be read in conjunction with the STM32L4x1 reference manual
(RM0392). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
12/200
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STM32L431xx
2
Description
Description
The STM32L431xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.
The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all
ARM single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU) which enhances application
security.
The STM32L431xx devices embed high-speed memories (Flash memory up to 256 Kbyte,
64 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and
an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L431xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
two DAC channels, an internal voltage reference buffer, a low-power RTC, one generalpurpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose
16-bit timers, and two 16-bit low-power timers.
In addition, up to 21 capacitive sensing channels are available.
They also feature standard and advanced communication interfaces.
•
Three I2Cs
•
Three SPIs
•
Three USARTs and one Low-Power UART.
•
One SAI (Serial Audio Interfaces)
•
One SDMMC
•
One CAN
•
One SWPMI (Single Wire Protocol Master Interface)
The STM32L431xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to
3.6 V power supply. A comprehensive set of power-saving modes allows the design of lowpower applications.
Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMPs and comparators. A VBAT input allows to backup the RTC and backup
registers.
The STM32L431xx family offers nine packages from 32 to 100-pin packages.
Table 2. STM32L431xx family device features and peripheral counts
Peripheral
Flash memory
STM32L431Vx
256KB
STM32L431Rx
128KB
256KB
SRAM
STM32L431Cx
128KB
256KB
STM32L431Kx
128KB
256KB
64KB
Quad SPI
Yes
DocID028800 Rev 1
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48
Description
STM32L431xx
Table 2. STM32L431xx family device features and peripheral counts (continued)
Peripheral
Timers
Comm.
interfaces
STM32L431Vx
STM32L431Rx
Advanced
control
1 (16-bit)
General
purpose
2 (16-bit)
1 (32-bit)
Basic
2 (16-bit)
Low -power
2 (16-bit)
SysTick timer
1
Watchdog
timers
(independent,
window)
2
STM32L431Kx
SPI
3
2
I2C
3
2
USART
LPUART
3
1
2
1
SAI
1
CAN
1
Yes
SDMMC
No
SWPMI
Yes
RTC
Tamper pins
Yes
3
2
2
1
GPIOs
Wakeup pins
83
5
52
4
38 or 39(1)
3
26
2
Capacitive sensing
Number of channels
21
12
6
3
12-bit ADCs
Number of channels
1
16
1
16
1
10
1
10
Random generator
Yes
12-bit DAC channels
Internal voltage reference
buffer
2
No
Yes
Analog comparator
2
Operational amplifiers
1
Max. CPU frequency
80 MHz
Operating voltage
Operating temperature
Packages
1.71 to 3.6 V
Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
LQFP100
UFBGA100
WLCSP64
LQFP64
UFBGA64
1. For WLCSP49 package.
14/200
STM32L431Cx
DocID028800 Rev 1
WLCSP49
LQFP48
UFQFPN48
UFQFPN32
STM32L431xx
Description
Figure 1. STM32L431xx block diagram
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DocID028800 Rev 1
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48
Functional overview
STM32L431xx
3
Functional overview
3.1
ARM® Cortex®-M4 core with FPU
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32L431xx family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32L431xx family devices.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M4 processors. It balances the inherent performance advantage of
the ARM® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
16/200
DocID028800 Rev 1
STM32L431xx
3.4
Functional overview
Embedded Flash memory
STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for
storing programs and data in single bank architecture. The Flash memory contains 128
pages of 2 Kbyte.
Flexible protections can be configured thanks to option bytes:
•
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
Level 0: no readout protection
–
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
–
Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Area
Debug, boot from RAM or boot
from system memory (loader)
User execution
Protection
level
Read
Write
Erase
Read
Write
Erase
Main
memory
1
Yes
Yes
Yes
No
No
No
2
Yes
Yes
Yes
N/A
N/A
N/A
System
memory
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option
bytes
1
Yes
Yes
Yes
Yes
Yes
Yes
2
Yes
No
No
N/A
N/A
N/A
No
No
N/A(1)
Backup
registers
SRAM2
N/A
(1)
1
Yes
Yes
2
Yes
Yes
N/A
N/A
N/A
N/A
1
Yes
Yes
Yes(1)
No
No
No(1)
2
Yes
Yes
Yes
N/A
N/A
N/A
1. Erased when RDP change from Level 1 to Level 0.
•
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.
•
Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows to select if the PCROP area is erased or not when the RDP protection is
changed from Level 1 to Level 0.
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48
Functional overview
STM32L431xx
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
3.5
•
single error detection and correction
•
double error detection.
•
The address of the ECC fail can be read in the ECC register
Embedded SRAM
STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two
blocks:
•
48 Kbyte mapped at address 0x2000 0000 (SRAM1)
•
16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2000 C000, offering a contiguous address
space with the SRAM1 (16 Kbyte aliased by bit band)
This block is accessed through the ICode/DCode buses for maximum performance.
These 16 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6
Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
•
Three segments can be protected and defined thanks to the Firewall registers:
–
•
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
–
Non-volatile data segment (located in Flash)
–
Volatile data segment (located in SRAM1)
The start address and the length of each segments are configurable:
–
code segment: up to 1024 Kbyte with granularity of 256 bytes
–
Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
–
Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes
•
Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
•
Volatile data segment can be shared or not with the non-protected code
•
Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
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STM32L431xx
3.7
Functional overview
Boot modes
At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
A Flash empty check mechanism is implemented to force the boot from system flash if the
first flash memory location is not programmed and if the boot selection is configured to boot
from main flash.
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI and CAN in Device mode through DFU (device firmware upgrade).
3.8
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.9
Power supply management
3.9.1
Power supply schemes
•
VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
•
VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DACs/OPAMP) to 3.6 V: external analog power
supply for ADCs, DACs, OPAMP, Comparators and Voltage reference buffer. The VDDA
voltage level is independent from the VDD voltage.
•
VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note:
When the functions supplied by VDDA are not used, this supply should preferably be shorted
to VDD.
Note:
If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant (refer to Table 18: Voltage characteristics).
Note:
VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with
VDDIO1 = VDD.
DocID028800 Rev 1
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48
Functional overview
STM32L431xx
Figure 2. Power supply overview
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3.9.2
Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a Peripheral Voltage Monitor which compares the
independent supply voltage VDDA with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
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STM32L431xx
3.9.3
Functional overview
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
•
The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 16 Kbyte SRAM2 in Standby with RAM2 retention.
•
Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
•
Range 1 with the CPU running at up to 80 MHz.
•
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•
3.9.4
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
Low-power modes
The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources:
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.
•
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
DocID028800 Rev 1
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48
Functional overview
STM32L431xx
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL,
the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with RAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the
HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
22/200
DocID028800 Rev 1
STM32L431xx
Functional overview
Table 4. Functionalities depending on the working mode(1)
-
-
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
O(2)
O(2)
O(2)
O(2)
-
-
-
-
-
-
-
-
-
SRAM1 (48 KB)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
-
-
-
-
-
SRAM2 (16 KB)
Y
Y(3)
Y
Y(3)
Y
-
Y
-
O(4)
-
-
-
-
Quad SPI
O
O
O
O
-
-
-
-
-
-
-
-
-
Backup Registers
Y
Y
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
Brown-out reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
O
O
-
-
-
-
-
Peripheral Voltage
Monitor (PVMx;
x=1,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
-
-
-
-
-
-
-
-
-
High Speed Internal
(HSI16)
O
O
O
O
(5)
-
(5)
-
-
-
-
-
-
Oscillator RC48
O
O
-
-
-
-
-
-
-
-
-
-
-
High Speed
External (HSE)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low Speed Internal
(LSI)
O
O
O
O
O
-
O
-
O
-
-
-
-
Low Speed External
(LSE)
O
O
O
O
O
-
O
-
O
-
O
-
O
Multi-Speed Internal
(MSI)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock Security
System (CSS)
O
O
O
O
-
-
-
-
-
-
-
-
-
Clock Security
System on LSE
O
O
O
O
O
O
O
O
O
O
-
-
-
RTC / Auto wakeup
O
O
O
O
O
O
O
O
O
O
O
O
O
Number of RTC
Tamper pins
3
3
3
3
3
O
3
O
3
O
3
O
3
USARTx (x=1,2,3)
O
O
O
O
-
-
-
-
-
-
-
Peripheral
CPU
Flash memory (up
to 256 KB)
Run
Sleep
Lowpower
run
Lowpower
sleep
-
O(6) O(6)
DocID028800 Rev 1
Wakeup capability
Shutdown
Wakeup capability
Standby
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
23/200
48
Functional overview
STM32L431xx
Table 4. Functionalities depending on the working mode(1) (continued)
O
O
O
O
O(6) O(6) O(6) O(6)
-
-
-
-
-
I2Cx (x=1,2)
O
O
O
O
O(7) O(7)
-
-
-
-
-
-
-
O(7)
O(7)
O(7)
-
-
-
-
-
Sleep
Lowpower
run
Lowpower
sleep
-
-
-
Wakeup capability
Shutdown
Wakeup capability
Standby
Low-power UART
(LPUART)
Run
Wakeup capability
Stop 2
-
Peripheral
Wakeup capability
Stop 0/1
VBAT
I2C3
O
O
O
O
O(7)
SPIx (x=1,2,3)
O
O
O
O
-
-
-
-
-
-
-
-
-
CAN
O
O
O
O
-
-
-
-
-
-
-
-
-
SDMMC1
O
O
O
O
-
-
-
-
-
-
-
-
-
SWPMI1
O
O
O
O
-
O
-
-
-
-
-
-
-
SAIx (x=1)
O
O
O
O
-
-
-
-
-
-
-
-
-
ADCx (x=1)
O
O
O
O
-
-
-
-
-
-
-
-
-
DACx (x=1,2)
O
O
O
O
O
-
-
-
-
-
-
-
-
VREFBUF
O
O
O
O
O
-
-
-
-
-
-
-
-
OPAMPx (x=1)
O
O
O
O
O
-
-
-
-
-
-
-
-
COMPx (x=1,2)
O
O
O
O
O
O
O
O
-
-
-
-
-
Temperature sensor
O
O
O
O
-
-
-
-
-
-
-
-
-
Timers (TIMx)
O
O
O
O
-
-
-
-
-
-
-
-
-
Low-power timer 1
(LPTIM1)
O
O
O
O
O
O
O
O
-
-
-
-
-
Low-power timer 2
(LPTIM2)
O
O
O
O
O
O
-
-
-
-
-
-
-
Independent
watchdog (IWDG)
O
O
O
O
O
O
O
O
O
O
-
-
-
Window watchdog
(WWDG)
O
O
O
O
-
-
-
-
-
-
-
-
-
SysTick timer
O
O
O
O
-
-
-
-
-
-
-
-
-
Touch sensing
controller (TSC)
O
O
O
O
-
-
-
-
-
-
-
-
-
Random number
generator (RNG)
O(8)
O(8)
-
-
-
-
-
-
-
-
-
-
-
24/200
DocID028800 Rev 1
STM32L431xx
Functional overview
Table 4. Functionalities depending on the working mode(1) (continued)
-
-
-
CRC calculation
unit
O
O
O
O
-
-
-
-
-
-
-
-
-
GPIOs
O
O
O
O
O
O
O
O
(9)
5
pins
(11)
5
pins
-
Peripheral
Run
Sleep
Lowpower
run
Lowpower
sleep
-
(10)
Wakeup capability
Shutdown
Wakeup capability
Standby
Wakeup capability
Stop 2
Wakeup capability
Stop 0/1
VBAT
(10)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.5
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
DocID028800 Rev 1
25/200
48
Functional overview
3.10
STM32L431xx
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Table 5. STM32L431xx peripherals interconnect matrix
TIMx
Timers synchronization or chaining
Y
Y
Y
Y
-
-
ADCx
DACx
Conversion triggers
Y
Y
Y
Y
-
-
DMA
Memory to memory transfer trigger
Y
Y
Y
Y
-
-
COMPx
Comparator output blanking
Y
Y
Y
Y
-
-
IRTIM
Infrared interface output generation
Y
Y
Y
Y
-
-
TIM1
TIM2
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by analog
signals comparison
Y
Y
Y
Y
Y
(1)
TIM1
Timer triggered by analog watchdog
Y
Y
Y
Y
-
-
TIM16
Timer input channel from RTC events
Y
Y
Y
Y
-
-
LPTIMERx
Low-power timer triggered by RTC alarms
or tampers
Y
Y
Y
Y
Y
(1)
All clocks sources (internal TIM2
and external)
TIM15, 16
Clock source used as input channel for
RC measurement and trimming
Y
Y
Y
Y
-
-
CSS
CPU (hard fault)
RAM (parity error)
TIM1
Flash memory (ECC error) TIM15,16
COMPx
PVD
Timer break
Y
Y
Y
Y
-
-
Interconnect source
TIMx
TIM15/TIM16
COMPx
ADCx
RTC
26/200
Interconnect
destination
Interconnect action
DocID028800 Rev 1
Y
Y
STM32L431xx
Functional overview
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
Interconnect source
Run
Table 5. STM32L431xx peripherals interconnect matrix (continued)
TIMx
External trigger
Y
Y
Y
Y
-
-
LPTIMERx
External trigger
Y
Y
Y
Y
Y
(1)
ADCx
DACx
Conversion external trigger
Y
Y
Y
Y
-
-
Interconnect
destination
Interconnect action
Y
GPIO
1. LPTIM1 only.
DocID028800 Rev 1
27/200
48
Functional overview
3.11
STM32L431xx
Clocks and startup
The clock controller (see Figure 3) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
28/200
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
•
RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be
used to drive the SDMMC or the RNG peripherals. This clock can be output on the
MCO.
•
Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
–
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
•
Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs,
LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock.
Two PLLs, each having three independent outputs allowing the highest flexibility, can
generate independent clocks for the ADC, the SDMMC/RNG and the SAI.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DocID028800 Rev 1
STM32L431xx
Functional overview
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application
–
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
DocID028800 Rev 1
29/200
48
Functional overview
STM32L431xx
Figure 3. Clock tree
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