STM32L476RET6TR

STM32L476xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.4 µA with RTC – 100 µA/MHz run mode (LDO Mode) – 39 μA/MHz run mode (@3.3 V SMPS Mode) – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 CoreMark® (3.42 CoreMark/MHz @ 80 MHz) • Energy benchmark – 294 ULPMark™ CP score – 106 ULPMark™ PP score • Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – 3 PLLs for system clock, USB, audio, ADC June 2019 This is information on a product in full production. LQFP144 (20 × 20) LQFP100 (14 × 14) UFBGA132 (7 × 7) WLCSP72 LQFP64 (10 × 10) UFBGA144 (10 × 10) WLCSP81 • Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V • RTC with HW calendar, alarms and calibration • LCD 8× 40 or 4× 44 with step-up converter • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors • 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer • Memories – Up to 1 MB Flash, 2 banks read-whilewrite, proprietary code readout protection – Up to 128 KB of SRAM including 32 KB with hardware parity check – External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories – Quad SPI memory interface • 4x digital filters for sigma delta modulator • Rich analog peripherals (independent supply) – 3x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x 12-bit DAC output channels, low-power sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators • 20x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) – 3x I2C FM+(1 Mbit/s), SMBus/PMBus – 5x USARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART (Stop 2 wake-up) DS10198 Rev 8 1/270 www.st.com STM32L476xx – – – – 3x SPIs (and 1x Quad SPI) CAN (2.0B Active) and SDMMC interface SWPMI single wire protocol master I/F IRTIM (Infrared interface) • 14-channel DMA controller Reference STM32L476xx 2/270 • True random number generator • CRC calculation unit, 96-bit unique ID • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ • All packages are ECOPACK2® compliant Table 1. Device summary Part numbers STM32L476RG, STM32L476JG, STM32L476MG, STM32L476ME, STM32L476VG, STM32L476QG, STM32L476ZG, STM32L476RE, STM32L476JE, STM32L476VE, STM32L476QE, STM32L476ZE, STM32L476RC, STM32L476VC DS10198 Rev 8 STM32L476xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21 3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.15 3.16 3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40 3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DS10198 Rev 8 3/270 6 Contents 4 4/270 STM32L476xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 45 3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 49 3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51 3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 53 3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54 3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 56 3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 57 3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 57 3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58 3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS10198 Rev 8 STM32L476xx Contents 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 119 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 120 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 176 6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 177 6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 190 6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 195 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 DS10198 Rev 8 5/270 6 Contents 7 STM32L476xx 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 208 6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.3.30 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.5 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6 WLCSP72 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 7.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 261 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 6/270 DS10198 Rev 8 STM32L476xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19 STM32L476xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32L476xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 STM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . 108 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 120 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 125 Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 128 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 130 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 131 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Typical current consumption in Run and Low-power run modes, with different codes DS10198 Rev 8 7/270 10 List of tables Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/270 STM32L476xx running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 133 Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . 133 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 134 Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 135 Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 136 Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 137 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 DS10198 Rev 8 STM32L476xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. List of tables DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 216 eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 217 USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 223 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 223 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 224 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 225 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 226 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 228 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 237 SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 244 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 247 LQFP - 100 pins, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 WLCSP- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 253 WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip DS10198 Rev 8 9/270 10 List of tables STM32L476xx scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 129. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 256 Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Table 131. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 132. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 10/270 DS10198 Rev 8 STM32L476xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32L476Zx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32L476Zx, external SMPS device, LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32L476Zx UFBGA144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32L476Qx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32L476Qx, external SMPS device, UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . 64 STM32L476Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STM32L476Mx WLCSP81 ballout(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L476Jx WLCSP72 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L476Jx, external SMPS device, WLCSP72 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L476Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L476Rx, external SMPS device, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 67 STM32L476xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Current consumption measurement scheme with and without external SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 219 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 222 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 224 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 225 DS10198 Rev 8 11/270 12 List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. 12/270 STM32L476xx Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 227 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 236 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 237 LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 239 LQFP - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 249 LQFP - 100 pins, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 258 LQFP - 64 pins, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 DS10198 Rev 8 STM32L476xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L476xx microcontrollers. This document should be read in conjunction with the STM32L4x6 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS10198 Rev 8 13/270 60 Description 2 STM32L476xx Description The STM32L476xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. They also feature standard and advanced communication interfaces. • Three I2Cs • Three SPIs • Three USARTs, two UARTs and one Low-Power UART. • Two SAIs (Serial Audio Interfaces) • One SDMMC • One CAN • One USB OTG full-speed • One SWPMI (Single Wire Protocol Master Interface) The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. The STM32L476xx family offers six packages from 64-pin to 144-pin packages. 14/270 DS10198 Rev 8 STM32L476xx Description Table 2. STM32L476xx family device features and peripheral counts Peripheral Flash memory STM32 L476Zx STM32 L476Qx STM32 L476Vx STM32 L476Mx STM32 L476Rx 512K 512K 256K 512K 512K 512K 256K 512K 1MB 1MB 1MB 1MB 1MB 1MB B B B B B B B B SRAM 128KB External memory controller for static memories Yes Yes(1) Yes No Quad SPI Timers STM32 L476Jx No No 2 2 2 Yes 8x30 or 4x32 Yes 8x28 or 4x32 Yes 8x28 or 4x32 Yes Advanced control 2 (16-bit) General purpose 5 (16-bit) 2 (32-bit) Basic 2 (16-bit) Low -power 2 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 SPI 3 2C 3 I USART UART LPUART 3 2 1 Comm. SAI interfaces CAN 2 1 USB OTG FS Yes SDMMC Yes SWPMI Yes Digital filters for sigmadelta modulators Yes (4 filters) Number of channels 8 RTC Yes Tamper pins LCD COM x SEG 3 Yes 8x40 or 4x44 Yes 8x40 or 4x44 Yes 8x40 or 4x44 DS10198 Rev 8 15/270 60 Description STM32L476xx Table 2. STM32L476xx family device features and peripheral counts (continued) Peripheral STM32 L476Zx STM32 L476Qx STM32 L476Vx Random generator (2) GPIOs Wakeup pins Nb of I/Os down to 1.08 V STM32 L476Mx STM32 L476Jx STM32 L476Rx Yes 114 5 14 109 5 14 82 5 0 65 4 6 57 4 6 51 4 0 Capacitive sensing Number of channels 24 24 21 12 12 12 12-bit ADCs Number of channels 3 24 3 19 3 16 3 16 3 16 3 16 12-bit DAC channels 2 Internal voltage reference buffer Yes No Analog comparator 2 Operational amplifiers 2 Max. CPU frequency 80 MHz Operating voltage (VDD) 1.71 to 3.6 V Operating voltage (VDD12) 1.05 to 1.32 V Operating temperature Packages Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C LQFP144 UFBGA144 UFBGA 132 LQFP100 WLCSP81 WLCSP72 LQFP64 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2. 16/270 DS10198 Rev 8 STM32L476xx Description Figure 1. STM32L476xx block diagram JTCK/SWCLK JTAG & SW MPU ETM NVIC JTDO/SWD, JTDO CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE3, INT3 as AF Flexible static memory controller (FSMC): SRAM, PSRAM, NOR Flash, NAND Flash NJTRST, JTDI, TRACECLK D-BUS TRACED[3:0] ARM Cortex-M4 80 MHz FPU BK1_IO[3:0] CLK NCS Quad SPI memory interface I-BUS Flash up to 1 MB AHB bus-matrix FIFO @ VDDUSB USB OTG PHY ART ACCEL/ CACHE RNG S-BUS SRAM 96 KB DP DM SCL, SDA, INTN, ID, VBUS, SOF SRAM 32 KB VDD AHB2 80 MHz DMA2 VDD12 Power management Voltage regulator 3.3 to 1.2 V VDD = 1.71 to 3.6 V VDD12 = 1.05 to 1.32 V(1) VSS DMA1 @ VDD @ VDD 8 Groups of 3 channels max as AF supervision RC HSI Touch sensing controller Supply reset MSI VDDIO2, VDDUSB Int BOR VDDA, VSSA RC LSI PA[15:0] VDD, VSS, NRST GPIO PORT A GPIO PORT B PC[15:0] GPIO PORT C PLL 1&2&3 AHB1 80 MHz PB[15:0] PVD, PVM @VDD OSC_IN XTAL OSC OSC_OUT 4- 16MHz IWDG PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E VBAT = 1.55 to 3.6 V Standby PF[15:0] interface Reset & clock M AN AGT control @VBAT GPIO PORT F XTAL 32 kHz OSC32_IN OSC32_OUT PG[15:0] GPIO PORT G PCLKx FCLK GPIO PORT H HCLKx PH[1:0] RTC RTC_TS AWU Backup register RTC_TAMPx RTC_OUT @ VDD U STemperature AR T 2 M sensor Bps TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels, ETR as AF CRC @ VDDA 8 analog inputs common to the 3 ADCs ADC1 8 analog inputs common to the ADC1 & 2 ADC2 8 analog inputs for ADC3 ADC3 IF ITF USART2 @ VDDA VREF+ VREF Buffer 114 AF AHB/APB2 AHB/APB1 EXT IT. WKUP SDIO / MMC 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1 / PWM 16b 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM8 / PWM 16b FIFO D[7:0] CMD, CK as AF IrDA smcard UART4 RX, TX, CTS, RTS as AF UART5 RX, TX, CTS, RTS as AF SP2 MOSI, MISO, SCK, NSS as AF SP3 MOSI, MISO, SCK, NSS as AF 16b TIM17 16b smcard USART1 SAI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI2 SDCKIN[7:0], SDDATIN[7:0], SDCKOUT,SDTRIG as AF DFSDM @ VDDA INP, INM, OUT INP, INM, OUT TIM6 16b TIM7 16b A 60PM B Hz 2 SPI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF bxCAN1 IrDA MOSI, MISO, SCK, NSS as AF SCL, SDA, SMBA as AF I2C2/SMBUS @ VDDA DAC1 COMP2 TX, RX as AF @VDDA OpAmp1 VOUT, VINM, VINP OpAmp2 VOUT, VINM, VINP LCD Booster VLCD = 2.5V to 3.6V LCD 8x40 SEGx, COMx as AF LPUART1 RX, TX, CTS, RTS as AF SWPMI1 IO RX, TX, SUSPEND as AF LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF COMP1 ITF FIFO TIM16 1 channel, 1 compl. channel, BKIN as AF VLCD 1 channel, 1 compl. channel, BKIN as AF A P B(max) 1 3 0 M Hz APB1 80 MHz 16b RX, TX, CK, CTS, RTS as AF WWDG APB2 80MHz TIM15 RX, TX, CK, CTS, RTS as AF IrDA I2C1/SMBUS 2 channels, 1 compl. channel, BKIN as AF RX, TX, CK,CTS, RTS as AF USART3 smcard Firewall 1. Only available when using external SMPS supply mode. Note: DAC1_OUT1 DAC1_OUT2 MS31263V8 AF: alternate function on I/O pins. DS10198 Rev 8 17/270 60 Functional overview STM32L476xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32L476xx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L476xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 18/270 DS10198 Rev 8 STM32L476xx 3.4 Functional overview Embedded Flash memory STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 (1) 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. DS10198 Rev 8 19/270 60 Functional overview STM32L476xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 96 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This block is accessed through the ICode/DCode buses for maximum performance. These 32 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. 20/270 DS10198 Rev 8 STM32L476xx 3.7 Functional overview Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade). 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes Note: • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA voltage level is independent from the VDD voltage. • VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. • VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2 voltage level is independent from the VDD voltage. • VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. When the functions supplied by VDDA, VDDUSB or VDDIO2 are not used, these supplies should preferably be shorted to VDD. DS10198 Rev 8 21/270 60 Functional overview STM32L476xx Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 20: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1. Figure 2. Power supply overview VDDA domain VDDA VSSA 3 x A/D converters 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer VLCD VDDUSB VSS LCD USB transceivers VDDIO2 domain VDDIO2 VSS I/O ring PG[15:2] VDD domain VDD VDDIO1 I/O ring Reset block Temp. sensor 3 x PLL, HSI, MSI VSS Standby circuitry (Wakeup logic, IWDG) Voltage regulator VDD12 VCORE domain VCORE Core SRAM1 SRAM2 Digital peripherals Flash memory Low voltage detector Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv45700V1 During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDA, VDDUSB, VDDIO2, VLCD) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. 22/270 DS10198 Rev 8 STM32L476xx Functional overview Figure 3. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. DS10198 Rev 8 23/270 60 Functional overview 3.9.3 STM32L476xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. When the MR is in use, the STM32L476xx with the external SMPS option allows to force an external VCORE supply on the VDD12 supply pins. When VDD12 is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter. 3.9.4 Low-power modes The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. 24/270 DS10198 Rev 8 Mode Regulator (1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source MR range 1 Run SMPS range 2 High MR range2 DS10198 Rev 8 LPR All 40 µA/MHz(5) Yes ON(4) ON Any N/A Sleep MR range2 All except OTG_FS, RNG 39 µA/MHz(6) Yes ON(4) ON Any except PLL All except OTG_FS, RNG N/A to Range 1: 4 µs to Range 2: 64 µs All 6 cycles 13 µA/MHz(5) No ON(4) ON(7) Any interrupt or event Any 35 µA/MHz All except OTG_FS, RNG 6 cycles 15 µA/MHz(6) No ON(4) ON(7) Any except PLL All except OTG_FS, RNG Any interrupt or event 40 µA/MHz 6 cycles 25/270 Functional overview LPR 136 µA/MHz 37 µA/MHz SMPS range 2 Low LPSleep N/A 100 µA/MHz MR range 1 SMPS range 2 High Wakeup time 112 µA/MHz SMPS range 2 Low LPRun Consumption(3) STM32L476xx Table 4. STM32L476xx modes overview Mode Regulator (1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 108 µA 0.7 µs in SRAM 4.5 µs in Flash LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 6.6 µA w/o RTC 6.9 µA w RTC 4 µs in SRAM 6 µs in Flash Range 1(8) Stop 0 No Off ON Range 2(8) DS10198 Rev 8 Stop 1 LPR No Off ON Functional overview 26/270 Table 4. STM32L476xx modes overview (continued) STM32L476xx Mode Stop 2 Regulator (1) LPR CPU No Flash Off DS10198 Rev 8 OFF Shutdown OFF ON Clocks DMA & Peripherals(2) Wakeup source Consumption(3) LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 1.1 µA w/o RTC 1.4 µA w/RTC LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(14) Reset pin 5 I/Os (WKUPx)(13) RTC SRAM2 ON LPR Standby SRAM Powered Off Powered Off Off Off Powered Off Powered Off Wakeup time 5 µs in SRAM 7 µs in Flash 0.35 µA w/o RTC 0.65 µA w/ RTC 14 µs 0.12 µA w/o RTC 0.42 µA w/ RTC 0.03 µA w/o RTC 0.33 µA w/ RTC 256 µs 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 5. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.10 V 27/270 6. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.05 V 7. The SRAM1 and SRAM2 clocks can be gated on or off independently. Functional overview 1. LPR means Main regulator is OFF and Low-power regulator is ON. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. STM32L476xx Table 4. STM32L476xx modes overview (continued) 9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 11. OTG_FS wakeup by resume from suspend and attach detection protocol event. 12. SWPMI1 wakeup by resume from suspend. 13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Functional overview 28/270 8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected. DS10198 Rev 8 STM32L476xx STM32L476xx Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. DS10198 Rev 8 29/270 60 Functional overview • STM32L476xx Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. 30/270 DS10198 Rev 8 STM32L476xx Functional overview Table 5. Functionalities depending on the working mode(1) - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (up to 96 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (32 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - FSMC O O O O - - - - - - - - - Quad SPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - High Speed Internal (HSI16) O O O O (5) - (5) - - - - - - High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 Peripheral CPU Flash memory (up to 1 MB) Run Sleep Lowpower run Lowpower sleep - DS10198 Rev 8 Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT 31/270 60 Functional overview STM32L476xx Table 5. Functionalities depending on the working mode(1) (continued) O (8) O O (8) Lowpower run Lowpower sleep - O O O - - - - O O O - Wakeup capability USB OTG FS O Sleep Wakeup capability LCD Run Standby Shutdown Wakeup capability Peripheral Stop 2 Wakeup capability Stop 0/1 - O - - - - - - - - - - - - - - - - - - - VBAT USARTx (x=1,2,3,4,5) O O O O O(6) O(6) Low-power UART (LPUART) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2) O O O O O(7) O(7) (7) - - - - - - - O(7) O(7) O(7) - - - - - I2C3 O O O O O SPIx (x=1,2,3) O O O O - - - - - - - - - CAN O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1,2) O O O O - - - - - - - - - DFSDM1 O O O O - - - - - - - - - ADCx (x=1,2,3) O O O O - - - - - - - - - DAC1 O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - 32/270 DS10198 Rev 8 STM32L476xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Random number generator (RNG) Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.9.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. DS10198 Rev 8 33/270 60 Functional overview 3.10 STM32L476xx Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L476xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DAC1 DFSDM1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - IRTIM Infrared interface output generation Y Y Y Y - - TIM1, 8 TIM2, 3 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - USB Timer triggered by USB SOF Y Y - - - - Timer break Y Y Y Y - - Interconnect source TIMx TIM16/TIM17 COMPx ADCx RTC Interconnect destination TIM2 CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) TIM1,8 COMPx TIM15,16,17 PVD DFSDM1 (analog watchdog, short circuit detection) 34/270 Interconnect action DS10198 Rev 8 Y Y STM32L476xx Functional overview Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 GPIO Sleep Interconnect source Run Table 6. STM32L476xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y 1. LPTIM1 only. DS10198 Rev 8 35/270 60 Functional overview 3.11 STM32L476xx Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: • 36/270 – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS10198 Rev 8 STM32L476xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. DS10198 Rev 8 37/270 60 Functional overview STM32L476xx Figure 4. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC and LCD OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN LSE LSI MSI HSE MCO / 1→16 to PWR SYSCLK HSI16 OSC_OUT HSE OSC 4-48 MHz OSC_IN to AHB bus, core, memory and DMA Clock source control PLLCLK AHB PRESC / 1,2,..512 HCLK HSE Clock detector FCLK Cortex free running clock to Cortex system timer /8 MSI SYSCLK APB1 PRESC / 1,2,4,8,16 HSI16 PCLK1 to APB1 peripherals x1 or x2 HSI RC 16 MHz LSE HSI16 SYSCLK to USARTx x=2..5 to LPUART1 HSI16 SYSCLK MSI RC 100 kHz – 48 MHz to TIMx x=2..7 to I2Cx x=1,2,3 LSI LSE HSI16 to LPTIMx x=1,2 HSI16 to SWPMI MSI PLL /M VCO FVCO / P APB2 PRESC / 1,2,4,8,16 HSE PLLSAI3CLK /Q PLL48M1CLK /R PLLCLK PLLSAI1 VCO FVCO / P HSI16 PLL48M2CLK /R PLLADC1CLK to TIMx x=1,8,15,16,17 LSE HSI16 SYSCLK MSI to ADC PLLSAI2CLK /Q /R to USART1 48 MHz clock to USB, RNG, SDMMC SYSCLK PLLSAI2 VCO FVCO / P to APB2 peripherals x1 or x2 PLLSAI1CLK /Q PCLK2 to SAI1 PLLADC2CLK SAI1_EXTCLK to SAI2 SAI2_EXTCLK MS32440V3 38/270 DS10198 Rev 8 STM32L476xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.13 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 DS10198 Rev 8 39/270 60 Functional overview STM32L476xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 40 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 40/270 DS10198 Rev 8 STM32L476xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3. • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.15.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes) – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into 3 data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. DS10198 Rev 8 41/270 60 Functional overview STM32L476xx To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 110 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.15.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.16 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. 42/270 DS10198 Rev 8 STM32L476xx Functional overview This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.17 Voltage reference buffer (VREFBUF) The STM32L476xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 5. Voltage reference buffer VREFBUF VDDA Bandgap + DAC, ADC VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 DS10198 Rev 8 43/270 60 Functional overview 3.18 STM32L476xx Comparators (COMP) The STM32L476xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.19 Operational amplifier (OPAMP) The STM32L476xx embeds two operational amplifiers with external or internal follower routing and PGA capability. The operational amplifier features: 3.20 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. 44/270 DS10198 Rev 8 STM32L476xx Functional overview The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. 3.21 Liquid crystal display controller (LCD) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.22 • Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • Phase inversion to reduce power consumption and EMI • Integrated voltage output buffers for higher LCD driving capability • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode Digital filter for Sigma-Delta Modulators (DFSDM) The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in DS10198 Rev 8 45/270 60 Functional overview STM32L476xx hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by: • • – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from final output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel • break signal generation on analog watchdog event or on short circuit detector event • extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – 46/270 internal sources: device memory data streams (DMA) “regular” conversions can be requested at any time or even in continuous mode DS10198 Rev 8 STM32L476xx Functional overview without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Table 10. DFSDM1 implementation DFSDM features DFSDM1 Number of channels 8 Number of filters 4 Input from internal ADC - Supported trigger sources 3.23 10 Pulses skipper - ID registers support - Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.24 Timers and watchdogs The STM32L476xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 11. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1, TIM8 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2, TIM5 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 DS10198 Rev 8 47/270 60 Functional overview STM32L476xx Table 11. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.24.1 Advanced-control timer (TIM1, TIM8) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.24.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 48/270 DS10198 Rev 8 STM32L476xx 3.24.2 Functional overview General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L476xx (see Table 11 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, TIM4 and TIM5 They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.24.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.24.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. DS10198 Rev 8 49/270 60 Functional overview STM32L476xx This low-power timer supports the following features: 3.24.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Infrared interface (IRTIM) The STM32L476xx includes one infrared interface (IRTIM). It can be used with an infrared LED to perform remote control functions. It uses TIM16 and TIM17 output channels to generate output signal waveforms on IR_OUT pin. 3.24.6 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.24.7 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.24.8 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 50/270 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DS10198 Rev 8 STM32L476xx 3.25 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. DS10198 Rev 8 51/270 60 Functional overview 3.26 STM32L476xx Inter-integrated circuit interface (I2C) The device embeds three I2C. Refer to Table 12: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 4: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 12. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X Wakeup from Stop 0 / Stop 1 mode on address match X X X Wakeup from Stop 2 mode on address match - - X 1. X: supported 52/270 DS10198 Rev 8 STM32L476xx 3.27 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L476xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 13. STM32L476xx USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X - - - Smartcard mode X X X - - - Single-wire half-duplex communication X X X X X X IrDA SIR ENDEC block X X X X X - LIN mode X X X X X - Dual clock domain X X X X X X Wakeup from Stop 0 / Stop 1 modes X X X X X X Wakeup from Stop 2 mode - - - - - X Receiver timeout interrupt X X X X X - Modbus communication X X X X X - Auto baud rate detection Driver Enable X (4 modes) X X LPUART/USART data length X X X X 7, 8 and 9 bits 1. X = supported. DS10198 Rev 8 53/270 60 Functional overview 3.28 STM32L476xx Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 54/270 DS10198 Rev 8 STM32L476xx 3.29 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.30 Serial audio interfaces (SAI) The device embeds 2 SAI. Refer to Table 14: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. DS10198 Rev 8 55/270 60 Functional overview STM32L476xx Table 14. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.31 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 3.32 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 56/270 DS10198 Rev 8 STM32L476xx Functional overview The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.33 – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – 14 Scalable filter banks – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards Interface (SDMMC) The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The SDMMC features include the following: 3.34 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data write and read with DMA capability Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE). DS10198 Rev 8 57/270 60 Functional overview STM32L476xx The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. 3.35 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller This memory controller is also named Flexible memory controller (FMC). The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbyte of data • 8-,16- bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 58/270 DS10198 Rev 8 STM32L476xx 3.36 Functional overview Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory The Quad SPI interface supports: • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS10198 Rev 8 59/270 60 Functional overview STM32L476xx 3.37 Development support 3.37.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.37.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L476xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell™ operates with third party debugger software tools. 60/270 DS10198 Rev 8 STM32L476xx 4 Pinouts and pin description Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PG15 VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) Figure 6. STM32L476Zx LQFP144 pinout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VDDUSB PA13 (JTMS-SWDIO) PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDIO2 VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN (PC14) PC15-OSC32_OUT (PC15) PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN (PH0) PH1-OSC_OUT (PH1) NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 MS31270V5 1. The above figure shows the package top view. DS10198 Rev 8 61/270 111 Pinouts and pin description STM32L476xx 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS VDD12 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VDDUSB PA13 (JTMS-SWDIO) PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDIO2 VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 VDD12 VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN (PC14) PC15-OSC32_OUT (PC15) PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN (PH0) PH1-OSC_OUT (PH1) NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 1. The above figure shows the package top view. 62/270 DS10198 Rev 8 MSv43895V2 STM32L476xx Pinouts and pin description Figure 8. STM32L476Zx UFBGA144 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A VSS PE0 PB8 BOOT0 PB7 PG14 PG12 PD7 PD6 PD1 PD0 VSS B VBAT PE4 PE3 PE1 PB6 PG15 PG11 PD5 PC12 PC10 PA12 PA11 C PC15OSC32_OUT PE5 PE2 PB9 PB5 PB3 PG9 PD4 PC11 PA14 PA13 PA10 D PF4 PC14OSC32_IN PE6 PC13 PB4 PG13 PG10 PD3 PD2 PA15 PA9 PA8 E PF6 PF1 PF0 PF2 VSS VDDIO2 VDD VSS VDDUSB PC6 PC9 PC8 F PF8 PF7 PF5 PF3 VDD VSS VSS VDDIO2 PG7 PG6 PG8 PC7 G PH1OSC_OUT PH0-OSC_IN PF10 PF9 VDD VSS VSS VDD PG4 PD13 PG3 PG5 H PC2 PC0 PC1 NRST VSS VDD VDD VSS PD12 PD11 PD14 PG2 J VSSA VREF- PA0 PC3 PC4 PF11 PG1 PE9 PB13 PB14 PD10 PD15 K VREF+ VDDA PA1 PA6 PB2 PF12 PG0 PE11 PB11 PB12 PD8 PD9 L OPAMP1 _VINM PA2 PA4 OPAMP2 _VINM PB0 PF13 PE8 PE12 PE13 PE14 PB10 PB15 M VSS PA3 PA5 PA7 PC5 PB1 PF14 PE7 PF15 PE10 PE15 VSS MSv50902V1 1. The above figure shows the package top view. Figure 9. STM32L476Qx UFBGA132 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 PG14 PG13 PD2 PD0 PC11 VDDUSB PA10 D PC14OSC32_IN PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PF3 PG5 PC8 PC7 PC6 F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS G PH1OSC_OUT VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13 J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10 K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12 PA1 OPAMP1_ VINM OPAMP2_ VINM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 M VDDA MSv35003V7 1. The above figure shows the package top view. DS10198 Rev 8 63/270 111 Pinouts and pin description STM32L476xx Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 VDD12 PG13 PD2 PD0 PC11 VDDUSB PA10 D PC14OSC32_IN PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PF3 PG5 PC8 PC7 PC6 F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS G PH1OSC_OUT VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13 J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10 K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 VDD12 PB12 M VDDA PA1 OPAMP1_ VINM OPAMP2_ VINM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 MSv47486V1 1. The above figure shows the package top view. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 11. STM32L476Vx LQFP100 pinout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0 PA1 PA2 MS31271V3 1. The above figure shows the package top view. 64/270 DS10198 Rev 8 STM32L476xx Pinouts and pin description Figure 12. STM32L476Mx WLCSP81 ballout(1) 1 2 3 4 5 6 7 8 9 A VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VDD B VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13 VBAT C PA12 PA13 PC11 PG11 PG12 PB4 PB5 PC15OSC32_OUT PC14OSC32_IN D PA11 PA10 PC10 PD5 PD6 PD7 BOOT0 PH1OSC_OUT PH0-OSC_IN E PC9 PA8 PA9 VDD PD4 PE7 PB8 PB9 NRST F PC7 PC8 PC6 PD9 PD8 PE8 PC2 PC1 PC0 G PB15 PB14 PB11 PA1 PA4 PA2 PC3 VREF+ VSSA/VREF- H PB12 PB13 PB10 PA7 PA6 PA5 PA3 PA0 VDDA J VDD VSS PB2 PB1 PB0 PC5 PC4 VDD VSS MSv38020V3 1. The above figure shows the package top view. Figure 13. STM32L476Jx WLCSP72 ballout(1) 1 2 3 4 5 6 7 8 9 A VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS VDD B VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13 VBAT C PA12 PA13 PC11 PG11 PG12 PB4 PB5 PC15OSC32_OUT PC14OSC32_IN D PA11 PA10 PC10 BOOT0 PH1OSC_OUT PH0-OSC_IN E PC9 PA8 PA9 PB8 PB9 NRST F PC7 PC8 PC6 PC2 PC1 PC0 G PB15 PB14 PB11 PA1 PA4 PA2 PC3 VREF+ VSSA/VREF- H PB12 PB13 PB10 PA7 PA6 PA5 PA3 PA0 VDDA J VDD VSS PB2 PB1 PB0 PC5 PC4 VDD VSS WLCSP72 MSv35083V7 1. The above figure shows the package top view. DS10198 Rev 8 65/270 111 Pinouts and pin description STM32L476xx Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout(1) 1 2 3 4 5 6 7 8 9 A VDDUSB PC10 PD2 PG9 PG14 PB3 BOOT0 VSS VDD B VSS PA14 PC12 PG10 PG13 VDDIO2 PB7 VDD12 VBAT C PA12 PA13 PA15 PG12 PB4 PB8 PC13 PC15OSC32_OUT PC14OSC32_IN D PA11 PA10 PC11 PB9 PH1OSC_OUT PH0-OSC_IN E PC9 PA8 PA9 PB5 PB6 NRST F VDD PC7 PC8 PC2 PC1 PC0 G PB15 PC6 PB14 PA2 PA0 PA1 PC3 VREF+ VSSA/VREF- H PB12 PB13 PB11 PA7 PA5 PA4 PA3 VDD VDDA J VDD12 VSS PB10 PB0 PB1 PB2 PC4 PA6 VSS WLCSP72 MSv43896V1 1. The above figure shows the package top view. VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PD2 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 15. STM32L476Rx LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN (PC14) 3 46 PA13 (JTMS-SWDIO) PC15-OSC32_OUT (PC15) 4 45 PA12 PH0-OSC_IN (PH0) 5 44 PA11 PH1-OSC_OUT (PH1) 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP64 MS31272V5 1. The above figure shows the package top view. 66/270 DS10198 Rev 8 STM32L476xx Pinouts and pin description VDD VSS VDD12 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 16. STM32L476Rx, external SMPS device, LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN (PC14) 3 46 PA13 (JTMS-SWDIO) PC15-OSC32_OUT (PC15) 4 45 PA12 PH0-OSC_IN (PH0) 5 44 PA11 PH1-OSC_OUT (PH1) 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PB10 PB11 VDD12 VSS VDD LQFP64 MSv45744V1 1. The above figure shows the package top view. Table 15. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Definition Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os _f (1) _l (2) _u (3) _a (4) _s (5) I/O, Fm+ capable I/O, with LCD function supplied by VLCD I/O, with USB function supplied by VDDUSB I/O, with Analog switch function supplied by VDDA I/O supplied only by VDDIO2 DS10198 Rev 8 67/270 111 Pinouts and pin description STM32L476xx Table 15. Legend/abbreviations used in the pinout table (continued) Name Notes Abbreviation Definition Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla. 2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 16 are: FT_u, FT_lu. 4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. The related I/O structures in Table 16 are: FT_s, FT_fs. 68/270 DS10198 Rev 8 STM32L476xx Table 16. STM32L476xx pin definitions - DS10198 Rev 8 - - - - - - - - - - - - - - 1 2 3 B2 A1 B1 B2 A1 B1 1 2 3 1 2 3 C3 B3 B2 PE2 PE3 PE4 I/O I/O I/O FT_l FT_l FT Alternate functions Additional functions - TRACECK, TIM3_ETR, TSC_G7_IO1, LCD_SEG38, FMC_A23, SAI1_MCLK_A, EVENTOUT - - TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B, EVENTOUT - - TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number - - - - 4 C2 C2 4 4 C2 PE5 I/O FT - - - - - - 5 D2 D2 5 5 D3 PE6 I/O FT - TRACED3, TIM3_CH4, FMC_A22, SAI1_SD_A, EVENTOUT RTC_TAMP3/WKUP3 1 1 B9 B9 B9 6 E2 E2 6 6 B1 VBAT S - - - - 2 2 B8 C7 B8 7 C1 C1 7 7 D4 PC13 I/O FT EVENTOUT RTC_TAMP1/RTC_TS/ RTC_OUT/WKUP2 (1) (2) 69/270 Pinouts and pin description - TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, FMC_A21, SAI1_SCK_A, EVENTOUT UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA144 8 D1 D1 8 8 D2 PC14OSC32_ I/O IN (PC14) FT Alternate functions Additional functions EVENTOUT OSC32_IN (2) EVENTOUT OSC32_OUT Notes LQFP100 C9 C9 C9 I/O structure WLCSP81 3 Pin name (function after reset) Pin type WLCSP72 3 WLCSP72_SMPS LQFP64_SMPS Pin functions LQFP64 Pin Number (1) (2) DS10198 Rev 8 E1 E1 9 9 C1 - - D6 D6 10 10 E3 PF0 I/O FT_f - I2C2_SDA, FMC_A0, EVENTOUT - - - - D5 D5 11 11 E2 PF1 I/O FT_f - I2C2_SCL, FMC_A1, EVENTOUT - - - - - D4 D4 12 12 E4 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - - - E4 E4 13 13 F4 PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6 - - - - - - F3 F3 14 14 D1 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7 - - - - - - F4 F4 15 15 F3 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8 - - - - - 10 F2 F2 16 16 F6 VSS S - - - - - - - - - 11 G2 G2 17 17 G5 VDD S - - - - - - - - - - - - 18 18 E1 PF6 I/O FT_a - TIM5_ETR, TIM5_CH1, SAI1_SD_B, EVENTOUT ADC3_IN9 - - - - - - - - 19 19 F2 PF7 I/O FT_a - TIM5_CH2, SAI1_MCLK_B, EVENTOUT ADC3_IN10 4 4 C8 C8 C8 - - - - - - - - - - I/O FT (1) STM32L476xx 9 PC15OSC32_ OUT (PC15) Pinouts and pin description 70/270 Table 16. STM32L476xx pin definitions (continued) WLCSP72_SMPS WLCSP81 LQFP100 UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA144 Pin type I/O structure Notes - - - - - - - - 20 20 F1 PF8 I/O FT_a - TIM5_CH3, SAI1_SCK_B, EVENTOUT ADC3_IN11 - - - - - - - - 21 21 G4 PF9 I/O FT_a - TIM5_CH4, SAI1_FS_B, TIM15_CH1, EVENTOUT ADC3_IN12 - - - - - - - - 22 22 G3 PF10 I/O FT_a - TIM15_CH2, EVENTOUT ADC3_IN13 5 5 12 F1 F1 23 23 G2 PH0OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN I/O FT - EVENTOUT OSC_OUT I/O RST - - - - LPTIM1_IN1, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT ADC123_IN1 - LPTIM1_OUT, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX, LCD_SEG19, EVENTOUT ADC123_IN2 D9 D9 D9 Pin name (function after reset) 6 6 D8 D8 D8 13 G1 G1 24 24 G1 PH1OSC_ OUT (PH1) 7 7 E9 E9 E9 14 H2 H2 25 25 H4 NRST 8 9 8 9 F9 F8 F9 F8 F9 F8 15 16 H1 J2 H1 J2 26 27 26 27 H2 H3 PC0 PC1 I/O FT_fla I/O FT_fla Alternate functions Additional functions 71/270 Pinouts and pin description WLCSP72 DS10198 Rev 8 LQFP64_SMPS Pin functions LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) 10 10 F7 F7 F7 DS10198 Rev 8 11 11 G7 G7 G7 17 J3 J3 28 28 H1 PC2 I/O FT_la Alternate functions Additional functions - LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, LCD_SEG20, EVENTOUT ADC123_IN3 ADC123_IN4 Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number 18 K2 K2 29 29 J4 PC3 I/O FT_a - LPTIM1_ETR, SPI2_MOSI, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT - - - - - 19 - - 30 30 J1 VSSA S - - - - - - - - - 20 - - 31 31 J2 VREF- S - - - - - J1 J1 - - - VSSA/ VREF- S - - - - 12 12 G9 G9 G9 - G8 G8 G8 21 L1 L1 32 32 K1 VREF+ S - - - VREFBUF_OUT - - H9 H9 H9 22 M1 M1 33 33 K2 VDDA S - - - - - - - - - - VDDA/ VREF+ S - - - - - TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR, EVENTOUT OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1 13 13 - - - 14 14 H8 G5 H8 23 L2 L2 34 34 J3 PA0 I/O FT_a STM32L476xx - Pinouts and pin description 72/270 Table 16. STM32L476xx pin definitions (continued) WLCSP81 LQFP100 UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA144 - - - - M3 M3 - - L1 15 15 G4 G6 G4 DS10198 Rev 8 16 16 G6 G4 G6 24 25 M2 K3 M2 K3 35 36 35 36 K3 L2 OPAMP1 _VINM PA1 PA2 Notes WLCSP72_SMPS - I/O structure WLCSP72 - Pin name (function after reset) Pin type LQFP64_SMPS Pin functions LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) I TT - I/O FT_la I/O FT_la Additional functions - - (3) TIM2_CH2, TIM5_CH2, USART2_RTS_DE, UART4_RX, LCD_SEG0, TIM15_CH1N, EVENTOUT OPAMP1_VINM, ADC12_IN6 - TIM2_CH3, TIM5_CH3, USART2_TX, LCD_SEG1, SAI2_EXTCLK, TIM15_CH1, EVENTOUT ADC12_IN7, WKUP4/LSCO - TIM2_CH4, TIM5_CH4, USART2_RX, LCD_SEG2, TIM15_CH2, EVENTOUT OPAMP1_VOUT, ADC12_IN8 26 L3 L3 37 37 M2 PA3 18 18 J9 J9 J9 27 E3 E3 38 38 F7 VSS S - - - - 19 19 J8 H8 J8 28 H3 H3 39 39 G8 VDD S - - - - - SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT ADC12_IN9, DAC1_OUT1 29 J4 J4 40 40 L3 PA4 I/O TT_a 73/270 Pinouts and pin description 17 17 H7 H7 H7 20 20 G5 H6 G5 I/O TT_la Alternate functions 21 21 H6 H5 H6 DS10198 Rev 8 22 22 H5 - - - J8 H5 - - 30 K4 K4 41 41 M3 PA5 31 L4 L4 42 42 K4 PA6 - M4 M4 - - L4 OPAMP2 _VINM I/O TT_a I/O FT_la I TT Alternate functions Additional functions - TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR, EVENTOUT ADC12_IN10, DAC1_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM1_BKIN_COMP2, TIM8_BKIN_COMP2, TIM16_CH1, EVENTOUT OPAMP2_VINP, ADC12_IN11 - - - OPAMP2_VINM, ADC12_IN12 Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number 32 J5 J5 43 43 M4 PA7 I/O FT_la (3) 24 24 J7 J7 J7 33 K5 K5 44 44 J5 PC4 I/O FT_la - USART3_TX, LCD_SEG22, EVENTOUT COMP1_INM, ADC12_IN13 25 J6 - J6 34 L5 L5 45 45 M5 PC5 I/O FT_la - USART3_RX, LCD_SEG23, EVENTOUT COMP1_INP, ADC12_IN14, WKUP5 - STM32L476xx 23 23 H4 H4 H4 TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1, EVENTOUT Pinouts and pin description 74/270 Table 16. STM32L476xx pin definitions (continued) 26 25 DS10198 Rev 8 27 26 28 27 J5 J4 J4 J5 J5 J4 35 36 M5 M6 M5 M6 46 47 46 47 L5 M6 PB0 PB1 I/O TT_la I/O FT_la Alternate functions Additional functions - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, EVENTOUT OPAMP2_VOUT, ADC12_IN15 - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT COMP1_INM, ADC12_IN16 COMP1_INP Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) J3 J6 J3 37 L6 L6 48 48 K5 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, EVENTOUT - - - - - K6 K6 49 49 J6 PF11 I/O FT - EVENTOUT - - - - - - - J7 J7 50 50 K6 PF12 I/O FT - FMC_A6, EVENTOUT - - - - - - - - - 51 51 G6 VSS S - - - - - - - - - - - - 52 52 H6 VDD S - - - - - - - - - - K7 K7 53 53 L6 PF13 I/O FT - DFSDM1_DATIN6, FMC_A7, EVENTOUT - 75/270 Pinouts and pin description - WLCSP72 WLCSP72_SMPS WLCSP81 LQFP100 UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA144 Pin type I/O structure Notes DS10198 Rev 8 LQFP64_SMPS Pin functions LQFP64 Pin Number - - - - - - J8 J8 54 54 M7 PF14 I/O FT - DFSDM1_CKIN6, TSC_G8_IO1, FMC_A8, EVENTOUT - - - - - - - J9 J9 55 55 M9 PF15 I/O FT - TSC_G8_IO2, FMC_A9, EVENTOUT - - - - - - - H9 H9 56 56 K7 PG0 I/O FT - TSC_G8_IO3, FMC_A10, EVENTOUT - - - - - - - G9 G9 57 57 J7 PG1 I/O FT - TSC_G8_IO4, FMC_A11, EVENTOUT - - TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B, EVENTOUT - - TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B, EVENTOUT - - - - - - - - - - E6 F6 38 39 M7 L7 M7 L7 58 59 58 59 M8 L7 Pin name (function after reset) PE7 PE8 I/O I/O FT FT Alternate functions Additional functions - - - - 40 M8 M8 60 60 J8 PE9 I/O FT - - - - - - - F6 F6 61 61 G7 VSS S - - - - - - - - - - G6 G6 62 62 E7 VDD S - - - - STM32L476xx - TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B, EVENTOUT Pinouts and pin description 76/270 Table 16. STM32L476xx pin definitions (continued) - DS10198 Rev 8 - - - - - - - - - - - - - - - - - - - - - - 41 42 43 44 45 L8 M9 L9 L8 M9 L9 63 64 65 M10 M10 66 M11 M11 67 63 M10 64 65 66 67 K8 L8 L9 L10 PE10 PE11 PE12 PE13 PE14 I/O I/O I/O I/O I/O FT FT FT FT FT Alternate functions Additional functions - TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT - - TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_NCS, FMC_D8, EVENTOUT - - TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9, EVENTOUT - - TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11, EVENTOUT - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 - Pin functions 77/270 Pinouts and pin description - LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) - - - DS10198 Rev 8 29 28 H3 - - J3 H3 30 29 G3 H3 G3 30 46 47 M12 M12 68 L10 L10 69 68 69 M11 L11 PE15 PB10 I/O I/O FT FT_fl Alternate functions Additional functions - TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 Pin functions 48 L11 - 70 - K9 PB11 I/O FT_fl - TIM2_CH4, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT - L11 - 70 - VDD12 S - - - - - B8 - - 31 31 J2 J2 J2 49 F12 F12 71 71 H5 VSS S - - - - 32 32 J1 F1 J1 50 G12 G12 72 72 - VDD S - - - - STM32L476xx - LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number Pinouts and pin description 78/270 Table 16. STM32L476xx pin definitions (continued) 33 33 H1 H1 H1 51 L12 L12 73 73 K10 PB12 I/O FT_l Alternate functions Additional functions - TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT - - TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 34 34 H2 H2 H2 52 STM32L476xx Table 16. STM32L476xx pin definitions (continued) K12 K12 74 74 J9 PB13 I/O FT_fl Pinouts and pin description 79/270 35 35 G2 G3 G2 53 K11 K11 75 75 J10 PB14 I/O FT_fl Alternate functions Additional functions - TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 36 36 G1 G1 G1 - - - - - - F5 F4 K10 K10 76 76 L12 PB15 I/O FT_l - 55 K9 77 77 K11 PD8 I/O FT_l - USART3_TX, LCD_SEG28, FMC_D13, EVENTOUT - - USART3_RX, LCD_SEG29, FMC_D14, SAI2_MCLK_A, EVENTOUT - 56 K8 K9 K8 78 78 K12 PD9 I/O FT_l STM32L476xx - - 54 RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2, EVENTOUT Pinouts and pin description 80/270 Table 16. STM32L476xx pin definitions (continued) - DS10198 Rev 8 - - - - - - - - - - - - - - 57 58 59 J12 J11 J10 - - - - 60 - - - - - - - - - - - - - - - - - - - 61 J12 J11 J10 80 81 79 80 81 J11 H10 H9 PD10 PD11 PD12 I/O I/O I/O FT_l FT_l FT_l Alternate functions Additional functions - USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A, EVENTOUT - - USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT - - TIM4_CH1, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT - - Notes I/O structure Pin type UFBGA144 LQFP144_SMPS LQFP144 79 Pin name (function after reset) 82 82 G10 PD13 I/O FT_l - TIM4_CH2, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT, EVENTOUT - 83 83 E5 VSS S - - - - - 84 84 F5 VDD S - - - - 85 85 H11 PD14 I/O FT_l - TIM4_CH3, LCD_SEG34, FMC_D0, EVENTOUT - H12 H12 H11 H11 Pinouts and pin description 81/270 - Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) Pin functions LQFP64_SMPS WLCSP72 WLCSP72_SMPS WLCSP81 LQFP100 UFBGA132 LQFP144 LQFP144_SMPS UFBGA144 Pin type I/O structure Notes DS10198 Rev 8 LQFP64 UFBGA132_SMPS Pin Number - - - - - 62 H10 H10 86 86 J12 PD15 I/O FT_l - TIM4_CH4, LCD_SEG35, FMC_D1, EVENTOUT - - - - - - - G10 G10 87 87 H12 PG2 I/O FT_s - SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT - - - - - - - F9 F9 88 88 G11 PG3 I/O FT_s - SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT - - - - - - - F10 F10 89 89 G9 PG4 I/O FT_s - SPI1_MOSI, FMC_A14, SAI2_MCLK_B, EVENTOUT - - Pin name (function after reset) Alternate functions Additional functions - - - - - E9 E9 90 90 G12 PG5 I/O FT_s - - - - - - - G4 G4 91 91 F10 PG6 I/O FT_s - I2C3_SMBA, LPUART1_RTS_DE, EVENTOUT - - - - - - - H4 H4 92 92 F9 PG7 I/O FT_fs - I2C3_SCL, LPUART1_TX, FMC_INT, EVENTOUT - - - - - - - J6 J6 93 93 F11 PG8 I/O FT_fs - I2C3_SDA, LPUART1_RX, EVENTOUT - - - - - - - - - 94 94 M12 VSS S - - - - - - - - - - - - 95 95 VDDIO2 S - - - - F8 STM32L476xx - SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT Pinouts and pin description 82/270 Table 16. STM32L476xx pin definitions (continued) 37 37 F3 G2 F3 DS10198 Rev 8 38 38 F1 39 39 F2 F2 F3 F1 F2 63 64 65 66 E12 E12 E11 E11 E10 E10 D12 D12 96 97 98 99 96 97 98 99 E10 F12 E12 E11 PC6 PC7 PC8 PC9 I/O I/O I/O I/O FT_l FT_l FT_l FT_l 83/270 Alternate functions Additional functions - TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT - - TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT - - TIM3_CH3, TIM8_CH3, TSC_G4_IO3, LCD_SEG26, SDMMC1_D0, EVENTOUT - - TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1, EVENTOUT - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 Pin functions Pinouts and pin description 40 40 E1 E1 E1 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) Alternate functions Additional functions - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 41 41 E2 E2 E2 67 D11 D11 100 100 D12 PA8 I/O FT_l - MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, LPTIM2_OUT, EVENTOUT 42 42 E3 E3 E3 68 D10 D10 101 101 D11 PA9 I/O FT_lu - TIM1_CH2, USART1_TX, LCD_COM1, TIM15_BKIN, EVENTOUT OTG_FS_VBUS - TIM1_CH3, USART1_RX, OTG_FS_ID, LCD_COM2, TIM17_BKIN, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, OTG_FS_DM, TIM1_BKIN2_COMP1, EVENTOUT - - 43 43 D2 D2 D2 44 44 D1 D1 D1 69 70 C12 C12 102 102 C12 B12 B12 103 103 B12 PA10 PA11 I/O FT_lu I/O FT_u 71 A12 A12 104 104 B11 PA12 I/O FT_u - 46 46 C2 C2 C2 72 A11 A11 105 105 C11 PA13 (JTMSSWDIO) I/O FT (4) JTMS-SWDIO, IR_OUT, OTG_FS_NOE, EVENTOUT - 47 47 B1 B1 B1 - VSS S - - - - - - - - E8 STM32L476xx 45 45 C1 C1 C1 TIM1_ETR, USART1_RTS_DE, CAN1_TX, OTG_FS_DP, EVENTOUT Pinouts and pin description 84/270 Table 16. STM32L476xx pin definitions (continued) I/O structure Notes E9 VDDUSB S - - - - UFBGA144 Pin type LQFP144_SMPS C11 C11 106 106 LQFP144 73 WLCSP72 48 48 A1 A1 A1 LQFP64 UFBGA132 Pin name (function after reset) LQFP100 UFBGA132_SMPS Pin functions WLCSP81 WLCSP72_SMPS LQFP64_SMPS Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) Alternate functions Additional functions - - - - 74 F11 F11 107 107 H8 VSS S - - - - - - - - - 75 G11 G11 108 108 H7 VDD S - - - - 76 A10 A10 109 109 C10 PA14 (JTCKSWCLK) I/O FT (4) JTCK-SWCLK, EVENTOUT - (4) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SAI2_FS_B, EVENTOUT - - SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, LCD_COM4/LCD_SEG28 /LCD_SEG40, SDMMC1_D2, SAI2_SCK_B, EVENTOUT - 49 49 B2 B2 B2 DS10198 Rev 8 50 50 A2 C3 A2 51 51 D3 A2 D3 77 78 A9 A9 110 110 D10 B11 B11 111 111 B10 PA15 (JTDI) PC10 I/O I/O FT_l FT_l 85/270 Pinouts and pin description - 52 52 C3 D3 C3 79 C10 C10 112 112 C9 PC11 I/O FT_l Additional functions - SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, LCD_COM5/LCD_SEG29 /LCD_SEG41, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT - - SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, LCD_COM6/LCD_SEG30 /LCD_SEG42, SDMMC1_CK, SAI2_SD_B, EVENTOUT - - SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2, EVENTOUT - - SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3, EVENTOUT - DS10198 Rev 8 53 53 B3 B3 B3 - - - - - - - - - - 80 81 82 B10 B10 113 113 C9 B9 C9 B9 B9 114 114 A11 115 115 A10 PC12 PD0 PD1 I/O I/O I/O FT_l FT FT STM32L476xx Alternate functions Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number Pinouts and pin description 86/270 Table 16. STM32L476xx pin definitions (continued) 54 DS10198 Rev 8 - - - A3 A3 A3 - - - 83 84 C8 B8 C8 B8 116 116 117 117 D9 D8 PD2 PD3 I/O I/O FT_l FT Alternate functions Additional functions - TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, LCD_COM7/LCD_SEG31 /LCD_SEG43, SDMMC1_CMD, EVENTOUT - - SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, FMC_CLK, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) - - - E5 85 B7 B7 118 118 C8 PD4 I/O FT - - - - - D4 86 A6 A6 119 119 B8 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - - - - - - - 120 120 A1 VSS S - - - - - - - - E4 - - - 121 121 - VDD S - - - - - - - - - - D5 87 B6 B6 122 122 A9 PD6 I/O FT - DFSDM1_DATIN1, USART2_RX, FMC_NWAIT, SAI1_SD_A, EVENTOUT - - - - D6 88 A5 A5 123 123 A8 PD7 I/O FT - DFSDM1_CKIN1, USART2_CK, FMC_NE1, EVENTOUT Pinouts and pin description 87/270 - SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, FMC_NOE, EVENTOUT - DS10198 Rev 8 - - - - - A4 A4 A4 B4 B4 B4 C4 - C4 - - - D9 D8 G3 D9 D8 G3 124 124 125 125 126 126 C7 D7 B7 PG9 PG10 PG11 I/O I/O I/O FT_s FT_s FT_s Alternate functions Additional functions - SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - - LPTIM1_IN1, SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - - LPTIM1_IN2, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT - - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number - C5 C4 C5 - D7 D7 127 127 A7 PG12 I/O FT_s - - - B5 B5 B5 - C7 C7 128 128 D6 PG13 I/O FT_fs - I2C1_SDA, USART1_CK, FMC_A24, EVENTOUT - - - A5 A5 A5 - C6 - 129 129 A6 PG14 I/O FT_fs - I2C1_SCL, FMC_A25, EVENTOUT - - - - F7 F7 130 130 A12 VSS S - - - - - - - G7 G7 131 131 VDDIO2 S - - - - - - - B6 B6 B6 E6 STM32L476xx - LPTIM1_ETR, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT Pinouts and pin description 88/270 Table 16. STM32L476xx pin definitions (continued) WLCSP81 LQFP100 UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA144 - - - - K1 K1 132 - B6 55 54 A6 A6 A6 89 A8 A8 133 132 C6 DS10198 Rev 8 56 55 C6 C5 C6 91 A7 C5 A7 C5 134 133 135 134 D5 C5 PB3 (JTDOTRACE SWO) I/O FT_s - I/O FT_la PB4 I/O FT_la (NJTRST) PB5 I/O FT_la Alternate functions Additional functions LPTIM1_OUT, I2C1_SMBA, EVENTOUT - (4) JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, LCD_SEG7, SAI1_SCK_B, EVENTOUT COMP2_INM (4) NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT COMP2_INP - LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT - 89/270 Pinouts and pin description 57 56 C7 E7 C7 90 PG15 Notes WLCSP72_SMPS - I/O structure WLCSP72 - Pin name (function after reset) Pin type LQFP64_SMPS Pin functions LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) 58 57 B7 E8 B7 92 B5 B5 136 135 B5 PB6 I/O FT_fa Additional functions - LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM1_DATIN5, USART1_TX, TSC_G2_IO3, TIM8_BKIN2_COMP2, SAI1_FS_B, TIM16_CH1N, EVENTOUT COMP2_INP - LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, LCD_SEG21, FMC_NL, TIM8_BKIN_COMP1, TIM17_CH1N, EVENTOUT COMP2_INM, PVD_IN - - - - TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT - DS10198 Rev 8 59 58 A7 B7 A7 93 B4 B4 137 136 A5 PB7 60 59 D7 A7 D7 94 A4 A4 138 137 A4 BOOT0 61 60 E7 C6 E7 95 A3 A3 139 138 A3 PB8 I/O FT_fla I I/O - FT_fl STM32L476xx Alternate functions Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number Pinouts and pin description 90/270 Table 16. STM32L476xx pin definitions (continued) 62 61 E8 D7 E8 Alternate functions Additional functions - Notes I/O structure Pin name (function after reset) Pin type UFBGA144 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100 WLCSP81 WLCSP72_SMPS WLCSP72 LQFP64_SMPS LQFP64 Pin Number STM32L476xx Table 16. STM32L476xx pin definitions (continued) 96 B3 B3 140 139 C4 PB9 I/O FT_fl - IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT DS10198 Rev 8 - - - - - 97 C3 C3 141 140 A2 PE0 I/O FT_l - TIM4_ETR, LCD_SEG36, FMC_NBL0, TIM16_CH1, EVENTOUT - - - - - - 98 A2 A2 142 141 B4 PE1 I/O FT_l - LCD_SEG37, FMC_NBL1, TIM17_CH1, EVENTOUT - - 62 - J1 - - - C6 - VDD12 S - - - - 99 D3 D3 143 143 M1 VSS S - - - - 64 64 A9 A9 A9 100 C4 C4 144 144 VDD S - - - - 63 63 A8 A8 A8 - 142 - 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual. 3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins. 91/270 4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. Pinouts and pin description 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS_ DE PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - USART3_CTS PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - - USART1_CK PA9 - TIM1_CH2 - - - - - USART1_TX PA10 - TIM1_CH3 - - - - - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - - - USART1_CTS PA12 - TIM1_ETR - - - - - USART1_RTS_ DE PA13 JTMS-SWDIO IR_OUT - - - - - - PA14 JTCK-SWCLK - - - - - - - PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS - Port DS10198 Rev 8 Port A STM32L476xx AF0 Pinouts and pin description 92/270 Table 17. Alternate function AF0 to AF7(1) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - USART3_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_ DATIN0 USART3_RTS_ DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 - PB3 JTDOTRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_ DE PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO USART1_CTS PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL - DFSDM1_ DATIN5 USART1_TX PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA - DFSDM1_CKIN5 USART1_RX PB8 - - TIM4_CH3 - I2C1_SCL - DFSDM1_ DATIN6 - PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_CKIN6 - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK DFSDM1_ DATIN7 USART3_TX PB11 - TIM2_CH4 - - I2C2_SDA - DFSDM1_CKIN7 USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN_ COMP2 I2C2_SMBA SPI2_NSS DFSDM1_ DATIN1 USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM1_ DATIN2 USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 - Port DS10198 Rev 8 Port B 93/270 Pinouts and pin description AF0 STM32L476xx Table 17. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PC0 - LPTIM1_IN1 - - I2C3_SCL - DFSDM1_ DATIN4 - PC1 - LPTIM1_OUT - - I2C3_SDA - DFSDM1_CKIN4 - PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_ CKOUT - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 - PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM1_ DATIN3 - PC8 - - TIM3_CH3 TIM8_CH3 - - - - PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - - PC10 - - - - - - SPI3_SCK USART3_TX PC11 - - - - - - SPI3_MISO USART3_RX PC12 - - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port DS10198 Rev 8 Port C STM32L476xx AF0 Pinouts and pin description 94/270 Table 17. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PD0 - - - - - SPI2_NSS DFSDM1_ DATIN7 - PD1 - - - - - SPI2_SCK DFSDM1_CKIN7 - PD2 - - TIM3_ETR - - - - USART3_RTS_ DE PD3 - - - - - SPI2_MISO DFSDM1_ DATIN0 USART2_CTS PD4 - - - - - SPI2_MOSI DFSDM1_CKIN0 USART2_RTS_ DE PD5 - - - - - - - USART2_TX PD6 - - - - - - DFSDM1_ DATIN1 USART2_RX PD7 - - - - - - DFSDM1_CKIN1 USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - - - - USART3_CTS PD12 - - TIM4_CH1 - - - - USART3_RTS_ DE PD13 - - TIM4_CH2 - - - - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - Port DS10198 Rev 8 Port D 95/270 Pinouts and pin description AF0 STM32L476xx Table 17. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PE0 - - TIM4_ETR - - - - - PE1 - - - - - - - - PE2 TRACECK - TIM3_ETR - - - - - PE3 TRACED0 - TIM3_CH1 - - - - - PE4 TRACED1 - TIM3_CH2 - - - DFSDM1_ DATIN3 - PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 - PE6 TRACED3 - TIM3_CH4 - - - - - PE7 - TIM1_ETR - - - - DFSDM1_ DATIN2 - PE8 - TIM1_CH1N - - - - DFSDM1_CKIN2 - PE9 - TIM1_CH1 - - - - DFSDM1_ CKOUT - PE10 - TIM1_CH2N - - - - DFSDM1_ DATIN4 - PE11 - TIM1_CH2 - - - - DFSDM1_ CKIN4 - PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM1_ DATIN5 - PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_ COMP2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN_ COMP1 - SPI1_MOSI - - Port DS10198 Rev 8 Port E STM32L476xx AF0 Pinouts and pin description 96/270 Table 17. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - PF2 - - - - I2C2_SMBA - - - PF3 - - - - - - - - PF4 - - - - - - - - PF5 - - - - - - - - PF6 - TIM5_ETR TIM5_CH1 - - - - - PF7 - - TIM5_CH2 - - - - - PF8 - - TIM5_CH3 - - - - - PF9 - - TIM5_CH4 - - - - - PF10 - - - - - - - - PF11 - - - - - - - - PF12 - - - - - - - - PF13 - - - - - - DFSDM1_ DATIN6 - PF14 - - - - - - DFSDM1_CKIN6 - PF15 - - - - - - - - Port DS10198 Rev 8 Port F 97/270 Pinouts and pin description AF0 STM32L476xx Table 17. Alternate function AF0 to AF7(1) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PG0 - - - - - - - - PG1 - - - - - - - - PG2 - - - - - SPI1_SCK - - PG3 - - - - - SPI1_MISO - - PG4 - - - - - SPI1_MOSI - - PG5 - - - - - SPI1_NSS - - PG6 - - - - I2C3_SMBA - - - PG7 - - - - I2C3_SCL - - - PG8 - - - - I2C3_SDA - - - PG9 - - - - - - SPI3_SCK USART1_TX PG10 - LPTIM1_IN1 - - - - SPI3_MISO USART1_RX PG11 - LPTIM1_IN2 - - - - SPI3_MOSI USART1_CTS PG12 - LPTIM1_ETR - - - - SPI3_NSS USART1_RTS_ DE PG13 - - - - I2C1_SDA - - USART1_CK PG14 - - - - I2C1_SCL - - - PG15 - LPTIM1_OUT - - I2C1_SMBA - - - PH0 - - - - - - - - PH1 - - - - - - - - Port DS10198 Rev 8 Port G Port H 1. Please refer to Table 18 for AF8 to AF15. STM32L476xx AF0 Pinouts and pin description 98/270 Table 17. Alternate function AF0 to AF7(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT PA2 - - - LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT PA3 - - - LCD_SEG2 - - TIM15_CH2 EVENTOUT PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 - - QUADSPI_BK1_IO3 LCD_SEG3 TIM1_BKIN_ COMP2 TIM8_BKIN_ COMP2 TIM16_CH1 EVENTOUT PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT PA8 - - OTG_FS_SOF LCD_COM0 - - LPTIM2_OUT EVENTOUT PA9 - - - LCD_COM1 - - TIM15_BKIN EVENTOUT PA10 - - OTG_FS_ID LCD_COM2 - - TIM17_BKIN EVENTOUT PA11 - CAN1_RX OTG_FS_DM - TIM1_BKIN2_ COMP1 - - EVENTOUT PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT PA13 - - OTG_FS_NOE - - - - EVENTOUT PA14 - - - - - - - EVENTOUT PA15 UART4_RTS _DE TSC_G3_IO1 - LCD_SEG17 - SAI2_FS_B - EVENTOUT Port DS10198 Rev 8 Port A 99/270 Pinouts and pin description AF8 STM32L476xx Table 18. Alternate function AF8 to AF15(1) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT - - EVENTOUT PB1 - - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT PB2 - - - - - - - EVENTOUT PB3 - - - LCD_SEG7 - SAI1_SCK_B - EVENTOUT PB4 UART5_RTS _DE TSC_G2_IO1 - LCD_SEG8 - SAI1_MCLK_ B TIM17_BKIN EVENTOUT PB5 UART5_CTS TSC_G2_IO2 - LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 - TSC_G2_IO3 - - TIM8_BKIN2_ COMP2 SAI1_FS_B TIM16_CH1N EVENTOUT PB7 UART4_CTS TSC_G2_IO4 - LCD_SEG21 FMC_NL TIM8_BKIN_ COMP1 TIM17_CH1N EVENTOUT PB8 - CAN1_RX - LCD_SEG16 SDMMC1_D4 SAI1_MCLK_ A TIM16_CH1 EVENTOUT PB9 - CAN1_TX - LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT PB10 LPUART1_ RX - QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - QUADSPI_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT PB12 LPUART1_ RTS_DE TSC_G1_IO1 - LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_ CTS TSC_G1_IO2 - LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX SAI2_MCLK_ A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT Port DS10198 Rev 8 Port B STM32L476xx AF8 Pinouts and pin description 100/270 Table 18. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PC0 LPUART1_ RX - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - - LCD_SEG19 - - - EVENTOUT PC2 - - - LCD_SEG20 - - - EVENTOUT PC3 - - - LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - - LCD_SEG22 - - - EVENTOUT PC5 - - - LCD_SEG23 - - - EVENTOUT PC6 - TSC_G4_IO1 - LCD_SEG24 SDMMC1_D6 SAI2_MCLK_ A - EVENTOUT PC7 - TSC_G4_IO2 - LCD_SEG25 SDMMC1_D7 SAI2_MCLK_ B - EVENTOUT PC8 - TSC_G4_IO3 - LCD_SEG26 SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 OTG_FS_NOE LCD_SEG27 SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2_ COMP1 EVENTOUT PC10 UART4_TX TSC_G3_IO2 - LCD_COM4/ LCD_SEG28/ LCD_SEG40 SDMMC1_D2 SAI2_SCK_B - EVENTOUT PC11 UART4_RX TSC_G3_IO3 - LCD_COM5/ LCD_SEG29/ LCD_SEG41 SDMMC1_D3 SAI2_MCLK_ B - EVENTOUT PC12 UART5_TX TSC_G3_IO4 - LCD_COM6/ LCD_SEG30/ LCD_SEG42 SDMMC1_CK SAI2_SD_B - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port DS10198 Rev 8 Port C 101/270 Pinouts and pin description AF8 STM32L476xx Table 18. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT PD2 UART5_RX TSC_SYNC - LCD_COM7/ LCD_SEG31/ LCD_SEG43 SDMMC1_CMD - - EVENTOUT PD3 - - - - FMC_CLK - - EVENTOUT PD4 - - - - FMC_NOE - - EVENTOUT PD5 - - - - FMC_NWE - - EVENTOUT PD6 - - - - FMC_NWAIT SAI1_SD_A - EVENTOUT PD7 - - - - FMC_NE1 - - EVENTOUT PD8 - - - LCD_SEG28 FMC_D13 - - EVENTOUT PD9 - - - LCD_SEG29 FMC_D14 SAI2_MCLK_ A - EVENTOUT PD10 - TSC_G6_IO1 - LCD_SEG30 FMC_D15 SAI2_SCK_A - EVENTOUT PD11 - TSC_G6_IO2 - LCD_SEG31 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - LCD_SEG32 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - LCD_SEG33 FMC_A18 - LPTIM2_OUT EVENTOUT PD14 - - - LCD_SEG34 FMC_D0 - - EVENTOUT PD15 - - - LCD_SEG35 FMC_D1 - - EVENTOUT Port DS10198 Rev 8 Port D STM32L476xx AF8 Pinouts and pin description 102/270 Table 18. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PE0 - - - LCD_SEG36 FMC_NBL0 - TIM16_CH1 EVENTOUT PE1 - - - LCD_SEG37 FMC_NBL1 - TIM17_CH1 EVENTOUT PE2 - TSC_G7_IO1 - LCD_SEG38 FMC_A23 SAI1_MCLK_ A - EVENTOUT PE3 - TSC_G7_IO2 - LCD_SEG39 FMC_A19 SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 - - FMC_A20 SAI1_FS_A - EVENTOUT PE5 - TSC_G7_IO4 - - FMC_A21 SAI1_SCK_A - EVENTOUT PE6 - - - - FMC_A22 SAI1_SD_A - EVENTOUT PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 SAI1_MCLK_ B - EVENTOUT PE11 - TSC_G5_IO2 QUADSPI_NCS - FMC_D8 - - EVENTOUT PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT Port DS10198 Rev 8 Port E 103/270 Pinouts and pin description AF8 STM32L476xx Table 18. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PF0 - - - - FMC_A0 - - EVENTOUT PF1 - - - - FMC_A1 - - EVENTOUT PF2 - - - - FMC_A2 - - EVENTOUT PF3 - - - - FMC_A3 - - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - - EVENTOUT PF6 - - - - - SAI1_SD_B - EVENTOUT PF7 - - - - - SAI1_MCLK_ B - EVENTOUT PF8 - - - - - SAI1_SCK_B - EVENTOUT PF9 - - - - - SAI1_FS_B TIM15_CH1 EVENTOUT PF10 - - - - - - TIM15_CH2 EVENTOUT PF11 - - - - - - - EVENTOUT PF12 - - - - FMC_A6 - - EVENTOUT PF13 - - - - FMC_A7 - - EVENTOUT PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT Port DS10198 Rev 8 Port F Pinouts and pin description 104/270 Table 18. Alternate function AF8 to AF15(1) (continued) STM32L476xx AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT PG4 - - - - FMC_A14 SAI2_MCLK_ B - EVENTOUT PG5 LPUART1_ CTS - - - FMC_A15 SAI2_SD_B - EVENTOUT PG6 LPUART1_ RTS_DE - - - - - - EVENTOUT PG7 LPUART1_TX - - - FMC_INT - - EVENTOUT PG8 LPUART1_ RX - - - - - - EVENTOUT PG9 - - - - FMC_NCE/ FMC_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT PG11 - - - - - SAI2_MCLK_ A TIM15_CH2 EVENTOUT PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT PG13 - - - - FMC_A24 - - EVENTOUT PG14 - - - - FMC_A25 - - EVENTOUT PG15 - - - - - - - EVENTOUT Port DS10198 Rev 8 Port G 105/270 Pinouts and pin description AF8 STM32L476xx Table 18. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT Port Port H 1. Please refer to Table 17 for AF0 to AF7. Pinouts and pin description 106/270 Table 18. Alternate function AF8 to AF15(1) (continued) DS10198 Rev 8 STM32L476xx STM32L476xx 5 Memory mapping Memory mapping Figure 17. STM32L476xx memory map 0xFFFF FFFF 0xBFFF FFFF Cortex™-M4 with FPU Internal Peripherals 7 Reserved 0xA000 1400 QUADSPI registers 0xA000 1000 FMC registers 0xA000 0000 0xE000 0000 0x5FFF FFFF Reserved 6 0x5006 0C00 AHB2 0x4800 0000 Reserved 0xC000 0000 0x4002 4400 FMC and QUADSPI registers 5 AHB1 0x4002 0000 0x4001 6400 0xA000 0000 4 QUADSPI Flash bank 0x4001 0000 FMC bank 3 0x4000 0000 0x9000 0000 Reserved APB2 Reserved 0x4000 9800 APB1 0x1FFF FFFF 0x8000 0000 Reserved 0x1FFF F810 FMC bank 1 & bank 2 3 Option Bytes 0x1FFF F800 Reserved 0x1FFF F000 System memory 0x6000 0000 0x1FFF 8000 Reserved 0x1FFF 7810 Options Bytes 2 0x1FFF 7800 Reserved 0x1FFF 7400 Peripherals 0x4000 0000 OTP area 0x1FFF 7000 System memory 1 0x1FFF 0000 SRAM1 0x2000 0000 Reserved 0x1000 8000 SRAM2 0x1000 0000 Reserved 0 CODE 0x0810 0000 Flash memory 0x0800 0000 0x0000 0000 0x0010 0000 Reserved 0x0000 0000 Reserved Flash, system memory or SRAM, depending on BOOT configuration MS34100V3 DS10198 Rev 8 107/270 111 Memory mapping STM32L476xx Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) Bus AHB3 AHB2 - AHB1 108/270 Boundary address Size (bytes) Peripheral 0xA000 1000 - 0xA000 13FF 1 KB QUADSPI 0xA000 0000 - 0xA000 0FFF 4 KB FMC 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5004 0400 - 0x5006 07FF 129 KB 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB OTG_FS 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1800 - 0x4800 1BFF 1 KB GPIOG 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~127 MB 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 0x4002 0000 - 0x4002 03FF 1 KB DMA1 DS10198 Rev 8 Reserved Reserved STM32L476xx Memory mapping Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 APB2 Boundary address Size (bytes) Peripheral 0x4001 6400 - 0x4001 FFFF 39 KB Reserved 0x4001 6000 - 0x4000 63FF 1 KB DFSDM1 0x4001 5C00 - 0x4000 5FFF 1 KB Reserved 0x4001 5800 - 0x4000 5BFF 1 KB SAI2 0x4001 5400 - 0x4000 57FF 1 KB SAI1 0x4001 4C00 - 0x4000 53FF 2 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB TIM8 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF 0x4001 0000 - 0x4001 002F DS10198 Rev 8 COMP 1 KB VREFBUF SYSCFG 109/270 111 Memory mapping STM32L476xx Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 110/270 Boundary address Size (bytes) Peripheral 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 - 0x4000 87FF 1 KB Reserved 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP 0x4000 7400 - 0x4000 77FF 1 KB DAC1 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6800 - 0x4000 6FFF 1 KB Reserved 0x4000 6400 - 0x4000 67FF 1 KB CAN1 0x4000 6000 - 0x4000 63FF 1 KB Reserved 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 5000 - 0x4000 53FF 1 KB UART5 0x4000 4C00 - 0x4000 4FFF 1 KB UART4 0x4000 4800 - 0x4000 4BFF 1 KB USART3 0x4000 4400 - 0x4000 47FF 1 KB USART2 DS10198 Rev 8 STM32L476xx Memory mapping Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB LCD 0x4000 1800 - 0x4000 23FF 3 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0C00- 0x4000 0FFF 1 KB TIM5 0x4000 0800 - 0x4000 0BFF 1 KB TIM4 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. DS10198 Rev 8 111/270 111 Electrical characteristics STM32L476xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 18. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 19. Figure 18. Pin loading conditions Figure 19. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 112/270 DS10198 Rev 8 MS19211V1 STM32L476xx 6.1.6 Electrical characteristics Power supply scheme Figure 20. Power supply scheme VBAT VBAT 1.55 – 3.6 V 1.55 – 3.6 V Backup circuitry Backup circuitry (LSE, RTC, (LSE, RTC, Backup registers) Backup registers) Backup circuitry (LSE, RTC, Backup registers) VVCORE CORE VBAT Power switch Power switch 1.55 – 3.6 V VVDD DD Power switch nnx xVDD VDD Regulator Regulator 2 x VDD12 OUT OUT nnxx100 100nF nF GPIOs GPIOs +1xx4.7 4.7μF μF +1 IN IN VDD n x VDD VSS n nx xVSS Level shifter Level shifter VVDDIO1 DDIO1 1.05 – 1.32 V IO IO logic logic Kernel Kernellogic logic (CPU, Digital (CPU, Digital & Memories) Memories) & VCORE IO logic Kernel logic (CPU, Digital & Memories) Regulator OUT x VDDIO2 m xmVDDIO2 GPIOs +1 x 4.7 μF m x100 nF m x100 nF +4.7 μF +4.7 μF DDIO2 IN VVDDIO2 OUT OUT GPIOs nGPIOs x VSS VDDIO2 VDDA VDDA m x100 nF 10μF nF +4.7 +1nF μF 10 +1 μF IN IN m x VSS m x VSS m x VDDIO2 VDDA VDDA VREF GPIOs μF 100 nF m x+1VSS VSSA VREF+ VVREF+ REFVREF- OUT ADCs/ DACs/ ADCs/ OPAMPs/ DACs/ IN COMPs/ OPAMPs/ VREF COMPs/ VREF IO logic VSSA VDDA VDDA MS35001V1 VREF 10 nF +1 μF IO IO logic logic VDDIO2 Level shifter n x 100 nF Level shifter Level shifterLevel shifter VDDIO1 DDIO2 VVDDIO2 100 nF +1 μF VREF+ VREF- ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF MS35001V2 VSSA MSv45701V1 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or DS10198 Rev 8 113/270 238 Electrical characteristics STM32L476xx below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 114/270 DS10198 Rev 8 STM32L476xx 6.1.7 Electrical characteristics Current consumption measurement Figure 21. Current consumption measurement scheme with and without external SMPS power supply IDD_USB IDD_USB VDDUSB VDDUSB IDD_VBAT IDD_VBAT VBAT VBAT IDD IDD IDDA SMPS VDD12 VDD VDD VDDIO2 VDDIO2 IDDA VDDA VDDA MSv45730V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 20. Voltage characteristics(1) Symbol Ratings Min Max Unit VDDX - VSS External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) -0.3 4.0 V VDD12 - VSS External SMPS supply voltage Range 1 -0.3 Range 2 -0.3 1.4 V VIN(2) Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 VSS-0.3 4.0 Input voltage on any other pins DS10198 Rev 8 V 115/270 238 Electrical characteristics STM32L476xx Table 20. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 21: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 21. Current characteristics Symbol ∑IVDD ∑IVSS Ratings Max Total current into sum of all VDD power lines (source)(1)(2) Total current out of sum of all VSS ground lines (sink) 150 (1) 150 IVDD(PIN) Maximum current into each VDD power pin (source)(1)(2) 100 IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(4) ∑|IINJ(PIN)| Unit Total output current sunk by sum of all I/Os and control pins(3) mA 100 (3) Total output current sourced by sum of all I/Os and control pins Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 100 -5/+0(5) Injected current on PA4, PA5 -5/0 Total injected current (sum of all I/Os and control pins)(6) 25 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. Valid also for VDD12 on SMPS packages. 3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the minimum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). 116/270 DS10198 Rev 8 STM32L476xx Electrical characteristics Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS10198 Rev 8 Value Unit –65 to +150 °C 150 °C 117/270 238 Electrical characteristics STM32L476xx 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 VDD Standard operating voltage - VDD12 Standard operating voltage VDDIO2 PG[15:2] I/Os supply voltage VDDA Analog supply voltage 1.71 (1) At least one I/O in PG[15:2] used 1.08 3.6 0 3.6 1.62 DAC or OPAMP used 1.8 VREFBUF used 2.4 USB used USB not used TT_xx I/O BOOT0 VIN All I/O except BOOT0 and TT_xx PD 118/270 V 1.55 3.6 V 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3 0 9 -0.3 Min(Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V, 5.5 V)(2)(3) 0 LQFP144 - - 625 LQFP100 - - 476 LQFP64 - - 444 UFBGA144 - - 377 UFBGA132 - - 363 WLCSP81 - - 487 WLCSP72 - - 434 DS10198 Rev 8 V 3.6 I/O input voltage Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(4) V 1.05 Backup operating voltage VDDUSB USB supply voltage 1.32 Up to 26 MHz ADC, DAC, OPAMP, COMP, VREFBUF not used VBAT V 1.08 ADC or COMP used MHz 3.6 Full frequency range PG[15:2] not used Unit V V mW STM32L476xx Electrical characteristics Table 23. General operating conditions (continued) Symbol PD TA TJ Parameter Conditions Power dissipation at TA = 125 °C for suffix 3(4) Min Max LQFP144 - - 156 LQFP100 - - 119 LQFP64 - - 111 UFBGA144 - - 94 UFBGA132 - - 90 WLCSP81 - - 121 WLCSP72 - - 108 –40 85 Ambient temperature for the suffix 6 version Maximum power dissipation Low-power dissipation –40 105 Ambient temperature for the suffix 7 version Maximum power dissipation –40 105 –40 125 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 –40 130 Suffix 6 version –40 105 Suffix 7 version –40 125 Suffix 3 version –40 130 Junction temperature range (5) Low-power Low-power dissipation(5) dissipation(5) Unit mW °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 24 are derived from tests performed under the ambient temperature condition summarized in Table 23. Table 24. Operating conditions at power-up / power-down(1) Symbol tVDD tVDDA tVDDUSB Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate VDDUSB rise time rate - VDDUSB fall time rate DS10198 Rev 8 Min Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ Unit µs/V µs/V µs/V 119/270 238 Electrical characteristics STM32L476xx Table 24. Operating conditions at power-up / power-down(1) (continued) Symbol Parameter Conditions VDDIO2 rise time rate tVDDIO2 Min Max 0 ∞ 10 ∞ - VDDIO2 fall time rate Unit µs/V 1. At power-up, the VDD12 voltage should not be forced externally. The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected. 6.3.3 Embedded reset and power control block characteristics The parameters given in Table 25 are derived from tests performed under the ambient temperature conditions summarized in Table 23: General operating conditions. Table 25. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) 120/270 Parameter Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 VDD rising DS10198 Rev 8 V V V V V V V V V V V STM32L476xx Electrical characteristics Table 25. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Symbol VPVD6 Vhyst_BORH0 Parameter PVD threshold 6 Unit V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and IDD (BOR_PVD)(2) PVD consumption from VDD - - 1.1 1.6 µA Vhyst_BOR_PVD VPVM1 VDDUSB peripheral voltage monitoring - 1.18 1.22 1.26 V VPVM2 VDDIO2 peripheral voltage monitoring - 0.92 0.96 1 V VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV IDD PVM1 and PVM2 (PVM1/PVM2) consumption from VDD (2) - - 0.2 - µA IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) - - 2 - µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS10198 Rev 8 121/270 238 Electrical characteristics 6.3.4 STM32L476xx Embedded voltage reference The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. Table 26. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs - - 12.5 20(2) µA VREFINT buffer consumption from VDD when converted by IDD(VREFINTBUF) ADC Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV TCoeff Average temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm - 250 1200(2) ppm/V 24 25 26 49 50 51 74 75 76 ∆VREFINT VDDCoeff Average voltage coefficient VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage 3.0 V < VDD < 3.6 V - 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 122/270 DS10198 Rev 8 % VREFINT STM32L476xx Electrical characteristics Figure 22. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 DS10198 Rev 8 123/270 238 Electrical characteristics 6.3.5 STM32L476xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 21: Current consumption measurement scheme with and without external SMPS power supply. The IDD_ALL parameters given in Table 27 to Table 49 represent the total MCU consumption including the current supplying VDD, VDD12, VDDIO2, VDDA, VLCD, VDDUSB and VBAT. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0351 reference manual). • When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 27 to Table 50 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. 124/270 DS10198 Rev 8 Conditions Symbol Parameter - Voltage scaling DS10198 Rev 8 85 °C 3.20 3.37 3.51 3.93 4.76 2.49 2.01 2.16 2.30 2.72 3.34 1.29 1.62 1.10 1.17 1.31 1.73 2.56 0.69 0.85 1.18 0.61 0.70 0.89 1.24 1.95 0.37 0.47 0.64 0.96 0.37 0.46 0.64 0.98 1.71 0.23 0.26 0.36 0.53 0.85 0.27 0.33 0.50 0.86 1.57 100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.21 0.38 0.74 1.44 80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.8 12.1 12.5 13.3 72 MHz 9.24 9.31 9.47 9.69 10.1 10.16 10.7 11.0 11.4 12.2 64 MHz 8.25 8.32 8.46 8.68 9.09 9.08 9.6 9.9 10.3 11.1 Range 1 48 MHz 6.28 6.35 6.5 6.72 7.11 6.91 7.3 7.6 8.0 8.8 32 MHz 4.24 4.30 4.44 4.65 5.04 4.66 4.97 5.26 5.67 6.51 24 MHz 3.21 3.27 3.4 3.61 3.98 3.53 3.76 4.05 4.46 5.30 16 MHz 2.19 2.24 2.36 2.56 2.94 2.41 2.66 2.95 3.16 3.99 2 MHz 272 303 413 592 958 330 393 579 954 1704 1 MHz 154 184 293 473 835 195 265 457 822 1572 400 kHz 78 108 217 396 758 110 180 380 755 1505 100 kHz 42 73 182 360 723 75 138 331 706 1456 fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI Low-power all peripherals disable run mode 25 °C 55 °C 85 °C 26 MHz 2.88 2.93 3.05 3.23 3.58 16 MHz 1.83 1.87 1.98 2.16 8 MHz 0.98 1.02 1.12 4 MHz 0.55 0.59 2 MHz 0.34 1 MHz fHCLK 1. Guaranteed by characterization results, unless otherwise specified. 105 °C 125 °C 25 °C 105 °C 125 °C mA µA 125/270 Electrical characteristics IDD_ALL (LPRun) Unit 55 °C Range 2 IDD_ALL (Run) MAX(1) TYP STM32L476xx Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) Conditions(1) Symbol Unit - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS10198 Rev 8 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 3.67 3.70 3.77 3.85 3.99 72 MHz 3.32 3.35 3.40 3.48 3.63 64 MHz 2.97 2.99 3.04 3.12 3.27 48 MHz 2.26 2.28 2.34 2.42 2.56 32 MHz 1.52 1.55 1.60 1.67 1.81 24 MHz 1.15 1.18 1.22 1.30 1.43 16 MHz 0.79 0.81 0.85 0.92 1.06 8 MHz 0.42 0.44 0.48 0.56 0.70 4 MHz 0.24 0.25 0.30 0.37 0.51 2 MHz 0.15 0.16 0.20 0.28 0.41 1 MHz 0.10 0.11 0.16 0.23 0.37 100 kHz 0.06 0.07 0.12 0.19 0.32 Electrical characteristics 126/270 Table 28. Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L476xx Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Run) DS10198 Rev 8 IDD_ALL (LPRun) fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable MAX(1) TYP Unit 25 °C 55 °C 85 °C 26 MHz 3.15 3.19 3.31 3.50 3.85 16 MHz 2.24 2.28 2.39 2.57 8 MHz 1.26 1.29 1.40 1.57 4 MHz 0.71 0.75 0.85 2 MHz 0.42 0.45 1 MHz 0.27 0.30 100 kHz 0.14 80 MHz 10.0 fHCLK 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3.47 3.70 3.84 4.26 4.88 2.90 2.46 2.60 2.74 3.16 3.78 1.89 1.40 1.50 1.64 2.06 2.68 1.02 1.34 0.79 0.88 1.06 1.38 2.21 0.55 0.72 1.04 0.46 0.55 0.73 1.09 1.88 0.40 0.57 0.89 0.30 0.38 0.57 0.90 1.61 0.17 0.27 0.43 0.75 0.17 0.22 0.40 0.74 1.44 10.1 10.3 10.6 11.0 11.00 11.35 11.64 12.26 13.10 72 MHz 9.06 9.13 9.28 9.51 9.92 9.97 10.36 10.65 11.06 11.69 64 MHz 8.96 9.04 9.22 9.48 9.92 9.86 10.25 10.54 10.95 11.79 Range 1 48 MHz 7.64 7.72 7.91 8.17 8.62 8.40 8.76 8.90 9.52 10.36 32 MHz 5.49 5.57 5.74 5.98 6.40 6.04 6.40 6.69 7.10 7.94 24 MHz 4.16 4.22 4.36 4.57 4.96 4.60 4.86 5.15 5.56 6.19 16 MHz 2.93 2.99 3.13 3.35 3.75 3.22 3.43 3.72 4.13 4.97 2 MHz 358 392 503 683 1050 435 501 694 1069 1819 1 MHz 197 230 340 519 880 245 312 512 887 1637 400 kHz 97 126 235 414 778 130 202 402 777 1527 100 kHz 47 77 186 365 726 85 147 347 711 1472 Supply current in fHCLK = fMSI Low-power all peripherals disable run mA µA 127/270 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L476xx Table 29. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable Conditions(1) Symbol Unit - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS10198 Rev 8 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 3.59 3.63 3.70 3.81 3.95 72 MHz 3.26 3.28 3.34 3.42 3.57 64 MHz 3.22 3.25 3.31 3.41 3.57 48 MHz 2.75 2.78 2.84 2.94 3.10 32 MHz 1.97 2.00 2.06 2.15 2.30 24 MHz 1.50 1.52 1.57 1.64 1.78 16 MHz 1.05 1.07 1.13 1.20 1.35 8 MHz 0.54 0.56 0.60 0.68 0.82 4 MHz 0.31 0.32 0.37 0.44 0.58 2 MHz 0.18 0.19 0.24 0.31 0.45 1 MHz 0.12 0.13 0.17 0.25 0.38 100 kHz 0.06 0.07 0.12 0.19 0.32 Electrical characteristics 128/270 Table 30. Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L476xx Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Run) Supply current in Run mode DS10198 Rev 8 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 IDD_ALL (LPRun) Supply current in low-power run mode fHCLK = fMSI all peripherals disable FLASH in power-down MAX(1) TYP fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 26 MHz 2.88 2.94 3.05 3.23 3.58 3.18 3.26 3.40 4.02 4.65 16 MHz 1.83 1.87 1.98 2.15 2.50 2.01 2.16 2.30 2.72 3.34 8 MHz 0.97 1.00 1.11 1.27 1.62 1.07 1.16 1.32 1.73 2.36 4 MHz 0.54 0.57 0.67 0.84 1.18 0.59 0.69 0.88 1.23 1.96 2 MHz 0.33 0.36 0.46 0.62 0.96 0.37 0.45 0.63 0.98 1.70 1 MHz 0.22 0.25 0.35 0.51 0.85 0.25 0.33 0.50 0.86 1.57 100 kHz 0.12 0.15 0.25 0.41 0.75 0.15 0.21 0.39 0.74 1.45 80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.57 11.86 12.07 13.11 72 MHz 9.25 9.31 9.46 9.68 10.1 10.18 10.41 10.55 10.76 11.80 64 MHz 8.25 8.31 8.46 8.67 9.08 9.08 9.37 9.66 9.87 10.91 48 MHz 6.26 6.33 6.48 6.69 7.11 6.89 7.11 7.25 7.67 8.50 32 MHz 4.22 4.28 4.42 4.63 5.03 4.64 4.86 5.15 5.56 6.19 24 MHz 3.20 3.25 3.38 3.59 3.99 3.52 3.70 3.84 4.26 5.09 16 MHz 2.18 2.22 2.35 2.55 2.94 2.40 2.55 2.84 3.25 4.09 2 MHz 242 275 384 562 924 300 380 573 927 1677 1 MHz 130 162 269 445 809 180 243 435 810 1560 400 kHz 61 90 197 374 734 95 160 353 728 1478 100 kHz 26 56 163 339 702 55 122 314 679 1429 mA µA 129/270 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. Unit STM32L476xx Table 31. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 Conditions(1) Symbol TYP Parameter Unit - IDD_ALL(Run) Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS10198 Rev 8 25 °C 55 °C 85 °C 80 MHz 3.67 3.70 3.77 3.85 3.99 72 MHz 3.33 3.35 3.40 3.48 3.63 64 MHz 2.97 2.99 3.04 3.12 3.26 48 MHz 2.25 2.28 2.33 2.40 2.56 32 MHz 1.52 1.54 1.59 1.66 1.81 24 MHz 1.15 1.17 1.22 1.29 1.43 16 MHz 0.78 0.80 0.84 0.92 1.06 8 MHz 0.42 0.43 0.48 0.55 0.70 4 MHz 0.23 0.25 0.29 0.36 0.51 2 MHz 0.14 0.16 0.20 0.27 0.41 1 MHz 0.09 0.11 0.15 0.22 0.37 100 kHz 0.05 0.06 0.11 0.18 0.32 fHCLK 105 °C 125 °C Electrical characteristics 130/270 Table 32. Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L476xx STM32L476xx Electrical characteristics Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Parameter Supply current in Run mode Range 2 fHCLK = 26 MHz IDD_ALL (Run) fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Code 25 °C Reduced code(1) 2.9 111 Coremark 3.1 118 Dhrystone 2.1 3.1 Fibonacci 2.9 112 2.8 108 Reduced code 10.2 127 Coremark 10.9 136 Dhrystone 2.1 11.0 Fibonacci 10.5 131 9.9 124 Reduced code 272 136 Coremark 291 145 Dhrystone 2.1 302 Fibonacci 269 135 While(1) 269 135 While(1) (1) Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run Unit 25 °C While(1) (1) IDD_ALL (LPRun) TYP Unit Voltage scaling - Range 1 fHCLK = 80 MHz Symbol TYP mA mA µA 119 137 151 µA/MHz µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 34. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz IDD_ALL (Run) Parameter fHCLK = 80 MHz Symbol TYP Code 25 °C Reduced code(2) 1.25 TYP Unit 25 °C 48 Coremark 1.34 51 Dhrystone 2.1 1.34 51 Fibonacci 1.25 48 While(1) 1.21 Reduced code(2) 3.67 mA 46 46 Coremark 3.92 49 Dhrystone 2.1 3.95 49 Fibonacci 3.77 47 While(1) 3.56 44 DS10198 Rev 8 Unit µA/MHz 131/270 238 Electrical characteristics STM32L476xx 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 35. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.14 44 Coremark 1.22 47 Dhrystone 2.1 1.22 Fibonacci 1.14 44 While(1) 1.10 42 mA Unit 25 °C 47 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 36. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable Conditions Parameter - IDD_ALL (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code IDD_ALL (LPRun) 25 °C Reduced code(1) 3.1 119 Coremark 2.9 Dhrystone 2.1 2.8 Fibonacci 2.7 104 While(1) 2.6 100 10.0 125 9.4 117 Reduced code(1) Coremark 111 mA mA 111 Dhrystone 2.1 9.1 Fibonacci 9.0 112 While(1) 9.3 116 code(1) 114 358 179 Coremark 392 196 Dhrystone 2.1 390 Fibonacci 385 192 While(1) 385 192 1. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. 132/270 Unit 25 °C Reduced Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit DS10198 Rev 8 µA 195 µA/MHz µA/MHz µA/MHz STM32L476xx Electrical characteristics Table 37. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.34 TYP Unit Unit 25 °C 51 Coremark 1.25 48 Dhrystone 2.1 1.21 46 Fibonacci 1.16 45 While(1) 1.12 Reduced code(2) 3.59 mA 43 45 Coremark 3.38 42 Dhrystone 2.1 3.27 41 Fibonacci 3.24 40 While(1) 3.34 42 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 38. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals Voltage scaling fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.22 TYP Unit 25 °C Unit 47 Coremark 1.14 Dhrystone 2.1 1.10 44 Fibonacci 1.06 41 While(1) 1.02 39 mA 42 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. DS10198 Rev 8 133/270 238 Electrical characteristics STM32L476xx Table 39. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions Parameter IDD_ALL (Run) IDD_ALL (LPRun) fHCLK = fHSE up to 48 MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit Voltage scaling - Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code Unit 25 °C 25 °C Reduced code(1) 2.9 111 Coremark 2.9 111 mA Dhrystone 2.1 2.9 Fibonacci 2.6 100 While(1) 2.6 100 Reduced code(1) 10.2 127 Coremark 10.4 Dhrystone 2.1 10.3 Fibonacci 9.6 111 130 mA 129 9.3 116 Reduced code(1) 242 121 242 Dhrystone 2.1 242 µA/MHz 120 While(1) Coremark µA/MHz 121 µA 121 Fibonacci 225 112 While(1) 242 121 µA/MHz 1. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 40. Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.25 TYP Unit 25 °C Unit 48 Coremark 1.25 48 Dhrystone 2.1 1.25 48 Fibonacci 1.12 43 While(1) 1.12 Reduced code(2) 3.67 Coremark 3.74 47 Dhrystone 2.1 3.70 46 Fibonacci 3.45 43 While(1) 3.34 42 mA 43 46 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. 134/270 DS10198 Rev 8 STM32L476xx Electrical characteristics Table 41. Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.14 44 Coremark 1.14 44 Dhrystone 2.1 1.14 Fibonacci 1.02 39 While(1) 1.02 39 mA 25 °C 44 Unit µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. DS10198 Rev 8 135/270 238 Conditions Symbol Parameter - Voltage scaling Unit fHCLK 26 MHz IDD_ALL (Sleep) DS10198 Rev 8 IDD_ALL (LPSleep) 25 °C 55 °C 85 °C 0.92 1.07 0.96 105 °C 125 °C 25 °C 1.25 1.59 1.012 55 °C 85 °C 1.14 1.36 105 °C 125 °C 1.77 2.40 16 MHz 0.61 0.65 0.75 0.92 1.27 0.69 0.78 0.97 1.32 2.04 8 MHz 0.36 0.40 0.50 0.66 1.01 0.42 0.50 0.68 1.03 1.75 4 MHz 0.24 0.27 0.37 0.53 0.87 0.28 0.36 0.54 0.89 1.60 2 MHz 0.18 0.20 0.30 0.47 0.81 0.215 0.29 0.46 0.82 1.53 1 MHz 0.15 0.17 0.27 0.43 0.77 0.18 0.25 0.44 0.78 1.49 100 kHz 0.12 0.14 0.24 0.41 0.74 0.15 0.21 0.39 0.74 1.44 80 MHz 2.96 3.00 3.13 3.33 3.73 3.26 3.43 3.72 4.13 4.97 72 MHz 2.69 2.73 2.85 3.05 3.45 2.96 3.21 3.50 3.71 4.54 64 MHz 2.41 2.45 2.58 2.77 3.17 2.65 2.88 3.17 3.58 4.21 Range 1 48 MHz 1.88 1.93 2.07 2.27 2.67 2.10 2.27 2.41 2.83 3.66 32 MHz 1.30 1.35 1.48 1.68 2.08 1.43 1.56 1.85 2.26 3.10 24 MHz 1.01 1.05 1.17 1.37 1.76 1.11 1.23 1.52 1.93 2.77 16 MHz 0.71 0.75 0.87 1.07 1.45 0.80 0.90 1.19 1.60 2.44 2 MHz 96 126 233 412 775 130 202 402 777 1527 1 MHz 65 94 202 381 742 95 166 358 733 1483 400 kHz 43 73 181 359 718 75 138 331 706 1456 100 kHz 33 63 171 348 708 65 128 322 691 1441 Range 2 Supply current in sleep mode, MAX(1) TYP fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Supply current in =f f low-power HCLK MSI all peripherals disable sleep mode Electrical characteristics 136/270 Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L476xx Conditions(1) Symbol TYP Parameter Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 1.06 1.08 1.13 1.20 1.34 72 MHz 0.97 0.98 1.02 1.10 1.24 64 MHz 0.87 0.88 0.93 1.00 1.14 48 MHz 0.68 0.69 0.74 0.82 0.96 32 MHz 0.47 0.49 0.53 0.60 0.75 24 MHz 0.36 0.38 0.42 0.49 0.63 16 MHz 0.26 0.27 0.31 0.38 0.52 8 MHz 0.16 0.17 0.22 0.28 0.44 4 MHz 0.10 0.12 0.16 0.23 0.38 2 MHz 0.08 0.09 0.13 0.20 0.35 1 MHz 0.06 0.07 0.12 0.19 0.33 100 kHz 0.05 0.06 0.10 0.18 0.32 - IDD_ALL(Sleep) Supply current in sleep mode, fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable STM32L476xx Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) mA DS10198 Rev 8 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V Table 44. Current consumption in Low-power sleep modes, Flash in power-down Conditions Symbol Parameter - fHCLK = fMSI all peripherals disable Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 2 MHz 81 110 217 395 754 115 182 375 750 1500 1 MHz 50 78 185 362 720 80 149 342 717 1456 400 kHz 28 57 163 340 698 60 122 314 689 1429 100 kHz 18 47 155 332 686 50 114 313 688 1438 1. Guaranteed by characterization results, unless otherwise specified. µA 137/270 Electrical characteristics IDD_ALL (LPSleep) Supply current in low-power sleep mode Voltage scaling MAX(1) TYP Symbol Parameter Conditions - LCD disabled IDD_ALL (Stop 2) Supply current in Stop 2 mode, RTC disabled 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 1.8 V 1.14 3.77 14.7 34.7 77 2.4 V 1.15 3.86 15 35.5 3V 1.18 3.97 15.4 36.4 105 °C 125 °C 2.7 9 37 87 193 79.1 2.7 10 38 89 198 81.3 2.8 10 39 91 203 (2) 16 38 85.1 3.0 10 40 1.8 V 1.43 3.98 15 35 77.3 3.2 10 38 2.4 V 1.49 4.07 15.3 35.8 79.4 3.2 10 38 90 199 3V 1.54 4.24 15.7 36.7 81.6 3.3 11 39 92 204 3.6 V 1.75 4.47 16.1 38.3 85.4 3.5 11 40 96 214 1.8 V 1.42 4.04 15 34.9 77.2 3.1 10 38 87 193 2.4 V 1.5 4.22 15.4 35.7 79.2 3.2 11 39 89 198 3V 1.64 4.37 15.8 36.7 81.4 3.4 11 40 92 204 3.6 V 1.79 4.65 16.6 38.4 85.4 3.6 12 42 96 214 1.8 V 1.53 4.07 15.1 35.1 77.4 3.3 10 38 88 194 2.4 V 1.62 4.32 15.5 35.9 79.5 3.4 11 39 90 199 3V 1.69 4.43 15.9 36.8 81.7 3.5 11 40 92 204 3.6 V 1.86 4.65 16.7 38.5 85.5 3.7 12 42 96 214 1.8 V 1.5 4.13 15.2 35.3 77.6 3.2 10 38 88 194 RTC clocked by LSE 2.4 V bypassed at 32768Hz,LCD disabled 3 V 3.6 V 1.63 4.33 15.6 36 79.6 3.4 11 39 90 199 1.79 4.55 16.1 37 81.8 3.6 11 40 93 205 2.04 4.9 16.8 38.7 85.6 3.9 12 42 97 214 1.8 V 1.43 3.99 14.7 35 - 3.2 10 37 88 - 2.4 V 1.54 4.11 15 35.8 - 3.3 10 38 90 - 3V 1.67 4.29 15.5 36.7 - 3.4 11 39 92 - 3.6 V 1.87 4.57 16.2 38.3 - 3.7 11 41 96 - DS10198 Rev 8 RTC clocked by LSE quartz(4) in low drive mode, LCD disabled 88 193 Unit µA µA STM32L476xx 4.11 RTC clocked by LSI, LCD enabled(3) 95 213 1.26 RTC clocked by LSI, LCD disabled Supply current in Stop 2 mode, RTC enabled VDD 3.6 V LCD enabled(3) clocked by LSI IDD_ALL (Stop 2 with RTC) MAX(1) TYP Electrical characteristics 138/270 Table 45. Current consumption in Stop 2 mode Symbol Parameter Supply current IDD_ALL during wakeup (wakeup from from Stop 2 Stop 2) mode Conditions - MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C Wakeup clock is MSI = 48 MHz, voltage Range 1. See (5). 3V 1.9 - - - - Wakeup clock is MSI = 4 MHz, voltage Range 2. See (5). 3V 2.24 - - - - Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (5). 3V 2.1 - - - - 55 °C 85 °C - 105 °C 125 °C Unit STM32L476xx Table 45. Current consumption in Stop 2 mode (continued) mA DS10198 Rev 8 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. Electrical characteristics 139/270 Symbol Parameter Conditions - IDD_ALL (Stop 1) Supply current in Stop 1 mode, RTC disabled - LCD disabled LCD enabled(2) clocked by LSI DS10198 Rev 8 LCD disabled RTC clocked by LSI Supply current IDD_ALL in stop 1 (Stop 1 with mode, RTC) RTC enabled RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz(3) in low drive mode LCD enabled(2) LCD disabled LCD disabled MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 6.59 24.7 92.7 208 437 16 62 232 520 1093 2.4 V 6.65 24.8 92.9 209 439 17 62 232 523 1098 3V 6.65 24.9 93.3 210 442 17 62 233 525 1105 3.6 V 6.70 25.1 93.8 212 447 17 63 235 530 1118 1.8 V 7.00 25.2 97.2 219 461 18 63 243 548 1153 2.4 V 7.14 25.4 97.5 220 463 18 64 244 550 1158 3V 7.24 25.7 97.7 221 465 18 64 244 553 1163 3.6 V 7.36 26.1 98.7 223 471 18 65 247 558 1178 1.8 V 6.88 25.0 93.1 209 439 17 63 233 523 1098 2.4 V 7.02 25.2 93.7 210 441 18 63 234 525 1103 3V 7.12 25.4 94.2 212 444 18 64 236 530 1110 3.6 V 7.25 25.7 95.2 214 449 18 64 238 535 1123 1.8 V 7.01 26.1 99.0 223 467 18 65 248 558 1168 2.4 V 7.14 26.3 99.6 225 470 18 66 249 563 1175 3V 7.31 26.6 100.0 226 474 18 67 250 565 1185 3.6 V 7.41 26.9 102.0 229 480 19 67 255 573 1200 1.8 V 6.91 25.2 93.4 210 440 17 63 234 525 1100 2.4 V 7.04 25.3 94.2 211 443 18 63 236 528 1108 3V 7.19 25.7 95.0 212 446 18 64 238 530 1115 3.6 V 7.97 26.0 96.1 215 451 20 65 240 538 1128 1.8 V 6.85 25.0 93.0 208.3 - 17 63 233 521 - 2.4 V 6.94 25.1 93.2 209.3 - 17 63 233 523 - 3V 7.10 25.2 93.6 210.3 - 18 63 234 526 - 3.6 V 7.34 25.4 94.1 212.3 - 18 64 235 531 - Unit µA Electrical characteristics 140/270 Table 46. Current consumption in Stop 1 mode µA STM32L476xx Symbol Parameter Conditions - - Wakeup clock MSI = 48 MHz, voltage Range 1. See (4). Supply current Wakeup clock MSI = 4 MHz, IDD_ALL voltage Range 2. during (wakeup wakeup from See (4). from Stop1) Stop 1 Wakeup clock HSI16 = 16 MHz, voltage Range 1. See (4). MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3V 1.47 - - - - 3V 1.7 - - - - 3V 1.62 - - - - - Unit STM32L476xx Table 46. Current consumption in Stop 1 mode (continued) mA 1. Guaranteed by characterization results, unless otherwise specified. DS10198 Rev 8 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. Electrical characteristics 141/270 Symbol Parameter IDD_ALL (Stop 0) Supply current in Stop 0 mode, RTC disabled Conditions VDD MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 108 132 217 356 631 153 213 426 773 1461 2.4 V 110 134 219 358 634 158 218 431 778 1468 3V 111 135 220 360 637 161 221 433 783 1476 3.6 V 113 137 222 363 642 166 226 438 791(2) 1488 1. Guaranteed by characterization results, unless otherwise specified. Unit µA Electrical characteristics 142/270 Table 47. Current consumption in Stop 0 mode 2. Guaranteed by test in production. DS10198 Rev 8 STM32L476xx Symbol IDD_ALL (Standby) Parameter Supply current in Standby mode (backup registers retained), RTC disabled Conditions - no independent watchdog with independent watchdog DS10198 Rev 8 RTC clocked by LSI, no independent watchdog IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC enabled RTC clocked by LSI, with independent watchdog RTC clocked by LSE bypassed at 32768Hz MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 114 355 1540 4146 10735 176 888 3850 10365 26838 2.4 V 138 407 1795 4828 12451 223 1018 4488 12070 31128 3V 150 486 2074 5589 14291 263 1215 5185 13973 35728 3.6 V 198 618 2608 6928 17499 383 1545 6520 1.8 V 317 - - - - - - 2.4 V 391 - - - - - - 17320 (2) 43748 - - - - - - 3V 438 - - - - - - - - - 3.6 V 566 - - - - - - - - - 1.8 V 377 621 1873 4564 11318 491 1207 4250 10867 27537 2.4 V 464 756 2210 5348 13166 614 1436 4986 12694 31986 3V 572 913 2599 6219 15197 770 1727 5815 14729 36815 3.6 V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184 1.8 V 456 - - - - - - - - - 2.4 V 557 - - - - - - - - - 3V 663 - - - - - - - - - 3.6 V 885 - - - - - - - - - 1.8 V 289 527 1747 4402 11009 - - - - - 2.4 V 396 671 2108 5202 12869 - - - - - 528 853 2531 6095 14915 - - - - - 710 1111 3115 7470 18221 - - - - - 1.8 V 416 640 1862 4479 11908 - - - - - 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 514 796 2193 5236 13689 - - - - - 652 961 2589 6103 15598 - - - - - 3.6 V 821 1226 3235 7551 17947 - - - - - nA nA nA 143/270 Electrical characteristics 3V 3.6 V Unit STM32L476xx Table 48. Current consumption in Standby mode Symbol IDD_ALL (SRAM2)(4) IDD_ALL (wakeup from Standby) Conditions Parameter Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode - VDD - Wakeup clock is MSI = 4 MHz. See (5). MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 235 641 2293 5192 11213 588 1603 5733 12980 28033 2.4 V 237 645 2303 5213 11246 593 1613 5758 13033 28115 3V 236 647 2306 5221 11333 593 1618 5765 13053 28333 3.6 V 235 646 2308 5200 11327 595 1620 5770 13075 28350 3V 1.7 - - - - - Unit nA Electrical characteristics 144/270 Table 48. Current consumption in Standby mode (continued) mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. DS10198 Rev 8 4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby + RTC) + IDD_ALL(SRAM2). 5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. Table 49. Current consumption in Shutdown mode Symbol IDD_ALL (Shutdown) Parameter Supply current in Shutdown mode (backup registers retained) RTC disabled Conditions - - MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 1.8 V 29.8 194 1110 3250 9093 2.4 V 44.3 237 1310 3798 3V 64.1 293 1554 3.6 V 112 420 2041 105 °C 125 °C 75 485 2775 8125 22733 10473 111 593 3275 9495 26183 4461 12082 160 733 3885 11153 30205 5689 15186 280 1050 5103 14223 37965 Unit nA STM32L476xx Symbol IDD_ALL (Shutdown with RTC) Parameter Supply current in Shutdown mode (backup registers retained) RTC enabled DS10198 Rev 8 Supply current IDD_ALL during wakeup (wakeup from from Shutdown Shutdown) mode Conditions - RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz (2) in low drive mode Wakeup clock is MSI = 4 MHz. See (3). MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 210 378 1299 3437 9357 - - - - - 2.4 V 303 499 1577 4056 10825 - - - - - 3V 422 655 1925 4820 12569 - - - - - 3.6 V 584 888 2511 6158 15706 - - - - - 1.8 V 329 499 1408 3460 - - - - - - 2.4 V 431 634 1688 4064 - - - - - - 3V 554 791 2025 4795 - - - - - - 3.6 V 729 1040 2619 6129 - - - - - - 3V 0.6 - - - - - - - - - Unit STM32L476xx Table 49. Current consumption in Shutdown mode (continued) nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. Electrical characteristics 145/270 Symbol Parameter Conditions - RTC disabled IDD_VBAT RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz DS10198 Rev 8 RTC enabled and clocked by LSE quartz(2) MAX(1) TYP VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 73 490 1468 4158 1.8 V 4 29 196 587 1663 10.8 2.4 V 5.27 36 226 673 1884 13.2 90 565 1683 4710 3V 6 42 264 775 2147 15.5 106 660 1938 5368 3.6 V 10 58 323 919 2488 25.8 144 808 2298 6220 1.8 V 183 201 367 729 - - - - - - 2.4 V 268 295 486 901 - - - - - - 3V 376 412 602 1075 - - - - - - 3.6 V 508 558 752 1299 - - - - - - 1.8 V 302 344 521 915 1978 - - - - - 2.4 V 388 436 639 1091 2289 - - - - - 3V 494 549 784 1301 2656 - - - - - 3.6 V 630 692 971 1571 3115 - - - - - Unit Electrical characteristics 146/270 Table 50. Current consumption in VBAT mode nA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. STM32L476xx STM32L476xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 70: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 51: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DS10198 Rev 8 147/270 238 Electrical characteristics STM32L476xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 51. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 20: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 51. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 51. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus Matrix(1) 4.5 3.7 4.1 ADC independent clock domain 0.4 0.1 0.2 ADC AHB clock domain 5.5 4.7 5.5 CRC 0.4 0.2 0.3 DMA1 1.4 1.3 1.4 DMA2 1.5 1.3 1.4 FLASH 6.2 5.2 5.8 FMC 8.9 7.5 8.4 GPIOA(2) 4.8 3.8 4.4 (2) 4.8 4.0 4.6 GPIOC(2) 4.5 3.8 4.3 (2) GPIOD 4.6 3.9 4.4 GPIOE(2) 5.2 4.5 4.9 GPIOF(2) 5.9 4.9 5.7 (2) 4.3 3.8 4.2 (2) GPIOH 0.7 0.6 0.8 OTG_FS independent clock domain 23.2 N/A N/A OTG_FS AHB clock domain 16.4 N/A N/A QUADSPI 7.8 6.7 7.3 RNG independent clock domain 2.2 N/A N/A RNG AHB clock domain 0.6 N/A N/A SRAM1 0.9 0.8 0.9 Peripheral GPIOB AHB GPIOG 148/270 DS10198 Rev 8 Unit µA/MHz STM32L476xx Electrical characteristics Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep SRAM2 1.6 1.4 1.6 TSC 1.8 1.4 1.6 118.5 77.3 87.6 AHB to APB1 bridge 0.9 0.7 0.9 CAN1 4.6 4.0 4.4 DAC1 2.4 1.9 2.2 I2C1 independent clock domain 3.7 3.1 3.2 I2C1 APB clock domain 1.3 1.1 1.5 I2C2 independent clock domain 3.7 3.0 3.2 I2C2 APB clock domain 1.4 1.1 1.5 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 APB clock domain 0.9 0.9 1.1 LCD 1.0 0.8 0.9 LPUART1 independent clock domain 2.1 1.6 2.0 LPUART1 APB clock domain 0.6 0.6 0.6 LPTIM1 independent clock domain 3.3 2.6 2.9 LPTIM1 APB clock domain 0.9 0.8 1.0 LPTIM2 independent clock domain 3.1 2.7 2.9 LPTIM2 APB clock domain 0.8 0.6 0.7 OPAMP 0.4 0.4 0.3 PWR 0.5 0.5 0.4 SPI2 1.8 1.6 1.6 SPI3 2.1 1.7 1.8 SWPMI1 independent clock domain 2.3 1.8 2.2 SWPMI1 APB clock domain 1.1 1.1 1.0 TIM2 6.8 5.7 6.3 TIM3 5.4 4.6 5.0 TIM4 5.2 4.4 4.9 TIM5 6.5 5.5 6.1 TIM6 1.1 1.0 1.0 TIM7 1.1 0.9 1.0 Peripheral AHB All AHB Peripherals (3) APB1 DS10198 Rev 8 Unit µA/MHz µA/MHz 149/270 238 Electrical characteristics STM32L476xx Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep USART2 independent clock domain 4.1 3.6 3.8 USART2 APB clock domain 1.4 1.1 1.5 USART3 independent clock domain 4.7 4.1 4.2 USART3 APB clock domain 1.5 1.3 1.7 UART4 independent clock domain 3.9 3.2 3.5 UART4 APB clock domain 1.5 1.3 1.6 UART5 independent clock domain 3.9 3.2 3.5 UART5 APB clock domain 1.3 1.2 1.4 WWDG 0.5 0.5 0.5 All APB1 on 84.2 70.7 80.2 AHB to APB2 bridge(4) 1.0 0.9 0.9 DFSDM1 5.6 4.6 5.3 FW 0.7 0.5 0.7 SAI1 independent clock domain 2.6 2.1 2.3 SAI1 APB clock domain 2.1 1.8 2.0 SAI2 independent clock domain 3.3 2.7 3.0 SAI2 APB clock domain 2.4 2.1 2.2 SDMMC1 independent clock domain 4.7 3.9 4.2 SDMMC1 APB clock domain 2.5 1.9 2.1 SPI1 2.0 1.6 1.9 SYSCFG/VREFBUF/COMP 0.6 0.4 0.5 TIM1 8.3 6.9 7.9 TIM8 8.6 7.1 8.1 TIM15 4.1 3.4 3.9 TIM16 3.0 2.5 2.9 TIM17 3.0 2.4 2.9 USART1 independent clock domain 4.9 4.0 4.4 USART1 APB clock domain 1.5 1.3 1.7 All APB2 on 56.8 43.3 48.2 256.8 189.6 215.5 Peripheral APB1 APB2 ALL 150/270 DS10198 Rev 8 Unit µA/MHz STM32L476xx Electrical characteristics 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes). 3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1. 4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2. The consumption for the peripherals when using SMPS can be found using STM32CubeMX PCC tool. 6.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 52 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 52. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Conditions Typ Max - 6 6 Wakeup time from Sleep mode to Run mode Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz Range 1 Wake up time from Stop 0 mode to Run mode in Flash Range 2 tWUSTOP0 Range 1 Wake up time from Stop 0 mode to Run mode in SRAM1 Range 2 6 9.3 Wakeup clock MSI = 48 MHz 5.6 10.9 Wakeup clock HSI16 = 16 MHz 4.7 10.4 Wakeup clock MSI = 24 MHz 5.7 11.1 Wakeup clock HSI16 = 16 MHz 4.5 10.5 Wakeup clock MSI = 4 MHz 6.6 14.2 Wakeup clock MSI = 48 MHz 0.7 2.05 Wakeup clock HSI16 = 16 MHz 1.7 2.8 Wakeup clock MSI = 24 MHz 0.8 2.72 Wakeup clock HSI16 = 16 MHz 1.7 2.8 Wakeup clock MSI = 4 MHz 2.4 11.32 DS10198 Rev 8 Unit Nb of CPU cycles µs 151/270 238 Electrical characteristics STM32L476xx Table 52. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 1 mode to Run mode in Flash Range 2 Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Run mode in SRAM1 Wake up time from Stop 1 mode to Low-power run mode in Flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 Range 2 Wake up time from Stop 2 mode to Run mode in Flash Range 2 tWUSTOP2 Range 1 tWUSTBY tWUSTBY SRAM2 tWUSHDN Max Wakeup clock MSI = 48 MHz 6.2 10.2 Wakeup clock HSI16 = 16 MHz 6.3 8.99 Wakeup clock MSI = 24 MHz 6.3 10.46 Wakeup clock HSI16 = 16 MHz 6.3 Wakeup clock MSI = 4 MHz 8.0 13.23 Wakeup clock MSI = 48 MHz 4.5 5.78 Wakeup clock HSI16 = 16 MHz 5.5 7.1 Wakeup clock MSI = 24 MHz 5.0 6.5 Wakeup clock HSI16 = 16 MHz 5.5 7.1 Wakeup clock MSI = 4 MHz 8.2 13.5 12.7 20 Regulator in low-power Wakeup clock MSI = 2 MHz mode (LPR=1 in PWR_CR1) Range 1 Wake up time from Stop 2 mode to Run mode in SRAM1 Typ Range 2 Wakeup time from Standby mode to Run mode Range 1 Wakeup time from Standby with SRAM2 to Run mode Range 1 Wakeup time from Shutdown mode to Run mode Range 1 152/270 8.87 8.0 9.4 Wakeup clock HSI16 = 16 MHz 7.3 9.3 Wakeup clock MSI = 24 MHz 8.2 9.9 Wakeup clock HSI16 = 16 MHz 7.3 9.3 Wakeup clock MSI = 4 MHz 10.6 15.8 Wakeup clock MSI = 48 MHz 5.1 6.7 Wakeup clock HSI16 = 16 MHz 5.7 8 Wakeup clock MSI = 24 MHz 5.5 6.65 Wakeup clock HSI16 = 16 MHz 5.7 7.53 Wakeup clock MSI = 4 MHz 8.2 16.6 Wakeup clock MSI = 8 MHz 14.3 20.8 Wakeup clock MSI = 4 MHz 20.1 35.5 Wakeup clock MSI = 8 MHz 14.3 24.3 Wakeup clock MSI = 4 MHz 20.1 38.5 Wakeup clock MSI = 4 MHz 256 330.6 DS10198 Rev 8 µs 10.7 21.5 Wakeup clock MSI = 48 MHz 1. Guaranteed by characterization results. Unit µs µs µs µs STM32L476xx Electrical characteristics Table 53. Regulator modes transition times(1) Symbol Parameter tWULPRUN tVOST Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Unit µs Code run with MSI 24 MHz 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. Table 54. Wakeup time using USART/LPUART(1) Symbol Parameter tWUUSART tWULPUART Conditions Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is HSI16 Unit µs 1. Guaranteed by design. 6.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 23: High-speed external clock source AC timing diagram. Table 55. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 - - tw(HSEH) OSC_IN high or low time tw(HSEL) Unit V ns 1. Guaranteed by design. DS10198 Rev 8 153/270 238 Electrical characteristics STM32L476xx Figure 23. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 24. Table 56. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 24. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 154/270 DS10198 Rev 8 STM32L476xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 57. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 57. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 25). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. DS10198 Rev 8 155/270 238 Electrical characteristics Note: STM32L476xx For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 25. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 58. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 58. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time 156/270 Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - DS10198 Rev 8 Unit nA µA/V s STM32L476xx Electrical characteristics 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 26. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DS10198 Rev 8 157/270 238 Electrical characteristics 6.3.8 STM32L476xx Internal clock source characteristics The parameters given in Table 59 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 59. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step DuCy(HSI16)(2) Duty Cycle Conditions Min Typ Max Unit 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % VDD=3.0 V, TA=30 °C - % ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA 1. Guaranteed by characterization results. 2. Guaranteed by design. 158/270 DS10198 Rev 8 STM32L476xx Electrical characteristics Figure 27. HSI16 frequency versus temperature MHz 16.4 +2 % 16.3 +1.5 % 16.2 +1 % 16.1 16 15.9 -1 % 15.8 -1.5 % 15.7 -2 % 15.6 -40 -20 0 Mean 20 40 60 min 80 100 120 °C max MSv39299V2 DS10198 Rev 8 159/270 238 Electrical characteristics STM32L476xx Multi-speed internal (MSI) RC oscillator Table 60. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 99 100 101 Range 1 198 200 202 Range 2 396 400 404 Range 3 792 800 808 Range 4 0.99 1 1.01 Range 5 1.98 2 2.02 Range 6 3.96 4 4.04 Range 7 7.92 8 8.08 Range 8 15.8 16 16.16 Range 9 23.8 24 24.4 Range 10 31.7 32 32.32 Range 11 47.5 48 48.48 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode fMSI ∆TEMP(MSI)(2) 160/270 MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature MSI mode TA= -0 to 85 °C TA= -40 to 125 °C DS10198 Rev 8 Unit kHz MHz kHz MHz % STM32L476xx Electrical characteristics Table 60. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI) (2) MSI oscillator frequency drift MSI mode over VDD (reference is 3 V) Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(6) Frequency variation in MSI mode sampling mode(3) P_USB Jitter(MSI)(6) Period jitter for USB clock(4) MT_USB Jitter(MSI)(6) Medium term jitter PLL mode for USB clock(5) Range 11 CC jitter(MSI)(6) P jitter(MSI)(6) tSU(MSI)(6) tSTAB(MSI)(6) PLL mode Range 11 Max Unit 0.5 0.7 % 1 % for next transition - - - 3.458 for paired transition - - - 3.916 for next transition - - - 2 for paired transition - - - 1 ns ns RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - ps RMS Period jitter PLL mode Range 11 - - 50 - ps Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 0.5 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator stabilization time PLL mode Range 11 DS10198 Rev 8 us ms 161/270 238 Electrical characteristics STM32L476xx Table 60. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock. 5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles. For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles. For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over 56 cycles. 6. Guaranteed by design. 162/270 DS10198 Rev 8 STM32L476xx Electrical characteristics Figure 28. Typical current consumption versus MSI frequency Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Parameter LSI Frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 μs 5% of final frequency - 125 180 μs - - 110 180 nA LSI oscillator startup time LSI oscillator stabilization time LSI oscillator power consumption Unit kHz 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.9 PLL characteristics The parameters given in Table 62 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. DS10198 Rev 8 163/270 238 Electrical characteristics STM32L476xx Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.0645 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 64 - 344 Voltage scaling Range 2 64 - 128 - 15 40 - 40 - - 30 - VCO freq = 64 MHz - 150 200 VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time - RMS cycle-to-cycle jitter System clock 80 MHz RMS period jitter PLL power consumption on VDD(1) MHz MHz MHz MHz μs ±ps μA 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs. 6.3.10 Flash memory characteristics Table 63. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.95 fast programming 3.91 4.35 22.13 24.59 tERASE tprog_bank tME 164/270 Page (2 KB) erase time one bank (512 Kbyte) programming time - Mass erase time (one or two banks) - DS10198 Rev 8 ms s ms STM32L476xx Electrical characteristics Table 63. Flash memory characteristics(1) (continued) Symbol IDD Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - Unit mA 1. Guaranteed by design. Table 64. Flash memory endurance and data retention Symbol NEND Min(1) Unit TA = –40 to +105 °C 10 kcycles 1 kcycle(2) at TA = 85 °C 30 Parameter Endurance Conditions 1 kcycle tRET Data retention 1 (2) kcycle(2) at TA = 105 °C 15 at TA = 125 °C 7 (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles(2) at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. DS10198 Rev 8 165/270 238 Electrical characteristics 6.3.11 STM32L476xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 65. They are based on the EMS levels and classes defined in application note AN1709. Table 65. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 166/270 • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) DS10198 Rev 8 STM32L476xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 66. EMI characteristics Symbol SEMI 6.3.12 Parameter Monitored frequency band Conditions Max vs. [fHSE/fHCLK] Unit fMSI = 24 MHz 8 MHz / 80 MHz -9 2 -8 3 -10 14 1.5 3.5 0.1 MHz to 30 MHz VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz LQFP144 package Peak level compliant with 130 MHz to 1 GHz IEC 61967-2 EMI Level dBµV - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 67. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions TA = +25 °C, conforming Electrostatic discharge to ANSI/ESDA/JEDEC voltage (human body model) JS-001 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 °C, conforming to ANSI/ESD STM5.3.1 Class Maximum value(1) 2 2000 Unit V C3 250 1. Guaranteed by characterization results. DS10198 Rev 8 167/270 238 Electrical characteristics STM32L476xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 68. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A(1) 1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14. 6.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 69. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 69. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Positive injection Injected current on BOOT0 pin -0 0 Injected current on pins except PA4, PA5, BOOT0 -5 N/A(1) Injected current on PA4, PA5 pins -5 0 1. Injection is not possible. 168/270 Unit Negative injection DS10198 Rev 8 mA STM32L476xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 70 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 70. I/O static characteristics Symbol VIL(1) VIH (1) Parameter Conditions Typ Max Unit I/O input low level voltage except BOOT0 1.62 V