STM32L496ZGT6

STM32L496xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 320 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 25 nA Shutdown mode (5 wakeup pins) – 108 nA Standby mode (5 wakeup pins) – 426 nA Standby mode with RTC – 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with RTC – 91 µA/MHz run mode (LDO Mode) – 37 μA/MHz run mode (@3.3 V SMPS Mode) – Batch acquisition mode (BAM) – 5 µs wakeup from Stop mode – Brown out reset (BOR) in all modes except shutdown – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100 DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 Coremark® (3.42 Coremark/MHz @ 80 MHz) • Energy benchmark – 279 ULPMark™ CP score – 80.2 ULPMark™ PP score • RTC with HW calendar, alarms and calibration This is information on a product in full production. UFBGA169 (7 x 7) UFBGA132 (7 × 7) WLCSP100 • Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V • Dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • 8- to 14-bit camera interface up to 32 MHz (black&white) or 10 MHz (color) • Memories – Up to 1 MB Flash, 2 banks read-whilewrite, proprietary code readout protection – 320 KB of SRAM including 64 KB with hardware parity check – External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories – Dual-flash Quad SPI memory interface • Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) – Internal 48 MHz with clock recovery – 3 PLLs for system clock, USB, audio, ADC • LCD 8 × 40 or 4 × 44 with step-up converter • 16 x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2 x 16-bit basic, 2 x low-power 16-bit timers (available in Stop mode), 2 x watchdogs, SysTick timer September 2018 LQFP144 (20 × 20) LQFP100 (14 x 14) LQFP64 (10 x 10) • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors • 4 x digital filters for sigma delta modulator • Rich analog peripherals (independent supply) – 3 × 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps DS11585 Rev 10 1/280 www.st.com STM32L496xx – – – – – – 2 x 12-bit DAC output channels, low-power sample and hold – 2 x operational amplifiers with built-in PGA – 2 x ultra-low-power comparators • 20 x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2 x SAIs (serial audio interface) – 4 x I2C FM+(1 Mbit/s), SMBus/PMBus – 5 x U(S)ARTs (ISO 7816, LIN, IrDA, modem) 1 x LPUART 3 x SPIs (4 x SPIs with the Quad SPI) 2 x CAN (2.0B Active) and SDMMC SWPMI single wire protocol master I/F IRTIM (Infrared interface) • 14-channel DMA controller • True random number generator • CRC calculation unit, 96-bit unique ID • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ • Table 1. Device summary Reference STM32L496xx 2/280 Part numbers STM32L496AG, STM32L496QG, STM32L496RG, STM32L496VG, STM32L496ZG, STM32L496AE, STM32L496QE, STM32L496RE, STM32L496VE, STM32L496ZE DS11585 Rev 10 STM32L496xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 22 3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.15 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.16 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.17 3.16.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41 3.16.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 41 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DS11585 Rev 10 3/280 6 Contents STM32L496xx 3.17.3 4/280 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.19 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.21 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.24 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 46 3.25 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.26 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.27 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.27.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.27.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.28 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52 3.29 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.30 Universal synchronous/asynchronous receiver transmitter (USART) . . . 54 3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 55 3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.34 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 57 3.35 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.36 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 58 3.37 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 58 3.38 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.39 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 59 3.40 Dual-flash Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . 60 3.41 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS11585 Rev 10 STM32L496xx Contents 3.41.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.41.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 128 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 128 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 185 6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 186 DS11585 Rev 10 5/280 6 Contents 7 STM32L496xx 6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 199 6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 204 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 217 6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 248 6.3.31 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 6.3.32 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 249 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.1 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 7.5 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 274 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6/280 DS11585 Rev 10 STM32L496xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L496xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19 STM32L496xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L496xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32L496xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32L496xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 STM32L496xx memory map and peripheral register boundary addresses . . . . . . . . . . . 118 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 128 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 133 Current consumption in Run modes, code with data processing running from Flash, (ART enable Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 136 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 138 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 139 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DS11585 Rev 10 7/280 10 List of tables Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/280 STM32L496xx Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 141 Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . 141 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 142 Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 143 Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 144 Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 146 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS11585 Rev 10 STM32L496xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. List of tables DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 226 eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 227 USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 233 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 233 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 234 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 235 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 236 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 238 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 243 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 247 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 250 SD / MMC dynamic characteristics, VDD=1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . 250 UFBGA - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 253 LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 262 LQPF - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 WLCSP – 100 ball, 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale DS11585 Rev 10 9/280 10 List of tables STM32L496xx package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Table 130. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 269 Table 131. LQFP - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Table 132. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Table 133. STM32L496xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 134. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 10/280 DS11585 Rev 10 STM32L496xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM32L496xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32L496Ax UFBGA169 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32L496Ax, external SMPS device, UFBGA169 pinout(1) . . . . . . . . . . . . . . . . . . . . . . 62 STM32L496Zx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STM32L496Zx, external SMPS device, LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 64 STM32L496Qx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L496Qx, external SMPS device, UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L496Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L496Vx, external SMPS device, LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 67 STM32L496Vx WLCSP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STM32L496Vx, external SMPS device, WLCSP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . 68 STM32L496Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32L496Rx, external SMPS, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32L496xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Current consumption measurement scheme with and without external SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 229 DS11585 Rev 10 11/280 12 List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. 12/280 STM32L496xx Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 232 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 234 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 235 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 237 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 243 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 246 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 247 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 UFBGA - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 UFBGA - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 UFBGA169, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 255 LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 256 LQFP - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 LQFP144, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 260 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 UFBGA132, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 263 LQFP - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 264 LQFP - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 LQFP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 266 WLCSP – 100 ball, 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 WLCSP – 100 ball, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 WLCSP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 WLCSP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 270 LQFP - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 271 LQFP - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 LQFP64, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . . 273 DS11585 Rev 10 STM32L496xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L496xx microcontrollers. This document should be read in conjunction with the STM32L4x6 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS11585 Rev 10 13/280 61 Description 2 STM32L496xx Description The STM32L496xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L496xx devices embed high-speed memories (up to 1 Mbyte of Flash memory, 320 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L496xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. They also feature standard and advanced communication interfaces. • Four I2Cs • Three SPIs • Three USARTs, two UARTs and one Low-Power UART. • Two SAIs (Serial Audio Interfaces) • One SDMMC • Two CAN • One USB OTG full-speed • One SWPMI (Single Wire Protocol Master Interface) • Camera interface • DMA2D controller The STM32L496xx operates in the -40 to +85 °C (+105 °C junction), -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. 14/280 DS11585 Rev 10 STM32L496xx Description The STM32L496xx family offers six packages from 64-pin to 169-pin packages. Table 2. STM32L496xx family device features and peripheral counts Peripheral Flash memory STM32L496Ax STM32L496Zx STM32L496Qx STM32L496Vx STM32L496Rx 512KB 512KB 512KB 512KB 512KB 1MB 1MB SRAM 1MB 1MB 320 KB External memory controller for static memories Yes Yes Yes Quad SPI Timers 1MB Yes(1) No Yes Advanced control 2 (16-bit) General purpose 5 (16-bit) 2 (32-bit) Basic 2 (16-bit) Low power 2 (16-bit) SysTick timer 1 Watchdog timers (independent window) 2 SPI 3 2C 4 I USART UART LPUART 3 2 1 Comm. interfaces SAI 2 CAN 2 USB OTG FS Yes SDMMC Yes SWPMI Yes Digital filters for sigmadelta modulators Yes (4 filters) Number of channels 8 RTC Yes Tamper pins Camera interface 3 Yes(2) Yes Chrom-ART Accelerator™ Yes LCD COM x SEG Yes 8x40 or 4x44 DS11585 Rev 10 15/280 61 Description STM32L496xx Table 2. STM32L496xx family device features and peripheral counts (continued) Peripheral STM32L496Ax STM32L496Zx STM32L496Qx Random generator GPIOs(3) Wakeup pins Nb of I/Os down to 1.08 V STM32L496Vx STM32L496Rx Yes 136 5 14 115 5 14 110 5 14 83 5 0 52 4 0 Capacitive sensing Number of channels 24 24 24 21 21 12-bit ADCs Number of channels 3 24 3 24 3 19 3 16 3 16 12-bit DAC channels 2 Internal voltage reference buffer Yes Analog comparator 2 Operational amplifiers 2 Max. CPU frequency 80 MHz Operating voltage (VDD) 1.71 to 3.6 V Operating voltage (VDD12) 1.05 to 1.32 V Ambient operating temperature: -40 to 85 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 130 °C Operating temperature Packages UFBGA169 LQFP144 UFBGA132 LQFP100 WLCSP100 LQFP64 1. For the LQFP100 and WLCSP100 packages, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. Only up to 13 data bits. 3. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2. 16/280 DS11585 Rev 10 STM32L496xx Description Figure 1. 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During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. 24/280 DS11585 Rev 10 STM32L496xx Functional overview Figure 4. Power-up/down sequence 9  9''; 9'' 9%25   3RZHURQ ,QYDOLGVXSSO\DUHD 2SHUDWLQJPRGH 9'';9''P9 3RZHUGRZQ 9'';LQGHSHQGHQWIURP9'' WLPH 06Y9 1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD. 3.10.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. DS11585 Rev 10 25/280 61 Functional overview 3.10.3 STM32L496xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 64 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L496xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. When the MR is in use, the STM32L496xx with the external SMPS option allows to force an external VCORE supply on the VDD12 supply pins. When VDD12 is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter. 3.10.4 Low-power modes The ultra-low-power STM32L496xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. 26/280 DS11585 Rev 10 Mode Regulator(1) CPU Flash SRAM Clocks MR range 1 Run SMPS range 2 High MR range2 LPR Yes ON(4) ON Any Yes ON(4) ON Any except PLL SMPS range 2 High MR range2 No ON(4) ON(7) DS11585 Rev 10 LPR No ON(4) ON(7) No ON 93 µA/MHz N/A 129 µA/MHz to Range 1: 4 µs to Range 2: 64 µs 11.5 µA/MHz(5) 30 µA/MHz 6 cycles 13 µA/MHz(6) Any except PLL All except OTG_FS, RNG Any interrupt or event LSE LSI BOR, PVD, PVM RTC,LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 51 µA/MHz 6 cycles TBD 2.7 µs in SRAM 6.2 µs in Flash 127 µA 27/280 Functional overview MR Range 2(8) OFF 40 µA/MHz(5) 32 µA/MHz All except OTG_FS, RNG MR Range 1(8) Stop 0 N/A Any interrupt or event Any Wakeup time 39 µA/MHz(6) All SMPS range 2 Low LPSleep N/A All except OTG_FS, RNG Consumption(3) 108 µA/MHz All except OTG_FS, RNG MR range 1 Sleep Wakeup source All SMPS range 2 Low LPRun DMA & Peripherals(2) STM32L496xx Table 4. STM32L496xx modes overview Mode Stop 1 DS11585 Rev 10 Stop 2 Regulator LPR LPR CPU No No DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 11.2 µA w/o RTC 11.8 µA w RTC 6.6 µs in SRAM 7.8 µs in Flash LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 2.57 µA w/o RTC 2.86 µA w/RTC Flash SRAM Clocks Off Off ON ON Functional overview 28/280 Table 4. STM32L496xx modes overview (continued) (1) 6.8 µs in SRAM 8.2 µs in Flash STM32L496xx Mode Regulator CPU Flash SRAM Clocks Standby OFF Shutdown OFF Power ed Off Power ed Off Off Off Power ed Off Power ed Off Wakeup source Consumption(3) Wakeup time 0.48 µA w/o RTC 0.78 µA w/ RTC DS11585 Rev 10 LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(14) Reset pin 5 I/Os (WKUPx)(14) RTC SRAM 2 ON LPR DMA & Peripherals(2) 0.11 µA w/o RTC 0.42 µA w/ RTC 0.03 µA w/o RTC 0.23 µA w/ RTC STM32L496xx Table 4. STM32L496xx modes overview (continued) (1) 15.3 µs 306 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.10 V 6. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.05 V 7. The SRAM1 and SRAM2 clocks can be gated on or off independently. 8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected. 9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 11. OTG_FS wakeup by resume from suspend and attach detection protocol event. 12. SWPMI1 wakeup by resume from suspend. 13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 29/280 Functional overview 10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. Functional overview STM32L496xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. 30/280 DS11585 Rev 10 STM32L496xx • Functional overview Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. DS11585 Rev 10 31/280 61 Functional overview STM32L496xx Table 5. Functionalities depending on the working mode(1) - - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (256 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (64 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - FSMC O O O O - - - - - - - - - Quad SPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - DMA2D O O O O - - - - - - - - - High Speed Internal (HSI16) O O O O (5) - (5) - - - - - - Oscillator HSI48 O O - - - - - - - - - - - High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Peripheral CPU Flash memory (up to 1 MB) 32/280 Run Sleep Lowpower run Lowpower sleep - DS11585 Rev 10 Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT STM32L496xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - - Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 Camera interface O O O O - - - - - - - - - LCD O O O O O O O O - - - - - - - - O - - - - - - - - - - - - - - Peripheral USB OTG FS Run O (8) Sleep O (8) Lowpower run Lowpower sleep - Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT USARTx (x=1,2,3,4,5) O O O O O(6) O(6) Low-power UART (LPUART) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2,4) O O O O O(7) O(7) - - - - - I2C3 O O O O O(7) O(7) O(7) O(7) - - - - - SPIx (x=1,2,3) O O O O - - - - - - - - - CAN(x=1,2) O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1,2) O O O O - - - - - - - - - DFSDM1 O O O O - - - - - - - - - ADCx (x=1,2,3) O O O O - - - - - - - - - DAC1 O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - DS11585 Rev 10 - - 33/280 61 Functional overview STM32L496xx Table 5. Functionalities depending on the working mode(1) (continued) - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.10.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.10.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. 34/280 DS11585 Rev 10 STM32L496xx Functional overview An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.11 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L496xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DAC1 DFSDM1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - IRTIM Infrared interface output generation Y Y Y Y - - TIM1, 8 TIM2, 3 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - USB Timer triggered by USB SOF Y Y - - - - Interconnect source TIMx TIM16/TIM17 COMPx ADCx RTC Interconnect destination TIM2 Interconnect action DS11585 Rev 10 Y Y 35/280 61 Functional overview STM32L496xx Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6. STM32L496xx peripherals interconnect matrix (continued) Timer break Y Y Y Y - - TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect destination CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) TIM1,8 COMPx TIM15,16,17 PVD DFSDM1 (analog watchdog, short circuit detection) GPIO Interconnect action 1. LPTIM1 only. 36/280 DS11585 Rev 10 Y STM32L496xx 3.12 Functional overview Clocks and startup The clock controller (see Figure 5) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. • RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS11585 Rev 10 37/280 61 Functional overview STM32L496xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. 38/280 DS11585 Rev 10 STM32L496xx Functional overview Figure 5. Clock tree WR,:'* >^/ZϯϮŬ,nj /6&2 WR57&DQG/&' 26&B287 >^K^ ϯϮ͘ϳϲϴŬ,nj ͬϯϮ 26&B,1 0&2 WR3:5 /6( /6, 06, +6, +6( 6^/Ϯ sK )9&2 ͬW WR$3%SHULSKHUDOV džϭŽƌdžϮ 3//6$,&/. ͬY WR7,0[ [  WR6$, 3//$'&&/. 6$,B(;7&/. WR6$, 6$,B(;7&/. 069 DS11585 Rev 10 39/280 61 Functional overview 3.13 STM32L496xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.14 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation 40/280 DMA features DMA1 DMA2 Number of regular channels 7 7 DS11585 Rev 10 STM32L496xx 3.15 Functional overview Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.16 Interrupts and events 3.16.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 90 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.16.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 41 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 136 GPIOs can be connected to the 16 external interrupt lines. DS11585 Rev 10 41/280 61 Functional overview 3.17 STM32L496xx Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3. • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.17.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes) – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into 3 data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. 42/280 DS11585 Rev 10 STM32L496xx Functional overview To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.17.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.17.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.18 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. DS11585 Rev 10 43/280 61 Functional overview STM32L496xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.19 Voltage reference buffer (VREFBUF) The STM32L496xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 6. Voltage reference buffer 95()%8) 9''$ %DQGJDS  '$&$'& 95()  /RZIUHTXHQF\ FXWRIIFDSDFLWRU Q) 06Y9 44/280 DS11585 Rev 10 STM32L496xx 3.20 Functional overview Comparators (COMP) The STM32L496xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.21 Operational amplifier (OPAMP) The STM32L496xx embeds two operational amplifiers with external or internal follower routing and PGA capability. The operational amplifier features: 3.22 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. DS11585 Rev 10 45/280 61 Functional overview STM32L496xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. 3.23 Liquid crystal display controller (LCD) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.24 • Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • Phase inversion to reduce power consumption and EMI • Integrated voltage output buffers for higher LCD driving capability • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode Digital filter for Sigma-Delta Modulators (DFSDM) The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in 46/280 DS11585 Rev 10 STM32L496xx Functional overview hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM or from internal ADCs). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • internal sources: ADCs data or device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by: • • – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from final output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel • break signal generation on analog watchdog event or on short circuit detector event • extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode DS11585 Rev 10 47/280 61 Functional overview STM32L496xx without having any impact on the timing of “injected” conversions – 3.25 “injected” conversions for precise timing and with high conversion priority Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.26 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 3.27 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image Timers and watchdogs The STM32L496xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1, TIM8 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2, TIM5 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 48/280 DS11585 Rev 10 STM32L496xx Functional overview Table 10. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.27.1 Advanced-control timer (TIM1, TIM8) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.27.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. DS11585 Rev 10 49/280 61 Functional overview 3.27.2 STM32L496xx General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L496xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, TIM4 and TIM5 They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.27.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.27.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. 50/280 DS11585 Rev 10 STM32L496xx Functional overview This low-power timer supports the following features: 3.27.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Infrared interface (IRTIM) The STM32L496xx includes one infrared interface (IRTIM). It can be used with an infrared LED to perform remote control functions. It uses TIM16 and TIM17 output channels to generate output signal waveforms on IR_OUT pin. 3.27.6 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.27.7 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.27.8 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DS11585 Rev 10 51/280 61 Functional overview 3.28 STM32L496xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 52/280 DS11585 Rev 10 STM32L496xx 3.29 Functional overview Inter-integrated circuit interface (I2C) The device embeds four I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 5: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X Wakeup from Stop0, Stop 1 mode on address match X X X X Wakeup from Stop 2 mode on address match - - X - 1. X: supported DS11585 Rev 10 53/280 61 Functional overview 3.30 STM32L496xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L496xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 12. STM32L496xx USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X - - - Smartcard mode X X X - - - Single-wire half-duplex communication X X X X X X IrDA SIR ENDEC block X X X X X - LIN mode X X X X X - Dual clock domain X X X X X X Wakeup from Stop 0 / Stop 1 modes X X X X X X Wakeup from Stop 2 mode - - - - - X Receiver timeout interrupt X X X X X - Modbus communication X X X X X - Auto baud rate detection Driver Enable X (4 modes) X X LPUART/USART data length X 7, 8 and 9 bits 1. X = supported. 54/280 X - DS11585 Rev 10 X X STM32L496xx 3.31 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. DS11585 Rev 10 55/280 61 Functional overview 3.32 STM32L496xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.33 Serial audio interfaces (SAI) The device embeds 2 SAI. Refer to Table 13: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • 56/280 – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. DS11585 Rev 10 STM32L496xx Functional overview Table 13. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.34 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 3.35 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to 1Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. DS11585 Rev 10 57/280 61 Functional overview STM32L496xx Dual CAN peripheral configuration is available. The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.36 – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – Scalable filter banks: 28 filter banks shared between CAN1 and CAN2 – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards Interface (SDMMC) The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The SDMMC features include the following: 3.37 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data write and read with DMA capability Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE). 58/280 DS11585 Rev 10 STM32L496xx Functional overview The synchronization for this oscillator can also be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. 3.38 Clock recovery system (CRS) The STM32L496xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.39 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller This memory controller is also named Flexible memory controller (FMC). The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbyte of data • 8-,16- bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2. DS11585 Rev 10 59/280 61 Functional overview STM32L496xx LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. For WLCSP100 package, address lines [A18:A16] are missing versus other 100 pin packages, thus FMC provides only 2MB of addressable space, split into 64K blocks. The main usage of the FMC in this case is to drive external LCD interface. 3.40 Dual-flash Quad SPI memory interface (QUADSPI) The Dual-flash Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad SPI flash memories are accessed simultaneously. The Dual-flash Quad SPI interface supports: 60/280 • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS11585 Rev 10 STM32L496xx Functional overview 3.41 Development support 3.41.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.41.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L496xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell™ operates with third party debugger software tools. DS11585 Rev 10 61/280 61 Pinouts and pin description 4 STM32L496xx Pinouts and pin description Figure 7. STM32L496Ax UFBGA169 pinout(1)              $ 3, 3+ 9'' 3( 3% 3% 966 9'' 3$ 3$ 3$ 3, 3+ % 3, 3, 966 3( 3% 9'',2 3* 3' 3, 3, 3, 3+ 3+ & 9'' 966 3, 3% 3% 3* 3' 3' 3+ 3, 3, 966 9'' ' 3( 3( 3( 3% 3% 3* 3' 3' 3& 3, 3+ 3+ 3$ ( 3& 9%$7 3( 3( 3+%227 3* 3' 3' 3& 3, 3+ 9''86% 3$ ) 3& 26&B,1 966 3) 3) 3) 3* 3' 3& 3$ 3$ 3& 9'',2 966 * 3& 26&B287 9'' 3) 3) 3) 3* 3* 3$ 3& 3& 3* 3& 9'' + 3+26&B,1 966 1567 3) 3& 3* 3( 3% 3* 3* 3' 966 9'' - 3+ 26&B287 3& 3& 3& 3& 3* 3( 3( 3* 3* 3* 3* 3' . 3& 966$95() 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 3' 3' / 95() 9''$ 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 9'' 966 0 23$03B9, 10 3$ 966 3$ 3) 3) 966 3( 3+ 3+ 966 3% 3% 1 3$ 3$ 9'' 23$03B9, 10 3% 3) 9'' 3( 3% 3+ 9'' 3% 3% 06Y9 1. The above figure shows the package top view. Figure 8. STM32L496Ax, external SMPS device, UFBGA169 pinout(1)              $ 3, 3+ 9'' 3( 3% 3% 966 9'' 3$ 3$ 3$ 3, 3+ % 3, 3, 966 3( 3% 9'',2 3* 3' 3, 3, 3, 3+ 3+ & 9'' 966 3, 3% 3% 9'' 3' 3' 3+ 3, 3, 966 9'' ' 3( 3( 3( 3% 3% 3* 3' 3' 3& 3, 3+ 3+ 3$ ( 3& 9%$7 3( 3( 3+%227 3* 3' 3' 3& 3, 3+ 9''86% 3$ ) 3& 26&B,1 966 3) 3) 3) 3* 3' 3& 3$ 3$ 3& 9'',2 966 * 3& 26&B287 9'' 3) 3) 3) 3* 3* 3$ 3& 3& 3* 3& 9'' + 3+26&B,1 966 1567 3) 3& 3* 3( 3% 3* 3* 3' 966 9'' - 3+ 26&B287 3& 3& 3& 3& 3* 3( 3( 3* 3* 3* 3* 3' . 3& 966$95() 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 3' 3' / 95() 9''$ 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 9'' 966 0 23$03B9, 10 3$ 966 3$ 3) 3) 966 3( 3+ 9'' 966 3% 3% 9'' 23$03B9, 10 3% 3) 9'' 3( 3% 3+ 9'' 3% 3% 1 3$ 3$ 06Y9 1. The above figure shows the package top view. 62/280 DS11585 Rev 10 STM32L496xx Pinouts and pin description 9'' 966 3( 3( 3% 3% 3+%227 3% 3% 3% 3% 3% 3* 9'',2 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$                                     Figure 9. STM32L496Zx LQFP144 pinout(1) 3( 3( 3( 3(      9''  966  9''86%  3$ 3(   3$ 9%$7   3$ 3&  3&26&B,1    3$ 3$ 3&26&B287   3$ 3)   3& 3)  3)    3& 3& 3)   3& 3)   9'',2 3)   966 966   3* 9''   3* 3)   3* 3)   3* 3)   3* 3)   3* 3)   3* 3+26&B,1   3' 3+26&B287   3' 1567   9'' 3&   966 3&   3' 3&   3' 3&   3' 966$   3' 95()   3' 95()   3' 9''$   3% 3$   3% 3$   3% 3$   3%                                     3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' /4)3 06Y9 1. The above figure shows the package top view. DS11585 Rev 10 63/280 121 Pinouts and pin description STM32L496xx 9'' 966 9'' 3( 3( 3% 3% 3+%227 3% 3% 3% 3% 3% 9'',2 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$                                     Figure 10. STM32L496Zx, external SMPS device, LQFP144 pinout(1) 3( 3( 3( 3(      9''  966  9''86%  3$ 3(   3$ 9%$7   3$ 3&  3&26&B,1    3$ 3$ 3&26&B287   3$ 3)   3& 3)  3)    3& 3& 3)   3& 3)   9'',2 3)   966 966   3* 9''   3* 3)   3* 3)   3* 3)   3* 3)   3* 3)   3* 3+26&B,1   3' 3+26&B287   3' 1567   9'' 3&   966 3&   3' 3&   3' 3&   3' 966$   3' 95()   3' 95()   3' 9''$   3% 3$   3% 3$   3% 3$   3%                                     3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 9'' 966 9'' /4)3 06Y9 1. The above figure shows the package top view. 64/280 DS11585 Rev 10 STM32L496xx Pinouts and pin description Figure 11. STM32L496Qx UFBGA132 ballout(1)             $ 3( 3( 3% 3+%227 3' 3' 3% 3% 3$ 3$ 3$ 3$ % 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$ & 3& 3( 3( 9'' 3% 3* 3* 3' 3' 3& 9''86% 3$ ' 3& 26&B,1 3( 966 3) 3) 3) 3* 3* 3* 3$ 3$ 3& ( 3& 26&B287 9%$7 966 3) 3* 3& 3& 3& ) 3+26&B,1 966 3) 3) 966 966 3* 3* 966 966 * 3+ 26&B287 9'' 3* 3* 9'' 9'',2 3* 3* 9'' 9'' + 3& 1567 9'' 3* 3* 3' 3' 3' - 966$95() 3& 3& 3$ 3$ 3* 3) 3) 3) 3' 3' 3' . 3* 3& 3$ 3$ 3& 3) 3) 3' 3' 3% 3% 3% / 95() 3$ 3$ 3$ 3& 3% 3( 3( 3( 3% 3% 3% 0 9''$ 3$ 23$03B 9,10 23$03B 9,10 3% 3% 3( 3( 3( 3( 3( 3( 06Y9 1. The above figure shows the package top view. Figure 12. STM32L496Qx, external SMPS device, UFBGA132 ballout             $ 3( 3( 3% 3+%227 3' 3' 3% 3% 3$ 3$ 3$ 3$ % 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$ & 3& 3( 3( 9'' 3% 9'' 3* 3' 3' 3& 9''86% 3$ ' 3& 26&B,1 3( 966 3) 3) 3) 3* 3* 3* 3$ 3$ 3& ( 3& 26&B287 9%$7 966 3) 3* 3& 3& 3& ) 3+26&B,1 966 3) 3) 966 966 3* 3* 966 966 * 3+ 26&B287 9'' 3* 3* 9'' 9'',2 3* 3* 9'' 9'' + 3& 1567 9'' 3* 3* 3' 3' 3' - 966$95() 3& 3& 3$ 3$ 3* 3) 3) 3) 3' 3' 3' . 3* 3& 3$ 3$ 3& 3) 3) 3' 3' 3% 3% 3% / 95() 3$ 3$ 3$ 3& 3% 3( 3( 3( 3% 9'' 3% 0 9''$ 3$ 23$03B9, 10 23$03B9, 10 3% 3% 3( 3( 3( 3( 3( 3( 069 1. The above figure shows the package top view. DS11585 Rev 10 65/280 121 Pinouts and pin description STM32L496xx 9'' 966 3( 3( 3% 3% 3+%227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$                          Figure 13. STM32L496Vx LQFP100 pinout(1) 3(   9'' 3(   966 3(   9''86% 3(   3$ 3(   3$ 9%$7   3$ 3&   3$ 3&26&B,1   3$ 3&26&B287   3$ 966   3& 9''   3& 3+26&B,1   3& 3+26&B287   3& 1567   3' 3&   3' 3&   3' 3&   3' 3&   3' 966$   3' 95()   3' 95()   3' 9''$   3% 3$   3% 3$   3% 3$   3%                          3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' /4)3 06Y9 1. The above figure shows the package top view. 66/280 DS11585 Rev 10 STM32L496xx Pinouts and pin description 9'' 966 9'' 3( 3% 3% 3+%227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$                          Figure 14. STM32L496Vx, external SMPS device, LQFP100 pinout(1) 3(   9'' 3(   966 3(   9''86% 3(   3$ 3(   3$ 9%$7   3$ 3&   3$ 3&26&B,1   3$ 3&26&B287   3$ 966   3& 9''   3& 3+26&B,1   3& 3+26&B287   3& 1567   3' 3&   3' 3&   3' 3&   3' 3&   3' 966$   3' 95()   3' 95()   3' 9''$   3% 3$   3% 3$   3% 3$   3%                          3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 9'' 966 9'' /4)3 DS11585 Rev 10 069 67/280 121 Pinouts and pin description STM32L496xx Figure 15. STM32L496Vx WLCSP100 pinout(1)           $ 9''86% 3$ 3' 9'' 3* 9'',2 3% 3% 966 9'' % 966 3$ 3' 3' 3* 3* 3% 3% 3( 3( & 3$ 3$ 3& 3& 3' 3% 3% 3( 3& 9%$7 ' 3$ 3$ 3$ 3& 3' 3* 3% 3( 966 3& 26&B,1 ( 3& 3& 3$ 3' 3' 3+%227 3( 1567 9'' 3& 26&B287 ) 9'' 3& 3& 3' 3% 3$ 3& 3& 3& 3+26&B,1 * 3' 3' 3' 3( 3( 3$ 95() 95() 3$ 3+ 26&B287 + 3% 3% 3' 3( 3( 3& 3$ 3$ 966$95() 3& - 3% 3% 3% 3( 3( 3% 3$ 9'' 3$ 9''$ . 9'' 966 3% 3( 3( 3( 3% 3& 3$ 966 069 1. The above figure shows the package top view. Figure 16. STM32L496Vx, external SMPS device, WLCSP100 pinout(1)           $ 9''86% 3$ 3' 9'' 3* 9'',2 3% 3% 9'' 9'' % 966 3$ 3' 3' 3' 3* 3% 3% 966 3( & 3$ 3$ 3& 3& 3' 3' 3% 3( 3& 9%$7 ' 3$ 3$ 3$ 3& 3' 3* 3+%227 3( 3& 26&B287 3& 26&B,1 ( 3& 3& 3$ 3& 3* 3% 3( 3( 9'' 966 ) 9'' 3' 3' 3& 3% 3& 3& 1567 3+ 26&B287 3+26&B,1 * 3' 3' 3' 3( 3( 3$ 3$ 3$ 3& 3& + 3% 3% 3% 3( 3( 3% 3$ 3$ 966$95() 95() - 3% 9'' 3% 3( 3( 3% 3$ 9'' 3$ 9''$ . 9'' 966 3% 3( 3( 3( 3% 3& 3$ 966 069 1. The above figure shows the package top view. 68/280 DS11585 Rev 10 STM32L496xx Pinouts and pin description 9'' 966 3% 3% 3+%227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$                 Figure 17. STM32L496Rx LQFP64 pinout(1) 9%$7   9''86% 3&   966 3&26&B,1   3$ 3&26&B287   3$ 3+26&B,1   3$ 3+26&B287   3$ 1567   3$ 3&   3$ 3&   3& 3&   3& 3&   3& 966$95()   3& 9''$95()   3% 3$   3% 3$   3% 3$   3%                 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9'' /4)3 069 1. The above figure shows the package top view. 9'' 966 9'' 3% 3% 3+%227 3% 3% 3% 3% 3% 3& 3& 3& 3$ 3$                 Figure 18. STM32L496Rx, external SMPS, LQFP64 pinout(1) 9%$7   9''86% 3&   966 3&26&B,1   3$ 3&26&B287   3$ 3+26&B,1   3$ 3+26&B287   3$ 1567   3$ 3&   3$ 3&   3& 3&   3& 3&   3& 966$95()   3& 9''$95()   3% 3$   3% 3$   3% 3$   3%         3% 3% 3% 3% 9'' 966 9''  3$ 3%  3$   3$   9'' 3$  3&  3$ 966 4)[ 069 1. The above figure shows the package top view. DS11585 Rev 10 69/280 121 Pinouts and pin description STM32L496xx Table 14. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os I/O structure _f (1) I/O, Fm+ capable _l (2) I/O, with LCD function supplied by VLCD _u (3) I/O, with USB function supplied by VDDUSB _a (4) I/O, with Analog switch function supplied by VDDA _s (5) Notes I/O supplied only by VDDIO2 Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 15 are: FT_f, FT_fa, FT_fl, FT_fla. 2. The related I/O structures in Table 15 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 15 are: FT_u, FT_lu. 4. The related I/O structures in Table 15 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. The related I/O structures in Table 15 are: FT_s, FT_fs. 70/280 DS11585 Rev 10 LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS - - - - - - - - C3 C3 - DS11585 Rev 10 - - - - - B9 B10 C8 C8 B10 E7 1 2 3 1 2 3 B2 A1 B1 B2 A1 B1 1 2 3 1 2 3 D3 D2 D1 D3 D2 D1 PI11 I/O PE2 PE3 PE4 I/O I/O I/O Notes WLCSP100_SMPS - (function after reset) I/O structure WLCSP100 - Pin name Pin type LQFP64_SMPS Pin functions LQFP64 Pin Number FT - EVENTOUT - - TRACECK, TIM3_ETR, TSC_G7_IO1, LCD_SEG38, FMC_A23, SAI1_MCLK_A, EVENTOUT - - TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B, EVENTOUT - TRACED1, TIM3_CH2, DFSDM1_DATIN3, TSC_G7_IO3, DCMI_D4, FMC_A20, SAI1_FS_A, EVENTOUT FT_l FT_l FT Alternate functions Additional functions - D8 E8 4 4 C2 C2 4 4 E4 E4 PE5 I/O FT - - - E7 D8 5 5 D2 D2 5 5 E3 E3 PE6 I/O FT - TRACED3, TIM3_CH4, DCMI_D7, FMC_A22, RTC_TAMP3/WKUP3 SAI1_SD_A, EVENTOUT 1 1 C10 C10 6 6 E2 E2 6 6 E2 E2 VBAT S - - - - 2 2 C9 C9 7 7 C1 C1 7 7 E1 E1 PC13 I/O FT EVENTOUT RTC_TAMP1/RTC_TS/R TC_OUT/WKUP2 (2) Pinouts and pin description 71/280 - TRACED2, TIM3_CH3, DFSDM1_CKIN3, TSC_G7_IO4, DCMI_D6, FMC_A21, SAI1_SCK_A, EVENTOUT (1) STM32L496xx Table 15. STM32L496xx pin definitions LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure 3 D10 D10 8 8 D1 D1 8 8 F1 F1 PC14OSC32_IN (PC14) I/O FT 4 4 E10 D9 9 9 E1 E1 9 9 G1 G1 PC15OSC32_OUT (PC15) I/O FT - - - - - - D6 D6 10 10 F5 F5 PF0 I/O FT_f - - - - - - D5 D5 11 11 F4 F4 PF1 I/O - - - - - - D4 D4 12 12 F3 F3 PF2 - - - - - - E4 E4 13 13 G3 G3 - - - - - - F3 F3 14 14 G4 - - - - - - F4 F4 15 15 - - D9 E10 10 10 F2 F2 16 - - E9 E9 11 11 G2 G2 - - - - - - - - (function after reset) Notes WLCSP100_SMPS 3 Pin name (1) Alternate functions Additional functions EVENTOUT OSC32_IN EVENTOUT OSC32_OUT - I2C2_SDA, FMC_A0, EVENTOUT - FT_f - I2C2_SCL, FMC_A1, EVENTOUT - I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6 G4 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7 G5 G5 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8 16 F2 F2 VSS S - - - - 17 17 G2 G2 VDD S - - - - 18 18 - - PF6 I/O FT_a - TIM5_ETR, TIM5_CH1, QUADSPI_BK1_IO3, ADC3_IN9 SAI1_SD_B, EVENTOUT (2) (1) (2) STM32L496xx WLCSP100 DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number Pinouts and pin description 72/280 Table 15. STM32L496xx pin definitions (continued) - - - - - - - - - - - - - - - - 19 20 19 20 - - - - PF7 PF8 I/O I/O FT_a FT_a Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - TIM5_CH2, QUADSPI_BK1_IO2, SAI1_MCLK_B, EVENTOUT ADC3_IN10 - TIM5_CH3, QUADSPI_BK1_IO0, SAI1_SCK_B, EVENTOUT ADC3_IN11 - - - - - - - 21 21 - - PF9 I/O FT_a - - - - - - - - - 22 22 H4 H4 PF10 I/O FT_a - QUADSPI_CLK, DCMI_D11, TIM15_CH2, EVENTOUT ADC3_IN13 5 5 F10 F10 12 12 F1 F1 23 23 H1 H1 PH0-OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN 6 6 G10 F9 13 13 G1 G1 24 24 J1 J1 PH1OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT 7 7 E8 F8 14 14 H2 H2 25 25 H3 H3 NRST I/O RST - - - - LPTIM1_IN1, I2C4_SCL, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT ADC123_IN1 8 F9 G10 15 15 H1 H1 26 26 J2 J2 PC0 I/O FT_fla 73/280 Pinouts and pin description - TIM5_CH4, QUADSPI_BK1_IO1, ADC3_IN12 SAI1_FS_B, TIM15_CH1, EVENTOUT 8 STM32L496xx Table 15. STM32L496xx pin definitions (continued) 9 DS11585 Rev 10 10 9 10 F8 H10 F7 G9 16 17 16 17 J2 J3 J2 J3 27 28 27 28 J3 J4 J3 J4 PC1 PC2 I/O I/O FT_fla FT_la Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions - TRACED0, LPTIM1_OUT, I2C4_SDA, SPI2_MOSI, I2C3_SDA, ADC123_IN2 DFSDM1_CKIN4, LPUART1_TX, QUADSPI_BK2_IO0, LCD_SEG19, SAI1_SD_A, EVENTOUT - LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, QUADSPI_BK2_IO1, LCD_SEG20, EVENTOUT Pinouts and pin description 74/280 Table 15. STM32L496xx pin definitions (continued) ADC123_IN3 11 F7 F6 18 18 K2 K2 29 29 K1 K1 PC3 I/O FT_la - 12 12 H9 H9 19 19 J1 J1 30 30 K2 K2 VSSA/VREF- S - - - - - - G8 - 20 20 - - 31 31 - - VREF- S - - - - - - G7 H10 21 21 L1 L1 32 32 L1 L1 VREF+ S - - - VREFBUF_OUT - - J10 J10 22 22 M1 M1 33 33 L2 L2 VDDA S - - - - STM32L496xx 11 LPTIM1_ETR, SPI2_MOSI, QUADSPI_BK2_IO2, ADC123_IN4 LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS - - - - - - - - - - VDDA/VREF+ - DS11585 Rev 10 Notes WLCSP100_SMPS 13 (function after reset) I/O structure WLCSP100 13 Pin name Pin type LQFP64_SMPS Pin functions LQFP64 Pin Number - - - - OPAMP1_VINP, ADC12_IN5, RTC_TAMP2/WKUP1 - Alternate functions 14 14 G9 G8 23 23 L2 L2 34 34 K3 K3 PA0 I/O FT_a - TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI1_EXTCLK, TIM2_ETR, EVENTOUT - - - - - - M3 M3 - - M1 M1 OPAMP1_ VINM I TT - - 15 17 16 17 H8 H7 J9 G7 H8 J9 24 25 26 24 25 26 M2 K3 L3 M2 K3 L3 35 36 37 35 36 37 N2 N1 M2 N2 N1 M2 PA1 PA2 PA3 I/O I/O I/O FT_la FT_la TT_la (3) Additional functions TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, OPAMP1_VINM, USART2_RTS_DE, UART4_RX, LCD_SEG0, ADC12_IN6 TIM15_CH1N, EVENTOUT 75/280 - TIM2_CH3, TIM5_CH3, USART2_TX, LPUART1_TX, ADC12_IN7, QUADSPI_BK1_NCS, WKUP4/LSCO LCD_SEG1, SAI2_EXTCLK, TIM15_CH1, EVENTOUT - TIM2_CH4, TIM5_CH4, USART2_RX, LPUART1_RX, OPAMP1_VOUT, QUADSPI_CLK, ADC12_IN8 LCD_SEG2, SAI1_MCLK_A, TIM15_CH2, EVENTOUT Pinouts and pin description 16 15 STM32L496xx Table 15. STM32L496xx pin definitions (continued) WLCSP100 WLCSP100_SMPS LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number 18 18 K10 K10 27 27 E3 E3 38 38 H2 H2 VSS S - - - - 19 19 J8 J8 28 28 H3 H3 39 39 G13 G13 VDD S - - - - ADC12_IN9, DAC1_OUT1 ADC12_IN10, DAC1_OUT2 Pin name (function after reset) Alternate functions 20 20 F6 H7 29 29 J4 J4 40 40 L3 L3 PA4 I/O TT_a - SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, SAI1_FS_B, LPTIM2_OUT, EVENTOUT 21 21 G6 J7 30 30 K4 K4 41 41 K4 K4 PA5 I/O TT_a - TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR, EVENTOUT Additional functions 22 K9 K9 31 31 L4 L4 42 42 M4 M4 PA6 I/O FT_la - - - - - - - M4 M4 - - N4 N4 OPAMP2_VIN M I TT - - - STM32L496xx 22 TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK, SPI1_MISO, USART3_CTS, OPAMP2_VINP, LPUART1_CTS, ADC12_IN11 QUADSPI_BK1_IO3, LCD_SEG3, TIM1_BKIN_COMP2, TIM8_BKIN_COMP2, TIM16_CH1, EVENTOUT Pinouts and pin description 76/280 Table 15. STM32L496xx pin definitions (continued) 23 23 J7 G6 32 32 J5 J5 43 43 L4 L4 PA7 I/O FT_fla Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number (3) Alternate functions Additional functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, OPAMP2_VINM, SPI1_MOSI, ADC12_IN12 QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1, EVENTOUT DS11585 Rev 10 24 H6 K8 33 33 K5 K5 44 44 H5 H5 PC4 I/O FT_la - 25 - K8 - 34 34 L5 L5 45 45 J5 J5 PC5 I/O FT_la - USART3_RX, LCD_SEG23, EVENTOUT - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI1_NSS, USART3_CK, OPAMP2_VOUT, QUADSPI_BK1_IO1, ADC12_IN15 LCD_SEG5, COMP1_OUT, SAI1_EXTCLK, EVENTOUT - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, COMP1_INM, LPUART1_RTS_DE, ADC12_IN16 QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT 27 25 26 J6 K7 H6 K7 35 36 35 36 M5 M6 M5 M6 46 47 46 47 K5 L5 K5 L5 PB0 PB1 I/O I/O TT_la FT_la COMP1_INM, ADC12_IN13 COMP1_INP, ADC12_IN14, WKUP5 77/280 Pinouts and pin description 24 USART3_TX, QUADSPI_BK2_IO3, LCD_SEG22, EVENTOUT 26 STM32L496xx Table 15. STM32L496xx pin definitions (continued) Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 28 27 F5 J6 37 37 L6 L6 48 48 N5 N5 PB2 I/O FT_la - RTC_OUT, LPTIM1_OUT, COMP1_INP I2C3_SMBA, DFSDM1_CKIN0, LCD_VLCD, EVENTOUT - - - - - - K6 K6 49 49 M5 M5 PF11 I/O FT - DCMI_D12, EVENTOUT - - - - - - - J7 J7 50 50 N6 N6 PF12 I/O FT - FMC_A6, EVENTOUT - - - - - - - - - 51 51 - - VSS S - - - - - - - - - - - - 52 52 A8 A8 VDD S - - - - - - - - - - K7 K7 53 53 M6 M6 PF13 I/O FT - I2C4_SMBA, DFSDM1_DATIN6, FMC_A7, EVENTOUT - - - - - - - - J8 J8 54 54 L6 L6 PF14 I/O FT_fa - - - - - - - J9 J9 55 55 K6 K6 PF15 I/O FT_fa - I2C4_SDA, TSC_G8_IO2, FMC_A9, EVENTOUT - - - - - - H9 H9 56 56 J6 J6 PG0 I/O FT - TSC_G8_IO3, FMC_A10, EVENTOUT - - - - - - G9 G9 57 57 H6 H6 PG1 I/O FT - TSC_G8_IO4, FMC_A11, EVENTOUT STM32L496xx - I2C4_SCL, DFSDM1_CKIN6, TSC_G8_IO1, FMC_A8, EVENTOUT Pinouts and pin description 78/280 Table 15. STM32L496xx pin definitions (continued) - - - - K6 K5 K6 K5 38 39 38 39 M7 L7 M7 L7 58 59 58 59 L7 K7 L7 K7 PE7 PE8 I/O I/O FT FT Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B, EVENTOUT - - TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B, EVENTOUT - - - J5 J5 40 40 M8 M8 60 60 J7 J7 PE9 I/O FT - - - - - - - F6 F6 61 61 M7 M7 VSS S - - - - - - - - - - G6 G6 62 62 N7 N7 VDD S - - - - - TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT - - TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, QUADSPI_BK1_NCS, FMC_D8, EVENTOUT - - - - H5 K4 H5 K4 41 42 41 42 L8 M9 L8 M9 63 64 63 64 H7 N8 H7 N8 PE10 PE11 I/O I/O FT FT 79/280 Pinouts and pin description - TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B, EVENTOUT - STM32L496xx Table 15. STM32L496xx pin definitions (continued) - DS11585 Rev 10 - - - - - - - 28 G4 J4 H4 K3 J4 G5 G4 H4 K3 43 44 45 46 47 43 44 45 46 47 L9 M10 M11 M12 L10 L9 M10 M11 M12 L10 65 66 67 68 69 65 66 67 68 69 M8 L8 K8 J8 N9 M8 L8 K8 J8 N9 PE12 PE13 PE14 PE15 PB10 I/O I/O I/O I/O I/O FT FT FT FT FT_fl Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 G5 Pin functions Alternate functions Additional functions - TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9, EVENTOUT - - TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11, EVENTOUT - TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12, EVENTOUT - - TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT - STM32L496xx 29 LQFP64_SMPS LQFP64 Pin Number Pinouts and pin description 80/280 Table 15. STM32L496xx pin definitions (continued) Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) Additional functions DS11585 Rev 10 29 J3 J3 48 - L11 - 70 - H8 H8 PB11 I/O FT_fl - - 30 - K1 - 48 - L11 - 70 - M10 VDD12 S - - - - - - - - - - - - - - K9 K9 PH4 I/O FT_f - I2C2_SCL, EVENTOUT - - - - - - - - - - - L9 L9 PH5 I/O FT_f - I2C2_SDA, DCMI_PIXCLK, EVENTOUT - - - - - - - - - - - N10 N10 PH8 I/O FT_f - I2C3_SDA, DCMI_HSYNC, EVENTOUT - - - - - - - - - - - M9 M9 PH10 I/O FT - TIM5_CH1, DCMI_D1, EVENTOUT - - - - - - - - - - - M10 - PH11 I/O FT - TIM5_CH2, DCMI_D2, EVENTOUT - - - - - - - - - - - M3 M3 VSS S - - - - - - - - - - - - - - N3 N3 VDD S - - - - - 81/280 Pinouts and pin description 30 TIM2_CH4, I2C4_SDA, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT WLCSP100 WLCSP100_SMPS LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number - - - - - - - - - - M11 M11 VSS S - - - - 31 31 K2 K2 49 49 F12 F12 71 71 L13 L13 VSS S - - - - 32 32 K1 J2 50 50 G12 G12 72 72 L12 L12 VDD S - - - - - - - - - - - - - - N11 N11 VDD S - - - - - TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN2_RX, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT 33 33 J1 J1 51 51 L12 L12 73 73 N12 N12 Pin name (function after reset) PB12 I/O FT_l Alternate functions Additional functions Pinouts and pin description 82/280 Table 15. STM32L496xx pin definitions (continued) STM32L496xx 34 34 J2 H2 52 52 K12 K12 74 74 N13 N13 PB13 I/O FT_fl Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number - - TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT 36 H2 H1 H1 H3 53 54 53 54 K11 K10 K11 K10 75 76 75 76 M13 M12 M13 M12 PB14 PB15 I/O I/O FT_fl - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2, EVENTOUT FT_l 83/280 Pinouts and pin description 36 35 Additional functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN2_TX, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT DS11585 Rev 10 35 Alternate functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) - DS11585 Rev 10 - - - - - - - - - H3 G2 G1 - - G3 G2 G1 - - 55 56 57 58 59 55 56 57 58 59 K9 K8 J12 J11 J10 K9 K8 J12 J11 J10 77 78 79 80 81 77 78 79 80 81 L11 L10 J13 K12 K11 L11 L10 J13 K12 K11 PD8 PD9 PD10 PD11 PD12 I/O I/O I/O I/O I/O FT_l FT_l FT_l FT_l FT_fl Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions - - USART3_RX, DCMI_PIXCLK, LCD_SEG29, FMC_D14, SAI2_MCLK_A, EVENTOUT - - USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A, EVENTOUT - - I2C4_SMBA, USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT - - TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT - STM32L496xx - USART3_TX, DCMI_HSYNC, LCD_SEG28, FMC_D13, EVENTOUT Pinouts and pin description 84/280 Table 15. STM32L496xx pin definitions (continued) Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - - - 60 60 H12 H12 82 82 K13 K13 PD13 I/O FT_fl - - - - - - - - - 83 83 H12 H12 VSS S - - - - - - F1 F1 - - - - 84 84 H13 H13 VDD S - - - - - - G3 F3 61 61 H11 H11 85 85 K10 K10 PD14 I/O FT_l - TIM4_CH3, LCD_SEG34, FMC_D0, EVENTOUT - - - F4 F2 62 62 H10 H10 86 86 H11 H11 PD15 I/O FT_l - TIM4_CH4, LCD_SEG35, FMC_D1, EVENTOUT - - - - - - - G10 G10 87 87 J12 J12 PG2 I/O FT_s - SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT - - - - - - - F9 F9 88 88 J11 J11 PG3 I/O FT_s - SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT - - - - - - F10 F10 89 89 J10 J10 PG4 I/O FT_s - SPI1_MOSI, FMC_A14, SAI2_MCLK_B, EVENTOUT - - SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT - - - - - - E9 E9 90 90 J9 J9 PG5 I/O FT_s - 85/280 Pinouts and pin description - TIM4_CH2, I2C4_SDA, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT, EVENTOUT - STM32L496xx Table 15. STM32L496xx pin definitions (continued) WLCSP100 WLCSP100_SMPS LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number - - - - - - G4 G4 91 91 G11 G11 PG6 I/O FT_s - I2C3_SMBA, LPUART1_RTS_DE, EVENTOUT - - - - - - H4 H4 92 92 H10 H10 PG7 I/O FT_fs - I2C3_SCL, LPUART1_TX, FMC_INT, SAI1_MCLK_A, EVENTOUT - - - - - - J6 J6 93 93 H9 H9 PG8 I/O FT_fs - I2C3_SDA, LPUART1_RX, EVENTOUT - - - - - - - - - 94 94 F13 F13 VSS S - - - - - - - - - - - - 95 95 F12 F12 VDDIO2 S - - - - - TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, DCMI_D0, LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT - TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, DCMI_D1, LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT 37 38 F2 F3 F4 E4 63 64 63 64 E12 E11 E12 E11 96 97 96 97 F11 G12 F11 G12 (function after reset) PC6 PC7 I/O I/O FT_l FT_l Alternate functions Additional functions - STM32L496xx 38 37 Pin name Pinouts and pin description 86/280 Table 15. STM32L496xx pin definitions (continued) 39 DS11585 Rev 10 40 41 39 40 41 42 E2 E3 D3 E1 E2 E3 D3 65 66 67 68 65 66 67 68 E10 D12 D11 D10 E10 D12 D11 D10 98 99 100 101 98 99 100 101 G10 G9 G8 F10 G10 G9 G8 F10 PC8 PC9 PA8 PA9 I/O I/O I/O I/O FT_l FT_fl FT_l FT_lu Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 E1 Pin functions Alternate functions Additional functions - TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2, LCD_SEG26, SDMMC1_D0, EVENTOUT - TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3, I2C3_SDA, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1, EVENTOUT - MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT - - TIM1_CH2, SPI2_SCK, DCMI_D0, USART1_TX, LCD_COM1, SAI1_FS_A, TIM15_BKIN, EVENTOUT OTG_FS_VBUS 87/280 Pinouts and pin description 42 LQFP64_SMPS LQFP64 Pin Number STM32L496xx Table 15. STM32L496xx pin definitions (continued) 43 DS11585 Rev 10 44 43 44 D2 D1 D2 D1 69 70 69 70 C12 B12 C12 B12 102 103 102 103 F9 E13 F9 E13 PA10 PA11 I/O I/O FT_lu FT_u Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions - TIM1_CH3, DCMI_D1, USART1_RX, OTG_FS_ID, LCD_COM2, SAI1_SD_A, TIM17_BKIN, EVENTOUT - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CAN1_RX, OTG_FS_DM, TIM1_BKIN2_COMP1, EVENTOUT TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, OTG_FS_DP, EVENTOUT Pinouts and pin description 88/280 Table 15. STM32L496xx pin definitions (continued) - 45 45 C1 C1 71 71 A12 A12 104 104 D13 D13 PA12 I/O FT_u - 46 46 C2 C2 72 72 A11 A11 105 105 A11 A11 PA13 (JTMS/ SWDIO) I/O FT (4) 47 47 B1 B1 - - - - - - - - VSS S - - - - 48 48 A1 A1 73 73 C11 C11 106 106 E12 E12 VDDUSB S - - - - - - - - 74 74 F11 F11 107 107 C12 C12 VSS S - - - - - JTMS/SWDIO, IR_OUT, OTG_FS_NOE, SWPMI1_TX, SAI1_SD_B, EVENTOUT STM32L496xx WLCSP100_SMPS LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes - - - - 75 75 G11 G11 108 108 C13 C13 VDD S - - - - - - - - - - - - - - E11 E11 PH6 I/O FT - I2C2_SMBA, DCMI_D8, EVENTOUT - - - - - - - - - - - D12 D12 PH7 I/O FT_f - I2C3_SCL, DCMI_D9, EVENTOUT - - - - - - - - - - - D11 D11 PH9 I/O FT - I2C3_SMBA, DCMI_D0, EVENTOUT - - - - - - - - - - - B13 B13 PH12 I/O FT - TIM5_CH3, DCMI_D3, EVENTOUT - - - - - - - - - - - A13 A13 PH14 I/O FT - TIM8_CH2N, DCMI_D4, EVENTOUT - - - - - - - - - - - B12 B12 PH15 I/O FT - TIM8_CH3N, DCMI_D11, EVENTOUT - - - - - - - - - - A12 A12 PI0 I/O FT - TIM5_CH4, SPI2_NSS, DCMI_D13, EVENTOUT - - - - - - - - - - - C11 C11 PI8 I/O FT - DCMI_D12, EVENTOUT - - - - - - - - - - - B11 B11 PI1 I/O FT - SPI2_SCK, DCMI_D8, EVENTOUT - - - - - - - - - - - B10 B10 PI2 I/O FT - TIM8_CH4, SPI2_MISO, DCMI_D9, EVENTOUT - - - - - - - - - - - C10 C10 PI3 I/O FT - TIM8_ETR, SPI2_MOSI, DCMI_D10, EVENTOUT - - - - - - - - - - - D10 D10 PI4 I/O FT - TIM8_BKIN, DCMI_D5, EVENTOUT - Pin name (function after reset) Alternate functions Additional functions Pinouts and pin description 89/280 WLCSP100 DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number STM32L496xx Table 15. STM32L496xx pin definitions (continued) WLCSP100 WLCSP100_SMPS LQFP100 LQFP100_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 10 LQFP64_SMPS Pin functions LQFP64 Pin Number - - - - - - - - - - E10 E10 PI5 I/O FT - TIM8_CH1, DCMI_VSYNC, EVENTOUT - - - - - - - - - - - C9 C9 PH13 I/O FT - TIM8_CH1N, CAN1_TX, EVENTOUT - - - - - - - - - - - B9 B9 PI6 I/O FT - TIM8_CH2, DCMI_D6, EVENTOUT - 49 50 49 50 B2 A2 B2 A2 76 77 76 77 A10 A9 A10 A9 109 110 109 110 A10 A9 A10 A9 Pin name (function after reset) PA14 (JTCK/ SWCLK) PA15 (JTDI) I/O I/O FT FT_l Alternate functions Additional functions (4) JTCK/SWCLK, LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SWPMI1_RX, SAI1_FS_B, EVENTOUT (4) JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, SAI2_FS_B, EVENTOUT Pinouts and pin description 90/280 Table 15. STM32L496xx pin definitions (continued) STM32L496xx 51 DS11585 Rev 10 52 - 51 52 53 - C3 C4 B3 C3 D4 C4 B3 78 79 80 81 78 79 80 81 B11 C10 B10 C9 B11 C10 B10 C9 111 112 113 114 111 112 113 114 D9 E9 F8 B8 D9 E9 F8 B8 PC10 PC11 PC12 PD0 I/O I/O I/O I/O FT_l FT_l FT_l FT Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 D4 Pin functions Alternate functions Additional functions 91/280 - TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, DCMI_D8, LCD_COM4/LCD_SEG2 8/LCD_SEG40, SDMMC1_D2, SAI2_SCK_B, EVENTOUT - QUADSPI_BK2_NCS, SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, DCMI_D4, LCD_COM5/LCD_SEG2 9/LCD_SEG41, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT - TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9, LCD_COM6/LCD_SEG3 0/LCD_SEG42, SDMMC1_CK, SAI2_SD_B, EVENTOUT - SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2, EVENTOUT - Pinouts and pin description 53 LQFP64_SMPS LQFP64 Pin Number STM32L496xx Table 15. STM32L496xx pin definitions (continued) - DS11585 Rev 10 54 - - - - A3 E4 - A3 D5 - 82 83 84 82 83 84 B9 C8 B8 B9 C8 B8 115 116 117 115 116 117 C8 D8 E8 C8 D8 E8 PD1 PD2 PD3 I/O I/O I/O FT FT_l FT Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions - SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3, EVENTOUT - TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11, LCD_COM7/LCD_SEG3 1/LCD_SEG43, SDMMC1_CMD, EVENTOUT - SPI2_SCK, DCMI_D5, SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, QUADSPI_BK2_NCS, FMC_CLK, EVENTOUT - - Pinouts and pin description 92/280 Table 15. STM32L496xx pin definitions (continued) - - B4 C5 85 85 B7 B7 118 118 C7 C7 PD4 I/O FT - - - E5 B4 86 86 A6 A6 119 119 D7 D7 PD5 I/O FT - USART2_TX, QUADSPI_BK2_IO1, FMC_NWE, EVENTOUT - - - - - - - - - 120 120 - - VSS S - - - - - - A4 A4 - - - - 121 121 - - VDD S - - - - STM32L496xx - SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, QUADSPI_BK2_IO0, FMC_NOE, EVENTOUT Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - - D5 B5 87 87 B6 B6 122 122 E7 E7 PD6 I/O FT - DCMI_D10, QUADSPI_BK2_IO1, DFSDM1_DATIN1, USART2_RX, QUADSPI_BK2_IO2, FMC_NWAIT, SAI1_SD_A, EVENTOUT - - C5 C6 88 88 A5 A5 123 123 F7 F7 PD7 I/O FT - DFSDM1_CKIN1, USART2_CK, QUADSPI_BK2_IO3, FMC_NE1, EVENTOUT - SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - LPTIM1_IN1, SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - LPTIM1_IN2, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT - - - - B5 A5 D6 D6 A5 E5 - - - - - - D9 D8 G3 D9 D8 G3 124 125 126 124 125 126 B7 D6 E6 B7 D6 E6 PG9 PG10 PG11 I/O I/O I/O FT_s FT_s FT_s - 93/280 Pinouts and pin description - - STM32L496xx Table 15. STM32L496xx pin definitions (continued) Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - - B6 B6 - - D7 D7 127 127 F6 F6 PG12 I/O FT_s - LPTIM1_ETR, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT - - - - - - C7 C7 128 128 G7 G7 PG13 I/O FT_fs - I2C1_SDA, USART1_CK, FMC_A24, EVENTOUT - - - - - - C6 - 129 129 G6 G6 PG14 I/O FT_fs - I2C1_SCL, FMC_A25, EVENTOUT - - - - - - - F7 F7 130 130 A7 A7 VSS S - - - - - - A6 A6 - - G7 G7 131 131 B6 B6 VDDIO2 S - - - - - - - - - - K1 K1 132 - C6 - PG15 I/O FT_s - LPTIM1_OUT, I2C1_SMBA, DCMI_D13, EVENTOUT 55 54 C6 F5 89 89 A8 A8 133 132 A6 A6 PB3 (JTDO/TRACE SWO) I/O FT_la (4) JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, OTG_FS_CRS_SYNC, LCD_SEG7, SAI1_SCK_B, EVENTOUT Pinouts and pin description 94/280 Table 15. STM32L496xx pin definitions (continued) - COMP2_INM STM32L496xx 56 55 C7 E6 90 90 A7 A7 134 133 A5 A5 PB4 (NJTRST) I/O FT_fla Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number (4) DS11585 Rev 10 57 57 B7 A7 C7 A7 91 92 91 92 C5 B5 C5 B5 135 136 134 135 B5 C5 B5 C5 PB5 PB6 I/O I/O FT_la FT_fa NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, DCMI_D12, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT Additional functions COMP2_INP 95/280 - LPTIM1_IN1, TIM3_CH2, CAN2_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, DCMI_D10, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT - LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, I2C4_SCL, DFSDM1_DATIN5, USART1_TX, CAN2_TX, COMP2_INP TSC_G2_IO3, DCMI_D5, TIM8_BKIN2_COMP2, SAI1_FS_B, TIM16_CH1N, EVENTOUT Pinouts and pin description 58 56 Alternate functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 59 58 D7 B7 93 93 B4 B4 137 136 D5 D5 PB7 I/O FT_fla - LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, I2C4_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, COMP2_INM, PVD_IN TSC_G2_IO4, DCMI_VSYNC, LCD_SEG21, FMC_NL, TIM8_BKIN_COMP1, TIM17_CH1N, EVENTOUT 60 59 E6 D7 94 94 A4 A4 138 137 E5 E5 PH3-BOOT0 I/O FT - EVENTOUT - TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, DCMI_D6, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT 61 60 B8 B8 95 95 A3 A3 139 138 C4 C4 PB8 I/O FT_fl Pinouts and pin description 96/280 Table 15. STM32L496xx pin definitions (continued) - 61 A8 A8 96 96 B3 B3 140 139 D4 D4 PB9 I/O FT_fl - - 62 - - - - - C6 - - - C6 VDD12 S - - - - STM32L496xx 62 IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, DCMI_D7, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT Notes (function after reset) I/O structure Pin name Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 Pin functions UFBGA132_SMPS UFBGA132 LQFP100_SMPS LQFP100 WLCSP100_SMPS WLCSP100 LQFP64_SMPS LQFP64 Pin Number Alternate functions Additional functions DS11585 Rev 10 - - - 97 97 C3 C3 141 140 A4 A4 PE0 I/O FT_l - - - - - 98 - A2 A2 142 141 B4 B4 PE1 I/O FT_l - DCMI_D3, LCD_SEG37, FMC_NBL1, TIM17_CH1, EVENTOUT - - - A9 - 98 - - - 142 - - VDD12 S - - - - 63 63 A9 B9 99 99 D3 D3 143 143 B3 B3 VSS S - - - - 64 64 A10 A10 100 100 C4 C4 144 144 A3 A3 VDD S - - - - - - - - - - - - - - C2 C2 VSS S - - - - - - - - - - - - - - C1 C1 VDD S - - - - - - - - - - - - - - A2 A2 PH2 I/O FT - QUADSPI_BK2_IO0, EVENTOUT - - - - - - - - - - - - TIM8_CH3, DCMI_D7, EVENTOUT - - - - - - - - - - - - - - - - - - - - - B2 PI7 I/O FT B1 B1 PI9 I/O FT A1 A1 PI10 I/O FT - CAN1_RX, EVENTOUT EVENTOUT - 97/280 Pinouts and pin description - TIM4_ETR, DCMI_D2, LCD_SEG36, FMC_NBL0, TIM16_CH1, EVENTOUT B2 STM32L496xx Table 15. STM32L496xx pin definitions (continued) 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual. 3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins available on M3 and M4 balls. 4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. Pinouts and pin description 98/280 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These GPIOs must not be used as current sources (e.g. to drive an LED). DS11585 Rev 10 STM32L496xx AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS PA1 - TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK - USART2_RTS_ DE PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN DCMI_PIXCLK SPI1_MISO - USART3_CTS PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - - USART1_CK PA9 - TIM1_CH2 - SPI2_SCK - DCMI_D0 - USART1_TX PA10 - TIM1_CH3 - - - DCMI_D1 - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_ DE PA13 JTMS/SWDIO IR_OUT - - - - - - PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA I2C4_SMBA - - PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_ DE Port DS11585 Rev 10 Port A 99/280 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - SPI1_NSS - USART3_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_ DATIN0 USART3_RTS_ DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 - PB3 JTDO/ TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_ DE PB4 NJTRST - TIM3_CH1 - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS PB5 - LPTIM1_IN1 TIM3_CH2 CAN2_RX I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL DFSDM1_ DATIN5 USART1_TX PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA DFSDM1_CKIN5 USART1_RX PB8 - - TIM4_CH3 - I2C1_SCL - DFSDM1_ DATIN6 - PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_CKIN6 - PB10 - TIM2_CH3 - I2C4_SCL I2C2_SCL SPI2_SCK DFSDM1_ DATIN7 USART3_TX PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - DFSDM1_CKIN7 USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN_ COMP2 I2C2_SMBA SPI2_NSS DFSDM1_ DATIN1 USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM1_ DATIN2 USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 - Port DS11585 Rev 10 Port B STM32L496xx AF2 Pinouts and pin description 100/280 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PC0 - LPTIM1_IN1 I2C4_SCL - I2C3_SCL - DFSDM1_ DATIN4 - PC1 TRACED0 LPTIM1_OUT I2C4_SDA SPI2_MOSI I2C3_SDA - DFSDM1_CKIN4 - PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_ CKOUT - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 - PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM1_ DATIN3 - PC8 - - TIM3_CH3 TIM8_CH3 - - - - PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 DCMI_D3 - I2C3_SDA - PC10 TRACED1 - - - - - SPI3_SCK USART3_TX PC11 - - - - - QUADSPI_BK 2_NCS SPI3_MISO USART3_RX PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port DS11585 Rev 10 Port C 101/280 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PD0 - - - - - SPI2_NSS DFSDM1_ DATIN7 - PD1 - - - - - SPI2_SCK DFSDM1_CKIN7 - PD2 TRACED2 - TIM3_ETR - - - - USART3_RTS_ DE PD3 - - - SPI2_SCK DCMI_D5 SPI2_MISO DFSDM1_ DATIN0 USART2_CTS PD4 - - - - - SPI2_MOSI DFSDM1_CKIN0 USART2_RTS_ DE PD5 - - - - - - - USART2_TX PD6 - - - - DCMI_D10 QUADSPI_ BK2_IO1 DFSDM1_ DATIN1 USART2_RX PD7 - - - - - - DFSDM1_CKIN1 USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - I2C4_SMBA - - USART3_CTS PD12 - - TIM4_CH1 - I2C4_SCL - - USART3_RTS_ DE PD13 - - TIM4_CH2 - I2C4_SDA - - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - Port DS11585 Rev 10 Port D STM32L496xx AF2 Pinouts and pin description 102/280 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PE0 - - TIM4_ETR - - - - - PE1 - - - - - - - - PE2 TRACECK - TIM3_ETR - - - - - PE3 TRACED0 - TIM3_CH1 - - - - - PE4 TRACED1 - TIM3_CH2 - - - DFSDM1_ DATIN3 - PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 - PE6 TRACED3 - TIM3_CH4 - - - - - PE7 - TIM1_ETR - - - - DFSDM1_ DATIN2 - PE8 - TIM1_CH1N - - - - DFSDM1_CKIN2 - PE9 - TIM1_CH1 - - - - DFSDM1_ CKOUT - PE10 - TIM1_CH2N - - - - DFSDM1_ DATIN4 - PE11 - TIM1_CH2 - - - - DFSDM1_CKIN4 - PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM1_ DATIN5 - PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_ COMP2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN_ COMP1 - SPI1_MOSI - - Port DS11585 Rev 10 Port E 103/280 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - PF2 - - - - I2C2_SMBA - - - PF3 - - - - - - - - PF4 - - - - - - - - PF5 - - - - - - - - PF6 - TIM5_ETR TIM5_CH1 - - - - - PF7 - - TIM5_CH2 - - - - - PF8 - - TIM5_CH3 - - - - - PF9 - - TIM5_CH4 - - - - - PF10 - - - QUADSPI_CLK - - - - PF11 - - - - - - - - PF12 - - - - - - - - PF13 - - - - I2C4_SMBA - DFSDM1_ DATIN6 - PF14 - - - - I2C4_SCL - DFSDM1_CKIN6 - PF15 - - - - I2C4_SDA - - - Port DS11585 Rev 10 Port F Pinouts and pin description 104/280 Table 16. Alternate function AF0 to AF7(1) (continued) STM32L496xx AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PG0 - - - - - - - - PG1 - - - - - - - - PG2 - - - - - SPI1_SCK - - PG3 - - - - - SPI1_MISO - - PG4 - - - - - SPI1_MOSI - - PG5 - - - - - SPI1_NSS - - PG6 - - - - I2C3_SMBA - - - PG7 - - - - I2C3_SCL - - - PG8 - - - - I2C3_SDA - - - PG9 - - - - - - SPI3_SCK USART1_TX PG10 - LPTIM1_IN1 - - - - SPI3_MISO USART1_RX PG11 - LPTIM1_IN2 - - - - SPI3_MOSI USART1_CTS PG12 - LPTIM1_ETR - - - - SPI3_NSS USART1_RTS_ DE PG13 - - - - I2C1_SDA - - USART1_CK PG14 - - - - I2C1_SCL - - - PG15 - LPTIM1_OUT - - I2C1_SMBA - - - Port DS11585 Rev 10 Port G 105/280 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PH0 - - - - - - - - PH1 - - - - - - - - PH2 - - - QUADSPI_ BK2_IO0 - - - - PH3 - - - - - - - - PH4 - - - - I2C2_SCL - - - PH5 - - - - I2C2_SDA - - - PH6 - - - - I2C2_SMBA - - - PH7 - - - - I2C3_SCL - - - PH8 - - - - I2C3_SDA - - - PH9 - - - - I2C3_SMBA - - - PH10 - - TIM5_CH1 - - - - - PH11 - - TIM5_CH2 - - - - - PH12 - - TIM5_CH3 - - - - - PH13 - - - TIM8_CH1N - - - - PH14 - - - TIM8_CH2N - - - - PH15 - - - TIM8_CH3N - - - - Port DS11585 Rev 10 Port H Pinouts and pin description 106/280 Table 16. Alternate function AF0 to AF7(1) (continued) STM32L496xx AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PI0 - - TIM5_CH4 - - SPI2_NSS - - PI1 - - - - - SPI2_SCK - - PI2 - - - TIM8_CH4 - SPI2_MISO - - PI3 - - - TIM8_ETR - SPI2_MOSI - - PI4 - - - TIM8_BKIN - - - - PI5 - - - TIM8_CH1 - - - - PI6 - - - TIM8_CH2 - - - - PI7 - - - TIM8_CH3 - - - - PI8 - - - - - - - - PI9 - - - - - - - - PI10 - - - - - - - - PI11 - - - - - - - - Port DS11585 Rev 10 Port I STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) 1. Please refer to Table 17 for AF8 to AF15. Pinouts and pin description 107/280 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT PA2 LPUART1_TX - QUADSPI_BK1_NCS LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT PA3 LPUART1_RX - QUADSPI_CLK LCD_SEG2 - SAI1_MCLK_A TIM15_CH2 EVENTOUT PA4 - - DCMI_HSYNC - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 LPUART1_CT S - QUADSPI_BK1_IO3 LCD_SEG3 TIM1_BKIN_C OMP2 TIM8_BKIN_C OMP2 TIM16_CH1 EVENTOUT PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT PA8 - - OTG_FS_SOF LCD_COM0 SWPMI1_IO SAI1_SCK_A LPTIM2_OUT EVENTOUT PA9 - - - LCD_COM1 - SAI1_FS_A TIM15_BKIN EVENTOUT PA10 - - OTG_FS_ID LCD_COM2 - SAI1_SD_A TIM17_BKIN EVENTOUT PA11 - CAN1_RX OTG_FS_DM - TIM1_BKIN2_ COMP1 - - EVENTOUT PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT PA13 - - OTG_FS_NOE - SWPMI1_TX SAI1_SD_B - EVENTOUT PA14 - - OTG_FS_SOF - SWPMI1_RX SAI1_FS_B - EVENTOUT - LCD_SEG17 SWPMI1_SUS PEND SAI2_FS_B - EVENTOUT Port DS11585 Rev 10 Port A PA15 UART4_RTS_ TSC_G3_IO1 DE STM32L496xx AF8 Pinouts and pin description 108/280 Table 17. Alternate function AF8 to AF15(1) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT SAI1_EXTCLK - EVENTOUT PB1 LPUART1_RT S_DE - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT PB2 - - - LCD_VLCD - - - EVENTOUT PB3 - - OTG_FS_CRS_SYNC LCD_SEG7 - SAI1_SCK_B - EVENTOUT Port DS11585 Rev 10 Port B UART5_RTS_ TSC_G2_IO1 DE DCMI_D12 LCD_SEG8 - SAI1_MCLK_B TIM17_BKIN EVENTOUT PB5 UART5_CTS TSC_G2_IO2 DCMI_D10 LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 CAN2_TX TSC_G2_IO3 DCMI_D5 - TIM8_BKIN2_ COMP2 SAI1_FS_B TIM16_CH1N EVENTOUT PB7 UART4_CTS TSC_G2_IO4 DCMI_VSYNC LCD_SEG21 FMC_NL TIM8_BKIN_C OMP1 TIM17_CH1N EVENTOUT PB8 - CAN1_RX DCMI_D6 LCD_SEG16 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT PB9 - CAN1_TX DCMI_D7 LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - QUADSPI_BK1_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT PB12 LPUART1_RT TSC_G1_IO1 S_DE CAN2_RX LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_CT TSC_G1_IO2 S CAN2_TX LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT 109/280 PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX SAI2_MCLK_A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_SUS PEND SAI2_SD_A TIM15_CH2 EVENTOUT Pinouts and pin description PB4 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PC0 LPUART1_RX - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - QUADSPI_BK2_IO0 LCD_SEG19 - SAI1_SD_A - EVENTOUT PC2 - - QUADSPI_BK2_IO1 LCD_SEG20 - - - EVENTOUT PC3 - - QUADSPI_BK2_IO2 LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - QUADSPI_BK2_IO3 LCD_SEG22 - - - EVENTOUT PC5 - - - LCD_SEG23 - - - EVENTOUT PC6 - TSC_G4_IO1 DCMI_D0 LCD_SEG24 SDMMC1_D6 SAI2_MCLK_A - EVENTOUT PC7 - TSC_G4_IO2 DCMI_D1 LCD_SEG25 SDMMC1_D7 SAI2_MCLK_B - EVENTOUT PC8 - TSC_G4_IO3 DCMI_D2 LCD_SEG26 SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 OTG_FS_NOE LCD_SEG27 SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2_C OMP1 EVENTOUT PC10 UART4_TX TSC_G3_IO2 DCMI_D8 LCD_COM4/L CD_SEG28/L CD_SEG40 SDMMC1_D2 SAI2_SCK_B - EVENTOUT PC11 UART4_RX TSC_G3_IO3 DCMI_D4 LCD_COM5/L CD_SEG29/L CD_SEG41 SDMMC1_D3 SAI2_MCLK_B - EVENTOUT PC12 UART5_TX TSC_G3_IO4 DCMI_D9 LCD_COM6/L CD_SEG30/L CD_SEG42 SDMMC1_CK SAI2_SD_B - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port DS11585 Rev 10 Port C STM32L496xx AF8 Pinouts and pin description 110/280 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT PD2 UART5_RX TSC_SYNC DCMI_D11 - - EVENTOUT PD3 - - QUADSPI_BK2_NCS - FMC_CLK - - EVENTOUT PD4 - - QUADSPI_BK2_IO0 - FMC_NOE - - EVENTOUT PD5 - - QUADSPI_BK2_IO1 - FMC_NWE - - EVENTOUT PD6 - - QUADSPI_BK2_IO2 - FMC_NWAIT SAI1_SD_A - EVENTOUT PD7 - - QUADSPI_BK2_IO3 - FMC_NE1 - - EVENTOUT PD8 - - DCMI_HSYNC LCD_SEG28 FMC_D13 - - EVENTOUT PD9 - - DCMI_PIXCLK LCD_SEG29 FMC_D14 SAI2_MCLK_A - EVENTOUT PD10 - TSC_G6_IO1 - LCD_SEG30 FMC_D15 SAI2_SCK_A - EVENTOUT PD11 - TSC_G6_IO2 - LCD_SEG31 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - LCD_SEG32 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - LCD_SEG33 FMC_A18 - LPTIM2_OUT EVENTOUT PD14 - - - LCD_SEG34 FMC_D0 - - EVENTOUT PD15 - - - LCD_SEG35 FMC_D1 - - EVENTOUT Port DS11585 Rev 10 Port D LCD_COM7/L SDMMC1_CM CD_SEG31/L D CD_SEG43 111/280 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PE0 - - DCMI_D2 LCD_SEG36 FMC_NBL0 - TIM16_CH1 EVENTOUT PE1 - - DCMI_D3 LCD_SEG37 FMC_NBL1 - TIM17_CH1 EVENTOUT PE2 - TSC_G7_IO1 - LCD_SEG38 FMC_A23 SAI1_MCLK_A - EVENTOUT PE3 - TSC_G7_IO2 - LCD_SEG39 FMC_A19 SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 DCMI_D4 - FMC_A20 SAI1_FS_A - EVENTOUT PE5 - TSC_G7_IO4 DCMI_D6 - FMC_A21 SAI1_SCK_A - EVENTOUT PE6 - - DCMI_D7 - FMC_A22 SAI1_SD_A - EVENTOUT PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 SAI1_MCLK_B - EVENTOUT PE11 - TSC_G5_IO2 QUADSPI_BK1_NCS - FMC_D8 - - EVENTOUT PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT Port DS11585 Rev 10 Port E Pinouts and pin description 112/280 Table 17. Alternate function AF8 to AF15(1) (continued) STM32L496xx AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PF0 - - - - FMC_A0 - - EVENTOUT PF1 - - - - FMC_A1 - - EVENTOUT PF2 - - - - FMC_A2 - - EVENTOUT PF3 - - - - FMC_A3 - - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - - EVENTOUT PF6 - - QUADSPI_BK1_IO3 - - SAI1_SD_B - EVENTOUT PF7 - - QUADSPI_BK1_IO2 - - SAI1_MCLK_B - EVENTOUT PF8 - - QUADSPI_BK1_IO0 - - SAI1_SCK_B - EVENTOUT PF9 - - QUADSPI_BK1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT PF10 - - DCMI_D11 - - - TIM15_CH2 EVENTOUT PF11 - - DCMI_D12 - - - - EVENTOUT PF12 - - - - FMC_A6 - - EVENTOUT PF13 - - - - FMC_A7 - - EVENTOUT PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT Port DS11585 Rev 10 Port F 113/280 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT PG5 LPUART1_CT S - - - FMC_A15 SAI2_SD_B - EVENTOUT PG6 LPUART1_RT S_DE - - - - - - EVENTOUT PG7 LPUART1_TX - - - FMC_INT SAI1_MCLK_A - EVENTOUT PG8 LPUART1_RX - - - - - - EVENTOUT PG9 - - - - FMC_NCE/FM C_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT PG13 - - - - FMC_A24 - - EVENTOUT PG14 - - - - FMC_A25 - - EVENTOUT PG15 - - DCMI_D13 - - - - EVENTOUT Port DS11585 Rev 10 Port G STM32L496xx AF8 Pinouts and pin description 114/280 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH2 - - - - - - - EVENTOUT PH3 - - - - - - - EVENTOUT PH4 - - - - - - - EVENTOUT PH5 - - DCMI_PIXCLK - - - - EVENTOUT PH6 - - DCMI_D8 - - - - EVENTOUT PH7 - - DCMI_D9 - - - - EVENTOUT PH8 - - DCMI_HSYNC - - - - EVENTOUT PH9 - - DCMI_D0 - - - - EVENTOUT PH10 - - DCMI_D1 - - - - EVENTOUT PH11 - - DCMI_D2 - - - - EVENTOUT PH12 - - DCMI_D3 - - - - EVENTOUT PH13 - CAN1_TX - - - - - EVENTOUT PH14 - - DCMI_D4 - - - - EVENTOUT PH15 - - DCMI_D11 - - - - EVENTOUT Port DS11585 Rev 10 Port H 115/280 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/FM C/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PI0 - - DCMI_D13 - - - - EVENTOUT PI1 - - DCMI_D8 - - - - EVENTOUT PI2 - - DCMI_D9 - - - - EVENTOUT PI3 - - DCMI_D10 - - - - EVENTOUT PI4 - - DCMI_D5 - - - - EVENTOUT PI5 - - DCMI_VSYNC - - - - EVENTOUT PI6 - - DCMI_D6 - - - - EVENTOUT PI7 - - DCMI_D7 - - - - EVENTOUT PI8 - - DCMI_D12 - - - - EVENTOUT PI9 - CAN1_RX - - - - - EVENTOUT PI10 - - - - - - - EVENTOUT PI11 - - - - - - - EVENTOUT Port Port I Pinouts and pin description 116/280 Table 17. Alternate function AF8 to AF15(1) (continued) DS11585 Rev 10 1. Please refer to Table 16 for AF0 to AF7. STM32L496xx STM32L496xx 5 Memory mapping Memory mapping Figure 19. STM32L496xx memory map [)))))))) [%))))))) 5HVHUYHG &RUWH[Œ0 ZLWK)38 ,QWHUQDO 3HULSKHUDOV  [$ 48$'63,UHJLVWHUV [$ )0&UHJLVWHUV [$ [( [))))))) 5HVHUYHG  [& $+% [ [& 5HVHUYHG [ $+% )0&DQG 48$'63, UHJLVWHUV  [ [ [$  48$'63,)ODVK EDQN [ )0&EDQN [ 5HVHUYHG $3% 5HVHUYHG [ [ $3% [))))))) [ 5HVHUYHG [)))) 2SWLRQ%\WHV  [)))) 5HVHUYHG )0&EDQN [)))) 6\VWHPPHPRU\ [ [))) [)))  [))) 5HVHUYHG 2SWLRQV%\WHV 5HVHUYHG [))) 3HULSKHUDOV 273DUHD [ [))) 6\VWHPPHPRU\  [ [ [))) 65$0 5HVHUYHG [ 65$0 65$0 [ 5HVHUYHG  [ &2'( )ODVKPHPRU\ [ [ [ [ 5HVHUYHG 5HVHUYHG )ODVKV\VWHPPHPRU\ RU65$0GHSHQGLQJRQ %227FRQILJXUDWLRQ 06Y9 DS11585 Rev 10 117/280 121 Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) Bus AHB4 AHB3 - AHB2 - AHB1 118/280 Boundary address Size (bytes) Peripheral 0xA000 1000 - 0xA000 13FF 1 KB QUADSPI 0xA000 0400 - 0xA000 0FFF 3 KB Reserved 0xA000 0000 - 0xA000 03FF 1 KB FMC 0x5006 0C00 - 0x5FFF FFFF ~260 MB 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5005 0400 - 0x5005 FFFF 62 KB Reserved 0x5005 0000 - 0x5005 03FF 1 KB DCMI 0x5004 0400 - 0x5004 FFFF 62 KB Reserved 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB OTG_FS 0x4800 2400 - 0x4FFF FFFF ~127 MB Reserved 0x4800 2000 - 0x4800 23FF 1 KB GPIOI 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1800 - 0x4800 1BFF 1 KB GPIOG 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 BC00 - 0x47FF FFFF ~127 MB 0x4002 B000 - 0x4002 BBFF 3 KB DMA2D 0x4002 4400 - 0x4002 AFFF 26 KB Reserved 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 0x4002 0000 - 0x4002 03FF 1 KB DMA1 DS11585 Rev 10 Reserved Reserved STM32L496xx Memory mapping Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 Boundary address Size (bytes) Peripheral 0x4001 6400 - 0x4001 FFFF 39 KB Reserved 0x4001 6000 - 0x4001 63FF 1 KB DFSDM1 0x4001 5C00 - 0x4001 5FFF 1 KB Reserved 0x4001 5800 - 0x4001 5BFF 1 KB SAI2 0x4001 5400 - 0x4001 57FF 1 KB SAI1 0x4001 4C00 - 0x4001 53FF 2 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB TIM8 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF 0x4001 0000 - 0x4001 002F DS11585 Rev 10 COMP 1 KB VREFBUF SYSCFG 119/280 121 Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 120/280 Boundary address Size (bytes) Peripheral 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 - 0x4000 87FF 1 KB I2C4 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP 0x4000 7400 - 0x4000 77FF 1 KB DAC1 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6800 - 0x4000 6FFF 1 KB Reserved 0x4000 6800 - 0x4000 6BFF 1 KB CAN2 0x4000 6400 - 0x4000 67FF 1 KB CAN1 0x4000 6000 - 0x4000 63FF 1 KB CRS 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 5000 - 0x4000 53FF 1 KB UART5 0x4000 4C00 - 0x4000 4FFF 1 KB UART4 DS11585 Rev 10 STM32L496xx Memory mapping Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 4800 - 0x4000 4BFF 1 KB USART3 0x4000 4400 - 0x4000 47FF 1 KB USART2 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB LCD 0x4000 1800 - 0x4000 23FF 3 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0C00- 0x4000 0FFF 1 KB TIM5 0x4000 0800 - 0x4000 0BFF 1 KB TIM4 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. DS11585 Rev 10 121/280 121 Electrical characteristics STM32L496xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 20. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 21. Figure 20. Pin loading conditions Figure 21. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 069 122/280 DS11585 Rev 10 069 STM32L496xx 6.1.6 Electrical characteristics Power supply scheme Figure 22. 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