STM32L4S5AII6

STM32L4S5xx STM32L4S7xx STM32L4S9xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AES+HASH Datasheet- production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – Batch acquisition mode (BAM) – 305 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 33 nA Shutdown mode (5 wakeup pins) – 125 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 2.8 μA Stop 2 with RTC – 110 μA/MHz Run mode – 5 µs wakeup from Stop mode – Brownout reset (BOR) in all modes except Shutdown – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 409.20 CoreMark® (3.41 CoreMark/MHz @120 MHz) • Energy benchmark – 233 ULPMark™CP score – 56.5 ULPMark™PP score • Clock sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – Internal 48 MHz with clock recovery March 2020 This is information on a product in full production. LQFP144 (20 × 20) UFBGA169 (7 x 7) LQFP100 (14 x 14) UFBGA144 (10 x 10) WLCSP144 (pitch 0.4 mm) UFBGA132 (7 × 7) – 3 PLLs for system clock, USB, audio, ADC • RTC with hardware calendar, alarms and calibration • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors • Advanced graphics features – Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation – Chrom-GRC (GFXMMU) allowing up to 20% of graphic resources optimization – MIPI® DSI Host controller with two DSI lanes running at up to 500 Mbit/s each – LCD-TFT controller • 16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer • Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V • Memories – 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection – 640 Kbytes of SRAM including 64 Kbytes with hardware parity check – External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories – 2 x Octo-SPI memory interface • 4x digital filters for sigma delta modulator • Rich analog peripherals (independent supply) – 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps DS12024 Rev 4 1/273 www.st.com STM32L4S5xx, STM32L4S7xx and STM32L4S9xx – 2x 12-bit DAC, low-power sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators • 20x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) – 4x I2C FM+(1 Mbit/s), SMBus/PMBus – 6x USARTs (ISO 7816, LIN, IrDA, modem) – 3x SPIs (5x SPIs with the dual Octo-SPI) – CAN (2.0B Active) and SDMMC • 14-channel DMA controller • True random number generator • CRC calculation unit, 96-bit unique ID • 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) • Encryption hardware accelerator: AES (128/256-bit key), HASH (SHA-256) • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM) Table 1. Device summary Reference Part numbers STM32L4S5xx STM32L4S5VI, STM32L4S5QI, STM32L4S5ZI, STM32L4S5AI STM32L4S7xx STM32L4S7VI, STM32L4S7ZI, STM32L4S7AI STM32L4S9xx STM32L4S9VI, STM32L4S9ZI, STM32L4S9AI 2/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 17 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21 3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.15 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.16 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.17 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.19 3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 42 3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 42 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DS12024 Rev 4 3/273 6 Contents 4/273 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.19.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.19.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.19.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.21 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.24 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.25 LCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.26 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.27 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 49 3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.29 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.30 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 51 3.31 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.32 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.32.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.32.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.32.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.32.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 53 3.32.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.32.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.32.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.33 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 55 3.34 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.35 Universal synchronous/asynchronous receiver transmitter (USART) . . . 57 3.36 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 58 3.37 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.38 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.39 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.40 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 60 3.41 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 61 3.42 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Contents 3.43 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 61 3.44 OctoSPI interface (OctoSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.45 OctoSPI IO manager (OctoSPIIOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.46 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.46.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.46.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 120 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 120 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.10 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.11 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.12 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DS12024 Rev 4 5/273 6 Contents 7 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.3.19 Extended interrupt and event controller input (EXTI) characteristics . . 181 6.3.20 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.3.21 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 182 6.3.22 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 195 6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.25 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.26 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.27 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.28 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.3.29 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.3.30 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 211 6.3.31 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.3.32 OctoSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 244 6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 245 6.3.35 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 246 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.1 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 7.4 WLCSP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 7.5 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 7.6 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 268 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 6/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18 STM32L4S5xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STM32L4Sxxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 120 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . 125 Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . 126 Current consumption in Run and Low-power run modes, code with data processing running from Flash in single bank, ART disable. . . . . . . . . . . 127 Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ART disable . . . . . . . . . . . . 128 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 130 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 134 Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 135 Current consumption in Stop 2 mode, SRAM3 disabled . . . . . . . . . . . . . . . . . . . . . . . . . 136 Current consumption in Stop 2 mode, SRAM3 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DS12024 Rev 4 7/273 9 List of tables Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. 8/273 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 167 DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 WWDG min/max timeout value at 120 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. List of tables SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 222 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 222 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 223 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 224 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 225 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 227 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 236 OctoSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 OctoSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 OctoSPI characteristics in DTR mode (with DQS)/Octal and HyperBus™ . . . . . . . . . . . . 239 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Dynamics characteristics: SD / eMMC characteristics at VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Dynamics characteristics: eMMC characteristics at VDD = 1.71 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 UFBGA169 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 250 UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 253 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 WLCSP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 WLCSP144 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 263 LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 STM32L4Sxxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 DS12024 Rev 4 9/273 9 List of figures STM32L4S5xx, STM32L4S7xx and STM32L4S9xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/273 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx block diagram . . . . . . . . . . . . . . . . . . 16 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32L4S5xx and STM32L4S7xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32L4S9xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32L4S5xx and STM32L4S7xx UFBGA169 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L4S9xx UFBGA169 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 STM32L4S5xx and STM32L4S7xx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L4S9xx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 STM32L4S9xx UFBGA144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STM32L4S9xx WLCSP144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STM32L4S5xx WLCSP144 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32L4S5xx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32L4S5xx and STM32L4S7xx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32L4S9xx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 168 MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 219 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 221 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 223 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 224 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 226 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. List of figures Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 232 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 235 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 236 OctoSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 OctoSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 OctoSPI HyperBus™ clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 OctoSPI HyperBus™ read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 OctoSPI HyperBus™ read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 OctoSPI HyperBus™ write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 UFBGA169 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 UFBGA169 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 WLCSP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 WLCSP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 WLCSP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 DS12024 Rev 4 11/273 11 Introduction 1 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L4Sxxx microcontrollers. This document should be read in conjunction with the STM32L4Sxxx reference manual (RM0432). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 2 Description Description The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices are an ultra-low-power microcontrollers family (STM32L4+ Series) based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 120 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm® single-precision data-processing instructions and all the data types. The CortexM4 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. These devices embed high-speed memories (2 Mbytes of Flash memory and 640 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), two OctoSPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L4Sxxx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and a firewall. These devices offer a fast 12-bit ADC (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive sensing channels are available. They also feature standard and advanced communication interfaces such as: • Four I2Cs • Three SPIs • Three USARTs, two UARTs and one low-power UART • Two SAIs • One SDMMC • One CAN • One USB OTG full-speed • Camera interface • DMA2D controller The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices embed an AES and a HASH hardware accelerator. The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. Some independent power supplies are supported like an analog independent supply input for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows to backup the RTC and backup the registers. The STM32L4Sxxx family offers six packages from 100-pin to 169-pin. DS12024 Rev 4 13/273 64 Description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 2. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx features and peripheral counts Peripheral S5VI S7VI S9VI S5QI S5ZI Flash memory SRAM System 640 (192 + 64 + 384) Kbytes Backup 128 bytes OctoSPI Comm. interfaces Yes(1) Yes 1 2 Advanced control 2 (16-bit) General purpose 5 (16-bit) 2 (32-bit) Basic 2 (16-bit) Low-power 2 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 SPI 3 2C I 4 USART/UART UART LPUART 3 2 1 SAI 2 CAN 1 USB OTG FS Yes SDMMC Yes Digital filters for sigmadelta modulators S5AI S7AI S9AI Yes (4 filters) Number of channels 8 RTC Yes Tamper pins 3 Camera interface Yes Chrom-ART Accelerator Yes Chrom-GRC™ No LCD - TFT No (2) MIPI DSI Host 14/273 S9ZI 2 Mbytes External memory controller for static memories (FSMC) Timers S7ZI Yes Yes No No No Yes No Yes No Yes No Yes Yes DS12024 Rev 4 No Yes No Yes STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Description Table 2. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx features and peripheral counts (continued) Peripheral S5VI S7VI S9VI S5QI S5ZI Random number generator Yes AES + HASH Yes GPIOs Wakeup pins Nb of I/Os down to 1.08 V 83 5 0 77 4 0 Capacitive sensing Number of channels 21 18 12-bit ADCs Number of channels 110 5 14 S7ZI 112(3) 5 11 115 5 14 S5AI S7AI 140 5 14 S9AI 131 4 13 24 1 16 14 16 14 2 2 12-bit DAC Number of channels Internal voltage reference buffer Yes Analog comparator 2 Operational amplifiers 2 Max. CPU frequency 120 MHz Operating voltage Operating temperature S9ZI 1.71 to 3.6 V Ambient operating temperature: -40 to 85 °C / -40 to 125 °C LQFP LQFP 144, 144 LQFP UFBGA UFBGA 132 WLCS 144 144 P144 WLCSP 144 Packages LQFP100 Bootloader USART USART USART 1 2 3 SPI1 SPI2 I2C1 I2C2 UFBGA169 USB I2C3 CAN1 through DFU 1. For the LQFP100 package, only FMC bank1 and NAND bank are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 chip select. 2. The DSI Host interface is only available on the STM32L4S9xx sales types. 3. 110 GPIOs available for WLCSP144 and LQFP144 packages. DS12024 Rev 4 15/273 64 Description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Figure 1. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx block diagram CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF, FRAM Flexible static memory controller (FSMC): SRAM, PSRAM, NOR Flash, NAND Flash JTAG & SW MPU ETM NVIC TRACECLK TRACED[3:0] OctoSPI1 memory interface IO[7:0], CLK, NCS. DQS OctoSPI2 memory interface D-BUS RNG AES I-BUS D[7:0] CMD, CK as AF SDIO / MMC FIFO @ VDDUSB SRAM2 64 KB USB OTG SRAM3 384 KB VDD AHB2 120 MHz VSS Supply supervision reset MSI Touch sensing controller VDD = 1.71 to 3.6 V @ VDD @ VDD DMA1 RC HSI VDDIO, VDDUSB Int BOR VDDA, VSSA RC LSI GPIO PORT A PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E VDD, VSS, NRST PVD, PVM PLL 1&2&3 AHB1 120 MHz PA[15:0] DP DM ID, VBUS, SOF Power management Voltage regulator 3.3 to 1.2 V DMA2 8 Groups of 4 channels max as AF HSYNC, VSYNC, PIXCLK, D[13:0] Camera Interface SRAM1 192 KB FIFO FIFO Chrom-GRC (GFXMMU) AHB bus-matrix CHROM-ART DMA2D FIFO LCD - TFT HASH Flash up to 2 MB FIFO LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK FIFO S-BUS PHY Arm Cortex-M4 120 MHz FPU ART ACCEL/ CACHE NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO @VDD OSC_IN OSC_OUT XTAL OSC 4- 16MHz IWDG PF[15:0] Standby interface Reset & clock M AN AGT control @VBAT GPIO PORT F XTAL 32 kHz OSC32_IN OSC32_OUT PG[15:0] GPIO PORT G GPIO PORT I TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels, ETR as AF CRC @ VDD @ VDDA ITF ADC1 @ VDDA USART2 smcard irDA RX, TX, CK, CTS, RTS as AF USART3 smcard irDA RX, TX, CK, CTS, RTS as AF VREF+ VREF Buffer AHB/APB2 114 AF TIM1 / PWM 3 compl. Channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM8 / PWM 16b UART4 RX, TX, CTS, RTS as AF UART5 RX, TX, CTS, RTS as AF SPI2 MOSI, MISO, SCK, NSS as AF SPI3 MOSI, MISO, SCK, NSS as AF I2C1/SMBUS 16b SCL, SDA, SMBA as AF WWDG 16b USART1 MOSI, MISO, SCK, NSS as AF SPI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI2 SDCKIN[7:0], SDDATIN[7:0], SDCKOUT,SDTRIG as AF SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF I2C4/SMBUS SCL, SDA, SMBA as AF TIM6 16b TIM7 16b bxCAN1 FIFO 16b TIM17 P B 1(max) 3 0 M Hz APB1 120AMHz TIM16 1 channel, 1 compl. channel, BKIN as AF smcard irDA I2C2/SMBUS 16b APB2 120MHz TIM15 1 channel, 1 compl. channel, BKIN as AF A 60PM B Hz 2 2 channels, 1 compl. channel, BKIN as AF TX, RX as AF @VDDA OpAmp1 OUT, INN, INP OpAmp2 OUT, INN, INP LPUART1 RX, TX, CTS, RTS as AF LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF DFSDM DSI PHI DSIHOST_D0 P/N DSIHOST_D1 P/N DSIHOST_CK P/N VDD12DSI, VDDSI, VSSDSI VCAPDSI DSIHOST_TE AHB/APB1 EXT IT. WKUP 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF RX, TX, CK,CTS, RTS as AF RTC_TS RTC_TAMPx RTC_OUT VBAT = 1.55 to 3.6 V U STemperature AR T 2 M B ps sensor 8 analog inputs common to the ADC PCLKx PI[11:0] FCLK GPIO PORT H HCLKx PH[15:0] RTC AWU Backup register DSI Host @ VDDA @ VDDA INP, INN, OUT COMP1 INP, INN, OUT COMP2 DAC1 ITF DAC2 Firewall DAC1_OUT DAC2_OUT 1. AF: alternate function on I/O pins. 16/273 DS12024 Rev 4 MSv38487V4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU Functional overview The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of the MCU implementation, with a reduced pin count and with low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional codeefficiency, delivering the expected high-performance from an Arm® core in a memory size usually associated with 8-bit and 16-bit devices. The processor supports a set of DSP instructions which allows an efficient signal processing and a complex algorithm execution. Its single precision FPU speeds up the software development by using metalanguage development tools to avoid saturation. With its embedded Arm® core, the STM32L4Sxxx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L4Sxxx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator) The ART Accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm®Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 150 DMIPS performance at 120 MHz, the accelerator implements an instruction prefetch queue and a branch cache, which increases the program’s execution speed from the Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from the Flash memory at a CPU frequency of up to 120 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to eight protected areas, which can be divided in up into eight subareas each. The protection area sizes range between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS12024 Rev 4 17/273 64 Functional overview 3.4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Embedded Flash memory The STM32L4Sxxx devices feature 2 Mbytes of embedded Flash memory which is available for storing programs and data. The Flash interface features: – Single or dual bank operating modes – Read-while-write (RWW) in dual bank mode This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 4 or 8 Kbytes (depending on the read access width). Flexible protections can be configured thanks to the option bytes: • Readout protection (RDP) to protect the whole memory. Three levels of protection are available: – Level 0: no readout protection – Level 1: memory readout protection; the Flash memory cannot be read from or written to if either the debug features are connected or the boot in RAM or bootloader are selected – Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 (1) 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. • 18/273 Write protection (WRP): the protected area is protected against erasing and programming: – In single bank mode, four areas can be selected with 8-Kbyte granularity. – In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx • Functional overview Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited: – In single bank mode, two areas can be selected with 128-bit granularity. – In dual bank mode, one area per bank can be selected with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • Single error detection and correction • Double error detection • The address of the ECC fail can be read in the ECC register. Embedded SRAM The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices feature 640 Kbytes of embedded SRAM. This SRAM is split into three blocks: • 192 Kbytes mapped at address 0x2000 0000 (SRAM1). • 64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2003 0000 offering a contiguous address space with the SRAM1. This block is accessed through the ICode/DCode buses for maximum performance. These 64 Kbytes SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. • 384 Kbytes mapped at address 0x2004 0000 - (SRAM3). The memory can be accessed in read/write at CPU clock speed with 0 wait states. DS12024 Rev 4 19/273 64 Functional overview 3.6 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D, SDMMC1, LCD-TFT and GFXMMU) and the slaves (Flash memory, RAM, FMC, OctoSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix DMA1 DMA2 DMA2D LCD-TFT SDMMC1 GFXMMU S-bus D-bus I-bus Cortex®-M4 with FPU DCode ACCEL ICode FLASH 2 MB SRAM1 SRAM2 SRAM3 GFXMMU AHB1 peripherals AHB2 peripherals FSMC OCTOSPI1 OCTOSPI2 BusMatrix-S MSv38490V1 3.7 Firewall These devices embed a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. 20/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview The main features of the firewall are the following: • • Three segments can be protected and defined thanks to the firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) The start address and the length of each segment are configurable: – Code segment: up to 2048 Kbytes with granularity of 256 bytes – Non-volatile data segment: up to 2048 Kbytes with granularity of 256 bytes – Volatile data segment: up to 192 Kbytes of SRAM1 with a granularity of 64 bytes • Specific mechanism implemented to open the firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. 3.8 Boot modes At startup, a BOOT0 pin and an nBOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. A Flash empty-check mechanism is implemented to force the boot from system Flash if the first Flash memory location is not programmed and if the boot selection is configured to boot from main Flash. The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in device mode through the DFU (device firmware upgrade). 3.9 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location. DS12024 Rev 4 21/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.10 Power supply management 3.10.1 Power supply schemes The STM32L4x devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent supplies can be provided for specific peripherals: • VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage and should preferably be connected to VDD when these peripherals are not used. • VDDUSB = 3.0 V to 3.6 V VDDUSB is the external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage and should preferably be connected to VDD when the USB is not used. • VDDIO2 = 1.08 V to 3.6 V • VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level is independent from the VDD voltage and should preferably be connected to VDD when PG[15:2] are not used. • VDDDSI is an independent DSI power supply dedicated for is used to supply the DSI regulator and MIPI D-PHY. This supply must be connected to the global VDD. • VCAPDSI pin is the output of DSI regulator (1.2 V) which must be connected externally to VDD12DSI. • VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin. • VBAT = 1.55 V to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. • VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. When VDDA < 2 V VREF+ must be equal to VDDA. When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA. VREF+ can be grounded when ADC and DAC are not active. The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register: – VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V. – VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V. VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively. When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to datasheet for 22/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview packages pinout description). VREF- must always be equal to VSSA. An embedded linear voltage-regulator is used to supply the internal digital power VCORE. VCORE is the power supply for digital peripherals, SRAM1, SRAM2 and SRAM3. The Flash is supplied by VCORE and VDD. Figure 3. STM32L4S5xx and STM32L4S7xx power supply overview VDDA domain VDDA VSSA 3 x A/D converters 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer VDDUSB VSS VDDIO2 VSS USB transceivers VDDIO2 domain VDDIO2 I/O ring PG[15:2] VDD domain VDDIO1 I/O ring VCORE domain Reset block Temp. sensor 3 x PLL, HSI, MSI VSS VDD Standby circuitry (Wakeup logic, IWDG) VCORE Core SRAM1 SRAM2 SRAM3 Digital peripherals Voltage regulator Low voltage detector Flash memory Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv38489V1 DS12024 Rev 4 23/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Figure 4. STM32L4S9xx power supply overview VDDA domain VDDA VSSA 3 x A/D converters 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer VDDUSB VSS VDDIO2 VSS VDDDSI VCAPDSI USB transceivers VDDIO2 domain VDDIO2 I/O ring PG[15:2] DSI voltage regulator VDD12DSI DSI PHY VDD domain VDDIO1 I/O ring VCORE domain Reset block Temp. sensor 3 x PLL, HSI, MSI VSS VDD Standby circuitry (Wakeup logic, IWDG) VCORE Voltage regulator Low voltage detector Core SRAM1 SRAM2 SRAM3 Digital peripherals Flash memory Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv38488V1 During power-up and power-down phases, the following power sequence requirements must be respected: 24/273 • When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB and VLCD) must remain below VDD +300 mV. • When VDD is above 1 V, all power supplies are independent. • During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the powerdown transient phase. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview Figure 5. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDIO2, VDDUSB and VLCD. 3.10.2 Power supply supervisor The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices have an integrated ultralow-power Brownout reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the devices after power-on and during power-down. The devices remain in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The devices feature an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the devices embed a peripheral voltage monitor which compares the independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 3.10.3 Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is also used to supply the 64 Kbytes SRAM2 in standby with RAM2 retention. • Both regulators are in power-down while they are in standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. DS12024 Rev 4 25/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx The ultra-low-power STM32L4Sxxx devices support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. The main regulator operates in the following ranges: • Range 1 boost mode with the CPU running at up to 120 MHz. • Range 1 normal mode with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • Note: 26/273 Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by the HSI16. The USB and DSIHOST can only be used when the main regulator is in range1 boost mode. DS12024 Rev 4 Low-power modes The ultra-low-power STM32L4Sxxx devices support seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wake-up sources. Table 4 shows the related STM32L4Sxxx modes overview. Table 4. STM32L4S5xx modes overview Mode Regulator(1) CPU Flash SRAM Clocks LPRun Range2 LPR Yes ON (3) ON Any All except OTG_FS, RNG, LCD-TFT Yes ON(3) ON Any except PLL All except OTG_FS, RNG, LCD-TFT No ON(3) ON(4) Any DS12024 Rev 4 LPSleep Range 2 LPR No ON(3) ON(4) No N/A ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) *** All other peripherals are frozen Any interrupt or event Any interrupt or event Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) OTG_FS(7) 27/273 Functional overview Range 2 Off All except OTG_FS, RNG, LCD-TFT Any All except OTG_FS, RNG, LCD-TFT except PLL Range 1 Stop 0 N/A All Range 1 Sleep Wakeup source All Range 1 Run DMA & Peripherals(2) STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.10.4 Mode Stop 1 LPR LPR CPU No No Flash Off Off LPR Standby Shutdown OFF OFF SRAM ON ON Clocks DMA & Peripherals(2) Wakeup source LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) OTG_FS(7) LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(6) LPUART1(5) LPTIM1 *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(6) LPUART1(5) LPTIM1 LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off *** I/O configuration can be floating, pullup or pull-down Reset pin 5 I/Os (WKUPx)(8) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off *** I/O configuration can be floating, pullup or pull-down(9) Reset pin 5 I/Os (WKUPx)(8) RTC SRAM2 ON Powered Off Powered Off Off Off Powered Off Powered Off STM32L4S5xx, STM32L4S7xx and STM32L4S9xx DS12024 Rev 4 Stop 2 Regulator Functional overview 28/273 Table 4. STM32L4S5xx modes overview (continued) (1) 2. All peripherals can be active or clock gated to save power consumption. 3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently. 5. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 6. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 7. OTG_FS wakeup by resume from suspend and attach detection protocol event. 8. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 1. LPR means Main regulator is OFF and Low-power regulator is ON. Functional overview 29/273 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the Low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode to detect their wake-up condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The Brownout reset (BOR) always remains active in Standby mode. The state of each I/O during Standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1, SRAM3 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be 30/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview retained in Standby mode, supplied by the low-power regulator (standby with RAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. • Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. DS12024 Rev 4 31/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 5. Functionalities depending on the working mode(1) - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (192 Kbytes) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (64 Kbytes) Y Y(3) Y Y(3) Y - Y - O(4) - - - - SRAM3 (384 Kbytes) Y Y(3) Y Y(3) Y - Y(3) - - - - - - FSMC O O O O - - - - - - - - - OctoSPIs O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brownout reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - DMA2D O O O O - - - - - - - - - High speed internal (HSI16) O O O O (5) - (5) - - - - - - Oscillator HSI48 O O - - - - - - - - - - - High speed external (HSE) O O O O - - - - - - - - - Low speed internal (LSI) O O O O O - O - O - - - - Low speed external (LSE) O O O O O - O - O - O - O Multi speed internal (MSI) O O O O - - - - - - - - - Clock security system (CSS) O O O O - - - - - - - - - Peripheral CPU Flash memory (2 Mbytes) 32/273 Run Sleep Lowpower run Lowpower sleep - DS12024 Rev 4 Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - Clock security system on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 Camera interface O O O O - - - - - - - - - LCD-TFT O O - - - - - - - - - - - GFXMMU O O O O - - - - - - - - - DSIHOST O O - - - - - - - - - - - O(8) - - - O - - - - - - - - - - - - - - Peripheral USB OTG FS Run O (8) Sleep Lowpower run Lowpower sleep - Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT USARTx (x=1,2,3,4,5) O O O O O(6) O(6) Low-power UART (LPUART) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2,4) O O O O O(7) O(7) (7) - - - - - - - O(7) O(7) O(7) - - - - - I2C3 O O O O O SPIx (x=1,2,3) O O O O - - - - - - - - - CAN(x=1,2) O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SAIx (x=1,2) O O O O - - - - - - - - - DFSDM1 O O O O - - - - - - - - - ADC O O O O - - - - - - - - - DACx (x=1,2) O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - DS12024 Rev 4 33/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 5. Functionalities depending on the working mode(1) (continued) - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - AES hardware accelerator O O O O - - - - - - - - - HASH hardware accelerator O O O O - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available. Gray cells highlight the wakeup capability in each mode. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the RRSTP bit in PWR_CR1 register. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 34/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.10.5 Functional overview Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.10.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when there is no external battery and when an external supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode. The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation. 3.11 Interconnect matrix Several peripherals have direct connections between them, which allow autonomous communication between them and support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency. Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 6 for more details. Stop 0 / Stop 1 Stop 2 ADCx Low-power sleep COMPx Low-power run TIMx Sleep Interconnect source Run Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADC DACx DFSDM1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - TIM1, 8 TIM2, 3 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - - Interconnect destination Interconnect action DS12024 Rev 4 Y 35/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx peripherals interconnect matrix (continued) TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - USB Timer triggered by USB SOF Y Y - - - - Timer break Y Y Y Y - - TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADC DACx DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect source RTC Interconnect destination TIM2 CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) TIM1,8 COMPx TIM15,16,17 PVD DFSDM1 (analog watchdog, short circuit detection) GPIO Interconnect action 1. LPTIM1 only. 36/273 DS12024 Rev 4 Y Y STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.12 Functional overview Clocks and startup The clock controller (see Figure 6) distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low-power modes and ensures the clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. • Safe clock switching: clock sources can be changed safely on the fly in Run mode through a configuration register. • Clock management: to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 120 MHz. • RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG, the two SAIs, LCDTFT and DSI-HOST. When using DSI-HOST peripheral, the high-speed external crystal (HSE) must be available. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS12024 Rev 4 37/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application – LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 120 MHz. 38/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview Figure 6. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN MCO to PWR LSE LSI MSI HSI16 HSE SYSCLK / 1→16 to AHB bus, core, memory and DMA AHB PRESC / 1,2,..512 HCLK PLLCLK HSI48 to Cortex system timer /8 Clock source control OSC_OUT HSE OSC 4-48 MHz OSC_IN Clock detector FCLK Cortex free running clock APB1 PRESC / 1,2,4,8,16 HSE PCLK1 to APB1 peripherals x1 or x2 MSI SYSCLK HSI16 LSE HSI16 SYSCLK to USARTx X=2..5 to LPUART1 HSI RC 16 MHz HSI16 SYSCLK MSI RC 100 kHz – 48 MHz PLL MSI HSI16 HSE /M /P PLLSAI3CLK /Q PLL48M1CLK /R PLLCLK to LPTIMx x=1,2 MSI OCTOSPI clock CRS clock PCLK2 APB2 PRESC / 1,2,4,8,16 HSI16 /M PLLSAI1 to I2Cx x=1,2,3,4 LSI LSE HSI16 RC 48 MHz to TIMx x=2..7 /P PLLSAI1CLK /Q PLL48M2CLK /R PLLADC1CLK to APB2 peripherals x1 or x2 to TIMx x=1,8,15,16,17 LSE HSI16 SYSCLK to USART1 SDMMC clock HSI16 MSI 48 MHz clock to USB, RNG SYSCLK HSE DSI PLL ≤ 20 MHz DSI - PHY ≤ 62.5 MHz < 62.5 MHz MSI HSI16 /M PLLSAI2 /P PLLSAI2CLK /Q PLLDSICLK /R PLLLCDCLK to ADC DSIHOST byte lane clock DSIHOST rxclkesc clock DFSDM audio clock to SAI1 HSI16 PLLSAI2DIVR SAI1_EXTCLK LTDC clock to SAI2 SAI2_EXTCLK MSv38434V7 DS12024 Rev 4 39/273 64 Functional overview 3.13 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.14 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations. The two DMA controllers have 14 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) – Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size • Support for circular buffer management • 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536 Table 7. DMA implementation 40/273 DMA features DMA1 DMA2 Number of regular channels 7 7 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.15 Functional overview DMA request router (DMAMux) When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product. An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs. For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs. 3.16 Chrom-ART Accelerator (DMA2D) Chrom-ART Accelerator (DMA2D) is a graphic accelerator that offers an advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp direct color. It embeds a dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.17 Chrom-GRC (GFXMMU) The Chrom-GRC (GFXMMU) is a graphical oriented memory management unit aimed to: • Optimize memory usage according to the display shape • Manage packing/unpacking for 24 bpp frame buffers The Chrom-GRC features: • Fully programmable display shape to physically store only the visible pixel • Up to four virtual buffers • Each virtual buffer have 4096 bytes per line and 1024 lines • Each virtual buffer can be physically mapped to any system memory • 24 bpp packing unit to store unpacked 24bpp data in a packed 24 bpp • Packing/un-packing management per buffer • Interrupt in case of buffer overflow (1 per buffer) • Interrupt in case of memory transfer error DS12024 Rev 4 41/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.18 Interrupts and events 3.18.1 Nested vectored interrupt controller (NVIC) The STM32L4S5xx, STM32L4S7xx and STM32L4S9xxdevices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to 95 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.18.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 36 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 42/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.19 Functional overview Analog-to-digital converter (ADC) The device embeds a successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1 and DAC2 outputs • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.19.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into a data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channels which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. DS12024 Rev 4 43/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 8. Temperature sensor calibration values 3.19.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.19.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware enables the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third of the VBAT voltage. 3.20 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 44/273 • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.21 Voltage reference buffer (VREFBUF) The STM32L4Sxxx devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 7. Voltage reference buffer VREFBUF VDDA Bandgap DAC, ADC + VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 3.22 Comparators (COMP) The STM32L4Sxxx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can also be combined into a window comparator. DS12024 Rev 4 45/273 64 Functional overview 3.23 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Operational amplifier (OPAMP) The STM32L4Sxxx devices embed two operational amplifiers with external or internal follower routing and PGA capability. The operational amplifier features: 3.24 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution to add capacitive sensing functionality to any application. A capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (glass, plastic or other). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. The main features of the touch sensing controller are the following: Note: 46/273 • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.25 Functional overview LCD-TFT controller (LTDC) The LCD-TFT display controller provides a 24-bit parallel digital RGB (red, green, blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels with the following features: 3.26 • Two displays layers with dedicated FIFO (64 x 32-bit) • Color look-up table (CLUT) up to 256 colors (256 x 24-bit) per layer • Up to 8 input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to four programmable interrupt events DSI Host (DSIHOST) The DSI Host is a dedicated IP that interfaces with the MIPI® DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. The interfaces are as follows: • • • LTDC interface: – Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI) – Used to transmit information in full bandwidth in the Adapted Command Mode (DBI) through a custom mode APB slave interface: – Allows the transmission of generic information in Command mode, and follows a proprietary register interface – Can operate concurrently with either LTDC interface in either Video Mode or Adapted Command Mode Video mode pattern generator: – Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli DS12024 Rev 4 47/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx The DSI Host main features are: • Compliant with MIPI® Alliance standards • Interface with MIPI® D-PHY • Supports all commands defined in the MIPI® Alliance specification for DCS: – Transmission of all Command mode packets through the APB interface – Transmission of commands in low-power and high-speed during Video Mode • Supports up to two D-PHY data lanes • Bidirectional communication and escape mode support through data lane 0 • Supports non-continuous clock in D-PHY clock lane for additional power saving • Supports Ultra Low-Power mode with PLL disabled • ECC and Checksum capabilities • Support for end of transmission packet (EoTp) • Fault recovery schemes • Configurable selection of system interfaces: • – AMBA APB for control and optional support for generic and DCS commands – Video Mode interface through LTDC – Adapted command mode interface through LTDC Independently programmable virtual channel ID in – Video mode – Adapted command mode – APB Slave Video Mode interfaces features: • LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2 and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB • Programmable polarity of all LTDC interface signals • Maximum resolution is limited by available DSI physical link bandwidth: – Number of lanes: 2 – Maximum speed per lane: 500 Mbps Adapted interface features: • Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands • LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2 and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB Video mode pattern generator: 48/273 • Vertical and horizontal color bar generation without LTDC stimuli • BER pattern without LTDC stimuli DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.27 Functional overview Digital filter for sigma-delta modulators (DFSDM) The STM32L4Sxxx devices embed one DFSDM with four digital filters modules and eight external input serial channels (transceivers) or alternately eight internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). The DFSDM can also interface the PDM (pulse density modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators) and the DFSDM digital filter modules perform digital processing according to the user’s selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – Configurable SPI interface to connect various SD modulator(s) – Configurable Manchester coded 1 wire interface support – PDM (pulse density modulation) microphone input support – Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – Clock output for SD modulator(s): 0..20 MHz Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution): – • Internal sources: device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – Integrator: oversampling ratio (1..256) • Up to 24-bit output data resolution, signed output data format • Automatic data offset correction (offset stored in register by user) • Continuous or single conversion • Start-of-conversion triggered by: • • – Software trigger – Internal timers – External events – Start-of-conversion synchronously with first digital filter module (DFSDM0) Analog watchdog feature: – Low value and high-value data threshold registers – Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – Input from final output data or from selected input digital serial channels – Continuous monitoring independently from standard conversion Short circuit detector to detect saturated analog input values (bottom and top range): – Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – Monitoring continuously each input serial channel DS12024 Rev 4 49/273 64 Functional overview 3.28 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx • Break signal generation on analog watchdog event or on short circuit detector event • Extremes detector: – Storage of minimum and maximum values of final conversion data – Refreshed by software • DMA capability to read the final conversion data • Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “Regular” or “injected” conversions: – “Regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions – “Injected” conversions for precise timing and with high conversion priority Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.29 Digital camera interface (DCMI) The STM32L4Sxxx devices embed a camera interface that can connect with any camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface in order to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbytes/s at 54 MHz. It features: 50/273 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication of 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.30 Functional overview Advanced encryption standard hardware accelerator (AES) The STM32L4Sxxx devices embed an AES hardware accelerator that can be used both to encipher and to decipher data using an AES algorithm. The AES peripheral supports: 3.31 • Encryption/decryption using AES Rijndael block cipher algorithm • NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm • 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x 32-bit registers) • Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher Message Authentication Code mode (CMAC) supported • Key scheduler • Key derivation for decryption • 128-bit data block processing • 128-bit, 256-bit key length • 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer • Register access supporting 32-bit data width only • One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC mode • Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data • Suspend a message if another message with a higher priority needs to be processed. HASH hardware accelerator (HASH) The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications. It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1, SHA-224, SHA-256 or MD5 hash function twice. 3.32 Timers and watchdogs The STM32L4Sxxx devices include two advanced control timers, up to nine generalpurpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The Table 10 below compares the features of the advanced control, general-purpose and basic timers. DS12024 Rev 4 51/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1, TIM8 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2, TIM5 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.32.1 Advanced-control timer (TIM1, TIM8) The advanced-control timers can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The four independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs. Many features are shared with the general-purpose TIMx timers (described in Section 3.32.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 52/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.32.2 Functional overview General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L4Sxxx devices (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, TIM4 and TIM5 They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature four independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has two channels and one complementary channel – TIM16 and TIM17 have one channel and one complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.32.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.32.4 Low-power timer (LPTIM1 and LPTIM2) The STM32L4Sxxx devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. DS12024 Rev 4 53/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx This low-power timer supports the following features: 3.32.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only). Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.32.6 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.32.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 54/273 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.33 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month • Two programmable alarms • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy • Three anti-tamper detection pins with programmable filter • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (alarm, wake-up timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 3.34 Inter-integrated circuit interface (I2C) The device embeds four I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. DS12024 Rev 4 55/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx The I2C peripheral supports: • I2C-bus specification and user manual rev. 5 compatibility: – • Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System management bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power system management protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 6: Clock tree • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X Wakeup from Stop 0, Stop 1 mode on address match X X X X Wakeup from Stop 2 mode on address match - - X - 1. X: supported 56/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.35 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L4Sxxx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable. They are able to communicate at speeds of up to 10 Mbit/s. The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 12. USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X - - - Smartcard mode X X X - - - Single-wire half-duplex communication X X X X X X IrDA SIR ENDEC block X X X X X - LIN mode X X X X X - Dual clock domain X X X X X X Wakeup from Stop 0 / Stop 1 modes X X X X X X Wakeup from Stop 2 mode - - - - - X Receiver timeout interrupt X X X X X - Modbus communication X X X X X - Auto baud rate detection Driver enable X (4 modes) X X LPUART/USART data length X X X X 7, 8 and 9 bits 1. X = supported. DS12024 Rev 4 57/273 64 Functional overview 3.36 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Low-power universal asynchronous receiver transmitter (LPUART) The STM32L4Sxxx devices embed one low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interface can be served by the DMA controller. 3.37 Serial peripheral interface (SPI) Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.38 Serial audio interfaces (SAI) The STM32L4Sxxx devices embed two SAI. Refer to Table 13: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: 58/273 • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. Table 13. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) SPDIF X X PDM X - FIFO size 1. X: supported 3.39 Controller area network (CAN) The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated. DS12024 Rev 4 59/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx The CAN peripheral supports: • CAN protocol version 2.0 A, B Active • Bit rates of up to 1 Mbit/s • Transmission • • • 3.40 – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – Scalable filter banks: 28 filter banks – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards Interface (SDMMC) The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices. The SDMMC features include the following: 60/273 • Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (backward compatibility) • Full compliance with SD Memory Card Specifications Version 4.1. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported) • Full compliance with SDIO Card Specification Version 4.0: card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported) • Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO speed) • Data and command output enable signals to control external bidirectional drivers. DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 3.41 Functional overview Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE). The major features are: • Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • Eight host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • Software configurable to OTG 1.3 and OTG 2.0 modes of operation • OTG 2.0 Supports ADP (Attach detection Protocol) • USB 2.0 LPM (Link Power Management) support • Battery charging specification revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. The synchronization for this oscillator can also be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.42 Clock recovery system (CRS) The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.43 Flexible static memory controller (FSMC) The flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller This memory controller is also named flexible memory controller (FMC). DS12024 Rev 4 61/273 64 Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (four memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data – Ferroelectric RAM (FRAM) • 8-,16- bit data bus width • Independent chip select control for each memory bank • Independent configuration for each memory bank • Write FIFO • The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 3.44 OctoSPI interface (OctoSPI) The OctoSPI is a specialized communication interface targetting single, dual, quad or octal SPI memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the OctoSPI registers • Status polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation The OctoSPI supports two frame formats: • Classical frame format with command, address, alternate byte, dummy cycles and data phase over 1, 2, 4 or 8 data pins • HyperBusTM frame format The OctoSPI offers the following features: 62/273 • Three functional modes: indirect, status-polling, and memory-mapped • Read and write support in memory-mapped mode • Supports for single, dual, quad and octal communication • Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two quad memories in parallel. • SDR and DTR support • Data strobe support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx • 3.45 Functional overview Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • HyperBusTM support • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error OctoSPI IO manager (OctoSPIIOM) The OctoSPI IO Manager is a low level interface allowing: • Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map) • Multiplexing single/dual/quad/octal SPI interface over the same bus The OctoSPI IO Manager has the following features: • Support up to two single/dual/quad/octal SPI Interface • Support up to eight ports for pin assignment • Fully programmable IO matrix for pin assignment by function (data/control/clock) • Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus 3.46 Development support 3.46.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DS12024 Rev 4 63/273 64 Functional overview 3.46.2 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L4Sxxx devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 64/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 4 Pinouts and pin description Pinouts and pin description Figure 8. STM32L4S5xx and STM32L4S7xx UFBGA169 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 A PI10 PH2 VDD PE0 PB4 PB3 VSS VDD PA15 PA14 PA13 PI0 PH14 B PI9 PI7 VSS PE1 PB5 VDDIO2 PG9 PD0 PI6 PI2 PI1 PH15 PH12 C VDD VSS PI11 PB8 PB6 PG15 PD4 PD1 PH13 PI3 PI8 VSS VDD D PE4 PE3 PE2 PB9 PB7 PG10 PD5 PD2 PC10 PI4 PH9 PH7 PA12 E PC13 VBAT PE6 PE5 PH3-BOOT0 PG11 PD6 PD3 PC11 PI5 PH6 VDDUSB PA11 F PC14OSC32_IN VSS PF2 PF1 PF0 PG12 PD7 PC12 PA10 PA9 PC6 VDDIO2 VSS G PC15OSC32_OUT VDD PF3 PF4 PF5 PG14 PG13 PA8 PC9 PC8 PG6 PC7 VDD H PH0-OSC_IN VSS NRST PF10 PC4 PG1 PE10 PB11 PG8 PG7 PD15 VSS VDD J PH1OSC_OUT PC0 PC1 PC2 PC5 PG0 PE9 PE15 PG5 PG4 PG3 PG2 PD10 K PC3 VSSA/VREF- PA0 PA5 PB0 PF15 PE8 PE14 PH4 PD14 PD12 PD11 PD13 L VREF+ VDDA PA4 PA7 PB1 PF14 PE7 PE13 PH5 PD9 PD8 VDD VSS M OPAMP1_VI NM PA3 VSS PA6 PF11 PF13 VSS PE12 PH10 PH11 VSS PB15 PB14 N PA2 PA1 VDD OPAMP2_VI NM PB2 PF12 VDD PE11 PB10 PH8 VDD PB12 PB13 MSv38036V4 1. The above figure shows the package top view. Figure 9. STM32L4S9xx UFBGA169 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 A PI10 PH2 VDD PE0 PB4 PB3 VSS VDD PA15 PA14 PA13 PI0 PH14 B PI9 PI7 VSS PE1 PB5 VDDIO2 PG9 PD0 PI6 PI2 PI1 PH15 PH12 C VDD VSS PI11 PB8 PB6 PG15 PD4 PD1 PH13 PI3 PH9 VSS VDD D PE4 PE3 PE2 PB9 PB7 PG10 PD5 PD2 PC10 PI4 PA10 VDDUSB PA12 E PC13 VBAT PE6 PE5 PH3-BOOT0 PG11 PD6 PD3 PC11 PI5 PA8 PA9 PA11 F PC14OSC32_IN VSS PF2 PF1 PF0 PG12 PD7 PC12 PC8 PG8 PC6 VDDIO2 VSS G PC15OSC32_OUT VDD PF3 PF4 PF5 PG13 PG4 PG3 PG5 PG7 PC7 PG6 PC9 H PH0-OSC_IN VSS NRST PF10 PG1 PE10 PB11 PD13 PG2 PD15 PD14 VSS VDD J PH1OSC_OUT PC0 PC1 PC2 PG0 PE9 PE15 PD12 PD11 PD10 DSI_D1P DSI_D1N VSSDSI K PC3 VSSA/VREF- PA0 PC4 PF15 PE8 PE14 PH4 PD9 PD8 DSI_CKP DSI_CKN VSSDSI L VREF+ VDDA PA5 PA6 PB1 PF14 PE7 PE13 PH5 PB15 DSI_D0P DSI_D0N VCAPDSI M PA1 PA3 VSS PA7 PF11 PF13 VSS PE12 PH10 PH11 VSS PB14 VDDDSI N PA2 PA4 VDD PB0 PB2 PF12 VDD PE11 PB10 PH8 VDD PB12 PB13 MSv45223V2 1. The above figure shows the package top view. DS12024 Rev 4 65/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx VDD VSS PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Figure 10. STM32L4S5xx and STM32L4S7xx LQFP144 pinout(1) PE2 PE3 PE4 PE5 1 2 3 4 108 VDD 107 VSS 106 VDDUSB 105 PA13 PE6 5 104 PA12 VBAT 6 103 PA11 PC13 7 PC14-OSC32_IN 8 102 101 PA10 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 PF2 12 98 97 PC8 PC7 PF3 13 96 PC6 PF4 14 95 VDDIO2 PF5 15 94 VSS VSS 16 93 PG8 VDD 17 92 PG7 PF6 18 91 PG6 PF7 19 90 PG5 PF8 20 89 PG4 PF9 21 88 PG3 PF10 22 87 PG2 PH0-OSC_IN 23 86 PD15 PH1-OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 29 80 PD11 VSSA 30 79 PD10 VREF- 31 78 PD9 VREF+ 32 77 PD8 VDDA 33 76 PB15 PA0 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD LQFP144 MSv45224V1 1. The above figure shows the package top view. 66/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description VDD VSS PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDDIO2 VSS PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Figure 11. STM32L4S9xx LQFP144 pinout(1) PE2 PE3 PE4 PE5 1 2 3 4 108 VDDUSB 107 PA13 106 PA12 105 PA11 PA10 PE6 5 104 VBAT 6 103 PA9 PC13 7 PC14-OSC32_IN 8 102 101 PA8 PC9 PC15-OSC32_OUT 9 100 PC8 PF0 10 99 PC7 PF1 11 PF2 12 98 97 PC6 PG8 PF3 13 96 PG7 PF4 14 95 PG6 PF5 15 94 PG5 VSS 16 93 PG4 VDD 17 92 PG3 PF6 18 91 PG2 PF7 19 90 PD15 PF10 20 89 PD14 PH0-OSC_IN 21 88 VDD PH1-OSC_OUT 22 87 VSS NRST 23 86 PD13 PC0 24 85 PD12 PC1 25 84 PD11 PC2 26 83 PD10 PC3 27 82 PD9 VSSA/VREF- 28 81 PD8 VREF+ 29 80 VDD12DSI VDDA 30 79 DSI_CKN PA0 31 78 DSI_CKP PA1 32 77 VSSDSI PA2 33 76 DSI_D0N PA3 34 75 DSI_D0P VSS 35 74 VCAPDSI VDD 36 73 VDDDSI 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD PB12 PB13 PB14 PB15 LQFP144 MSv45225V1 1. The above figure shows the package top view. DS12024 Rev 4 67/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Figure 12. STM32L4S9xx UFBGA144 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A VSS PE0 PB9 PH3-BOOT0 PB4 VDDIO2 VSS PD3 PC11 PA14 VDD VSS B VBAT VDD PE3 PB8 PB5 PB3 PD6 PD1 PA15 PA13 PA12 PA11 C VSS PE5 PE2 PE1 PB7 PG13 PD4 PD0 PC10 PA10 VDDUSB PC9 D PC14OSC32_IN PC15OSC32_OUT PE4 PE6 PB6 PG12 PD5 PD2 PC12 PA9 PA8 PC6 E PF2 PF1 PF0 PC13 PF3 PG10 PD7 PG8 PC7 PC8 PG7 VDDIO2 F PF8 PF6 PF4 PF5 PF7 PG9 PG3 PG5 PG6 PG4 VSS PG2 G VDD VSS PF10 PF9 PF12 PE7 PD15 PD14 PD12 PD13 PD11 VDD H PH0-OSC_IN PH1OSC_OUT PC0 PC2 PB2 PF15 PE11 PD10 PD9 PD8 DSI_D1P DSI_D1N J NRST PC1 PC3 PA6 PB1 PF13 PE9 PE13 PB15 VSSDSI DSI_CKP DSI_CKN K VSSA/VREF- VREF+ PA0 PA4 PC5 PF11 PE8 PE15 PB11 PB14 DSI_D0P DSI_D0N L VDDA PA1 PA2 PA5 PC4 VSS PG0 PE10 PB10 PB12 VDD VCAPDSI M VSS VDD PA3 PA7 PB0 VDD PF14 PG1 PE12 PE14 PB13 VSS MSv38491V4 1. The above figure shows the package top view. Figure 13. STM32L4S9xx WLCSP144 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A VSS PA14 PA15 PD0 PD5 VDD PG12 VDDIO2 PB7 PE0 PE1 VSS B VDD VDDUSB PA13 PC12 PD2 VSS PG10 PB3 PH3-BOOT0 PB9 PE2 VDD C PA11 PA12 PC10 PC11 PD1 PD4 PG9 PB4 PB6 PB8 PE3 PE4 D PC8 PC9 PA8 PA9 PA10 PD3 PD7 PG13 PE5 PE6 PC13 VSS E PG7 PG8 VDDIO2 PC6 PG6 PC7 PD6 PB5 PF0 VBAT PC14OSC32_IN PC15OSC32_OUT F PD15 PG2 PD14 PD12 PG3 PG4 PG5 PF1 PF5 PF4 PF3 PF2 G VSS VDD PD13 PD11 PD10 PE9 PF14 PA5 PF7 PF6 VSS VDD H PD9 PD8 PB14 PB13 PE14 PE8 PB1 PA2 PC2 PF10 NRST PH0-OSC_IN J DSI_D1N DSI_D1P PB15 PB12 PE13 PF15 PB2 PA6 PA0 PC3 PC0 PH1OSC_OUT K DSI_CKP DSI_CKN VSSDSI PE15 PE10 PG0 PF11 PC5 PA4 PA1 VSSA/VREF- PC1 L DSI_D0P DSI_D0N VCAPDSI PB10 PE11 PG1 VDD PF12 PC4 PA3 VREF+ VDDA M VDD VDD VSS PB11 PE12 PE7 PF13 VSS PB0 PA7 VDD VSS MSv42219V2 1. The above figure shows the package top view 68/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Figure 14. STM32L4S5xx WLCSP144 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A VSS PA14 PA15 PD0 PD5 VDD PG12 VDDIO2 PB7 PE0 PE1 VSS B VDD VDDUSB PA13 PC12 PD2 VSS PG10 PB3 PH3-BOOT0 PB9 PE2 VDD C PA11 PA12 PC10 PC11 PD1 PD4 PG9 PB4 PB6 PB8 PE3 PE4 D PC8 PC9 PA8 PA9 PA10 PD3 PD7 PG13 PE5 PE6 PC13 VSS E PG7 PG8 VDDIO2 PC6 PG6 PC7 PD6 PB5 PF0 VBAT PC14OSC32_IN PC15OSC32_OUT F PD15 PG2 PD14 PD12 PG3 PG4 PG5 PF1 PF5 PF4 PF3 PF2 G VSS VDD PD13 PD11 PD10 PE9 PF14 PA5 PF7 PF6 VSS VDD H PD9 PD8 PB14 PB13 PE14 PE8 PB1 PA2 PC2 PF10 NRST PH0-OSC_IN J NC NC PB15 PB12 PE13 PF15 PB2 PA6 PA0 PC3 PC0 PH1OSC_OUT K NC NC VSS PE15 PE10 PG0 PF11 PC5 PA4 PA1 VSSA/VREF- PC1 L NC NC NC PB10 PE11 PG1 VDD PF12 PC4 PA3 VREF+ VDDA M VDD VDD VSS PB11 PE12 PE7 PF13 VSS PB0 PA7 VDD VSS MSv43442V1 1. The above figure shows the package top view. NC (not-connected) balls must be left unconnected. Figure 15. STM32L4S5xx UFBGA132 ballout(1) 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 PG14 PG13 PD2 PD0 PC11 VDDUSB PA10 D PC14OSC32_IN PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PF3 PG5 PC8 PC7 PC6 F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS G PH1OSC_OUT VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13 J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10 K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12 M VDDA PA1 OPAMP1_VI NM OPAMP2_VI NM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 MSv38035V5 1. The above figure shows the package top view. DS12024 Rev 4 69/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx VDD VSS PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 16. STM32L4S5xx and STM32L4S7xx LQFP100 pinout(1) PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDDUSB PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD LQFP100 MSv38494V1 1. The above figure shows the package top view. 70/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description 9'' 966 3% 3% 3+%227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 966                          Figure 17. STM32L4S9xx LQFP100 pinout(1) 3(   9''86% 3(   3$ 3(   3$ 3(   3$ 3(   3$ 9%$7   3$ 3&   3$ 3&26&B,1   3& 3&26&B287   3& 966   3& 9''   3& 3+26&B,1   3' 3+26&B287   3' 1567   3' 3&   3' 3&   3' 3&   9'''6, 3&   '6,B&.1 966$95()   '6,B&.3 9''$95()   966'6, 3$   '6,B'1 3$   '6,B'3 3$   9&$3'6, 3$   9'''6, 966   3%                        3$ 3$ 3$ 3$ 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' 3% 3% 3%   9'' /4)3 06Y9 1. The above figure shows the package top view. DS12024 Rev 4 71/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 14. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os I/O structure _f (1) I/O, Fm+ capable _l (2) Notes I/O, with LCD function supplied by VLCD _u (3) I/O, with USB function supplied by VDDUSB _a (4) I/O, with Analog switch function supplied by VDDA _s (5) I/O supplied only by VDDIO2 Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 15 are: FT_f, FT_fa, FT_fl, FT_fla. 2. The related I/O structures in Table 15 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 15 are: FT_u, FT_lu. 4. The related I/O structures in Table 15 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. The related I/O structures in Table 15 are: FT_s, FT_fs. 72/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions Pin Number LQFP144 WLCSP144 UFBGA169 LQFP100 LQFP144 UFBGA144 WLCSP144 Pin type I/O structure Notes Alternate functions UBGA132 Pin name (functio n after reset) LQFP100 STM32L4S5xx STM32L4S7xx - - - - M11 - - - - M11 VSS S - - - - - - - - C1 - - - - C1 VDD S - - - - - - - - C3 - - - - C3 PI11 I/O FT - OCTOSPIM_P2_IO0 , EVENTOUT - - TRACECK, TIM3_ETR, SAI1_CK1, TSC_G7_IO1, LCD_R0, FMC_A23, SAI1_MCLK_A, EVENTOUT - - TRACED0, TIM3_CH1, OCTOSPIM_P1_DQ S, TSC_G7_IO2, LCD_R1, FMC_A19, SAI1_SD_B, EVENTOUT - - TRACED1, TIM3_CH2, SAI1_D2, DFSDM1_DATIN3, TSC_G7_IO3, DCMI_D4, LCD_B0, FMC_A20, SAI1_FS_A, EVENTOUT - - TRACED2, TIM3_CH3, SAI1_CK2, DFSDM1_CKIN3, TSC_G7_IO4, DCMI_D6, LCD_G0, FMC_A21, SAI1_SCK_A, EVENTOUT - RTC_TAMP3, WKUP3 - 1 2 3 4 B2 A1 B1 C2 1 2 3 4 B11 C11 C12 D9 D3 D2 D1 E4 1 2 3 4 1 2 3 4 C3 B3 D3 C2 B11 C11 C12 D9 UFBGA169 STM32L4S9xx D3 D2 D1 E4 PE2 PE3 PE4 PE5 I/O I/O I/O I/O FT_l FT_l FT FT 5 D2 5 D10 E3 5 5 D4 D10 E3 PE6 I/O FT - TRACED3, TIM3_CH4, SAI1_D1, DCMI_D7, LCD_G1, FMC_A22, SAI1_SD_A, EVENTOUT 6 E2 6 E10 E2 6 6 B1 E10 E2 VBAT S - - - DS12024 Rev 4 Additional functions 73/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) UBGA132 LQFP144 WLCSP144 UFBGA169 LQFP100 LQFP144 UFBGA144 WLCSP144 UFBGA169 Pin type I/O structure Pin name (functio n after reset) LQFP100 STM32L4S5xx STM32L4S7xx 7 C1 7 D11 E1 7 7 E4 D11 E1 PC13 I/O FT 8 D1 8 E11 F1 8 8 D1 E11 F1 PC14OSC32_ IN (PC14) I/O FT I/O FT I/O FT_f STM32L4S9xx 9 E1 9 E12 G1 9 9 D2 E12 G1 PC15OSC32_ OUT (PC15) - D6 10 E9 F5 - 10 E3 E9 F5 PF0 Notes Pin Number Alternate functions Additional functions EVENTOUT RTC_TAMP1/R TC_TS/RTC_O UT,WKUP2 EVENTOUT OSC32_IN (2) EVENTOUT OSC32_OUT - I2C2_SDA, OCTOSPIM_P2_IO0 , FMC_A0, EVENTOUT - - (1) (2) (1) (2) (1) - D5 11 F8 F4 - 11 E2 F8 F4 PF1 I/O FT_f - I2C2_SCL, OCTOSPIM_P2_IO1 , FMC_A1, EVENTOUT - D4 12 F12 F3 - 12 E1 F12 F3 PF2 I/O FT - I2C2_SMBA, OCTOSPIM_P2_IO2 , FMC_A2, EVENTOUT - - E4 13 F11 G3 - 13 E5 F11 G3 PF3 I/O FT - OCTOSPIM_P2_IO3 , FMC_A3, EVENTOUT - - F3 14 F10 G4 - 14 F3 F10 G4 PF4 I/O FT - OCTOSPIM_P2_CL K, FMC_A4, EVENTOUT - - F4 15 F9 G5 - 15 F4 F9 G5 PF5 I/O FT - FMC_A5, EVENTOUT - 10 F2 16 G11 F2 10 16 L6 G11 F2 VSS S - - - - 11 G2 17 G12 G2 11 17 G1 G12 G2 VDD S - - - - - - - - 18 G10 - - 18 F2 G10 - PF6 I/O FT - TIM5_ETR, TIM5_CH1, OCTOSPIM_P1_IO3 , SAI1_SD_B, EVENTOUT - - 19 G9 - - 19 F5 G9 - PF7 I/O FT - TIM5_CH2, OCTOSPIM_P1_IO2 , SAI1_MCLK_B, EVENTOUT 74/273 DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) UFBGA169 LQFP100 LQFP144 NC - - - - - 21 NC - - - F1 NC G4 NC - - Pin name (functio n after reset) PF8 I/O PF9 I/O Notes WLCSP144 20 UFBGA169 LQFP144 - WLCSP144 UBGA132 - UFBGA144 LQFP100 STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions FT (3) TIM5_CH3, OCTOSPIM_P1_IO0 , SAI1_SCK_B, EVENTOUT - (3) TIM5_CH4, OCTOSPIM_P1_IO1 , SAI1_FS_B, TIM15_CH1, EVENTOUT - - FT - - 22 H10 H4 - 20 G3 H10 H4 PF10 I/O FT - OCTOSPIM_P1_CL K, DFSDM1_CKOUT, DCMI_D11, SAI1_D3, TIM15_CH2, EVENTOUT 12 F1 23 H12 H1 12 21 H1 H12 H1 PH0OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN 13 G1 24 J12 J1 13 22 H2 J12 J1 PH1OSC_O UT (PH1) I/O FT - EVENTOUT OSC_OUT 14 H2 25 H11 H3 14 23 J1 H11 H3 NRST I-O RST - - - - LPTIM1_IN1, I2C3_SCL, DFSDM1_DATIN4, LPUART1_RX, SAI2_FS_A, LPTIM2_IN1, EVENTOUT ADC1_IN1 - TRACED0, LPTIM1_OUT, SPI2_MOSI, I2C3_SDA, DFSDM1_CKIN4, LPUART1_TX, OCTOSPIM_P1_IO4 , SAI1_SD_A, EVENTOUT ADC1_IN2 - LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, OCTOSPIM_P1_IO5 , EVENTOUT ADC1_IN3 15 16 17 H1 J2 J3 26 27 28 J11 K12 H9 J2 J3 J4 15 16 17 24 25 26 H3 J2 H4 J11 K12 H9 J2 J3 J4 PC0 PC1 PC2 I/O I/O I/O DS12024 Rev 4 FT_fl a FT_fl a FT_l a 75/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) J10 K1 PC3 I/O FT_a - 19 - 30 - - - - - - - VSSA S - - - - 20 - 31 - - - - - - - VREF- S - - - - - J1 - K11 K2 19 28 K1 K11 K2 VSSA/V REF- S - - - - 21 L1 32 L11 L1 - 29 K2 L11 L1 VREF+ S - - - VREFBUF_OU T 22 M1 33 L12 L2 - 30 L1 L12 L2 VDDA S - - - - - - - - - 20 - - - - VDDA/V REF+ S - - - - OPAMP1_VIN P, ADC1_IN5, RTC_TAMP2, WKUP1 UFBGA169 J3 WLCSP144 27 UFBGA144 18 LQFP144 K1 LQFP100 J10 UFBGA169 29 WLCSP144 K2 LQFP144 18 LPTIM1_ETR, SAI1_D1, SPI2_MOSI, OCTOSPIM_P1_IO6 , SAI1_SD_A, LPTIM2_ETR, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number Additional functions ADC1_IN4 23 L2 34 J9 K3 21 31 K3 J9 K3 PA0 I/O FT_a - TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS_NSS, UART4_TX, SAI1_EXTCLK, TIM2_ETR, EVENTOUT - M3 - - M1 - - - - - OPAMP 1_VINM I TT - - - - TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, OCTOSPIM_P1_DQ S, TIM15_CH1N, EVENTOUT OPAMP1_VIN M, ADC1_IN6 - TIM2_CH3, TIM5_CH3, USART2_TX, LPUART1_TX, OCTOSPIM_P1_NC S, SAI2_EXTCLK, TIM15_CH1, EVENTOUT ADC1_IN7, WKUP4/LSCO 24 25 M2 K3 76/273 35 36 K10 H8 N2 N1 22 23 32 33 L2 L3 K10 H8 M1 N1 PA1 PA2 I/O I/O DS12024 Rev 4 FT_l a FT_l a STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) L10 M2 PA3 I/O TT_a - 27 E3 38 M12 H2 25 35 G2 M12 H2 VSS S - - - - 28 H3 39 M11 N3 26 36 M2 M11 N3 VDD S - - - - - OCTOSPIM_P1_NC S, SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, SAI1_FS_B, LPTIM2_OUT, EVENTOUT ADC1_IN9, DAC1_OUT1 - TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR, EVENTOUT ADC1_IN10, DAC1_OUT2 OPAMP2_VIN P, ADC1_IN11 29 30 J4 K4 40 41 K9 G8 L3 K4 27 28 37 38 K4 L4 K9 G8 UFBGA169 M3 WLCSP144 34 UFBGA144 24 LQFP144 M2 LQFP100 L10 UFBGA169 37 WLCSP144 L3 LQFP144 26 TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX, LPUART1_RX, OCTOSPIM_P1_CL K, SAI1_MCLK_A, TIM15_CH2, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number N2 L3 PA4 PA5 I/O I/O TT_a TT_a Additional functions OPAMP1_VOU T, ADC1_IN8 31 L4 42 J8 M4 29 39 J4 J8 L4 PA6 I/O FT_a - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK, SPI1_MISO, USART3_CTS_NSS, LPUART1_CTS, OCTOSPIM_P1_IO3 , TIM16_CH1, EVENTOUT - M4 - - N4 - - - - - OPAMP 2_VINM I TT - - - - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI, OCTOSPIM_P1_IO2 , TIM17_CH1, EVENTOUT OPAMP2_VIN M, ADC1_IN12 32 J5 43 M10 L4 30 40 M4 M10 M4 PA7 I/O DS12024 Rev 4 FT_fl a 77/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) Pin Number LQFP144 WLCSP144 UFBGA169 LQFP100 LQFP144 WLCSP144 UFBGA169 Pin type I/O structure Notes Alternate functions UBGA132 Pin name (functio n after reset) LQFP100 STM32L4S5xx STM32L4S7xx 33 K5 44 L9 H5 31 41 L5 L9 K4 PC4 I/O FT_a - USART3_TX, OCTOSPIM_P1_IO7 , EVENTOUT COMP1_INM, ADC1_IN13 34 L5 45 K8 J5 - - K5 K8 - PC5 I/O FT_a - SAI1_D3, USART3_RX, EVENTOUT COMP1_INP, ADC1_IN14, WKUP5 35 36 M5 M6 46 47 M9 H7 K5 L5 32 33 42 43 UFBGA144 STM32L4S9xx M5 J5 M9 H7 N4 L5 PB0 PB1 I/O I/O TT_l a FT_a Additional functions - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI1_NSS, OPAMP2_VOU USART3_CK, T, ADC1_IN15 OCTOSPIM_P1_IO1 , COMP1_OUT, SAI1_EXTCLK, EVENTOUT - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE, LPUART1_RTS_DE, OCTOSPIM_P1_IO0 , LPTIM2_IN1, EVENTOUT COMP1_INM, ADC1_IN16 COMP1_INP 37 L6 48 J7 N5 34 44 H5 J7 N5 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM1_CKIN0, OCTOSPIM_P1_DQ S, LCD_B1, EVENTOUT - K6 49 K7 M5 - 45 K6 K7 M5 PF11 I/O FT - LCD_DE, DCMI_D12, DSI_TE, EVENTOUT - - J7 50 L8 N6 - 46 G5 L8 N6 PF12 I/O FT - OCTOSPIM_P2_DQ S, LCD_B0, FMC_A6, EVENTOUT - - - 51 M8 - - 47 M1 M8 - VSS S - - - - - - 52 L7 N7 - 48 M6 L7 N7 VDD S - - - - - I2C4_SMBA, DFSDM1_DATIN6, LCD_B1, FMC_A7, EVENTOUT - - K7 78/273 53 M7 M6 - 49 J6 M7 M6 PF13 I/O DS12024 Rev 4 FT STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) G7 L6 PF14 I/O FT_f - - J9 55 J6 K6 - 51 H6 J6 K5 PF15 I/O FT_f - I2C4_SDA, TSC_G8_IO2, LCD_G1, FMC_A9, EVENTOUT - - UFBGA169 M7 WLCSP144 50 UFBGA144 - LQFP144 L6 LQFP100 G7 UFBGA169 54 WLCSP144 J8 LQFP144 - I2C4_SCL, DFSDM1_CKIN6, TSC_G8_IO1, LCD_G0, FMC_A8, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number Additional functions - - H9 56 K6 J6 - 52 L7 K6 J5 PG0 I/O FT - OCTOSPIM_P2_IO4 , TSC_G8_IO3, FMC_A10, EVENTOUT - G9 57 L6 H6 - 53 M8 L6 H5 PG1 I/O FT - OCTOSPIM_P2_IO5 , TSC_G8_IO4, FMC_A11, EVENTOUT - - TIM1_ETR, DFSDM1_DATIN2, LCD_B6, FMC_D4, SAI1_SD_B, EVENTOUT - - TIM1_CH1N, DFSDM1_CKIN2, LCD_B7, FMC_D5, SAI1_SCK_B, EVENTOUT - - 38 39 M7 L7 58 59 M6 H6 L7 K7 35 36 54 55 G6 K7 M6 H6 L7 K6 PE7 PE8 I/O I/O FT FT 40 M8 60 G6 J7 37 56 J7 G6 J6 PE9 I/O FT - TIM1_CH1, DFSDM1_CKOUT, LCD_G2, FMC_D6, SAI1_FS_B, EVENTOUT - F6 61 - M7 - 57 C1 - M7 VSS S - - - - - G6 62 - - - 58 - - - VDD S - - - - - TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, OCTOSPIM_P1_CL K, LCD_G3, FMC_D7, SAI1_MCLK_B, EVENTOUT - 41 L8 63 K5 H7 38 59 L8 K5 H6 PE10 I/O DS12024 Rev 4 FT 79/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) 43 44 45 46 47 M9 L9 M10 M11 M12 L10 80/273 65 66 67 68 69 L5 M5 J5 H5 K4 L4 N8 M8 L8 K8 J8 N9 39 40 41 42 43 44 60 61 62 63 64 65 H7 M9 J8 M10 K8 L9 L5 M5 J5 H5 K4 L4 N8 M8 L8 K7 J7 N9 Pin name (functio n after reset) PE11 PE12 PE13 PE14 PE15 PB10 I/O I/O I/O I/O I/O I/O DS12024 Rev 4 I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 64 STM32L4S9xx FT FT FT FT FT FT_fl Notes 42 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - TIM1_CH2, DFSDM1_CKIN4, TSC_G5_IO2, OCTOSPIM_P1_NC S, LCD_G4, FMC_D8, EVENTOUT - - TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, TSC_G5_IO3, OCTOSPIM_1_IO0, LCD_G5, FMC_D9, EVENTOUT - - TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, TSC_G5_IO4, OCTOSPIM_P1_IO1 , LCD_G6, FMC_D10, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, OCTOSPIM_P1_IO2 , LCD_G7, FMC_D11, EVENTOUT - - TIM1_BKIN, SPI1_MOSI, OCTOSPIM_P1_IO3 , LCD_R2, FMC_D12, EVENTOUT - - TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, TSC_SYNC, OCTOSPIM_P1_CL K, COMP1_OUT, SAI1_SCK_A, EVENTOUT - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) M4 H7 PB11 I/O FT_fl - - - - - K9 - - - - K8 PH4 I/O FT_f - I2C2_SCL, OCTOSPIM_P2_DQ S, EVENTOUT - - - - - L9 - - - - L9 PH5 I/O FT_f - I2C2_SDA, DCMI_PIXCLK, EVENTOUT - - UFBGA169 K9 WLCSP144 66 UFBGA144 45 LQFP144 H8 LQFP100 M4 UFBGA169 70 WLCSP144 L11 LQFP144 48 TIM2_CH4, I2C4_SDA, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, OCTOSPIM_P1_NC S, DSI_TE, COMP2_OUT, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number Additional functions - - - - - N10 - - - - N10 PH8 I/O FT_f - I2C3_SDA, OCTOSPIM_P2_IO3 , DCMI_HSYNC, EVENTOUT - - - - M9 - - - - M9 PH10 I/O FT - TIM5_CH1, OCTOSPIM_P2_IO5 , DCMI_D1, EVENTOUT - - - - - - M10 - - - - M10 PH11 I/O FT - TIM5_CH2, OCTOSPIM_P2_IO6 , DCMI_D2, EVENTOUT - - - - C2 - - - - C2 VSS S - - - - 49 F12 71 M3 A7 46 67 M12 M3 A7 VSS S - - - - 50 G12 72 M1 N11 47 68 L11 M1 N11 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, SAI2_FS_A, TIM15_BKIN, EVENTOUT - 51 L12 73 J4 N12 48 69 L10 J4 N12 PB12 I/O DS12024 Rev 4 FT 81/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) 53 K12 K11 75 H4 H3 N13 49 M13 50 70 71 M11 K10 H4 H3 N13 M12 Pin name (functio n after reset) PB13 PB14 I/O I/O I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 74 STM32L4S9xx FT_fl FT_fl Notes 52 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS_NSS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - - TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, TSC_G1_IO3, SAI2_MCLK_A, TIM15_CH1, EVENTOUT - - 72 J9 J3 L10 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, SAI2_SD_A, TIM15_CH2, EVENTOUT - - - M2 - VDD S - - - - - 52 73 - - S - - - - - L13 - - - - - VSS S - - - - - - - 53 74 L12 L3 L13 VCAPD SI S - - - - - - - - 54 75 K11 L1 L11 DSI_D0 P I/O - (3) - - - - - - - 55 76 K12 L2 L12 DSI_D0 N I/O - (3) - - - - - - - 56 77 - - J13 VSSDSI S - - - - - - - - - 57 78 J11 K1 K11 DSI_CK P I/O - (3) - - - - - - - 58 79 J12 K2 K12 DSI_CK N I/O - (3) - - 54 K10 76 J3 M12 51 - - - M2 L12 - - - - - - - - - - 82/273 M13 VDDDSI DS12024 Rev 4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin Number LQFP144 WLCSP144 UFBGA169 LQFP100 LQFP144 UFBGA144 WLCSP144 UFBGA169 Pin type I/O structure Notes Alternate functions UBGA132 Pin name (functio n after reset) LQFP100 STM32L4S5xx STM32L4S7xx - - - - - 59 80 - - - VDD12D SI S - - - - - - - - - - - H11 J2 J11 DSI_D1 P I/O - (3) - - - - - - - - - H12 J1 J12 DSI_D1 N I/O - (3) - - - - - - - - - J10 K3 K13 VSSDSI S - - - - - - - K3 - - - - - - VSS S - - - - - - - L3 - - - - - - NC - - - - - - - - L1 - - - - - - NC - - - - - - - - L2 - - - - - - NC - - - - - - - - K1 - - - - - - NC - - - - - - - - K2 - - - - - - NC - - - - - - - - J2 - - - - - - NC - - - - - - - - J1 - - - - - - NC - - - - - - USART3_TX, DCMI_HSYNC, LCD_R3, FMC_D13, EVENTOUT - - USART3_RX, DCMI_PIXCLK, LCD_R4, FMC_D14, SAI2_MCLK_A, EVENTOUT - - 55 56 K9 K8 77 78 H2 H1 STM32L4S9xx L11 L10 60 61 81 82 H10 H9 H2 H1 K10 K9 PD8 PD9 I/O I/O FT FT Additional functions 57 J12 79 G5 J13 62 83 H8 G5 J10 PD10 I/O FT - USART3_CK, TSC_G6_IO1, LCD_R5, FMC_D15, SAI2_SCK_A, EVENTOUT - - - - H13 - - - - - VDD S - - - - - I2C4_SMBA, USART3_CTS_NSS, TSC_G6_IO2, LCD_R6, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT - 58 J11 80 G4 K12 - 84 G11 G4 J9 PD11 I/O DS12024 Rev 4 FT 83/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) J10 F4 K11 - 85 G9 F4 J8 Pin name (functio n after reset) PD12 I/O I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 81 STM32L4S9xx FT_fl Notes 59 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LCD_R7, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT - - 60 H12 82 G3 K13 - 86 G10 G3 H8 PD13 I/O FT_fl - TIM4_CH2, I2C4_SDA, TSC_G6_IO4, FMC_A18, LPTIM2_OUT, EVENTOUT - - 83 G1 H12 - 87 - G1 H12 VSS S - - - - - - 84 G2 G13 - 88 G12 G2 H13 VDD S - - - - 61 H11 85 F3 K10 63 89 G8 F3 H11 PD14 I/O FT - TIM4_CH3, LCD_B2, FMC_D0, EVENTOUT - 62 H10 86 F1 H11 64 90 G7 F1 H10 PD15 I/O FT - TIM4_CH4, LCD_B3, FMC_D1, EVENTOUT - - G10 87 F2 J12 - 91 F12 F2 H9 PG2 I/O FT_s - SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT - - - F9 88 F5 J11 - 92 F7 F5 G8 PG3 I/O FT_s - SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT - F10 89 F6 J10 - 93 F10 F6 G7 PG4 I/O FT_s - SPI1_MOSI, FMC_A14, SAI2_MCLK_B, EVENTOUT - - SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT - - OCTOSPIM_P1_DQ S, I2C3_SMBA, LPUART1_RTS_DE, LCD_R1, DSI_TE, EVENTOUT - - - E9 G4 84/273 90 91 F7 E5 J9 G11 - - 94 95 F8 F9 F7 E5 G9 G12 PG5 PG6 I/O I/O DS12024 Rev 4 FT_s FT_s STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) E1 G10 PG7 I/O FT_f s - - J6 93 E2 H9 - 97 E8 E2 F10 PG8 I/O FT_f s - I2C3_SDA, LPUART1_RX, EVENTOUT - - - 94 D12 F13 - - F11 D12 F13 VSS S - - - - - - 95 E3 F12 - - E12 E3 F12 VDDIO2 S - - - - - TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, SDMMC1_D0DIR, TSC_G4_IO1, DCMI_D0, LCD_R0, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT - - TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1, LCD_R1, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT - - TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2, SDMMC1_D0, EVENTOUT - 63 64 65 E12 E11 E10 96 97 98 E4 E6 D1 F11 G12 G10 65 66 98 99 67 100 D12 E9 E10 E4 E6 D1 UFBGA169 E11 WLCSP144 96 UFBGA144 - LQFP144 H10 LQFP100 E1 UFBGA169 92 WLCSP144 H4 LQFP144 - SAI1_CK1, I2C3_SCL, OCTOSPIM_P2_DQ S, DFSDM1_CKOUT, LPUART1_TX, FMC_INT, SAI1_MCLK_A, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number F11 G11 F9 PC6 PC7 PC8 I/O I/O I/O DS12024 Rev 4 FT FT FT Additional functions - 85/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) 67 68 69 70 71 D12 D11 100 D10 101 C12 102 B12 103 A12 104 86/273 D2 D3 D4 D5 C1 C2 G9 G8 F10 F9 E13 D13 68 101 69 102 70 103 71 104 72 105 73 106 C12 D11 D10 C10 B12 B11 D2 D3 D4 D5 C1 C2 G13 E11 E12 D11 E13 D13 Pin name (functio n after reset) PC9 PA8 PA9 PA10 PA11 PA12 I/O I/O I/O I/O I/O I/O DS12024 Rev 4 I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 99 STM32L4S9xx FT_fl FT_f FT_fl u FT_fl u FT_u FT_u Notes 66 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - TRACED0, TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3, I2C3_SDA, TSC_G4_IO4, OTG_FS_NOE, SDMMC1_D1, SAI2_EXTCLK, EVENTOUT - - MCO, TIM1_CH1, SAI1_CK2, USART1_CK, OTG_FS_SOF, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT - - TIM1_CH2, SPI2_SCK, DCMI_D0, USART1_TX, SAI1_FS_A, TIM15_BKIN, EVENTOUT OTG_FS_VBU S - TIM1_CH3, SAI1_D1, DCMI_D1, USART1_RX, OTG_FS_ID, SAI1_SD_A, TIM17_BKIN, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS_NSS, CAN1_RX, OTG_FS_DM, EVENTOUT - - TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, OTG_FS_DP, EVENTOUT - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) I/O FT (4) JTMS/SWDIO, IR_OUT, OTG_FS_NOE, SAI1_SD_B, EVENTOUT VDDUS B S - - - - C12 VSS S - - - - C13 VDD S - - - - - 74 107 B10 B3 73 C11 106 B2 E12 75 108 C11 B2 D12 74 F11 107 A1 C12 76 109 A12 A1 75 G11 108 B1 C13 77 110 A11 B1 UFBGA144 A11 LQFP144 B3 LQFP100 105 UFBGA169 A11 LQFP144 72 UBGA132 UFBGA169 Alternate functions WLCSP144 Notes Pin name (functio n after reset) I/O structure STM32L4S9xx PA13 A11 (JTMS/S WDIO) LQFP100 WLCSP144 STM32L4S5xx STM32L4S7xx Pin type Pin Number Additional functions - - - - - E11 - - - - - PH6 I/O FT - I2C2_SMBA, OCTOSPIM_P2_CL K, DCMI_D8, EVENTOUT - - - - D12 - - - - - PH7 I/O FT_f - I2C3_SCL, DCMI_D9, EVENTOUT - - - - - D11 - - - - C11 PH9 I/O FT - I2C3_SMBA, OCTOSPIM_P2_IO4 , DCMI_D0, EVENTOUT - - - - - - B13 - - - - B13 PH12 I/O FT - TIM5_CH3, OCTOSPIM_P2_IO7 , DCMI_D3, EVENTOUT - - - - A13 - - - - A13 PH14 I/O FT - TIM8_CH2N, DCMI_D4, EVENTOUT - - - - - B12 - - - - B12 PH15 I/O FT - TIM8_CH3N, OCTOSPIM_P2_IO6 , DCMI_D11, EVENTOUT - - - - - - A12 - - - - A12 PI0 I/O FT - TIM5_CH4, OCTOSPIM_P1_IO5 , SPI2_NSS, DCMI_D13, EVENTOUT - - - - C11 - - - - - PI8 I/O FT - OCTOSPIM_P2_NC S, DCMI_D12, EVENTOUT - - - - - B11 - - - - B11 PI1 I/O FT - SPI2_SCK, DCMI_D8, EVENTOUT - DS12024 Rev 4 87/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) UFBGA169 LQFP100 LQFP144 - B10 - - - - B10 Pin name (functio n after reset) PI2 I/O Notes WLCSP144 - UFBGA169 LQFP144 - WLCSP144 UBGA132 - UFBGA144 LQFP100 STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions FT - TIM8_CH4, SPI2_MISO, DCMI_D9, EVENTOUT - - - - - - C10 - - - - C10 PI3 I/O FT - TIM8_ETR, SPI2_MOSI, DCMI_D10, EVENTOUT - - - - D10 - - - - D10 PI4 I/O FT - TIM8_BKIN, DCMI_D5, EVENTOUT - - - - - E10 - - - - E10 PI5 I/O FT - TIM8_CH1, OCTOSPIM_P2_NC S, DCMI_VSYNC, EVENTOUT - - - - - C9 - - - - C9 PH13 I/O FT - TIM8_CH1N, CAN1_TX, EVENTOUT - - TIM8_CH2, OCTOSPIM_P2_CL K, DCMI_D6, EVENTOUT - (4) JTCK/SWCLK, LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SAI1_FS_B, EVENTOUT - (4) JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, SAI2_FS_B, EVENTOUT - - 76 77 - - A10 109 A9 88/273 110 - A2 A3 B9 A10 A9 - 78 - 111 79 112 - A10 B9 - A2 A3 B9 PI6 PA14 A10 (JTCK/S WCLK) A9 PA15 (JTDI) I/O I/O I/O DS12024 Rev 4 FT FT FT STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) 79 80 81 82 83 B11 C10 112 B10 C9 B9 C8 113 114 115 116 C3 C4 B4 A4 C5 B5 D9 E9 F8 B8 C8 D8 80 113 81 114 82 115 83 116 84 117 85 118 C9 A9 D9 C8 B8 D8 C3 C4 B4 A4 C5 B5 D9 E9 F8 B8 C8 D8 Pin name (functio n after reset) PC10 PC11 PC12 PD0 PD1 PD2 I/O I/O I/O I/O I/O I/O DS12024 Rev 4 I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 111 STM32L4S9xx FT FT FT FT FT FT Notes 78 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, DCMI_D8, SDMMC1_D2, SAI2_SCK_B, EVENTOUT - - DCMI_D2, OCTOSPIM_P1_NC S, SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, DCMI_D4, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT - - TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9, SDMMC1_CK, SAI2_SD_B, EVENTOUT - - SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, LCD_B4, FMC_D2, EVENTOUT - - SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, LCD_B5, FMC_D3, EVENTOUT - - TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11, SDMMC1_CMD, EVENTOUT - 89/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) 85 B8 B7 118 D6 C6 E8 C7 86 119 87 120 86 A6 119 A5 D7 - - 120 B6 M3 - - - 121 A6 A8 - 87 88 - B6 A5 D9 90/273 122 123 124 E7 D7 C7 E7 F7 B7 A8 C7 C6 E8 C7 PD3 PD4 I/O I/O I/O structure UFBGA169 WLCSP144 D6 Pin name (functio n after reset) FT FT Alternate functions Additional functions - SPI2_SCK, DCMI_D5, SPI2_MISO, DFSDM1_DATIN0, USART2_CTS_NSS, OCTOSPIM_P2_NC S, LCD_CLK, FMC_CLK, EVENTOUT - - SPI2_MOSI, DFSDM1_CKIN0, USART2_RTS_DE, OCTOSPIM_P1_IO4 , FMC_NOE, EVENTOUT - - D7 A5 D7 PD5 I/O FT - USART2_TX, OCTOSPIM_P1_IO5 , FMC_NWE, EVENTOUT 122 - B6 M3 VSS S - - - - 123 - A6 A8 VDD S - - - - - SAI1_D1, DCMI_D10, SPI3_MOSI, DFSDM1_DATIN1, USART2_RX, OCTOSPIM_P1_IO6 , LCD_DE, FMC_NWAIT, SAI1_SD_A, EVENTOUT - - DFSDM1_CKIN1, USART2_CK, OCTOSPIM_P1_IO7 , FMC_NCE/FMC_NE 1, EVENTOUT - - OCTOSPIM_P2_IO6 , SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE 2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - 88 121 89 124 90 125 - UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 117 STM32L4S9xx Notes 84 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number 126 B7 E7 F6 E7 D7 C7 E7 F7 B7 PD6 PD7 PG9 I/O I/O I/O DS12024 Rev 4 FT FT FT_s STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) - - D8 G3 D7 126 127 B7 - A7 D6 E6 F6 - - - 127 128 129 E6 - D6 B7 - A7 D6 E6 F6 Pin name (functio n after reset) PG10 PG11 PG12 I/O I/O I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 125 STM32L4S9xx FT_s FT_s Notes - UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions - LPTIM1_IN1, OCTOSPIM_P2_IO7 , SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - - LPTIM1_IN2, OCTOSPIM_P1_IO5 , SPI3_MOSI, USART1_CTS_NSS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT - - LPTIM1_ETR, OCTOSPIM_P2_NC S, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT - - I/O FT_s - I2C1_SDA, USART1_CK, LCD_R0, FMC_A24, EVENTOUT - C7 128 D8 G7 - - C6 D8 G6 PG13 I/O FT_f s - C6 129 - G6 - - - - - PG14 I/O FT_f s - I2C1_SCL, LCD_R1, FMC_A25, EVENTOUT - - F7 130 - - - 130 A7 - - VSS S - - - - - G7 131 A8 B6 - 131 A6 A8 B6 VDDIO2 S - - - - - LPTIM1_OUT, I2C1_SMBA, OCTOSPIM_P2_DQ S, DCMI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, OTG_FS_CRS_SYN C, SAI1_SCK_B, EVENTOUT COMP2_INM - 89 K1 A8 132 133 - B8 C6 A6 - 132 91 133 - B6 - B8 C6 A6 PG15 PB3 (JTDO/T RACES WO) I/O I/O DS12024 Rev 4 FT_s FT_l a 91/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) 91 92 A7 C5 B5 92/273 135 136 C8 E8 C9 A5 B5 C5 92 134 93 135 94 136 A5 B5 D5 C8 E8 C9 A5 B5 C5 Pin name (functio n after reset) PB4 (NJTRST) PB5 PB6 I/O I/O I/O DS12024 Rev 4 I/O structure UFBGA169 WLCSP144 UFBGA144 LQFP144 LQFP100 UFBGA169 WLCSP144 LQFP144 134 STM32L4S9xx FT_f a FT_l a FT_f a Notes 90 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Alternate functions Additional functions (4) NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS_NSS, UART5_RTS_DE, TSC_G2_IO1, DCMI_D12, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT COMP2_INP - LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, DCMI_D10, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT - - LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, I2C4_SCL, DFSDM1_DATIN5, USART1_TX, TSC_G2_IO3, DCMI_D5, SAI1_FS_B, TIM16_CH1N, EVENTOUT COMP2_INP STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description Table 15. STM32L4Sxxx pin definitions (continued) Pin name (functio n after reset) D5 PB7 I/O FT_fl a - 94 A4 138 B9 E5 96 138 A4 B9 E5 PH3BOOT0 I/O FT - EVENTOUT - - TIM4_CH3, SAI1_CK1, I2C1_SCL, DFSDM1_CKOUT, DFSDM1_DATIN6, SDMMC1_CKIN, CAN1_RX, DCMI_D6, LCD_B1, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT - - IR_OUT, TIM4_CH4, SAI1_D2, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, SDMMC1_CDIR, CAN1_TX, DCMI_D7, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT - - TIM4_ETR, DCMI_D2, LCD_HSYNC, FMC_NBL0, TIM16_CH1, EVENTOUT - 95 96 97 A3 B3 C3 139 C10 140 B10 141 A10 C4 D4 A4 97 139 98 140 - 141 B4 A3 A2 C10 B10 A10 UFBGA169 A9 WLCSP144 C5 UFBGA144 95 137 LQFP144 D5 LQFP100 A9 UFBGA169 137 WLCSP144 B4 LQFP144 93 LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, I2C4_SDA, DFSDM1_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, DCMI_VSYNC, DSI_TE, FMC_NL, TIM17_CH1N, EVENTOUT UBGA132 Alternate functions LQFP100 Notes STM32L4S9xx I/O structure STM32L4S5xx STM32L4S7xx Pin type Pin Number C4 D4 A4 PB8 PB9 PE0 I/O I/O I/O DS12024 Rev 4 FT_fl FT_fl FT Additional functions COMP2_INM, PVD_IN 93/273 113 Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 15. STM32L4Sxxx pin definitions (continued) B4 PE1 I/O FT - B3 99 143 A1 A12 B3 VSS S - - - - A3 10 144 0 B2 B12 A3 VDD S - - - - - - - A2 PH2 I/O FT - OCTOSPIM_P1_IO4 , EVENTOUT - - - - - B2 PI7 I/O FT - TIM8_CH3, DCMI_D7, EVENTOUT - B1 - - - - B1 PI9 I/O FT - OCTOSPIM_P2_IO2 , CAN1_RX, EVENTOUT - A1 - - - - A1 PI10 I/O FT - OCTOSPIM_P2_IO1 , EVENTOUT - 142 A11 B4 - 99 D3 143 A12 100 C4 144 B12 - - - - A2 - - - - - B2 - - - - - - - - UFBGA169 A11 A2 WLCSP144 C4 98 UFBGA144 142 DCMI_D3, LCD_VSYNC, FMC_NBL1, TIM17_CH1, EVENTOUT LQFP144 Alternate functions LQFP100 Notes Pin name (functio n after reset) I/O structure STM32L4S9xx UFBGA169 WLCSP144 LQFP144 UBGA132 LQFP100 STM32L4S5xx STM32L4S7xx Pin type Pin Number Additional functions - 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (for example to drive a LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0432 reference manual. 3. NC (not-connected) balls must be left unconnected. However, PF8 and PF9 NC' IOs are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low-power modes. 4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. 94/273 DS12024 Rev 4 AF0 Port DS12024 Rev 4 Port A AF1 OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS_NSS PA1 - TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK - USART2_RTS_DE PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 SAI1_CK1 - - - USART2_RX PA4 - - - OCTOSPIM_P1_NC S - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN DCMI_PIXCLK SPI1_MISO - USART3_CTS_NSS PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - - PA8 MCO TIM1_CH1 - SAI1_CK2 - - - USART1_CK PA9 - TIM1_CH2 - SPI2_SCK - DCMI_D0 - USART1_TX PA10 - TIM1_CH3 - SAI1_D1 - DCMI_D1 - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS_NSS PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_DE PA13 JTMS/SW DIO IR_OUT - - - - - - PA14 JTCK/SW CLK LPTIM1_OUT - - I2C1_SMBA I2C4_SMBA - - PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_DE Pinouts and pin description 95/273 PA0 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 16. Alternate function AF0 to AF7(1) AF0 Port OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - SPI1_NSS - USART3_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_DATIN0 USART3_RTS_DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 - PB3 JTDO/TRA CESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_DE PB4 NJTRST - TIM3_CH1 - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS_NSS PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL DFSDM1_DATIN5 USART1_TX PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA DFSDM1_CKIN5 USART1_RX PB8 - - TIM4_CH3 SAI1_CK1 I2C1_SCL DFSDM1_CKOUT DFSDM1_DATIN6 - PB9 - IR_OUT TIM4_CH4 SAI1_D2 I2C1_SDA SPI2_NSS DFSDM1_CKIN6 - PB10 - TIM2_CH3 - I2C4_SCL I2C2_SCL SPI2_SCK DFSDM1_DATIN7 USART3_TX PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - DFSDM1_CKIN7 USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN I2C2_SMBA SPI2_NSS DFSDM1_DATIN1 USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS_NSS PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM1_DATIN2 USART3_RTS_DE PB15 RTC_ REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx DS12024 Rev 4 Port B AF1 Pinouts and pin description 96/273 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port DS12024 Rev 4 Port C AF1 OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 - LPTIM1_IN1 - - I2C3_SCL - DFSDM1_DATIN4 - PC1 TRACED0 LPTIM1_OUT - SPI2_MOSI I2C3_SDA - DFSDM1_CKIN4 - PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_CKOUT - PC3 - LPTIM1_ETR - SAI1_D1 - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - SAI1_D3 - - - USART3_RX PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 - PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM1_DATIN3 - PC8 - - TIM3_CH3 TIM8_CH3 - - - - PC9 TRACED0 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 DCMI_D3 - I2C3_SDA - PC10 TRACED1 - - - - - SPI3_SCK USART3_TX PC11 - - - DCMI_D2 OCTOSPIM_P1_NCS SPI3_MISO USART3_RX PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - - 97/273 Pinouts and pin description PC0 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 PD0 - - - - - SPI2_NSS DFSDM1_DATIN7 - PD1 - - - - - SPI2_SCK DFSDM1_CKIN7 - PD2 TRACED2 - TIM3_ETR - - - - USART3_RTS_DE PD3 - - - SPI2_SCK DCMI_D5 SPI2_MISO DFSDM1_DATIN0 USART2_CTS_NSS PD4 - - - - - SPI2_MOSI DFSDM1_CKIN0 USART2_RTS_DE PD5 - - - - - - - USART2_TX PD6 - - - SAI1_D1 DCMI_D10 SPI3_MOSI DFSDM1_DATIN1 USART2_RX PD7 - - - - - - DFSDM1_CKIN1 USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - I2C4_SMBA - - USART3_CTS_NSS PD12 - - TIM4_CH1 - I2C4_SCL - - USART3_RTS_DE PD13 - - TIM4_CH2 - I2C4_SDA - - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx DS12024 Rev 4 Port D AF1 Pinouts and pin description 98/273 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port DS12024 Rev 4 Port E AF1 OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 - - TIM4_ETR - - - - - PE1 - - - - - - - - PE2 TRACECK - TIM3_ETR SAI1_CK1 - - - - PE3 TRACED0 - TIM3_CH1 OCTOSPIM_P1_DQ S - - - - PE4 TRACED1 - TIM3_CH2 SAI1_D2 - - DFSDM1_DATIN3 - PE5 TRACED2 - TIM3_CH3 SAI1_CK2 - - DFSDM1_CKIN3 - PE6 TRACED3 - TIM3_CH4 SAI1_D1 - - - - PE7 - TIM1_ETR - - - - DFSDM1_DATIN2 - PE8 - TIM1_CH1N - - - - DFSDM1_CKIN2 - PE9 - TIM1_CH1 - - - - DFSDM1_CKOUT - PE10 - TIM1_CH2N - - - - DFSDM1_DATIN4 - PE11 - TIM1_CH2 - - - - DFSDM1_CKIN4 - PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM1_DATIN5 - PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN - SPI1_MOSI - - 99/273 Pinouts and pin description PE0 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 PF0 - - - - I2C2_SDA OCTOSPIM_P2_IO0 - - PF1 - - - - I2C2_SCL OCTOSPIM_P2_IO1 - - PF2 - - - - I2C2_SMBA OCTOSPIM_P2_IO2 - - PF3 - - - - - OCTOSPIM_P2_IO3 - - PF4 - - - - - OCTOSPIM_P2_CLK - - PF5 - - - - - - - - PF6 - TIM5_ETR TIM5_CH1 - - - - - PF7 - - TIM5_CH2 - - - - - PF8 - - TIM5_CH3 - - - - - PF9 - - TIM5_CH4 - - - - - PF10 - - - OCTOSPIM_P1_CLK - - DFSDM1_CKOUT - PF11 - - - - - - - - PF12 - - - - - OCTOSPIM_P2_DQS - - PF13 - - - - I2C4_SMBA - DFSDM1_DATIN6 - PF14 - - - - I2C4_SCL - DFSDM1_CKIN6 - PF15 - - - - I2C4_SDA - - - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx DS12024 Rev 4 Port F AF1 Pinouts and pin description 100/273 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port DS12024 Rev 4 Port G AF1 OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 - - - - - OCTOSPIM_P2_IO4 - - PG1 - - - - - OCTOSPIM_P2_IO5 - - PG2 - - - - - SPI1_SCK - - PG3 - - - - - SPI1_MISO - - PG4 - - - - - SPI1_MOSI - - PG5 - - - - - SPI1_NSS - - PG6 - - - OCTOSPIM_P1_DQ S I2C3_SMBA - - - PG7 - - - SAI1_CK1 I2C3_SCL PG8 - - - - I2C3_SDA - - - PG9 - - - - - OCTOSPIM_P2_IO6 SPI3_SCK USART1_TX PG10 - LPTIM1_IN1 - - - OCTOSPIM_P2_IO7 SPI3_MISO USART1_RX PG11 - LPTIM1_IN2 - OCTOSPIM_P1_IO5 - - SPI3_MOSI USART1_CTS_NSS PG12 - LPTIM1_ETR - - - OCTOSPIM_P2_NCS SPI3_NSS USART1_RTS_DE PG13 - - - - I2C1_SDA - - USART1_CK PG14 - - - - I2C1_SCL - - - PG15 - LPTIM1_OUT - - I2C1_SMBA OCTOSPIM_P2_DQS - - OCTOSPIM_P2_DQS DFSDM1_CKOUT - 101/273 Pinouts and pin description PG0 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 PH0 - - - - - - - - PH1 - - - - - - - - PH2 - - - OCTOSPIM_P1_IO4 - - - - PH3 - - - - - - - - PH4 - - - - I2C2_SCL OCTOSPIM_P2_DQS - - PH5 - - - - I2C2_SDA - - - PH6 - - - - I2C2_SMBA OCTOSPIM_P2_CLK - - PH7 - - - - I2C3_SCL - - - PH8 - - - - I2C3_SDA OCTOSPIM_P2_IO3 - - PH9 - - - - I2C3_SMBA OCTOSPIM_P2_IO4 - - PH10 - - TIM5_CH1 - - OCTOSPIM_P2_IO5 - - PH11 - - TIM5_CH2 - - OCTOSPIM_P2_IO6 - - PH12 - - TIM5_CH3 - - OCTOSPIM_P2_IO7 - - PH13 - - - TIM8_CH1N - - - - PH14 - - - TIM8_CH2N - - - - PH15 - - - TIM8_CH3N - OCTOSPIM_P2_IO6 - - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx DS12024 Rev 4 Port H AF1 Pinouts and pin description 102/273 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 Port DS12024 Rev 4 Port I AF1 OTG_FS/ TIM1/2/5/8/L SYS_AF PTIM1 AF2 TIM1/2/3/4/ 5 AF3 AF4 AF5 AF6 SPI2/SAI1/I2C4/U SPI1/2/3/I2C4/DFS SPI3/I2C3/DFS SART2/OTG_FS/T I2C1/2/3/4/DC DM1/DCMI/OCTOS DM1/COMP1/O IM1/8/OCTOSPIM MI PIM_P1/2 CTOSPIM_P2 _P1 AF7 USART1/2/3 PI0 - - TIM5_CH4 OCTOSPIM_P1_IO5 - SPI2_NSS - - PI1 - - - - - SPI2_SCK - - PI2 - - - TIM8_CH4 - SPI2_MISO - - PI3 - - - TIM8_ETR - SPI2_MOSI - - PI4 - - - TIM8_BKIN - - - - PI5 - - - TIM8_CH1 - OCTOSPIM_P2_NCS - - PI6 - - - TIM8_CH2 - OCTOSPIM_P2_CLK - - PI7 - - - TIM8_CH3 - - - - PI8 - - - - - OCTOSPIM_P2_NCS - - PI9 - - - - - OCTOSPIM_P2_IO2 - - PI10 - - - - - OCTOSPIM_P2_IO1 - - PI11 - - - - - OCTOSPIM_P2_IO0 - - STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 16. Alternate function AF0 to AF7(1) (continued) 1. Refer to Table 17 for AF8 to AF15. Pinouts and pin description 103/273 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT PA1 UART4_RX - OCTOSPIM_P1_DQS - - - TIM15_CH1N EVENTOUT PA2 LPUART1_TX - OCTOSPIM_P1_NCS - - SAI2_EXTCLK TIM15_CH1 EVENTOUT PA3 LPUART1_RX - OCTOSPIM_P1_CLK - - SAI1_MCLK_A TIM15_CH2 EVENTOUT PA4 - - DCMI_HSYNC - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 LPUART1_CT S - OCTOSPIM_P1_IO3 - TIM1_BKIN TIM8_BKIN TIM16_CH1 EVENTOUT PA7 - - OCTOSPIM_P1_IO2 - - - TIM17_CH1 EVENTOUT PA8 - - OTG_FS_SOF - - SAI1_SCK_A LPTIM2_OUT EVENTOUT PA9 - - - - - SAI1_FS_A TIM15_BKIN EVENTOUT PA10 - - OTG_FS_ID - - SAI1_SD_A TIM17_BKIN EVENTOUT PA11 - CAN1_RX OTG_FS_DM - TIM1_BKIN2 - - EVENTOUT PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT PA13 - - OTG_FS_NOE - - SAI1_SD_B - EVENTOUT PA14 - - OTG_FS_SOF - - SAI1_FS_B - EVENTOUT - - - SAI2_FS_B - EVENTOUT Port DS12024 Rev 4 Port A PA15 UART4_RTS_ TSC_G3_IO1 DE STM32L4S5xx, STM32L4S7xx and STM32L4S9xx AF8 Pinouts and pin description 104/273 Table 17. Alternate function AF8 to AF15(1) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PB0 - - OCTOSPIM_P1_IO1 - COMP1_OUT SAI1_EXTCLK - EVENTOUT PB1 LPUART1_ RTS_DE - OCTOSPIM_P1_IO0 - - - LPTIM2_IN1 EVENTOUT PB2 - - OCTOSPIM_P1_DQS LCD_B1 - - - EVENTOUT PB3 - - OTG_FS_CRS_SYNC - - SAI1_SCK_B - EVENTOUT Port DS12024 Rev 4 Port B UART5_RTS_ TSC_G2_IO1 DE DCMI_D12 - - SAI1_MCLK_B TIM17_BKIN EVENTOUT PB5 UART5_CTS TSC_G2_IO2 DCMI_D10 - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 - TSC_G2_IO3 DCMI_D5 - TIM8_BKIN2 SAI1_FS_B TIM16_CH1N EVENTOUT PB7 UART4_CTS TSC_G2_IO4 DCMI_VSYNC DSI_TE FMC_NL TIM8_BKIN TIM17_CH1N EVENTOUT PB8 SDMMC1_ CKIN CAN1_RX DCMI_D6 LCD_B1 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT PB9 SDMMC1_ CDIR CAN1_TX DCMI_D7 - SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT PB10 LPUART1_RX TSC_SYNC OCTOSPIM_P1_CLK - COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - OCTOSPIM_P1_NCS DSI_TE COMP2_OUT - - EVENTOUT PB12 LPUART1_RT TSC_G1_IO1 S_DE - - - SAI2_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_CT TSC_G1_IO2 S - - - SAI2_SCK_A TIM15_CH1N EVENTOUT 105/273 PB14 - TSC_G1_IO3 - - - SAI2_MCLK_A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - - - SAI2_SD_A TIM15_CH2 EVENTOUT Pinouts and pin description PB4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PC0 LPUART1_RX - - - - SAI2_FS_A LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - OCTOSPIM_P1_IO4 - - SAI1_SD_A - EVENTOUT PC2 - - OCTOSPIM_P1_IO5 - - - - EVENTOUT PC3 - - OCTOSPIM_P1_IO6 - - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - OCTOSPIM_P1_IO7 - - - - EVENTOUT PC5 - - - - - - - EVENTOUT PC6 SDMMC1_ D0DIR TSC_G4_IO1 DCMI_D0 LCD_R0 SDMMC1_D6 SAI2_MCLK_A - EVENTOUT PC7 SDMMC1_ D123DIR TSC_G4_IO2 DCMI_D1 LCD_R1 SDMMC1_D7 SAI2_MCLK_B - EVENTOUT PC8 - TSC_G4_IO3 DCMI_D2 - SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 OTG_FS_NOE - SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2 EVENTOUT PC10 UART4_TX TSC_G3_IO2 DCMI_D8 - SDMMC1_D2 SAI2_SCK_B - EVENTOUT PC11 UART4_RX TSC_G3_IO3 DCMI_D4 - SDMMC1_D3 SAI2_MCLK_B - EVENTOUT PC12 UART5_TX TSC_G3_IO4 DCMI_D9 - SDMMC1_CK SAI2_SD_B - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port DS12024 Rev 4 Port C STM32L4S5xx, STM32L4S7xx and STM32L4S9xx AF8 Pinouts and pin description 106/273 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PD0 - CAN1_RX - LCD_B4 FMC_D2 - - EVENTOUT PD1 - CAN1_TX - LCD_B5 FMC_D3 - - EVENTOUT PD2 UART5_RX TSC_SYNC DCMI_D11 - SDMMC1_CM D - - EVENTOUT PD3 - - OCTOSPIM_P2_NCS LCD_CLK FMC_CLK - - EVENTOUT PD4 - - OCTOSPIM_P1_IO4 - FMC_NOE - - EVENTOUT PD5 - - OCTOSPIM_P1_IO5 - FMC_NWE - - EVENTOUT PD6 - - OCTOSPIM_P1_IO6 LCD_DE FMC_NWAIT SAI1_SD_A - EVENTOUT PD7 - - OCTOSPIM_P1_IO7 - FMC_NCE/FM C_NE1 - - EVENTOUT PD8 - - DCMI_HSYNC LCD_R3 FMC_D13 - - EVENTOUT PD9 - - DCMI_PIXCLK LCD_R4 FMC_D14 SAI2_MCLK_A - EVENTOUT PD10 - TSC_G6_IO1 - LCD_R5 FMC_D15 SAI2_SCK_A - EVENTOUT PD11 - TSC_G6_IO2 - LCD_R6 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - LCD_R7 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - - FMC_A18 - LPTIM2_OUT EVENTOUT PD14 - - - LCD_B2 FMC_D0 - - EVENTOUT PD15 - - - LCD_B3 FMC_D1 - - EVENTOUT Port DS12024 Rev 4 Port D 107/273 Pinouts and pin description AF8 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PE0 - - DCMI_D2 LCD_HSYNC FMC_NBL0 - TIM16_CH1 EVENTOUT PE1 - - DCMI_D3 LCD_VSYNC FMC_NBL1 - TIM17_CH1 EVENTOUT PE2 - TSC_G7_IO1 - LCD_R0 FMC_A23 SAI1_MCLK_A - EVENTOUT PE3 - TSC_G7_IO2 - LCD_R1 FMC_A19 SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 DCMI_D4 LCD_B0 FMC_A20 SAI1_FS_A - EVENTOUT PE5 - TSC_G7_IO4 DCMI_D6 LCD_G0 FMC_A21 SAI1_SCK_A - EVENTOUT PE6 - - DCMI_D7 LCD_G1 FMC_A22 SAI1_SD_A - EVENTOUT PE7 - - - LCD_B6 FMC_D4 SAI1_SD_B - EVENTOUT PE8 - - - LCD_B7 FMC_D5 SAI1_SCK_B - EVENTOUT PE9 - - - LCD_G2 FMC_D6 SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 OCTOSPIM_P1_CLK LCD_G3 FMC_D7 SAI1_MCLK_B - EVENTOUT PE11 - TSC_G5_IO2 OCTOSPIM_P1_NCS LCD_G4 FMC_D8 - - EVENTOUT PE12 - TSC_G5_IO3 OCTOSPIM_1_IO0 LCD_G5 FMC_D9 - - EVENTOUT PE13 - TSC_G5_IO4 OCTOSPIM_P1_IO1 LCD_G6 FMC_D10 - - EVENTOUT PE14 - - OCTOSPIM_P1_IO2 LCD_G7 FMC_D11 - - EVENTOUT PE15 - - OCTOSPIM_P1_IO3 LCD_R2 FMC_D12 - - EVENTOUT Port DS12024 Rev 4 Port E STM32L4S5xx, STM32L4S7xx and STM32L4S9xx AF8 Pinouts and pin description 108/273 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PF0 - - - - FMC_A0 - - EVENTOUT PF1 - - - - FMC_A1 - - EVENTOUT PF2 - - - - FMC_A2 - - EVENTOUT PF3 - - - - FMC_A3 - - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - - EVENTOUT PF6 - - OCTOSPIM_P1_IO3 - - SAI1_SD_B - EVENTOUT PF7 - - OCTOSPIM_P1_IO2 - - SAI1_MCLK_B - EVENTOUT PF8 - - OCTOSPIM_P1_IO0 - - SAI1_SCK_B - EVENTOUT PF9 - - OCTOSPIM_P1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT PF10 - - DCMI_D11 - - SAI1_D3 TIM15_CH2 EVENTOUT PF11 - LCD_DE DCMI_D12 DSI_TE - - - EVENTOUT PF12 - - - LCD_B0 FMC_A6 - - EVENTOUT PF13 - - - LCD_B1 FMC_A7 - - EVENTOUT PF14 - TSC_G8_IO1 - LCD_G0 FMC_A8 - - EVENTOUT PF15 - TSC_G8_IO2 - LCD_G1 FMC_A9 - - EVENTOUT Port DS12024 Rev 4 Port F 109/273 Pinouts and pin description AF8 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT PG5 LPUART1_CT S - - - FMC_A15 SAI2_SD_B - EVENTOUT PG6 LPUART1_RT S_DE LCD_R1 - DSI_TE - - - EVENTOUT PG7 LPUART1_TX - - - FMC_INT SAI1_MCLK_A - EVENTOUT PG8 LPUART1_RX - - - - - - EVENTOUT PG9 - - - - FMC_NCE/FM C_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT PG13 - - - LCD_R0 FMC_A24 - - EVENTOUT PG14 - - - LCD_R1 FMC_A25 - - EVENTOUT PG15 - - DCMI_D13 - - - - EVENTOUT Port DS12024 Rev 4 Port G STM32L4S5xx, STM32L4S7xx and STM32L4S9xx AF8 Pinouts and pin description 110/273 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH2 - - - - - - - EVENTOUT PH3 - - - - - - - EVENTOUT PH4 - - - - - - - EVENTOUT PH5 - - DCMI_PIXCLK - - - - EVENTOUT PH6 - - DCMI_D8 - - - - EVENTOUT PH7 - - DCMI_D9 - - - - EVENTOUT PH8 - - DCMI_HSYNC - - - - EVENTOUT PH9 - - DCMI_D0 - - - - EVENTOUT PH10 - - DCMI_D1 - - - - EVENTOUT PH11 - - DCMI_D2 - - - - EVENTOUT PH12 - - DCMI_D3 - - - - EVENTOUT PH13 - CAN1_TX - - - - - EVENTOUT PH14 - - DCMI_D4 - - - - EVENTOUT PH15 - - DCMI_D11 - - - - EVENTOUT Port DS12024 Rev 4 Port H 111/273 Pinouts and pin description AF8 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC OTG_FS/DCMI/ OCTOSPI_P1/P2 LCD SDMMC/ COMP1/2/ FMC SAI1/2 TIM2/15/16/17/ LPTIM2 EVENOUT PI0 - - DCMI_D13 - - - - EVENTOUT PI1 - - DCMI_D8 - - - - EVENTOUT PI2 - - DCMI_D9 - - - - EVENTOUT PI3 - - DCMI_D10 - - - - EVENTOUT PI4 - - DCMI_D5 - - - - EVENTOUT PI5 - - DCMI_VSYNC - - - - EVENTOUT PI6 - - DCMI_D6 - - - - EVENTOUT PI7 - - DCMI_D7 - - - - EVENTOUT PI8 - - DCMI_D12 - - - - EVENTOUT PI9 - CAN1_RX - - - - - EVENTOUT PI10 - - - - - - - EVENTOUT PI11 - - - - - - - EVENTOUT Port Port I DS12024 Rev 4 1. Refer to Table 16 for AF0 to AF7. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx AF8 Pinouts and pin description 112/273 Table 17. Alternate function AF8 to AF15(1) (continued) STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 5 Memory mapping Memory mapping For memory map and peripheral register boundary addresses refer to the corresponding section of reference manual RM0432. DS12024 Rev 4 113/273 113 Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 18. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 19. Figure 18. Pin loading conditions Figure 19. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 114/273 DS12024 Rev 4 MS19211V1 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 6.1.6 Electrical characteristics Power supply scheme Figure 20. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch VDD VCORE n x VDD Regulator n x 100 nF GPIOs IN +1 x 4.7 μF Level shifter OUT IO logic Level shifter VDDIO1 IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDIO2 m x VDDIO2 VDDIO2 OUT m x100 nF +4.7 μF GPIOs IN m x VSS VDD VDDDSI DSI Voltage regulator VCAPDSI VDD12DSI DSI PHY 2.2 uF VDDA VDDA VREF 10 nF +1 μF 100 nF +1 μF VREF+ VREF- ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF VSSA MSv47745V1 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS12024 Rev 4 115/273 248 Electrical characteristics 6.1.7 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Current consumption measurement Figure 21. Current consumption measurement IDD_USB IDD_VBAT IDD VDDUSB VBAT VDD VDDIO2 IDDA VDDA MSv47746V1 The IDD_ALL parameters given in Table 25 to Table 32 represent the total MCU consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB and VBAT. 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 18. Voltage characteristics(1) Symbol Ratings Min Max VDDX - VSS External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VBAT, VREF+) -0.3 4.0 Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDIO2, VDDUSB) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 VSS-0.3 4.0 VIN(2) Input voltage on any other pins 116/273 DS12024 Rev 4 Unit V STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics Table 18. Voltage characteristics(1) (continued) Symbol Ratings Min Max |∆VDDx| Variations between different VDDX power pins of the same domain - 50 Variations between all the different ground pins(5) - 50 - 0.4 |VSSx-VSS| VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA Unit mV V 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 19. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 200 ∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200 IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100 IVSS(PIN) (sink)(1) 100 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(3) ∑|IINJ(PIN)| Maximum current out of each VSS ground pin Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(2) Unit mA 100 (2) Total output current sourced by sum of all I/Os and control pins 100 Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(4) Injected current on PA4, PA5 -5/0 (5) Total injected current (sum of all I/Os and control pins) 25 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the minimum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). DS12024 Rev 4 117/273 248 Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Table 20. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 120 fPCLK1 Internal APB1 clock frequency - 0 120 fPCLK2 Internal APB2 clock frequency - 0 120 VDD Standard operating voltage - VDDIO2 VDDA VBAT At least one I/O in PG[15:2] used PG[15:2] I/Os supply voltage PG[15:2] not used Analog supply voltage 1.08 3.6 0 3.6 DAC or OPAMP used 1.8 VREFBUF used 2.4 3.6 ADC, DAC, OPAMP, COMP, VREFBUF not used 0 - 1.55 3.6 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3 0 9 -0.3 MIN(MIN(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V, 5.5 V)(2)(3) USB used USB not used BOOT0 118/273 3.6 1.62 TT_xx I/O VIN (1) ADC or COMP used Backup operating voltage VDDUSB USB supply voltage 1.71 I/O input voltage All I/O except BOOT0 and TT_xx DS12024 Rev 4 Unit MHz V V STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics Table 21. General operating conditions (continued) Symbol PD PD Parameter Power dissipation at TA = 85 °C for suffix 6(4) Power dissipation at TA = 125 °C for suffix 3(4) Min Max LQFP144 - - 625 LQFP100 - - 476 UFBGA169 - - 385 UFBGA132 - - 364 WLCSP144 - - 664 LQFP144 - - 156 LQFP100 - - 119 UFBGA169 - - 96 UFBGA132 - - 91 WLCSP144 - - 831 –40 85 –40 105 Ambient temperature for the suffix 6 version Maximum power dissipation Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(5) –40 130 Suffix 6 version –40 105 Suffix 3 version –40 130 TA TJ Conditions Junction temperature range Low-power dissipation(5) Unit mW mW °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2, VDDUSB)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). DS12024 Rev 4 119/273 248 Electrical characteristics 6.3.2 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD VDDA rise time rate VDDUSB rise time rate 0 ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ - VDDUSB fall time rate VDDIO2 rise time rate tVDDIO2 Max - VDDA fall time rate tVDDUSB Min - VDD fall time rate tVDDA 6.3.3 Conditions - VDDIO2 fall time rate Unit µs/V µs/V µs/V µs/V Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions. Table 23. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) 120/273 Parameter Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 VDD rising DS12024 Rev 4 V V V V V V V STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics Table 23. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Symbol Parameter VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Unit V V V V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and IDD (BOR_PVD)(2) PVD consumption from VDD - - 1.1 1.6 µA - 1.18 1.22 1.26 V Vhyst_BOR_PVD VPVM1 VDDUSB peripheral voltage monitoring VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV IDD PVM1 and PVM2 (PVM1/PVM2) consumption from VDD (2) - - 0.2 - µA IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) - - 2 - µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS12024 Rev 4 121/273 248 Electrical characteristics 6.3.4 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol Parameter VREFINT Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ 1.182 1.212 Unit 1.232 V ADC sampling time when reading the internal reference voltage - 4(2) - - µs Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs VREFINT buffer consumption from VDD IDD(VREFINTBUF) when converted by ADC - - 12.5 20(2) µA tS_vrefint (1) tstart_vrefint ∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV TCoeff Average temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C ACoeff Long term stability 1000 hours, T = 25°C - 300 Average voltage coefficient 3.0 V < VDD < 3.6 V - 250 24 25 26 49 50 51 74 75 76 VDDCoeff VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage - 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 122/273 Max DS12024 Rev 4 1000(2 ) 1200(2 ) ppm ppm/V % VREFINT STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics Figure 22. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V2 DS12024 Rev 4 123/273 248 Electrical characteristics 6.3.5 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code The current consumption is measured as described in Figure 21: Current consumption measurement. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0432 reference manual). • When the peripherals are enabled fPCLK = fHCLK • The voltage scaling Range 1 is adjusted to fHCLK frequency as follows: – Voltage Range 1 Boost mode for 80 MHz < fHCLK